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- stm32mp: fix compilation issue with DEBUG_UART

Browse source 
- DT update :
   - Remove buck3 regulator-always-on on AV96
   - Enable btrfs support on DHSOM
   - Drop extra newline from AV96 U-Boot extras DT
   - Add DHCOR based Testbench board
   - Fix and expand PLL configuration comments
   - update SCMI dedicated file
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Merge tag 'u-boot-stm32-20221018' of https://source.denx.de/u-boot/custodians/u-boot-stm

- stm32mp: fix compilation issue with DEBUG_UART
- DT update :
  - Remove buck3 regulator-always-on on AV96
  - Enable btrfs support on DHSOM
  - Drop extra newline from AV96 U-Boot extras DT
  - Add DHCOR based Testbench board
  - Fix and expand PLL configuration comments
  - update SCMI dedicated file
This commit is contained in:
Tom Rini 2022-10-18 07:36:39 -04:00
commit d3031d442b
17 changed files with 398 additions and 78 deletions
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3
arch/arm/dts/Makefile
View file

@ -1205,7 +1205,8 @@ dtb-$(CONFIG_STM32MP15x) += \
stm32mp15xx-dhcom-pdk2.dtb \
stm32mp15xx-dhcom-picoitx.dtb \
stm32mp15xx-dhcor-avenger96.dtb \
stm32mp15xx-dhcor-drc-compact.dtb
stm32mp15xx-dhcor-drc-compact.dtb \
stm32mp15xx-dhcor-testbench.dtb
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-base-board.dtb \

4
arch/arm/dts/stm32mp15-scmi.dtsi
View file

@ -103,7 +103,3 @@
/delete-node/ &clk_lse;
/delete-node/ &clk_lsi;
/delete-node/ &clk_csi;
/delete-node/ &reg11;
/delete-node/ &reg18;
/delete-node/ &usb33;
/delete-node/ &pwr_regulators;

17
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View file

@ -190,6 +190,21 @@
CLK_LPTIM45_LSE
>;
/*
* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
* frac = < f >;
*
* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
* XTAL = 24 MHz
*
* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
* P = VCO / (P + 1)
* Q = VCO / (Q + 1)
* R = VCO / (R + 1)
*/
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
@ -208,7 +223,7 @@
u-boot,dm-pre-reloc;
};
/* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
/* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;

5
arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi
View file

@ -19,7 +19,6 @@
};
};
&ethernet0 {
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
@ -102,6 +101,10 @@
hnp-srp-disable;
};
&vdd {
/delete-property/ regulator-always-on;
};
&vdd_io {
u-boot,dm-spl;
};

100
arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi Normal file
View file

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
#include "stm32mp15xx-dhcor-u-boot.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
usb0 = &usbotg_hs;
};
config {
dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>;
};
};
&ethernet0 {
phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
mdio0 {
ethernet-phy@7 {
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-assert-us = <11000>;
reset-deassert-us = <1000>;
};
};
};
&sdmmc1 {
u-boot,dm-spl;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
st,ckin-gpios = <&gpioe 4 0>;
};
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_b {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2 {
u-boot,dm-spl;
};
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_c {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&uart4_pins_b {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
/delete-property/ bias-disable;
bias-pull-up;
};
};
&usbotg_hs {
u-boot,force-b-session-valid;
hnp-srp-disable;
};

178
arch/arm/dts/stm32mp15xx-dhcor-testbench.dts Normal file
View file

@ -0,0 +1,178 @@
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
/*
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "stm32mp151.dtsi"
#include "stm32mp15xx-dhcor-som.dtsi"
/ {
model = "DH electronics STM32MP15xx DHCOR Testbench";
compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx";
aliases {
ethernet0 = &ethernet0;
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
serial0 = &uart4;
serial1 = &uart7;
spi0 = &qspi;
};
chosen {
stdout-path = "serial0:115200n8";
};
sd_switch: regulator-sd_switch {
compatible = "regulator-gpio";
regulator-name = "sd_switch";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-type = "voltage";
regulator-always-on;
gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1>,
<2900000 0x0>;
};
};
&adc {
pinctrl-names = "default";
pinctrl-0 = <&adc12_ain_pins_b>;
vdd-supply = <&vdd>;
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
adc1: adc@0 {
st,adc-channels = <0 1 6>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
};
adc2: adc@100 {
st,adc-channels = <0 1 2>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
};
};
&ethernet0 {
status = "okay";
pinctrl-0 = <&ethernet0_rgmii_pins_c>;
pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>;
pinctrl-names = "default", "sleep";
phy-mode = "rgmii";
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
phy0: ethernet-phy@7 {
reg = <7>;
rxc-skew-ps = <1500>;
rxdv-skew-ps = <540>;
rxd0-skew-ps = <420>;
rxd1-skew-ps = <420>;
rxd2-skew-ps = <420>;
rxd3-skew-ps = <420>;
txc-skew-ps = <1440>;
txen-skew-ps = <540>;
txd0-skew-ps = <420>;
txd1-skew-ps = <420>;
txd2-skew-ps = <420>;
txd3-skew-ps = <420>;
};
};
};
&sdmmc1 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>;
cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,sig-dir;
st,neg-edge;
st,use-ckin;
bus-width = <4>;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&sd_switch>;
status = "okay";
};
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>;
bus-width = <8>;
mmc-ddr-1_8v;
no-sd;
no-sdio;
non-removable;
st,neg-edge;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&v3v3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_b>;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&uart7_pins_a>;
uart-has-rtscts;
/delete-property/dmas;
/delete-property/dma-names;
status = "okay";
};
&usbh_ehci {
phys = <&usbphyc_port0>;
phy-names = "usb";
status = "okay";
};
&usbotg_hs {
pinctrl-0 = <&usbotg_hs_pins_a>;
pinctrl-names = "default";
phy-names = "usb2-phy";
phys = <&usbphyc_port1 0>;
status = "okay";
vbus-supply = <&vbus_otg>;
};
&usbphyc {
status = "okay";
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&vdd_usb>;
};
&vdd {
/delete-property/ regulator-always-on;
regulator-min-microvolt = <1200000>;
};

17
arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
View file

@ -144,6 +144,21 @@
CLK_LPTIM45_LSE
>;
/*
* cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >;
* frac = < f >;
*
* PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled
* DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN
* m ... for PLL1,2: m=2 ; for PLL3,4: m=1
* XTAL = 24 MHz
*
* VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) )
* P = VCO / (P + 1)
* Q = VCO / (Q + 1)
* R = VCO / (R + 1)
*/
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
compatible = "st,stm32mp1-pll";
@ -162,7 +177,7 @@
u-boot,dm-pre-reloc;
};
/* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
pll4: st,pll@3 {
compatible = "st,stm32mp1-pll";
reg = <3>;

2
arch/arm/mach-stm32mp/Kconfig.15x
View file

@ -117,7 +117,7 @@ endif
if DEBUG_UART
config DEBUG_UART_BOARD_INIT
default y
default y if SPL
# debug on UART4 by default
config DEBUG_UART_BASE

41
board/dhelectronics/dh_stm32mp1/board.c
View file

@ -547,7 +547,7 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
if (!prop || !len)
return -ENODEV;
if (!strstr(prop, "avenger96"))
if (!strstr(prop, "avenger96") && !strstr(prop, "dhcor-testbench"))
return -EINVAL;
/* Read out STPMIC1 NVM and determine default Buck3 voltage. */
@ -564,18 +564,32 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv)
bucks_vout >>= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(3);
bucks_vout &= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK;
/*
* Avenger96 board comes in multiple regulator configurations:
* - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on
* boot and contains extra Enpirion EP53A8LQI DCDC converter which
* supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power.
* - rev.200L have Buck3 preconfigured to 1V8 operation and have no
* Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3.
*/
if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3)
*uv = 2900000;
else
*uv = 1800000;
if (strstr(prop, "avenger96")) {
/*
* Avenger96 board comes in multiple regulator configurations:
* - rev.100 or rev.200 have Buck3 preconfigured to
* 3V3 operation on boot and contains extra Enpirion
* EP53A8LQI DCDC converter which supplies the IO.
* Reduce Buck3 voltage to 2V9 to not waste power.
* - rev.200L have Buck3 preconfigured to 1V8 operation
* and have no Enpirion EP53A8LQI DCDC anymore, the
* IO is supplied from Buck3.
*/
if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3)
*uv = 2900000;
else
*uv = 1800000;
} else {
/* Testbench always respects Buck3 NVM settings */
if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3)
*uv = 3300000;
else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V0)
*uv = 3000000;
else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V8)
*uv = 1800000;
else /* STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 */
*uv = 1200000;
}
return 0;
}
@ -595,6 +609,7 @@ static void board_init_regulator_av96(void)
/* Adjust Buck3 per preconfigured PMIC voltage from NVM. */
regulator_set_value(rdev, uv);
regulator_set_enable(rdev, true);
}
static void board_init_regulator(void)

21
board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its
View file

@ -18,13 +18,21 @@
fdt-1 {
description = ".dtb";
data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb");
data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-testbench.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
};
fdt-2 {
description = ".dtb";
data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
};
fdt-3 {
description = ".dtb";
data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtb");
type = "flat_dt";
@ -38,18 +46,25 @@
config-1 {
/* DT+SoM+board model */
description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
description = "dh,stm32mp15xx-dhcor-testbench_somrev0_boardrev1";
firmware = "uboot";
fdt = "fdt-1";
};
config-2 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0";
description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1";
firmware = "uboot";
fdt = "fdt-2";
};
config-3 {
/* DT+SoM+board model */
description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0";
firmware = "uboot";
fdt = "fdt-3";
};
/* Add 586-200..586-400 with fdt-2..fdt-4 here */
};
};

2
board/engicam/stm32mp1/Makefile
View file

@ -8,3 +8,5 @@ obj-y += spl.o
else
obj-y += stm32mp1.o
endif
obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += ../../st/stm32mp1/debug_uart.o

25
board/engicam/stm32mp1/spl.c
View file

@ -6,7 +6,6 @@
*/
#include <common.h>
#include <asm/io.h>
/* board early initialisation in board_f: need to use global variable */
static u32 opp_voltage_mv __section(".data");
@ -22,27 +21,3 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
/* UART4 clock enable */
setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
#define GPIOG_BASE 0x50008000
/* GPIOG clock enable */
writel(BIT(6), RCC_MP_AHB4ENSETR);
/* GPIO configuration for ST boards: Uart4 TX = G11 */
writel(0xffbfffff, GPIOG_BASE + 0x00);
writel(0x00006000, GPIOG_BASE + 0x24);
#else
#error("CONFIG_DEBUG_UART_BASE: not supported value")
#endif
}
#endif

2
board/st/stm32mp1/Makefile
View file

@ -8,3 +8,5 @@ obj-y += spl.o
else
obj-y += stm32mp1.o
endif
obj-$(CONFIG_DEBUG_UART_BOARD_INIT) += debug_uart.o

29
board/st/stm32mp1/debug_uart.c Normal file
View file

@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
/*
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
*/
#include <config.h>
#include <debug_uart.h>
#include <asm/io.h>
#include <asm/arch/stm32.h>
#include <linux/bitops.h>
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
#define GPIOG_BASE 0x50008000
void board_debug_uart_init(void)
{
if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE) {
/* UART4 clock enable */
setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
/* GPIOG clock enable */
writel(BIT(6), RCC_MP_AHB4ENSETR);
/* GPIO configuration for ST boards: Uart4 TX = G11 */
writel(0xffbfffff, GPIOG_BASE + 0x00);
writel(0x00006000, GPIOG_BASE + 0x24);
}
}

28
board/st/stm32mp1/spl.c
View file

@ -5,11 +5,7 @@
#include <config.h>
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include "../common/stpmic1.h"
/* board early initialisation in board_f: need to use global variable */
@ -29,27 +25,3 @@ int board_early_init_f(void)
return 0;
}
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#if (CONFIG_DEBUG_UART_BASE == STM32_UART4_BASE)
#define RCC_MP_APB1ENSETR (STM32_RCC_BASE + 0x0A00)
#define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28)
/* UART4 clock enable */
setbits_le32(RCC_MP_APB1ENSETR, BIT(16));
#define GPIOG_BASE 0x50008000
/* GPIOG clock enable */
writel(BIT(6), RCC_MP_AHB4ENSETR);
/* GPIO configuration for ST boards: Uart4 TX = G11 */
writel(0xffbfffff, GPIOG_BASE + 0x00);
writel(0x00006000, GPIOG_BASE + 0x24);
#else
#error("CONFIG_DEBUG_UART_BASE: not supported value")
#endif
}
#endif

1
configs/stm32mp15_dhcom_basic_defconfig
View file

@ -79,6 +79,7 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=nor0"

1
configs/stm32mp15_dhcor_basic_defconfig
View file

@ -77,6 +77,7 @@ CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=nor0"