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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini 2018-04-26 07:21:41 -04:00
commit d2a1f120cf
40 changed files with 90 additions and 54 deletions
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1
arch/arm/Kconfig
View file

@ -1185,6 +1185,7 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET
imply ADC
imply SARADC_ROCKCHIP
imply SYS_NS16550
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"

24
arch/arm/dts/rk3188-radxarock-u-boot.dtsi Normal file
View file

@ -0,0 +1,24 @@
/*
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
&cru {
u-boot,dm-spl;
};
&pinctrl {
u-boot,dm-spl;
};
&uart2 {
status = "okay";
u-boot,dm-spl;
};
&timer3 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
u-boot,dm-spl;
clock-frequency = <24000000>;
};

6
arch/arm/dts/rk3188-radxarock.dts
View file

@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
#include "rk3188-radxarock-u-boot.dtsi"
/ {
model = "Radxa Rock";
@ -356,11 +357,6 @@
status = "okay";
};
&uart2 {
status = "okay";
u-boot,dm-spl;
};
&uart3 {
status = "okay";
};

8
arch/arm/dts/rk3188.dtsi
View file

@ -105,7 +105,6 @@
compatible = "rockchip,rk3188-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
u-boot,dm-spl;
#clock-cells = <1>;
#reset-cells = <1>;
@ -124,6 +123,12 @@
};
};
timer3: timer@2000e000 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
};
usbphy: phy {
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
rockchip,grf = <&grf>;
@ -156,7 +161,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
u-boot,dm-spl;
gpio0: gpio0@2000a000 {
compatible = "rockchip,gpio-bank";

1
arch/arm/mach-rockchip/Kconfig
View file

@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including

2
arch/arm/mach-rockchip/Makefile
View file

@ -40,8 +40,10 @@ endif
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
ifndef CONFIG_ARM64
ifndef CONFIG_ROCKCHIP_RK3188
obj-y += rk_timer.o
endif
endif
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/

2
arch/arm/mach-rockchip/make_fit_atf.py
View file

@ -13,8 +13,6 @@ import getopt
# pip install pyelftools
from elftools.elf.elffile import ELFFile
from elftools.elf.sections import SymbolTableSection
from elftools.elf.segments import Segment, InterpSegment, NoteSegment
ELF_SEG_P_TYPE='p_type'
ELF_SEG_P_PADDR='p_paddr'

2
arch/arm/mach-rockchip/rk3188-board-spl.c
View file

@ -131,8 +131,6 @@ void board_init_f(ulong dummy)
hang();
}
rockchip_timer_init();
ret = rockchip_get_clk(&dev);
if (ret) {
debug("CLK init failed: %d\n", ret);

2
arch/arm/mach-rockchip/rk322x-board-spl.c
View file

@ -95,7 +95,7 @@ void board_init_f(ulong dummy)
/* Disable the ddr secure region setting to make it non-secure */
rk_clrreg(SGRF_DDR_CON0, 0x4000);
#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
}

1
configs/chromebit_mickey_defconfig
View file

@ -71,7 +71,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y

1
configs/chromebook_jerry_defconfig
View file

@ -72,7 +72,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y

1
configs/chromebook_minnie_defconfig
View file

@ -71,7 +71,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SERIAL=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y

1
configs/evb-rk3128_defconfig
View file

@ -34,7 +34,6 @@ CONFIG_DM_RESET=y
CONFIG_DEBUG_UART_BASE=0x20068000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y

1
configs/evb-rk3229_defconfig
View file

@ -46,7 +46,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0x11030000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_GADGET=y

1
configs/evb-rk3288_defconfig
View file

@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

1
configs/evb-rk3328_defconfig
View file

@ -44,7 +44,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF130000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y

4
configs/evb-rk3399_defconfig
View file

@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb"
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_STACK_R=y
@ -25,6 +26,8 @@ CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_OF_PLATDATA=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
@ -56,7 +59,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y

1
configs/fennec-rk3288_defconfig
View file

@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

1
configs/firefly-rk3288_defconfig
View file

@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

1
configs/firefly-rk3399_defconfig
View file

@ -58,7 +58,6 @@ CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y

1
configs/miqi-rk3288_defconfig
View file

@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

1
configs/phycore-rk3288_defconfig
View file

@ -67,7 +67,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

1
configs/popmetal-rk3288_defconfig
View file

@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

3
configs/puma-rk3399_defconfig
View file

@ -80,10 +80,11 @@ CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_DM_RTC=y
CONFIG_RTC_ISL1208=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_ROCKCHIP_SPI=y
CONFIG_SYSRESET=y
CONFIG_USB=y

1
configs/rock2_defconfig
View file

@ -64,7 +64,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

4
configs/rock_defconfig
View file

@ -5,6 +5,9 @@ CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ROCKCHIP_RK3188=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ROCKCHIP_TIMER=y
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
CONFIG_TARGET_ROCK=y
CONFIG_SPL_STACK_R_ADDR=0x60080000
@ -47,7 +50,6 @@ CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0x20064000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_ROCKCHIP_USB2_PHY=y

1
configs/tinker-rk3288_defconfig
View file

@ -66,7 +66,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

1
configs/vyasa-rk3288_defconfig
View file

@ -63,7 +63,6 @@ CONFIG_SPL_RAM=y
CONFIG_DEBUG_UART_BASE=0xff690000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_DWC2=y

11
drivers/clk/rockchip/clk_rk3036.c
View file

@ -317,11 +317,19 @@ static struct clk_ops rk3036_clk_ops = {
.set_rate = rk3036_clk_set_rate,
};
static int rk3036_clk_probe(struct udevice *dev)
static int rk3036_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
return 0;
}
static int rk3036_clk_probe(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
rkclk_init(priv->cru);
return 0;
@ -367,6 +375,7 @@ U_BOOT_DRIVER(rockchip_rk3036_cru) = {
.id = UCLASS_CLK,
.of_match = rk3036_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3036_clk_priv),
.ofdata_to_platdata = rk3036_clk_ofdata_to_platdata,
.ops = &rk3036_clk_ops,
.bind = rk3036_clk_bind,
.probe = rk3036_clk_probe,

11
drivers/clk/rockchip/clk_rk3128.c
View file

@ -546,11 +546,19 @@ static struct clk_ops rk3128_clk_ops = {
.set_rate = rk3128_clk_set_rate,
};
static int rk3128_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rk3128_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
return 0;
}
static int rk3128_clk_probe(struct udevice *dev)
{
struct rk3128_clk_priv *priv = dev_get_priv(dev);
priv->cru = (struct rk3128_cru *)dev_read_addr(dev);
rkclk_init(priv->cru);
return 0;
@ -590,6 +598,7 @@ U_BOOT_DRIVER(rockchip_rk3128_cru) = {
.id = UCLASS_CLK,
.of_match = rk3128_clk_ids,
.priv_auto_alloc_size = sizeof(struct rk3128_clk_priv),
.ofdata_to_platdata = rk3128_clk_ofdata_to_platdata,
.ops = &rk3128_clk_ops,
.bind = rk3128_clk_bind,
.probe = rk3128_clk_probe,

13
drivers/clk/rockchip/clk_rk3288.c
View file

@ -893,12 +893,25 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par
return -ENOENT;
}
static int rk3288_clk_enable(struct clk *clk)
{
switch (clk->id) {
case HCLK_USBHOST0:
case HCLK_HSIC:
return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);
return -ENOENT;
}
static struct clk_ops rk3288_clk_ops = {
.get_rate = rk3288_clk_get_rate,
.set_rate = rk3288_clk_set_rate,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.set_parent = rk3288_clk_set_parent,
#endif
.enable = rk3288_clk_enable,
};
static int rk3288_clk_ofdata_to_platdata(struct udevice *dev)

10
drivers/clk/rockchip/clk_rv1108.c
View file

@ -209,12 +209,19 @@ static void rkclk_init(struct rv1108_cru *cru)
printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
}
static int rv1108_clk_probe(struct udevice *dev)
static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
priv->cru = dev_read_addr_ptr(dev);
return 0;
}
static int rv1108_clk_probe(struct udevice *dev)
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
rkclk_init(priv->cru);
return 0;
@ -260,6 +267,7 @@ U_BOOT_DRIVER(clk_rv1108) = {
.id = UCLASS_CLK,
.of_match = rv1108_clk_ids,
.priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
.ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
.ops = &rv1108_clk_ops,
.bind = rv1108_clk_bind,
.probe = rv1108_clk_probe,

2
drivers/timer/rockchip_timer.c
View file

@ -152,6 +152,8 @@ static const struct timer_ops rockchip_timer_ops = {
};
static const struct udevice_id rockchip_timer_ids[] = {
{ .compatible = "rockchip,rk3188-timer" },
{ .compatible = "rockchip,rk3288-timer" },
{ .compatible = "rockchip,rk3368-timer" },
{}
};

3
include/configs/firefly-rk3288.h
View file

@ -10,8 +10,7 @@
#define ROCKCHIP_DEVICE_SETTINGS \
"stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"preboot=usb start\0"
"stderr=serial,vidconsole\0"
#include <configs/rk3288_common.h>

3
include/configs/rk3036_common.h
View file

@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10081fff

2
include/configs/rk3128_common.h
View file

@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800

5
include/configs/rk3188_common.h
View file

@ -17,11 +17,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM

3
include/configs/rk322x_common.h
View file

@ -18,11 +18,10 @@
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10088000
#define CONFIG_SPL_TEXT_BASE 0x10081004
#define CONFIG_SPL_TEXT_BASE 0x10081000
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"

3
include/configs/rk3288_common.h
View file

@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#endif
@ -73,6 +71,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x0fffffff\0" \
"initrd_high=0x0fffffff\0" \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"partitions=" PARTS_DEFAULT \
ENV_MEM_LAYOUT_SETTINGS \
ROCKCHIP_DEVICE_SETTINGS \

3
include/configs/rv1108_common.h
View file

@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)