From 715cce65b889214a728dd44759204316aff29006 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:42 -0500 Subject: [PATCH 001/424] Convert CONFIG_SYS_NAND_DBW_8 et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_DBW_8 CONFIG_SYS_NAND_DBW_16 Note that all instances of the code check for CONFIG_SYS_NAND_DBW_16 being defined, and then "else" to CONFIG_SYS_NAND_DBW_8 whereas all of the configs set CONFIG_SYS_NAND_DBW_8. So we introduce CONFIG_SYS_NAND_DBW_16 as an option. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/mtd/nand/raw/Kconfig | 12 ++++++++++++ include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/corvus.h | 1 - include/configs/ethernut5.h | 1 - include/configs/gardena-smart-gateway-at91sam.h | 1 - include/configs/meesc.h | 1 - include/configs/pm9261.h | 1 - include/configs/pm9263.h | 1 - include/configs/pm9g45.h | 1 - include/configs/smartweb.h | 1 - include/configs/snapper9g45.h | 1 - include/configs/taurus.h | 1 - 17 files changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index da2c5795bc..48a7507c64 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -83,6 +83,18 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER help Generate Programmable Multibit ECC (PMECC) header for SPL image. +choice + prompt "NAND bus width (bits)" + default SYS_NAND_DBW_8 + +config SYS_NAND_DBW_8 + bool "NAND bus width is 8 bits" + +config SYS_NAND_DBW_16 + bool "NAND bus width is 16 bits" + +endchoice + endif config NAND_BRCMNAND diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index d51da9d506..60b47379e5 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -44,7 +44,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 5dc8f21a85..d80a686e9e 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -25,7 +25,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD22 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d31a7742a1..89a8e43e1e 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -151,7 +151,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 01085476a4..55edd706ea 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -21,7 +21,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index c60c248b74..0a512c217f 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -26,7 +26,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 71a2863bfc..b8a14d571d 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -28,7 +28,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 0596afbf9f..3e7c0c0d88 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -38,7 +38,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 22647abee0..a18920d3f0 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -38,7 +38,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 52b9fe2b17..3d62efb38f 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -23,7 +23,6 @@ /* NAND flash */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 9f913fad16..30267e29a1 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -53,7 +53,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ -# define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 278f1b5cc6..6a89fb1fa9 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -130,7 +130,6 @@ /* NAND flash */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD22 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) /* our CLE is AD21 */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 7c23206a30..c56db4d793 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -147,7 +147,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 35fd525683..7d3a326dea 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -26,7 +26,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index a77215d19b..c8f5816fed 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -55,7 +55,6 @@ /* NAND flash settings */ #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index c56fb37831..6aba1d3194 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -31,7 +31,6 @@ /* NAND Flash */ #define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 45780d9a4e..ca9616d8af 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -55,7 +55,6 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 From 50493dd1f9f56097721c043fb7bd55c4cb2cc5e4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:43 -0500 Subject: [PATCH 002/424] Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NAND_DDR_LAW CONFIG_SYS_NAND_ECCSTEPS CONFIG_SYS_NAND_ECCTOTAL CONFIG_SYS_NAND_ENABLE_PIN_SPL CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES CONFIG_SYS_NAND_U_BOOT_RELOC_SP Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/P1010RDB.h | 2 -- include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/colibri_imx7.h | 1 - include/configs/da850evm.h | 4 ---- include/configs/omapl138_lcdk.h | 4 ---- include/configs/siemens-am33x-common.h | 4 ---- include/configs/smartweb.h | 1 - include/configs/taurus.h | 1 - 12 files changed, 22 deletions(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index addb306d57..3448766d8e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -235,8 +235,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_FTIM3 0x0 #endif -#define CONFIG_SYS_NAND_DDR_LAW 11 - /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 62c4177f30..4b2327d323 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -234,7 +234,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index ad8037e7a8..e7d82bf411 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -210,7 +210,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2dcaeda78b..08195505b1 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -198,7 +198,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 223c856751..75d9200d56 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -174,7 +174,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 12edfdd68d..d79789af0e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -231,7 +231,6 @@ FTIM2_NAND_TWHRE(0x1e)) #define CONFIG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 7380440ae7..5c7a9f2e69 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -167,7 +167,6 @@ #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES #endif /* USB Configs */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 281cbe37f9..262a79be01 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -117,10 +117,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_NAND_ECCPOS { \ 24, 25, 26, 27, 28, \ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 4103930241..4b24d614e1 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -116,10 +116,6 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_NAND_ECCPOS { \ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 87da5e4232..dd247d2fd9 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -59,10 +59,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index c8f5816fed..538aad9a7b 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -92,7 +92,6 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE diff --git a/include/configs/taurus.h b/include/configs/taurus.h index ca9616d8af..5ab087da8b 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -126,7 +126,6 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE From 60db32502c7f5d54c4cd4e485b95204166a83678 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:44 -0500 Subject: [PATCH 003/424] Convert CONFIG_SYS_NAND_HW_ECC_OOBFIRST to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_HW_ECC_OOBFIRST Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 4 ---- configs/da850evm_nand_defconfig | 1 + configs/omapl138_lcdk_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 5 +++++ include/configs/da850evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - 6 files changed, 7 insertions(+), 6 deletions(-) diff --git a/README b/README index d75c3fbc85..4309d93386 100644 --- a/README +++ b/README @@ -1378,10 +1378,6 @@ The following options need to be configured: CONFIG_SYS_NAND_U_BOOT_START Entry point in loaded image to jump to - CONFIG_SYS_NAND_HW_ECC_OOBFIRST - Define this if you need to first read the OOB and then the - data. This is used, for example, on davinci platforms. - CONFIG_SPL_RAM_DEVICE Support for running image already present in ram, in SPL binary diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 30454a3787..84563b2a3c 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -87,6 +87,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y +CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 51c78dc51a..a067c01779 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -84,6 +84,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y +CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 48a7507c64..49b7a4b04b 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -712,6 +712,11 @@ config SPL_NAND_SIMPLE help Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. + +config SYS_NAND_HW_ECC_OOBFIRST + bool "In SPL, read the OOB first and then the data from NAND" + depends on SPL_NAND_SIMPLE + endif endif # if NAND diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 262a79be01..abf5db934c 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -113,7 +113,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 4b24d614e1..184360f7e9 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 From 41fa8f471d41fd42a249e3f24e5ecb2fa8f1b1d4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:45 -0500 Subject: [PATCH 004/424] Convert CONFIG_SYS_NAND_HW_ECC to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_HW_ECC Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/da850evm_nand_defconfig | 1 - configs/k2e_evm_defconfig | 1 - configs/k2e_hs_evm_defconfig | 1 - configs/k2hk_evm_defconfig | 1 - configs/k2hk_hs_evm_defconfig | 1 - configs/k2l_evm_defconfig | 1 - configs/k2l_hs_evm_defconfig | 1 - configs/omapl138_lcdk_defconfig | 1 - drivers/mtd/nand/raw/Kconfig | 14 +++++++++++++- drivers/mtd/nand/raw/davinci_nand.c | 7 +++---- include/configs/da850evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - 12 files changed, 16 insertions(+), 15 deletions(-) diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 84563b2a3c..a7aaf46ea5 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -86,7 +86,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 9bf2e862b0..977348e73f 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -79,7 +79,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index afa4dc1b41..afba285ffb 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -54,7 +54,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index cbf948f578..6c4563912b 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -79,7 +79,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 2480547a51..33624badae 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -54,7 +54,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index f4c8c5e233..e28054bcc7 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -79,7 +79,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 051cd23481..8f8bb54913 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -57,7 +57,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index a067c01779..ff3b5f0857 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -83,7 +83,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y -CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 49b7a4b04b..0e428418b2 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -148,9 +148,21 @@ config NAND_DAVINCI Enable this driver for NAND flash controllers available in TI Davinci and Keystone2 platforms +choice + prompt "Type of ECC used on NAND" + default SYS_NAND_4BIT_HW_ECC_OOBFIRST + depends on NAND_DAVINCI + +config SYS_NAND_HW_ECC + bool "Use 1-bit HW ECC" + config SYS_NAND_4BIT_HW_ECC_OOBFIRST bool "Use 4-bit HW ECC with OOB at the front" - depends on NAND_DAVINCI + +config SYS_NAND_SOFT_ECC + bool "Use software ECC" + +endchoice config KEYSTONE_RBL_NAND depends on ARCH_KEYSTONE diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 9158d94de2..54aed13638 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -766,10 +766,7 @@ static void davinci_nand_init(struct nand_chip *nand) nand->ecc.calculate = nand_davinci_calculate_ecc; nand->ecc.correct = nand_davinci_correct_data; nand->ecc.hwctl = nand_davinci_enable_hwecc; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif /* CONFIG_SYS_NAND_HW_ECC */ -#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#elif defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; nand->ecc.size = 512; nand->ecc.bytes = 10; @@ -778,6 +775,8 @@ static void davinci_nand_init(struct nand_chip *nand) nand->ecc.correct = nand_davinci_4bit_correct_data; nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc; nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst; +#elif defined(CONFIG_SYS_NAND_SOFT_ECC) + nand->ecc.mode = NAND_ECC_SOFT; #endif /* Set address of hardware control function */ nand->cmd_ctrl = nand_davinci_hwcontrol; diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index abf5db934c..11f104bcb8 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 184360f7e9..233e7b4ee5 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -110,7 +110,6 @@ #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 From b41641d52efa242b38fbe5f976331005e329487a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:46 -0500 Subject: [PATCH 005/424] mtd: nand: raw: atmel_nand: Use ATMEL_BASE_ECC directly This is the only driver, and only one platform makes use of, setting CONFIG_SYS_NAND_ECC_BASE. Reference ATMEL_BASE_ECC directly in this case. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/mtd/nand/raw/atmel_nand.c | 18 +++++++++--------- include/configs/snapper9g45.h | 1 - 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 61bfd175be..a541af6db4 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1012,13 +1012,13 @@ static int atmel_nand_calculate(struct mtd_info *mtd, unsigned int ecc_value; /* get the first 2 ECC bytes */ - ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR); + ecc_value = ecc_readl(ATMEL_BASE_ECC, PR); ecc_code[0] = ecc_value & 0xFF; ecc_code[1] = (ecc_value >> 8) & 0xFF; /* get the last 2 ECC bytes */ - ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY; + ecc_value = ecc_readl(ATMEL_BASE_ECC, NPR) & ATMEL_ECC_NPARITY; ecc_code[2] = ecc_value & 0xFF; ecc_code[3] = (ecc_value >> 8) & 0xFF; @@ -1101,16 +1101,16 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, unsigned int ecc_word, ecc_bit; /* get the status from the Status Register */ - ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR); + ecc_status = ecc_readl(ATMEL_BASE_ECC, SR); /* if there's no error */ if (likely(!(ecc_status & ATMEL_ECC_RECERR))) return 0; /* get error bit offset (4 bits) */ - ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR; + ecc_bit = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_BITADDR; /* get word address (12 bits) */ - ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR; + ecc_word = ecc_readl(ATMEL_BASE_ECC, PR) & ATMEL_ECC_WORDADDR; ecc_word >>= 4; /* if there are multiple errors */ @@ -1180,22 +1180,22 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd) switch (mtd->writesize) { case 512: nand->ecc.layout = &atmel_oobinfo_small; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_528); break; case 1024: nand->ecc.layout = &atmel_oobinfo_large; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_1056); break; case 2048: nand->ecc.layout = &atmel_oobinfo_large; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_2112); break; case 4096: nand->ecc.layout = &atmel_oobinfo_large; - ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, + ecc_writel(ATMEL_BASE_ECC, MR, ATMEL_ECC_PAGESIZE_4224); break; default: diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 6aba1d3194..29462c526e 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -29,7 +29,6 @@ /* Mem test settings */ /* NAND Flash */ -#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ From 4d3495deb653ad4e50051e846667eaad8257e1f9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:47 -0500 Subject: [PATCH 006/424] Convert CONFIG_SYS_NAND_MAX_OOBFREE et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_MAX_OOBFREE CONFIG_SYS_NAND_MAX_ECCPOS Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/CHIP_pro_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/am3517_evm_defconfig | 2 ++ configs/ls1088aqds_defconfig | 2 ++ configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088aqds_qspi_defconfig | 2 ++ configs/ls1088aqds_sdcard_ifc_defconfig | 2 ++ configs/ls1088aqds_sdcard_qspi_defconfig | 2 ++ configs/ls1088aqds_tfa_defconfig | 2 ++ configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_qspi_defconfig | 2 ++ ...s1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_sdcard_qspi_defconfig | 2 ++ configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1088ardb_tfa_defconfig | 2 ++ configs/ls2080aqds_SECURE_BOOT_defconfig | 2 ++ configs/ls2080aqds_defconfig | 2 ++ configs/ls2080aqds_nand_defconfig | 2 ++ configs/ls2080aqds_qspi_defconfig | 2 ++ configs/ls2080aqds_sdcard_defconfig | 2 ++ configs/ls2080ardb_SECURE_BOOT_defconfig | 2 ++ configs/ls2080ardb_defconfig | 2 ++ configs/ls2080ardb_nand_defconfig | 2 ++ configs/ls2088aqds_tfa_defconfig | 2 ++ configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls2088ardb_tfa_defconfig | 2 ++ configs/omap35_logic_defconfig | 2 ++ configs/omap35_logic_somlv_defconfig | 2 ++ configs/omap3_logic_defconfig | 2 ++ configs/omap3_logic_somlv_defconfig | 2 ++ doc/README.nand | 10 ---------- drivers/mtd/Kconfig | 18 ++++++++++++++++++ include/configs/T4240RDB.h | 2 -- include/configs/am3517_evm.h | 2 -- include/configs/ls1088aqds.h | 3 --- include/configs/ls1088ardb.h | 3 --- include/configs/ls2080aqds.h | 3 --- include/configs/ls2080ardb.h | 3 --- include/configs/omap3_logic.h | 2 -- include/configs/sunxi-common.h | 4 ---- 40 files changed, 76 insertions(+), 32 deletions(-) diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 0e7d5e7c96..2f558454e8 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0x100 +CONFIG_SYS_NAND_MAX_ECCPOS=1664 CONFIG_AXP_ALDO3_VOLT=3300 CONFIG_AXP_ALDO4_VOLT=3300 CONFIG_CONS_INDEX=2 diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 94060ab107..1b7a457408 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 +CONFIG_SYS_NAND_MAX_ECCPOS=1664 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_ELDO2_VOLT=1800 CONFIG_CONS_INDEX=5 diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 45332e2d60..0839d366cf 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -81,6 +81,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_DRIVER_TI_EMAC_USE_RMII=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 1e865909aa..8556c00355 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -83,6 +83,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index cfe15406e8..d4f2268041 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -69,6 +69,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 4e0e7c302a..af63278bb3 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -72,6 +72,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 0a7541d5e6..6b42170ffb 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -104,6 +104,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index d9f27816eb..dedefb3a0a 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -92,6 +92,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index cce2d9ab19..60f26f0183 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -91,6 +91,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_EON=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index 4c46384a6f..a819ebfeff 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -72,6 +72,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 796264502d..c569753338 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -75,6 +75,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 504db13696..2b96382f24 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -95,6 +95,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 8053bc17bb..4263635384 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -95,6 +95,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 7ba5940481..2e812943fd 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -71,6 +71,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index ff5784bf6c..9c12f2be9c 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -77,6 +77,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 8899fd930f..817ae8d728 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -74,6 +74,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index a9f52ae5a1..b3e75847cc 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -77,6 +77,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 0b70e7b02b..effcd33629 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -91,6 +91,8 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 648a539050..eb57948414 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -71,6 +71,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 318822bd83..e5702b8159 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -85,6 +85,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 8ae8b52f6a..face1e0532 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -76,6 +76,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index d548bcab3f..ba6f5090d4 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -79,6 +79,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index a49fe87f71..5000290030 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -100,6 +100,8 @@ CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 4c1e7421bf..9c6012460b 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_BANKS=2 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 93be74d00c..dc9a47463f 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -81,6 +81,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index c2bf451dd9..3610985680 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -88,6 +88,8 @@ CONFIG_SYS_MAX_FLASH_SECT=1024 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_FSL_IFC=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=256 CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 93daa460ba..84e267da58 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -80,6 +80,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index de33825d13..471e0556fa 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -88,6 +88,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index e2c6dfcf48..67db3afd7f 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -79,6 +79,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 3237c4280a..e18cbaa5c1 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -89,6 +89,8 @@ CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_MAX_OOBFREE=2 +CONFIG_SYS_NAND_MAX_ECCPOS=56 CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_PINCTRL=y diff --git a/doc/README.nand b/doc/README.nand index d1ce30768b..a3c3ab4b95 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -99,16 +99,6 @@ Configuration Options: CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below). - CONFIG_SYS_NAND_MAX_ECCPOS - If specified, overrides the maximum number of ECC bytes - supported. Useful for reducing image size, especially with SPL. - This must be at least 48 if nand_base.c is used. - - CONFIG_SYS_NAND_MAX_OOBFREE - If specified, overrides the maximum number of free OOB regions - supported. Useful for reducing image size, especially with SPL. - This must be at least 2 if nand_base.c is used. - CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index fcdb450f77..d8e2dec0a8 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -212,6 +212,24 @@ config SYS_MAX_FLASH_BANKS_DETECT source "drivers/mtd/nand/Kconfig" +config SYS_NAND_MAX_OOBFREE + int "Maximum number of free OOB regions supported" + depends on SAMSUNG_ONENAND || MTD_RAW_NAND + range 2 32 + default 32 + help + Set the maximum number of free OOB regions supported. Useful for + reducing image size, especially with SPL. + +config SYS_NAND_MAX_ECCPOS + int "Maximum number of ECC bytes supported" + depends on SAMSUNG_ONENAND || MTD_RAW_NAND + range 48 2147483647 + default 680 + help + Set the maximum number of ECC bytes supported. Useful for reducing + image size, especially with SPL. + config SYS_NAND_MAX_CHIPS int "NAND max chips" depends on MTD_RAW_NAND || CMD_ONENAND || TARGET_S5PC210_UNIVERSAL || \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index d79789af0e..cfd9cb3e7c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -197,8 +197,6 @@ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_BASE 0xff800000 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index e0f5f2b044..2eb7a51ce2 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -25,8 +25,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* NAND block size is 128 KiB. Synchronize these values with * corresponding Device Tree entries in Linux: diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index d50b76b89a..3a2fba6b04 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -69,9 +69,6 @@ #endif #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 4edf40b0b7..e2ae3026c2 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -53,9 +53,6 @@ #endif #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 1fa4aa3734..e6019870d8 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -70,9 +70,6 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index e1c66c5dcc..382d516c08 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -67,9 +67,6 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - #define CONFIG_SYS_NAND_CSPR_EXT (0x0) #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 442a3cad22..7c0bdcbb11 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -26,8 +26,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 #endif /* Environment information */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 720768629d..d9e4c8b699 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -71,10 +71,6 @@ #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ -#ifdef CONFIG_NAND_SUNXI -#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 -#endif - /* mmc config */ #define CONFIG_MMC_SUNXI_SLOT 0 From 1a792803d8905373bc04bbc2a4dc7d0d1ecdd967 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:48 -0500 Subject: [PATCH 007/424] Convert CONFIG_SYS_NAND_NO_SUBPAGE_WRITE to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_NO_SUBPAGE_WRITE Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 5 ----- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/ti_armv7_keystone2.h | 1 - 9 files changed, 10 insertions(+), 6 deletions(-) diff --git a/README b/README index 4309d93386..f24decf5e4 100644 --- a/README +++ b/README @@ -1806,11 +1806,6 @@ Low Level (hardware related) configuration options: If defined, the x86 reset vector code is included. This is not needed when U-Boot is running from Coreboot. -- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE - Option to disable subpage write in NAND driver - driver that uses this: - drivers/mtd/nand/raw/davinci_nand.c - Freescale QE/FMAN Firmware Support: ----------------------------------- diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 977348e73f..25007793b3 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index afba285ffb..6c8a284e7c 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 6c4563912b..fec29f2c91 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 33624badae..f6ac484f2e 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index e28054bcc7..bb91aa3534 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -78,6 +78,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 8f8bb54913..d10965a70f 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 0e428418b2..3585031ddf 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -41,6 +41,10 @@ config SYS_NAND_USE_FLASH_BBT help Enable the BBT (Bad Block Table) usage. +config SYS_NAND_NO_SUBPAGE_WRITE + bool "Disable subpage write support" + depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD + config NAND_ATMEL bool "Support Atmel NAND controller" select SYS_NAND_SELF_INIT diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 6c01ab813e..b8b4b28b3d 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE #define DFU_ALT_INFO_MMC \ "dfu_alt_info_mmc=" \ From a9f03760c1b85cda153723c5dc5d7ad0a64a5acc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:49 -0500 Subject: [PATCH 008/424] Convert CONFIG_SYS_NAND_PAGE_2K et al to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_PAGE_2K CONFIG_SYS_NAND_PAGE_4K Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 13 +++++++++++++ include/configs/da850evm.h | 1 - include/configs/k2e_evm.h | 3 --- include/configs/k2g_evm.h | 3 --- include/configs/k2hk_evm.h | 3 --- include/configs/k2l_evm.h | 3 --- include/configs/omapl138_lcdk.h | 1 - 9 files changed, 15 insertions(+), 14 deletions(-) diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index bb91aa3534..13d612ac3f 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -80,6 +80,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_PAGE_4K=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index d10965a70f..59ec3a6346 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -58,6 +58,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_SYS_NAND_NO_SUBPAGE_WRITE=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_PAGE_4K=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 3585031ddf..5483efeb39 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -168,6 +168,19 @@ config SYS_NAND_SOFT_ECC endchoice +choice + prompt "NAND page size" + depends on NAND_DAVINCI + default SYS_NAND_PAGE_2K + +config SYS_NAND_PAGE_2K + bool "Page size is 2K" + +config SYS_NAND_PAGE_4K + bool "Page size is 4K" + +endchoice + config KEYSTONE_RBL_NAND depends on ARCH_KEYSTONE def_bool y diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 11f104bcb8..5a5c65da16 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -107,7 +107,6 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 9b25c34982..bbc58be511 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index 887fda90d6..bb91751d5d 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -50,9 +50,6 @@ "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index cfc34c7da6..68cbe98b55 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - /* Network */ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 65988fff06..a18158a7eb 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -36,9 +36,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_4K - /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 233e7b4ee5..d9f70c7532 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -105,7 +105,6 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CONFIG_SYS_NAND_MASK_CLE 0x10 From 0cd03259644dcb967fcd6b31c3a92984125a1fe3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:50 -0500 Subject: [PATCH 009/424] Convert CONFIG_SYS_NAND_SIZE to Kconfig This converts the following to Kconfig: CONFIG_SYS_NAND_SIZE Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/mtd/nand/raw/Kconfig | 5 +++++ include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/m53menlo.h | 6 ------ include/configs/smartweb.h | 1 - include/configs/taurus.h | 1 - 6 files changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 5483efeb39..eb37b62759 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -461,6 +461,11 @@ config NAND_MXC This enables the NAND driver for the NAND flash controller on the i.MX27 / i.MX31 / i.MX5 processors. +config SYS_NAND_SIZE + int "Size of NAND in kilobytes" + depends on NAND_MXC && SPL_NAND_SUPPORT + default 268435456 + config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 47ea51c507..a39fe5f28a 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -94,7 +94,6 @@ #ifdef CONFIG_CMD_NAND # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index a2e36cc867..f0734712ea 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -95,7 +95,6 @@ #endif # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index a20b41bdf0..3652241917 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -85,12 +85,6 @@ /* Watchdog */ -/* - * NAND SPL - */ - -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) - /* * Extra Environments */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 538aad9a7b..5460c12a17 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -96,7 +96,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_SIZE (SZ_256M) #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 5ab087da8b..f130c630dd 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -130,7 +130,6 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ From 4e5909450ec2acafb3d2e5b9714251ae67e0f0e0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 12 Nov 2022 17:36:51 -0500 Subject: [PATCH 010/424] global: Move remaining CONFIG_SYS_NAND_* to CFG_SYS_NAND_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NAND namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 10 +-- arch/arm/include/asm/arch-lpc32xx/config.h | 8 +- arch/arm/include/asm/ti-common/davinci_nand.h | 8 +- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- arch/arm/mach-omap2/mem-common.c | 2 +- arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 20 ++--- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 10 +-- board/atmel/at91sam9260ek/at91sam9260ek.c | 4 +- board/atmel/at91sam9261ek/at91sam9261ek.c | 4 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 4 +- .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 4 +- board/atmel/at91sam9rlek/at91sam9rlek.c | 4 +- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 4 +- board/atmel/sam9x60ek/sam9x60ek.c | 4 +- board/bluewater/gurnard/gurnard.c | 8 +- board/calao/usb_a9263/usb_a9263.c | 8 +- board/egnite/ethernut5/ethernut5.c | 6 +- board/esd/meesc/meesc.c | 4 +- board/freescale/common/p_corenet/law.c | 4 +- board/freescale/common/p_corenet/tlb.c | 4 +- board/freescale/ls1043aqds/ls1043aqds.c | 32 ++++---- board/freescale/ls1043ardb/ls1043ardb.c | 34 ++++---- board/freescale/ls1046aqds/ls1046aqds.c | 32 ++++---- board/freescale/ls1088a/ls1088a.c | 32 ++++---- board/freescale/p1010rdb/law.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 6 +- board/freescale/p1010rdb/tlb.c | 2 +- board/freescale/p1_p2_rdb_pc/law.c | 4 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- board/freescale/t102xrdb/law.c | 4 +- board/freescale/t102xrdb/tlb.c | 4 +- board/freescale/t104xrdb/law.c | 4 +- board/freescale/t104xrdb/tlb.c | 4 +- board/freescale/t208xqds/law.c | 4 +- board/freescale/t208xqds/tlb.c | 4 +- board/freescale/t208xrdb/law.c | 4 +- board/freescale/t208xrdb/tlb.c | 4 +- board/freescale/t4rdb/law.c | 4 +- board/freescale/t4rdb/tlb.c | 4 +- board/gardena/smart-gateway-at91sam/spl.c | 4 +- board/keymile/kmcent2/law.c | 2 +- board/keymile/kmcent2/tlb.c | 2 +- board/ronetix/pm9261/pm9261.c | 4 +- board/ronetix/pm9263/pm9263.c | 4 +- board/ronetix/pm9g45/pm9g45.c | 6 +- board/siemens/corvus/board.c | 8 +- board/siemens/smartweb/smartweb.c | 8 +- board/siemens/taurus/taurus.c | 10 +-- board/socrates/nand.c | 2 +- common/spl/spl_nand.c | 8 +- doc/README.arm-relocation | 8 +- doc/README.omap3 | 6 +- doc/board/ti/am335x_evm.rst | 2 +- drivers/mtd/nand/raw/am335x_spl_bch.c | 12 +-- drivers/mtd/nand/raw/atmel_nand.c | 40 +++++----- drivers/mtd/nand/raw/davinci_nand.c | 14 ++-- drivers/mtd/nand/raw/denali_spl.c | 4 +- drivers/mtd/nand/raw/fsl_elbc_nand.c | 6 +- drivers/mtd/nand/raw/fsl_elbc_spl.c | 12 +-- drivers/mtd/nand/raw/fsl_ifc_nand.c | 6 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 20 ++--- drivers/mtd/nand/raw/fsmc_nand.c | 2 +- drivers/mtd/nand/raw/kmeter1_nand.c | 4 +- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 22 +++--- drivers/mtd/nand/raw/mxc_nand.c | 6 +- drivers/mtd/nand/raw/mxc_nand_spl.c | 8 +- drivers/mtd/nand/raw/nand.c | 6 +- drivers/mtd/nand/raw/nand_spl_load.c | 6 +- drivers/mtd/nand/raw/nand_spl_simple.c | 16 ++-- drivers/mtd/nand/raw/omap_gpmc.c | 2 +- drivers/mtd/nand/raw/vf610_nfc.c | 2 +- include/configs/M5329EVB.h | 4 +- include/configs/M5373EVB.h | 4 +- include/configs/MCR3000.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/P1010RDB.h | 78 +++++++++---------- include/configs/P2041RDB.h | 12 +-- include/configs/T102xRDB.h | 64 +++++++-------- include/configs/T104xRDB.h | 62 +++++++-------- include/configs/T208xQDS.h | 60 +++++++------- include/configs/T208xRDB.h | 60 +++++++------- include/configs/T4240RDB.h | 54 ++++++------- include/configs/am335x_evm.h | 6 +- include/configs/am335x_guardian.h | 6 +- include/configs/am335x_igep003x.h | 6 +- include/configs/am3517_evm.h | 8 +- include/configs/am43xx_evm.h | 6 +- include/configs/at91sam9260ek.h | 10 +-- include/configs/at91sam9261ek.h | 10 +-- include/configs/at91sam9263ek.h | 10 +-- include/configs/at91sam9m10g45ek.h | 18 ++--- include/configs/at91sam9n12ek.h | 10 +-- include/configs/at91sam9rlek.h | 10 +-- include/configs/at91sam9x5ek.h | 10 +-- include/configs/baltos.h | 8 +- include/configs/chiliboard.h | 6 +- include/configs/cm_fx6.h | 2 +- include/configs/cm_t43.h | 6 +- include/configs/colibri-imx6ull.h | 4 +- include/configs/colibri_imx7.h | 2 +- include/configs/corvus.h | 22 +++--- include/configs/da850evm.h | 20 ++--- include/configs/devkit3250.h | 10 +-- include/configs/devkit8000.h | 8 +- include/configs/dra7xx_evm.h | 6 +- include/configs/etamin.h | 18 ++--- include/configs/ethernut5.h | 8 +- .../configs/gardena-smart-gateway-at91sam.h | 16 ++-- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 4 +- include/configs/imx6_logic.h | 4 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx8mn_bsh_smm_s2.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/km/km-mpc83xx.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 38 ++++----- include/configs/kmcent2.h | 38 ++++----- include/configs/kmcoge5ne.h | 2 +- include/configs/ls1021aqds.h | 60 +++++++------- include/configs/ls1043a_common.h | 4 +- include/configs/ls1043aqds.h | 72 ++++++++--------- include/configs/ls1043ardb.h | 72 ++++++++--------- include/configs/ls1046a_common.h | 4 +- include/configs/ls1046afrwy.h | 38 ++++----- include/configs/ls1046aqds.h | 72 ++++++++--------- include/configs/ls1046ardb.h | 38 ++++----- include/configs/ls1088a_common.h | 4 +- include/configs/ls1088aqds.h | 66 ++++++++-------- include/configs/ls1088ardb.h | 34 ++++---- include/configs/ls2080a_common.h | 8 +- include/configs/ls2080aqds.h | 52 ++++++------- include/configs/ls2080ardb.h | 52 ++++++------- include/configs/m53menlo.h | 4 +- include/configs/meesc.h | 10 +-- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mxs.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/omap3_beagle.h | 6 +- include/configs/omap3_evm.h | 6 +- include/configs/omap3_igep00x0.h | 6 +- include/configs/omap3_logic.h | 6 +- include/configs/omapl138_lcdk.h | 20 ++--- include/configs/p1_p2_rdb_pc.h | 26 +++---- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/phycore_am335x_r2.h | 6 +- include/configs/pm9261.h | 10 +-- include/configs/pm9263.h | 10 +-- include/configs/pm9g45.h | 18 ++--- include/configs/presidio_asic.h | 4 +- include/configs/sam9x60ek.h | 10 +-- include/configs/sama5d2_ptc_ek.h | 6 +- include/configs/sama5d3_xplained.h | 6 +- include/configs/sama5d3xek.h | 6 +- include/configs/sama5d4_xplained.h | 6 +- include/configs/sama5d4ek.h | 6 +- include/configs/siemens-am33x-common.h | 10 +-- include/configs/smartweb.h | 22 +++--- include/configs/snapper9g45.h | 10 +-- include/configs/socfpga_common.h | 4 +- include/configs/socrates.h | 2 +- include/configs/taurus.h | 22 +++--- include/configs/ti816x_evm.h | 8 +- include/configs/ti_armv7_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 10 +-- include/configs/ti_armv7_omap.h | 4 +- include/configs/ti_omap3_common.h | 2 +- include/configs/uniphier.h | 4 +- include/configs/usb_a9263.h | 10 +-- include/configs/vf610twr.h | 2 +- include/configs/work_92105.h | 6 +- 175 files changed, 1102 insertions(+), 1102 deletions(-) diff --git a/README b/README index f24decf5e4..f540757627 100644 --- a/README +++ b/README @@ -1364,18 +1364,18 @@ The following options need to be configured: CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, - CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE, - CONFIG_SYS_NAND_ECCBYTES + CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE, + CFG_SYS_NAND_ECCBYTES Defines the size and behavior of the NAND that SPL uses to read U-Boot - CONFIG_SYS_NAND_U_BOOT_DST + CFG_SYS_NAND_U_BOOT_DST Location in memory to load U-Boot to - CONFIG_SYS_NAND_U_BOOT_SIZE + CFG_SYS_NAND_U_BOOT_SIZE Size of image to load - CONFIG_SYS_NAND_U_BOOT_START + CFG_SYS_NAND_U_BOOT_START Entry point in loaded image to jump to CONFIG_SPL_RAM_DEVICE diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index dc414c7d84..5dd90b47f9 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -32,17 +32,17 @@ #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } +#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } #else #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" #endif -#define CONFIG_SYS_NAND_ECCSIZE 0x100 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 0x100 +#define CFG_SYS_NAND_ECCBYTES 3 #endif /* CONFIG_NAND_LPC32XX_SLC */ /* NOR Flash */ diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h index a4cc27e920..38a1a6ea0d 100644 --- a/arch/arm/include/asm/ti-common/davinci_nand.h +++ b/arch/arm/include/asm/ti-common/davinci_nand.h @@ -18,13 +18,13 @@ #define MASK_CLE 0x10 #define MASK_ALE 0x08 -#ifdef CONFIG_SYS_NAND_MASK_CLE +#ifdef CFG_SYS_NAND_MASK_CLE #undef MASK_CLE -#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE +#define MASK_CLE CFG_SYS_NAND_MASK_CLE #endif -#ifdef CONFIG_SYS_NAND_MASK_ALE +#ifdef CFG_SYS_NAND_MASK_ALE #undef MASK_ALE -#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE +#define MASK_ALE CFG_SYS_NAND_MASK_ALE #endif struct davinci_emif_regs { diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index d877be119f..ae1f6fee53 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ #define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 2dcf0cf9c3..803dc7fb71 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -135,7 +135,7 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND) case MTD_DEV_TYPE_NAND: gpmc_regs = gpmc_regs_nand; - base = CONFIG_SYS_NAND_BASE; + base = CFG_SYS_NAND_BASE; size = GPMC_SIZE_16M; break; #endif diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h index e795cd10cb..b0b9a1e99e 100644 --- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h +++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h @@ -1,16 +1,16 @@ #if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM #elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4) -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM +#define CFG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM +#define CFG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM #endif diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index d8f6cfe2b4..8fcf20854e 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -71,16 +71,16 @@ void cpu_init_f (volatile immap_t * im) * has been determined */ -#if defined(CONFIG_SYS_NAND_BR_PRELIM) \ - && defined(CONFIG_SYS_NAND_OR_PRELIM) \ +#if defined(CFG_SYS_NAND_BR_PRELIM) \ + && defined(CFG_SYS_NAND_OR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; #else -#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined +#error CFG_SYS_NAND_BR_PRELIM, CFG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined #endif } diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index a9ea9b558a..d2c6ada668 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -56,10 +56,10 @@ static void at91sam9260ek_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 0c53325ba7..2992353199 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -78,10 +78,10 @@ static void at91sam9261ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 3e232aa87f..b2b7093080 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -69,10 +69,10 @@ static void at91sam9263ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 3af70971f3..2f3a772b81 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -63,10 +63,10 @@ void at91sam9m10g45ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index f05ee322d0..bca7c8d9af 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -64,10 +64,10 @@ static void at91sam9rlek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOD); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */ at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */ diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index b5af35bc7e..817aa2fef7 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -65,9 +65,9 @@ static void at91sam9x5ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCD); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 7035fab878..786de18f8c 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -36,9 +36,9 @@ static void sam9x60ek_nand_hw_init(void) at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index f547ce3cc2..35c74ba9dd 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -100,16 +100,16 @@ static int gurnard_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); + ret = gpio_request(CFG_SYS_NAND_READY_PIN, "nand_rdy"); if (ret) return ret; - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); + ret = gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand_ce"); if (ret) return ret; - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); return 0; } diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index c0a5c518ca..c89ad0bfe3 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -54,12 +54,12 @@ static void usb_a9263_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCDE); /* Configure RDY/BSY */ - gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy"); - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_request(CFG_SYS_NAND_READY_PIN, "NAND ready/busy"); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable"); - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "NAND enable"); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 559fdd2f64..a5d79d8e3e 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -117,11 +117,11 @@ static void ethernut5_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN /* Ready pin is optional. */ - at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CFG_SYS_NAND_READY_PIN, 1); #endif - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index a3eee63e37..98043b020c 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -84,10 +84,10 @@ static void meesc_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 603384ac4f..8951fae32d 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -28,8 +28,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index c0ab1a5fd1..ef46353a36 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -135,13 +135,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index b02f649910..481d3a5d9b 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -84,15 +84,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -113,15 +113,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 799900e9c9..7f32128198 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -47,15 +47,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -76,15 +76,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -355,7 +355,7 @@ void nand_fixup(void) return; /* Change NAND Flash PGS/SPRZ configuration */ - csor = CONFIG_SYS_NAND_CSOR; + csor = CFG_SYS_NAND_CSOR; if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index dfdc9f06ab..de6828673b 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -68,15 +68,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index ae81740dc3..b70c198188 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -73,15 +73,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { @@ -105,15 +105,15 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index debf571482..2dcee79b3a 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -10,7 +10,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index a262d5ca4a..9cd46c9664 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -22,9 +22,9 @@ void board_init_f(ulong bootflag) u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 7992666e93..aa7517a74d 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -68,7 +68,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 6bdfb356ee..8f3f4840e6 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -13,8 +13,8 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index e467c7adc1..2fd8a28743 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -21,9 +21,9 @@ void board_init_f(ulong bootflag) u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#if defined(CFG_SYS_NAND_BR_PRELIM) && defined(CFG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CFG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CFG_SYS_NAND_OR_PRELIM); #endif /* initialize selected port with appropriate baud rate */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 65cedd42a0..85d41327aa 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -67,9 +67,9 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index 04a4239797..850ece0110 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -23,8 +23,8 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 97080eb95e..8fdff7576f 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, +#ifdef CFG_SYS_NAND_BASE + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index 0f6b71a8c2..2f00d80106 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -23,8 +23,8 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 9dcba7933f..8a3d67449c 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -101,13 +101,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index 40fdcf61c0..f97467e844 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -25,8 +25,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 1e501da363..f27faf5d24 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index d3b263f59d..3ff4c773d5 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -25,8 +25,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 542ab1e034..da03aadb17 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -116,13 +116,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 038f60565f..438589604f 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -22,8 +22,8 @@ struct law_entry law_table[] = { /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_NAND_BASE_PHYS + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), #endif }; diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index b927dd8484..059449af1e 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -98,13 +98,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif -#ifdef CONFIG_SYS_NAND_BASE +#ifdef CFG_SYS_NAND_BASE /* * *I*G - NAND * entry 14 and 15 has been used hard coded, they will be disabled * in cpu_init_f, so we use entry 16 for nand. */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif diff --git a/board/gardena/smart-gateway-at91sam/spl.c b/board/gardena/smart-gateway-at91sam/spl.c index 3ab6760df7..2807c4e311 100644 --- a/board/gardena/smart-gateway-at91sam/spl.c +++ b/board/gardena/smart-gateway-at91sam/spl.c @@ -53,10 +53,10 @@ static void at91sam9x5ek_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOCD); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c index aa0f29f44f..b04a8e20dc 100644 --- a/board/keymile/kmcent2/law.c +++ b/board/keymile/kmcent2/law.c @@ -14,7 +14,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), /* other application LAW are not used in u-boot */ diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index dbd3b9b064..095fc7e961 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -76,7 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 9, BOOKE_PAGESZ_4M, 1), /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), /* QRIO */ diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index fe52c7c176..07febe69dc 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -66,10 +66,10 @@ static void pm9261_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */ diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 84926cdc68..76f62ddde9 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -62,10 +62,10 @@ static void pm9263_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 8d5825c7f1..23b55e3e03 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -65,13 +65,13 @@ static void pm9g45_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN /* Configure RDY/BSY */ - gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + gpio_direction_input(CFG_SYS_NAND_READY_PIN); #endif /* Enable NandFlash */ - gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + gpio_direction_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #endif diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index 90fece7f95..d87628097d 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -40,8 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; static void corvus_request_gpio(void) { - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy"); gpio_request(AT91_PIN_PD7, "d0"); gpio_request(AT91_PIN_PD8, "d1"); gpio_request(AT91_PIN_PA12, "d2"); @@ -110,8 +110,8 @@ static void corvus_nand_hw_init(void) at91_periph_clk_enable(ATMEL_ID_PIOA); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); } #if defined(CONFIG_SPL_BUILD) diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index d500a6214d..ce6c877959 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -42,8 +42,8 @@ DECLARE_GLOBAL_DATA_PTR; static void smartweb_request_gpio(void) { - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy"); gpio_request(AT91_PIN_PA26, "ena PHY"); } @@ -72,10 +72,10 @@ static void smartweb_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } static void smartweb_macb_hw_init(void) diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 6c44afb448..47d3f6aef2 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; static void taurus_request_gpio(void) { - gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena"); - gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy"); + gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena"); + gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy"); gpio_request(AT91_PIN_PA25, "ena PHY"); } @@ -73,10 +73,10 @@ static void taurus_nand_hw_init(void) &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); } #if defined(CONFIG_SPL_BUILD) @@ -149,7 +149,7 @@ void spl_board_init(void) } else { puts("erase spi flash sector 0\n"); spi_flash_erase(flash, 0, - CONFIG_SYS_NAND_U_BOOT_SIZE); + CFG_SYS_NAND_U_BOOT_SIZE); } } } diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 9b7ffee83a..b1e38c511e 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -6,7 +6,7 @@ #include -#if defined(CONFIG_SYS_NAND_BASE) +#if defined(CFG_SYS_NAND_BASE) #include #include #include diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 25a38be65e..dc45204fc0 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -26,12 +26,12 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, nand_init(); printf("Loading U-Boot from 0x%08x (size 0x%08x) to 0x%08x\n", - CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, - CONFIG_SYS_NAND_U_BOOT_DST); + CONFIG_SYS_NAND_U_BOOT_OFFS, CFG_SYS_NAND_U_BOOT_SIZE, + CFG_SYS_NAND_U_BOOT_DST); nand_spl_load_image(spl_nand_get_uboot_raw_page(), - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (void *)CFG_SYS_NAND_U_BOOT_DST); spl_set_header_raw_uboot(spl_image); nand_deselect(); diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index 6bb4e17847..69882a76a3 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -53,8 +53,8 @@ c) end executes this code d) this initialize CPU, RAM, ... and copy itself to RAM (this bin must fit in one page, so board_init_f() don;t fit in it ... ) -e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and - starts this image @ CONFIG_SYS_NAND_U_BOOT_START +e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and + starts this image @ CFG_SYS_NAND_U_BOOT_START f) u-boot code steps through board_init_f() and calculates the relocation address and copy itself to it @@ -86,8 +86,8 @@ Relocation with SPL (example for the tx25 booting from NAND Flash): - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads - the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution - @CONFIG_SYS_NAND_U_BOOT_START + the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution + @CFG_SYS_NAND_U_BOOT_START - This u-boot does no RAM init, nor CPU register setup. Just look where it has to copy and relocate itself to this address. If diff --git a/doc/README.omap3 b/doc/README.omap3 index 208714ad65..3a1ac8101d 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -146,11 +146,11 @@ implementation for OMAP3 works for you so the u-boot version should also. When you require the SPL to read with BCH8 there are two more configs to change: - * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in + * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in arch/arm/include/asm/arch-omap3/omap_gpmc.h) - * CONFIG_SYS_NAND_ECCSIZE must be 512 - * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup + * CFG_SYS_NAND_ECCSIZE must be 512 + * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup Acknowledgements ================ diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index a90f32da7a..0b230cf7c7 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -54,7 +54,7 @@ Step-1: Building u-boot for NAND boot CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block - CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CFG_SYS_NAND_ECCPOS ECC map for NAND page CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) Step-2: Flashing NAND via MMC/SD diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 83590a63cc..6ab3f1f42c 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -16,13 +16,13 @@ #include #include -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) /* @@ -155,8 +155,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; uint32_t data_pos = 0; @@ -207,7 +207,7 @@ void nand_init(void) */ mtd = nand_to_mtd(&nand_chip); nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = - (void __iomem *)CONFIG_SYS_NAND_BASE; + (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); if (nand_chip.select_chip) diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index a541af6db4..9fbb0b57cf 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1227,16 +1227,16 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE - | CONFIG_SYS_NAND_MASK_CLE); + IO_ADDR_W &= ~(CFG_SYS_NAND_MASK_ALE + | CFG_SYS_NAND_MASK_CLE); if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE; + IO_ADDR_W |= CFG_SYS_NAND_MASK_CLE; if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE; + IO_ADDR_W |= CFG_SYS_NAND_MASK_ALE; -#ifdef CONFIG_SYS_NAND_ENABLE_PIN - at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN, +#ifdef CFG_SYS_NAND_ENABLE_PIN + at91_set_gpio_value(CFG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE)); #endif this->IO_ADDR_W = (void *) IO_ADDR_W; @@ -1246,10 +1246,10 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd, writeb(cmd, this->IO_ADDR_W); } -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN static int at91_nand_ready(struct mtd_info *mtd) { - return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN); + return at91_get_gpio_value(CFG_SYS_NAND_READY_PIN); } #endif @@ -1314,10 +1314,10 @@ static int nand_is_bad_block(int block) } #ifdef CONFIG_SPL_NAND_ECC -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) static int nand_read_page(int block, int page, void *dst) { @@ -1325,8 +1325,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; int i; uint8_t *p = dst; @@ -1415,7 +1415,7 @@ int board_nand_init(struct nand_chip *nand) nand->read_buf = nand_read_buf; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #else nand->dev_ready = at91_nand_wait_ready; @@ -1439,8 +1439,8 @@ void nand_init(void) mtd = nand_to_mtd(&nand_chip); mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE; mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE; - nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; - nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand_chip.IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE; + nand_chip.IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); #ifdef CONFIG_SPL_NAND_ECC @@ -1464,11 +1464,11 @@ void nand_deselect(void) #else -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; +static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST; int atmel_nand_chip_init(int devnum, ulong base_addr) { @@ -1487,7 +1487,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91_nand_hwcontrol; -#ifdef CONFIG_SYS_NAND_READY_PIN +#ifdef CFG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #endif nand->chip_delay = 75; diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 54aed13638..e4e144bd7c 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -170,7 +170,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) u_int32_t ecc = 0; ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ - CONFIG_SYS_NAND_CS - 2])); + CFG_SYS_NAND_CS - 2])); return ecc; } @@ -183,8 +183,8 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) nand_davinci_readecc(mtd); val = __raw_readl(&davinci_emif_regs->nandfcr); - val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); - val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_1BIT_ECC_START(CFG_SYS_NAND_CS); __raw_writel(val, &davinci_emif_regs->nandfcr); } @@ -486,8 +486,8 @@ static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) */ val = __raw_readl(&davinci_emif_regs->nandfcr); val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; - val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); - val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_NAND_ENABLE(CFG_SYS_NAND_CS); + val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CFG_SYS_NAND_CS); val |= DAVINCI_NANDFCR_4BIT_ECC_START; __raw_writel(val, &davinci_emif_regs->nandfcr); break; @@ -794,8 +794,8 @@ static int davinci_nand_probe(struct udevice *dev) struct mtd_info *mtd = nand_to_mtd(nand); int ret; - nand->IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE; - nand->IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; + nand->IO_ADDR_R = (void __iomem *)CFG_SYS_NAND_BASE; + nand->IO_ADDR_W = (void __iomem *)CFG_SYS_NAND_BASE; davinci_nand_init(nand); diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index f72142817e..690279c997 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -25,9 +25,9 @@ #define BANK(x) ((x) << 24) static void __iomem *denali_flash_mem = - (void __iomem *)CONFIG_SYS_NAND_DATA_BASE; + (void __iomem *)CFG_SYS_NAND_DATA_BASE; static void __iomem *denali_flash_reg = - (void __iomem *)CONFIG_SYS_NAND_REGS_BASE; + (void __iomem *)CFG_SYS_NAND_REGS_BASE; static const int flash_bank; static int page_size, oob_size, pages_per_block; diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 4f0acd7c89..7853c3f74e 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -819,12 +819,12 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) #ifndef CONFIG_NAND_FSL_ELBC_DT -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] = - CONFIG_SYS_NAND_BASE_LIST; + CFG_SYS_NAND_BASE_LIST; void board_nand_init(void) { diff --git a/drivers/mtd/nand/raw/fsl_elbc_spl.c b/drivers/mtd/nand/raw/fsl_elbc_spl.c index e55b40f8f1..26aaab08e8 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_spl.c +++ b/drivers/mtd/nand/raw/fsl_elbc_spl.c @@ -46,8 +46,8 @@ static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) #endif { fsl_lbc_t *regs = LBC_BASE_ADDR; - uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; - const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; + uchar *buf = (uchar *)CFG_SYS_NAND_BASE; + const int large = CFG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; const int block_shift = large ? 17 : 14; const int block_size = 1 << block_shift; const int page_size = large ? 2048 : 512; @@ -143,8 +143,8 @@ void nand_boot(void) * Load U-Boot image from NAND into RAM */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (void *)CFG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -161,13 +161,13 @@ void nand_boot(void) * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); + flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE); #endif puts("transfering control\n"); /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index e5ff937872..59de325640 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -1053,12 +1053,12 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) return 0; } -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] = - CONFIG_SYS_NAND_BASE_LIST; + CFG_SYS_NAND_BASE_LIST; void board_nand_init(void) { diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 4d11922a65..7d4b77dd11 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -110,7 +110,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR; struct fsl_ifc_runtime *ifc = NULL; - uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; + uchar *buf = (uchar *)CFG_SYS_NAND_BASE; int page_size; int port_size; int pages_per_blk; @@ -129,8 +129,8 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) ifc = runtime_regs_address(); /* Get NAND Flash configuration */ - csor = CONFIG_SYS_NAND_CSOR; - cspr = CONFIG_SYS_NAND_CSPR; + csor = CFG_SYS_NAND_CSOR; + cspr = CFG_SYS_NAND_CSPR; port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; @@ -250,8 +250,8 @@ void nand_boot(void) * Load U-Boot image from NAND into RAM */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CFG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -270,7 +270,7 @@ void nand_boot(void) * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); + flush_cache(CFG_SYS_NAND_U_BOOT_DST, CFG_SYS_NAND_U_BOOT_SIZE); #endif #ifdef CONFIG_CHAIN_OF_TRUST @@ -279,11 +279,11 @@ void nand_boot(void) * calculate U-boot header address using U-boot header size. */ #define CONFIG_U_BOOT_HDR_ADDR \ - ((CONFIG_SYS_NAND_U_BOOT_START + \ - CONFIG_SYS_NAND_U_BOOT_SIZE) - \ + ((CFG_SYS_NAND_U_BOOT_START + \ + CFG_SYS_NAND_U_BOOT_SIZE) - \ CONFIG_U_BOOT_HDR_SIZE) spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, - CONFIG_SYS_NAND_U_BOOT_START); + CFG_SYS_NAND_U_BOOT_START); /* * In case of failure in validation, spl_validate_uboot would * not return back in case of Production environment with ITS=1. @@ -293,7 +293,7 @@ void nand_boot(void) */ #endif - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; uboot(); } diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index a92c6252a5..d795864949 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -427,7 +427,7 @@ int fsmc_nand_init(struct nand_chip *nand) nand->ecc.hwctl = fsmc_enable_hwecc; nand->cmd_ctrl = fsmc_nand_hwcontrol; nand->IO_ADDR_R = nand->IO_ADDR_W = - (void __iomem *)CONFIG_SYS_NAND_BASE; + (void __iomem *)CFG_SYS_NAND_BASE; nand->badblockbits = 7; mtd = nand_to_mtd(nand); diff --git a/drivers/mtd/nand/raw/kmeter1_nand.c b/drivers/mtd/nand/raw/kmeter1_nand.c index b838164bf2..84564b2f70 100644 --- a/drivers/mtd/nand/raw/kmeter1_nand.c +++ b/drivers/mtd/nand/raw/kmeter1_nand.c @@ -10,8 +10,8 @@ #include #include -#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000) -#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000) +#define CONFIG_NAND_MODE_REG (void *)(CFG_SYS_NAND_BASE + 0x20000) +#define CONFIG_NAND_DATA_REG (void *)(CFG_SYS_NAND_BASE + 0x30000) #define read_mode() in_8(CONFIG_NAND_MODE_REG) #define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 3d6cb1dc63..f4f1b22f5e 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -84,7 +84,7 @@ static struct nand_ecclayout lpc32xx_nand_oob_16 = { }; #if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD) -#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) +#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE) /* * DMA Descriptors @@ -187,7 +187,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip, DMAC_CHAN_DEST_AHB1; /* CTRL descriptor entry for reading/writing Data */ - ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) | + ctrl = (CFG_SYS_NAND_ECCSIZE / 4) | DMAC_CHAN_SRC_BURST_4 | DMAC_CHAN_DEST_BURST_4 | DMAC_CHAN_SRC_WIDTH_32 | @@ -241,7 +241,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip, * 2. X'fer 64 bytes of Spare area from Flash to Memory. */ - for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) { + for (i = 0; i < size/CFG_SYS_NAND_ECCSIZE; i++) { dmalist_cur = &dmalist[i * 2]; dmalist_cur_ecc = &dmalist[(i * 2) + 1]; @@ -337,9 +337,9 @@ static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf, static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count) { int i; - for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES); - i += CONFIG_SYS_NAND_ECCBYTES) { - u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES]; + for (i = 0; i < (count * CFG_SYS_NAND_ECCBYTES); + i += CFG_SYS_NAND_ECCBYTES) { + u32 ce = ecc[i / CFG_SYS_NAND_ECCBYTES]; ce = ~(ce << 2) & 0xFFFFFF; spare[i+2] = (u8)(ce & 0xFF); ce >>= 8; spare[i+1] = (u8)(ce & 0xFF); ce >>= 8; @@ -386,9 +386,9 @@ int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat, u16 data_offset = 0; for (i = 0 ; i < ECCSTEPS ; i++) { - r += CONFIG_SYS_NAND_ECCBYTES; - c += CONFIG_SYS_NAND_ECCBYTES; - data_offset += CONFIG_SYS_NAND_ECCSIZE; + r += CFG_SYS_NAND_ECCBYTES; + c += CFG_SYS_NAND_ECCBYTES; + data_offset += CFG_SYS_NAND_ECCSIZE; ret1 = nand_correct_data(mtd, dat + data_offset, r, c); if (ret1 < 0) @@ -568,8 +568,8 @@ int board_nand_init(struct nand_chip *lpc32xx_chip) * These values are predefined * for both small and large page NAND flash devices. */ - lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; + lpc32xx_chip->ecc.size = CFG_SYS_NAND_ECCSIZE; + lpc32xx_chip->ecc.bytes = CFG_SYS_NAND_ECCBYTES; lpc32xx_chip->ecc.strength = 1; if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 2b8a132a5f..fa903e324c 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -50,7 +50,7 @@ static struct mxc_nand_host *host = &mxc_host; /* OOB placement block for use with hardware ecc generation */ #if defined(MXC_NFC_V1) -#ifndef CONFIG_SYS_NAND_LARGEPAGE +#ifndef CFG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 5, .eccpos = {6, 7, 8, 9, 10}, @@ -69,7 +69,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = { }; #endif #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) -#ifndef CONFIG_SYS_NAND_LARGEPAGE +#ifndef CFG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 9, .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15}, @@ -1219,7 +1219,7 @@ int board_nand_init(struct nand_chip *this) if (is_16bit_nand()) this->options |= NAND_BUSWIDTH_16; -#ifdef CONFIG_SYS_NAND_LARGEPAGE +#ifdef CFG_SYS_NAND_LARGEPAGE host->pagesize_2k = 1; this->ecc.layout = &nand_hw_eccoob2k; #else diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index 0fea307ea4..309e75d01e 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -332,14 +332,14 @@ __used void nand_boot(void) __attribute__((noreturn)) void (*uboot)(void); /* - * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must + * CONFIG_SYS_NAND_U_BOOT_OFFS and CFG_SYS_NAND_U_BOOT_SIZE must * be aligned to full pages */ if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { + CFG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CFG_SYS_NAND_U_BOOT_DST)) { /* Copy from NAND successful, start U-Boot */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; uboot(); } else { /* Unrecoverable error when copying from NAND */ diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 14bca12024..eacd99c4e2 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -11,8 +11,8 @@ #include #include -#ifndef CONFIG_SYS_NAND_BASE_LIST -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#ifndef CFG_SYS_NAND_BASE_LIST +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif int nand_curr_device = -1; @@ -21,7 +21,7 @@ static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE]; #if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; -static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST; +static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST; #endif static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8]; diff --git a/drivers/mtd/nand/raw/nand_spl_load.c b/drivers/mtd/nand/raw/nand_spl_load.c index ecd373e054..7ac9bf4d12 100644 --- a/drivers/mtd/nand/raw/nand_spl_load.c +++ b/drivers/mtd/nand/raw/nand_spl_load.c @@ -20,8 +20,8 @@ void nand_boot(void) * Load U-Boot image from NAND into RAM */ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_U_BOOT_SIZE, - (void *)CONFIG_SYS_NAND_U_BOOT_DST); + CFG_SYS_NAND_U_BOOT_SIZE, + (void *)CFG_SYS_NAND_U_BOOT_DST); #ifdef CONFIG_NAND_ENV_DST nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -36,6 +36,6 @@ void nand_boot(void) /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot = (void *)CFG_SYS_NAND_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index 727861c8f7..2f3af9edd4 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -10,13 +10,13 @@ #include #include -static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; +static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; static struct mtd_info *mtd; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ - CONFIG_SYS_NAND_ECCSIZE) -#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES) + CFG_SYS_NAND_ECCSIZE) +#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) @@ -139,8 +139,8 @@ static int nand_read_page(int block, int page, uchar *dst) u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; @@ -170,8 +170,8 @@ static int nand_read_page(int block, int page, void *dst) u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; int i; - int eccsize = CONFIG_SYS_NAND_ECCSIZE; - int eccbytes = CONFIG_SYS_NAND_ECCBYTES; + int eccsize = CFG_SYS_NAND_ECCSIZE; + int eccbytes = CFG_SYS_NAND_ECCBYTES; int eccsteps = ECCSTEPS; uint8_t *p = dst; @@ -212,7 +212,7 @@ void nand_init(void) */ mtd = nand_to_mtd(&nand_chip); nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = - (void __iomem *)CONFIG_SYS_NAND_BASE; + (void __iomem *)CFG_SYS_NAND_BASE; board_nand_init(&nand_chip); #ifdef CONFIG_SPL_NAND_SOFTECC diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 8b9ff4de18..b7d261d8ce 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -407,7 +407,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le cnt = PREFETCH_STATUS_FIFO_CNT(cnt); for (i = 0; i < cnt / 4; i++) { - *buf++ = readl(CONFIG_SYS_NAND_BASE); + *buf++ = readl(CFG_SYS_NAND_BASE); len -= 4; } } while (len); diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index 13fd631cb4..d4b40e810f 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -812,7 +812,7 @@ void board_nand_init(void) return; } - nfc->regs = (void __iomem *)CONFIG_SYS_NAND_BASE; + nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE; err = vf610_nfc_nand_init(nfc, 0); if (err) printf("VF610 NAND init failed (err %d)\n", err); diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index a39fe5f28a..fc21af56ec 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -93,8 +93,8 @@ #endif #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f0734712ea..f7c09a2333 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -94,8 +94,8 @@ # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index b0809332bb..a5518d3d50 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -82,6 +82,6 @@ /* Ethernet configuration part */ /* NAND configuration part */ -#define CONFIG_SYS_NAND_BASE 0x0C000000 +#define CFG_SYS_NAND_BASE 0x0C000000 #endif /* __CONFIG_H */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index bb93c28744..c4cde1cc51 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -141,7 +141,7 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 +#define CFG_SYS_NAND_BASE 0xE0600000 /* Vitesse 7385 */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 3448766d8e..3288969ce8 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -36,18 +36,18 @@ #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) +#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) +#define CFG_SYS_NAND_U_BOOT_START 0x00200000 #else #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10) +#define CFG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CFG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000 +#define CFG_SYS_NAND_U_BOOT_START 0xD0000000 #endif #endif #endif @@ -167,23 +167,23 @@ extern unsigned long get_sdram_size(void); /* CFI for NOR Flash */ /* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif #define CONFIG_MTD_PARTITION -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) #if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ @@ -192,7 +192,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -201,49 +201,49 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ +#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ FTIM0_NAND_TWCHT(0x04) | \ FTIM0_NAND_TWH(0x05) -#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ +#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ FTIM1_NAND_TWBE(0x1d) | \ FTIM1_NAND_TRR(0x07) | \ FTIM1_NAND_TRP(0x0c) -#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ +#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ FTIM2_NAND_TREH(0x05) | \ FTIM2_NAND_TWHRE(0x0f) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) +#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) #elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 #endif /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR @@ -259,13 +259,13 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif /* CPLD on IFC */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 08c1bccb2b..b9311fc5e4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -111,22 +111,22 @@ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 +#define CFG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE} /* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | (2< /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* APBH DMA is required for NAND support */ /* Ethernet */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index f0fbbe2870..9061eba668 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -22,9 +22,9 @@ #endif /* NAND support */ -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index d7e181b942..afe8badd65 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -122,8 +122,8 @@ #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ -/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ -#define CONFIG_SYS_NAND_BASE -1 +/* used to initialize CFG_SYS_NAND_BASE_LIST which is unused */ +#define CFG_SYS_NAND_BASE -1 #endif /* USB Configs */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 5c7a9f2e69..f9bf849ae9 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -166,7 +166,7 @@ #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 #endif /* USB Configs */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 3e7c0c0d88..9d44e6723e 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -37,13 +37,13 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8 #endif /* DFU class support */ @@ -53,13 +53,13 @@ /* Defines for SPL */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ +#define CFG_SYS_NAND_ECCSIZE 256 +#define CFG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 5a5c65da16..f8ba4e8281 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -107,21 +107,21 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_ECCPOS { \ +#define CFG_SYS_NAND_CS 3 +#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CFG_SYS_NAND_MASK_CLE 0x10 +#define CFG_SYS_NAND_MASK_ALE 0x8 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x40000 +#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_ECCPOS { \ 24, 25, 26, 27, 28, \ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 10 #endif #ifdef CONFIG_MTD_NOR_FLASH diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 42366123cb..5244b9cf5c 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -35,8 +35,8 @@ /* * NAND controller */ -#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE SLC_NAND_BASE +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* * NAND chip timings @@ -79,10 +79,10 @@ */ /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE /* See common/spl/spl.c spl_set_header_raw_uboot() */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index d45115bdf6..46410595c2 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -100,12 +100,12 @@ /* Defines for SPL */ /* NAND boot config */ -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 +#define CFG_SYS_NAND_U_BOOT_SIZE 0x200000 #endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6cf716e293..93201be485 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -75,15 +75,15 @@ #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* !CONFIG_MTD_RAW_NAND */ /* Parallel NOR Support */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 75322a3732..6cae663cb8 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -14,10 +14,10 @@ #include "siemens-am33x-common.h" /* NAND specific changes for etamin due to different page size */ -#undef CONFIG_SYS_NAND_ECCPOS +#undef CFG_SYS_NAND_ECCPOS #define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ @@ -40,14 +40,14 @@ 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ } -#undef CONFIG_SYS_NAND_ECCSIZE -#undef CONFIG_SYS_NAND_ECCBYTES -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 +#undef CFG_SYS_NAND_ECCSIZE +#undef CFG_SYS_NAND_ECCBYTES +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ - CONFIG_SYS_NAND_BASE2} +#define CFG_SYS_NAND_BASE2 (0x18000000) /* physical address */ +#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE, \ + CFG_SYS_NAND_BASE2} #define DDR_PLL_FREQ 303 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index a18920d3f0..f19e12d909 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -37,12 +37,12 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CFG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) +#define CFG_SYS_NAND_MASK_CLE (1 << 22) +#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) #endif /* JFFS2 */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 3d62efb38f..ba098316e0 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -22,13 +22,13 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* NAND flash */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CFG_SYS_NAND_MASK_ALE BIT(21) /* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CFG_SYS_NAND_MASK_CLE BIT(22) +#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 /* SPL */ @@ -37,8 +37,8 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE #endif diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 232f7868cc..974dff8f6f 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -96,7 +96,7 @@ * NAND */ #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_NAND_BASE 0xd8000000 +#define CFG_SYS_NAND_BASE 0xd8000000 #define CONFIG_MXC_NAND_HWECC /* diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index f52367cc1a..e430efad42 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -126,8 +126,8 @@ /* NAND */ #ifdef CONFIG_NAND_MXS -# define CONFIG_SYS_NAND_BASE 0x40000000 -# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +# define CFG_SYS_NAND_BASE 0x40000000 +# define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* MTD device */ #endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 008fc079a6..7760c8c418 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -116,8 +116,8 @@ /* Environment organization */ /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 46a96f1f82..d42eb750d0 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -72,6 +72,6 @@ /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index a2323bd671..a768ff3551 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -44,6 +44,6 @@ /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif /* __IMX8MN_BSH_SMM_S2_H */ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 5be46090a1..8f2b474817 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -166,7 +166,7 @@ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CFG_SYS_NAND_BASE 0x20000000 #endif /* CONFIG_NAND_MXS */ #endif /* __IMX8MP_RSB3720_H */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 181ed1b8fa..a658cbc07c 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -59,7 +59,7 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE #endif /* diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 0613b77e96..d883b188ce 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -77,17 +77,17 @@ #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 /* NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x68000000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x68000000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_NAND | \ CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ | CSOR_NAND_ECC_DEC_EN \ | CSOR_NAND_ECC_MODE_4 \ | CSOR_NAND_RAL_3 \ @@ -97,29 +97,29 @@ | CSOR_NAND_TRHZ_40 \ | CSOR_NAND_BCTLD) -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ FTIM0_NAND_TWP(0x8) | \ FTIM0_NAND_TWCHT(0x3) | \ FTIM0_NAND_TWH(0x5)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ FTIM1_NAND_TWBE(0x1e) | \ FTIM1_NAND_TRR(0x6) | \ FTIM1_NAND_TRP(0x8)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ FTIM2_NAND_TREH(0x5) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) +#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO FPGA Definitions */ #define CONFIG_SYS_QRIO_BASE 0x70000000 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 2e1459e3e4..51ee686553 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -231,18 +231,18 @@ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC CS1*/ -#define CONFIG_SYS_NAND_BASE 0xfa000000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#define CFG_SYS_NAND_BASE 0xfa000000 +#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE) -#define CONFIG_SYS_NAND_CSPR_EXT (0x0f) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ +#define CFG_SYS_NAND_CSPR_EXT (0x0f) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE) | \ CSPR_PORT_SIZE_8 | /* Port Size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NAND | /* MSEL = NAND */\ CSPR_V) /* valid */ -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) /* 64kB */ -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN | /* ECC encoder on */ \ CSOR_NAND_ECC_DEC_EN | /* ECC decoder on */ \ CSOR_NAND_ECC_MODE_4 | /* 4-bit ECC */ \ CSOR_NAND_RAL_3 | /* RAL = 3Bytes */ \ @@ -253,30 +253,30 @@ CSOR_NAND_BCTLD) /**/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ FTIM0_NAND_TWP(0x8) | \ FTIM0_NAND_TWCHT(0x3) | \ FTIM0_NAND_TWH(0x5)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ FTIM1_NAND_TWBE(0x1e) | \ FTIM1_NAND_TRR(0x6) | \ FTIM1_NAND_TRP(0x8)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ FTIM2_NAND_TREH(0x5) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) +#define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 /* More NAND Flash Params */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO on IFC CS2 */ #define CONFIG_SYS_QRIO_BASE 0xfb000000 diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d6b60d8139..b954029874 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -12,7 +12,7 @@ #define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ +#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 926c85805b..7d89b53895 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,9 +11,9 @@ #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif @@ -70,17 +70,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -88,20 +88,20 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif /* @@ -156,14 +156,14 @@ #endif #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK @@ -205,14 +205,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 8c19468141..47367845a0 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -59,8 +59,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index d207e475fc..21263705c8 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -79,17 +79,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -97,25 +97,25 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif #if defined(CONFIG_TFABOOT) || \ @@ -188,14 +188,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -206,14 +206,14 @@ #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK @@ -255,14 +255,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 206de7e138..51667f2025 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -51,16 +51,16 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -68,24 +68,24 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif /* @@ -126,24 +126,24 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR @@ -163,14 +163,14 @@ #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7e1a724387..07ec2c9563 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -59,8 +59,8 @@ /* NAND SPL */ #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE #endif /* GPIO */ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 48408f2858..8402eac418 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -14,16 +14,16 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -31,31 +31,31 @@ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 037d462b5d..d51209c60f 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -95,17 +95,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -113,25 +113,25 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif #if defined(CONFIG_TFABOOT) || \ @@ -204,14 +204,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -222,14 +222,14 @@ #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK @@ -271,14 +271,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 769349336a..0df6891598 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -19,16 +19,16 @@ #define CONFIG_SYS_UBOOT_BASE 0x40100000 #endif -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -36,20 +36,20 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE /* @@ -78,14 +78,14 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 73e4ac3e3d..dec661d6b1 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -88,8 +88,8 @@ unsigned long long get_qixis_addr(void); #define QIXIS_BASE_PHYS_EARLY 0xC000000 -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 +#define CFG_SYS_NAND_BASE 0x530000000ULL +#define CFG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 3a2fba6b04..ae452075ac 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -69,14 +69,14 @@ #endif #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -85,20 +85,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 @@ -174,14 +174,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL @@ -193,14 +193,14 @@ #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL @@ -230,14 +230,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index e2ae3026c2..2ca1384c23 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -53,14 +53,14 @@ #endif #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -69,20 +69,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 @@ -132,14 +132,14 @@ #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 53a3af1baa..d8997208e9 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -81,8 +81,8 @@ unsigned long long get_qixis_addr(void); #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 +#define CFG_SYS_NAND_BASE 0x530000000ULL +#define CFG_SYS_NAND_BASE_PHYS 0x30000000 /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ @@ -129,8 +129,8 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_U_BOOT_DST 0x80400000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST #endif #include diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index e6019870d8..d9e11cc191 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -70,14 +70,14 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -86,20 +86,20 @@ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x07) | \ FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0x0e) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ FTIM2_NAND_TREH(0x0a) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 @@ -163,16 +163,16 @@ #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) +#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT @@ -194,14 +194,14 @@ #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 382d516c08..086c46902c 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -67,14 +67,14 @@ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ | CSPR_MSEL_NAND /* MSEL = NAND */ \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ @@ -83,20 +83,20 @@ | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ /* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ FTIM0_NAND_TWP(0x30) | \ FTIM0_NAND_TWCHT(0x0e) | \ FTIM0_NAND_TWH(0x14)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ FTIM1_NAND_TWBE(0xab) | \ FTIM1_NAND_TRR(0x1c) | \ FTIM1_NAND_TRP(0x30)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ FTIM2_NAND_TREH(0x14) | \ FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 @@ -146,16 +146,16 @@ #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) +#define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY @@ -166,14 +166,14 @@ #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 3652241917..1734f323f9 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -44,10 +44,10 @@ * NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE +#define CFG_SYS_NAND_LARGEPAGE #define CONFIG_MXC_NAND_HWECC #endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 30267e29a1..cd3910ee4b 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -52,11 +52,11 @@ /* NAND flash */ #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) +# define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ +# define CFG_SYS_NAND_MASK_ALE (1 << 21) +# define CFG_SYS_NAND_MASK_CLE (1 << 22) +# define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) +# define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) #endif /* hw-controller addresses */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 61570b7af5..8176566f3f 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -36,7 +36,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 0d9764e3b4..a41e428eb8 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -86,7 +86,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 2a97d2fac4..af17658381 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -93,7 +93,7 @@ */ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* DMA stuff, needed for GPMI/MXS NAND support */ #endif diff --git a/include/configs/mxs.h b/include/configs/mxs.h index e8610386f0..9d6b3d4048 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -83,7 +83,7 @@ /* NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BASE 0x60000000 +#define CFG_SYS_NAND_BASE 0x60000000 #endif /* OCOTP */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index a777305ec7..e18d16cc99 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -30,7 +30,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index ccc203f5f2..2a52885082 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -31,7 +31,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index d46ca337d5..0890f51eff 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -21,10 +21,10 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 /* NAND: SPL falcon mode configs */ #endif /* CONFIG_MTD_RAW_NAND */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 77629d7fc1..6eec955e88 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -26,10 +26,10 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 3 #endif /* CONFIG_MTD_RAW_NAND */ #define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 97f47ea5b7..10f6ba6360 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -70,14 +70,14 @@ #define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) /* NAND config */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ +#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ 18, 19, 20, 21, 22, 23, 24, 25, \ 26, 27, 28, 29, 30, 31, 32, 33, \ 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 14 #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 7c0bdcbb11..6001037ae8 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -17,15 +17,15 @@ /* Board NAND Info. */ #ifdef CONFIG_MTD_RAW_NAND /* NAND devices */ -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ +#define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 13, 14, 16, 17, 18, 19, 20, 21, 22, \ 23, 24, 25, 26, 27, 28, 30, 31, 32, \ 33, 34, 35, 36, 37, 38, 39, 40, 41, \ 42, 44, 45, 46, 47, 48, 49, 50, 51, \ 52, 53, 54, 55, 56} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 13 #endif /* Environment information */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index d9f70c7532..81ca68de9b 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -105,21 +105,21 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 +#define CFG_SYS_NAND_CS 3 +#define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE +#define CFG_SYS_NAND_MASK_CLE 0x10 +#define CFG_SYS_NAND_MASK_ALE 0x8 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_ECCPOS { \ +#define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K +#define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 +#define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST +#define CFG_SYS_NAND_ECCPOS { \ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 +#define CFG_SYS_NAND_ECCSIZE 512 +#define CFG_SYS_NAND_ECCBYTES 10 #endif /* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 778bf5112a..38f360b53c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -98,13 +98,13 @@ #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) +#define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) +#define CFG_SYS_NAND_U_BOOT_DST (0x11000000) +#define CFG_SYS_NAND_U_BOOT_START (0x11000000) #elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10) +#define CFG_SYS_NAND_U_BOOT_DST 0xf8f80000 +#define CFG_SYS_NAND_U_BOOT_START 0xf8f80000 #endif /* not CONFIG_TPL_BUILD */ #endif @@ -207,22 +207,22 @@ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CFG_SYS_NAND_BASE 0xff800000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull +#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull #else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | (2< Date: Wed, 16 Nov 2022 13:10:26 -0500 Subject: [PATCH 012/424] powerpc: Rename CONFIG_NS16550_MIN_FUNCTIONS This symbol is specific to the PowerPC SPL implementation, so rename this to reflect that it's in SPL and used / tested there, so that we can then safely migrate it to Kconfig. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 2 +- drivers/serial/ns16550.c | 8 ++++---- drivers/serial/serial_ns16550.c | 4 ++-- include/configs/P1010RDB.h | 4 +--- include/configs/p1_p2_rdb_pc.h | 4 +--- scripts/config_whitelist.txt | 2 +- 6 files changed, 10 insertions(+), 14 deletions(-) diff --git a/README b/README index f540757627..f71832b689 100644 --- a/README +++ b/README @@ -1619,7 +1619,7 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. -- CONFIG_NS16550_MIN_FUNCTIONS: +- CONFIG_SPL_NS16550_MIN_FUNCTIONS: Define this if you desire to only have use of the NS16550_init and NS16550_putc functions for the serial driver located at drivers/serial/ns16550.c. This option is useful for saving diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 7592979cab..5a693d2f02 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -272,7 +272,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor) #endif } -#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) { serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); @@ -281,7 +281,7 @@ void ns16550_reinit(struct ns16550 *com_port, int baud_divisor) serial_out(ns16550_getfcr(com_port), &com_port->fcr); ns16550_setbrg(com_port, baud_divisor); } -#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ void ns16550_putc(struct ns16550 *com_port, char c) { @@ -299,7 +299,7 @@ void ns16550_putc(struct ns16550 *com_port, char c) schedule(); } -#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) char ns16550_getc(struct ns16550 *com_port) { while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { @@ -317,7 +317,7 @@ int ns16550_tstc(struct ns16550 *com_port) return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; } -#endif /* CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ #ifdef CONFIG_DEBUG_UART_NS16550 diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 97b6a4ff40..76aa1e5afb 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -11,7 +11,7 @@ #include #include -#ifndef CONFIG_NS16550_MIN_FUNCTIONS +#if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) DECLARE_GLOBAL_DATA_PTR; @@ -251,4 +251,4 @@ void ns16550_serial_initialize(void) #endif } -#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */ +#endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 154bf584f2..9afd834f9f 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -325,9 +325,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 38f360b53c..838c62c671 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -322,9 +322,7 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif +#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c0f55e41a5..3e717bb72a 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -186,7 +186,6 @@ CONFIG_NETMASK CONFIG_NEVER_ASSERT_ODT_TO_CPU CONFIG_NOBQFMAN CONFIG_NORBOOT -CONFIG_NS16550_MIN_FUNCTIONS CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN CONFIG_OTHBOOTARGS @@ -278,6 +277,7 @@ CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET +CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET From 9591b63531fa5a34698ee7bb3800af6c4ea6ba2f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 09:39:03 -0500 Subject: [PATCH 013/424] Convert CONFIG_SYS_NS16550_MEM32 et al to Kconfig This converts the following to Kconfig: CONFIG_SPL_NS16550_MIN_FUNCTIONS CONFIG_SYS_NS16550_MEM32 CONFIG_SYS_NS16550_PORT_MAPPED CONFIG_SYS_NS16550_REG_SIZE CONFIG_SYS_NS16550_SERIAL To do this we also introduce CONFIG_SPL_SYS_NS16550_SERIAL so that platforms can enable the legacy driver here for SPL. Signed-off-by: Tom Rini --- README | 7 --- arch/arm/include/asm/arch-bcmcygnus/configs.h | 4 -- arch/arm/include/asm/arch-bcmnsp/configs.h | 3 -- configs/10m50_defconfig | 1 + configs/MPC837XERDB_defconfig | 2 +- configs/MPC8548CDS_36BIT_defconfig | 2 +- configs/MPC8548CDS_defconfig | 2 +- configs/MPC8548CDS_legacy_defconfig | 2 +- configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_defconfig | 2 +- configs/P1010RDB-PA_SDCARD_defconfig | 2 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 +- configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_defconfig | 2 +- configs/P1010RDB-PB_SDCARD_defconfig | 2 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_36BIT_defconfig | 2 +- configs/P1020RDB-PC_NAND_defconfig | 3 +- configs/P1020RDB-PC_SDCARD_defconfig | 2 +- configs/P1020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PC_defconfig | 2 +- configs/P1020RDB-PD_NAND_defconfig | 3 +- configs/P1020RDB-PD_SDCARD_defconfig | 2 +- configs/P1020RDB-PD_SPIFLASH_defconfig | 2 +- configs/P1020RDB-PD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 3 +- configs/P2020RDB-PC_SDCARD_defconfig | 2 +- configs/P2020RDB-PC_SPIFLASH_defconfig | 2 +- configs/P2020RDB-PC_defconfig | 2 +- configs/P2041RDB_NAND_defconfig | 2 +- configs/P2041RDB_SDCARD_defconfig | 2 +- configs/P2041RDB_SPIFLASH_defconfig | 2 +- configs/P2041RDB_defconfig | 2 +- configs/SBx81LIFKW_defconfig | 3 +- configs/SBx81LIFXCAT_defconfig | 3 +- configs/T1024RDB_NAND_defconfig | 2 +- configs/T1024RDB_SDCARD_defconfig | 2 +- configs/T1024RDB_SPIFLASH_defconfig | 2 +- configs/T1024RDB_defconfig | 2 +- configs/T1042D4RDB_NAND_defconfig | 2 +- configs/T1042D4RDB_SDCARD_defconfig | 2 +- configs/T1042D4RDB_SPIFLASH_defconfig | 2 +- configs/T1042D4RDB_defconfig | 2 +- configs/T2080QDS_NAND_defconfig | 2 +- configs/T2080QDS_SDCARD_defconfig | 2 +- configs/T2080QDS_SECURE_BOOT_defconfig | 2 +- configs/T2080QDS_SPIFLASH_defconfig | 2 +- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 2 +- configs/T2080RDB_SDCARD_defconfig | 2 +- configs/T2080RDB_SPIFLASH_defconfig | 2 +- configs/T2080RDB_defconfig | 2 +- configs/T2080RDB_revD_NAND_defconfig | 2 +- configs/T2080RDB_revD_SDCARD_defconfig | 2 +- configs/T2080RDB_revD_SPIFLASH_defconfig | 2 +- configs/T2080RDB_revD_defconfig | 2 +- configs/T4240RDB_SDCARD_defconfig | 2 +- configs/T4240RDB_defconfig | 2 +- configs/am43xx_evm_qspiboot_defconfig | 2 +- configs/am43xx_hs_evm_qspi_defconfig | 2 +- configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + configs/bayleybay_defconfig | 1 + configs/bcm7260_defconfig | 3 +- configs/bcm7445_defconfig | 3 +- configs/cherryhill_defconfig | 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_bob_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_kevin_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebook_samus_tpl_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/d2net_v2_defconfig | 3 +- configs/dns325_defconfig | 3 +- configs/dockstar_defconfig | 3 +- configs/dreamplug_defconfig | 3 +- configs/ds109_defconfig | 3 +- configs/eaidk-610-rk3399_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/elgin-rv1108_defconfig | 1 + configs/evb-px30_defconfig | 1 + configs/evb-px5_defconfig | 1 + configs/evb-rk3036_defconfig | 1 + configs/evb-rk3128_defconfig | 1 + configs/evb-rk3229_defconfig | 1 + configs/evb-rk3288_defconfig | 1 + configs/evb-rk3308_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + configs/evb-rk3399_defconfig | 1 + configs/evb-rk3568_defconfig | 1 + configs/evb-rv1108_defconfig | 1 + configs/ficus-rk3399_defconfig | 1 + configs/firefly-px30_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/firefly-rk3399_defconfig | 1 + configs/geekbox_defconfig | 1 + configs/goflexhome_defconfig | 3 +- configs/guruplug_defconfig | 3 +- configs/hsdk_4xd_defconfig | 1 + configs/hsdk_defconfig | 1 + configs/ib62x0_defconfig | 3 +- configs/iconnect_defconfig | 3 +- configs/inetspace_v2_defconfig | 3 +- configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/khadas-edge-captain-rk3399_defconfig | 1 + configs/khadas-edge-rk3399_defconfig | 1 + configs/khadas-edge-v-rk3399_defconfig | 1 + configs/kylin-rk3036_defconfig | 1 + configs/leez-rk3399_defconfig | 1 + configs/lion-rk3368_defconfig | 1 + configs/ls1012a2g5rdb_qspi_defconfig | 2 +- configs/ls1012a2g5rdb_tfa_defconfig | 2 +- configs/ls1012afrdm_qspi_defconfig | 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- .../ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_qspi_defconfig | 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 2 +- configs/ls1021aqds_nand_defconfig | 2 +- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 2 +- configs/ls1021aqds_sdcard_qspi_defconfig | 2 +- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 2 +- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 2 +- configs/ls1021atwr_sdcard_qspi_defconfig | 2 +- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028aqds_tfa_defconfig | 2 +- configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1028ardb_tfa_defconfig | 2 +- configs/ls1043aqds_defconfig | 2 +- configs/ls1043aqds_nand_defconfig | 2 +- configs/ls1043aqds_nor_ddr3_defconfig | 2 +- configs/ls1043aqds_qspi_defconfig | 2 +- configs/ls1043aqds_sdcard_ifc_defconfig | 2 +- configs/ls1043aqds_sdcard_qspi_defconfig | 2 +- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1043ardb_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_defconfig | 2 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_sdcard_defconfig | 2 +- configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_tfa_defconfig | 2 +- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046afrwy_tfa_defconfig | 2 +- configs/ls1046aqds_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_defconfig | 2 +- configs/ls1046aqds_nand_defconfig | 2 +- configs/ls1046aqds_qspi_defconfig | 2 +- configs/ls1046aqds_sdcard_ifc_defconfig | 2 +- configs/ls1046aqds_sdcard_qspi_defconfig | 2 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_tfa_defconfig | 2 +- configs/ls1046ardb_emmc_defconfig | 2 +- configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_qspi_defconfig | 2 +- configs/ls1046ardb_qspi_spl_defconfig | 2 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_sdcard_defconfig | 2 +- configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046ardb_tfa_defconfig | 2 +- configs/ls1088aqds_defconfig | 2 +- configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088aqds_qspi_defconfig | 2 +- configs/ls1088aqds_sdcard_ifc_defconfig | 2 +- configs/ls1088aqds_sdcard_qspi_defconfig | 2 +- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_qspi_defconfig | 2 +- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_sdcard_qspi_defconfig | 2 +- configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- configs/ls2080aqds_SECURE_BOOT_defconfig | 2 +- configs/ls2080aqds_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 2 +- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080aqds_sdcard_defconfig | 2 +- configs/ls2080ardb_SECURE_BOOT_defconfig | 2 +- configs/ls2080ardb_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 2 +- configs/ls2081ardb_defconfig | 2 +- configs/ls2088aqds_tfa_defconfig | 2 +- configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 2 +- configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls2088ardb_tfa_defconfig | 2 +- configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/minnowmax_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mk808_defconfig | 1 + configs/nanopc-t4-rk3399_defconfig | 1 + configs/nanopi-m4-2gb-rk3399_defconfig | 1 + configs/nanopi-m4-rk3399_defconfig | 1 + configs/nanopi-m4b-rk3399_defconfig | 1 + configs/nanopi-neo4-rk3399_defconfig | 1 + configs/nanopi-r2s-rk3328_defconfig | 1 + configs/nanopi-r4s-rk3399_defconfig | 1 + configs/nas220_defconfig | 3 +- configs/net2big_v2_defconfig | 3 +- configs/netspace_lite_v2_defconfig | 3 +- configs/netspace_max_v2_defconfig | 3 +- configs/netspace_mini_v2_defconfig | 3 +- configs/netspace_v2_defconfig | 3 +- configs/nsa310s_defconfig | 3 +- configs/odroid-go2_defconfig | 1 + configs/omap4_panda_defconfig | 2 +- configs/omap4_sdp4430_defconfig | 2 +- configs/omap5_uevm_defconfig | 2 +- configs/openrd_base_defconfig | 3 +- configs/openrd_client_defconfig | 3 +- configs/openrd_ultimate_defconfig | 3 +- configs/orangepi-rk3399_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/pinebook-pro-rk3399_defconfig | 1 + configs/pogo_e02_defconfig | 3 +- configs/pogo_v4_defconfig | 3 +- configs/popmetal-rk3288_defconfig | 1 + configs/puma-rk3399_defconfig | 1 + configs/px30-core-ctouch2-of10-px30_defconfig | 1 + configs/px30-core-ctouch2-px30_defconfig | 1 + configs/px30-core-edimm2.2-px30_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/roc-cc-rk3308_defconfig | 1 + configs/roc-cc-rk3328_defconfig | 1 + configs/roc-pc-mezzanine-rk3399_defconfig | 1 + configs/roc-pc-rk3399_defconfig | 1 + configs/rock-pi-4-rk3399_defconfig | 1 + configs/rock-pi-4c-rk3399_defconfig | 1 + configs/rock-pi-e-rk3328_defconfig | 1 + configs/rock-pi-n10-rk3399pro_defconfig | 1 + configs/rock-pi-n8-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + configs/rock64-rk3328_defconfig | 1 + configs/rock960-rk3399_defconfig | 1 + configs/rock_defconfig | 1 + configs/rockpro64-rk3399_defconfig | 1 + configs/sheep-rk3368_defconfig | 1 + configs/sheevaplug_defconfig | 3 +- configs/slimbootloader_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_chameleonv3_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/som-db5800-som-6867_defconfig | 1 + configs/ten64_tfa_defconfig | 2 +- ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + .../theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/ti816x_evm_defconfig | 2 +- configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + configs/xtfpga_defconfig | 3 +- drivers/serial/Kconfig | 54 ++++++++++++++++--- drivers/serial/Makefile | 2 +- include/configs/10m50_devboard.h | 1 - include/configs/MPC837XERDB.h | 2 - include/configs/MPC8548CDS.h | 2 - include/configs/P1010RDB.h | 3 -- include/configs/P2041RDB.h | 2 - include/configs/SBx81LIFKW.h | 2 - include/configs/SBx81LIFXCAT.h | 2 - include/configs/T102xRDB.h | 2 - include/configs/T104xRDB.h | 2 - include/configs/T208xQDS.h | 2 - include/configs/T208xRDB.h | 2 - include/configs/T4240RDB.h | 2 - include/configs/am43xx_evm.h | 4 -- include/configs/ax25-ae350.h | 4 -- include/configs/axs10x.h | 2 - include/configs/bcmstb.h | 2 - include/configs/bur_am335x_common.h | 2 - include/configs/chromebook_coral.h | 3 -- include/configs/cm_t43.h | 4 -- include/configs/dfi-bt700.h | 1 - include/configs/galileo.h | 1 - .../configs/gardena-smart-gateway-mt7688.h | 2 - include/configs/hsdk-4xd.h | 2 - include/configs/hsdk.h | 2 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 - include/configs/legoev3.h | 1 - include/configs/linkit-smart-7688.h | 2 - include/configs/ls1012a_common.h | 2 - include/configs/ls1021aiot.h | 2 - include/configs/ls1021aqds.h | 4 -- include/configs/ls1021atsn.h | 4 -- include/configs/ls1021atwr.h | 4 -- include/configs/ls1028a_common.h | 2 - include/configs/ls1043a_common.h | 2 - include/configs/ls1046a_common.h | 2 - include/configs/ls1088a_common.h | 2 - include/configs/ls2080a_common.h | 2 - include/configs/malta.h | 1 - include/configs/mt7621.h | 2 - include/configs/mt7628.h | 2 - include/configs/mt8183.h | 3 -- include/configs/mt8516.h | 3 -- include/configs/mv-common.h | 2 - include/configs/nokia_rx51.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 -- include/configs/px30_common.h | 2 - include/configs/rk3308_common.h | 2 - include/configs/rockchip-common.h | 2 - include/configs/siemens-am33x-common.h | 1 - include/configs/sniper.h | 5 -- include/configs/socfpga_arria10_socdk.h | 1 - include/configs/socfpga_chameleonv3.h | 1 - include/configs/socfpga_soc64_common.h | 1 - include/configs/sunxi-common.h | 2 - include/configs/tb100.h | 1 - include/configs/theadorable-x86-dfi-bt700.h | 1 - include/configs/ti814x_evm.h | 2 - include/configs/ti816x_evm.h | 2 - include/configs/ti_am335x_common.h | 6 --- include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_omap3_common.h | 4 -- include/configs/ti_omap4_common.h | 2 - include/configs/ti_omap5_common.h | 4 -- include/configs/vocore2.h | 2 - include/configs/x530.h | 2 - include/configs/x86-common.h | 1 - include/configs/xtfpga.h | 2 - include/ns16550.h | 2 +- 386 files changed, 397 insertions(+), 369 deletions(-) diff --git a/README b/README index f71832b689..9086207954 100644 --- a/README +++ b/README @@ -1619,13 +1619,6 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. -- CONFIG_SPL_NS16550_MIN_FUNCTIONS: - Define this if you desire to only have use of the NS16550_init - and NS16550_putc functions for the serial driver located at - drivers/serial/ns16550.c. This option is useful for saving - space for already greatly restricted images, including but not - limited to NAND_SPL configurations. - - CONFIG_DISPLAY_BOARDINFO Display information about the board that U-Boot is running on when U-Boot starts up. The board function checkboard() is called diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 327c0e0697..0c7262352d 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,10 +11,6 @@ /* uArchitecture specifics */ /* Serial Info */ -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_SYS_NS16550_CLK 100000000 #define CONFIG_SYS_NS16550_CLK_DIV 54 #define CONFIG_SYS_NS16550_COM3 0x18023000 diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 05fa9b9612..44699476b0 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,9 +11,6 @@ /* uArchitecture specifics */ /* Serial Info */ -/* no padding */ -#define CONFIG_SYS_NS16550_REG_SIZE 1 - #define CONFIG_SYS_NS16550_CLK 0x03b9aca0 #define CONFIG_SYS_NS16550_COM1 0x18000300 diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index dd88d10274..28966e0d0a 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -47,5 +47,6 @@ CONFIG_PHY_GIGE=y CONFIG_ALTERA_TSE=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_ALTERA_TIMER=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 675b2de151..7054333d73 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -206,7 +206,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_FSL=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index e5c45a1bff..85b055a93f 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -85,5 +85,5 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_ADDR_MAP=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 85ec76a597..0d21b893d8 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -84,4 +84,4 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 852ac9a6ee..b01919ec67 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -84,4 +84,4 @@ CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index e15ca5ea2b..a3d9a8b4b7 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -129,7 +129,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index dcf74f5d6a..2ca0250399 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -93,7 +93,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 230c6d0283..5d57aa3ba4 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -114,7 +114,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 982420db74..a13b48c20e 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -116,7 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b3af4450d0..a9c7652fab 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -128,7 +128,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 537d8bf576..a0277d0aa6 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -92,7 +92,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index dd9120970b..f43a5a0c54 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -113,7 +113,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index ff7cfa2461..ef52f94882 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -115,7 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index a61f4d017a..2b2744dd74 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -132,7 +132,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 92a7e09669..29b7d84809 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -95,7 +95,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 84e2d3c587..98164d2bad 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -116,7 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index b883b81e0c..d74fbecfaa 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -118,7 +118,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 7f7870d82c..efd0a7eb89 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 3e16470608..44e98b9520 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -94,7 +94,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index e985f8cd75..9c65043766 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -115,7 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 9f4ae14e0b..4b967352f4 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -117,7 +117,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 3f93b318c9..b65e651878 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -142,7 +142,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 3b3cf1ee7a..034a971bc8 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -124,7 +124,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index aba5b9cedd..9476c28e98 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index ce0ba0e375..ecd5e978c8 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -104,7 +104,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index f3fc4c82a5..80f4d22518 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -141,7 +141,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 25eb5d5da7..50fc0c124e 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 054320f356..dafb430e4c 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -125,7 +125,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index aae886b75c..411b4f05a4 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -103,7 +103,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index cc02fe6a8a..8b0b6e4e68 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -144,7 +144,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index dc82da81b8..6a17f085a7 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -126,7 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 7b80edeeeb..2738b208f1 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -128,7 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 5fecb66847..fdd7703f72 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -106,7 +106,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 9162774ad7..5904aa54b2 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -147,7 +147,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index fd143b610b..938148df93 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -129,7 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index edb8b9958e..c4a41c4c0e 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -131,7 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b1dbca6e7e..a4ed8fb39c 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -109,7 +109,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 1269d22f90..9b4ca39d34 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -146,7 +146,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index b5394d05b7..a6d98b42ce 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -128,7 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 431ca31302..b3e4a1f0d0 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -130,7 +130,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 1ee46f9fbe..f1a9c058ca 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -108,7 +108,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 2ba5666446..0eec508933 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -98,7 +98,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 9a2796fc7f..f9f4c31ddb 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -93,7 +93,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 8cb00d5d31..6a97437008 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -95,7 +95,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index c0bd16bd61..1725a8a5a9 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -90,7 +90,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 73ef73c484..fa7c35b9ef 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -63,7 +63,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 9fa0fda84f..125871301e 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -61,7 +61,8 @@ CONFIG_MV88E61XX_FIXED_PORTS=0x300 CONFIG_PHY_FIXED=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 2aada043e8..f21c53d59f 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -129,7 +129,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index e5661b0b60..6f9f5a2603 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 320f22e348..76a59604f2 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 1f571b6e6f..a4825909e7 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -98,7 +98,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0xEFE00000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 4088d40de3..1aa0e9eec1 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -129,7 +129,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 5a6f9a8d24..ba1820e93a 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -123,7 +123,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 2d03b4eb14..98cd9b71e0 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -126,7 +126,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 8f283fa8fd..f6301a57cf 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -98,7 +98,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xEFF10000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index beb0259488..dd7473ef7f 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -136,7 +136,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 7ee5fb4f47..364aab5847 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -130,7 +130,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c050e310c8..c6710a0413 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -104,7 +104,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 0ff651ae68..a705542eea 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -133,7 +133,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 98065da77d..d6d6ec0fbf 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -93,7 +93,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 88e943d4d0..802213de2b 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -105,7 +105,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 23f6ee6e43..a881488dbe 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -136,7 +136,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index c2d95c10ab..562a79955c 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -130,7 +130,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 2194ff6c51..00018033a3 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -133,7 +133,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 7f57b004d5..0cb359de94 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -104,7 +104,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 5d4573a7f9..cbe1bb4e3f 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -138,7 +138,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 7ca9a8b036..80a2c003e6 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -132,7 +132,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 39fcd2dad3..99bee8e5ea 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -135,7 +135,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index 8d1011d06c..aa6a053209 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -106,7 +106,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 9b082674d6..b445b6bde1 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -119,7 +119,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 662edc32c6..a807ac8347 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -94,7 +94,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index 0b759c8c2c..fc6cad59cf 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -53,7 +53,7 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 68a9651887..08cac404c6 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -55,7 +55,7 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y CONFIG_USB=y diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index a5436db7ac..85a70c0996 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 7fbec63c58..00d43e24c5 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 5f43f4c0ee..90a734fcda 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -59,6 +59,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index 920e882846..f8e0327d8f 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -40,5 +40,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCMSTB=y CONFIG_MTD=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 # CONFIG_EFI_LOADER is not set diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index b44eabaa42..81433b02cb 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -44,7 +44,8 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_BCMSTB_SPI=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 06987ab828..321121e3f7 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 59ae29a80e..2240988dd0 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -94,6 +94,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig index 3d2f40fb95..d768e11db5 100644 --- a/configs/chromebook_bob_defconfig +++ b/configs/chromebook_bob_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 45905c6792..a38b3b78c0 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -102,6 +102,7 @@ CONFIG_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SOUND_DA7219=y CONFIG_SOUND_I8254=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index ffa8070cb3..150dba1408 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -97,6 +97,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SOUND=y CONFIG_I2S=y diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig index e8ec8855dd..94d14d012d 100644 --- a/configs/chromebook_kevin_defconfig +++ b/configs/chromebook_kevin_defconfig @@ -93,6 +93,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index b645cba907..570c4e82a4 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -79,6 +79,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SPL_DM_RTC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 541b7fadea..43cf53045b 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_INTEL=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index ca453ac8b9..08e1e5be41 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -96,6 +96,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_ROCKCHIP=y diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index 27bf046f99..aa3d6f2b9d 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_I2C_DW=y CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index e922264875..77735739b8 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -91,6 +91,7 @@ CONFIG_CROS_EC_LPC=y # CONFIG_SPL_PINCTRL is not set # CONFIG_TPL_PINCTRL is not set CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SOUND_RT5677=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 92018fb78e..d5aaee9dde 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -95,6 +95,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index b78e98c204..e83f2dfe7f 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -59,6 +59,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_LPC=y CONFIG_RTL8169=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_TPM_TIS_LPC=y CONFIG_USB_STORAGE=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 0d904675f7..31979f32bc 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -69,6 +69,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 6fed3f2ecd..18d58bec20 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 20c0c18169..e4da59bae9 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -61,6 +61,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index d8c5be66ad..e297494663 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -55,6 +55,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 094b21666e..203eff8e16 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -53,6 +53,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 4521172f42..cb0f0d7c8d 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -57,6 +57,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_SPI=y diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 5eea1ec9a7..71c57ed5ab 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -66,7 +66,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 16a866f6b4..6c35f31a29 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -59,7 +59,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 6c805f4156..a17d01f3fd 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -55,7 +55,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 86fe0692a0..6deb05575c 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -62,7 +62,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 93aef472b5..9088fffb25 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -56,7 +56,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig index 5abdadf2d5..c364c9ecc8 100644 --- a/configs/eaidk-610-rk3399_defconfig +++ b/configs/eaidk-610-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 83f532d6e5..8d1fc22eb9 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 28aaff69e9..89e6d1febc 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -52,6 +52,7 @@ CONFIG_ATAPI=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y # CONFIG_GZIP is not set CONFIG_EFI=y CONFIG_EFI_STUB=y diff --git a/configs/elgin-rv1108_defconfig b/configs/elgin-rv1108_defconfig index 1f4ca01c50..36f57d5812 100644 --- a/configs/elgin-rv1108_defconfig +++ b/configs/elgin-rv1108_defconfig @@ -48,6 +48,7 @@ CONFIG_PINCTRL_ROCKCHIP_RV1108=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 6bc777c51c..bb6f21b2e6 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -101,6 +101,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig index f41c7580b4..2e3bff8cf0 100644 --- a/configs/evb-px5_defconfig +++ b/configs/evb-px5_defconfig @@ -78,6 +78,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_PANIC_HANG=y CONFIG_SPL_TINY_MEMSET=y diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index 8ef40d847c..289f47f4ae 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -55,6 +55,7 @@ CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PINCTRL=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig index ce10750857..06a044b934 100644 --- a/configs/evb-rk3128_defconfig +++ b/configs/evb-rk3128_defconfig @@ -46,6 +46,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index f8ca1f6597..33202e48fe 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_RAM=y CONFIG_TPL_RAM=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_GADGET=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 7c0b856ca5..8f8d34c703 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -81,6 +81,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 8502fcc51e..0aeaf01d9a 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 9421845b03..8a6d19a176 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -88,6 +88,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index e7da9c4e5f..3050fd5992 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index db3acf5be5..7374ee42fb 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -63,5 +63,6 @@ CONFIG_SPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig index 5de5de465c..aab3223111 100644 --- a/configs/evb-rv1108_defconfig +++ b/configs/evb-rv1108_defconfig @@ -42,6 +42,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index d48dcc1a0e..3aee6b6471 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig index 1f91118426..2a6d2edbab 100644 --- a/configs/firefly-px30_defconfig +++ b/configs/firefly-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 63c53a0248..26967a67cc 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig index a37870628c..5475172532 100644 --- a/configs/firefly-rk3399_defconfig +++ b/configs/firefly-rk3399_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig index 1d7832b959..c23d0549a4 100644 --- a/configs/geekbox_defconfig +++ b/configs/geekbox_defconfig @@ -27,5 +27,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 6fdb3ea680..8ee1183309 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -62,7 +62,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index 794cf4b23d..1889743f08 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -61,7 +61,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig index 8c6ad5a0d1..bba4067268 100644 --- a/configs/hsdk_4xd_defconfig +++ b/configs/hsdk_4xd_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 9543c785bb..4715f9d9d7 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 9290cb7af6..beee58962a 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -59,7 +59,8 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index ce5a089d32..f536dd3bcb 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -59,7 +59,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 42f812c31f..1fa1a5afa7 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -66,7 +66,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 25007793b3..96bcba6e94 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index 6c8a284e7c..0d1c97dd4b 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 6182101f11..bded097880 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -96,6 +96,7 @@ CONFIG_KEYSTONE_USB_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index fd169c3e95..a851d85082 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -70,6 +70,7 @@ CONFIG_NOP_PHY=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index fec29f2c91..b0069fd60b 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index f6ac484f2e..9ca26ae61f 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -67,6 +67,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 13d612ac3f..153abb7eb9 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -93,6 +93,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 59ec3a6346..2990a702d9 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -71,6 +71,7 @@ CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_DAVINCI_SPI=y diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig index dff0522308..754fd4e3c6 100644 --- a/configs/khadas-edge-captain-rk3399_defconfig +++ b/configs/khadas-edge-captain-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig index 5a8b69c0f9..7518f7f2ed 100644 --- a/configs/khadas-edge-rk3399_defconfig +++ b/configs/khadas-edge-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig index f54a610a27..4c4301a9e7 100644 --- a/configs/khadas-edge-v-rk3399_defconfig +++ b/configs/khadas-edge-v-rk3399_defconfig @@ -56,6 +56,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 1ad635daa9..646f0086c6 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -60,6 +60,7 @@ CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y # CONFIG_SPL_SYSRESET is not set CONFIG_USB=y diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig index a8326f03a2..5a958ee36a 100644 --- a/configs/leez-rk3399_defconfig +++ b/configs/leez-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig index 1ace7b795a..ee401b763d 100644 --- a/configs/lion-rk3368_defconfig +++ b/configs/lion-rk3368_defconfig @@ -97,6 +97,7 @@ CONFIG_TPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index dbb0ce0221..b551f5bdee 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -60,7 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index a8b4ce2bab..21ccc55573 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -58,7 +58,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_FSL_PFE=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 1a4fc999db..f1c9169a72 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -58,7 +58,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 7e9076a1f9..f40ede127b 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -56,7 +56,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index 7bfe1f7cae..ff5e323d57 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -61,7 +61,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 2327d89243..3b073241e4 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -64,7 +64,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 250440a70a..238886d0df 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -59,7 +59,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index f1600c4005..ccd8fb9801 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -62,7 +62,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index e4a26dc0ab..fcef5e5d5b 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -85,7 +85,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index c9fa109930..c2996a1372 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -75,7 +75,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 773a3e6b2b..a1709f4525 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -84,7 +84,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index c9f0635de1..3639b4dd93 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -65,7 +65,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index c1c21cb187..4fc7b38734 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -67,7 +67,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 503fe95c88..f162111d0b 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -63,7 +63,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 727d10ffaa..cc640461cf 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -64,7 +64,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 72129a70a8..e6cd6a7d19 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index c67f329f92..d5d3354457 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -98,7 +98,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xf40000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 14aa19fe72..c3c6678bb4 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 2f1b41f068..40228acaa8 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 1c38d99dfc..ebf6fdb463 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -84,7 +84,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 4a642f4a6c..07d52c249d 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -127,7 +127,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 1b5d8229c6..6834a696b6 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -112,7 +112,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 877a771b51..e5e732a508 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -69,7 +69,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 9695164a93..29dc23e179 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -96,7 +96,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 290d53f852..86060806fe 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index b3a93179c2..ed7e91e9b5 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -77,7 +77,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index cb3d1580d3..f84f4dd660 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -112,7 +112,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index c53827c637..40a0ea7032 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -111,7 +111,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 46ab9a26f0..621a0238d4 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -105,7 +105,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 753583d47b..525c7df6d0 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index b5e243bc0e..dde204eaa0 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index fad07863db..b8df245025 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -80,7 +80,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 20354f7e86..5b1cf988cf 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -86,7 +86,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_SCSI=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 9b3c77fe56..a7e9583c73 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -99,7 +99,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 29cbac3135..774d41308b 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index 21bb036ee8..f759baf36d 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -100,7 +100,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index fd7f3bb69b..e7dbf41b97 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 14931f7219..627abc81c9 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -127,7 +127,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index 22844636e2..f4dcbd4a92 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -115,7 +115,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index b75c75230f..307fbfcbb7 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -98,7 +98,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 21199b9d06..667fc2123a 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -107,7 +107,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index df227d8037..7d980c3c46 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index 0e2fa0284d..b345d13caa 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 6b9971f138..d4546348bb 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -110,7 +110,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 0aa046a425..f0f8cbf34e 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -117,7 +117,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index a6c33de397..529cd93bd2 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -110,7 +110,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ddf280a562..bfe9260d1b 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -115,7 +115,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index 7ca5457c2d..391e95a48d 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -84,7 +84,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 5fe6bae3a1..2ebde25bd9 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -90,7 +90,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 7d9f533001..0df5b85869 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -67,7 +67,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 03e944fa7a..a095bbcb82 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -76,7 +76,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index e9cf20d5f7..2bf8a94925 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -98,7 +98,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 0e2f4094f7..5fe73bc8ac 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -101,7 +101,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 75851ad390..7c8a1e70fa 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -130,7 +130,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 552bb43f7a..937581536a 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -91,7 +91,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 312464484d..4d3c0580a1 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -130,7 +130,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 344899ef6f..480ab03795 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -118,7 +118,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 0a363533ff..a0d57b1935 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 26fc4592a9..e08af4d1a2 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -109,7 +109,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index d9c716ebab..1a09fdadd3 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -111,7 +111,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 61b7244ff2..346a954760 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -86,7 +86,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 05115ea71e..4361cd223d 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -90,7 +90,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index ac2cede0d3..560362695f 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -119,7 +119,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 6074b6b314..cdcfa63bf4 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -109,7 +109,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index 07b077767a..e0442390db 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -111,7 +111,7 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 2432154f77..da6c2431bf 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 0aa2792c3c..f9aab31acf 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -85,7 +85,7 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index 8556c00355..aecd74d15b 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -101,7 +101,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index d4f2268041..8d1fc5f204 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -93,7 +93,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index af63278bb3..7c6e6b7637 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -96,7 +96,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 6b42170ffb..64296dbe0b 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -121,7 +121,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index dedefb3a0a..2b4712e07e 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -116,7 +116,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 60f26f0183..c8ab572353 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -118,7 +118,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index a819ebfeff..18213e5cc5 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -89,7 +89,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index c569753338..eb88cec6e0 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -92,7 +92,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 2b96382f24..33aedcfbd2 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -111,7 +111,7 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 4263635384..db28ae196f 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -112,7 +112,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 2e812943fd..0ec80be2ea 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -90,7 +90,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 9c12f2be9c..27323be408 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -96,7 +96,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF2127=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 817ae8d728..f66f529836 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index b3e75847cc..d601c083e2 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -99,7 +99,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index effcd33629..e2b6044d1f 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -112,7 +112,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index eb57948414..8abd58d53e 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -92,7 +92,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index e5702b8159..389b32b2d6 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -106,7 +106,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index face1e0532..e4d15dda14 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -94,7 +94,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index ba6f5090d4..4030fd4693 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -97,7 +97,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 5000290030..b6e154b78b 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -116,7 +116,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index 58bae66baa..fc43c535b5 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -86,7 +86,7 @@ CONFIG_RTC_PCF8563=y CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9c6012460b..09df15154e 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -112,7 +112,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 6e1fe901ff..8cdfe5cc0b 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -82,7 +82,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 8441814f13..84c9f15266 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -89,7 +89,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index dc9a47463f..3ac03305c7 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -100,7 +100,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 3610985680..41891d83ac 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -108,7 +108,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index 054c5e6d61..b635c651aa 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -45,3 +45,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 55f624bbee..243213cb81 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -47,3 +47,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index 53762a94e2..ed41e298f4 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -44,3 +44,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 8b86d74dc4..63e5fcb6a5 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -46,3 +46,4 @@ CONFIG_PCI_GT64120=y CONFIG_PCI_MSC01=y CONFIG_RTC_MC146818=y CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_PORT_MAPPED=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 66f3036313..52ed763424 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -65,6 +65,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_RTL8169=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 0811e70dce..9346cafc64 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig index 403a84befd..7ba8338add 100644 --- a/configs/mk808_defconfig +++ b/configs/mk808_defconfig @@ -99,6 +99,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig index 03fa857996..8fad8c643f 100644 --- a/configs/nanopc-t4-rk3399_defconfig +++ b/configs/nanopc-t4-rk3399_defconfig @@ -55,6 +55,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig index 67ca98563b..c5f13c060b 100644 --- a/configs/nanopi-m4-2gb-rk3399_defconfig +++ b/configs/nanopi-m4-2gb-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig index afa51bc8fa..b6a604b694 100644 --- a/configs/nanopi-m4-rk3399_defconfig +++ b/configs/nanopi-m4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig index d02eb1851a..767befe2d2 100644 --- a/configs/nanopi-m4b-rk3399_defconfig +++ b/configs/nanopi-m4b-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig index d2d9bf91c5..383ec1f39e 100644 --- a/configs/nanopi-neo4-rk3399_defconfig +++ b/configs/nanopi-neo4-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 82264de908..40d3117b4f 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -91,6 +91,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSRESET=y # CONFIG_TPL_SYSRESET is not set diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 2185f87d7d..40a45a0f4b 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -52,6 +52,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM_RK3399_LPDDR4=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 9cebc704ce..0590fc95c4 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -63,7 +63,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index c10e1a5013..b3278142c8 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 75907e05c5..dfdb06b237 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index db08ca5763..995c0ccb1b 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index dda3b6b5f9..877a39cfa7 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -65,7 +65,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 21534c59fd..24f7d8b4bc 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -67,7 +67,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_KIRKWOOD_SPI=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index afa0cad041..e7d6ffd925 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -53,7 +53,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_UBIFS_SILENCE_MSG=y diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig index 4705f61e42..33adcc952c 100644 --- a/configs/odroid-go2_defconfig +++ b/configs/odroid-go2_defconfig @@ -104,6 +104,7 @@ CONFIG_DM_RESET=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 2c4e26c290..0cae1c6150 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -46,7 +46,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OMAP3=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index 2315a84285..e15c6d5cb1 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_OMAP3=y CONFIG_USB_GADGET=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index bd0ede759c..d12199766a 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -56,7 +56,7 @@ CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y CONFIG_CONS_INDEX=3 -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_DWC3=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index c2e879c9bd..45bd307a1c 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -61,6 +61,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 01bfaed978..9c9f6c463d 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index 7c64103817..fbcdf4b363 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -62,6 +62,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig index 39245e8784..0980d81569 100644 --- a/configs/orangepi-rk3399_defconfig +++ b/configs/orangepi-rk3399_defconfig @@ -51,6 +51,7 @@ CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index 8a274187d0..0632a928bc 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -78,6 +78,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig index 528b7bb69f..dfbf5e70f4 100644 --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@ -80,6 +80,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index d0071f3af5..116e5d0ed3 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -55,7 +55,8 @@ CONFIG_MTD_RAW_NAND=y CONFIG_PHY_MARVELL=y CONFIG_MVGBE=y CONFIG_MII=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 3b08cb7b1d..018c2f5033 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -74,7 +74,8 @@ CONFIG_PCI=y CONFIG_PCI_MVEBU=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index f6c49da574..91123784b5 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -75,6 +75,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index c2b0b39c7b..9a5be3e913 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -92,6 +92,7 @@ CONFIG_DM_RESET=y CONFIG_DM_RTC=y CONFIG_RTC_ISL1208=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig index 9175c7c85a..9c36750bde 100644 --- a/configs/px30-core-ctouch2-of10-px30_defconfig +++ b/configs/px30-core-ctouch2-of10-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig index 0aa7cca7b8..db1ceaa31f 100644 --- a/configs/px30-core-ctouch2-px30_defconfig +++ b/configs/px30-core-ctouch2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig index d731b96878..d2cca48304 100644 --- a/configs/px30-core-edimm2.2-px30_defconfig +++ b/configs/px30-core-edimm2.2-px30_defconfig @@ -100,6 +100,7 @@ CONFIG_RNG_ROCKCHIP=y # CONFIG_SPECIFY_CONSOLE_INDEX is not set CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SOUND=y CONFIG_SYSRESET=y CONFIG_DM_THERMAL=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 8433b5734f..0f4811e5d7 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -70,6 +70,7 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y CONFIG_SPL_DM_RTC=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f82f628d5b..a8222122fc 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -50,6 +50,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_NVME_PCI=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_KEYBOARD=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 670211e2e9..0a029c4098 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -74,6 +74,7 @@ CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 7f1259d82c..8172ed0ad2 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -95,6 +95,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig index 3cdcc729f8..6827c98ed9 100644 --- a/configs/roc-pc-mezzanine-rk3399_defconfig +++ b/configs/roc-pc-mezzanine-rk3399_defconfig @@ -71,6 +71,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index e03442afa4..cf4a58de1c 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -68,6 +68,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig index 83721cedf3..54a400405b 100644 --- a/configs/rock-pi-4-rk3399_defconfig +++ b/configs/rock-pi-4-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig index ac9a3f9830..e74ba07e44 100644 --- a/configs/rock-pi-4c-rk3399_defconfig +++ b/configs/rock-pi-4c-rk3399_defconfig @@ -62,6 +62,7 @@ CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index c0c1ebf340..0ffb073f31 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -96,6 +96,7 @@ CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_SYSRESET=y diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig index fcb3a681ca..2443f29246 100644 --- a/configs/rock-pi-n10-rk3399pro_defconfig +++ b/configs/rock-pi-n10-rk3399pro_defconfig @@ -63,6 +63,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 4ed98c0a51..18c6d1b922 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -74,6 +74,7 @@ CONFIG_RAM=y CONFIG_SPL_RAM=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 38a5f3a80c..54d01456b1 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -77,6 +77,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index e75011bee5..73a4f06eb9 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -92,6 +92,7 @@ CONFIG_TPL_RAM=y CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 6ed5ef868e..f2c914f41f 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_RNG=y CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig index bd6183ba5b..26638405bf 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -63,6 +63,7 @@ CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SERIAL=y CONFIG_SYSRESET=y CONFIG_TIMER=y diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig index ba48d021f4..5b8d678f6b 100644 --- a/configs/rockpro64-rk3399_defconfig +++ b/configs/rockpro64-rk3399_defconfig @@ -79,6 +79,7 @@ CONFIG_SCSI=y CONFIG_DM_SCSI=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_ROCKCHIP_SPI=y CONFIG_SYSRESET=y CONFIG_USB=y diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig index 01f104a97d..40cd91c045 100644 --- a/configs/sheep-rk3368_defconfig +++ b/configs/sheep-rk3368_defconfig @@ -29,5 +29,6 @@ CONFIG_RAM=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_ERRNO_STR=y diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 52f5aba8ca..79f36c0360 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -65,7 +65,8 @@ CONFIG_MVGBE=y CONFIG_MII=y CONFIG_DM_RTC=y CONFIG_RTC_MV=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index b6b9f88c00..f5d16f64d7 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -31,5 +31,6 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y # CONFIG_PCI_PNP is not set +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_CONSOLE_SCROLL_LINES=5 # CONFIG_GZIP is not set diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 68440926c0..9269eccf17 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index de9ebd0722..48fb067223 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -75,6 +75,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index 7642498ea9..da4545efff 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 08ae6c502b..4e2dc0c985 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -62,6 +62,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig index 478efc59ea..00c4cf3008 100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@ -29,6 +29,7 @@ CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y CONFIG_MMC_DW=y CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_DESIGNWARE_APB_TIMER=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 0feda3b04f..4d856d535a 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -81,6 +81,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index fa19f555f2..1056932cd3 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -72,6 +72,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 12e8ebf013..a6714b265e 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -82,6 +82,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 5ee9f5ff9d..e0e6b2d046 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -83,6 +83,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index f689105695..919863270f 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -80,6 +80,7 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_DM_RESET=y +CONFIG_SYS_NS16550_MEM32=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index 5d401e6c2d..5b72469712 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -60,6 +60,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/ten64_tfa_defconfig b/configs/ten64_tfa_defconfig index 48b2ffc752..0209f62d2f 100644 --- a/configs/ten64_tfa_defconfig +++ b/configs/ten64_tfa_defconfig @@ -81,7 +81,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_RX8025=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 22544c0913..440c170c6b 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -65,6 +65,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index 8741ecbb2d..b91c3b1354 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -64,6 +64,7 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y CONFIG_WINBOND_W83627=y CONFIG_E1000=y +CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 47dbf34277..bab7b29bf8 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -77,6 +77,6 @@ CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y # CONFIG_USE_PRIVATE_LIBGCC is not set diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 85d94a6ea8..5976a84491 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 7dfbad8083..078f829c2d 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index cbae60f987..0c9d61b805 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -83,6 +83,7 @@ CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 3148329680..c58514669d 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=1027 CONFIG_PHYLIB=y CONFIG_ETHOC=y -CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SYS_NS16550_REG_SIZE=-4 CONFIG_SYSRESET=y CONFIG_OF_LIBFDT=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index de02e08a29..4978a65715 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -720,6 +720,17 @@ config PIC32_SERIAL help Support for the UART found on Microchip PIC32 SoC's. +config SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver" + depends on !DM_SERIAL + select SYS_NS16550 + +config SPL_SYS_NS16550_SERIAL + bool "NS16550 UART or compatible legacy driver in SPL" + depends on SPL && !SPL_DM_SERIAL + default y if SYS_NS16550_SERIAL || ARCH_SUNXI || ARCH_OMAP2PLUS + select SYS_NS16550 + config SYS_NS16550 bool "NS16550 UART or compatible" help @@ -732,25 +743,52 @@ config SYS_NS16550 config NS16550_DYNAMIC bool "Allow NS16550 to be configured at runtime" + depends on SYS_NS16550 default y if SYS_COREBOOT || SYS_SLIMBOOTLOADER help Enable this option to allow device-tree control of the driver. Normally this driver is controlled by the following options: - CONFIG_SYS_NS16550_PORT_MAPPED - indicates that port I/O is used for - access. If not enabled, then the UART is memory-mapped. - CONFIG_SYS_NS16550_MEM32 - if memory-mapped, indicates that 32-bit - access should be used (instead of 8-bit) - CONFIG_SYS_NS16550_REG_SIZE - indicates register width and also - endianness. If positive, big-endian access is used. If negative, - little-endian is used. - It is not a good practice for a driver to be statically configured, since it prevents the same driver being used for different types of UARTs in a system. This option avoids this problem at the cost of a slightly increased code size. +config SYS_NS16550_MEM32 + bool "If memory-mapped, 32bit access is needed for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, if memory-mapped, indicates that 32-bit access should be + used (instead of 8-bit) for register access. + +config SYS_NS16550_PORT_MAPPED + bool "Port I/O is used for ns16550 register access" + depends on SYS_NS16550 + help + If enabled, port I/O is used for ns16550 register access. If not + enabled, then the UART is memory-mapped. + +config SYS_NS16550_REG_SIZE + int "ns16550 register width and endianness" + depends on SYS_NS16550_SERIAL || SPL_SYS_NS16550_SERIAL + range -4 4 + default -4 if ARCH_OMAP2PLUS || ARCH_SUNXI + default 1 + help + Indicates register width and also endianness. If positive, big-endian + access is used. If negative, little-endian is used. + +config SPL_NS16550_MIN_FUNCTIONS + bool "Only provide NS16550_init and NS16550_putc in SPL" + depends on SPL_SYS_NS16550_SERIAL && PPC + help + Enable this if you desire to only have use of the NS16550_init and + NS16550_putc functions for the serial driver located at + drivers/serial/ns16550.c. This option is useful for saving space for + already greatly restricted images, including but not limited to + NAND_SPL configurations. + config INTEL_MID_SERIAL bool "Intel MID platform UART support" depends on DM_SERIAL && OF_CONTROL diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index eb7b8f23ee..45cf94c74c 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,7 +25,7 @@ ifdef CONFIG_DM_SERIAL obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o else obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o -obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o +obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index afd7cc89bf..719caf7b0c 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -15,7 +15,6 @@ /* * SERIAL */ -#define CONFIG_SYS_NS16550_MEM32 /* * Flash diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c4cde1cc51..b8cbdc3675 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,8 +151,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b241939fc3..dba15dae74 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,8 +235,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 9afd834f9f..fd721f30b3 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,10 +322,7 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b9311fc5e4..173f6205e0 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,8 +163,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 9629d735a2..c99e6ba781 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 67e42b94c1..8b43fe0c99 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 978cc6714e..7cb10b205d 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,8 +294,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f26e9d6e86..3fa2d01dcc 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,8 +267,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 62f0710812..c5a28fadb0 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,8 +269,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0616f8a86d..795120c02a 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,8 +229,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 2eb4e73efa..e3cbc649fa 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,8 +89,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index a0951fbf62..b61c8005c3 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -15,10 +15,6 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_SERIAL -#endif /* I2C Configuration */ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index cf5125fdfa..7224bd8d1f 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,10 +33,6 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif #define CONFIG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index f2357b5785..c0429ae15c 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,9 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33333333 -#define CONFIG_SYS_NS16550_MEM32 /* * Ethernet PHY configuration diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 5aa720da3d..481baff11d 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,8 +97,6 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index a6de28a42b..773ce3f6a6 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,6 @@ /* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index 0eeea80b32..d14c1d445b 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -18,7 +18,4 @@ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" -#define CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 9061eba668..0641d5c0a2 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,12 +14,8 @@ #include /* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 4297047e8c..52f2d50118 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -14,7 +14,6 @@ #ifndef CONFIG_INTERNAL_UART /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #endif #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 545408a4ba..472f236b9b 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -13,7 +13,6 @@ #include /* ns16550 UART is memory-mapped in Quark SoC */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 965fa87c65..0d61724db8 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,9 +20,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 4af845ea9c..bfc0fa5c44 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,9 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 /* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ce65e7755..ce3cb20732 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,9 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 /* * Ethernet PHY configuration diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index cc8c37ec0b..7acdb0fa03 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 16fd6d562d..30ba606525 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,6 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index f0ae9248af..5434c4f767 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,6 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 9eedd47c07..b9c853d7df 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,9 +20,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 #endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 77f84e1c9e..148598fab4 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,8 +26,6 @@ /* GPIO */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_HWCONFIG diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 885774f63d..3f2dfa640c 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,8 +47,6 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6b23134ecc..bd2f74c126 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,10 +227,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index fce91192df..8c43f652ab 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,10 +60,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() /* I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 1ac59a2d45..06830f401a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,10 +145,6 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 43dbeea1b3..7dd5649005 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,8 +28,6 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* Miscellaneous configurable options */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 47367845a0..2fc06c1dd2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 07ec2c9563..40b4cb964d 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,8 +40,6 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index dec661d6b1..5668e07d13 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,8 +45,6 @@ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index d8997208e9..895c566fea 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,8 +37,6 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) /* diff --git a/include/configs/malta.h b/include/configs/malta.h index 30c2e41eec..2dd34ea731 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -33,7 +33,6 @@ /* * Serial driver */ -#define CONFIG_SYS_NS16550_PORT_MAPPED /* * Flash configuration diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 9b1ba3655e..1f733d112d 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,9 +22,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xbe000c00 #endif diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 43527017d8..da16e3b21a 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,9 +14,7 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 0xb0000c00 #endif diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index c93d70ddf1..eaffe0bf4c 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,9 +12,6 @@ #include -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005200 #define CONFIG_SYS_NS16550_CLK 26000000 diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 7228f3e428..347598868b 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,9 +12,6 @@ #include -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 0x11005000 #define CONFIG_SYS_NS16550_CLK 26000000 diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 6d4fff3820..4f1067c23b 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,10 +32,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 99a020c3c7..310bdde7cb 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,7 +40,6 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 838c62c671..065820689c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,10 +319,7 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SPL_NS16550_MIN_FUNCTIONS #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 49d1878ebd..8b151ef188 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -8,8 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_NS16550_MEM32 - /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ #define CONFIG_IRAM_BASE 0xff020000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 200b34b35b..263d1bd180 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,8 +8,6 @@ #include "rockchip-common.h" -#define CONFIG_SYS_NS16550_MEM32 - #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 4c964cc377..1f6b82f2d0 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -7,8 +7,6 @@ #define _ROCKCHIP_COMMON_H_ #include -#define CONFIG_SYS_NS16550_MEM32 - /* ((CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - 64) * 512) */ #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index d071f590f1..5765f2ccb5 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x44e09000 #define CONFIG_SYS_NS16550_COM4 0x481a6000 diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 0187fca5f0..c29bc448ee 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,11 +52,6 @@ * Serial */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index f712928d3c..49883ea7a3 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} /* diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 75d2081fac..7012097276 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,6 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 86cc3771ba..029f898b64 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -76,7 +76,6 @@ * Serial / UART configurations */ #define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_MEM32 /* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d9e4c8b699..1ed0a262bc 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -16,7 +16,6 @@ #include /* Serial & console */ -#define CONFIG_SYS_NS16550_SERIAL /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ @@ -25,7 +24,6 @@ #define CONFIG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE -4 # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 16bdc39b75..38a43b726f 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,6 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK 166666666 /* diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h index bb3186e219..663a49e7b6 100644 --- a/include/configs/theadorable-x86-dfi-bt700.h +++ b/include/configs/theadorable-x86-dfi-bt700.h @@ -13,7 +13,6 @@ #include /* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED /* Set the board specific parameters */ #define DEF_ENV_TFTPDIR "theadorable-x86-dfi" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 97166e010f..60632c58c6 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index efd3a0db04..f2dbe3544a 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,6 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK (48000000) #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 5d5df6b101..fb01777168 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,12 +17,6 @@ #include /* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#endif #define CONFIG_SYS_NS16550_CLK 48000000 /* diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index a4a45fad9d..aaeea77281 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,7 +34,6 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* UART Configuration */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 6cc443c8e9..80d2a011f0 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,10 +27,6 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* !CONFIG_DM_SERIAL */ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 0568946fc8..eb930341c3 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -29,8 +29,6 @@ */ #define CONFIG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM3 UART3_BASE #endif diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 24bbf9e7c2..a1efb57f1b 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -30,10 +30,6 @@ * Hardware drivers */ #define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* * Environment setup diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 6f36d6964b..84e5ba39f1 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,9 +19,7 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM3 0xb0000e00 /* RAM */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 0add626e81..318e3680a6 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,10 +13,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 8e22d6e5d8..f76c1f8be0 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -21,7 +21,6 @@ /*----------------------------------------------------------------------- * Serial Configuration */ -#define CONFIG_SYS_NS16550_PORT_MAPPED /* * Miscellaneous configurable options diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 58d01f4bb4..7090fcef68 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,8 +127,6 @@ /* Serial Driver Info */ /*====================*/ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ diff --git a/include/ns16550.h b/include/ns16550.h index 3d9002d9f1..0ee5c4d6de 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@ #include -#ifdef CONFIG_DM_SERIAL +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver From 91092132bac0ae768beb76c12ef8be732ea6ba3a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:28 -0500 Subject: [PATCH 014/424] global: Move remaining CONFIG_SYS_NS16550_* to CFG_SYS_NS16550_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 2 +- arch/arm/include/asm/arch-bcmcygnus/configs.h | 6 +- arch/arm/include/asm/arch-bcmnsp/configs.h | 4 +- .../asm/arch-fsl-layerscape/immap_lsch2.h | 8 +-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 4 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 4 +- arch/arm/mach-davinci/da850_lowlevel.c | 6 +- arch/arm/mach-davinci/spl.c | 4 +- arch/arm/mach-keystone/init.c | 4 +- arch/arm/mach-lpc32xx/devices.c | 8 +-- arch/arm/mach-omap2/am33xx/board.c | 32 +++++----- arch/arm/mach-tegra/board.c | 4 +- arch/powerpc/cpu/mpc85xx/fdt.c | 12 ++-- arch/powerpc/include/asm/config.h | 2 +- board/Synology/ds109/ds109.c | 10 +-- board/eets/pdu001/mux.c | 12 ++-- board/emulation/qemu-ppce500/qemu-ppce500.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 2 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 6 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 6 +- board/freescale/t102xrdb/spl.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/nokia/rx51/rx51.c | 4 +- drivers/serial/Kconfig | 2 +- drivers/serial/ns16550.c | 8 +-- drivers/serial/serial_mtk.c | 40 ++++++------ drivers/serial/serial_ns16550.c | 64 +++++++++---------- drivers/serial/serial_omap.c | 6 +- include/configs/MPC837XERDB.h | 6 +- include/configs/MPC8548CDS.h | 6 +- include/configs/P1010RDB.h | 6 +- include/configs/P2041RDB.h | 10 +-- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 10 +-- include/configs/T104xRDB.h | 10 +-- include/configs/T208xQDS.h | 10 +-- include/configs/T208xRDB.h | 10 +-- include/configs/T4240RDB.h | 10 +-- include/configs/am335x_evm.h | 12 ++-- include/configs/am335x_guardian.h | 12 ++-- include/configs/am335x_igep003x.h | 2 +- include/configs/am335x_shc.h | 12 ++-- include/configs/am335x_sl50.h | 12 ++-- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-tk1.h | 2 +- include/configs/apalis_t30.h | 2 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 2 +- include/configs/baltos.h | 12 ++-- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/beaver.h | 2 +- include/configs/bur_am335x_common.h | 4 +- include/configs/cardhu.h | 2 +- include/configs/cei-tk1-som.h | 2 +- include/configs/chiliboard.h | 12 ++-- include/configs/ci20.h | 2 +- include/configs/cm_t43.h | 4 +- include/configs/colibri_t20.h | 2 +- include/configs/colibri_t30.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/dalmore.h | 2 +- include/configs/dra7xx_evm.h | 6 +- .../configs/gardena-smart-gateway-mt7688.h | 4 +- include/configs/harmony.h | 4 +- include/configs/hsdk-4xd.h | 2 +- include/configs/hsdk.h | 2 +- include/configs/jetson-tk1.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron_sl28.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/linkit-smart-7688.h | 4 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/medcom-wide.h | 2 +- include/configs/mt7621.h | 4 +- include/configs/mt7628.h | 4 +- include/configs/mt8183.h | 4 +- include/configs/mt8516.h | 4 +- include/configs/mv-common.h | 4 +- include/configs/nokia_rx51.h | 4 +- include/configs/nyan-big.h | 2 +- include/configs/omap5_uevm.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/p1_p2_rdb_pc.h | 6 +- include/configs/paz00.h | 2 +- include/configs/pdu001.h | 12 ++-- include/configs/plutux.h | 2 +- include/configs/seaboard.h | 2 +- include/configs/siemens-am33x-common.h | 6 +- include/configs/sniper.h | 4 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/sunxi-common.h | 14 ++-- include/configs/tb100.h | 2 +- include/configs/tec-ng.h | 2 +- include/configs/tec.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/ti814x_evm.h | 4 +- include/configs/ti816x_evm.h | 4 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +-- include/configs/ti_omap3_common.h | 8 +-- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/trimslice.h | 2 +- include/configs/vcoreiii.h | 2 +- include/configs/venice2.h | 2 +- include/configs/ventana.h | 2 +- include/configs/vocore2.h | 4 +- include/configs/x530.h | 4 +- include/configs/xtfpga.h | 4 +- 134 files changed, 347 insertions(+), 347 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index c01cebbf98..0e7d5fa06d 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -125,7 +125,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif sysclk_path = fdt_get_alias(blob, "sysclk"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index ee734577fc..4f91db49ee 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -646,7 +646,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "fsl,ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 0c7262352d..fd8dad394a 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -11,8 +11,8 @@ /* uArchitecture specifics */ /* Serial Info */ -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_CLK_DIV 54 -#define CONFIG_SYS_NS16550_COM3 0x18023000 +#define CFG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK_DIV 54 +#define CFG_SYS_NS16550_COM3 0x18023000 #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h index 44699476b0..0d4baf3c00 100644 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ b/arch/arm/include/asm/arch-bcmnsp/configs.h @@ -11,7 +11,7 @@ /* uArchitecture specifics */ /* Serial Info */ -#define CONFIG_SYS_NS16550_CLK 0x03b9aca0 -#define CONFIG_SYS_NS16550_COM1 0x18000300 +#define CFG_SYS_NS16550_CLK 0x03b9aca0 +#define CFG_SYS_NS16550_COM1 0x18000300 #endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index e8bd8d2713..aef6158733 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -26,10 +26,10 @@ #define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index f1ffb2327d..bad18d778a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -35,8 +35,8 @@ #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 #define CFG_SYS_FSL_TIMER_ADDR 0x023e0000 #define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \ diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 5dd90b47f9..6de431f6bb 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -19,8 +19,8 @@ #endif #endif -#if !defined(CONFIG_SYS_NS16550_CLK) -#define CONFIG_SYS_NS16550_CLK 13000000 +#if !defined(CFG_SYS_NS16550_CLK) +#define CFG_SYS_NS16550_CLK 13000000 #endif #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index e85918eb7e..033341dbfb 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -30,8 +30,8 @@ #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 759c93747c..2319ac6d56 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -290,8 +290,8 @@ int arch_cpu_init(void) board_gpio_init(); #if !CONFIG_IS_ENABLED(DM_SERIAL) - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM1), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif /* * Fix Power and Emulation Management Register @@ -299,7 +299,7 @@ int arch_cpu_init(void) */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), -#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) +#if (CFG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) &davinci_uart0_ctrl_regs->pwremu_mgmt); #else &davinci_uart2_ctrl_regs->pwremu_mgmt); diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index 54aff78894..5f5b9ebbf9 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -27,9 +27,9 @@ void puts(const char *str) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r'); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), '\r'); - ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c); + ns16550_putc((struct ns16550 *)(CFG_SYS_NS16550_COM1), c); } #endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 5b95f60500..1954e69e9f 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -185,8 +185,8 @@ int arch_cpu_init(void) * driver doesn't handle this. */ #ifndef CONFIG_DM_SERIAL - ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + ns16550_init((struct ns16550 *)(CFG_SYS_NS16550_COM2), + CFG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); #endif return 0; diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 0a4fef295a..3fcf8facb4 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -44,13 +44,13 @@ void lpc32xx_uart_init(unsigned int uart_id) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat lpc32xx_uart[] = { { .base = UART3_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART4_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART5_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, { .base = UART6_BASE, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, }; #if defined(CONFIG_LPC32XX_HSUART) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index f393ff9144..44d5214a3d 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -87,29 +87,29 @@ int dram_init_banksize(void) #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct ns16550_plat am33xx_serial[] = { - { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM2 - { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, -# ifdef CONFIG_SYS_NS16550_COM3 - { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, - { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM2 + { .base = CFG_SYS_NS16550_COM2, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, +# ifdef CFG_SYS_NS16550_COM3 + { .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM4, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM5, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, + { .base = CFG_SYS_NS16550_COM6, .reg_shift = 2, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, # endif # endif }; U_BOOT_DRVINFOS(am33xx_uarts) = { { "ns16550_serial", &am33xx_serial[0] }, -# ifdef CONFIG_SYS_NS16550_COM2 +# ifdef CFG_SYS_NS16550_COM2 { "ns16550_serial", &am33xx_serial[1] }, -# ifdef CONFIG_SYS_NS16550_COM3 +# ifdef CFG_SYS_NS16550_COM3 { "ns16550_serial", &am33xx_serial[2] }, { "ns16550_serial", &am33xx_serial[3] }, { "ns16550_serial", &am33xx_serial[4] }, diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 95d6555a0d..f8b61a2b3e 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -259,9 +259,9 @@ void board_init_uart_f(void) #if !CONFIG_IS_ENABLED(OF_CONTROL) static struct ns16550_plat ns16550_com1_pdata = { - .base = CONFIG_SYS_NS16550_COM1, + .base = CFG_SYS_NS16550_COM1, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 1161938d30..6dd61caf1c 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -649,7 +649,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); + "clock-frequency", CFG_SYS_NS16550_CLK, 1); #endif #ifdef CONFIG_FSL_CORENET @@ -751,7 +751,7 @@ static void msg(const char *name, uint64_t uaddr, uint64_t daddr) * This function compares several CONFIG_xxx macros that contain physical * addresses with the corresponding nodes in the device tree, to see if * the physical addresses are all correct. For example, if - * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address + * CFG_SYS_NS16550_COM1 is defined, then it contains the virtual address * of the first UART. We convert this to a physical address and compare * that with the physical address of the first ns16550-compatible node * in the device tree. If they don't match, then we display a warning. @@ -796,15 +796,15 @@ int ft_verify_fdt(void *fdt) */ aliases = fdt_path_offset(fdt, "/aliases"); if (aliases > 0) { -#ifdef CONFIG_SYS_NS16550_COM1 +#ifdef CFG_SYS_NS16550_COM1 if (!fdt_verify_alias_address(fdt, aliases, "serial0", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM1))) return 0; #endif -#ifdef CONFIG_SYS_NS16550_COM2 +#ifdef CFG_SYS_NS16550_COM2 if (!fdt_verify_alias_address(fdt, aliases, "serial1", - CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2))) + CCSR_VIRT_TO_PHYS(CFG_SYS_NS16550_COM2))) return 0; #endif } diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 79fe567b58..b0ad7d7aa7 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -52,7 +52,7 @@ * TODO: Convert this to a clock driver exists that can give us the UART * clock here. */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/board/Synology/ds109/ds109.c b/board/Synology/ds109/ds109.c index 9e7f6ac6c7..5c3f46e23f 100644 --- a/board/Synology/ds109/ds109.c +++ b/board/Synology/ds109/ds109.c @@ -101,17 +101,17 @@ int board_init(void) #include #define SOFTWARE_SHUTDOWN 0x31 #define SOFTWARE_REBOOT 0x43 -#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE +#define CFG_SYS_NS16550_COM2 KW_UART1_BASE void reset_misc(void) { int b_d; printf("Synology reset..."); udelay(50000); - b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2, - CONFIG_SYS_NS16550_CLK, 9600); - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2, + b_d = ns16550_calc_divisor((struct ns16550 *)CFG_SYS_NS16550_COM2, + CFG_SYS_NS16550_CLK, 9600); + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM2, b_d); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM2, SOFTWARE_REBOOT); } diff --git a/board/eets/pdu001/mux.c b/board/eets/pdu001/mux.c index f0f9e262eb..886fef60b0 100644 --- a/board/eets/pdu001/mux.c +++ b/board/eets/pdu001/mux.c @@ -92,22 +92,22 @@ void enable_uart5_pin_mux(void) void enable_uart_pin_mux(u32 addr) { switch (addr) { - case CONFIG_SYS_NS16550_COM1: + case CFG_SYS_NS16550_COM1: enable_uart0_pin_mux(); break; - case CONFIG_SYS_NS16550_COM2: + case CFG_SYS_NS16550_COM2: enable_uart1_pin_mux(); break; - case CONFIG_SYS_NS16550_COM3: + case CFG_SYS_NS16550_COM3: enable_uart2_pin_mux(); break; - case CONFIG_SYS_NS16550_COM4: + case CFG_SYS_NS16550_COM4: enable_uart3_pin_mux(); break; - case CONFIG_SYS_NS16550_COM5: + case CFG_SYS_NS16550_COM5: enable_uart4_pin_mux(); break; - case CONFIG_SYS_NS16550_COM6: + case CFG_SYS_NS16550_COM6: enable_uart5_pin_mux(); break; } diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index 99edaa3b42..a4254250bb 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -343,7 +343,7 @@ void *board_fdt_blob_setup(int *err) return get_fdt_virt(); } -/* See CONFIG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ +/* See CFG_SYS_NS16550_CLK in arch/powerpc/include/asm/config.h */ int get_serial_clock(void) { return get_bus_freq(0); diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index c39df462e3..ab3b2e3e69 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -587,7 +587,7 @@ void fdt_disable_uart1(void *blob) int nodeoff; nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550", - CONFIG_SYS_NS16550_COM2); + CFG_SYS_NS16550_COM2); if (nodeoff > 0) { fdt_status_disabled(blob, nodeoff); diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 0db11f4c5f..9bf948cb5c 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -45,7 +45,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 9cd46c9664..8f0dec4c0a 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -32,7 +32,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); @@ -54,9 +54,9 @@ void board_init_r(gd_t *gd, ulong dest_addr) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); } void puts(const char *str) diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index e7d4428d7c..6c3f82849e 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -57,7 +57,7 @@ void board_init_f(ulong bootflag) bus_clk = get_board_sys_clk() * plat_ratio; gd->bus_clk = bus_clk; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 2fd8a28743..f9e0b5b25a 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -31,7 +31,7 @@ void board_init_f(ulong bootflag) plat_ratio >>= 1; gd->bus_clk = get_board_sys_clk() * plat_ratio; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); puts("\nNAND boot... "); @@ -52,9 +52,9 @@ void board_init_r(gd_t *gd, ulong dest_addr) void putc(char c) { if (c == '\n') - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r'); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, '\r'); - ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c); + ns16550_putc((struct ns16550 *)CFG_SYS_NS16550_COM1, c); } void puts(const char *str) diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 3ba94fecaa..9faf259af7 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -73,7 +73,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); #if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index c7fb4272c6..66a142b3ad 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -72,7 +72,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; uart_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, uart_clk / 16 / CONFIG_BAUDRATE); relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 8b68329b98..8866be54a6 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -82,7 +82,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); #if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 3f9b1faa85..130cb8847c 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -42,7 +42,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); #if defined(CONFIG_SPL_MMC_BOOT) diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 72d3b80b19..779457d296 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -51,7 +51,7 @@ void board_init_f(ulong bootflag) plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; ccb_clk = sys_clk * plat_ratio / 2; - ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1, + ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1, ccb_clk / 16 / CONFIG_BAUDRATE); puts("\nSD boot...\n"); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index c1b4b91b60..fa95886fa3 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -795,9 +795,9 @@ U_BOOT_DRVINFOS(rx51_kp) = { }; static const struct ns16550_plat rx51_serial = { - .base = CONFIG_SYS_NS16550_COM3, + .base = CFG_SYS_NS16550_COM3, .reg_shift = 2, - .clock = CONFIG_SYS_NS16550_CLK, + .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 4978a65715..14b0febd1a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -737,7 +737,7 @@ config SYS_NS16550 Support NS16550 UART or compatible. This can be enabled in the device tree with the correct input clock frequency. If the input clock frequency is not defined in the device tree, the macro - CONFIG_SYS_NS16550_CLK defined in a legacy board header file will + CFG_SYS_NS16550_CLK defined in a legacy board header file will be used. It can be a constant or a function to get clock, eg, get_serial_clock(). diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 5a693d2f02..772dd6fef8 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -92,8 +92,8 @@ static inline int serial_in_shift(void *addr, int shift) #if CONFIG_IS_ENABLED(DM_SERIAL) -#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK 0 #endif /* @@ -567,9 +567,9 @@ int ns16550_serial_of_to_plat(struct udevice *dev) if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", - CONFIG_SYS_NS16550_CLK); + CFG_SYS_NS16550_CLK); if (!plat->clock) - plat->clock = CONFIG_SYS_NS16550_CLK; + plat->clock = CFG_SYS_NS16550_CLK; if (!plat->clock) { debug("ns16550 clock not defined\n"); return -EINVAL; diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 03b9e86bfc..6fb4cb65c2 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -284,8 +284,8 @@ DECLARE_GLOBAL_DATA_PTR; #define DECLARE_HSUART_PRIV(port) \ static struct mtk_serial_priv mtk_hsuart##port = { \ - .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \ - .fixed_clk_rate = CONFIG_SYS_NS16550_CLK \ + .regs = (struct mtk_serial_regs *)CFG_SYS_NS16550_COM##port, \ + .fixed_clk_rate = CFG_SYS_NS16550_CLK \ }; #define DECLARE_HSUART_FUNCTIONS(port) \ @@ -356,36 +356,36 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif -#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." -#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) #error "Console port 5 defined but not configured." -#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) #error "Console port 6 defined but not configured." #endif -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) DECLARE_HSUART(1, "mtk-hsuart0"); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) DECLARE_HSUART(2, "mtk-hsuart1"); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) DECLARE_HSUART(3, "mtk-hsuart2"); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) DECLARE_HSUART(4, "mtk-hsuart3"); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) DECLARE_HSUART(5, "mtk-hsuart4"); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) DECLARE_HSUART(6, "mtk-hsuart5"); #endif @@ -410,22 +410,22 @@ __weak struct serial_device *default_serial_console(void) void mtk_serial_initialize(void) { -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) serial_register(&mtk_hsuart1_device); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) serial_register(&mtk_hsuart2_device); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) serial_register(&mtk_hsuart3_device); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) serial_register(&mtk_hsuart4_device); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) serial_register(&mtk_hsuart5_device); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) serial_register(&mtk_hsuart6_device); #endif } diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index 76aa1e5afb..4014f68204 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -20,17 +20,17 @@ DECLARE_GLOBAL_DATA_PTR; #error "Invalid console index value." #endif -#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1) +#if CONFIG_CONS_INDEX == 1 && !defined(CFG_SYS_NS16550_COM1) #error "Console port 1 defined but not configured." -#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2) +#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_SYS_NS16550_COM2) #error "Console port 2 defined but not configured." -#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3) +#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_SYS_NS16550_COM3) #error "Console port 3 defined but not configured." -#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4) +#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_SYS_NS16550_COM4) #error "Console port 4 defined but not configured." -#elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5) +#elif CONFIG_CONS_INDEX == 5 && !defined(CFG_SYS_NS16550_COM5) #error "Console port 5 defined but not configured." -#elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6) +#elif CONFIG_CONS_INDEX == 6 && !defined(CFG_SYS_NS16550_COM6) #error "Console port 6 defined but not configured." #endif @@ -38,33 +38,33 @@ DECLARE_GLOBAL_DATA_PTR; * the array is 0 based. */ static struct ns16550 *serial_ports[6] = { -#ifdef CONFIG_SYS_NS16550_COM1 - (struct ns16550 *)CONFIG_SYS_NS16550_COM1, +#ifdef CFG_SYS_NS16550_COM1 + (struct ns16550 *)CFG_SYS_NS16550_COM1, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM2 - (struct ns16550 *)CONFIG_SYS_NS16550_COM2, +#ifdef CFG_SYS_NS16550_COM2 + (struct ns16550 *)CFG_SYS_NS16550_COM2, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM3 - (struct ns16550 *)CONFIG_SYS_NS16550_COM3, +#ifdef CFG_SYS_NS16550_COM3 + (struct ns16550 *)CFG_SYS_NS16550_COM3, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM4 - (struct ns16550 *)CONFIG_SYS_NS16550_COM4, +#ifdef CFG_SYS_NS16550_COM4 + (struct ns16550 *)CFG_SYS_NS16550_COM4, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM5 - (struct ns16550 *)CONFIG_SYS_NS16550_COM5, +#ifdef CFG_SYS_NS16550_COM5 + (struct ns16550 *)CFG_SYS_NS16550_COM5, #else NULL, #endif -#ifdef CONFIG_SYS_NS16550_COM6 - (struct ns16550 *)CONFIG_SYS_NS16550_COM6 +#ifdef CFG_SYS_NS16550_COM6 + (struct ns16550 *)CFG_SYS_NS16550_COM6 #else NULL #endif @@ -78,7 +78,7 @@ static struct ns16550 *serial_ports[6] = { { \ int clock_divisor; \ clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \ - CONFIG_SYS_NS16550_CLK, gd->baudrate); \ + CFG_SYS_NS16550_CLK, gd->baudrate); \ ns16550_init(serial_ports[port - 1], clock_divisor); \ return 0 ; \ } \ @@ -144,7 +144,7 @@ static void _serial_setbrg(const int port) { int clock_divisor; - clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK, + clock_divisor = ns16550_calc_divisor(PORT, CFG_SYS_NS16550_CLK, gd->baudrate); ns16550_reinit(PORT, clock_divisor); } @@ -179,32 +179,32 @@ serial_setbrg_dev(unsigned int dev_index) _serial_setbrg(dev_index); } -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) DECLARE_ESERIAL_FUNCTIONS(1); struct serial_device eserial1_device = INIT_ESERIAL_STRUCTURE(1, "eserial0"); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) DECLARE_ESERIAL_FUNCTIONS(2); struct serial_device eserial2_device = INIT_ESERIAL_STRUCTURE(2, "eserial1"); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) DECLARE_ESERIAL_FUNCTIONS(3); struct serial_device eserial3_device = INIT_ESERIAL_STRUCTURE(3, "eserial2"); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) DECLARE_ESERIAL_FUNCTIONS(4); struct serial_device eserial4_device = INIT_ESERIAL_STRUCTURE(4, "eserial3"); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) DECLARE_ESERIAL_FUNCTIONS(5); struct serial_device eserial5_device = INIT_ESERIAL_STRUCTURE(5, "eserial4"); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) DECLARE_ESERIAL_FUNCTIONS(6); struct serial_device eserial6_device = INIT_ESERIAL_STRUCTURE(6, "eserial5"); @@ -231,22 +231,22 @@ __weak struct serial_device *default_serial_console(void) void ns16550_serial_initialize(void) { -#if defined(CONFIG_SYS_NS16550_COM1) +#if defined(CFG_SYS_NS16550_COM1) serial_register(&eserial1_device); #endif -#if defined(CONFIG_SYS_NS16550_COM2) +#if defined(CFG_SYS_NS16550_COM2) serial_register(&eserial2_device); #endif -#if defined(CONFIG_SYS_NS16550_COM3) +#if defined(CFG_SYS_NS16550_COM3) serial_register(&eserial3_device); #endif -#if defined(CONFIG_SYS_NS16550_COM4) +#if defined(CFG_SYS_NS16550_COM4) serial_register(&eserial4_device); #endif -#if defined(CONFIG_SYS_NS16550_COM5) +#if defined(CFG_SYS_NS16550_COM5) serial_register(&eserial5_device); #endif -#if defined(CONFIG_SYS_NS16550_COM6) +#if defined(CFG_SYS_NS16550_COM6) serial_register(&eserial6_device); #endif } diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index e9ff61a0ba..904f7d21bf 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -15,8 +15,8 @@ #include #include -#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK 0 #endif #ifdef CONFIG_DEBUG_UART_OMAP @@ -128,7 +128,7 @@ static int omap_serial_of_to_plat(struct udevice *dev) if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", - CONFIG_SYS_NS16550_CLK); + CFG_SYS_NS16550_CLK); if (!plat->clock) { debug("omap serial clock not defined\n"); return -EINVAL; diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index b8cbdc3675..059885ecb5 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -151,13 +151,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ #define CONFIG_FSL_SERDES diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index dba15dae74..bde8fa8df4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -235,13 +235,13 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* * I2C diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index fd721f30b3..05c097759f 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -322,13 +322,13 @@ extern unsigned long get_sdram_size(void); /* Serial Port */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ #define I2C_PCA9557_ADDR1 0x18 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 173f6205e0..132786a423 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -163,15 +163,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index c99e6ba781..824190a412 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,8 +12,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* * Serial Port configuration diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 8b43fe0c99..e67da1fe1d 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,8 +12,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* * Serial Port configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 7cb10b205d..b8f3d70e59 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,15 +294,15 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 3fa2d01dcc..777a64ecee 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -267,15 +267,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index c5a28fadb0..710f105cfa 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -269,13 +269,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* * I2C diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 795120c02a..4c60364f7e 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -229,13 +229,13 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* * I2C diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index e3cbc649fa..ba4a989fc5 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -89,15 +89,15 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) /* I2C */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 13b1ff3bce..25d9c96e16 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -158,12 +158,12 @@ #endif /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index cb649b598f..7c5e7ce475 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -83,12 +83,12 @@ #define CONSOLE_COLOR_RED 0x001F /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #ifdef CONFIG_MTD_RAW_NAND #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index b7b1cb0cfe..abd868c145 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -88,7 +88,7 @@ "echo WARNING: Could not determine device tree to use; fi; \0" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ /* Ethernet support */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 08bae9b886..452887d699 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -136,11 +136,11 @@ #endif /* Regular Boot */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 7df5f14055..4af9edafca 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -36,12 +36,12 @@ BOOTENV /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index b61c8005c3..4ff8528cf8 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -14,7 +14,7 @@ #include /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* I2C Configuration */ @@ -41,7 +41,7 @@ #define V_SCLK (V_OSCK) /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #ifndef CONFIG_SPL_BUILD /* USB Device Firmware Update support */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index d8b0531673..c3b6a3fbda 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -16,9 +16,9 @@ #define CONFIG_IODELAY_RECALIBRATION -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 0eed8db23b..3114cf0c4f 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* Miscellaneous configurable options */ diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 7124711119..f0674456fd 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* Miscellaneous configurable options */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 6a4092a83e..f0a02ae179 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -14,7 +14,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 84bd88f835..4f00b3bad3 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -21,7 +21,7 @@ * Apalis UART4: NVIDIA UARTC */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 7224bd8d1f..e3b6956eb5 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -33,7 +33,7 @@ /* * Serial console configuration */ -#define CONFIG_SYS_NS16550_CLK 19660800 +#define CFG_SYS_NS16550_CLK 19660800 /* Init Stack Pointer */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index c0429ae15c..1932713f45 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -26,7 +26,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33333333 +#define CFG_SYS_NS16550_CLK 33333333 /* * Ethernet PHY configuration diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 31f107a465..f29729d09b 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -181,12 +181,12 @@ /*DFUARGS*/ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* PMIC support */ #define CONFIG_POWER_TPS65910 diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index 1bae49e15f..cba109b74a 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_NS16550_COM1 0xf040c000 +#define CFG_SYS_NS16550_COM1 0xf040c000 #define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index 4b41dc220b..a07f1b7ad0 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_NS16550_COM1 0xf040ab00 +#define CFG_SYS_NS16550_COM1 0xf040ab00 #define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 795de46938..76189a4d31 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -26,7 +26,7 @@ /* 12MB Malloc size */ /* console configuration */ -#define CONFIG_SYS_NS16550_CLK 25000000 +#define CFG_SYS_NS16550_CLK 25000000 /* * Increase max uncompressed/gunzip size, keeping size same as EMMC linux diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 481baff11d..9f51b9ca59 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -97,7 +97,7 @@ extern phys_addr_t prior_stage_fdt_address; */ #define V_NS16550_CLK 81000000 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK /* * Serial console configuration. diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 1d51bb4e4c..6b5f650811 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -18,7 +18,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 773ce3f6a6..1bf6baf75c 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -14,8 +14,8 @@ /* legacy #defines for non DM bur-board */ #ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 #endif /* CONFIG_DM */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index f3416b534b..35c5a4f122 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -22,7 +22,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_TEGRA_SLINK_CTRLS 6 diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 0672b7dbbe..55e2d744c4 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -20,7 +20,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index bfa076b5cc..1e5154af0a 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -97,12 +97,12 @@ NANDARGS /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ +#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ /* SPL */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 63dac1d4a7..b7511adc09 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* Ethernet: davicom DM9000 */ #define CONFIG_DM9000_BASE 0xb6000000 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 0641d5c0a2..8f058213e9 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -14,8 +14,8 @@ #include /* Serial support */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_COM1 0x44e09000 /* NAND support */ #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index b758086b86..2ba3c3bc87 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -13,7 +13,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* NAND support */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index c9d384e2bd..ffed71a2e8 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -22,7 +22,7 @@ * Colibri UART-C: NVIDIA UARTB */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index f8ba4e8281..4f0188dd19 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -94,7 +94,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index e03a24adca..24cf554649 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -15,7 +15,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 93201be485..e1d18a7783 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -27,9 +27,9 @@ #elif (CONFIG_CONS_INDEX == 3) #define CONSOLEDEV "ttyS2" #endif -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index 0d61724db8..a1400eba1a 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -20,8 +20,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif /* UART */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index fe4b02c0ce..211dab4d23 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -17,10 +17,10 @@ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #ifdef CONFIG_TEGRA_ENABLE_UARTA /* UARTA: debug board UART */ -#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE #endif /* NAND support */ diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index bfc0fa5c44..1d7b171da7 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -28,7 +28,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33330000 +#define CFG_SYS_NS16550_CLK 33330000 /* * Ethernet PHY configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index ce3cb20732..9e092e16ea 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -27,7 +27,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 33330000 +#define CFG_SYS_NS16550_CLK 33330000 /* * Ethernet PHY configuration diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 69aa55f86c..b846889541 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7acdb0fa03..57b0fc9069 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -148,7 +148,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* * I2C diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 30ba606525..e6e54fba89 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -330,8 +330,8 @@ * Retain non-DM serial port for debug purposes. */ #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) #endif #ifndef __ASSEMBLY__ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 38860bfd5c..7ed1f153c2 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -35,7 +35,7 @@ #define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE /* serial port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* SPL */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 5434c4f767..1f642fbecc 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -36,7 +36,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index b9c853d7df..28372d4159 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -20,8 +20,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00 #endif diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 148598fab4..b57eb52d14 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -26,7 +26,7 @@ /* GPIO */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3f2dfa640c..3579f9c843 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -47,7 +47,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* * I2C diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bd2f74c126..45665115f6 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -227,7 +227,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 8c43f652ab..1e2db12a83 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() /* I2C */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 06830f401a..323feb6e33 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -145,7 +145,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 7dd5649005..587f23be58 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,7 +28,7 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* Miscellaneous configurable options */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 2fc06c1dd2..6fc509af23 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -40,7 +40,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 40b4cb964d..8a3c87c6ab 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -40,7 +40,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* SD boot SPL */ #ifdef CONFIG_SD_BOOT diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 5668e07d13..2117b08116 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -45,7 +45,7 @@ /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) /* * During booting, IFC is mapped at the region of 0x30000000. diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 895c566fea..c79a50795b 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -37,7 +37,7 @@ /* I2C */ /* Serial Port */ -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) +#define CFG_SYS_NS16550_CLK (get_serial_clock()) /* * During booting, IFC is mapped at the region of 0x30000000. diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index b90a84da8a..a8d8d8b09e 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1f733d112d..e09e9c82eb 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -22,8 +22,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 50000000 -#define CONFIG_SYS_NS16550_COM1 0xbe000c00 +#define CFG_SYS_NS16550_CLK 50000000 +#define CFG_SYS_NS16550_COM1 0xbe000c00 #endif /* Serial common */ diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index da16e3b21a..bb12ebfe4f 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -14,8 +14,8 @@ /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM1 0xb0000c00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM1 0xb0000c00 #endif /* Serial common */ diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index eaffe0bf4c..3da7619d78 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -12,8 +12,8 @@ #include -#define CONFIG_SYS_NS16550_COM1 0x11005200 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005200 +#define CFG_SYS_NS16550_CLK 26000000 /* Environment settings */ #include diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 347598868b..0f7981a566 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -12,8 +12,8 @@ #include -#define CONFIG_SYS_NS16550_COM1 0x11005000 -#define CONFIG_SYS_NS16550_CLK 26000000 +#define CFG_SYS_NS16550_COM1 0x11005000 +#define CFG_SYS_NS16550_CLK 26000000 /* Environment settings */ #include diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 4f1067c23b..e870fc810c 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,9 +32,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif #if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 310bdde7cb..2623f99f8d 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -40,12 +40,12 @@ */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK /* * select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index c59e103243..baa452156e 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ #define CONFIG_SPI_FLASH_SIZE (4 << 20) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index cce5556fe2..883cc0b99c 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -28,7 +28,7 @@ #include -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE /* MMC ENV related defines */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 81ca68de9b..2b47d4ca37 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -91,7 +91,7 @@ /* * Serial Driver info */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) +#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 065820689c..9fc22f0a6c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -319,13 +319,13 @@ * shorted - index 1 */ #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) diff --git a/include/configs/paz00.h b/include/configs/paz00.h index c12f4d0937..a945f4e9b2 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -17,7 +17,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index ed3201aa3c..7180783767 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -50,11 +50,11 @@ "\0" /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 UART2_BASE -#define CONFIG_SYS_NS16550_COM4 UART3_BASE -#define CONFIG_SYS_NS16550_COM5 UART4_BASE -#define CONFIG_SYS_NS16550_COM6 UART5_BASE +#define CFG_SYS_NS16550_COM1 UART0_BASE +#define CFG_SYS_NS16550_COM2 UART1_BASE +#define CFG_SYS_NS16550_COM3 UART2_BASE +#define CFG_SYS_NS16550_COM4 UART3_BASE +#define CFG_SYS_NS16550_COM5 UART4_BASE +#define CFG_SYS_NS16550_COM6 UART5_BASE #endif /* ! __CONFIG_PDU001_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 09f0ed9b9a..99db59c489 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index c7f03a1e75..4887747968 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -22,7 +22,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5765f2ccb5..c9dd7509cb 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -38,9 +38,9 @@ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_NS16550_COM4 0x481a6000 +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x44e09000 +#define CFG_SYS_NS16550_COM4 0x481a6000 /* I2C Configuration */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index c29bc448ee..6054fa42c1 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -52,8 +52,8 @@ * Serial */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 029f898b64..2b2d78b8c8 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -75,7 +75,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000 /* * SDMMC configurations diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1ed0a262bc..cd2a74fb52 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -19,16 +19,16 @@ /* ns16550 reg in the low bits of cpu reg */ #ifdef CONFIG_MACH_SUNIV /* suniv doesn't have apb2 and uart is connected to apb1 */ -#define CONFIG_SYS_NS16550_CLK 100000000 +#define CFG_SYS_NS16550_CLK 100000000 #else -#define CONFIG_SYS_NS16550_CLK 24000000 +#define CFG_SYS_NS16550_CLK 24000000 #endif #ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE -# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE -# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE -# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE -# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE +# define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE +# define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE +# define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE +# define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE +# define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE #endif /* CPU */ diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 38a43b726f..92ee920346 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -19,7 +19,7 @@ /* * UART configuration */ -#define CONFIG_SYS_NS16550_CLK 166666666 +#define CFG_SYS_NS16550_CLK 166666666 /* * Even though the board houses Realtek RTL8211E PHY diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index f8e741ab6f..0987966370 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -14,7 +14,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 2377b47e05..ddf753da4a 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2915db7f8b..92df457e81 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -26,7 +26,7 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK #ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 60632c58c6..9614fe686f 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -77,8 +77,8 @@ #define CONFIG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ /* CPU */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index f2dbe3544a..1bd2a1874b 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -30,8 +30,8 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ +#define CFG_SYS_NS16550_CLK (48000000) +#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ /* allow overwriting serial config and ethaddr */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index fb01777168..00eb329faa 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -17,7 +17,7 @@ #include /* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* * SPL related defines. The Public RAM memory map the ROM defines the diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index aaeea77281..119b4c0410 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -34,13 +34,13 @@ #define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) /* UART Configuration */ -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CFG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CFG_SYS_NS16550_COM2 KS2_UART1_BASE #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 +#define CFG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 #endif /* SPI Configuration */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 80d2a011f0..d282c3956e 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -26,15 +26,15 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CFG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* Select serial console configuration */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CFG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CFG_SYS_NS16550_COM2 OMAP34XX_UART2 +#define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 #endif /* Physical Memory Map */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index eb930341c3..ce50e35d8d 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -27,9 +27,9 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CFG_SYS_NS16550_COM3 UART3_BASE #endif /* TWL6030 */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index a1efb57f1b..c49c177390 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -29,7 +29,7 @@ /* * Hardware drivers */ -#define CONFIG_SYS_NS16550_CLK 48000000 +#define CFG_SYS_NS16550_CLK 48000000 /* * Environment setup diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index b14726ad23..22d783c325 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -14,7 +14,7 @@ /* * Serial Port */ -#define CONFIG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_CLK 40000000 /* * Command diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b562d44a13..e4cbc7da84 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_TEGRA_UARTA_GPU -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 02ddc6fb6e..338d8af8fb 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ +#define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 03aa7adcc0..b2dc04a975 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -16,7 +16,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 0bd5a1e852..f7a507768e 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -15,7 +15,7 @@ /* Board-specific serial config */ #define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 84e5ba39f1..2107bec658 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -19,8 +19,8 @@ #define CONFIG_SYS_UBOOT_BASE 0 /* Serial SPL */ -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_NS16550_COM3 0xb0000e00 +#define CFG_SYS_NS16550_CLK 40000000 +#define CFG_SYS_NS16550_COM3 0xb0000e00 /* RAM */ diff --git a/include/configs/x530.h b/include/configs/x530.h index 318e3680a6..a0162cab21 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,9 +13,9 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE +#define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif /* diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 7090fcef68..b93451cbe0 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -127,10 +127,10 @@ /* Serial Driver Info */ /*====================*/ -#define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ +#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ -#define CONFIG_SYS_NS16550_CLK get_board_sys_clk() +#define CFG_SYS_NS16550_CLK get_board_sys_clk() /*======================*/ /* Ethernet Driver Info */ From cdc5ed8f1f2add27105151ecf61a07c5d4c3684a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:29 -0500 Subject: [PATCH 015/424] global: Move remaining CONFIG_SYS_NUM_* to CFG_SYS_NUM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NUM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 4 +- .../include/asm/arch-fsl-layerscape/config.h | 12 +-- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 +- arch/powerpc/cpu/mpc85xx/fdt.c | 4 +- arch/powerpc/cpu/mpc85xx/liodn.c | 6 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 6 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 4 +- arch/powerpc/include/asm/config_mpc85xx.h | 80 +++++++++---------- arch/powerpc/include/asm/fsl_portals.h | 2 +- board/freescale/ls1043aqds/eth.c | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/eth.c | 2 +- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/p2041rdb/eth.c | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 4 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 4 +- board/freescale/t4rdb/eth.c | 12 +-- board/freescale/t4rdb/t4rdb.h | 8 +- cmd/i2c.c | 6 +- drivers/i2c/i2c_core.c | 6 +- drivers/misc/fsl_portals.c | 2 +- drivers/net/fm/fm.c | 2 +- drivers/net/fm/fm.h | 4 +- drivers/net/fm/init.c | 48 +++++------ include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/km/km-mpc83xx.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 2 +- include/e500.h | 2 +- include/fm_eth.h | 6 +- include/i2c.h | 2 +- 43 files changed, 138 insertions(+), 138 deletions(-) diff --git a/README b/README index 9086207954..efb1d37df9 100644 --- a/README +++ b/README @@ -923,7 +923,7 @@ The following options need to be configured: with a list of GPIO LEDs that have inverted polarity. - I2C Support: - CONFIG_SYS_NUM_I2C_BUSES + CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. CONFIG_SYS_I2C_DIRECT_BUS @@ -940,7 +940,7 @@ The following options need to be configured: hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and - CONFIG_SYS_NUM_I2C_BUSES = 9: + CFG_SYS_NUM_I2C_BUSES = 9: CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ff752c21b1..0669222fed 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -209,9 +209,9 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 7 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -255,9 +255,9 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index aef6158733..c11018d732 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -160,7 +160,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif unsigned long freq_qman; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index bad18d778a..a4e971ebbd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -306,7 +306,7 @@ struct sys_info { unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 49a1aac42b..b0363c9c10 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -264,7 +264,7 @@ int checkcpu (void) #endif #ifdef CONFIG_SYS_DPAA_FMAN - for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + for (i = 0; i < CFG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 47bea512c9..2c320b202e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -162,7 +162,7 @@ void disable_cpc_sram(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); @@ -232,7 +232,7 @@ void enable_cpc(void) have_hwconfig = true; } - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (have_hwconfig) { sprintf(cpc_subarg, "cpc%u", i + 1); cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer); @@ -273,7 +273,7 @@ static void invalidate_cpc(void) int i; cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR; - for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { + for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { /* skip CPC when it used as all SRAM */ if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) continue; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 6dd61caf1c..32348b4e14 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -167,7 +167,7 @@ static inline void ft_fixup_l3cache(void *blob, int off) cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR; u32 cfg0 = in_be32(&cpc->cpccfg0); - size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; + size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC; num_ways = CPC_CFG0_NUM_WAYS(cfg0); line_size = CPC_CFG0_LINE_SZ(cfg0); num_sets = size / (line_size * num_ways); @@ -469,7 +469,7 @@ static void ft_fixup_dpaa_clks(void *blob) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET, sysinfo.freq_fman[0]); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET, sysinfo.freq_fman[1]); #endif diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 9ad48d440f..abc14fae4e 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -104,7 +104,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, fm = (void *)CFG_SYS_FSL_FM1_ADDR; break; -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) case FSL_HW_PORTAL_FMAN2: fm = (void *)CFG_SYS_FSL_FM2_ADDR; break; @@ -201,7 +201,7 @@ void set_liodns(void) setup_fman_liodn_base(FSL_HW_PORTAL_FMAN1, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) set_fman_liodn(fman2_liodn_tbl, fman2_liodn_tbl_sz); setup_fman_liodn_base(FSL_HW_PORTAL_FMAN2, fman2_liodn_tbl, fman2_liodn_tbl_sz); @@ -373,7 +373,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_liodn_tbl_fman(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) fdt_fixup_liodn_tbl_fman(blob, fman2_liodn_tbl, fman2_liodn_tbl_sz); #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 8a83346678..2b790868e1 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -66,7 +66,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 2, 12), SET_FMAN_RX_1G_LIODN(1, 3, 13), SET_FMAN_RX_1G_LIODN(1, 4, 14), -#if (CONFIG_SYS_NUM_FM1_10GEC == 1) +#if (CFG_SYS_NUM_FM1_10GEC == 1) SET_FMAN_RX_10G_LIODN(1, 0, 15), #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 5b766f1d51..ba54b0310a 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -62,7 +62,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 16), SET_FMAN_RX_1G_LIODN(2, 1, 17), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(96, 106), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(64), #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index e3d163af9e..6f11c81aba 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -57,7 +57,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 17), SET_FMAN_RX_1G_LIODN(2, 1, 18), @@ -101,7 +101,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32), #endif -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160), #endif #ifdef CONFIG_SYS_FSL_RAID_ENGINE diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 31d0481927..e2bdc2f9f1 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -406,7 +406,7 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_fman[0] = sys_info->freq_systembus / 2; break; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 #ifdef CONFIG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 @@ -440,7 +440,7 @@ void get_sys_info(sys_info_t *sys_info) break; } #endif -#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CFG_SYS_NUM_FMAN == 2 */ #else sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; #endif @@ -491,7 +491,7 @@ void get_sys_info(sys_info_t *sys_info) } else { sys_info->freq_fman[0] = sys_info->freq_systembus / 2; } -#if (CONFIG_SYS_NUM_FMAN) == 2 +#if (CFG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) { if (rcw_tmp & HWA_ASYNC_DIV) sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4; diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 172dbdbe46..8fe4e96a11 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -122,7 +122,7 @@ struct fman_liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_10G_LIODN(1, 1, 95), }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) struct fman_liodn_id_table fman2_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(2, 0, 88), SET_FMAN_RX_1G_LIODN(2, 1, 89), @@ -175,7 +175,7 @@ struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069), #endif #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 25d1b48617..2edf0d6f83 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -41,8 +41,8 @@ #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_P1023) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 2 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 2 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 @@ -65,9 +65,9 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -75,9 +75,9 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P3041) -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -85,11 +85,11 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 @@ -98,11 +98,11 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 #elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 5 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 5 +#define CFG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 @@ -119,21 +119,21 @@ #elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 2 #else -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FM2_DTSEC 8 +#define CFG_SYS_NUM_FM2_10GEC 1 #endif #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 -#define CONFIG_SYS_NUM_FMAN 2 +#define CFG_SYS_NUM_FMAN 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 3 @@ -146,7 +146,7 @@ #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CONFIG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 @@ -155,23 +155,23 @@ #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CFG_SYS_NUM_FM1_DTSEC 6 +#define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #define CONFIG_MAX_DSP_CPUS 2 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 0 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 0 #endif #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 @@ -186,9 +186,9 @@ #elif defined(CONFIG_ARCH_T1024) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CFG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 0 @@ -200,12 +200,12 @@ #define QE_NUM_OF_SNUM 28 #elif defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FMAN 1 +#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CFG_SYS_NUM_FM1_DTSEC 8 +#define CFG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index b1fd6bd5ce..54ef4fb629 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -11,7 +11,7 @@ enum fsl_dpaa_dev { FSL_HW_PORTAL_SEC, #ifdef CONFIG_SYS_DPAA_FMAN FSL_HW_PORTAL_FMAN1, -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) FSL_HW_PORTAL_FMAN2, #endif #endif diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 6783ebebb5..645c56c73d 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -427,7 +427,7 @@ int board_eth_init(struct bd_info *bis) break; } - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index 00ff6028e6..3cae2a0867 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -62,7 +62,7 @@ int board_eth_init(struct bd_info *bis) } dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); /* 10GBase-R on lane A, MAC 9 */ diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 88265a3994..926bd74ddc 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -349,7 +349,7 @@ int board_eth_init(struct bd_info *bis) /* SGMII on slot 4, MAC 2 */ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index 04fa57f81b..af70d10773 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) } dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); /* 10GBase-R on lane A, MAC 9 */ diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 23fd619cee..23ec32b7f9 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -162,7 +162,7 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index be42efa5c7..ed6b36339f 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -85,7 +85,7 @@ int board_eth_init(struct bd_info *bis) break; } - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_RGMII: @@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index bb6641b88a..5ce24b4096 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -39,7 +39,7 @@ int board_eth_init(struct bd_info *bis) /* * Program on board RGMII, SGMII PHY addresses. */ - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 555985b6f2..62261f50ea 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -625,7 +625,7 @@ int board_eth_init(struct bd_info *bis) break; } - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; interface = fm_info_get_enet_if(i); switch (interface) { @@ -673,7 +673,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { idx = i - FM1_10GEC1; switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 4041b3d9ac..241ee5a4a2 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -81,7 +81,7 @@ int board_eth_init(struct bd_info *bis) fm_disable_port(FM1_DTSEC5); fm_disable_port(FM1_DTSEC6); - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: @@ -93,7 +93,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + for (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); @@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis) } } -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { /* SGMII && 10GBase-R */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); @@ -121,7 +121,7 @@ int board_eth_init(struct bd_info *bis) fm_disable_port(FM2_DTSEC5); fm_disable_port(FM2_DTSEC6); - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { case PHY_INTERFACE_MODE_SGMII: @@ -133,7 +133,7 @@ int board_eth_init(struct bd_info *bis) } } - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + for (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_XGMII: dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); @@ -143,7 +143,7 @@ int board_eth_init(struct bd_info *bis) break; } } -#endif /* CONFIG_SYS_NUM_FMAN */ +#endif /* CFG_SYS_NUM_FMAN */ cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h index 06779f552f..bb3ce216d7 100644 --- a/board/freescale/t4rdb/t4rdb.h +++ b/board/freescale/t4rdb/t4rdb.h @@ -6,10 +6,10 @@ #ifndef __T4RDB_H__ #define __T4RDB_H__ -#undef CONFIG_SYS_NUM_FM1_DTSEC -#undef CONFIG_SYS_NUM_FM2_DTSEC -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#undef CFG_SYS_NUM_FM1_DTSEC +#undef CFG_SYS_NUM_FM2_DTSEC +#define CFG_SYS_NUM_FM1_DTSEC 4 +#define CFG_SYS_NUM_FM2_DTSEC 4 #define CORTINA_FW_ADDR_IFCNOR 0xefe00000 #define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 diff --git a/cmd/i2c.c b/cmd/i2c.c index e196a73efa..7b84378f7c 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1697,7 +1697,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, #else int i; - for (i = 0; i < CONFIG_SYS_NUM_I2C_BUSES; i++) { + for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; @@ -1730,7 +1730,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, } show_bus(bus); #else - if (i >= CONFIG_SYS_NUM_I2C_BUSES) { + if (i >= CFG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", i); return -1; } @@ -1788,7 +1788,7 @@ static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, } else { bus_no = dectoul(argv[1], NULL); #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) - if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) { + if (bus_no >= CFG_SYS_NUM_I2C_BUSES) { printf("Invalid bus %d\n", bus_no); return -1; } diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 09f91e674d..c3f6a1251f 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -34,7 +34,7 @@ struct i2c_adapter *i2c_get_adapter(int index) } #if !defined(CONFIG_SYS_I2C_DIRECT_BUS) -struct i2c_bus_hose i2c_bus[CONFIG_SYS_NUM_I2C_BUSES] = +struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = CONFIG_SYS_I2C_BUSES; #endif @@ -173,7 +173,7 @@ static int i2c_mux_disconnect_all(void) */ static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr) { - if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) + if (bus_no >= CFG_SYS_NUM_I2C_BUSES) return; I2C_ADAP->init(I2C_ADAP, speed, slaveaddr); @@ -238,7 +238,7 @@ int i2c_set_bus_num(unsigned int bus) return 0; #ifndef CONFIG_SYS_I2C_DIRECT_BUS - if (bus >= CONFIG_SYS_NUM_I2C_BUSES) + if (bus >= CFG_SYS_NUM_I2C_BUSES) return -1; #endif diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 30a9409e5a..9c4b4d7e46 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -257,7 +257,7 @@ defined(CONFIG_ARCH_LS1046A) #endif #ifdef CONFIG_SYS_DPAA_FMAN - for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { + for (j = 0; j < CFG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; name[sizeof(name) - 2] = '0' + j; diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 9b6dbe2882..1d3b7aa058 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -26,7 +26,7 @@ #include #endif -struct fm_muram muram[CONFIG_SYS_NUM_FMAN]; +struct fm_muram muram[CFG_SYS_NUM_FMAN]; void *fm_muram_base(int fm_idx) { diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 2379b3a11c..3d9cc5ca06 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -15,11 +15,11 @@ #define OH_PORT_ID_BASE 0x01 #define MAX_NUM_OH_PORT 7 #define RX_PORT_1G_BASE 0x08 -#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define MAX_NUM_RX_PORT_1G CFG_SYS_NUM_FM1_DTSEC #define RX_PORT_10G_BASE 0x10 #define RX_PORT_10G_BASE2 0x08 #define TX_PORT_1G_BASE 0x28 -#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC +#define MAX_NUM_TX_PORT_1G CFG_SYS_NUM_FM1_DTSEC #define TX_PORT_10G_BASE 0x30 #define TX_PORT_10G_BASE2 0x28 #define MIIM_TIMEOUT 0xFFFF diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 34f3816e65..8443cbb6b6 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -19,70 +19,70 @@ #ifndef CONFIG_DM_ETH struct fm_eth_info fm_info[] = { -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1) +#if (CFG_SYS_NUM_FM1_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(1, 1), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2) +#if (CFG_SYS_NUM_FM1_DTSEC >= 2) FM_DTSEC_INFO_INITIALIZER(1, 2), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3) +#if (CFG_SYS_NUM_FM1_DTSEC >= 3) FM_DTSEC_INFO_INITIALIZER(1, 3), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4) +#if (CFG_SYS_NUM_FM1_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(1, 4), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5) +#if (CFG_SYS_NUM_FM1_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(1, 5), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6) +#if (CFG_SYS_NUM_FM1_DTSEC >= 6) FM_DTSEC_INFO_INITIALIZER(1, 6), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7) +#if (CFG_SYS_NUM_FM1_DTSEC >= 7) FM_DTSEC_INFO_INITIALIZER(1, 9), #endif -#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8) +#if (CFG_SYS_NUM_FM1_DTSEC >= 8) FM_DTSEC_INFO_INITIALIZER(1, 10), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1) +#if (CFG_SYS_NUM_FM2_DTSEC >= 1) FM_DTSEC_INFO_INITIALIZER(2, 1), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2) +#if (CFG_SYS_NUM_FM2_DTSEC >= 2) FM_DTSEC_INFO_INITIALIZER(2, 2), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3) +#if (CFG_SYS_NUM_FM2_DTSEC >= 3) FM_DTSEC_INFO_INITIALIZER(2, 3), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4) +#if (CFG_SYS_NUM_FM2_DTSEC >= 4) FM_DTSEC_INFO_INITIALIZER(2, 4), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5) +#if (CFG_SYS_NUM_FM2_DTSEC >= 5) FM_DTSEC_INFO_INITIALIZER(2, 5), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6) +#if (CFG_SYS_NUM_FM2_DTSEC >= 6) FM_DTSEC_INFO_INITIALIZER(2, 6), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7) +#if (CFG_SYS_NUM_FM2_DTSEC >= 7) FM_DTSEC_INFO_INITIALIZER(2, 9), #endif -#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8) +#if (CFG_SYS_NUM_FM2_DTSEC >= 8) FM_DTSEC_INFO_INITIALIZER(2, 10), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 1) +#if (CFG_SYS_NUM_FM1_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(1, 1), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 2) +#if (CFG_SYS_NUM_FM1_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(1, 2), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) FM_TGEC_INFO_INITIALIZER2(1, 3), #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 4) +#if (CFG_SYS_NUM_FM1_10GEC >= 4) FM_TGEC_INFO_INITIALIZER2(1, 4), #endif -#if (CONFIG_SYS_NUM_FM2_10GEC >= 1) +#if (CFG_SYS_NUM_FM2_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(2, 1), #endif -#if (CONFIG_SYS_NUM_FM2_10GEC >= 2) +#if (CFG_SYS_NUM_FM2_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(2, 2), #endif }; @@ -101,7 +101,7 @@ int fm_standard_init(struct bd_info *bis) fm_eth_initialize(reg, &fm_info[i]); } -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) reg = (void *)CFG_SYS_FSL_FM2_ADDR; if (fm_init_common(1, reg)) return 0; @@ -276,7 +276,7 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) || diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 132786a423..6b83b021f7 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -30,7 +30,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b8f3d70e59..c4fed68273 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -15,7 +15,7 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 777a64ecee..1eec945421 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -58,7 +58,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* * These can be toggled for performance analysis, otherwise use default. diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 710f105cfa..42a0926329 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -22,7 +22,7 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4c60364f7e..941efdc243 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -17,7 +17,7 @@ /* High Level Configuration Options */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #ifdef CONFIG_RAMBOOT_PBL #define RESET_VECTOR_OFFSET 0x27FFC diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ba4a989fc5..5969854796 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -39,7 +39,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* * These can be toggled for performance analysis, otherwise use default. diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index a658cbc07c..ab0d0a721a 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } /* I2C */ -#define CONFIG_SYS_NUM_I2C_BUSES 4 +#define CFG_SYS_NUM_I2C_BUSES 4 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 57b0fc9069..ad9853ab6b 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -156,7 +156,7 @@ #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e6e54fba89..7af65737ff 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -136,7 +136,7 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* Environment in parallel NOR-Flash */ #define CONFIG_ENV_TOTAL_SIZE 0x040000 diff --git a/include/e500.h b/include/e500.h index 255f46bf1e..9f68a834c2 100644 --- a/include/e500.h +++ b/include/e500.h @@ -19,7 +19,7 @@ typedef struct unsigned long freq_localbus; unsigned long freq_qe; #ifdef CONFIG_SYS_DPAA_FMAN - unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; + unsigned long freq_fman[CFG_SYS_NUM_FMAN]; #endif #ifdef CONFIG_SYS_DPAA_QBMAN unsigned long freq_qman; diff --git a/include/fm_eth.h b/include/fm_eth.h index 7475b51507..aeb640925e 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -56,7 +56,7 @@ enum fm_eth_type { #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000) #endif #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000) -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000) #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000) #endif @@ -102,7 +102,7 @@ enum fm_eth_type { offsetof(struct ccsr_fman, memac[n-1]),\ } #else -#if (CONFIG_SYS_NUM_FMAN == 2) +#if (CFG_SYS_NUM_FMAN == 2) #define FM_TGEC_INFO_INITIALIZER(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ @@ -131,7 +131,7 @@ enum fm_eth_type { #endif #endif -#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#if (CFG_SYS_NUM_FM1_10GEC >= 3) #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ { \ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ diff --git a/include/i2c.h b/include/i2c.h index e0ee94e550..c07e60b04b 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -637,7 +637,7 @@ void i2c_early_init_f(void); /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 #define CONFIG_SYS_I2C_MAX_HOPS 0 -#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) +#define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ #undef CONFIG_SYS_I2C_DIRECT_BUS From a6b537266f525169c6469bd92c2a25ddca73bfc4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:30 -0500 Subject: [PATCH 016/424] rtc: Remove unused drivers These RTC drivers are currently unused and reference other unused CONFIG variables, so remove them. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 1 - drivers/rtc/Makefile | 3 - drivers/rtc/ds1556.c | 179 ------------------------------------------- drivers/rtc/ds164x.c | 171 ----------------------------------------- drivers/rtc/ds174x.c | 172 ----------------------------------------- 5 files changed, 526 deletions(-) delete mode 100644 drivers/rtc/ds1556.c delete mode 100644 drivers/rtc/ds164x.c delete mode 100644 drivers/rtc/ds174x.c diff --git a/README b/README index efb1d37df9..5ab042a2de 100644 --- a/README +++ b/README @@ -473,7 +473,6 @@ The following options need to be configured: CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC - CONFIG_RTC_DS164x - use Dallas DS164x RTC CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 009dd9d28c..2089086551 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -17,9 +17,6 @@ obj-$(CONFIG_RTC_DS1339) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o obj-$(CONFIG_RTC_DS1388) += ds1337.o -obj-$(CONFIG_RTC_DS1556) += ds1556.o -obj-$(CONFIG_RTC_DS164x) += ds164x.o -obj-$(CONFIG_RTC_DS174x) += ds174x.o obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o diff --git a/drivers/rtc/ds1556.c b/drivers/rtc/ds1556.c deleted file mode 100644 index 687b32937a..0000000000 --- a/drivers/rtc/ds1556.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * ARIO Data Networks, Inc. dchiu@ariodata.com - * - * modified for DS1556: - * Frank Panno , Delphin Technology AG - * - * Based on MontaVista DS1743 code and U-Boot mc146818 code - */ - -/* - * Date & Time support for the DS1556 RTC - */ - -/*#define RTC_DEBUG */ - -#include -#include -#include - -#if defined(CONFIG_CMD_DATE) - -static uchar rtc_read( unsigned int addr ); -static void rtc_write( unsigned int addr, uchar val); - -#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) - -#define RTC_YEAR ( RTC_BASE + 0xf ) -#define RTC_MONTH ( RTC_BASE + 0xe ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 0xd ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 0xc ) -#define RTC_HOURS ( RTC_BASE + 0xb ) -#define RTC_MINUTES ( RTC_BASE + 0xa ) -#define RTC_SECONDS ( RTC_BASE + 0x9 ) -#define RTC_CENTURY ( RTC_BASE + 0x8 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_BASE - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x10 -#define RTC_CC_FREQ_TEST 0x40 - -/* ------------------------------------------------------------------------- */ - -int rtc_get( struct rtc_time *tmp ) -{ - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %02x mon/cent: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, century, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - /* glue year from century and year in century */ - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - uchar reg_a; -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - - return 0; -} - -void rtc_reset (void) -{ - uchar reg_a, reg_b, reg_c; - - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n" ); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read( unsigned int addr ) -{ - uchar val = *(volatile unsigned char*)(addr); -#ifdef RTC_DEBUG - printf( "rtc_read: %x:%x\n", addr, val ); -#endif - return( val ); -} - -static void rtc_write( unsigned int addr, uchar val ) -{ -#ifdef RTC_DEBUG - printf( "rtc_write: %x:%x\n", addr, val ); -#endif - *(volatile unsigned char*)(addr) = val; -} - -#endif diff --git a/drivers/rtc/ds164x.c b/drivers/rtc/ds164x.c deleted file mode 100644 index f8707892e7..0000000000 --- a/drivers/rtc/ds164x.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * ARIO Data Networks, Inc. dchiu@ariodata.com - * - * modified for DS164x: - * The LEOX team , http://www.leox.org - * - * Based on MontaVista DS1743 code and U-Boot mc146818 code - */ - -/* - * Date & Time support for the DS164x RTC - */ - -/* #define RTC_DEBUG */ - -#include -#include -#include - - -static uchar rtc_read(unsigned int addr ); -static void rtc_write(unsigned int addr, uchar val); - -#define RTC_EPOCH 2000 /* century */ - -/* - * DS164x registers layout - */ -#define RTC_BASE ( CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE ) - -#define RTC_YEAR ( RTC_BASE + 0x07 ) -#define RTC_MONTH ( RTC_BASE + 0x06 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 0x05 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 0x04 ) -#define RTC_HOURS ( RTC_BASE + 0x03 ) -#define RTC_MINUTES ( RTC_BASE + 0x02 ) -#define RTC_SECONDS ( RTC_BASE + 0x01 ) -#define RTC_CONTROL ( RTC_BASE + 0x00 ) - -#define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */ -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 -#define RTC_CONTROLB RTC_SECONDS /* OSC=bit7 */ -#define RTC_CB_OSC_DISABLE 0x80 -#define RTC_CONTROLC RTC_DAY_OF_WEEK /* FT=bit6 */ -#define RTC_CC_FREQ_TEST 0x40 - -/* ------------------------------------------------------------------------- */ - -int rtc_get( struct rtc_time *tmp ) -{ - uchar sec, min, hour; - uchar mday, wday, mon, year; - - uchar reg_a; - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - /* glue year in century (2000) */ - tmp->tm_year = bcd2bin( year ) + RTC_EPOCH; - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - uchar reg_a; - -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year in century */ - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - - return 0; -} - -void rtc_reset (void) -{ - uchar reg_a, reg_b; - - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read( unsigned int addr ) -{ - uchar val = *(volatile unsigned char*)(addr); - -#ifdef RTC_DEBUG - printf( "rtc_read: %x:%x\n", addr, val ); -#endif - return( val ); -} - -static void rtc_write( unsigned int addr, uchar val ) -{ -#ifdef RTC_DEBUG - printf( "rtc_write: %x:%x\n", addr, val ); -#endif - *(volatile unsigned char*)(addr) = val; -} diff --git a/drivers/rtc/ds174x.c b/drivers/rtc/ds174x.c deleted file mode 100644 index 94f943d97a..0000000000 --- a/drivers/rtc/ds174x.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 - * ARIO Data Networks, Inc. dchiu@ariodata.com - * - * Based on MontaVista DS1743 code and U-Boot mc146818 code - */ - -/* - * Date & Time support for the DS174x RTC - */ - -/*#define DEBUG*/ - -#include -#include -#include - -static uchar rtc_read( unsigned int addr ); -static void rtc_write( unsigned int addr, uchar val); - -#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR ) - -#define RTC_YEAR ( RTC_BASE + 7 ) -#define RTC_MONTH ( RTC_BASE + 6 ) -#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 ) -#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 ) -#define RTC_HOURS ( RTC_BASE + 3 ) -#define RTC_MINUTES ( RTC_BASE + 2 ) -#define RTC_SECONDS ( RTC_BASE + 1 ) -#define RTC_CENTURY ( RTC_BASE + 0 ) - -#define RTC_CONTROLA RTC_CENTURY -#define RTC_CONTROLB RTC_SECONDS -#define RTC_CONTROLC RTC_DAY_OF_WEEK - -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 - -#define RTC_CB_OSC_DISABLE 0x80 - -#define RTC_CC_BATTERY_FLAG 0x80 -#define RTC_CC_FREQ_TEST 0x40 - -/* ------------------------------------------------------------------------- */ - -int rtc_get( struct rtc_time *tmp ) -{ - uchar sec, min, hour; - uchar mday, wday, mon, year; - - int century; - - uchar reg_a; - - reg_a = rtc_read( RTC_CONTROLA ); - /* lock clock registers for read */ - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ )); - - sec = rtc_read( RTC_SECONDS ); - min = rtc_read( RTC_MINUTES ); - hour = rtc_read( RTC_HOURS ); - mday = rtc_read( RTC_DAY_OF_MONTH ); - wday = rtc_read( RTC_DAY_OF_WEEK ); - mon = rtc_read( RTC_MONTH ); - year = rtc_read( RTC_YEAR ); - century = rtc_read( RTC_CENTURY ); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ )); - -#ifdef RTC_DEBUG - printf( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon_cent, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin( sec & 0x7F ); - tmp->tm_min = bcd2bin( min & 0x7F ); - tmp->tm_hour = bcd2bin( hour & 0x3F ); - tmp->tm_mday = bcd2bin( mday & 0x3F ); - tmp->tm_mon = bcd2bin( mon & 0x1F ); - tmp->tm_wday = bcd2bin( wday & 0x07 ); - - /* glue year from century and year in century */ - tmp->tm_year = bcd2bin( year ) + - ( bcd2bin( century & 0x3F ) * 100 ); - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); -#endif - return 0; -} - -int rtc_set( struct rtc_time *tmp ) -{ - uchar reg_a; -#ifdef RTC_DEBUG - printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - /* lock clock registers for write */ - reg_a = rtc_read( RTC_CONTROLA ); - rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE )); - - rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon )); - - rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday )); - rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday )); - rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour )); - rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min )); - rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec )); - - /* break year up into century and year in century */ - rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 )); - rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 )); - - /* unlock clock registers after read */ - rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); - - return 0; -} - -void rtc_reset (void) -{ - uchar reg_a, reg_b, reg_c; - - reg_a = rtc_read( RTC_CONTROLA ); - reg_b = rtc_read( RTC_CONTROLB ); - - if ( reg_b & RTC_CB_OSC_DISABLE ) - { - printf( "real-time-clock was stopped. Now starting...\n" ); - reg_a |= RTC_CA_WRITE; - reg_b &= ~RTC_CB_OSC_DISABLE; - - rtc_write( RTC_CONTROLA, reg_a ); - rtc_write( RTC_CONTROLB, reg_b ); - } - - /* make sure read/write clock register bits are cleared */ - reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ ); - rtc_write( RTC_CONTROLA, reg_a ); - - reg_c = rtc_read( RTC_CONTROLC ); - if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 ) - printf( "RTC battery low. Clock setting may not be reliable.\n" ); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read( unsigned int addr ) -{ - uchar val = in8( addr ); -#ifdef RTC_DEBUG - printf( "rtc_read: %x:%x\n", addr, val ); -#endif - return( val ); -} - -static void rtc_write( unsigned int addr, uchar val ) -{ -#ifdef RTC_DEBUG - printf( "rtc_write: %x:%x\n", addr, val ); -#endif - out8( addr, val ); -} From 3408d96e6cec9dac16fce1a32a522c5de8a182ae Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:31 -0500 Subject: [PATCH 017/424] Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .../asm/arch-fsl-layerscape/immap_lsch2.h | 3 -- .../asm/arch-fsl-layerscape/immap_lsch3.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7790.h | 3 -- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 -- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 -- .../arm/mach-rmobile/include/mach/rcar-base.h | 9 ------ arch/powerpc/include/asm/immap_85xx.h | 8 ----- include/configs/M5282EVB.h | 6 ---- include/configs/MPC8548CDS.h | 5 ---- include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 4 --- include/configs/T104xRDB.h | 6 ---- include/configs/T208xQDS.h | 5 ---- include/configs/T208xRDB.h | 5 ---- include/configs/T4240RDB.h | 5 ---- include/configs/aristainetos2.h | 2 -- include/configs/eb_cpu5282.h | 30 ------------------- include/configs/highbank.h | 5 ---- include/configs/km/km-mpc8360.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/ls1012a2g5rdb.h | 4 --- include/configs/ls1012a_common.h | 4 --- include/configs/ls1043aqds.h | 4 --- include/configs/ls1046a_common.h | 5 ---- include/configs/p1_p2_rdb_pc.h | 6 ---- include/configs/phycore_am335x_r2.h | 6 ---- include/configs/r2dplus.h | 5 ---- include/configs/socrates.h | 8 ++--- include/configs/ti814x_evm.h | 2 -- include/configs/ti_armv7_keystone2.h | 5 ---- 31 files changed, 2 insertions(+), 157 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index c11018d732..85ac5eb281 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,7 +35,6 @@ #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -56,9 +55,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index a4e971ebbd..59488a04e4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -194,8 +194,6 @@ /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) -#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index ef74d59fed..28669e3c77 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,9 +24,6 @@ #define MSTP11_BITS 0x00000000 /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 #define R8A7790_CUT_ES2X 2 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 681d1ea524..37d134c5bf 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,8 +14,6 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 31433c3693..85f59d9771 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,8 +15,6 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 3baa4237c2..2bd6e469c8 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,8 +24,6 @@ #define MSTP11_BITS 0x000001C0 /* SDHI */ -#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 -#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 #define R8A7794_CUT_ES2 2 diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h index 4c98dffa07..e422e9100a 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -70,15 +70,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* RCAR-I2C */ -#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 -#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 -#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000 -#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000 - -/* SDHI */ -#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 - #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c9ced5474c..78c0d05496 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2662,18 +2662,10 @@ struct ccsr_pman { #define CONFIG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) -#define CONFIG_SYS_PCI1_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) -#define CONFIG_SYS_PCI2_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET) #define CONFIG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) #define CONFIG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_PCIE3_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET) -#define CONFIG_SYS_PCIE4_ADDR \ - (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET) #define CONFIG_SYS_SFP_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index e191dc615b..925d26eaf1 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -130,13 +130,7 @@ #define CONFIG_SYS_PBDDR 0x0000000 #define CONFIG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 #define CONFIG_SYS_PEHLPAR 0xC0 #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bde8fa8df4..c29e63c54e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -256,21 +256,16 @@ */ #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #endif -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6b83b021f7..c832981078 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -248,8 +248,6 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -276,9 +274,7 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index c4fed68273..e21639a695 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -349,8 +349,6 @@ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif #endif /* CONFIG_PCI */ @@ -391,9 +389,7 @@ #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #endif #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 1eec945421..a3d04882f0 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -325,16 +325,12 @@ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull #endif #endif /* CONFIG_PCI */ @@ -364,9 +360,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 42a0926329..72052be78a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -359,13 +359,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN @@ -385,9 +382,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 941efdc243..c798e4487a 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -313,13 +313,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN @@ -339,9 +336,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5969854796..5777df8e50 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -121,13 +121,10 @@ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull /* * Miscellaneous configurable options @@ -337,9 +334,7 @@ #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ CONFIG_SYS_QMAN_CENA_SIZE) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 1f2b3b58ca..35e8840a92 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -30,8 +30,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - #ifdef CONFIG_IMX_HAB #define HAB_EXTRA_SETTINGS \ "hab_check_addr=" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index aaa2ef039d..80a820c913 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -137,13 +137,7 @@ #define CONFIG_SYS_PBDDR 0x0000000 #define CONFIG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 #define CONFIG_SYS_PASPAR 0x0F0F #define CONFIG_SYS_PEHLPAR 0xC0 @@ -160,29 +154,5 @@ #define CONFIG_I2C_RTC_ADDR 0x68 #endif -/*----------------------------------------------------------------------- - * VIDEO configuration - */ - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 -#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 -#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 - -#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 - -#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 - -#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE -#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE -#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 - #endif /* _CONFIG_M5282EVB_H */ /*---------------------------------------------------------------------*/ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e2b50bbac..a7d21a76db 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,11 +14,6 @@ * Miscellaneous configurable options */ -/* Environment data setup -*/ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ - #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 92e046d02d..fb43fb81bc 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -72,4 +72,3 @@ * PAXE on the local bus CS3 */ #define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index ab0d0a721a..7d36a25dc2 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -8,7 +8,6 @@ * DDR Setup */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index f0248e6464..196e024b57 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -11,10 +11,6 @@ /* DDR */ #define CONFIG_SYS_SDRAM_SIZE 0x40000000 -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index b57eb52d14..809f9ae8c8 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -18,10 +18,6 @@ /*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000 -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* I2C */ /* GPIO */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 3b51cb8f17..87751f786c 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -35,10 +35,6 @@ #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB #endif -/* SATA */ - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - /* * IFC Definitions */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8a3c87c6ab..3934fbbb41 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -65,11 +65,6 @@ /* I2C */ -/* SATA */ -#ifndef SPL_NO_SATA -#define CONFIG_SYS_SATA AHCI_BASE_ADDR -#endif - /* FMan ucode */ #ifndef SPL_NO_FMAN #define CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9fc22f0a6c..44e608536f 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -279,12 +279,6 @@ #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE #endif -#define CONFIG_SYS_VSC7385_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \ - OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - /* The size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index c5817b010f..43a60825b5 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -97,10 +97,4 @@ #endif /* !CONFIG_MTD_RAW_NAND */ -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - #endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index ac39e11a99..406ee6282c 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -18,9 +18,4 @@ #define CONFIG_SYS_FLASH_BASE (0xA0000000) #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -/* - * SuperH Clock setting - */ -#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ - #endif /* __CONFIG_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 388a4e42ef..9b106fc1c9 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -109,12 +109,8 @@ * Memory space is mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index 9614fe686f..fc78077014 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -84,8 +84,6 @@ /* Defines for SPL */ -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 - /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 119b4c0410..65abb187d9 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -46,11 +46,6 @@ /* SPI Configuration */ #define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) -/* Network Configuration */ -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 - /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE From 789bb9537a4427798e3e28ff0c6be2c27454315f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:32 -0500 Subject: [PATCH 018/424] Convert CONFIG_SYS_OMAP_ABE_SYSCK to Kconfig This converts the following to Kconfig: CONFIG_SYS_OMAP_ABE_SYSCK Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/mach-omap2/Kconfig | 3 +++ arch/arm/mach-omap2/omap5/Kconfig | 1 + include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 78317e474d..3bf9720522 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -144,6 +144,9 @@ config SYS_MPUCLK help Defines the MPU clock speed (in MHz). +config SYS_OMAP_ABE_SYSCK + bool + config TI_SECURE_EMIF_REGION_START hex "Reserved EMIF region start address" depends on TI_SECURE_DEVICE diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 4c2f990b28..18a6676422 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -2,6 +2,7 @@ if OMAP54XX config DRA7XX bool + select SYS_OMAP_ABE_SYSCK help DRA7xx is an OMAP based SOC with Dual Core A-15s. diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c3b6a3fbda..84555f3b13 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -20,8 +20,6 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_SYS_OMAP_ABE_SYSCK - #ifndef CONFIG_SPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index e1d18a7783..bb335a0a47 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -31,8 +31,6 @@ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_SYS_OMAP_ABE_SYSCK - #ifndef CONFIG_SPL_BUILD #define DFUARGS \ "dfu_bufsiz=0x10000\0" \ From ecc8d425fd50d894dd0a06796c17030ef4a7942f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:33 -0500 Subject: [PATCH 019/424] global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++---- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 +++++++++---------- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 24 +++++----- .../asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++++++------- arch/arm/include/asm/arch-ls102xa/config.h | 22 ++++----- arch/m68k/include/asm/immap.h | 8 ++-- arch/powerpc/cpu/mpc83xx/pcie.c | 10 ++-- arch/powerpc/cpu/mpc85xx/liodn.c | 2 +- arch/powerpc/include/asm/fsl_pci.h | 32 ++++++------- arch/powerpc/include/asm/immap_85xx.h | 4 +- board/freescale/common/p_corenet/tlb.c | 12 ++--- board/freescale/mpc8548cds/tlb.c | 6 +-- board/freescale/p1010rdb/tlb.c | 4 +- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- board/freescale/t102xrdb/tlb.c | 4 +- board/freescale/t104xrdb/tlb.c | 4 +- board/freescale/t208xqds/tlb.c | 10 ++-- board/freescale/t208xrdb/tlb.c | 10 ++-- board/freescale/t4rdb/tlb.c | 12 ++--- board/keymile/kmcent2/tlb.c | 4 +- board/socrates/tlb.c | 4 +- common/fdt_support.c | 4 +- drivers/pci/pci_auto.c | 8 ++-- drivers/pci/pcie_fsl.c | 16 +++---- drivers/pci/pcie_fsl.h | 12 ++--- drivers/pci/pcie_layerscape.h | 16 +++---- drivers/pci/pcie_layerscape_ep.c | 6 +-- drivers/pci/pcie_layerscape_gen4.c | 6 +-- drivers/pci/pcie_layerscape_gen4.h | 8 ++-- include/configs/MPC837XERDB.h | 16 +++---- include/configs/MPC8548CDS.h | 24 +++++----- include/configs/P1010RDB.h | 24 +++++----- include/configs/P2041RDB.h | 20 ++++---- include/configs/T102xRDB.h | 20 ++++---- include/configs/T104xRDB.h | 24 +++++----- include/configs/T208xQDS.h | 24 +++++----- include/configs/T208xRDB.h | 24 +++++----- include/configs/T4240RDB.h | 24 +++++----- include/configs/kmcent2.h | 8 ++-- include/configs/p1_p2_rdb_pc.h | 24 +++++----- include/configs/socrates.h | 4 +- 42 files changed, 297 insertions(+), 297 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d530e0655b..d09c21d5d9 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -168,18 +168,18 @@ static void mmu_setup(void) /* Level 1 has 512 entries */ for (i = 0; i < 512; i++) { /* Mapping for PCIe 1 */ - if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR && + va_start < (CFG_SYS_PCIE1_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE1_PHYS_BASE + va_start, + CFG_SYS_PCIE1_PHYS_BASE + va_start, MT_DEVICE_MEM); /* Mapping for PCIe 2 */ - else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR && - va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR + - CONFIG_SYS_PCIE_MMAP_SIZE)) + else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR && + va_start < (CFG_SYS_PCIE2_VIRT_ADDR + + CFG_SYS_PCIE_MMAP_SIZE)) set_pgsection(level1_table, i, - CONFIG_SYS_PCIE2_PHYS_BASE + va_start, + CFG_SYS_PCIE2_PHYS_BASE + va_start, MT_DEVICE_MEM); else set_pgsection(level1_table, i, diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c11341a1d3..ef71e2cf2b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -257,26 +257,26 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR, + CFG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -368,19 +368,19 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void) (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { - case CONFIG_SYS_PCIE1_PHYS_ADDR: + case CFG_SYS_PCIE1_PHYS_ADDR: final_map[i].phys = 0x2000000000ULL; final_map[i].virt = 0x2000000000ULL; final_map[i].size = 0x800000000ULL; break; - case CONFIG_SYS_PCIE2_PHYS_ADDR: + case CFG_SYS_PCIE2_PHYS_ADDR: final_map[i].phys = 0x2800000000ULL; final_map[i].virt = 0x2800000000ULL; final_map[i].size = 0x800000000ULL; break; -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - case CONFIG_SYS_PCIE3_PHYS_ADDR: +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + case CFG_SYS_PCIE3_PHYS_ADDR: final_map[i].phys = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL; final_map[i].size = 0x800000000ULL; break; #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - case CONFIG_SYS_PCIE4_PHYS_ADDR: +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + case CFG_SYS_PCIE4_PHYS_ADDR: final_map[i].phys = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL; final_map[i].size = 0x800000000ULL; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4db479140e..20f9671387 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -35,17 +35,17 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 #ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x200000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x200000000 #else -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#ifndef CFG_SYS_PCIE3_PHYS_SIZE +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #endif -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE4_PHYS_SIZE 0x800000000 #define SYS_PCIE5_PHYS_SIZE 0x800000000 #define SYS_PCIE6_PHYS_SIZE 0x800000000 #endif @@ -83,9 +83,9 @@ #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */ -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000 +#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 85ac5eb281..64dc7c88b7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) @@ -90,9 +90,9 @@ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) #define QMAN_CQSIDR_REG 0x20a80 -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL /* LUT registers */ #ifdef CONFIG_ARCH_LS1012A #define PCIE_LUT_BASE 0xC0000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 59488a04e4..cd112402e0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -192,35 +192,35 @@ /* PCIe */ -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000) #define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000) #endif #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL #define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL #define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL #elif CONFIG_ARCH_LS1088A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL #elif CONFIG_ARCH_LS1028A -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x01f0000000ULL /* this is used by integrated PCI on LS1028, includes ECAM and register space */ -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL +#define CFG_SYS_PCIE3_PHYS_SIZE 0x0010000000ULL #else -#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL -#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL -#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL +#define CFG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL +#define CFG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL +#define CFG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL +#define CFG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL #endif /* Device Configuration */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 033341dbfb..62026bda9e 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -55,22 +55,22 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) +#define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL -#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL -#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL -#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL -#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ +#define CFG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL +#define CFG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL +#define CFG_SYS_PCIE1_VIRT_ADDR 0x24000000UL +#define CFG_SYS_PCIE2_VIRT_ADDR 0x34000000UL +#define CFG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ /* * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. */ -#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ - CONFIG_SYS_PCIE1_VIRT_ADDR) -#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ - CONFIG_SYS_PCIE2_VIRT_ADDR) +#define CFG_SYS_PCIE1_PHYS_ADDR (CFG_SYS_PCIE1_PHYS_BASE + \ + CFG_SYS_PCIE1_VIRT_ADDR) +#define CFG_SYS_PCIE2_PHYS_ADDR (CFG_SYS_PCIE2_PHYS_BASE + \ + CFG_SYS_PCIE2_VIRT_ADDR) /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index ead62cd038..f2eb6fcb46 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -337,10 +337,10 @@ #define CONFIG_SYS_NUM_IRQS (128) #ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_BAR0 (0x40000000) -#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR0 (0x40000000) +#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index d2b6b05bda..47ca74c5c3 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -24,13 +24,13 @@ static struct { u32 size; } mpc83xx_pcie_cfg_space[] = { { - .base = CONFIG_SYS_PCIE1_CFG_BASE, - .size = CONFIG_SYS_PCIE1_CFG_SIZE, + .base = CFG_SYS_PCIE1_CFG_BASE, + .size = CFG_SYS_PCIE1_CFG_SIZE, }, -#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) +#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE) { - .base = CONFIG_SYS_PCIE2_CFG_BASE, - .size = CONFIG_SYS_PCIE2_CFG_SIZE, + .base = CFG_SYS_PCIE2_CFG_BASE, + .size = CFG_SYS_PCIE2_CFG_SIZE, }, #endif }; diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index abc14fae4e..d5df02d39d 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -387,7 +387,7 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR; int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; if (pci_ver >= 0x0204) { diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 06f9bfb8ac..809ab1d418 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno); #define SET_STD_PCI_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCI##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCI_##num; \ x.pci_num = num; \ } #define SET_STD_PCIE_INFO(x, num) \ { \ - x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ - x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ - x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ - x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ - x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ - x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ - x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.regs = CFG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \ x.law = LAW_TRGT_IF_PCIE_##num; \ x.pci_num = num; \ } #define __FT_FSL_PCI_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR) #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ - ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) + ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR) #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 78c0d05496..9ae698743e 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2662,9 +2662,9 @@ struct ccsr_pman { #define CONFIG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) -#define CONFIG_SYS_PCIE1_ADDR \ +#define CFG_SYS_PCIE1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) -#define CONFIG_SYS_PCIE2_ADDR \ +#define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) #define CONFIG_SYS_SFP_ADDR \ diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index ef46353a36..4cdef89bf0 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -91,23 +91,23 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 8d1e5fee93..9c8e948600 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 4: * PCI and PCIe MEM 1G Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1G, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 5: * PCI1 IO 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 6: * PCIe IO 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), }; diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index aa7517a74d..5e1fa70bca 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -52,12 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_PCI /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256K, 1), #endif diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 85d41327aa..4cc5e01f57 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -45,12 +45,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_PCI /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 8fdff7576f..74744c8ab0 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -54,12 +54,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 8a3d67449c..905e4771c9 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -67,12 +67,12 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f27faf5d24..9160674b94 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_512M, 1), /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index da03aadb17..69e58e7e97 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCIe 1, 0x80000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_512M, 1), /* *I*G* - PCIe 2, 0xa0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 3, 0xb0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCIe 4, 0xc0000000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256K, 1), diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index 059449af1e..c57af3046f 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -52,23 +52,23 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CFG_SYS_PCIE1_MEM_PHYS + 0x50000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 095fc7e961..0f6dc6063a 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -46,12 +46,12 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 2, BOOKE_PAGESZ_128M, 1), /* *I*G* - PCI1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI1 I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256K, 1), diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index de80c3c0e5..1ab403d145 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), diff --git a/common/fdt_support.c b/common/fdt_support.c index ebebffc789..dbceec6f2d 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -739,7 +739,7 @@ int fdt_delete_disabled_nodes(void *blob) } #ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4 +#define CFG_SYS_PCI_NR_INBOUND_WIN 4 #define FDT_PCI_PREFETCH (0x40000000) #define FDT_PCI_MEM32 (0x02000000) @@ -751,7 +751,7 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) { int addrcell, sizecell, len, r; u32 *dma_range; /* sized based on pci addr cells, size-cells, & address-cells */ - u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN]; + u32 dma_ranges[(3 + 2 + 2) * CFG_SYS_PCI_NR_INBOUND_WIN]; addrcell = fdt_getprop_u32_default(blob, "/", "#address-cells", 1); sizecell = fdt_getprop_u32_default(blob, "/", "#size-cells", 1); diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index c7968926a1..14fd3bbf67 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -16,9 +16,9 @@ #include #include "pci_internal.h" -/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ -#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 +/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */ +#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE +#define CFG_SYS_PCI_CACHE_LINE_SIZE 8 #endif static void dm_pciauto_setup_device(struct udevice *dev, @@ -178,7 +178,7 @@ static void dm_pciauto_setup_device(struct udevice *dev, dm_pci_write_config16(dev, PCI_COMMAND, cmdstat); dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE, - CONFIG_SYS_PCI_CACHE_LINE_SIZE); + CFG_SYS_PCI_CACHE_LINE_SIZE); dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80); } diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index a8f8c31bef..4600652f2b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -343,8 +343,8 @@ static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie) static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) { - phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; - pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; + phys_addr_t phys_start = CFG_SYS_PCI_MEMORY_PHYS; + pci_addr_t bus_start = CFG_SYS_PCI_MEMORY_BUS; u64 sz = min((u64)gd->ram_size, (1ull << 32)); pci_size_t pci_sz; int idx; @@ -367,8 +367,8 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) sz = 2ull << __ilog2_u64(sz); fsl_pcie_setup_inbound_win(pcie, idx--, true, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI_MEMORY_BUS, sz); + CFG_SYS_PCI_MEMORY_PHYS, + CFG_SYS_PCI_MEMORY_BUS, sz); #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) /* * On 64-bit capable systems, set up a mapping for all of DRAM @@ -380,12 +380,12 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie) pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n", - (u64)CONFIG_SYS_PCI64_MEMORY_BUS, - (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); + (u64)CFG_SYS_PCI64_MEMORY_BUS, + (u64)CFG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); fsl_pcie_setup_inbound_win(pcie, idx--, true, - CONFIG_SYS_PCI_MEMORY_PHYS, - CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz); + CFG_SYS_PCI_MEMORY_PHYS, + CFG_SYS_PCI64_MEMORY_BUS, pci_sz); #endif return 0; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 70c5f4e4cf..ba84a232b8 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -28,16 +28,16 @@ #define DBI_RO_WR_EN 0x8bc -#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS 0 +#ifndef CFG_SYS_PCI_MEMORY_BUS +#define CFG_SYS_PCI_MEMORY_BUS 0 #endif -#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS 0 +#ifndef CFG_SYS_PCI_MEMORY_PHYS +#define CFG_SYS_PCI_MEMORY_PHYS 0 #endif -#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS) -#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) +#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS) +#define CFG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024) #endif #define PEX_CSR0_LTSSM_MASK 0xFC diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 8cdf516d9f..a52774179e 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -13,20 +13,20 @@ #include #include -#ifndef CONFIG_SYS_PCI_MEMORY_BUS -#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#ifndef CFG_SYS_PCI_MEMORY_BUS +#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE #endif -#ifndef CONFIG_SYS_PCI_MEMORY_PHYS -#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#ifndef CFG_SYS_PCI_MEMORY_PHYS +#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE #endif -#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G +#ifndef CFG_SYS_PCI_MEMORY_SIZE +#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G #endif -#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#ifndef CFG_SYS_PCI_EP_MEMORY_BASE +#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif #define PCIE_PHYS_SIZE 0x200000000 diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index f2813aeef6..ff26a5cd9b 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -72,7 +72,7 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) u32 vf_flag = 0; u64 phys = 0; - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M; + phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M; phys = ALIGN(phys, PCIE_BAR0_SIZE); /* ATU 0 : INBOUND : map BAR0 */ @@ -117,8 +117,8 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf) /* ATU: OUTBOUND : map MEM */ ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM, (u64)pcie_ep->addr_res.start + - pf * CONFIG_SYS_PCI_MEMORY_SIZE, - 0, CONFIG_SYS_PCI_MEMORY_SIZE); + pf * CFG_SYS_PCI_MEMORY_SIZE, + 0, CFG_SYS_PCI_MEMORY_SIZE); } /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */ diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c index 6ecdd6af40..021c975869 100644 --- a/drivers/pci/pcie_layerscape_gen4.c +++ b/drivers/pci/pcie_layerscape_gen4.c @@ -333,7 +333,7 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf) if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1) return; - phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf; + phys = CFG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf; for (bar = 0; bar < PF_BAR_NUM; bar++) { ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys); phys += PCIE_BAR_SIZE; @@ -342,8 +342,8 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf) /* OUTBOUND: map MEM */ ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM, pcie->cfg_res.start + - CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0, - CONFIG_SYS_PCI_MEMORY_SIZE); + CFG_SYS_PCI_MEMORY_SIZE * pf, 0x0, + CFG_SYS_PCI_MEMORY_SIZE); val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf)); val &= ~FUNC_NUM_PCIE_MASK; diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h index 483eb538b5..805c23a7da 100644 --- a/drivers/pci/pcie_layerscape_gen4.h +++ b/drivers/pci/pcie_layerscape_gen4.h @@ -11,12 +11,12 @@ #include #include -#ifndef CONFIG_SYS_PCI_MEMORY_SIZE -#define CONFIG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL) +#ifndef CFG_SYS_PCI_MEMORY_SIZE +#define CFG_SYS_PCI_MEMORY_SIZE (4 * 1024 * 1024 * 1024ULL) #endif -#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE -#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR +#ifndef CFG_SYS_PCI_EP_MEMORY_BASE +#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR #endif #define PCIE_PF_NUM 2 diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 059885ecb5..0e70b2853b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -177,15 +177,15 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 /* * TSEC diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c29e63c54e..c59a37646f 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -254,31 +254,31 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CFG_SYS_PCI1_IO_VIRT 0xe2000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull +#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull #else -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CFG_SYS_PCI1_IO_PHYS 0xe2000000 #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 +#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif #endif diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 05c097759f..f87e7597ad 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -68,31 +68,31 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c832981078..e996dbaa4d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -234,20 +234,20 @@ */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e21639a695..6d6e334bf0 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -331,24 +331,24 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif #endif /* CONFIG_PCI */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index a3d04882f0..423ba81617 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -307,30 +307,30 @@ #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull #endif #endif /* CONFIG_PCI */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 72052be78a..2efc2eb95c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -345,24 +345,24 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c798e4487a..ca8bfac0c6 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -299,24 +299,24 @@ * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 5777df8e50..091920dccf 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -107,24 +107,24 @@ */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull /* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull /* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull /* * Miscellaneous configurable options diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 7af65737ff..1df90def67 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -346,10 +346,10 @@ int get_scl(void); * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 1 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 44e608536f..6e8ac1b98d 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -343,31 +343,31 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif #endif /* CONFIG_PCI */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 9b106fc1c9..a60ac6d1a3 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -109,8 +109,8 @@ * Memory space is mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CFG_SYS_PCI1_MEM_PHYS 0x80000000 +#define CFG_SYS_PCI1_IO_PHYS 0xE2000000 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" From 2db82bf2bd8fa5de2b55ad7c4c1c0afa58f171c2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:34 -0500 Subject: [PATCH 020/424] Convert CONFIG_SYS_PMAN et al to Kconfig This converts the following to Kconfig: CONFIG_NOBQFMAN CONFIG_SYS_DPAA_DCE CONFIG_SYS_DPAA_FMAN CONFIG_SYS_DPAA_PME CONFIG_SYS_DPAA_RMAN CONFIG_SYS_PMAN Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/Kconfig.nxp | 3 ++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 8 ++--- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/Kconfig | 35 +++++++++++++++++++ include/configs/P2041RDB.h | 4 --- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 3 -- include/configs/T208xQDS.h | 6 ---- include/configs/T208xRDB.h | 6 ---- include/configs/T4240RDB.h | 6 ---- include/configs/kmcent2.h | 3 -- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - 16 files changed, 45 insertions(+), 41 deletions(-) diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 8c5a6f63a9..805fe934a1 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -251,3 +251,6 @@ config QIXIS_I2C_ACCESS config HAS_FSL_DR_USB def_bool y depends on USB_EHCI_HCD && PPC + +config SYS_DPAA_FMAN + bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ebca11d174..2862257e1f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -69,6 +69,7 @@ config ARCH_LS1043A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -106,6 +107,7 @@ config ARCH_LS1046A select GICV2 select HAS_FSL_XHCI_USB if USB_HOST select SKIP_LOWLEVEL_INIT + select SYS_DPAA_FMAN select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 6440ce714f..f18407b6d3 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -24,11 +24,7 @@ void get_sys_info(struct sys_info *sys_info) /* rcw_tmp is needed to get FMAN clock, or to get cluster group A * mux 2 clock for LS1043A/LS1046A. */ -#if defined(CONFIG_SYS_DPAA_FMAN) || \ - defined(CONFIG_ARCH_LS1046A) || \ - defined(CONFIG_ARCH_LS1043A) - u32 rcw_tmp; -#endif + __maybe_unused u32 rcw_tmp; struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { @@ -96,7 +92,7 @@ void get_sys_info(struct sys_info *sys_info) #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) rcw_tmp = in_be32(&gur->rcwsr[7]); switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) { case 2: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index e972603f24..ad20d71717 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -41,7 +41,7 @@ void set_icids(void) /* setup general icid offsets */ set_icid(icid_tbl, icid_tbl_sz); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz); #endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 3bd993bebf..4880a313ea 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -59,7 +59,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index abd847b5be..e47d3af85e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -58,7 +58,7 @@ struct icid_id_table icid_tbl[] = { int icid_tbl_sz = ARRAY_SIZE(icid_tbl); -#ifdef CONFIG_SYS_DPAA_FMAN +#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD) struct fman_icid_id_table fman_icid_tbl[] = { /* port id, icid */ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 24d3f1f20c..f2361560e9 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -252,6 +252,8 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM select FSL_CORENET + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_L3_SIZE_256KB endchoice @@ -618,6 +620,9 @@ config ARCH_P2041 select E500MC select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME + select SYS_DPAA_RMAN select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A005275 @@ -762,6 +767,7 @@ config ARCH_T1024 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008109 @@ -792,6 +798,8 @@ config ARCH_T1040 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -822,6 +830,8 @@ config ARCH_T1042 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_FMAN + select SYS_DPAA_PME select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008378 @@ -851,6 +861,10 @@ config ARCH_T2080 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006593 @@ -871,6 +885,7 @@ config ARCH_T2080 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -886,6 +901,10 @@ config ARCH_T4240 select FSL_CORENET select FSL_LAW select SYS_CACHE_SHIFT_6 + select SYS_DPAA_DCE if !NOBQFMAN + select SYS_DPAA_FMAN if !NOBQFMAN + select SYS_DPAA_PME if !NOBQFMAN + select SYS_DPAA_RMAN if !NOBQFMAN select SYS_FSL_DDR_VER_47 select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A005871 @@ -907,6 +926,7 @@ config ARCH_T4240 select SYS_FSL_SRIO_LIODN select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN select SYS_FSL_USB_DUAL_PHY_ENABLE + select SYS_PMAN if !NOBQFMAN select SYS_PPC64 select FSL_IFC imply CMD_SATA @@ -947,6 +967,9 @@ config E6500 help Enable PowerPC E6500 core +config NOBQFMAN + bool + config FSL_LAW bool help @@ -1019,6 +1042,15 @@ config SYS_CCSRBAR_DEFAULT if changed by pre-boot regime. The value here must match the current value in SoC. If not sure, do not change. +config SYS_DPAA_PME + bool + +config SYS_DPAA_DCE + bool + +config SYS_DPAA_RMAN + bool + config A003399_NOR_WORKAROUND bool help @@ -1195,6 +1227,9 @@ config FSL_PCIE_DISABLE_ASPM config FSL_PCIE_RESET bool +config SYS_PMAN + bool + config SYS_FSL_RAID_ENGINE bool diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e996dbaa4d..8c7b877bfb 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -36,7 +36,6 @@ #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #ifndef __ASSEMBLY__ #include @@ -281,9 +280,6 @@ #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 6d6e334bf0..154b2f174a 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -395,8 +395,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 423ba81617..847cf65b40 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -366,9 +366,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2efc2eb95c..b49c264776 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -388,12 +388,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ca8bfac0c6..aae41a3392 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -342,12 +342,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 091920dccf..9dc45e397f 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -340,12 +340,6 @@ CONFIG_SYS_QMAN_CENA_SIZE) #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 1df90def67..c8423fdfb0 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -372,9 +372,6 @@ int get_scl(void); #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ #define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 6fc509af23..df6338298b 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -103,7 +103,6 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 3934fbbb41..b09588f479 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -67,7 +67,6 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #endif From f16b1a6c0082fc29371776096986d56c21851565 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:35 -0500 Subject: [PATCH 021/424] spl: Migrate SYS_SATA_FAT_BOOT_PARTITION to Kconfig This moves SYS_SATA_FAT_BOOT_PARTITION to Kconfig and enforces the current default via Kconfig rather than C code. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- common/spl/Kconfig | 5 +++++ common/spl/spl_sata.c | 4 ---- include/configs/imx6_spl.h | 5 ----- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index fef01bdd7d..c6da4a403e 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1232,6 +1232,11 @@ config SPL_SATA expense and power consumption. This enables loading from SATA using a configured device. +config SYS_SATA_FAT_BOOT_PARTITION + int "Partition on the SATA disk to load U-Boot from" + depends on SPL_SATA && SPL_FS_FAT + default 1 + config SPL_SATA_RAW_U_BOOT_USE_SECTOR bool "SATA raw mode: by sector" depends on SPL_SATA diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 9ae0273068..12397f0ae1 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -17,10 +17,6 @@ #include #include -#ifndef CONFIG_SYS_SATA_FAT_BOOT_PARTITION -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - #ifndef CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR /* Dummy value to make the compiler happy */ #define CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR 0x100 diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 3afe418b67..f34988fdd7 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -10,11 +10,6 @@ /* MMC support */ -/* SATA support */ -#if defined(CONFIG_SPL_SATA) -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - #endif #endif From aec118ebe63f7f0ab60916f9906fb3cb680abf7a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:36 -0500 Subject: [PATCH 022/424] imx6/imx7: Remove now empty imx6_spl.h and imx7_spl.h There are now no flags being set in these files, so remove them. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/apalis_imx6.h | 4 ---- include/configs/brppt2.h | 5 ----- include/configs/cl-som-imx7.h | 3 --- include/configs/cm_fx6.h | 3 --- include/configs/colibri_imx6.h | 4 ---- include/configs/dart_6ul.h | 3 --- include/configs/dh_imx6.h | 3 --- include/configs/display5.h | 2 -- include/configs/el6x_common.h | 4 ---- include/configs/embestmx6boards.h | 6 ------ include/configs/ge_b1x5v2.h | 2 -- include/configs/gw_ventana.h | 1 - include/configs/imx6-engicam.h | 5 ----- include/configs/imx6_logic.h | 4 ---- include/configs/imx6_spl.h | 15 --------------- include/configs/imx6dl-mamoj.h | 3 --- include/configs/imx6q-bosch-acc.h | 1 - include/configs/imx6ulz_smm_m2.h | 3 --- include/configs/imx7-cm.h | 3 --- include/configs/imx7_spl.h | 19 ------------------- include/configs/kontron-sl-mx6ul.h | 3 --- include/configs/kp_imx6q_tpc.h | 3 --- include/configs/liteboard.h | 3 --- include/configs/mccmon6.h | 2 -- include/configs/mx6cuboxi.h | 2 -- include/configs/mx6memcal.h | 1 - include/configs/mx6sabreauto.h | 4 ---- include/configs/mx6sabresd.h | 4 ---- include/configs/mx6slevk.h | 4 ---- include/configs/mx6sxsabresd.h | 4 ---- include/configs/mx6ul_14x14_evk.h | 3 --- include/configs/mys_6ulx.h | 3 --- include/configs/novena.h | 3 --- include/configs/npi_imx6ull.h | 3 --- include/configs/opos6uldev.h | 4 ---- include/configs/pcl063.h | 3 --- include/configs/pcl063_ull.h | 3 --- include/configs/pcm058.h | 4 ---- include/configs/pico-imx6.h | 8 -------- include/configs/pico-imx6ul.h | 7 ------- include/configs/pico-imx7d.h | 8 -------- include/configs/somlabs_visionsom_6ull.h | 4 ---- include/configs/tqma6.h | 7 ------- include/configs/udoo.h | 2 -- include/configs/udoo_neo.h | 2 -- include/configs/vining_2000.h | 4 ---- include/configs/wandboard.h | 2 -- include/configs/xpress.h | 3 --- 48 files changed, 196 deletions(-) delete mode 100644 include/configs/imx6_spl.h delete mode 100644 include/configs/imx7_spl.h diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 192c9cf0c3..30d32d27e3 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -15,10 +15,6 @@ #include #include -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 0c7fe5f3ab..bdedf7ea2d 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -86,9 +86,4 @@ BUR_COMMON_ENV \ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" - -#endif /* CONFIG_SPL */ #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index cbf85341a6..fc45e597f6 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -101,7 +101,4 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 2cb09fa30d..25443629e2 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -143,9 +143,6 @@ /* misc */ -/* SPL */ -#include "imx6_spl.h" - /* Display */ #define CONFIG_IMX_HDMI diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14fdf5b50e..68d923c1ae 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -15,10 +15,6 @@ #include #include -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 6079596cae..b944d50663 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -10,9 +10,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - /* NAND pin conflicts with usdhc2 */ #ifdef CONFIG_CMD_NAND #define CFG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 54b2192b4a..e694dd7551 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -21,9 +21,6 @@ * 0x12_0000-0x1f_ffff ... UNUSED */ -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */ /* MMC Configs */ diff --git a/include/configs/display5.h b/include/configs/display5.h index eb65f17cbe..0e5ecab9fe 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -34,8 +34,6 @@ #define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 #define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART5_BASE /* I2C Configs */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index affe20a101..16d2648e11 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -12,10 +12,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 555239b8e8..a4891ddbc4 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -49,12 +49,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -/* RiOTboard */ - -#endif - /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, * 1M script, 1M pxe and the ramdisk at the end */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 176f80bb09..c862f15ee2 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* PWM */ #define CONFIG_IMX6_PWM_PER_CLK 66000000 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a9ef35ebeb..645ca162a3 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -13,7 +13,6 @@ /* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" /* Serial */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index e430efad42..b8eb5c82cf 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -142,9 +142,4 @@ # define CONFIG_IMX_VIDEO_SKIP #endif -/* SPL */ -#ifdef CONFIG_SPL -# include "imx6_spl.h" -#endif - #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 7760c8c418..6b822e7250 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -11,10 +11,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h" /* MMC Configs */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h deleted file mode 100644 index f34988fdd7..0000000000 --- a/include/configs/imx6_spl.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey - */ -#ifndef __IMX6_SPL_CONFIG_H -#define __IMX6_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif - -#endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 909453cd66..f7f8f33ed8 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -59,7 +59,4 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* SPL */ -#include "imx6_spl.h" - #endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 5025ad9d9f..15171d7ad6 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -91,7 +91,6 @@ /* SPL */ #ifdef CONFIG_SPL -#include "imx6_spl.h" #ifdef CONFIG_SPL_BUILD #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index d42eb750d0..70b4b84215 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -12,9 +12,6 @@ #include #include -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART4_BASE #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index caa6a11d40..c6db5e943e 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -83,7 +83,4 @@ #define CONFIG_USBD_HS -/* SPL */ -#include "imx7_spl.h" - #endif /* __CONFIG_H */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h deleted file mode 100644 index 362b98075f..0000000000 --- a/include/configs/imx7_spl.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SPL definitions for the i.MX7 SPL - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach - */ - -#ifndef __IMX7_SPL_CONFIG_H -#define __IMX7_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -/* MMC support */ - -#endif /* CONFIG_SPL */ - -#endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index d3447a80ca..b3e1fc2a86 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -11,9 +11,6 @@ #include #include "mx6_common.h" -#ifdef CONFIG_SPL_BUILD -#include "imx6_spl.h" -#endif /* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 1823a79398..b0e49ad6df 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* Miscellaneous configurable options */ /* FEC ethernet */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a784002158..1d51b87b68 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -13,9 +13,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 69ca7c5275..f9f0825f6f 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,8 +9,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) /* diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index bc90b9563a..1db4d6c01b 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -11,8 +11,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index ad53f17d67..a6cefab550 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -11,7 +11,6 @@ /* SPL */ #include "mx6_common.h" -#include "imx6_spl.h" #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 8176566f3f..3fdf829e96 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -8,10 +8,6 @@ #ifndef __MX6SABREAUTO_CONFIG_H #define __MX6SABREAUTO_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 49cd1512dc..0d06b6dc46 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -8,10 +8,6 @@ #ifndef __MX6SABRESD_CONFIG_H #define __MX6SABRESD_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 26b97bd3f2..ca1d077437 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 83779f09bf..c655671ee1 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -12,10 +12,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index d0e3d3f028..65f0a5c996 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -15,9 +15,6 @@ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index e18d16cc99..273f938554 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -10,9 +10,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index f2a04ca618..9dc05d80ec 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -34,9 +34,6 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - /* I2C */ #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 2a52885082..ea407c9f6f 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -10,9 +10,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 3e551e13aa..b3cdd2f1eb 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - /* Miscellaneous configurable options */ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index bc04c50821..6267dc729a 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -11,9 +11,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - /* * There is a bug in some i.MX6UL processors that results in the initial * portion of OCRAM being unavailable when booting from (at least) an SD diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 817fabfb97..e13b5df0fa 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -13,9 +13,6 @@ #include #include "mx6_common.h" -/* SPL options */ -#include "imx6_spl.h" - #define CFG_SYS_FSL_USDHC_NUM 2 /* Environment settings */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 01190904cf..14cbfde28b 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -6,10 +6,6 @@ #ifndef __PCM058_CONFIG_H #define __PCM058_CONFIG_H -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #include "mx6_common.h" #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 687133b9bd..f95beeb214 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -10,14 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index d4f58b6a7b..85772ba6e8 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -12,13 +12,6 @@ #include #include "mx6_common.h" #include -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif /* Network support */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 159bf4c68c..b3a38d8a94 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,14 +10,6 @@ #include "mx7_common.h" -#include "imx7_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 49672dfe7c..dcb88a3a73 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -13,10 +13,6 @@ #include "mx6_common.h" #include -/* SPL options */ -#include "imx6_spl.h" - - /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 2c58915895..a65ebfb4de 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -11,13 +11,6 @@ #include #include -/* SPL */ -/* #if defined(CONFIG_SPL_BUILD) */ -/* common IMX6 SPL configuration */ -#include "imx6_spl.h" - -/* #endif */ - /* place code in last 4 MiB of RAM */ #include "mx6_common.h" diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 8af5151c50..268c737e7e 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -10,8 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART2_BASE /* MMC Configuration */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 093e2e8dae..147224806f 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a4484fd3f8..a0846b3f7c 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -10,10 +10,6 @@ #include "mx6_common.h" -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(MMC, mmc, 1) \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 91c1f4b3b5..b4c757fd92 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -10,8 +10,6 @@ #include "mx6_common.h" -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index fc8ec3204b..7d0402feea 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include -/* SPL options */ -#include "imx6_spl.h" - #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ From aa6e94deabb45154cea07ad44c4a5c047bca078b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:37 -0500 Subject: [PATCH 023/424] global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 2 +- arch/arc/lib/cache.c | 4 +- arch/arc/lib/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +-- arch/arm/dts/rockchip-optee.dtsi | 4 +- arch/arm/include/asm/emif.h | 2 +- arch/arm/include/asm/iproc-common/configs.h | 2 +- arch/arm/mach-aspeed/ast2500/board_common.c | 2 +- arch/arm/mach-aspeed/ast2600/board_common.c | 2 +- arch/arm/mach-at91/arm920t/lowlevel_init.S | 48 +++++++++---------- arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 48 +++++++++---------- arch/arm/mach-davinci/misc.c | 4 +- arch/arm/mach-exynos/dmc_init_ddr3.c | 2 +- arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- arch/arm/mach-imx/mx6/litesom.c | 2 +- arch/arm/mach-imx/mx6/opos6ul.c | 2 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-k3/r5_mpu.c | 2 +- arch/arm/mach-keystone/ddr3.c | 2 +- arch/arm/mach-mediatek/mt7623/init.c | 4 +- arch/arm/mach-mediatek/mt7981/init.c | 2 +- arch/arm/mach-mediatek/mt7986/init.c | 2 +- arch/arm/mach-mvebu/alleycat5/cpu.c | 6 +-- arch/arm/mach-mvebu/arm64-common.c | 2 +- arch/arm/mach-mvebu/armada8k/dram.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 6 +-- arch/arm/mach-omap2/emif-common.c | 8 ++-- arch/arm/mach-omap2/sec-common.c | 4 +- arch/arm/mach-owl/soc.c | 2 +- arch/arm/mach-rockchip/sdram.c | 16 +++---- arch/arm/mach-socfpga/board.c | 2 +- arch/arm/mach-sunxi/dram_helpers.c | 8 ++-- arch/arm/mach-sunxi/dram_suniv.c | 20 ++++---- arch/arm/mach-sunxi/dram_sunxi_dw.c | 6 +-- arch/arm/mach-tegra/board2.c | 4 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/m68k/cpu/mcf532x/speed.c | 2 +- arch/m68k/include/asm/immap.h | 4 +- arch/m68k/lib/traps.c | 2 +- arch/mips/lib/traps.c | 2 +- arch/mips/mach-jz47xx/jz4780/jz4780.c | 2 +- arch/mips/mach-mscc/cpu.c | 8 ++-- arch/mips/mach-mscc/dram.c | 2 +- arch/mips/mach-mscc/include/mach/ddr.h | 2 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 2 +- arch/mips/mach-octeon/dram.c | 2 +- arch/nios2/cpu/cpu.c | 2 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 2 +- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 2 +- arch/powerpc/lib/bootm.c | 2 +- arch/sandbox/cpu/state.c | 2 +- arch/sandbox/dts/sandbox.dts | 2 +- arch/sandbox/dts/sandbox64.dts | 2 +- arch/sh/cpu/u-boot.lds | 2 +- arch/sh/lib/board.c | 4 +- arch/sh/lib/bootm.c | 2 +- arch/xtensa/cpu/cpu.c | 2 +- board/BuR/brppt1/board.c | 2 +- board/BuS/eb_cpu5282/eb_cpu5282.c | 20 ++++---- board/CZ.NIC/turris_mox/turris_mox.c | 2 +- board/Marvell/mvebu_alleycat-5/board.c | 2 +- board/Marvell/mvebu_armada-37xx/board.c | 2 +- board/Marvell/mvebu_armada-8k/board.c | 2 +- board/Marvell/octeontx/board.c | 2 +- board/Marvell/octeontx2/board.c | 2 +- board/Marvell/octeontx2_cn913x/board.c | 2 +- board/armltd/integrator/integrator.c | 6 +-- board/armltd/vexpress/vexpress_common.c | 2 +- board/astro/mcf5373l/mcf5373l.c | 12 ++--- board/atmel/at91sam9260ek/at91sam9260ek.c | 6 +-- board/atmel/at91sam9261ek/at91sam9261ek.c | 6 +-- board/atmel/at91sam9263ek/at91sam9263ek.c | 6 +-- .../atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 6 +-- board/atmel/at91sam9n12ek/at91sam9n12ek.c | 6 +-- board/atmel/at91sam9rlek/at91sam9rlek.c | 6 +-- board/atmel/at91sam9x5ek/at91sam9x5ek.c | 6 +-- board/atmel/sam9x60ek/sam9x60ek.c | 6 +-- .../sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 6 +-- board/atmel/sama5d2_icp/sama5d2_icp.c | 6 +-- board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 6 +-- .../atmel/sama5d3_xplained/sama5d3_xplained.c | 6 +-- board/atmel/sama5d3xek/sama5d3xek.c | 6 +-- .../atmel/sama5d4_xplained/sama5d4_xplained.c | 6 +-- board/atmel/sama5d4ek/sama5d4ek.c | 6 +-- board/atmel/sama7g5ek/sama7g5ek.c | 6 +-- board/bluewater/gurnard/gurnard.c | 6 +-- board/bosch/guardian/board.c | 2 +- board/bosch/shc/board.c | 2 +- board/broadcom/bcm_ep/board.c | 8 ++-- board/calao/usb_a9263/usb_a9263.c | 6 +-- board/cobra5272/cobra5272.c | 2 +- board/compulab/cm_t43/cm_t43.c | 2 +- board/compulab/cm_t43/spl.c | 4 +- board/cssi/MCR3000/MCR3000.c | 2 +- .../ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 4 +- board/eets/pdu001/board.c | 2 +- board/egnite/ethernut5/ethernut5.c | 6 +-- board/emulation/qemu-arm/qemu-arm.c | 2 +- board/esd/meesc/meesc.c | 2 +- board/freescale/common/arm_sleep.c | 2 +- board/freescale/common/mpc85xx_sleep.c | 2 +- board/freescale/ls1012afrdm/ls1012afrdm.c | 4 +- board/freescale/ls1012aqds/ls1012aqds.c | 4 +- board/freescale/ls1012ardb/ls1012ardb.c | 4 +- board/freescale/ls1021aqds/ddr.c | 2 +- board/freescale/ls1021atsn/ls1021atsn.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 2 +- board/freescale/m5208evbe/m5208evbe.c | 26 +++++----- board/freescale/m5235evb/m5235evb.c | 8 ++-- board/freescale/m5249evb/m5249evb.c | 2 +- board/freescale/m5253demo/m5253demo.c | 6 +-- board/freescale/m5272c3/m5272c3.c | 2 +- board/freescale/m5275evb/m5275evb.c | 18 +++---- board/freescale/m5282evb/m5282evb.c | 8 ++-- board/freescale/m53017evb/README | 2 +- board/freescale/m53017evb/m53017evb.c | 26 +++++----- board/freescale/m5329evb/m5329evb.c | 24 +++++----- board/freescale/m5373evb/README | 2 +- board/freescale/m5373evb/m5373evb.c | 24 +++++----- board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +-- board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/p1_p2_rdb_pc/ddr.c | 2 +- board/friendlyarm/nanopi2/board.c | 8 ++-- board/gardena/smart-gateway-at91sam/board.c | 6 +-- board/gdsys/mpc8308/sdram.c | 6 +-- board/grinn/chiliboard/board.c | 2 +- board/imgtec/boston/ddr.c | 2 +- board/imgtec/malta/lowlevel_init.S | 4 +- board/imgtec/malta/malta.c | 2 +- board/imgtec/xilfpga/xilfpga.c | 2 +- board/inversepath/usbarmory/usbarmory.c | 2 +- board/isee/igep003x/board.c | 2 +- board/keymile/common/common.c | 4 +- board/keymile/km83xx/km83xx.c | 6 +-- board/keymile/pg-wcom-ls102xa/ddr.c | 2 +- .../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 2 +- board/l+g/vinco/vinco.c | 6 +-- board/mediatek/mt7622/mt7622_rfb.c | 2 +- board/mediatek/mt7623/mt7623_rfb.c | 2 +- board/mediatek/mt7629/mt7629_rfb.c | 2 +- board/mediatek/mt8518/mt8518_ap1.c | 2 +- board/mscc/jr2/jr2.c | 2 +- board/mscc/luton/luton.c | 2 +- board/mscc/ocelot/ocelot.c | 2 +- board/mscc/serval/serval.c | 2 +- board/mscc/servalt/servalt.c | 2 +- board/phytec/phycore_am335x_r2/board.c | 4 +- board/phytium/pomelo/pomelo.c | 2 +- board/renesas/alt/alt.c | 2 +- board/renesas/blanche/blanche.c | 2 +- board/renesas/gose/gose.c | 2 +- board/renesas/grpeach/grpeach.c | 2 +- board/renesas/koelsch/koelsch.c | 2 +- board/renesas/lager/lager.c | 2 +- board/renesas/porter/porter.c | 2 +- board/renesas/silk/silk.c | 2 +- board/renesas/stout/stout.c | 2 +- board/ronetix/pm9g45/pm9g45.c | 10 ++-- board/samsung/arndale/arndale.c | 4 +- board/samsung/common/board.c | 4 +- board/sandbox/sandbox.c | 4 +- board/siemens/common/board.c | 2 +- board/siemens/corvus/board.c | 6 +-- board/siemens/iot2050/board.c | 2 +- board/siemens/smartweb/smartweb.c | 6 +-- board/siemens/taurus/taurus.c | 10 ++-- board/sipeed/maix/maix.c | 2 +- board/socrates/sdram.c | 4 +- board/softing/vining_fpga/socfpga.c | 2 +- board/solidrun/mx6cuboxi/mx6cuboxi.c | 4 +- board/sysam/amcore/amcore.c | 6 +-- board/sysam/stmark2/stmark2.c | 2 +- board/tbs/tbs2910/tbs2910.c | 2 +- board/tcl/sl50/board.c | 2 +- board/ti/am335x/board.c | 2 +- board/ti/am43xx/board.c | 2 +- board/ti/am57xx/board.c | 2 +- board/ti/am65x/evm.c | 4 +- board/ti/dra7xx/evm.c | 2 +- board/ti/j721e/evm.c | 4 +- board/ti/j721s2/evm.c | 4 +- board/ti/ks2_evm/board.c | 12 ++--- board/ti/ti816x/evm.c | 2 +- board/timll/devkit3250/devkit3250.c | 6 +-- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/vscom/baltos/board.c | 2 +- board/work-microwave/work_92105/work_92105.c | 6 +-- board/xilinx/zynq/board.c | 6 +-- board/xilinx/zynqmp/zynqmp.c | 8 ++-- boot/image-board.c | 4 +- cmd/ti/ddr3.c | 18 +++---- common/board_f.c | 8 ++-- doc/arch/m68k.rst | 16 +++---- doc/arch/nios2.rst | 4 +- drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +- drivers/ddr/fsl/main.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/ddr/marvell/axp/ddr3_axp.h | 4 +- drivers/pci/Kconfig | 2 +- drivers/pci/pci-rcar-gen2.c | 4 +- drivers/pci/pci_sh7751.c | 6 +-- drivers/pci/pcie_dw_mvebu.c | 4 +- drivers/pci/pcie_layerscape.h | 4 +- drivers/ram/aspeed/sdram_ast2500.c | 4 +- drivers/ram/aspeed/sdram_ast2600.c | 6 +-- drivers/ram/mediatek/ddr3-mt7629.c | 12 ++--- drivers/ram/octeon/octeon_ddr.c | 2 +- drivers/ram/rockchip/dmc-rk3368.c | 12 ++--- drivers/ram/rockchip/sdram_common.c | 34 ++++++------- drivers/ram/rockchip/sdram_px30.c | 2 +- drivers/ram/rockchip/sdram_rk3066.c | 14 +++--- drivers/ram/rockchip/sdram_rk3128.c | 2 +- drivers/ram/rockchip/sdram_rk3188.c | 14 +++--- drivers/ram/rockchip/sdram_rk322x.c | 24 +++++----- drivers/ram/rockchip/sdram_rk3288.c | 14 +++--- drivers/ram/rockchip/sdram_rk3308.c | 2 +- drivers/ram/rockchip/sdram_rk3328.c | 2 +- drivers/ram/rockchip/sdram_rk3399.c | 2 +- drivers/ram/rockchip/sdram_rk3568.c | 2 +- drivers/usb/host/ehci-rmobile.c | 4 +- drivers/video/sunxi/sunxi_display.c | 4 +- include/configs/10m50_devboard.h | 4 +- include/configs/3c120_devboard.h | 4 +- include/configs/M5208EVBE.h | 22 ++++----- include/configs/M5235EVB.h | 12 ++--- include/configs/M5249EVB.h | 12 ++--- include/configs/M5253DEMO.h | 12 ++--- include/configs/M5272C3.h | 12 ++--- include/configs/M5275EVB.h | 12 ++--- include/configs/M5282EVB.h | 12 ++--- include/configs/M53017EVB.h | 22 ++++----- include/configs/M5329EVB.h | 22 ++++----- include/configs/M5373EVB.h | 22 ++++----- include/configs/MCR3000.h | 4 +- include/configs/MPC837XERDB.h | 4 +- include/configs/MPC8548CDS.h | 2 +- include/configs/P1010RDB.h | 4 +- include/configs/P2041RDB.h | 4 +- include/configs/SBx81LIFKW.h | 2 +- include/configs/SBx81LIFXCAT.h | 2 +- include/configs/T102xRDB.h | 6 +-- include/configs/T104xRDB.h | 4 +- include/configs/T208xQDS.h | 4 +- include/configs/T208xRDB.h | 4 +- include/configs/T4240RDB.h | 4 +- include/configs/am62x_evm.h | 2 +- include/configs/am64x_evm.h | 2 +- include/configs/am65x_evm.h | 2 +- include/configs/amcore.h | 4 +- include/configs/ap121.h | 2 +- include/configs/ap143.h | 2 +- include/configs/ap152.h | 2 +- include/configs/apalis-imx8.h | 2 +- include/configs/apalis_imx6.h | 2 +- include/configs/arbel.h | 4 +- include/configs/aristainetos2.h | 2 +- include/configs/aspeed-common.h | 2 +- include/configs/astro_mcf5373l.h | 12 ++--- include/configs/at91sam9260ek.h | 4 +- include/configs/at91sam9261ek.h | 4 +- include/configs/at91sam9263ek.h | 28 +++++------ include/configs/at91sam9m10g45ek.h | 4 +- include/configs/at91sam9n12ek.h | 4 +- include/configs/at91sam9rlek.h | 4 +- include/configs/at91sam9x5ek.h | 4 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 4 +- include/configs/bcm947622.h | 2 +- include/configs/bcm94908.h | 2 +- include/configs/bcm94912.h | 2 +- include/configs/bcm963138.h | 2 +- include/configs/bcm963146.h | 2 +- include/configs/bcm963148.h | 2 +- include/configs/bcm963158.h | 2 +- include/configs/bcm963178.h | 2 +- include/configs/bcm96756.h | 2 +- include/configs/bcm96813.h | 2 +- include/configs/bcm96846.h | 2 +- include/configs/bcm96855.h | 2 +- include/configs/bcm96856.h | 2 +- include/configs/bcm96858.h | 2 +- include/configs/bcm96878.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/bitmain_antminer_s9.h | 4 +- include/configs/bk4r1.h | 2 +- include/configs/bmips_bcm3380.h | 2 +- include/configs/bmips_bcm6318.h | 2 +- include/configs/bmips_bcm63268.h | 2 +- include/configs/bmips_bcm6328.h | 2 +- include/configs/bmips_bcm6338.h | 2 +- include/configs/bmips_bcm6348.h | 2 +- include/configs/bmips_bcm6358.h | 2 +- include/configs/bmips_bcm6362.h | 2 +- include/configs/bmips_bcm6368.h | 2 +- include/configs/bmips_bcm6838.h | 2 +- include/configs/boston.h | 4 +- include/configs/brppt2.h | 2 +- include/configs/bur_am335x_common.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/ci20.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/cobra5272.h | 12 ++--- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri-imx8x.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/colibri_imx7.h | 2 +- include/configs/colibri_vf.h | 2 +- include/configs/corstone1000.h | 2 +- include/configs/corvus.h | 4 +- include/configs/da850evm.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/devkit3250.h | 4 +- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/dragonboard410c.h | 2 +- include/configs/dragonboard820c.h | 2 +- include/configs/durian.h | 2 +- include/configs/ea-lpc3250devkitv2.h | 2 +- include/configs/eb_cpu5282.h | 14 +++--- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/emsdp.h | 4 +- include/configs/espresso7420.h | 2 +- include/configs/ethernut5.h | 4 +- include/configs/exynos5-common.h | 16 +++---- include/configs/exynos5250-common.h | 2 +- include/configs/exynos7420-common.h | 16 +++---- include/configs/exynos78x0-common.h | 26 +++++----- .../configs/gardena-smart-gateway-at91sam.h | 4 +- .../configs/gardena-smart-gateway-mt7688.h | 2 +- include/configs/gazerbeam.h | 6 +-- include/configs/ge_b1x5v2.h | 2 +- include/configs/ge_bx50v3.h | 2 +- include/configs/grpeach.h | 4 +- include/configs/gw_ventana.h | 2 +- include/configs/gxp.h | 2 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 4 +- include/configs/hsdk.h | 4 +- include/configs/imgtec_xilfpga.h | 4 +- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_beacon.h | 2 +- include/configs/imx8mn_bsh_smm_s2_common.h | 2 +- include/configs/imx8mn_evk.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mn_venice.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mp_venice.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/integrator-common.h | 2 +- include/configs/iot_devkit.h | 14 +++--- include/configs/j721e_evm.h | 2 +- include/configs/j721s2_evm.h | 2 +- include/configs/km/km-mpc83xx.h | 4 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 4 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/kp_imx53.h | 2 +- include/configs/kp_imx6q_tpc.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/librem5.h | 2 +- include/configs/linkit-smart-7688.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/ls1012a2g5rdb.h | 2 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1012afrdm.h | 2 +- include/configs/ls1012aqds.h | 2 +- include/configs/ls1012ardb.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 2 +- include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 4 +- include/configs/m53menlo.h | 2 +- include/configs/malta.h | 6 +-- include/configs/maxbcm.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/meerkat96.h | 2 +- include/configs/meesc.h | 4 +- include/configs/meson64.h | 2 +- include/configs/microchip_mpfs_icicle.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mt7620.h | 2 +- include/configs/mt7621.h | 2 +- include/configs/mt7622.h | 2 +- include/configs/mt7623.h | 2 +- include/configs/mt7628.h | 2 +- include/configs/mt7629.h | 2 +- include/configs/mt7981.h | 2 +- include/configs/mt7986.h | 2 +- include/configs/mt8518.h | 4 +- include/configs/mv-common.h | 2 +- include/configs/mvebu_alleycat-5.h | 2 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 2 +- include/configs/mx23_olinuxino.h | 2 +- include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53ppd.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mx7ulp_evk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/nokia_rx51.h | 4 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/nsim.h | 4 +- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/octeon_common.h | 2 +- include/configs/octeontx2_common.h | 2 +- include/configs/octeontx_common.h | 2 +- include/configs/odroid.h | 4 +- include/configs/odroid_xu3.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/openpiton-riscv64.h | 2 +- include/configs/opos6uldev.h | 2 +- include/configs/origen.h | 4 +- include/configs/owl-common.h | 2 +- include/configs/p1_p2_rdb_pc.h | 8 ++-- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pcm052.h | 2 +- include/configs/pcm058.h | 2 +- include/configs/peach-pi.h | 2 +- include/configs/peach-pit.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/pic32mzdask.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/pm9261.h | 26 +++++----- include/configs/pm9263.h | 26 +++++----- include/configs/pm9g45.h | 4 +- include/configs/poleg.h | 2 +- include/configs/pomelo.h | 2 +- include/configs/presidio_asic.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/qemu-arm.h | 2 +- include/configs/qemu-ppce500.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/r2dplus.h | 4 +- include/configs/rcar-gen2-common.h | 4 +- include/configs/rcar-gen3-common.h | 4 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rpi.h | 4 +- include/configs/rv1108_common.h | 2 +- include/configs/s5p4418_nanopi2.h | 4 +- include/configs/s5p_goni.h | 4 +- include/configs/s5pc210_universal.h | 4 +- include/configs/sam9x60_curiosity.h | 4 +- include/configs/sam9x60ek.h | 4 +- include/configs/sama5d27_wlsom1_ek.h | 4 +- include/configs/sama5d2_icp.h | 4 +- include/configs/sama5d2_ptc_ek.h | 4 +- include/configs/sama5d3_xplained.h | 4 +- include/configs/sama5d3xek.h | 4 +- include/configs/sama5d4_xplained.h | 4 +- include/configs/sama5d4ek.h | 4 +- include/configs/sama7g5ek.h | 4 +- include/configs/sandbox.h | 4 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/sifive-unmatched.h | 2 +- include/configs/sipeed-maix.h | 4 +- include/configs/smartweb.h | 4 +- include/configs/smdk5420.h | 2 +- include/configs/smdkc100.h | 4 +- include/configs/smdkv310.h | 10 ++-- include/configs/smegw01.h | 2 +- include/configs/snapper9g45.h | 4 +- include/configs/sniper.h | 2 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_soc64_common.h | 2 +- include/configs/socrates.h | 4 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stmark2.h | 14 +++--- include/configs/stv0991.h | 2 +- include/configs/sunxi-common.h | 8 ++-- include/configs/synquacer.h | 2 +- include/configs/taurus.h | 4 +- include/configs/tb100.h | 4 +- include/configs/tbs2910.h | 2 +- include/configs/tegra-common.h | 2 +- include/configs/theadorable.h | 2 +- include/configs/thunderx_88xx.h | 4 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_armv7_common.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/tplink_wdr4300.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/trats.h | 4 +- include/configs/trats2.h | 4 +- include/configs/turris_mox.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/usb_a9263.h | 4 +- include/configs/usbarmory.h | 2 +- include/configs/vcoreiii.h | 8 ++-- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- include/configs/vexpress_aemv8.h | 2 +- include/configs/vexpress_common.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vinco.h | 4 +- include/configs/vining_2000.h | 2 +- include/configs/vocore2.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/warp7.h | 2 +- include/configs/work_92105.h | 4 +- include/configs/xea.h | 2 +- include/configs/xenguest_arm64.h | 2 +- include/configs/xilinx_zynqmp_mini_nand.h | 4 +- include/configs/xpress.h | 2 +- include/configs/xtfpga.h | 10 ++-- include/init.h | 4 +- include/system-constants.h | 2 +- post/drivers/memory.c | 2 +- test/dm/remoteproc.c | 6 +-- 589 files changed, 1197 insertions(+), 1197 deletions(-) diff --git a/README b/README index 5ab042a2de..b095937121 100644 --- a/README +++ b/README @@ -1441,7 +1441,7 @@ Configuration Settings: the RAM base is not zero, or RAM is divided into banks, this variable needs to be recalcuated to get the address. -- CONFIG_SYS_SDRAM_BASE: +- CFG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. - CONFIG_SYS_FLASH_BASE: diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 4c696cb53a..d97a578742 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) static void arc_ioc_setup(void) { /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + unsigned int ap_base = CFG_SYS_SDRAM_BASE; /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; + long ap_size = CFG_SYS_SDRAM_SIZE; /* Unsupported configuration. See [ NOTE 2 ] for more details. */ if (!slc_exists()) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 6b215206a2..1567857961 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -20,7 +20,7 @@ int arch_cpu_init(void) timer_init(); gd->cpu_clk = get_board_sys_clk(); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; cache_init(); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index b4d113dc1e..954fa5f8b4 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -29,7 +29,7 @@ */ static void __secure ls1_save_ddr_head(void) { - const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; + const char *src = (const char *)CFG_SYS_SDRAM_BASE; char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ef71e2cf2b..bbaa91f0e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1441,7 +1441,7 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; @@ -1571,7 +1571,7 @@ void update_early_mmu_table(void) if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, gd->ram_size, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1579,7 +1579,7 @@ void update_early_mmu_table(void) PTE_TYPE_VALID); } else { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, CONFIG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi index 328ba90845..d84c10cf43 100644 --- a/arch/arm/dts/rockchip-optee.dtsi +++ b/arch/arm/dts/rockchip-optee.dtsi @@ -32,8 +32,8 @@ arch = "arm"; os = "tee"; compression = "none"; - load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; blob-ext { filename = "tee.bin"; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 35424345bf..2141a4581c 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -583,7 +583,7 @@ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 4733c0793c..c63c27dac7 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -12,6 +12,6 @@ #define CONFIG_IPROC /* Memory Info */ -#define CONFIG_SYS_SDRAM_BASE 0x61000000 +#define CFG_SYS_SDRAM_BASE 0x61000000 #endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index aca2002231..bae1027184 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index 82ff21908f..dc6cdc35d1 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -54,7 +54,7 @@ int board_init(void) int i = 0, rc; struct udevice *dev; - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; while (1) { rc = uclass_get_device(UCLASS_MISC, i++, &dev); diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 57e51c8105..3b91a0cba3 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -114,38 +114,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM1 + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index c51eee2f17..ecfe589e45 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -201,38 +201,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL3 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL4 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL5 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL6 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL7 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL8 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 73fdd1f243..42078b39f8 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -26,14 +26,14 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index fa867f27f3..cad8ccc531 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) * better have similar timings, since there's only a single adjustment that is * shared by both chips). */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; +const unsigned int test_addr = CFG_SYS_SDRAM_BASE; /* Test pattern with which RAM will be tested */ static const unsigned int test_pattern[] = { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a4863281e3..8050406613 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++) - if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 802cb0e2ba..5d95fb89a6 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++) - if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 699a3dc317..2ba3245e22 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -172,7 +172,7 @@ static void spl_dram_init(void) * Get actual RAM size, so we can adjust DDR row size for <512M * memories */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); if (ram_size < SZ_512M) { mem_ddr.rowaddr = 14; mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index e9d78740a1..38ead8ace2 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -44,7 +44,7 @@ static int setup_fec(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6b8f4115c4..cb9801b7a1 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = imx_ddr_size(); return 0; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 227706e8dc..d5e1f8e2e7 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + phys_addr_t ram_top = CFG_SYS_SDRAM_BASE; dram_init(); diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 3d2ff6775a..2aec96277e 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = { O_I_WB_RD_WR_ALLOC, REGION_8MB}, /* U-Boot's code area marking it as WB and Write allocate */ - {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_2GB}, /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 53117c2695..ea7d0b903c 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size) } ddr3_ecc_init_range(base); - ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); + ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size); /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 5d837e0597..988b057e59 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -25,7 +25,7 @@ int dram_init(void) { u32 i; - if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) && ((size_t)preloader_param % sizeof(size_t) == 0) && preloader_param->magic == BOOT_ARGUMENT_MAGIC && preloader_param->dram_rank_num <= @@ -35,7 +35,7 @@ int dram_init(void) for (i = 0; i < preloader_param->dram_rank_num; i++) gd->ram_size += preloader_param->dram_rank_size[i]; } else { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SZ_2G); } diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index a8955064e0..d8b10f0358 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index cf89e63e80..fb74b2f34d 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index cc7f9794c5..8204d96275 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region ac5_mem_map[] = { { /* RAM */ - .phys = CONFIG_SYS_SDRAM_BASE, - .virt = CONFIG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .virt = CFG_SYS_SDRAM_BASE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, @@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index e3098a7ca8..2c94f899f3 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); + unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index bab375e18a..6c801bfa1d 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,7 +38,7 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 44d5214a3d..86755d6d95 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -72,14 +72,14 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; @@ -520,7 +520,7 @@ void board_init_f(ulong dummy) sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 312f868fbc..a6a97af37d 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -389,7 +389,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region1 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -400,7 +400,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region2 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -1340,7 +1340,7 @@ void dmm_init(u32 base) mapped_size = 0; section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; + sys_addr = CFG_SYS_SDRAM_BASE; emif1_size = get_emif_mem_size(EMIF1_BASE); emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); @@ -1568,7 +1568,7 @@ void sdram_init(void) size_prog = log_2_n_round_down(size_prog); size_prog = (1 << size_prog); - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ if (size_detect != size_prog) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0551bc125e..0f9b915ea3 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -198,11 +198,11 @@ u32 get_sec_mem_start(void) */ if (sec_mem_start == 0) sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + ( + (CFG_SYS_SDRAM_BASE + ( #if defined(CONFIG_OMAP54XX) omap_sdram_size() #else - get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 4baef2eed3..f0f46f2dcb 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,7 +50,7 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 12f1d7ee56..e086c47f3c 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -37,7 +37,7 @@ struct tos_parameter_t { int dram_init_banksize(void) { - size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE), (unsigned long)(gd->ram_top)); #ifdef CONFIG_ARM64 @@ -48,26 +48,26 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_OPTEE_IMAGE struct tos_parameter_t *tos_parameter; - tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE + TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr - - CONFIG_SYS_SDRAM_BASE; + - CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } else { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE + gd->bd->bi_dram[0].size + 0x2000000; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } #else - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; #endif #endif @@ -207,7 +207,7 @@ int dram_init(void) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index b49006c6c8..09e09192fb 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -46,7 +46,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 2c873192e6..cdf2750f1c 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -33,11 +33,11 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val) bool mctl_mem_matches(u32 offset) { /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + writel(0, CFG_SYS_SDRAM_BASE); + writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset); dsb(); /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); + return readl(CFG_SYS_SDRAM_BASE) == + readl((ulong)CFG_SYS_SDRAM_BASE + offset); } #endif diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 56c2d557ff..3aa3ce7627 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -175,9 +175,9 @@ static int sdr_readpipe_scan(void) u32 k = 0; for (k = 0; k < 32; k++) - writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k); + writel(k, CFG_SYS_SDRAM_BASE + 4 * k); for (k = 0; k < 32; k++) { - if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k) + if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k) return 0; } return 1; @@ -266,11 +266,11 @@ static u32 dram_get_dram_size(struct dram_para *para) dram_para_setup(para); dram_scan_readpipe(para); for (i = 0; i < 32; i++) { - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; } for (i = 0; i < 32; i++) { - val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)); + val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)); if (val1 == 0x22) count++; } @@ -283,11 +283,11 @@ static u32 dram_get_dram_size(struct dram_para *para) para->row_width = rowflag; dram_para_setup(para); if (colflag == 10) { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000; + addr1 = CFG_SYS_SDRAM_BASE + 0x400000; + addr2 = CFG_SYS_SDRAM_BASE + 0xc00000; } else { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000; + addr1 = CFG_SYS_SDRAM_BASE + 0x200000; + addr2 = CFG_SYS_SDRAM_BASE + 0x600000; } for (i = 0; i < 32; i++) { *((u8 *)(addr1 + i)) = 0x33; @@ -319,7 +319,7 @@ static u32 dram_get_dram_size(struct dram_para *para) static void simple_dram_check(void) { - volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE; + volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE; int i; for (i = 0; i < 0x40; i++) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9107b114df..4af5922f33 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -711,7 +711,7 @@ static unsigned long mctl_calc_rank_size(struct rank_para *rank) */ static void mctl_r40_detect_rank_count(struct dram_para *para) { - ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE + + ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]); struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; @@ -744,10 +744,10 @@ static void mctl_r40_detect_rank_count(struct dram_para *para) static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]); if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); } } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 82d3d33502..54bbd8a776 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -370,7 +370,7 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PCI @@ -412,5 +412,5 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) /* fall back to default usable RAM computation */ - return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); + return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ac595ee0a2..3b6518c71c 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -54,7 +54,7 @@ int arch_cpu_init(void) writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); -#if (CONFIG_SYS_SDRAM_BASE == 0) +#if (CFG_SYS_SDRAM_BASE == 0) /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index e2985792d9..dac2229f72 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -239,7 +239,7 @@ int clock_pll(int fsys, int flags) * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); + out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE); #endif /* wait for DQS logic to relock */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index f2eb6fcb46..672aa0bb14 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -338,9 +338,9 @@ #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) -#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) #define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 0c2c1a9965..28fe803928 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -62,7 +62,7 @@ static void trap_init(ulong value) { int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 7577fdd25d..7a682f256a 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -135,7 +135,7 @@ void trap_restore(void) int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index cff98b0a77..15d1eff2ba 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -78,7 +78,7 @@ void board_init_f(ulong dummy) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); + return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } int print_cpuinfo(void) diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 5bc31006aa..d484eb92c4 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -17,16 +17,16 @@ DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M +#if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M +#elif CFG_SYS_SDRAM_SIZE <= SZ_128M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_RW -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M +#elif CFG_SYS_SDRAM_SIZE <= SZ_256M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M +#elif CFG_SYS_SDRAM_SIZE <= SZ_512M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_RW #else diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c53a4202e0..f7fbd33cc4 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -67,6 +67,6 @@ int print_cpuinfo(void) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d52eabbd2b..75fb3ca00d 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -13,7 +13,7 @@ #include #define MIPS_VCOREIII_MEMORY_DDR3 -#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE +#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */ diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 3cad3567e7..6b9f253952 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -18,7 +18,7 @@ #include "dram.h" #ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ +#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) #endif diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 9c5789b1c8..85cb084c13 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -81,7 +81,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ - return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, + return CFG_SYS_SDRAM_BASE + min(gd->ram_size, UBOOT_RAM_SIZE_MAX); } else { return gd->ram_top; diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 4dd9c10faa..85544503a5 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -73,7 +73,7 @@ static int nios_cpu_setup(void *ctx, struct event *event) if (ret) return ret; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #ifndef CONFIG_ROM_STUBS copy_exception_trampoline(); #endif diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index e12043b260..6d1c6b055c 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -288,7 +288,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b0363c9c10..6acd31d284 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -424,7 +424,7 @@ int dram_init(void) defined(CONFIG_ARCH_QEMU_E500) gd->ram_size = fsl_ddr_sdram_size(); #else - gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024; #endif return 0; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index f109ecb9ff..44f8ed8a19 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -195,7 +195,7 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? CONFIG_MAX_MEM_MAPPED : gd->ram_size) + - CONFIG_SYS_SDRAM_BASE - 4096; + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index d917e9dfb6..71496ab294 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -16,7 +16,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) int j; tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); + (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8ae8d8a3e7..1df0822e9d 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -126,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb) #ifdef DEBUG if (((u64)bootmap_base + bootm_size) > - (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size)) + (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) puts("WARNING: bootm_low + bootm_size exceed total memory\n"); if ((bootmap_base + bootm_size) > get_effective_memsize()) puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index a681e472ab..dd7978cfce 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -448,7 +448,7 @@ int state_init(void) { state = &main_state; - state->ram_size = CONFIG_SYS_SDRAM_SIZE; + state->ram_size = CFG_SYS_SDRAM_SIZE; state->ram_buf = os_malloc(state->ram_size); if (!state->ram_buf) { printf("Out of memory\n"); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2051207f0b..88b57bfb7e 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -25,7 +25,7 @@ }; memory { - reg = <0 CONFIG_SYS_SDRAM_SIZE>; + reg = <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 3eb0457089..a9cd7908f8 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -21,7 +21,7 @@ }; memory { - reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>; + reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 85ee547b4a..d360eea7eb 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -18,7 +18,7 @@ OUTPUT_ARCH(sh) MEMORY { - ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE + ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE } ENTRY(_start) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 3fa093a02e..b31fa6d703 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index a5fad6c46c..b205e5e3db 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -88,7 +88,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200); set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001); set_sh_linux_param((unsigned long)param + INITRD_START, - GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE)); + GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE)); set_sh_linux_param((unsigned long)param + INITRD_SIZE, images->rd_end - images->rd_start); } diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index a09e103fc1..98d9753b7e 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -45,7 +45,7 @@ int print_cpuinfo(void) int arch_cpu_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index c8dc186cdd..36945bbdcc 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -150,7 +150,7 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index 2b08930af6..f9a37e7215 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -40,8 +40,8 @@ int dram_init(void) MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); asm (" nop"); -#ifdef CONFIG_SYS_SDRAM_BASE0 - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)| +#ifdef CFG_SYS_SDRAM_BASE0 + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32; asm (" nop"); @@ -54,7 +54,7 @@ int dram_init(void) for (i = 0; i < 10; i++) asm (" nop"); - *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; + *(unsigned long *)(CFG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; asm (" nop"); @@ -65,12 +65,12 @@ int dram_init(void) MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; asm (" nop"); /* write SDRAM mode register */ - *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; + *(unsigned long *)(CFG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; asm (" nop"); - size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024; + size += CFG_SYS_SDRAM_SIZE0 * 1024 * 1024; #endif -#ifdef CONFIG_SYS_SDRAM_BASE1xx - MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1) +#ifdef CFG_SYS_SDRAM_BASE1xx + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -79,15 +79,15 @@ int dram_init(void) MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5; + *(unsigned short *) (CFG_SYS_SDRAM_BASE1) = 0xA5A5; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; - *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; - size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024; + *(unsigned int *) (CFG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CFG_SYS_SDRAM_SIZE1 * 1024 * 1024; #endif gd->ram_size = size; diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index ff1c4cb170..a52a032e4d 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -139,7 +139,7 @@ int board_fix_fdt(void *blob) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/mvebu_alleycat-5/board.c b/board/Marvell/mvebu_alleycat-5/board.c index 619cd6c6cd..0c4f8e03b8 100644 --- a/board/Marvell/mvebu_alleycat-5/board.c +++ b/board/Marvell/mvebu_alleycat-5/board.c @@ -7,7 +7,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index c6ecc323bb..45fe3e5f0b 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -80,7 +80,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/mvebu_armada-8k/board.c b/board/Marvell/mvebu_armada-8k/board.c index 77c7dd7ab0..a8899af6e5 100644 --- a/board/Marvell/mvebu_armada-8k/board.c +++ b/board/Marvell/mvebu_armada-8k/board.c @@ -150,7 +150,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c index 059ebf8f17..224653519b 100644 --- a/board/Marvell/octeontx/board.c +++ b/board/Marvell/octeontx/board.c @@ -63,7 +63,7 @@ int timer_init(void) int dram_init(void) { gd->ram_size = smc_dram_size(0); - gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + gd->ram_size -= CFG_SYS_SDRAM_BASE; mem_map_fill(); return 0; diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c index 63aa2d6134..e7899f49f0 100644 --- a/board/Marvell/octeontx2/board.c +++ b/board/Marvell/octeontx2/board.c @@ -105,7 +105,7 @@ int timer_init(void) int dram_init(void) { gd->ram_size = smc_dram_size(0); - gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + gd->ram_size -= CFG_SYS_SDRAM_BASE; mem_map_fill(); diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c index 953e9db9c8..3d20cfb2fa 100644 --- a/board/Marvell/octeontx2_cn913x/board.c +++ b/board/Marvell/octeontx2_cn913x/board.c @@ -34,7 +34,7 @@ int board_early_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 4959a7fd6d..ad02cf16da 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -137,7 +137,7 @@ int misc_init_r (void) int dram_init (void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -160,12 +160,12 @@ extern void dram_query(void); * */ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE + REMAPPED_FLASH_SZ, 0x01000000 << sdram_shift); } #else - gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE + REMAPPED_FLASH_SZ, PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ diff --git a/board/armltd/vexpress/vexpress_common.c b/board/armltd/vexpress/vexpress_common.c index 1c83019265..763131c217 100644 --- a/board/armltd/vexpress/vexpress_common.c +++ b/board/armltd/vexpress/vexpress_common.c @@ -73,7 +73,7 @@ static void flash__init(void) int dram_init(void) { gd->ram_size = - get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); + get_ram_size((long *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c index 3e2f79a1cf..43563c4127 100644 --- a/board/astro/mcf5373l/mcf5373l.c +++ b/board/astro/mcf5373l/mcf5373l.c @@ -39,12 +39,12 @@ int dram_init(void) * GPIO configuration for bus should be set correctly from reset, * so we do not care! First, set up address space: at this point, * we should be running from internal SRAM; - * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, + * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, * and do not care where it is */ - __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, + __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, &sdp->cs0); - __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, + __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, &sdp->cs1); /* * I am not sure from the data sheet, but it seems burst length @@ -72,7 +72,7 @@ int dram_init(void) */ __raw_writel(0x71462C00, &sdp->ctrl); /* Dummy write to start SDRAM */ - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); #endif /* @@ -82,8 +82,8 @@ int dram_init(void) * (Do not rely on the SDCS register(s) being set to 0x00000000 * during reset as stated in the data sheet.) */ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - 0x80000000 - CONFIG_SYS_SDRAM_BASE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + 0x80000000 - CFG_SYS_SDRAM_BASE); return 0; } diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index d2c6ada668..b8e02f4590 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -81,7 +81,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9260ek_nand_hw_init(); @@ -92,8 +92,8 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 2992353199..eab3a13081 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -156,7 +156,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9261ek_nand_hw_init(); @@ -176,8 +176,8 @@ int board_eth_init(struct bd_info *bis) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index b2b7093080..15f20b62f6 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -95,7 +95,7 @@ int board_init(void) /* arch number of AT91SAM9263EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9263ek_nand_hw_init(); @@ -108,8 +108,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 2f3a772b81..f53c1cf612 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -168,7 +168,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); @@ -181,8 +181,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 546851953a..a3e294c88f 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -99,7 +99,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL at91sam9n12ek_nand_hw_init(); @@ -114,8 +114,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index bca7c8d9af..11725f778b 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -93,7 +93,7 @@ int board_init(void) /* arch number of AT91SAM9RLEK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9rlek_nand_hw_init(); @@ -104,7 +104,7 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 817aa2fef7..ab666b6be3 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -115,7 +115,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND at91sam9x5ek_nand_hw_init(); @@ -129,8 +129,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *) CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 786de18f8c..a3e35f3066 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -120,7 +120,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND sam9x60ek_nand_hw_init(); @@ -130,7 +130,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 6524867708..6e41017af1 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; rgb_leds_init(); @@ -84,8 +84,8 @@ int misc_init_r(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 0207770028..fabe492715 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -54,7 +54,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; rgb_leds_init(); @@ -63,8 +63,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 16e9183f54..854715ea22 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -115,7 +115,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; rgb_leds_init(); @@ -130,8 +130,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index a778f2694d..ce73a801e5 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -94,7 +94,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d3_xplained_nand_hw_init(); @@ -110,8 +110,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 008f1db6b0..660a6b9d58 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -147,7 +147,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d3xek_nand_hw_init(); @@ -166,8 +166,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 4058594e4d..780aba15ab 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -121,7 +121,7 @@ int misc_init_r(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d4_xplained_nand_hw_init(); @@ -135,8 +135,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index ef5a8a0d5c..2226906a3b 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -107,7 +107,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_NAND_ATMEL sama5d4ek_nand_hw_init(); @@ -121,8 +121,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c index 7d83e76f9a..295fd079dc 100644 --- a/board/atmel/sama7g5ek/sama7g5ek.c +++ b/board/atmel/sama7g5ek/sama7g5ek.c @@ -67,7 +67,7 @@ int misc_init_r(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; board_leds_init(); @@ -76,7 +76,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c index 35c74ba9dd..9b42299b08 100644 --- a/board/bluewater/gurnard/gurnard.c +++ b/board/bluewater/gurnard/gurnard.c @@ -307,7 +307,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND ret = gurnard_nand_hw_init(); @@ -407,8 +407,8 @@ int board_eth_init(struct bd_info *bis) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index bdf8d06add..c31e2c86a2 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -182,7 +182,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_MTD_RAW_NAND gpmc_init(); diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c index a7a9775fdf..e3a9c00e80 100644 --- a/board/bosch/shc/board.c +++ b/board/bosch/shc/board.c @@ -449,7 +449,7 @@ int board_init(void) if (read_eeprom() < 0) puts("EEPROM Content Invalid.\n"); - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/broadcom/bcm_ep/board.c b/board/broadcom/bcm_ep/board.c index 6064eb43db..e91fa40e64 100644 --- a/board/broadcom/bcm_ep/board.c +++ b/board/broadcom/bcm_ep/board.c @@ -26,7 +26,7 @@ int board_init(void) * Address of boot parameters passed to kernel * Use default offset 0x100 */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -36,14 +36,14 @@ int board_init(void) */ int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c index c89ad0bfe3..3d31776d48 100644 --- a/board/calao/usb_a9263/usb_a9263.c +++ b/board/calao/usb_a9263/usb_a9263.c @@ -95,7 +95,7 @@ static void usb_a9263_macb_hw_init(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND usb_a9263_nand_hw_init(); @@ -111,8 +111,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index 3e2418866c..69a9df9423 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -28,7 +28,7 @@ int dram_init(void) /* Dummy write to start SDRAM */ *((volatile unsigned long *) 0) = 0; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index bcfe1bfaf6..5df378a62e 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -45,7 +45,7 @@ int power_init_board(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); set_i2c_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index e67bf81ee3..a6223a477f 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -119,7 +119,7 @@ void sdram_init(void) unsigned long ram_size; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x80000000 || ram_size == 0x40000000 || ram_size == 0x20000000) @@ -127,7 +127,7 @@ void sdram_init(void) ddr3_emif_regs.sdram_config = 0x638453B2; config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + ram_size = get_ram_size((long int *)CFG_SYS_SDRAM_BASE, 0x80000000); if (ram_size == 0x08000000) return; diff --git a/board/cssi/MCR3000/MCR3000.c b/board/cssi/MCR3000/MCR3000.c index c20e871494..e95e04a30a 100644 --- a/board/cssi/MCR3000/MCR3000.c +++ b/board/cssi/MCR3000/MCR3000.c @@ -114,7 +114,7 @@ int dram_init(void) out_be32(&memctl->memc_mcr, 0x80002038); udelay(200); - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); return 0; diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c index 72cf46c749..2b03e4891d 100644 --- a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c +++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c @@ -29,13 +29,13 @@ board_early_init_f(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000; return 0; } int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M); return 0; } diff --git a/board/eets/pdu001/board.c b/board/eets/pdu001/board.c index 1054837d43..648d77fd21 100644 --- a/board/eets/pdu001/board.c +++ b/board/eets/pdu001/board.c @@ -286,7 +286,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index a5d79d8e3e..913c2ea166 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -85,8 +85,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } @@ -135,7 +135,7 @@ int board_init(void) at91_periph_clk_enable(ATMEL_ID_PIOC); /* Set adress of boot parameters. */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Initialize UARTs and power management. */ ethernut5_power_init(); #ifdef CONFIG_CMD_NAND diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 16237e29e4..3df3e41c0b 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -126,7 +126,7 @@ void *board_fdt_blob_setup(int *err) { *err = 0; /* QEMU loads a generated DTB for us at the start of RAM. */ - return (void *)CONFIG_SYS_SDRAM_BASE; + return (void *)CFG_SYS_SDRAM_BASE; } void enable_caches(void) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 98043b020c..2304e9e8ec 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -264,7 +264,7 @@ int board_init(void) meesc_ethercat_hw_init(); /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index f5bed6c35b..46ffd817b4 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -61,7 +61,7 @@ static void dp_ddr_restore(void) /* get the address of ddr date from SPARECR3 */ src = (u64 *)in_le32(&scfg->sparecr[2]); - dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + dst = (u64 *)CFG_SYS_SDRAM_BASE; for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst++ = *src++; diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index 71922aab4e..d3323b9ec1 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -50,7 +50,7 @@ static void dp_ddr_restore(void) /* get the address of ddr date from SPARECR3 */ src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); - dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); + dst = (u64 *)(CFG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8); for (i = 0; i < DDR_BUFF_LEN / 8; i++) *dst-- = *src--; diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index bc37c553a5..f2b8750a3f 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -102,7 +102,7 @@ int dram_init(void) else gd->ram_size = SYS_SDRAM_SIZE_512; #else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #endif } return 0; @@ -139,7 +139,7 @@ int dram_init(void) gd->ram_size = SYS_SDRAM_SIZE_512; } #else - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #endif mmdc_init(&mparam); diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 3f70fbc356..f17a6c186d 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -66,7 +66,7 @@ int dram_init(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -90,7 +90,7 @@ int dram_init(void) }; mmdc_init(&mparam); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 456609d993..62c935e4d3 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -113,7 +113,7 @@ int dram_init(void) { gd->ram_size = tfa_get_dram_size(); if (!gd->ram_size) - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -140,7 +140,7 @@ int dram_init(void) mmdc_init(&mparam); #endif - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 66fe1519cc..4e70acc5a0 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -192,7 +192,7 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index 4325439be9..d144f25c62 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -47,7 +47,7 @@ static void ddrmc_init(void) if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, (1 << 31)); /* DRAM VRef will not be trained */ diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 33027ad057..8b74d45823 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -162,7 +162,7 @@ void ddrmc_init(void) if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, (1 << 31)); /* DRAM VRef will not be trained */ diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c index 7bfb4557dd..6125c9e13a 100644 --- a/board/freescale/m5208evbe/m5208evbe.c +++ b/board/freescale/m5208evbe/m5208evbe.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,35 +37,35 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); -#ifdef CONFIG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); #endif - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); asm("nop"); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); asm("nop"); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00); asm("nop"); udelay(100); diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index e7c7a94036..44161a0b0a 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -44,7 +44,7 @@ int dram_init(void) GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3)); - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -61,7 +61,7 @@ int dram_init(void) /* Initialize DACR0 */ out_be32(&sdram->dacr0, - SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | + SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32); asm("nop"); @@ -80,7 +80,7 @@ int dram_init(void) } /* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696; /* Set RE (bit 15) in DACR */ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE); @@ -95,7 +95,7 @@ int dram_init(void) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } gd->ram_size = dramsize; diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index 48c0079111..efff055140 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -86,7 +86,7 @@ int dram_init(void) mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 85f5f0c034..179a2a242a 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -47,7 +47,7 @@ int dram_init(void) __asm__("nop"); /* Initialize DMR0 */ - dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); + dramsize = (CFG_SYS_SDRAM_SIZE << 20); temp = (dramsize - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, temp | 1); __asm__("nop"); @@ -57,7 +57,7 @@ int dram_init(void) __asm__("nop"); /* Write to this block to initiate precharge */ - *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xa5a5a5a5; mb(); __asm__("nop"); @@ -74,7 +74,7 @@ int dram_init(void) mbar_readLong(MCFSIM_DACR0) | 0x0040); __asm__("nop"); - *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + *(u32 *) (CFG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; mb(); } diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index 9580cf2a03..3c20a23385 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -30,7 +30,7 @@ int dram_init(void) /* Dummy write to start SDRAM */ *((volatile unsigned long *)0) = 0; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index 1c4fb7232a..00fa35ca5f 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -35,7 +35,7 @@ int dram_init(void) out_be16(&gpio_reg->par_sdram, 0x3FF); /* Set up chip select */ - out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE); + out_be32(&sdp->sdbar0, CFG_SYS_SDRAM_BASE); out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V); /* Set up timing */ @@ -49,34 +49,34 @@ int dram_init(void) setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); /* Dummy write to start SDRAM */ - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LEMR */ setbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | MCF_SDRAMC_SDMR_CMD); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LMR */ out_be32(&sdp->sdmr, 0x058d0000); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); /* Set precharge */ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop manual precharge, send 2 IREF */ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL); setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; out_be32(&sdp->sdmr, 0x018d0000); - *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CFG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD); @@ -91,7 +91,7 @@ int dram_init(void) | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) | MCF_SDRAMC_SDCR_DQS_OE(0x3)); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; return 0; }; diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index e1ea9b3a58..53e0f20210 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -21,7 +21,7 @@ int dram_init(void) { u32 dramsize, i, dramclk; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -40,7 +40,7 @@ int dram_init(void) /* Initialize DACR0 */ MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE) + | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE) | MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32); @@ -62,7 +62,7 @@ int dram_init(void) } /* Write to this block to initiate precharge */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; + *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696; asm("nop"); /* Set RE (bit 15) in DACR */ @@ -79,7 +79,7 @@ int dram_init(void) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } gd->ram_size = dramsize; diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 8a7d8cadf0..0de36a7f74 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -106,7 +106,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CFG_SYS_SDRAM_BASE -- defines the DRAM Base 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c index c9f89353ce..76ebc0ab8d 100644 --- a/board/freescale/m53017evb/m53017evb.c +++ b/board/freescale/m53017evb/m53017evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,35 +37,35 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); -#ifdef CONFIG_SYS_SDRAM_BASE1 - out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); +#ifdef CFG_SYS_SDRAM_BASE1 + out_be32(&sdram->cs1, CFG_SYS_SDRAM_BASE | i); #endif - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); asm("nop"); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); asm("nop"); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); asm("nop"); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); asm("nop"); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); asm("nop"); udelay(100); diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index 7a75b04dd0..b278dbfb48 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,30 +37,30 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index bba5420215..bfbcd5dc81 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -105,7 +105,7 @@ CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register -CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base +CFG_SYS_SDRAM_BASE -- defines the DRAM Base 2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL =========================================== diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index cfa5ca4a47..0e9eec316c 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -29,7 +29,7 @@ int dram_init(void) sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -37,30 +37,30 @@ int dram_init(void) } i--; - out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); - out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); - out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); + out_be32(&sdram->cs0, CFG_SYS_SDRAM_BASE | i); + out_be32(&sdram->cfg1, CFG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CFG_SYS_SDRAM_CFG2); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Issue LEMR */ - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CFG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CFG_SYS_SDRAM_CTRL | 4); - out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); + out_be32(&sdram->mode, CFG_SYS_SDRAM_MODE); out_be32(&sdram->ctrl, - (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); + (CFG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); udelay(100); diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 2650d300e3..85d43cccd1 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -97,10 +97,10 @@ int dram_init(void) int fixed_sdram(void) { immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; + u32 msize = CFG_SYS_SDRAM_SIZE; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; @@ -127,7 +127,7 @@ int fixed_sdram(void) im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; udelay(2000); - return CONFIG_SYS_SDRAM_SIZE >> 20; + return CFG_SYS_SDRAM_SIZE >> 20; } #endif /*!CONFIG_SYS_SPD_EEPROM */ diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 46095acedf..86364acf8c 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 038e6736ac..f896fd7ccc 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -244,7 +244,7 @@ phys_size_t fixed_sdram(void) printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, sysinfo.freq_ddrbus)); - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_size = CFG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index 70e4dfcfa4..954197282e 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -507,7 +507,7 @@ int splash_screen_prepare(void) /* u-boot dram initialize */ int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -518,10 +518,10 @@ int dram_init_banksize(void) unsigned int reg_val = readl(SCR_USER_SIG6_READ); /* set global data memory */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x00000100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x00000100; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; /* Number of Row: 14 bits */ if ((reg_val >> 28) == 14) diff --git a/board/gardena/smart-gateway-at91sam/board.c b/board/gardena/smart-gateway-at91sam/board.c index c6eb11e932..d9dfb256b3 100644 --- a/board/gardena/smart-gateway-at91sam/board.c +++ b/board/gardena/smart-gateway-at91sam/board.c @@ -45,15 +45,15 @@ int board_early_init_f(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 47b8804352..4889a6a4f3 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -34,11 +34,11 @@ DECLARE_GLOBAL_DATA_PTR; static long fixed_sdram(void) { immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = CONFIG_SYS_SDRAM_SIZE; + u32 msize = CFG_SYS_SDRAM_SIZE; u32 msize_log2 = __ilog2(msize); out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & 0xfffff000); + CFG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); @@ -66,7 +66,7 @@ static long fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); sync(); - return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); + return get_ram_size(CFG_SYS_SDRAM_BASE, msize); } int dram_init(void) diff --git a/board/grinn/chiliboard/board.c b/board/grinn/chiliboard/board.c index 6423c1efb2..b472ca5b94 100644 --- a/board/grinn/chiliboard/board.c +++ b/board/grinn/chiliboard/board.c @@ -95,7 +95,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); return 0; diff --git a/board/imgtec/boston/ddr.c b/board/imgtec/boston/ddr.c index 5b245cb447..8532225dc0 100644 --- a/board/imgtec/boston/ddr.c +++ b/board/imgtec/boston/ddr.c @@ -27,7 +27,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { DECLARE_GLOBAL_DATA_PTR; - if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) { + if (gd->ram_top < CFG_SYS_SDRAM_BASE) { /* 2GB wrapped around to 0 */ return CKSEG0ADDR(256 << 20); } diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index bed24972f7..aa910bf1ce 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -118,7 +118,7 @@ _msc01: /* setup basic address decode */ PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) li t1, 0x0 - li t2, -CONFIG_SYS_SDRAM_SIZE + li t2, -CFG_SYS_SDRAM_SIZE sw t1, MSC01_BIU_MCBAS1L_OFS(t0) sw t2, MSC01_BIU_MCMSK1L_OFS(t0) sw t1, MSC01_BIU_MCBAS2L_OFS(t0) @@ -168,7 +168,7 @@ _msc01: sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) /* setup PCI_BAR0 memory window */ - li t1, -CONFIG_SYS_SDRAM_SIZE + li t1, -CFG_SYS_SDRAM_SIZE sw t1, MSC01_PCI_BAR0_OFS(t0) /* setup PCI to SysCon/CPU translation */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 9853a0ba82..4a72ab5cec 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -94,7 +94,7 @@ static enum sys_con malta_sys_con(void) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/imgtec/xilfpga/xilfpga.c b/board/imgtec/xilfpga/xilfpga.c index 6a836370e3..7122692721 100644 --- a/board/imgtec/xilfpga/xilfpga.c +++ b/board/imgtec/xilfpga/xilfpga.c @@ -19,7 +19,7 @@ int dram_init(void) { /* MIG IP block is smart and doesn't need SW * to do any init */ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; /* in bytes */ + gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */ return 0; } diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index 7dbb3a9143..f3a0de3967 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -412,7 +412,7 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 1 << 30); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 1 << 30); return 0; } diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 02ae7df04d..5462a3dea2 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -185,7 +185,7 @@ int spl_start_uboot(void) */ int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index c8138dcf30..0252ada93f 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -52,7 +52,7 @@ int set_km_env(void) char envval[16]; char *p; - pnvramaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + pnvramaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM - CONFIG_KM_PNVRAM; sprintf(envval, "0x%x", pnvramaddr); env_set("pnvramaddr", envval); @@ -65,7 +65,7 @@ int set_km_env(void) CONFIG_KM_PNVRAM) / 0x400; env_set_ulong("pram", pram); - varaddr = CONFIG_SYS_SDRAM_BASE + gd->ram_size - + varaddr = CFG_SYS_SDRAM_BASE + gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM; env_set_hex("varaddr", varaddr); sprintf(envval, "0x%x", varaddr); diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 6a7b848161..ddd8f7a13e 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -142,10 +142,10 @@ static int fixed_sdram(void) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE); + msize = get_ram_size(CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); enable_addr_trans(); msize /= (1024 * 1024); - if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) { + if (CFG_SYS_SDRAM_SIZE >> 20 != msize) { for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) @@ -169,7 +169,7 @@ int dram_init(void) return -ENXIO; out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); + CFG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/keymile/pg-wcom-ls102xa/ddr.c b/board/keymile/pg-wcom-ls102xa/ddr.c index 4ec60f1685..556d39d4d4 100644 --- a/board/keymile/pg-wcom-ls102xa/ddr.c +++ b/board/keymile/pg-wcom-ls102xa/ddr.c @@ -84,7 +84,7 @@ int fsl_initdram(void) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 3719bcf731..1a7fa3fc1e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -184,7 +184,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { /* Define only 1MiB range for mem_regions at the middle of the RAM */ /* For 1GiB range mem_regions takes approx. 4min */ - *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1); + *vstart = CFG_SYS_SDRAM_BASE + (gd->ram_size >> 1); *size = 1 << 20; return 0; } diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c index d47c7b5f1e..b3c176dd59 100644 --- a/board/l+g/vinco/vinco.c +++ b/board/l+g/vinco/vinco.c @@ -164,7 +164,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if !CONFIG_IS_ENABLED(DM_SPI) vinco_spi0_hw_init(); @@ -188,8 +188,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c index 0504d6177f..ff233e920a 100644 --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/mediatek/mt7623/mt7623_rfb.c b/board/mediatek/mt7623/mt7623_rfb.c index 755e879085..ec10f77c51 100644 --- a/board/mediatek/mt7623/mt7623_rfb.c +++ b/board/mediatek/mt7623/mt7623_rfb.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/mediatek/mt7629/mt7629_rfb.c b/board/mediatek/mt7629/mt7629_rfb.c index d1bca6d62e..55f7696c51 100644 --- a/board/mediatek/mt7629/mt7629_rfb.c +++ b/board/mediatek/mt7629/mt7629_rfb.c @@ -11,7 +11,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/mediatek/mt8518/mt8518_ap1.c b/board/mediatek/mt8518/mt8518_ap1.c index fce5de6767..2490b15ec7 100644 --- a/board/mediatek/mt8518/mt8518_ap1.c +++ b/board/mediatek/mt8518/mt8518_ap1.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; debug("gd->fdt_blob is %p\n", gd->fdt_blob); return 0; diff --git a/board/mscc/jr2/jr2.c b/board/mscc/jr2/jr2.c index 6abf08bd24..84b95be648 100644 --- a/board/mscc/jr2/jr2.c +++ b/board/mscc/jr2/jr2.c @@ -28,7 +28,7 @@ int board_early_init_r(void) ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c index 76e3f2ebbc..48170b3aa1 100644 --- a/board/mscc/luton/luton.c +++ b/board/mscc/luton/luton.c @@ -29,7 +29,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c index 2a75ec281c..f261346b35 100644 --- a/board/mscc/ocelot/ocelot.c +++ b/board/mscc/ocelot/ocelot.c @@ -77,7 +77,7 @@ int board_early_init_r(void) ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/serval/serval.c b/board/mscc/serval/serval.c index 87e7907657..99d5f5be65 100644 --- a/board/mscc/serval/serval.c +++ b/board/mscc/serval/serval.c @@ -22,7 +22,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/mscc/servalt/servalt.c b/board/mscc/servalt/servalt.c index bd8c7e8b70..49993168c2 100644 --- a/board/mscc/servalt/servalt.c +++ b/board/mscc/servalt/servalt.c @@ -22,7 +22,7 @@ int board_early_init_r(void) writel(0, BASE_CFG + ICPU_SW_MODE); /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; return 0; } diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index d97ebd0151..e84dd251c2 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -166,7 +166,7 @@ void sdram_init(void) 0); /* Detect memory physically present */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); /* Reconfigure memory for actual detected size */ @@ -269,7 +269,7 @@ void set_mux_conf_regs(void) */ int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c index 4fbe1e5835..75d2636bf4 100644 --- a/board/phytium/pomelo/pomelo.c +++ b/board/phytium/pomelo/pomelo.c @@ -24,7 +24,7 @@ int dram_init(void) ddr_init(); gd->mem_clk = 0; - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000); sec_init(); debug("PBF relocate done\n"); diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index 3b60afc59c..85fbaf0b28 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -70,7 +70,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index a36526986c..ea090575fb 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -312,7 +312,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 6197e549c2..2d1435acff 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -78,7 +78,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/grpeach/grpeach.c b/board/renesas/grpeach/grpeach.c index 199ec4a310..f609e4f072 100644 --- a/board/renesas/grpeach/grpeach.c +++ b/board/renesas/grpeach/grpeach.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100); return 0; } diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index 87607df20d..c3ebcd3e39 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -80,7 +80,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 8e24ac013c..1437875cfa 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -89,7 +89,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 1a3a4c11a1..db1fb4b035 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -78,7 +78,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 4558070af8..6ecebfe814 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -71,7 +71,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* Force ethernet PHY out of reset */ gpio_request(ETHERNET_PHY_RESET, "phy_reset"); diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c index 56bdb34329..f069eccde9 100644 --- a/board/renesas/stout/stout.c +++ b/board/renesas/stout/stout.c @@ -88,7 +88,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; cpld_init(); diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index 23b55e3e03..c56582a194 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -126,7 +126,7 @@ int board_init(void) /* arch number of AT91SAM9M10G45EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_CMD_NAND pm9g45_nand_hw_init(); @@ -141,15 +141,15 @@ int board_init(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index 5320c1f2e0..a992dc6842 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -46,7 +46,7 @@ int dram_init(void) u32 addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); } return 0; @@ -64,7 +64,7 @@ int dram_init_banksize(void) u32 addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); gd->bd->bi_dram[i].start = addr; diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 943b498293..16ce5cb892 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -122,7 +122,7 @@ int dram_init(void) unsigned long addr; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); } return 0; @@ -134,7 +134,7 @@ int dram_init_banksize(void) unsigned long addr, size; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); + addr = CFG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); gd->bd->bi_dram[i].start = addr; diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 4c655dfd49..8b953f9b39 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -115,7 +115,7 @@ enum env_location env_get_location(enum env_operation op, int prio) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } @@ -173,7 +173,7 @@ int board_late_init(void) int init_addr_map(void) { if (IS_ENABLED(CONFIG_ADDR_MAP)) - addrmap_set_entry(0, 0, CONFIG_SYS_SDRAM_SIZE, 0); + addrmap_set_entry(0, 0, CFG_SYS_SDRAM_SIZE, 0); return 0; } diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 85025f20ef..2efede62aa 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -85,7 +85,7 @@ int board_init(void) #ifdef CONFIG_MACH_TYPE gd->bd->bi_arch_number = CONFIG_MACH_TYPE; #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FACTORYSET factoryset_read_eeprom(FACTORYSET_EEPROM_ADDR); diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index d87628097d..569b86db00 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -262,7 +262,7 @@ void at91_udp_hw_init(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; /* we have to request the gpios again after relocation */ corvus_request_gpio(); @@ -287,8 +287,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/siemens/iot2050/board.c b/board/siemens/iot2050/board.c index b965ae9fa4..8f4b0eae49 100644 --- a/board/siemens/iot2050/board.c +++ b/board/siemens/iot2050/board.c @@ -146,7 +146,7 @@ int dram_init_banksize(void) dram_init(); /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; /* Bank 1 declares the memory available in the DDR high region */ diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index ce6c877959..3d0f7341a3 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -167,7 +167,7 @@ int board_init(void) #endif /* Adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; smartweb_nand_hw_init(); smartweb_macb_hw_init(); @@ -177,8 +177,8 @@ int board_init(void) int dram_init(void) { gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + (void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 47d3f6aef2..1eee972d49 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -185,8 +185,8 @@ void mem_init(void) sdramc_configure(AT91_SDRAMC_NC_10); /* Do memtest for 128MB */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); /* * If 32MB or 16MB should be supported check also for @@ -306,7 +306,7 @@ struct at91_udc_data board_udc_data = { int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; taurus_request_gpio(); #ifdef CONFIG_CMD_NAND @@ -326,8 +326,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c index a218278cb3..79e492f0a8 100644 --- a/board/sipeed/maix/maix.c +++ b/board/sipeed/maix/maix.c @@ -11,7 +11,7 @@ phys_size_t get_effective_memsize(void) { - return CONFIG_SYS_SDRAM_SIZE; + return CFG_SYS_SDRAM_SIZE; } static int sram_init(void) diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 04527cf79a..ad49999dc2 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -51,11 +51,11 @@ phys_size_t fixed_sdram(void) asm ("sync; isync; msync"); udelay(1000); - if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { + if (get_ram_size(0, CFG_SYS_SDRAM_SIZE<<20) == CFG_SYS_SDRAM_SIZE<<20) { /* * OK, size detected -> all done */ - return CONFIG_SYS_SDRAM_SIZE<<20; + return CFG_SYS_SDRAM_SIZE<<20; } return 0; /* nothing found ! */ diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c index 2299227391..b3f9550742 100644 --- a/board/softing/vining_fpga/socfpga.c +++ b/board/softing/vining_fpga/socfpga.c @@ -30,7 +30,7 @@ int board_late_init(void) status_led_set(2, CONFIG_LED_STATUS_ON); /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); if (!ret) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 8e80ca6e17..7c44379ec4 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -107,7 +107,7 @@ int dram_init(void) { u32 max_size = imx_ddr_size(); - gd->ram_size = get_ram_size_stride_test((u32 *) CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size_stride_test((u32 *) CFG_SYS_SDRAM_BASE, (u32)max_size); return 0; @@ -288,7 +288,7 @@ int board_init(void) int ret = 0; /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_VIDEO_IPUV3 ret = setup_display(); diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index beab4e9d18..5426fc4ffd 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -88,7 +88,7 @@ int dram_init(void) */ out_be32(&dc->dacr0, 0x00003304); - dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; + dramsize = ((CFG_SYS_SDRAM_SIZE)-1) & 0xfffc0000; out_be32(&dc->dmr0, dramsize|1); /* issue a PRECHARGE ALL */ @@ -102,8 +102,8 @@ int dram_init(void) out_be32(&dc->dacr0, 0x0000b344); out_be32((u32 *)0x00000c00, 0xbeaddeed); - gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size(CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c index d48da48b69..475e3edfa6 100644 --- a/board/sysam/stmark2/stmark2.c +++ b/board/sysam/stmark2/stmark2.c @@ -35,7 +35,7 @@ int dram_init(void) * Serial Boot: The dram is already initialized in start.S * only require to return DRAM size */ - dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; gd->ram_size = dramsize; diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index 3a447ca8a9..8d9eedb752 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -144,7 +144,7 @@ static const struct boot_mode board_boot_modes[] = { int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_VIDEO_IPUV3 setup_display(); diff --git a/board/tcl/sl50/board.c b/board/tcl/sl50/board.c index b7ddc3ba78..839a692ce8 100644 --- a/board/tcl/sl50/board.c +++ b/board/tcl/sl50/board.c @@ -238,7 +238,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index b97fedddd5..9e58281611 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -704,7 +704,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 529129ecc7..d0b7a14e0e 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -639,7 +639,7 @@ int board_init(void) u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, modena_init0_bw_integer, modena_init0_watermark_0; - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; gpmc_init(); /* diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index cfc825e52a..652c40f55c 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -661,7 +661,7 @@ bool am571x_idk_needs_lcd(void) int board_init(void) { gpmc_init(); - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + gd->bd->bi_boot_params = (CFG_SYS_SDRAM_BASE + 0x100); return 0; } diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 34ec3915f3..b266ccb4b8 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -75,13 +75,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index a854d615c1..1c00e253ff 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -644,7 +644,7 @@ int dram_init_banksize(void) ram_size = board_ti_get_emif_size(); - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); if (ram_size > CONFIG_MAX_MEM_MAPPED) { gd->bd->bi_dram[1].start = 0x200000000; diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index d6e431ead0..d4e672a7ac 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -71,13 +71,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x80000000; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x80000000; gd->ram_size = 0x100000000; #endif diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index e09adc8ad3..4d28582311 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -60,13 +60,13 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) int dram_init_banksize(void) { /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x7fffffff; gd->ram_size = 0x80000000; #ifdef CONFIG_PHYS_64BIT /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1; gd->bd->bi_dram[1].size = 0x37fffffff; gd->ram_size = 0x400000000; #endif diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 51e8de4b89..34818736a4 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -46,7 +46,7 @@ int dram_init(void) ddr3_size = ddr3_init(); - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) if (!(board_is_k2g_ice() || board_is_k2g_i1())) @@ -71,7 +71,7 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } @@ -120,7 +120,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* adjust memory start address for LPAE */ if (lpae) { - start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] -= CFG_SYS_SDRAM_BASE; start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; } @@ -174,11 +174,11 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) "linux,initrd-end", NULL); if (prop1 && prop2) { initrd_start = __be64_to_cpu(*prop1); - initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start -= CFG_SYS_SDRAM_BASE; initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); initrd_end = __be64_to_cpu(*prop2); - initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end -= CFG_SYS_SDRAM_BASE; initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end); @@ -221,7 +221,7 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) *reserve_start = __cpu_to_be64(*reserve_start); size = __cpu_to_be64(*(reserve_start + 1)); if (size) { - *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += CONFIG_SYS_LPAE_SDRAM_BASE; *reserve_start = diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index 2d42af6b80..8c708355d4 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c index 9d4ffb0f97..efef855b3d 100644 --- a/board/timll/devkit3250/devkit3250.c +++ b/board/timll/devkit3250/devkit3250.c @@ -56,7 +56,7 @@ int board_early_init_f(void) int board_init(void) { /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_SYS_FLASH_CFI /* Use 16-bit memory interface for NOR Flash */ @@ -76,8 +76,8 @@ int board_init(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 96d0185329..3c7cfa309c 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -79,7 +79,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, (ulong)imx_ddr_size()); return 0; diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 475250d801..65e0e9a156 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -73,7 +73,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { /* use the DDR controllers configured size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, (ulong)imx_ddr_size()); return 0; diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index 07fe454471..f335d5b4f4 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -266,7 +266,7 @@ int board_init(void) hw_watchdog_init(); #endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND) gpmc_init(); #endif diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c index 5d12f84cfe..c8e791a4da 100644 --- a/board/work-microwave/work_92105/work_92105.c +++ b/board/work-microwave/work_92105/work_92105.c @@ -67,15 +67,15 @@ int board_init(void) { reset_periph(); /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 17ee541bd8..df4c457672 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -105,7 +105,7 @@ int board_late_init(void) return board_late_init_xilinx(); } -#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); @@ -123,8 +123,8 @@ int dram_init(void) #else int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); zynq_ddrc_init(); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 579708d2e0..e3f70c4caf 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -236,7 +236,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, return ret; } -#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +#if !defined(CFG_SYS_SDRAM_BASE) && !defined(CFG_SYS_SDRAM_SIZE) int dram_init_banksize(void) { int ret; @@ -261,7 +261,7 @@ int dram_init(void) #else int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); mem_map_fill(); @@ -271,8 +271,8 @@ int dram_init_banksize(void) int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/boot/image-board.c b/boot/image-board.c index 34d1e5f18b..8813be544b 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -116,8 +116,8 @@ ulong env_get_bootm_low(void) return tmp; } -#if defined(CONFIG_SYS_SDRAM_BASE) - return CONFIG_SYS_SDRAM_BASE; +#if defined(CFG_SYS_SDRAM_BASE) + return CFG_SYS_SDRAM_BASE; #elif defined(CONFIG_ARM) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_RISCV) return gd->bd->bi_dram[0].start; #else diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c index aaaedfe973..bbd406fc66 100644 --- a/cmd/ti/ddr3.c +++ b/cmd/ti/ddr3.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_ARCH_KEYSTONE #include -#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE +#define DDR_MIN_ADDR CFG_SYS_SDRAM_BASE #define STACKSIZE (512 << 10) /* 512 KiB */ #define DDR_REMAP_ADDR 0x80000000 @@ -247,9 +247,9 @@ static int is_addr_valid(u32 addr) /* Check in ecc address range 1 */ if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_1_EN_MASK) { start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) - + CONFIG_SYS_SDRAM_BASE; + + CFG_SYS_SDRAM_BASE; end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + - CONFIG_SYS_SDRAM_BASE; + CFG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 1 */ return 1; @@ -259,9 +259,9 @@ static int is_addr_valid(u32 addr) if (ecc_ctrl & EMIF_ECC_REG_ECC_ADDR_RGN_2_EN_MASK) { range = readl(&emif->emif_ecc_address_range_2); start_addr = ((range & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16) - + CONFIG_SYS_SDRAM_BASE; + + CFG_SYS_SDRAM_BASE; end_addr = (range & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0xFFFF + - CONFIG_SYS_SDRAM_BASE; + CFG_SYS_SDRAM_BASE; if ((addr >= start_addr) && (addr <= end_addr)) /* addr within ecc address range 2 */ return 1; @@ -309,11 +309,11 @@ static int do_ddr_test(struct cmd_tbl *cmdtp, start_addr = hextoul(argv[2], NULL); end_addr = hextoul(argv[3], NULL); - if ((start_addr < CONFIG_SYS_SDRAM_BASE) || - (start_addr > (CONFIG_SYS_SDRAM_BASE + + if ((start_addr < CFG_SYS_SDRAM_BASE) || + (start_addr > (CFG_SYS_SDRAM_BASE + get_effective_memsize() - 1)) || - (end_addr < CONFIG_SYS_SDRAM_BASE) || - (end_addr > (CONFIG_SYS_SDRAM_BASE + + (end_addr < CFG_SYS_SDRAM_BASE) || + (end_addr > (CFG_SYS_SDRAM_BASE + get_effective_memsize() - 1)) || (start_addr >= end_addr)) { puts("Invalid start or end address!\n"); return cmd_usage(cmdtp); diff --git a/common/board_f.c b/common/board_f.c index e6117a7ba5..aab1130763 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -329,12 +329,12 @@ __weak int mach_cpu_init(void) /* Get the top of usable RAM */ __weak phys_size_t board_get_usable_ram_top(phys_size_t total_size) { -#if defined(CONFIG_SYS_SDRAM_BASE) && CONFIG_SYS_SDRAM_BASE > 0 +#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0 /* * Detect whether we have so much RAM that it goes past the end of our * 32-bit address space. If so, clip the usable RAM so it doesn't. */ - if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) + if (gd->ram_top < CFG_SYS_SDRAM_BASE) /* * Will wrap back to top of 32-bit space when reservations * are made. @@ -369,8 +369,8 @@ static int setup_dest_addr(void) */ gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; #endif -#ifdef CONFIG_SYS_SDRAM_BASE - gd->ram_base = CONFIG_SYS_SDRAM_BASE; +#ifdef CFG_SYS_SDRAM_BASE + gd->ram_base = CFG_SYS_SDRAM_BASE; #endif gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->mon_len); diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 15806dfaee..584503eb12 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -142,21 +142,21 @@ CONFIG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config -CONFIG_SYS_SDRAM_BASE: +CFG_SYS_SDRAM_BASE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_SIZE: +CFG_SYS_SDRAM_SIZE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_BASEX: +CFG_SYS_SDRAM_BASEX: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG1: +CFG_SYS_SDRAM_CFG1: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG2: +CFG_SYS_SDRAM_CFG2: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CTRL: +CFG_SYS_SDRAM_CTRL: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_MODE: +CFG_SYS_SDRAM_MODE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_EMOD: +CFG_SYS_SDRAM_EMOD: SDRAM config for SDRAM controller-specific registers, please see arch/m68k/cpu//start.S files to see how these options are used. diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst index 35defb0af0..34a75e7fb0 100644 --- a/doc/arch/nios2.rst +++ b/doc/arch/nios2.rst @@ -96,8 +96,8 @@ to 0xDxxx_xxxx. .. code-block:: c - #define CONFIG_SYS_SDRAM_BASE 0xc8000000 - #define CONFIG_SYS_SDRAM_SIZE 0x08000000 + #define CFG_SYS_SDRAM_BASE 0xc8000000 + #define CFG_SYS_SDRAM_SIZE 0x08000000 You will need to change the environment variables location and setting, too. You may change other configs to fit your board. diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 5e8fb7a89c..9dada5e117 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -130,7 +130,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); /* DRAM VRef will not be trained */ diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 3c1f7a1891..f8d1468a26 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -230,7 +230,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); /* DRAM VRef will not be trained */ diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index fcff223b4f..4975dbb821 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -30,7 +30,7 @@ */ #ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 0f2dc243cb..1c4a1cae4d 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -162,7 +162,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, if (is_warm_boot()) { out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_addr, CFG_SYS_SDRAM_BASE); out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); /* DRAM VRef will not be trained */ diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index a14c766dda..c40cd768ab 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -19,10 +19,10 @@ #define FAR_END_DIMM_ADDR 0x50 #define MAX_DIMM_ADDR 0x60 -#ifndef CONFIG_SYS_SDRAM_SIZE +#ifndef CFG_SYS_SDRAM_SIZE #define SDRAM_CS_SIZE 0xFFFFFFF #else -#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) +#define SDRAM_CS_SIZE ((CFG_SYS_SDRAM_SIZE >> 10) - 1) #endif #define SDRAM_CS_BASE 0x0 #define SDRAM_DIMM_SIZE 0x80000000 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 22f4995453..a3b662fb13 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -60,7 +60,7 @@ config PCI_MAP_SYSTEM_MEMORY instead of a physical address (e.g. on MIPS). The PCI core will then remap the virtual memory base address to a physical address when adding the PCI region of type PCI_REGION_SYS_MEMORY. - This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is still + This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still being used as virtual address. config PCI_SRIOV diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index dc11402781..b81eb35368 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -191,7 +191,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* AHB-PCI Bridge Communication Registers */ writel(RCAR_AHB_BUS_MODE, priv->cfg_base + RCAR_AHB_BUS_CTR_REG); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN1_CTR_REG); writel(0xf0000000 | RCAR_PCIAHB_PREFETCH16, priv->cfg_base + RCAR_PCIAHB_WIN2_CTR_REG); @@ -204,7 +204,7 @@ static int rcar_gen2_pci_probe(struct udevice *dev) /* PCI Configuration Registers for AHBPCI */ devad = setup_bus_address(dev, PCI_BDF(0, 0, 0), 0); writel(priv->cfg_base + 0x800, devad + PCI_BASE_ADDRESS_0); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, devad + PCI_BASE_ADDRESS_1); writel(0xf0000000, devad + PCI_BASE_ADDRESS_2); writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR, diff --git a/drivers/pci/pci_sh7751.c b/drivers/pci/pci_sh7751.c index d514c04034..c1be56ce7a 100644 --- a/drivers/pci/pci_sh7751.c +++ b/drivers/pci/pci_sh7751.c @@ -158,9 +158,9 @@ static int sh7751_pci_probe(struct udevice *dev) /* Set up target memory mappings (for external DMA access) */ /* Map both P0 and P2 range to Area 3 RAM for ease of use */ - p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); - p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); + p4_out(CFG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0); + p4_out(CFG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0); + p4_out(CFG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5); p4_out(0, SH7751_PCILSR1); p4_out(0, SH7751_PCILAR1); diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 99891dce61..a0b82c7832 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -459,9 +459,9 @@ static void pcie_dw_set_host_bars(const void *regs_base) } /* Set the BAR base and size towards DDR */ - bar0 = CONFIG_SYS_SDRAM_BASE & ~0xf; + bar0 = CFG_SYS_SDRAM_BASE & ~0xf; bar0 |= PCI_BASE_ADDRESS_MEM_TYPE_32; - writel(CONFIG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); + writel(CFG_SYS_SDRAM_BASE, regs_base + PCIE_CONFIG_BAR0); reg = ((size >> 20) - 1) << 12; writel(size, regs_base + RESIZABLE_BAR_CTL0); diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index a52774179e..b7f692f645 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -14,11 +14,11 @@ #include #ifndef CFG_SYS_PCI_MEMORY_BUS -#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_BUS CFG_SYS_SDRAM_BASE #endif #ifndef CFG_SYS_PCI_MEMORY_PHYS -#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_PCI_MEMORY_PHYS CFG_SYS_SDRAM_BASE #endif #ifndef CFG_SYS_PCI_MEMORY_SIZE diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c index 141b19b57a..dc466a88e7 100644 --- a/drivers/ram/aspeed/sdram_ast2500.c +++ b/drivers/ram/aspeed/sdram_ast2500.c @@ -203,7 +203,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info) u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_1024M; u32 refresh_timing_param = DDR4_TRFC; - const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset; for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { @@ -231,7 +231,7 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info) ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT)); - info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info); clrsetbits_le32(&info->regs->config, (SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT), diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c index 5d426088be..a2d7ca82fc 100644 --- a/drivers/ram/aspeed/sdram_ast2600.c +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -838,7 +838,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info) u32 test_pattern = 0xdeadbeef; u32 cap_param = SDRAM_CONF_CAP_2048M; u32 refresh_timing_param = DDR4_TRFC; - const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + const u32 write_addr_base = CFG_SYS_SDRAM_BASE + write_test_offset; for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; ram_size >>= 1) { @@ -866,7 +866,7 @@ static void ast2600_sdrammc_calc_size(struct dram_info *info) ((refresh_timing_param & SDRAM_AC_TRFC_MASK) << SDRAM_AC_TRFC_SHIFT)); - info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK, @@ -1015,7 +1015,7 @@ static void ast2600_sdrammc_update_size(struct dram_info *info) break; } - info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.base = CFG_SYS_SDRAM_BASE; info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); if (0 == (conf & SDRAM_CONF_ECC_SETUP)) diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c index d12a3b4f43..1737fdac97 100644 --- a/drivers/ram/mediatek/ddr3-mt7629.c +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -243,17 +243,17 @@ static int mtk_ddr3_rank_size_detect(struct udevice *dev) * and it has maximum addressing region */ - writel(WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE); + writel(WALKING_PATTERN, CFG_SYS_SDRAM_BASE); - if (readl(CONFIG_SYS_SDRAM_BASE) != WALKING_PATTERN) + if (readl(CFG_SYS_SDRAM_BASE) != WALKING_PATTERN) return -EINVAL; for (step = 0; step < 5; step++) { - writel(~WALKING_PATTERN, CONFIG_SYS_SDRAM_BASE + + writel(~WALKING_PATTERN, CFG_SYS_SDRAM_BASE + (WALKING_STEP << step)); - start = readl(CONFIG_SYS_SDRAM_BASE); - test = readl(CONFIG_SYS_SDRAM_BASE + (WALKING_STEP << step)); + start = readl(CFG_SYS_SDRAM_BASE); + test = readl(CFG_SYS_SDRAM_BASE + (WALKING_STEP << step)); if ((test != ~WALKING_PATTERN) || test == start) break; } @@ -727,7 +727,7 @@ static int mtk_ddr3_get_info(struct udevice *dev, struct ram_info *info) struct mtk_ddr3_priv *priv = dev_get_priv(dev); u32 val = readl(priv->emi + EMI_CONA); - info->base = CONFIG_SYS_SDRAM_BASE; + info->base = CFG_SYS_SDRAM_BASE; switch ((val & EMI_COL_ADDR_MASK) >> EMI_COL_ADDR_SHIFT) { case 0: diff --git a/drivers/ram/octeon/octeon_ddr.c b/drivers/ram/octeon/octeon_ddr.c index 42daf06866..bb21078df1 100644 --- a/drivers/ram/octeon/octeon_ddr.c +++ b/drivers/ram/octeon/octeon_ddr.c @@ -2687,7 +2687,7 @@ static int octeon_ddr_probe(struct udevice *dev) if (!mem_mbytes) return -ENODEV; - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = MB(mem_mbytes); /* diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 69c454a4ba..6929a7e494 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -617,12 +617,12 @@ static int sdram_col_row_detect(struct udevice *dev) /* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + params->chan.bw - 1)); writel(test_pattern, addr); if ((readl(addr) == test_pattern) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } @@ -637,11 +637,11 @@ static int sdram_col_row_detect(struct udevice *dev) /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(test_pattern, addr); if ((readl(addr) == test_pattern) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } diff --git a/drivers/ram/rockchip/sdram_common.c b/drivers/ram/rockchip/sdram_common.c index b3e7421d08..ec46ba5457 100644 --- a/drivers/ram/rockchip/sdram_common.c +++ b/drivers/ram/rockchip/sdram_common.c @@ -220,12 +220,12 @@ int sdram_detect_col(struct sdram_cap_info *cap_info, u32 bw = cap_info->bw; for (col = coltmp; col >= 9; col -= 1) { - writel(0, CONFIG_SYS_SDRAM_BASE); - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (col + bw - 1ul))); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -245,12 +245,12 @@ int sdram_detect_bank(struct sdram_cap_info *cap_info, u32 bk; u32 bw = cap_info->bw; - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (coltmp + bktmp + bw - 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) bk = 3; else bk = 2; @@ -268,12 +268,12 @@ int sdram_detect_bg(struct sdram_cap_info *cap_info, u32 dbw; u32 bw = cap_info->bw; - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (coltmp + bw + 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE); + writel(0, CFG_SYS_SDRAM_BASE); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) dbw = 0; else dbw = 1; @@ -337,12 +337,12 @@ int sdram_detect_row(struct sdram_cap_info *cap_info, void __iomem *test_addr; for (row = rowtmp; row > 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + (1ul << (row + bktmp + coltmp + bw - 1ul))); writel(PATTERN, test_addr); if ((readl(test_addr) == PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -363,8 +363,8 @@ int sdram_detect_row_3_4(struct sdram_cap_info *cap_info, u32 row = cap_info->cs0_row; void __iomem *test_addr, *test_addr1; - test_addr = CONFIG_SYS_SDRAM_BASE; - test_addr1 = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = CFG_SYS_SDRAM_BASE; + test_addr1 = (void __iomem *)(CFG_SYS_SDRAM_BASE + (0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul))); writel(0, test_addr); @@ -421,15 +421,15 @@ int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type) /* detect cs1 row */ for (row = cap_info->cs0_row; row > 12; row--) { - test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + + test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE + cs0_cap + (1ul << (row + bktmp + coltmp + bw - 1ul))); - writel(0, CONFIG_SYS_SDRAM_BASE + cs0_cap); + writel(0, CFG_SYS_SDRAM_BASE + cs0_cap); writel(PATTERN, test_addr); if (((readl(test_addr) & byte_mask) == (PATTERN & byte_mask)) && - ((readl(CONFIG_SYS_SDRAM_BASE + cs0_cap) & + ((readl(CFG_SYS_SDRAM_BASE + cs0_cap) & byte_mask) == 0)) { break; } diff --git a/drivers/ram/rockchip/sdram_px30.c b/drivers/ram/rockchip/sdram_px30.c index c024a0cd63..98b2593ac4 100644 --- a/drivers/ram/rockchip/sdram_px30.c +++ b/drivers/ram/rockchip/sdram_px30.c @@ -726,7 +726,7 @@ static int px30_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: grf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]); diff --git a/drivers/ram/rockchip/sdram_rk3066.c b/drivers/ram/rockchip/sdram_rk3066.c index 832154ee3a..a2425f22e2 100644 --- a/drivers/ram/rockchip/sdram_rk3066.c +++ b/drivers/ram/rockchip/sdram_rk3066.c @@ -616,12 +616,12 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in /* Detect col. */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTERN, addr); if ((readl(addr) == TEST_PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -638,11 +638,11 @@ static int rk3066_dmc_sdram_col_row_detect(struct rk3066_dmc_dram_info *dram, in rk3066_dmc_move_to_access_state(chan); /* Detect row, max 15, min13 for rk3066 */ for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTERN, addr); if ((readl(addr) == TEST_PATTERN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -854,7 +854,7 @@ static int rk3066_dmc_probe(struct udevice *dev) if (ret) return ret; } else { - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmu->sys_reg[2]); } diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index 16cfbf947b..ded6539380 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -23,7 +23,7 @@ static int rk3128_dmc_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[1]); diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index be8ba4464d..272b1b2dce 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -638,12 +638,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, /* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -660,11 +660,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, move_to_access_state(chan); /* Detect row, max 15,min13 in rk3188*/ for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 12) { @@ -919,7 +919,7 @@ static int rk3188_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->pmu->sys_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index cd4234f389..1b204fb56e 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -636,12 +636,12 @@ static int dram_cap_detect(struct dram_info *dram, writel(3, &axi_bus->ddrconf); move_to_access_state(dram->chan[0].pctl); for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -656,11 +656,11 @@ static int dram_cap_detect(struct dram_info *dram, /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 11) { @@ -672,11 +672,11 @@ static int dram_cap_detect(struct dram_info *dram, sdram_params->ch[0].cs0_row = row; } /* cs detect */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30)); - writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4); - if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + writel(0, CFG_SYS_SDRAM_BASE); + writel(TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30)); + writel(~TEST_PATTEN, CFG_SYS_SDRAM_BASE + (1u << 30) + 4); + if ((readl(CFG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) && + (readl(CFG_SYS_SDRAM_BASE) == 0)) sdram_params->ch[0].rank = 2; else sdram_params->ch[0].rank = 1; @@ -813,7 +813,7 @@ static int rk322x_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 227a3cc6a8..83778ad1c2 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -684,12 +684,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, /* Detect col */ for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (col + sdram_params->ch[channel].bw - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (col == 8) { @@ -705,11 +705,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel, move_to_access_state(chan); /* Detect row*/ for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(0, CFG_SYS_SDRAM_BASE); + addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); writel(TEST_PATTEN, addr); if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + (readl(CFG_SYS_SDRAM_BASE) == 0)) break; } if (row == 11) { @@ -1087,7 +1087,7 @@ static int rk3288_dmc_probe(struct udevice *dev) if (ret) return ret; #else - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->pmu->sys_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3308.c b/drivers/ram/rockchip/sdram_rk3308.c index 44d7d8a0d9..10828e8082 100644 --- a/drivers/ram/rockchip/sdram_rk3308.c +++ b/drivers/ram/rockchip/sdram_rk3308.c @@ -21,7 +21,7 @@ static int rk3308_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->grf->os_reg2); return 0; diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 9c6798f816..b511c6bf6f 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -580,7 +580,7 @@ static int rk3328_dmc_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size( (phys_addr_t)&priv->grf->os_reg[2]); #endif diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index cbf502bd0e..136e4ede71 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3151,7 +3151,7 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf = %p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2); #endif diff --git a/drivers/ram/rockchip/sdram_rk3568.c b/drivers/ram/rockchip/sdram_rk3568.c index 0ac4b54eef..f661615c1b 100644 --- a/drivers/ram/rockchip/sdram_rk3568.c +++ b/drivers/ram/rockchip/sdram_rk3568.c @@ -21,7 +21,7 @@ static int rk3568_dmc_probe(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.base = CFG_SYS_SDRAM_BASE; priv->info.size = rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2); diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c index 130b73dfe4..60525f2286 100644 --- a/drivers/usb/host/ehci-rmobile.c +++ b/drivers/usb/host/ehci-rmobile.c @@ -90,7 +90,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, /* AHB-PCI Bridge Communication Registers */ writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); - writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, + writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, &ahbcom_pci->pciahb_win1_ctr); writel(0xf0000000 | PCIAHB_WIN_PREFETCH, &ahbcom_pci->pciahb_win2_ctr); @@ -103,7 +103,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, &ahbcom_pci->ahbpci_win1_ctr); writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); - writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); + writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); writel(0xf0000000, &ahbconf_pci->win2_basead); writel(SERREN | PERREN | MASTEREN | MEMEN, &ahbconf_pci->cmnd_sts); diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 2ee6212c58..9110a48482 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -385,7 +385,7 @@ static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode, (struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE; setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS); - writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); + writel(CFG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr); writel(mode->xres * 4, &de_fe->ch0_stride); writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt); writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt); @@ -1222,7 +1222,7 @@ static int sunxi_de_probe(struct udevice *dev) EFI_RESERVED_MEMORY_TYPE); #endif - fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE; + fb_dma_addr = sunxi_display->fb_addr - CFG_SYS_SDRAM_BASE; if (overscan_offset) { fb_dma_addr += 0x1000 - (overscan_offset & 0xfff); sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000); diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 719caf7b0c..3a4fbc6eab 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -30,8 +30,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xc8000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xc8000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index ad7bd13320..ab889180ee 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -26,8 +26,8 @@ * -The heap is placed below the monitor * -The stack is placed below the heap (&grows down). */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0xD0000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 25c3f22bea..6dfa3dd0f0 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -60,22 +60,22 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1002000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI @@ -100,8 +100,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index f200d706a9..e28662c6e5 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -70,10 +70,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* * For booting Linux, the board info and command line data @@ -81,7 +81,7 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -109,8 +109,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 9ff66d751c..f1da278d51 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -52,10 +52,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) #if 0 /* test-only */ @@ -67,7 +67,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -90,8 +90,8 @@ #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index f7bfe598a8..bd3c57d143 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -77,17 +77,17 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) @@ -117,8 +117,8 @@ #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index dcd83650f2..7c3bc032bf 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -71,10 +71,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE 0xffe00000 /* @@ -82,7 +82,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* * FLASH organization @@ -100,8 +100,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 9012794501..4eb4abea72 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -73,10 +73,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE /* @@ -84,7 +84,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -101,8 +101,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 925d26eaf1..eda394467e 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -72,10 +72,10 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 @@ -85,7 +85,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -105,8 +105,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 79a4e6171d..159993a46b 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -74,22 +74,22 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x43711630 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x80010000 +#define CFG_SYS_SDRAM_MODE 0x00CD0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -118,8 +118,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index fc21af56ec..d7ece63934 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -68,22 +68,22 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -117,8 +117,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f7c09a2333..b2fc6923e0 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -70,22 +70,22 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_CFG1 0x53722730 +#define CFG_SYS_SDRAM_CFG2 0x56670000 +#define CFG_SYS_SDRAM_CTRL 0xE1092000 +#define CFG_SYS_SDRAM_EMOD 0x40010000 +#define CFG_SYS_SDRAM_MODE 0x018D0000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization @@ -117,8 +117,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index a5518d3d50..2e7140cd86 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -62,8 +62,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) #define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) -/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* FLASH organization */ #define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 0e70b2853b..d9627e393d 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -59,7 +59,7 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) @@ -69,7 +69,7 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index c59a37646f..6a51149a94 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -40,7 +40,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f87e7597ad..21491b9f97 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -110,9 +110,9 @@ #ifndef __ASSEMBLY__ extern unsigned long get_sdram_size(void); #endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8c7b877bfb..d7e06d23ec 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -69,10 +69,10 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * Local Bus Definitions diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 824190a412..417b9ae7b2 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -7,7 +7,7 @@ #define _CONFIG_SBX81LIFKW_H /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index e67da1fe1d..87b68227a0 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -7,7 +7,7 @@ #define _CONFIG_SBX81LIFXCAT_H /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 154b2f174a..616387f487 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -116,12 +116,12 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ #elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_SDRAM_SIZE 2048 +#define CFG_SYS_SDRAM_SIZE 2048 #endif /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 847cf65b40..37dfe32e21 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -88,11 +88,11 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * IFC Definitions diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b49c264776..8f56de40ce 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -86,8 +86,8 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index aae41a3392..e9db4a224f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -81,8 +81,8 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 9dc45e397f..cc86c9d4a5 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -62,7 +62,7 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* * IFC Definitions @@ -154,7 +154,7 @@ #define SPD_EEPROM_ADDRESS2 0x54 #define SPD_EEPROM_ADDRESS3 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* * IFC Definitions diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 78201adc07..57f3f37908 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -13,7 +13,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 140940730d..25c71f00a2 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -16,7 +16,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 0345160787..0307426e4a 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -15,7 +15,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 #define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 2bda66fe03..eba78d3894 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -33,8 +33,8 @@ /* size of internal SRAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* amcore design has flash data bytes wired swapped */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 650140bb72..63c7dfc1fe 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 3114cf0c4f..865aad2a3f 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/ap152.h b/include/configs/ap152.h index f0674456fd..0464a69e82 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index e2e491bdb0..cf23837863 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -63,7 +63,7 @@ /* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 30d32d27e3..356d4c35ee 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -106,7 +106,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/arbel.h b/include/configs/arbel.h index f7deba4f56..ed32e772f8 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -6,9 +6,9 @@ #ifndef __CONFIG_ARBEL_H #define __CONFIG_ARBEL_H -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 #define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 35e8840a92..90cf4705f4 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -406,7 +406,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 5c9005805e..cbd0d6cea0 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -14,7 +14,7 @@ /* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE +#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE #ifdef CONFIG_PRE_CON_BUF_SZ #define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 58635df149..b142ea3c33 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_CLK 80000000 #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ /* * Define baudrate for UART1 (console output, tftp, ...) @@ -158,7 +158,7 @@ * (Set up by the startup code) * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* * Chipselect bank definitions @@ -195,8 +195,8 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ @@ -213,8 +213,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 574bfe37e9..0d76f419db 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -31,8 +31,8 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 2c785ad426..dcc1cca479 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -17,8 +17,8 @@ #include /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index bba8574b1c..aefa9fc60c 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -23,8 +23,8 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 @@ -100,22 +100,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 3ce264a4a9..08cfee1a4e 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -15,8 +15,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 5e3ded241f..76f87c1619 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -14,8 +14,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* DataFlash */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b79c8ba5bf..e1111b6dd3 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -17,8 +17,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 40ea4ed49e..eb1d1ad60d 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -20,8 +20,8 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* DataFlash */ diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index e3b6956eb5..83ac87b10a 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -28,7 +28,7 @@ (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0 /* * Serial console configuration diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 1932713f45..6d82712186 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -20,8 +20,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_512M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_512M /* * UART configuration diff --git a/include/configs/bcm947622.h b/include/configs/bcm947622.h index d0c46a2c82..b02ed1bfe0 100644 --- a/include/configs/bcm947622.h +++ b/include/configs/bcm947622.h @@ -6,7 +6,7 @@ #ifndef __BCM947622_H #define __BCM947622_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define COUNTER_FREQUENCY 50000000 #endif diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h index 1346ace4bf..246feb66b2 100644 --- a/include/configs/bcm94908.h +++ b/include/configs/bcm94908.h @@ -6,6 +6,6 @@ #ifndef __BCM94908_H #define __BCM94908_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h index f3d17ddaac..c428b1ab57 100644 --- a/include/configs/bcm94912.h +++ b/include/configs/bcm94912.h @@ -6,6 +6,6 @@ #ifndef __BCM94912_H #define __BCM94912_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index 361569a8c5..f1b68ba673 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -6,7 +6,7 @@ #ifndef __BCM963138_H #define __BCM963138_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_HZ_CLOCK 500000000 #endif diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h index edbdfc3c51..90dfa98311 100644 --- a/include/configs/bcm963146.h +++ b/include/configs/bcm963146.h @@ -6,6 +6,6 @@ #ifndef __BCM963146_H #define __BCM963146_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h index 5a24cccba1..54f6750c74 100644 --- a/include/configs/bcm963148.h +++ b/include/configs/bcm963148.h @@ -6,6 +6,6 @@ #ifndef __BCM963148_H #define __BCM963148_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h index b15c4111c9..2fdd22d1b0 100644 --- a/include/configs/bcm963158.h +++ b/include/configs/bcm963158.h @@ -6,6 +6,6 @@ #ifndef __BCM963158_H #define __BCM963158_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h index b25f6a1281..32fc4a5e39 100644 --- a/include/configs/bcm963178.h +++ b/include/configs/bcm963178.h @@ -6,6 +6,6 @@ #ifndef __BCM963178_H #define __BCM963178_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h index c8f32672b7..c69d177da2 100644 --- a/include/configs/bcm96756.h +++ b/include/configs/bcm96756.h @@ -6,6 +6,6 @@ #ifndef __BCM96756_H #define __BCM96756_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h index 5d9e87b693..37d2d91d96 100644 --- a/include/configs/bcm96813.h +++ b/include/configs/bcm96813.h @@ -6,6 +6,6 @@ #ifndef __BCM96813_H #define __BCM96813_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h index 1d6d5d6166..581fd55985 100644 --- a/include/configs/bcm96846.h +++ b/include/configs/bcm96846.h @@ -6,6 +6,6 @@ #ifndef __BCM96846_H #define __BCM96846_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h index 6e420f2c66..3fb1ab9230 100644 --- a/include/configs/bcm96855.h +++ b/include/configs/bcm96855.h @@ -6,6 +6,6 @@ #ifndef __BCM96855_H #define __BCM96855_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h index a7ae71eeaa..5f5af32189 100644 --- a/include/configs/bcm96856.h +++ b/include/configs/bcm96856.h @@ -6,6 +6,6 @@ #ifndef __BCM96856_H #define __BCM96856_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h index 4e584b41fb..9a0d89a751 100644 --- a/include/configs/bcm96858.h +++ b/include/configs/bcm96858.h @@ -6,6 +6,6 @@ #ifndef __BCM96858_H #define __BCM96858_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h index 3e23e94ac4..7702d1f568 100644 --- a/include/configs/bcm96878.h +++ b/include/configs/bcm96878.h @@ -6,6 +6,6 @@ #ifndef __BCM96878_H #define __BCM96878_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #endif diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index 76189a4d31..b5469880fe 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -15,7 +15,7 @@ #define V2M_BASE 0x80000000 #define PHYS_SDRAM_1 V2M_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * Initial SP before reloaction is placed at end of first DRAM bank, diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 9f51b9ca59..9769a71409 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -81,7 +81,7 @@ extern phys_addr_t prior_stage_fdt_address; * MiB. However, BOLT can be configured to allow loading larger * initramfs images, in which case this limitation is eliminated. */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x100000 /* diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 829e816ad6..556bfa08eb 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_BITMAIN_ANTMINER_S9_H #define __CONFIG_BITMAIN_ANTMINER_S9_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "pxefile_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index ca2bc1907e..a075a5b2f3 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -199,7 +199,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (SZ_512M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index c328f41420..e40f110cac 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index d16d50e5ec..508317f231 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index f69c46b11c..c5bda16d2b 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index acd021ecad..32397c26e8 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index fa9e5f02a0..18c99727a0 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index bcf5c874d3..f8d7148d49 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index e31b8bc719..d564a32ee5 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index 6e707d341b..f982a4363d 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index bb72c8cb53..11d623c28b 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index a1c992b7a6..30965c85bf 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -9,7 +9,7 @@ #include /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* U-Boot */ diff --git a/include/configs/boston.h b/include/configs/boston.h index a09e831c54..0033a7fb02 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -22,9 +22,9 @@ * Memory map */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index bdedf7ea2d..78b2000aa2 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -76,7 +76,7 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 1bf6baf75c..f1734aaca7 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -45,7 +45,7 @@ * always, even when we have more. We always start at 0x80000000, * and we place the initial stack pointer in our SRAM. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* * Our platforms make use of SPL to initalize the hardware (primarily diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index c4110f84c0..474ad69d99 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -92,7 +92,7 @@ /* On CCP board, USDHC1 is for eMMC */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 /* DDR3 board total DDR is 1 GB */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index c395384c8d..6f2b8245b9 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -111,7 +111,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index b7511adc09..f268dfd094 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -11,7 +11,7 @@ /* Memory configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ +#define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index fc45e597f6..eb899c4557 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -82,7 +82,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 25443629e2..47c4aacc43 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,7 +21,7 @@ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 52000b58b7..65b9074cd9 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -30,7 +30,7 @@ */ #define CONFIG_SYS_CLK 66000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* --- * Define baudrate for UART1 (console output, tftp, ...) @@ -152,9 +152,9 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* *------------------------------------------------------------------------- @@ -162,7 +162,7 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */ -/* #define CONFIG_SYS_SDRAM_SIZE 16 */ +/* #define CFG_SYS_SDRAM_SIZE 16 */ /* *----------------------------------------------------------------------- @@ -186,8 +186,8 @@ enter a valid image address in flash */ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index afe8badd65..ca8445a3d0 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -116,7 +116,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index d641fbf47e..6002d8d5c9 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -96,7 +96,7 @@ /* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ #define CFG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 68d923c1ae..14278e9ca4 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -100,7 +100,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index f9bf849ae9..c08095561d 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -160,7 +160,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 0f6f99d244..1128307139 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -85,7 +85,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (256 * SZ_1M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8e0230c135..8aec52d508 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM_1 (V2M_BASE) #define PHYS_SDRAM_1_SIZE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 9d44e6723e..c7a3e47437 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -32,8 +32,8 @@ #define CONFIG_USART_ID ATMEL_ID_SYS /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 4f0188dd19..e2e1cfedbd 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -166,7 +166,7 @@ /* Load U-Boot Image From MMC */ /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b944d50663..b16f3d48e3 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -42,7 +42,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5244b9cf5c..c473f3d86e 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -15,8 +15,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_64M /* * DMA diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index e694dd7551..ddc436d501 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -72,7 +72,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/display5.h b/include/configs/display5.h index 0e5ecab9fe..0a7428b02c 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -283,7 +283,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index c37b4c635b..daf7ecd797 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -17,7 +17,7 @@ #define PHYS_SDRAM_1 0x80000000 /* Note: 8 MiB (0x86000000 - 0x86800000) are reserved for tz/smem/hyp/rmtfs/rfsa */ #define PHYS_SDRAM_1_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Environment */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 1fa5d05e7b..31cd8536de 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -19,7 +19,7 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0x5ea4ffff -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #include diff --git a/include/configs/durian.h b/include/configs/durian.h index 8f0e8be433..001596c00a 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -11,7 +11,7 @@ /* Sdram Bank #1 Address */ #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE 0x7B000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* BOOT */ diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h index 1d655292d7..fc1c2aed77 100644 --- a/include/configs/ea-lpc3250devkitv2.h +++ b/include/configs/ea-lpc3250devkitv2.h @@ -13,7 +13,7 @@ /* * RAM */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE /* * cmd diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 80a820c913..80de73d15d 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -66,13 +66,13 @@ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE0 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE0 0x00000000 +#define CFG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 +#define CFG_SYS_SDRAM_BASE CFG_SYS_SDRAM_BASE0 +#define CFG_SYS_SDRAM_SIZE CFG_SYS_SDRAM_SIZE0 /* * For booting Linux, the board info and command line data @@ -103,8 +103,8 @@ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 16d2648e11..d24bc56f34 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -50,7 +50,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index a4891ddbc4..e39bb94314 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -27,7 +27,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index 60fab0419f..c2b921e7cb 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -8,8 +8,8 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_16M +#define CFG_SYS_SDRAM_BASE 0x10000000 +#define CFG_SYS_SDRAM_SIZE SZ_16M /* * Environment diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h index 2f067a4424..b4f14a9a58 100644 --- a/include/configs/espresso7420.h +++ b/include/configs/espresso7420.h @@ -10,7 +10,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index f19e12d909..97a8ffb4f6 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -26,8 +26,8 @@ #define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (128 << 20) /* 512kB on-chip NOR flash */ # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 44f5cb1e83..dd322c2b3a 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -29,21 +29,21 @@ #define CONFIG_RD_LVL -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* SPI */ diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 8e2f135f93..cc0cf5ecbf 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index a8bef860c2..cff910c1bd 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -23,21 +23,21 @@ /* select serial console configuration */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE /* Configuration of ENV Blocks */ diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index b05846d0b9..68c36dc2fd 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -21,32 +21,32 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5 (CFG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6 (CFG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7 (CFG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8 (CFG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_9 (CONFIG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_9 (CFG_SYS_SDRAM_BASE + (8 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_9_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_10 (CONFIG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_10 (CFG_SYS_SDRAM_BASE + (9 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_10_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_11 (CONFIG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_11 (CFG_SYS_SDRAM_BASE + (10 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_11_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_12 (CONFIG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_12 (CFG_SYS_SDRAM_BASE + (11 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_12_SIZE SDRAM_BANK_SIZE #ifndef MEM_LAYOUT_ENV_SETTINGS diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index ba098316e0..f5353ec79a 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -18,8 +18,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ /* NAND flash */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index a1400eba1a..a755714440 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -7,7 +7,7 @@ #define __CONFIG_GARDENA_SMART_GATEWAY_H /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index fa6f0e63ac..6cdfe8c4c3 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -12,9 +12,9 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE /* * Memory test diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index c862f15ee2..85ceaf8ccb 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -37,7 +37,7 @@ /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index d519384d02..1dba2e92fb 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -94,7 +94,7 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index d2138c220f..dd6b22de7b 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -13,8 +13,8 @@ /* Miscellaneous */ /* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 645ca162a3..fe00272a1b 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -53,7 +53,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/gxp.h b/include/configs/gxp.h index e3c97b20d5..2b0b04891c 100644 --- a/include/configs/gxp.h +++ b/include/configs/gxp.h @@ -10,6 +10,6 @@ #ifndef _GXP_H_ #define _GXP_H_ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/highbank.h b/include/configs/highbank.h index a7d21a76db..0d281a3379 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -14,7 +14,7 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 18c1e83aeb..775f166f1d 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -24,7 +24,7 @@ /* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ #define PHYS_SDRAM_1_SIZE 0x3EFFFFFF -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 973df8e4ab..914c3ad9ef 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -16,7 +16,7 @@ #define PHYS_SDRAM_1 0x00000000 #define PHYS_SDRAM_1_SIZE 0xC0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 1d7b171da7..fcb2dec54e 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -22,8 +22,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G /* * UART configuration diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 9e092e16ea..0ae935208c 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -21,8 +21,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_1G /* * UART configuration diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h index 1fc45f9060..f1ca28b7ca 100644 --- a/include/configs/imgtec_xilfpga.h +++ b/include/configs/imgtec_xilfpga.h @@ -21,8 +21,8 @@ */ /* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ /*---------------------------------------------------------------------- * Commands diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 974dff8f6f..594aa4f75e 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -130,5 +130,5 @@ "upd=run load update\0" \ /* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index b8eb5c82cf..d4e2583ee8 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -109,7 +109,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 6b822e7250..1b08c5e9a7 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -105,7 +105,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index f7f8f33ed8..a074df5829 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -55,7 +55,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 15171d7ad6..855af29ec9 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -85,7 +85,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 70b4b84215..0a688afe6c 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -63,7 +63,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index c6db5e943e..e5118f1158 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -69,7 +69,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 917d567d2e..e62f9c5462 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -127,7 +127,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 8e08899458..143da00110 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -74,7 +74,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index dd9f93f35c..c7669305f5 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -21,7 +21,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index f1d1c1c9c3..9937071874 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -57,7 +57,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 9cdba70493..cd47d842ff 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 065356341f..58e165c35a 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -32,7 +32,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 0ae3da12ad..f532c1052f 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -78,7 +78,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR) #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index d6959ac95a..415248eadf 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */ diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 9c75e3eec1..8857bc7c59 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -49,7 +49,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index a484d91364..628bb5813f 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -46,7 +46,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index d5252abb21..a169be35a4 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index bf87825136..62bcef5eec 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 1b533e2c14..d394762e3b 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -55,7 +55,7 @@ /* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 7986d20eed..3e995c9721 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 8f2b474817..1943a24b79 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -136,7 +136,7 @@ /* Totally 6GB or 4G DDR */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G) #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index b1c213cc89..7d360583c4 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -26,7 +26,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE SZ_2M -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 4b2107e405..271376cb9f 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -50,7 +50,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 2d4c8d78c6..672a9fa7a3 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -56,7 +56,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 1905e538c5..dd354b0265 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -88,7 +88,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7f6d59db3a..f1f907f3e5 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -103,7 +103,7 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 67f19bc192..fe27ac36a3 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -108,7 +108,7 @@ */ #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 567351fcad..19f1dba047 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -103,7 +103,7 @@ /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 7bf0ce784c..592df2795b 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -54,7 +54,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index b281466408..077a4d843d 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -127,7 +127,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 512e0e61aa..8d0458d1d6 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -30,7 +30,7 @@ */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * FLASH and environment organization diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h index a2e50c3b8d..5a769e0787 100644 --- a/include/configs/iot_devkit.h +++ b/include/configs/iot_devkit.h @@ -32,12 +32,12 @@ * : : * : Specified explicitly by CONFIG_CUSTOM_SYS_INIT_SP_ADDR * : - * Specified explicitly by CONFIG_SYS_SDRAM_BASE + * Specified explicitly by CFG_SYS_SDRAM_BASE * * NOTES: * - Stack starts from CONFIG_CUSTOM_SYS_INIT_SP_ADDR and grows down, - * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing - * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on + * i.e. towards CFG_SYS_SDRAM_BASE but nothing stops it from crossing + * that CFG_SYS_SDRAM_BASE in which case data won't be really saved on * stack any longer and values popped from stack will contain garbage * leading to unexpected behavior, typically but not limited to: * - "Returning" back to bogus caller function @@ -50,16 +50,16 @@ #define DCCM_BASE 0x80000000 #define DCCM_SIZE SZ_128K -#define CONFIG_SYS_SDRAM_BASE DCCM_BASE -#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE +#define CFG_SYS_SDRAM_BASE DCCM_BASE +#define CFG_SYS_SDRAM_SIZE DCCM_SIZE #define ROM_BASE CONFIG_SYS_MONITOR_BASE #define ROM_SIZE SZ_256K #define RAM_DATA_BASE SYS_INIT_SP_ADDR -#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ +#define RAM_DATA_SIZE CFG_SYS_SDRAM_SIZE - \ (SYS_INIT_SP_ADDR - \ - CONFIG_SYS_SDRAM_BASE) - \ + CFG_SYS_SDRAM_BASE) - \ CONFIG_SYS_MALLOC_LEN - \ CONFIG_ENV_SIZE #endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 9f54f25999..2a0b0c7163 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -16,7 +16,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ #define CONFIG_SYS_FLASH_BASE 0x000000000 diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index 932d7d3c8c..e690ef9590 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -17,7 +17,7 @@ #include /* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 +#define CFG_SYS_SDRAM_BASE1 0x880000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 7d36a25dc2..db1daee136 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -7,7 +7,7 @@ /* * DDR Setup */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) @@ -17,7 +17,7 @@ /* * Manually set up DDR parameters */ -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */ /* * The reserved memory diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index ad9853ab6b..b5913ed700 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -20,7 +20,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index c8423fdfb0..dbf038cefa 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -163,10 +163,10 @@ */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ +#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /****************************************************************************** * (PRAM usage) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index b3e1fc2a86..e2808ec02d 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -14,7 +14,7 @@ /* RAM */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index a2aedefcec..73b5951762 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -17,7 +17,7 @@ /* RAM */ #define PHYS_SDRAM DDR_CSD1_BASE_ADDR #define PHYS_SDRAM_SIZE (SZ_4G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 6acd2f7925..9b452818c1 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 7ed1f153c2..bbf0761814 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -21,7 +21,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* early stack pointer */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c401fd3216..967de66f3c 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -67,7 +67,7 @@ #define PHYS_SDRAM_1_SIZE (512 * SZ_1M) #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index b0e49ad6df..de1fc0bfa4 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -86,7 +86,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 1f642fbecc..bee064c6f3 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -85,7 +85,7 @@ "bootscript=source ${bootscraddr}\0" /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include diff --git a/include/configs/librem5.h b/include/configs/librem5.h index dbd7d107da..3a2c508ffa 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -82,7 +82,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB LPDDR4 one Rank */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index 28372d4159..b913450885 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -7,7 +7,7 @@ #define __CONFIG_LINKIT_SMART_7688_H /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 1d51b87b68..d1ebd99ae1 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -87,7 +87,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 196e024b57..f0a9e9ab31 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -9,7 +9,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 809f9ae8c8..0712437077 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /*SPI device */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 674bcbeb75..c19ed2f43e 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 9ad3a12011..54555b34dd 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 /* * QIXIS Definitions diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 4f77acdaed..d74936d128 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -10,7 +10,7 @@ #include "ls1012a_common.h" /* DDR */ -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x40000000 /* * I2C IO expander diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3579f9c843..49a77fd6b6 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -42,7 +42,7 @@ #define SDRAM_CFG_BI 0x00000001 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* * Serial Port diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 45665115f6..1f5a80ff08 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -20,7 +20,7 @@ #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 1e2db12a83..4954606611 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -57,7 +57,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Serial Port */ #define CFG_SYS_NS16550_CLK get_serial_clock() diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 323feb6e33..d77224934c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* * IFC Definitions diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 587f23be58..064c4f069c 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -15,7 +15,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index df6338298b..e940dff998 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -34,7 +34,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index b09588f479..ce254d8b3f 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -34,7 +34,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 2117b08116..f8eaee881d 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -32,7 +32,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c79a50795b..21c097ecbb 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -19,7 +19,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 8b2b7479c1..ad85e2de6e 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -17,8 +17,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE 0x200000000UL +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 1734f323f9..cbdb2fa135 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -20,7 +20,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/malta.h b/include/configs/malta.h index 2dd34ea731..c9aee00cd3 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -22,11 +22,11 @@ */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +# define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 +# define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index db84302231..5ad945b558 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -47,6 +47,6 @@ */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_1G +#define CFG_SYS_SDRAM_SIZE SZ_1G #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index f9f0825f6f..8aa3b0cd80 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -214,7 +214,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index c6ce883747..2422cbf9f0 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -17,7 +17,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/meesc.h b/include/configs/meesc.h index cd3910ee4b..2e07886c19 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -44,8 +44,8 @@ #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 726f33c26c..6331b7615d 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -36,7 +36,7 @@ #define STDIN_CFG "serial" #endif -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 4c7cfac8af..3def93d61e 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -9,7 +9,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index bd35378800..ac5ff9289a 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -49,7 +49,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ #define PHYS_SDRAM_2 0xc0000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index c76e1fcaed..65cd6f5bc4 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7620_H #define __CONFIG_MT7620_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index e09e9c82eb..1211bb4748 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7621_H #define __CONFIG_MT7621_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index fd8e30acf5..e5d60e1cd2 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -15,7 +15,7 @@ /* SPL -> Uboot */ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 73093f94d2..39a7ba7663 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -21,7 +21,7 @@ #define MMC_SUPPORTS_TUNING /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* This is needed for kernel booting */ #define FDT_HIGH "0xac000000" diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index bb12ebfe4f..9c5034f5f0 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_MT7628_H #define __CONFIG_MT7628_H -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x80000 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 668dc3c4f7..d330adbc01 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -25,7 +25,7 @@ /* UBoot -> Kernel */ /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ #define CONFIG_IPADDR 192.168.1.1 diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 9f26b0ba7b..249f0b9662 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -16,6 +16,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 4fbd57a573..990e411a64 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -16,6 +16,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #endif diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 7cabbef928..8a8bc85ca7 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -10,8 +10,8 @@ #define __MT8518_H /* DRAM definition */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* Uboot definition */ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e870fc810c..e45bfd76b6 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -27,7 +27,7 @@ */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* * NS16550 Configuration diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 41bdfae6c3..9c4038be8b 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -9,7 +9,7 @@ #include /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x200000000 +#define CFG_SYS_SDRAM_BASE 0x200000000 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 6d3cb99b2d..7641b56221 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -13,7 +13,7 @@ */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 5debd9117c..358e06fd20 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index dd303a17d6..aa3d7a1a3f 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -10,7 +10,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Status LED */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 4c0531212e..f597cdb305 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environments */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 140f5e98c5..bc8c893370 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -13,7 +13,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* UBI and NAND partitioning */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 95afb350ec..2229980db3 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -112,7 +112,7 @@ #define PHYS_SDRAM_1 CSD0_BASE_ADDR #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 7783563972..e84bac67ef 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 3c9b2ad58e..9e837a3883 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -95,7 +95,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index b26613a2ea..52ff7b00b4 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -96,7 +96,7 @@ #define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 1db4d6c01b..3c4ba095e4 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -85,7 +85,7 @@ #include /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index a6cefab550..9c160c41ec 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -27,7 +27,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index bc9fab1290..711b5a334a 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -139,7 +139,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ca1d077437..3c2621d8c9 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -82,7 +82,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 44a5eeff19..a3a12aeb39 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -82,7 +82,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_2G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index a41e428eb8..f0e239fdb6 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -78,7 +78,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index c655671ee1..a0f9c537e5 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -106,7 +106,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 65f0a5c996..8199b4b831 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -108,7 +108,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 604923ec2b..827385c65e 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -102,7 +102,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index af17658381..c39b3572b8 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -81,7 +81,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 62e8e62991..362de482f5 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -26,7 +26,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM 0x60000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index e93824928b..9ef1eea5e6 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -26,7 +26,7 @@ #define PHYS_SDRAM 0x60000000 #define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 273f938554..cdd12866ac 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -22,7 +22,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index ec5339d930..9d09811316 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -90,7 +90,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 2623f99f8d..9ad4f59069 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -161,7 +161,7 @@ * FLASH and environment organization */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -170,7 +170,7 @@ */ #define SDRAM_SIZE 0x10000000 /* 256 MB */ -#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) +#define SDRAM_END (CFG_SYS_SDRAM_BASE + SDRAM_SIZE) #define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ #define KERNEL_OFFSET 0x40000 /* 256 kB */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 9dc05d80ec..8d39d75a42 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -30,7 +30,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index ea407c9f6f..080c659b6e 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -23,7 +23,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/nsim.h b/include/configs/nsim.h index d469ef83c2..b930a53864 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -13,8 +13,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_256M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_256M /* * Console configuration diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 00f7d87127..5ac951a370 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -7,7 +7,7 @@ #include "mx6_common.h" #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 0fa7490e7d..b475354bbc 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -14,6 +14,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 #endif -#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 +#define CFG_SYS_SDRAM_BASE 0xffffffff80000000 #endif /* __OCTEON_COMMON_H__ */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index ab1eb787e7..03d1a8e7b5 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -10,7 +10,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */ /** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE /** Stack starting address */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 38f99ab216..58275ccffa 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -36,7 +36,7 @@ /** Maximum size of image supported for bootm (and bootable FIT images) */ /** Memory base address */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_TEXT_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_TEXT_BASE /** Stack starting address */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index babd3ca963..ce8ea583fa 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -17,9 +17,9 @@ #define CONFIG_SYS_PL310_BASE 0x10502000 #endif -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #include diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 1564629742..d2d7fca544 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define TZPC_BASE_OFFSET 0x10000 diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 2b47d4ca37..5b0d87a336 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -154,7 +154,7 @@ /* defines for SPL */ /* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CFG_SYS_SDRAM_BASE 0xc0000000 #include diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 3ff8187b5d..5b097e9fef 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -14,7 +14,7 @@ #include /* Environment options */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* --------------------------------------------------------------------- * Board boot configuration diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index b3cdd2f1eb..53889d699b 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -14,7 +14,7 @@ #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/origen.h b/include/configs/origen.h index 36aaa7c14f..6633d541a3 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -11,8 +11,8 @@ #include /* ORIGEN has 4 bank of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Power Down Modes */ diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h index b0233b96b0..8d0311cfb3 100644 --- a/include/configs/owl-common.h +++ b/include/configs/owl-common.h @@ -11,7 +11,7 @@ #define _OWL_COMMON_CONFIG_H_ /* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 /* Some commands use this as the default load address */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6e8ac1b98d..14d702e1ef 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -125,13 +125,13 @@ #define SPD_EEPROM_ADDRESS 0x52 #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #else -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G +#define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) +#define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE /* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 6267dc729a..85cedde098 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -34,7 +34,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index e13b5df0fa..f7e36f22ce 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -36,7 +36,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE SZ_256M -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a04a03a7e1..586cddf418 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -118,7 +118,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 14cbfde28b..cf705dcb19 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -15,7 +15,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index 7a8d3c63d4..bfc0011fbf 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -20,7 +20,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_POWER_TPS65090_EC diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 2c749ac214..09c6b4f8dd 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -20,7 +20,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index c98393b7c7..ac68c933a0 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 49cd9d4b3c..aedaf806e5 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -63,7 +63,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 4ea16d6115..d9abbbc28b 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -23,7 +23,7 @@ (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x88000000 +#define CFG_SYS_SDRAM_BASE 0x88000000 /* Memory Test */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index f95beeb214..fc2cab960c 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -91,7 +91,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 85772ba6e8..22b4976d72 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -91,7 +91,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index b3a38d8a94..f5b9eed2bc 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -93,7 +93,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 17af19d49d..91baff9638 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -67,7 +67,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index adb2f43ea4..3fbddd903a 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -78,22 +78,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ @@ -160,6 +160,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ "" -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 4352a242de..c1f6334d6a 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -90,22 +90,22 @@ /* Memory Device Register -> SDRAM */ #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ +#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ #define CONFIG_SYS_SMC0_SETUP0_VAL \ @@ -184,6 +184,6 @@ "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ "" -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index a7deaa3213..4a0a16818e 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -20,8 +20,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE 0x70000000 +#define CFG_SYS_SDRAM_SIZE 0x08000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 05253d59ef..365fdd30c0 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -11,7 +11,7 @@ #endif #define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ #define CONFIG_SERVERIP 192.168.0.1 diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 2e206542f8..1c11685f49 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -9,7 +9,7 @@ #define __POMELO_CONFIG_H__ /* SDRAM Bank #1 start address */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* SIZE of malloc pool */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index f9decb2a4c..bee1ef6494 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -36,7 +36,7 @@ #define DDR_BASE 0x00000000 #define PHYS_SDRAM_1 DDR_BASE #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Console I/O Buffer Size */ diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 8b151ef188..99376155b4 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -14,7 +14,7 @@ #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index 535762ecb2..a67af73fd5 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -10,7 +10,7 @@ /* Physical memory map */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* GUIDs for capsule updatable firmware images */ #define QEMU_ARM_UBOOT_IMAGE_GUID \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 9fc51fdfd7..e7c810957d 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -31,7 +31,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_HWCONFIG diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index d81e5d6c86..72f35cc054 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index 406ee6282c..f6ee7201eb 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -6,8 +6,8 @@ /* SCIF */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x8C000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE 0x8C000000 +#define CFG_SYS_SDRAM_SIZE 0x04000000 /* Address of u-boot image in Flash */ #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 3a38e0656d..61b9447ea5 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -17,8 +17,8 @@ /* console */ #define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } -#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) +#define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ #define CONFIG_TMU_TIMER diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 7432cffb5a..5853072597 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -26,8 +26,8 @@ /* MEMORY */ #define DRAM_RSV_SIZE 0x08000000 -#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) -#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 6616396777..b4c1972747 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,7 @@ #define CONFIG_SYS_HZ_CLOCK 24000000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 9297184bde..99c86edeaa 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) #define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 12d4bc65d7..fac27a7d27 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -14,7 +14,7 @@ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_MAX_SIZE 0x80000000 /* usb mass storage */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 6fe1b2d9a2..334fb3affa 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -13,7 +13,7 @@ /* spl size 32kb sram - 2kb bootrom */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0x80000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 4fb86b69a8..6889ba591b 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -12,7 +12,7 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE 0x80000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 81f16edbad..4aa7e0449d 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -15,7 +15,7 @@ /* RAW SD card / eMMC locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 263d1bd180..4b510b1399 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -10,7 +10,7 @@ #define CONFIG_IRAM_BASE 0xfff80000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define SDRAM_BANK_SIZE (2UL << 30) diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 1e214e4ebe..132b7d0fe9 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -11,7 +11,7 @@ #define CONFIG_IRAM_BASE 0xff090000 /* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 37e0c1d936..92cdc1a51f 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2f9aee5819..78f624d31c 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -21,7 +21,7 @@ /* RAW SD card / eMMC locations. */ /* FAT sd card locations. */ -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 15e8152340..d43dc2580e 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -10,7 +10,7 @@ #define CONFIG_IRAM_BASE 0xfdcc0000 -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 #define ENV_MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index cd8fe8b518..2c24944d9c 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -23,7 +23,7 @@ #endif /* Memory layout */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares @@ -31,7 +31,7 @@ * smaller amount of RAM is present in order to avoid stomping on the area * the VC uses. */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_SIZE SZ_128M /* Devices */ /* LCD */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 83c3167f38..76836add30 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_TIMER_BASE 0x10350020 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) -#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 /* rockchip ohci host driver */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index ae94f0ecc5..e071d4da5e 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -18,7 +18,7 @@ /*----------------------------------------------------------------------- * System memory Configuration */ -#define CONFIG_SYS_SDRAM_BASE 0x71000000 +#define CFG_SYS_SDRAM_BASE 0x71000000 /* * "(0x40000000 - CONFIG_SYS_RESERVE_MEM_SIZE)" has been used in @@ -55,7 +55,7 @@ * Starting kernel ... * ... */ -#define CONFIG_SYS_SDRAM_SIZE (0xb0000000 - CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_SDRAM_SIZE (0xb0000000 - CFG_SYS_SDRAM_BASE) #define BMP_LOAD_ADDR 0x78000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index de4510aa43..ed891ab22a 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -14,7 +14,7 @@ #include /* get chip and board defs */ /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000 /* Text Base */ @@ -114,7 +114,7 @@ "dfu_alt_info=" CONFIG_DFU_ALT "\0" /* Goni has 3 banks of DRAM, but swap the bank */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ #define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ #define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ #define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 668b52600e..614d04fda0 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -14,8 +14,8 @@ /* Keep L2 Cache Disabled */ /* Universal has 2 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index afb1e3d0f1..75302bf5c0 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -17,7 +17,7 @@ #define CONFIG_USART_ID 0 /* ignored in arm */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */ #endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 7c5bfdb2e6..22813d4c54 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -23,8 +23,8 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index de6c92ed7d..f826eab9ff 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -16,8 +16,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* SPL */ diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index ebdb39273e..01ed1a3c8e 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -15,8 +15,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #ifdef CONFIG_SD_BOOT /* u-boot env in sd/mmc card */ diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 09cc4dddb2..2e3c1ea400 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -16,8 +16,8 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND Flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 1c9af9b675..4b13a10117 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -24,8 +24,8 @@ #define ATMEL_PMC_UHP (1 << 6) /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index afb9b9a2fb..3f58928565 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -31,8 +31,8 @@ #endif /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* SerialFlash */ diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index 0daadec553..084cb4def6 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index d59899f0ba..cbc1c0f465 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 3f905bf2d7..68fa31fe76 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x60000000 +#define CFG_SYS_SDRAM_SIZE 0x20000000 #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 0dcb2ebc31..5a7f5e135b 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -13,8 +13,8 @@ /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y #define SB_TO_UL(s) SB_CONCAT(s, UL) -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE \ +#define CFG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index c9dd7509cb..31552f4619 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -33,7 +33,7 @@ /* Physical Memory Map */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 2e5592cf94..5ad2124bdd 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -11,7 +11,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 85fab92719..f4b1a16019 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -11,7 +11,7 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 7159fc35d5..974531ea0d 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -8,8 +8,8 @@ #include -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_8M +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_8M #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 7c8f1676be..d2bc73a400 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -45,8 +45,8 @@ * SDRAM: 1 bank, 64 MB, base address 0x20000000 * Already initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (64 * SZ_1M) /* * Perform a SDRAM Memtest from the start of SDRAM diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 12c2e1f615..0392530c0a 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -14,7 +14,7 @@ #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ba562b2378..64963eebe5 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -16,7 +16,7 @@ /* input clock of PLL: SMDKC100 has 12MHz input clock */ /* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 +#define CFG_SYS_SDRAM_BASE 0x30000000 /* Text Base */ @@ -77,7 +77,7 @@ */ /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ /*----------------------------------------------------------------------- diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 0b1f0c5f54..af0c8200fc 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -11,7 +11,7 @@ #include "exynos4-common.h" /* High Level Configuration Options */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD @@ -23,13 +23,13 @@ /* SMDKV310 has 4 bank of DRAM */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3 (CFG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4 (CFG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index faa13c6521..44b9109d44 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -38,7 +38,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 7c35c912e5..9b1cb372ec 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -21,8 +21,8 @@ /* CPU */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 6054fa42c1..9551680079 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -32,7 +32,7 @@ * Memory */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* * I2C diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 70a24ed267..2656c97767 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -38,7 +38,7 @@ * in U-Boot pre-reloc is higher than in SPL. */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* * U-Boot general configurations diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 2b2d78b8c8..9403e2f430 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -70,7 +70,7 @@ */ #define PHYS_SDRAM_1 0x0 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE 0 +#define CFG_SYS_SDRAM_BASE 0 /* * Serial / UART configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index a60ac6d1a3..c628860eac 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -55,7 +55,7 @@ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ @@ -73,7 +73,7 @@ #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ +#define CFG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index dcb88a3a73..008aa50010 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -53,7 +53,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 1e966a2322..806323e375 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -11,7 +11,7 @@ /* ram memory-related information */ #define PHYS_SDRAM_1 0x40000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 #define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 07a5bfc8a8..d711149314 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -13,7 +13,7 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE /* * For booting Linux, use the first 256 MB of memory, since this is diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index b809f9322a..f78ce41ed8 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -13,7 +13,7 @@ /* * Configuration of the external SRAM memory used by U-Boot */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE /* * For booting Linux, use the first 256 MB of memory, since this is diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index ba49075ce0..234327e017 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -56,10 +56,10 @@ /* * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 + * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ #define CONFIG_SYS_DRAM_TEST @@ -75,8 +75,8 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ + (CFG_SYS_SDRAM_SIZE << 20)) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -89,8 +89,8 @@ CONFIG_SYS_INIT_RAM_SIZE - 4) #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ +#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 567aa1ffe4..b2dcb6058b 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -10,7 +10,7 @@ /* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x00198000 /* user interface */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cd2a74fb52..e1a66f53ff 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -42,13 +42,13 @@ */ #ifdef CONFIG_MACH_SUN9I #define SDRAM_OFFSET(x) 0x2##x -#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 #elif defined(CONFIG_MACH_SUNIV) #define SDRAM_OFFSET(x) 0x8##x -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #else #define SDRAM_OFFSET(x) 0x4##x -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* V3s do not have enough memory to place code at 0x4a000000 */ #endif @@ -66,7 +66,7 @@ /* FIXME: this may be larger on some SoCs */ #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ /* mmc config */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 63d897d090..daa9bbec88 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -11,7 +11,7 @@ /* * SDRAM (for initialize) */ -#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ +#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ #define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index dd1fe0af7c..1aba986e1e 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -41,8 +41,8 @@ * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) /* * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, diff --git a/include/configs/tb100.h b/include/configs/tb100.h index 92ee920346..cd1309b3b8 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -13,8 +13,8 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M /* * UART configuration diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 7f197851d0..2d8bde1cee 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -13,7 +13,7 @@ /* General configuration */ /* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR +#define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 92df457e81..7e764b0000 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -40,7 +40,7 @@ #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 655fcb0011..76b496303f 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -68,6 +68,6 @@ /* Defines for SPL */ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SYS_SDRAM_SIZE SZ_2G +#define CFG_SYS_SDRAM_SIZE SZ_2G #endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index cf2efdbe23..1f60b9b497 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -13,7 +13,7 @@ /* Link Definitions */ /* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CPU_RELEASE_ADDR (CFG_SYS_SDRAM_BASE + 0x7fff0) /* PL011 Serial Configuration */ @@ -30,7 +30,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Initial environment variables */ #define UBOOT_IMG_HEAD_SIZE 0x40 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index fc78077014..e5b23d2a54 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -69,7 +69,7 @@ #define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 1bd2a1874b..4a7c3d5b44 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -20,7 +20,7 @@ #define V_SCLK (V_OSCK >> 1) #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /** * Platform/Board specific defs diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index b289b9e26a..d54c208ef6 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -64,7 +64,7 @@ * initial stack pointer in our SRAM. Otherwise, we can define * CONFIG_NR_DRAM_BANKS before including this file. */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 /* If DM_I2C, enable non-DM I2C support */ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index ab6cd06332..a609aa3a2a 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -23,7 +23,7 @@ /* Top 48MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x03000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000 diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 22d783c325..1378981991 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CFG_SYS_SDRAM_BASE 0xa0000000 #define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index a65ebfb4de..f8e3a2d017 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -268,7 +268,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/trats.h b/include/configs/trats.h index ca31868778..23dcf20c1f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -16,8 +16,8 @@ #endif /* TRATS has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Tizen - partitions definitions */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index f324ea7ebe..9c6433ccfd 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -17,8 +17,8 @@ #endif /* TRATS2 has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ /* Tizen - partitions definitions */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index f549f9f7ad..4ca8eafc91 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -8,7 +8,7 @@ #ifndef _CONFIG_TURRIS_MOX_H #define _CONFIG_TURRIS_MOX_H -#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 268c737e7e..c1e80b44c8 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -49,7 +49,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 147224806f..f73092661a 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -57,7 +57,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 2cdc3fbf73..d2fd23e1d9 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -25,8 +25,8 @@ */ /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 +#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CFG_SYS_SDRAM_SIZE 0x04000000 #define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) #define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index c381934f31..e944e78603 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -60,7 +60,7 @@ #define PHYS_SDRAM CSD0_BASE_ADDR #define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 338d8af8fb..d9e5dfacea 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -14,13 +14,13 @@ #define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (128 * SZ_1M) #elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) -#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (256 * SZ_1M) #elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) -#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) +#define CFG_SYS_SDRAM_SIZE (512 * SZ_1M) #else #error Unknown DDR size - please add! #endif diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index f513dade6a..b209d97e5e 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -60,7 +60,7 @@ /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #endif -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 /* SDRAM configuration */ #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index fea4329d23..1b9f2ca26f 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -69,7 +69,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G) #define PHYS_SDRAM_2 0x100000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 0c11b6b333..9a46d50c6f 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -96,7 +96,7 @@ /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO #define PHYS_SDRAM_2 (0x880000000) diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 5d773060d8..ef136c75a8 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -135,7 +135,7 @@ #define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ /* additions for new relocation code */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Basic environment settings */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 215149af2e..7b526f725a 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -123,7 +123,7 @@ #define PHYS_SDRAM (0x80000000) #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/vinco.h b/include/configs/vinco.h index a157296761..df0e269b5d 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -24,8 +24,8 @@ #define CONFIG_SYS_TIMER_COUNTER 0xfc06863c /* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x4000000 +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x4000000 /* MMC */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a0846b3f7c..7555d97c81 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -23,7 +23,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 2107bec658..38b940d35e 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -7,7 +7,7 @@ #define __VOCORE2_CONFIG_H__ /* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b4c757fd92..3acef22132 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -89,7 +89,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a4b12dc55e..cba215c379 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -84,7 +84,7 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 054eb89d49..32555c9b6a 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -16,8 +16,8 @@ /* * Memory configurations */ -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CFG_SYS_SDRAM_SIZE SZ_128M #define CONFIG_RTC_DS1374 diff --git a/include/configs/xea.h b/include/configs/xea.h index 19ccf633c4..87f628d4ab 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -23,7 +23,7 @@ /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environment */ #define CONFIG_HOSTNAME "xea" diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 364dae0cd9..612436aeb4 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -11,7 +11,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_SDRAM_BASE +#undef CFG_SYS_SDRAM_BASE #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index d2c0e91b32..1b6e26ee39 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -12,7 +12,7 @@ #include -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CFG_SYS_SDRAM_SIZE 0x1000000 +#define CFG_SYS_SDRAM_BASE 0x0 #endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 7d0402feea..613ed95955 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -21,7 +21,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index b93451cbe0..8739bb2484 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -42,12 +42,12 @@ */ #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE +#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE #else -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 #endif -#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) +#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000) /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ @@ -70,12 +70,12 @@ #endif #if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE + CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) #endif /*==============================*/ diff --git a/include/init.h b/include/init.h index d40d11f33d..699dc2482c 100644 --- a/include/init.h +++ b/include/init.h @@ -90,8 +90,8 @@ int dram_init(void); * * If this is not provided, a default implementation will try to set up a * single bank. It will do this if CONFIG_NR_DRAM_BANKS and - * CONFIG_SYS_SDRAM_BASE are set. The bank will have a start address of - * CONFIG_SYS_SDRAM_BASE and the size will be determined by a call to + * CFG_SYS_SDRAM_BASE are set. The bank will have a start address of + * CFG_SYS_SDRAM_BASE and the size will be determined by a call to * get_effective_memsize(). * * Return: 0 if OK, -ve on error diff --git a/include/system-constants.h b/include/system-constants.h index 83b41b384f..07c3505e8f 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,7 +12,7 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) diff --git a/post/drivers/memory.c b/post/drivers/memory.c index d249942af0..8deac75ebb 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -467,7 +467,7 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { struct bd_info *bd = gd->bd; - *vstart = CONFIG_SYS_SDRAM_BASE; + *vstart = CFG_SYS_SDRAM_BASE; *size = (gd->ram_size >= 256 << 20 ? 256 << 20 : gd->ram_size) - (1 << 20); diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index 1cc07bc808..b5e9f9ddc9 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -208,7 +208,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) * at SDRAM_BASE *device* address (p_paddr field). * Its size is defined by the p_filesz field. */ - phdr->p_paddr = CONFIG_SYS_SDRAM_BASE; + phdr->p_paddr = CFG_SYS_SDRAM_BASE; loaded_firmware_size = phdr->p_filesz; /* @@ -231,7 +231,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) unmap_physmem(loaded_firmware, MAP_NOCACHE); /* Resource table */ - shdr->sh_addr = CONFIG_SYS_SDRAM_BASE; + shdr->sh_addr = CFG_SYS_SDRAM_BASE; rsc_table_size = shdr->sh_size; loaded_rsc_table_paddr = shdr->sh_addr + DEVICE_TO_PHYSICAL_OFFSET; @@ -243,7 +243,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) /* Load and verify */ ut_assertok(rproc_elf32_load_rsc_table(dev, (ulong)valid_elf32, size, &rsc_addr, &rsc_size)); - ut_asserteq(rsc_addr, CONFIG_SYS_SDRAM_BASE); + ut_asserteq(rsc_addr, CFG_SYS_SDRAM_BASE); ut_asserteq(rsc_size, rsc_table_size); ut_asserteq_mem(loaded_firmware, valid_elf32 + shdr->sh_offset, shdr->sh_size); From 3b8dfc42a239cbb1561e7ecbc116b69fb6913355 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:38 -0500 Subject: [PATCH 024/424] Convert CONFIG_SYS_TIMER_COUNTS_DOWN to Kconfig This converts the following to Kconfig: CONFIG_SYS_TIMER_COUNTS_DOWN Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/mach-kirkwood/include/mach/config.h | 1 - arch/sh/include/asm/config.h | 1 - configs/alt_defconfig | 1 + configs/bitmain_antminer_s9_defconfig | 1 + configs/blanche_defconfig | 1 + configs/gose_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/lager_defconfig | 1 + configs/porter_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/silk_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_is1_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/stout_defconfig | 1 + configs/syzygy_hub_defconfig | 1 + configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + include/configs/rcar-gen2-common.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/vexpress_common.h | 1 - include/configs/zynq-common.h | 1 - lib/Kconfig | 3 +++ 40 files changed, 36 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index ae1f6fee53..5186f6e4f9 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -52,7 +52,6 @@ /* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK #endif diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 09a15da485..99d8797a54 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,7 +9,6 @@ #include /* Timer */ -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) diff --git a/configs/alt_defconfig b/configs/alt_defconfig index e4d6fc2d2c..d28cdf4b36 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index cbcbc9b18d..02257176e3 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -93,4 +93,5 @@ CONFIG_ZYNQ_SERIAL=y # CONFIG_WATCHDOG is not set CONFIG_WDT=y CONFIG_WDT_CDNS=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_EFI_LOADER is not set diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index bed7370807..630a13f929 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -81,3 +81,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 55222ebe01..b918b131d3 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index b4e6baef48..24eff4648e 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/lager_defconfig b/configs/lager_defconfig index 472d8dafc4..56057e272d 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 83cc54aef9..ca56008cb5 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -103,3 +103,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index cee9a1ff5c..4217175345 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -57,4 +57,5 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SCIF_CONSOLE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 9ff9e23ef9..5005e1677f 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -105,3 +105,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 2951574464..67c6e74eb8 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 9c3c0f66b2..ce1a349299 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -79,3 +79,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index b3ba9ff21e..01c29a25e3 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -82,3 +82,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index 5f5706fbdb..905afb7d04 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -75,3 +75,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 1f835bea92..f2a53ba247 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index 412b0da0db..dbf979ee47 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 68a36892fb..613bf44262 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -60,4 +60,5 @@ CONFIG_SPI=y CONFIG_USB=y CONFIG_USB_DWC2=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_EFI_LOADER is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 3a21bc77a2..32d7b74520 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 8be8b85c0c..4d16ec32b6 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -73,3 +73,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index debe22f30a..7a805df5a3 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -112,4 +112,5 @@ CONFIG_DESIGNWARE_SPI=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 31cc03a5fd..b3de6701f9 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -79,3 +79,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 72a7037536..80a98712f6 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -80,3 +80,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 44e9ba6c88..cbe37d22fe 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -76,3 +76,4 @@ CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y # CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 96c0ebbc0c..cdad36bbfd 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -116,3 +116,4 @@ CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_DESIGNWARE_WATCHDOG=y CONFIG_WDT=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 231e22a2a0..53dce6a161 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -104,3 +104,4 @@ CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_PCI=y CONFIG_USB_STORAGE=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 179cb52212..aa28a68a86 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index e3ed0b2732..96aa62a7ec 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index cb156562ba..41ba8a7487 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 03d1887cda..763bd8cccd 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 234686eb7b..70ce13eccc 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -54,3 +54,4 @@ CONFIG_SMC911X=y CONFIG_SMC911X_32_BIT=y CONFIG_BAUDRATE=38400 CONFIG_CONS_INDEX=0 +CONFIG_SYS_TIMER_COUNTS_DOWN=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 1db3a2c635..a4c555dac5 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -146,6 +146,7 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y CONFIG_SPL_GZIP=y CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 7ca74837ae..74c35f3a4d 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -78,5 +78,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_ZYNQ=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_ARM_DCC=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 28e9c45981..f1c648a8f9 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -80,5 +80,6 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_ARM_DCC=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 215d5ed5eb..c623caf564 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -90,5 +90,6 @@ CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_ARM_DCC=y CONFIG_ZYNQ_QSPI=y +CONFIG_SYS_TIMER_COUNTS_DOWN=y # CONFIG_GZIP is not set # CONFIG_LMB is not set diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 61b9447ea5..606a0a7ecd 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -22,7 +22,6 @@ /* Timer */ #define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2656c97767..7ef7c5da82 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -55,7 +55,6 @@ */ #ifndef CONFIG_TIMER #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) #ifndef CONFIG_SYS_TIMER_RATE #define CONFIG_SYS_TIMER_RATE 25000000 diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index ef136c75a8..de571f63ee 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -114,7 +114,6 @@ #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 6574cf92e2..2d6522af81 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -16,7 +16,6 @@ #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 #define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR -#define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) /* GUIDs for capsule updatable firmware images */ diff --git a/lib/Kconfig b/lib/Kconfig index 6abe1d0a86..c39fc52321 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -15,6 +15,9 @@ config SYS_NUM_ADDR_MAP help Sets the number of entries in the virtual-physical mapping table. +config SYS_TIMER_COUNTS_DOWN + bool "System timer counts down rathe than up" + config PHYSMEM bool "Access to physical memory region (> 4G)" help From 97396cc9ce9963ece8778b3a7c6f918745ef25b2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:39 -0500 Subject: [PATCH 025/424] Convert CONFIG_SYS_SRIO et al to Kconfig This converts the following to Kconfig: CONFIG_SRIO1 CONFIG_SRIO2 CONFIG_SRIO_PCIE_BOOT_MASTER CONFIG_SYS_SRIO Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- README | 12 ------------ arch/powerpc/Kconfig | 15 +++++++++++++++ configs/MPC8548CDS_36BIT_defconfig | 2 ++ configs/MPC8548CDS_defconfig | 2 ++ configs/MPC8548CDS_legacy_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 4 ++++ configs/P2041RDB_SDCARD_defconfig | 4 ++++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++++ configs/P2041RDB_defconfig | 4 ++++ configs/T2080QDS_NAND_defconfig | 4 ++++ configs/T2080QDS_SDCARD_defconfig | 4 ++++ configs/T2080QDS_SECURE_BOOT_defconfig | 4 ++++ configs/T2080QDS_SPIFLASH_defconfig | 4 ++++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 4 ++++ configs/T2080QDS_defconfig | 4 ++++ include/configs/MPC8548CDS.h | 3 --- include/configs/P2041RDB.h | 5 ----- include/configs/T102xRDB.h | 2 -- include/configs/T208xQDS.h | 6 ------ include/configs/T208xRDB.h | 1 - 20 files changed, 61 insertions(+), 29 deletions(-) diff --git a/README b/README index b095937121..bb35a895b7 100644 --- a/README +++ b/README @@ -1686,18 +1686,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_OR_TIMING_SDRAM: SDRAM timing -- CONFIG_SYS_SRIO: - Chip has SRIO or not - -- CONFIG_SRIO1: - Board has SRIO 1 port available - -- CONFIG_SRIO2: - Board has SRIO 2 port available - -- CONFIG_SRIO_PCIE_BOOT_MASTER - Board can support master function for Boot from SRIO and PCIE - - CONFIG_SYS_SRIOn_MEM_VIRT: Virtual Address of SRIO port 'n' memory region diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index c355a95453..cf93a7b1da 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -44,6 +44,21 @@ config SYS_INIT_RAM_LOCK bool "Lock some portion of L1 for initial ram stack" depends on MPC83xx || MPC85xx +config SYS_SRIO + bool "Serial RapidIO support" + +config SRIO1 + bool "Board has SRIO 1 port available" + depends on SYS_SRIO + +config SRIO2 + bool "Board has SRIO 2 port available" + depends on SYS_SRIO + +config SRIO_PCIE_BOOT_MASTER + bool "Board can support master function for Boot from SRIO and PCIE" + depends on SYS_SRIO + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 85b055a93f..86a67d7b21 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 0d21b893d8..2ac4f26685 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index b01919ec67..faabd7bc04 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 0eec508933..3d24b1a78c 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index f9f4c31ddb..cec55a1412 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -6,6 +6,10 @@ CONFIG_ENV_OFFSET=0xCF400 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 6a97437008..5fcf154642 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -7,6 +7,10 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 1725a8a5a9..ce198e28cb 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -7,6 +7,10 @@ CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index dd7473ef7f..637842cda2 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -11,6 +11,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 364aab5847..35ab9931e7 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -12,6 +12,10 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c6710a0413..93b02a5e99 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -4,6 +4,10 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index a705542eea..7d25bbbb0b 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -14,6 +14,10 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index d6d6ec0fbf..2846f63d47 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -5,6 +5,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xFFE20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 802213de2b..a7dc88c0bf 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -6,6 +6,10 @@ CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y +CONFIG_SYS_SRIO=y +CONFIG_SRIO1=y +CONFIG_SRIO2=y +CONFIG_SRIO_PCIE_BOOT_MASTER=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 6a51149a94..eb75f8b37d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,9 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ #ifndef __ASSEMBLY__ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index d7e06d23ec..be8d09f6dd 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -32,11 +32,6 @@ #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER - #ifndef __ASSEMBLY__ #include #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 616387f487..f9f9318448 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -49,8 +49,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 8f56de40ce..acaad1bfc8 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -14,11 +14,6 @@ #include #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#endif /* High Level Configuration Options */ @@ -52,7 +47,6 @@ #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index e9db4a224f..7315afa39f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -47,7 +47,6 @@ #endif /* CONFIG_RAMBOOT_PBL */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) From a322afc9f9b69dd52a9bc72937cd5adc18ea55c7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:40 -0500 Subject: [PATCH 026/424] global: Move remaining CONFIG_*SRIO_* to CFG_* The rest of the unmigrated CONFIG symbols in the SRIO namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/powerpc/cpu/mpc8xxx/law.c | 20 +++---- arch/powerpc/cpu/mpc8xxx/srio.c | 72 +++++++++++++------------- board/freescale/common/p_corenet/tlb.c | 8 +-- board/freescale/t208xqds/tlb.c | 8 +-- board/freescale/t208xrdb/tlb.c | 8 +-- include/configs/MPC8548CDS.h | 8 +-- include/configs/P2041RDB.h | 46 ++++++++-------- include/configs/T102xRDB.h | 38 +++++++------- include/configs/T208xQDS.h | 42 +++++++-------- include/configs/T208xRDB.h | 42 +++++++-------- 10 files changed, 146 insertions(+), 146 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index dd274166c0..35409dc882 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -309,42 +309,42 @@ void init_laws(void) */ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) { case 0x0: /* boot from PCIE1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1); break; case 0x1: /* boot from PCIE2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2); break; case 0x2: /* boot from PCIE3 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_3); break; case 0x8: /* boot from SRIO1 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1); break; case 0x9: /* boot from SRIO2 */ - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); - set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2); break; diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c815d19384..dc1bc0db42 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -240,8 +240,8 @@ void srio_init(void) devdisr = &gur->devdisr; #endif if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE), + set_next_law(CFG_SYS_SRIO1_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO1_MEM_SIZE), LAW_TRGT_IF_RIO_1); srio1_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -256,8 +256,8 @@ void srio_init(void) #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS, - law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE), + set_next_law(CFG_SYS_SRIO2_MEM_PHYS, + law_size_bits(CFG_SYS_SRIO2_MEM_SIZE), LAW_TRGT_IF_RIO_2); srio2_used = 1; #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 @@ -301,44 +301,44 @@ void srio_boot_master(int port) /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's u-boot image */ debug("SRIOBOOT - MASTER: Inbound window for slave's image; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, - CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2, + CFG_SRIO_PCIE_BOOT_IMAGE_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar, - CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); + CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE)); /* configure inbound window for slave's ucode and ENV */ debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; " "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, - (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS, + (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS, + CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar, - CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); + CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12); out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar, SRIO_IB_ATMU_AR - | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); + | atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)); } void srio_boot_master_release_slave(int port) @@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + CFG_SYS_SRIO2_MEM_PHYS >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowbar, - CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + CFG_SYS_SRIO1_MEM_PHYS >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[1].rowar, SRIO_OB_ATMU_AR_MAINT @@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port) if (port - 1) out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO2_MEM_PHYS + (CFG_SYS_SRIO2_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); else out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowbar, - (CONFIG_SYS_SRIO1_MEM_PHYS + (CFG_SYS_SRIO1_MEM_PHYS + SRIO_MAINT_WIN_SIZE) >> 12); out_be32((void *)&srio->atmu.port[port - 1] .outbw[2].rowar, @@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port) * by the maint-outbound window */ if (port - 1) { - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } else { - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET, SRIO_LCSBA1CSR); - while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_LCSBA1CSR_OFFSET) != SRIO_LCSBA1CSR) ; @@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port) * And then set the BRR register * to release slave core */ - out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT + out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT + SRIO_MAINT_WIN_SIZE - + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET, - CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK); + + CFG_SRIO_PCIE_BOOT_BRR_OFFSET, + CFG_SRIO_PCIE_BOOT_RELEASE_MASK); } debug("SRIOBOOT - MASTER: " "Release slave successfully! Now the slave should start up!\n"); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 4cdef89bf0..7302b76066 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -69,8 +69,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -150,8 +150,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 17, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index 9160674b94..f2448e86c0 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 69e58e7e97..45c27c0812 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the * space is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else @@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for * fetching ucode and ENV from master */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 18, BOOKE_PAGESZ_1M, 1), #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index eb75f8b37d..25b4fe0c7d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -282,13 +282,13 @@ /* * RapidIO MMU */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #if defined(CONFIG_TSEC_ENET) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index be8d09f6dd..c3ef216333 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -18,9 +18,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -173,49 +173,49 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull #else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000 #endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index f9f9318448..b567b63980 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -53,40 +53,40 @@ * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 #endif /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull #else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 #endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* PCIe Boot - Slave */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) /* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index acaad1bfc8..798822e503 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -49,9 +49,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -295,39 +295,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 7315afa39f..ea366b671c 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -49,9 +49,9 @@ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) +#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -254,39 +254,39 @@ /* * RapidIO */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ /* * for slave u-boot IMAGE instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull +#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ +#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull /* * for slave UCODE and ENV instored in master memory space, * PHYS must be aligned based on the SIZE */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ /* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ +#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ /* * SRIO_PCIE_BOOT - SLAVE */ #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) #endif /* From 65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 16 Nov 2022 13:10:41 -0500 Subject: [PATCH 027/424] global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .checkpatch.conf | 2 +- Kconfig | 6 +- Makefile | 16 +- README | 66 +-- arch/arm/cpu/arm1176/start.S | 2 +- arch/arm/cpu/arm926ejs/start.S | 2 +- arch/arm/cpu/armv7/arch_timer.c | 6 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 4 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 4 +- arch/arm/cpu/armv7/stv0991/timer.c | 4 +- arch/arm/cpu/armv7m/systick-timer.c | 8 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 54 +-- .../cpu/armv8/fsl-layerscape/doc/README.lsch3 | 4 +- .../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 +- .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 +- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- arch/arm/cpu/armv8/sec_firmware.c | 4 +- .../include/asm/arch-fsl-layerscape/config.h | 36 +- .../asm/arch-fsl-layerscape/fsl_icid.h | 4 +- .../asm/arch-fsl-layerscape/immap_lsch2.h | 78 ++-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 10 +- arch/arm/include/asm/arch-lpc32xx/config.h | 4 +- arch/arm/include/asm/arch-ls102xa/config.h | 22 +- .../include/asm/arch-ls102xa/immap_ls102xa.h | 18 +- .../asm/arch-ls102xa/ls102xa_stream_id.h | 4 +- arch/arm/include/asm/arch-mx31/imx-regs.h | 4 +- .../include/asm/arch-stv0991/stv0991_gpt.h | 2 +- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- arch/arm/include/asm/global_data.h | 2 +- arch/arm/lib/bdinfo.c | 2 +- arch/arm/lib/cache-pl310.c | 2 +- arch/arm/lib/cache.c | 2 +- arch/arm/lib/vectors.S | 4 +- arch/arm/mach-at91/arm920t/clock.c | 6 +- arch/arm/mach-at91/arm920t/cpu.c | 6 +- arch/arm/mach-at91/arm920t/lowlevel_init.S | 18 +- arch/arm/mach-at91/arm920t/timer.c | 4 +- arch/arm/mach-at91/arm926ejs/clock.c | 6 +- arch/arm/mach-at91/arm926ejs/cpu.c | 6 +- arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 54 +-- arch/arm/mach-at91/armv7/clock.c | 8 +- arch/arm/mach-at91/armv7/cpu.c | 6 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9261.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9263.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9rl.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +- arch/arm/mach-at91/include/mach/sam9x60.h | 2 +- arch/arm/mach-at91/include/mach/sama5d2.h | 2 +- arch/arm/mach-at91/include/mach/sama5d3.h | 2 +- arch/arm/mach-at91/include/mach/sama5d4.h | 2 +- arch/arm/mach-at91/spl_at91.c | 12 +- arch/arm/mach-at91/spl_atmel.c | 2 +- arch/arm/mach-davinci/cpu.c | 2 +- arch/arm/mach-davinci/da850_lowlevel.c | 24 +- arch/arm/mach-davinci/timer.c | 4 +- arch/arm/mach-exynos/spl_boot.c | 2 +- arch/arm/mach-imx/image-container.c | 8 +- arch/arm/mach-imx/mx5/lowlevel_init.S | 10 +- arch/arm/mach-k3/config_secure.mk | 2 +- arch/arm/mach-keystone/cmd_mon.c | 2 +- .../arm/mach-keystone/include/mach/hardware.h | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 4 +- .../mach-kirkwood/include/mach/kw88f6192.h | 2 +- .../mach-kirkwood/include/mach/kw88f6281.h | 2 +- arch/arm/mach-mvebu/cpu.c | 4 +- arch/arm/mach-mvebu/include/mach/soc.h | 10 +- arch/arm/mach-mvebu/lowlevel.S | 4 +- arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c | 2 +- arch/arm/mach-omap2/config_secure.mk | 2 +- arch/arm/mach-omap2/mem-common.c | 12 +- arch/arm/mach-omap2/timer.c | 2 +- .../arm/mach-orion5x/include/mach/mv88f5182.h | 2 +- arch/arm/mach-orion5x/timer.c | 6 +- arch/arm/mach-rmobile/include/mach/r8a7790.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7791.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7792.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7793.h | 2 +- arch/arm/mach-rmobile/include/mach/r8a7794.h | 2 +- arch/arm/mach-rmobile/timer.c | 8 +- arch/arm/mach-socfpga/misc.c | 2 +- arch/arm/mach-socfpga/misc_arria10.c | 4 +- arch/arm/mach-socfpga/misc_gen5.c | 2 +- arch/arm/mach-socfpga/spl_a10.c | 2 +- arch/arm/mach-socfpga/timer.c | 2 +- arch/arm/mach-u8500/cache.c | 2 +- arch/arm/mach-uniphier/arm32/timer.c | 2 +- arch/arm/mach-versatile/timer.c | 8 +- arch/m68k/cpu/mcf523x/cpu.c | 2 +- arch/m68k/cpu/mcf523x/cpu_init.c | 38 +- arch/m68k/cpu/mcf523x/speed.c | 2 +- arch/m68k/cpu/mcf523x/start.S | 6 +- arch/m68k/cpu/mcf52x2/cpu.c | 10 +- arch/m68k/cpu/mcf52x2/cpu_init.c | 110 ++--- arch/m68k/cpu/mcf52x2/speed.c | 14 +- arch/m68k/cpu/mcf52x2/start.S | 48 +- arch/m68k/cpu/mcf530x/cpu.c | 2 +- arch/m68k/cpu/mcf530x/cpu_init.c | 48 +- arch/m68k/cpu/mcf530x/speed.c | 4 +- arch/m68k/cpu/mcf530x/start.S | 10 +- arch/m68k/cpu/mcf532x/cpu.c | 2 +- arch/m68k/cpu/mcf532x/cpu_init.c | 86 ++-- arch/m68k/cpu/mcf532x/speed.c | 2 +- arch/m68k/cpu/mcf532x/start.S | 6 +- arch/m68k/cpu/mcf5445x/cpu_init.c | 38 +- arch/m68k/cpu/mcf5445x/start.S | 46 +- arch/m68k/include/asm/cache.h | 24 +- arch/m68k/include/asm/immap.h | 32 +- arch/m68k/include/asm/immap_520x.h | 52 +-- arch/m68k/include/asm/immap_5235.h | 72 +-- arch/m68k/include/asm/immap_5249.h | 14 +- arch/m68k/include/asm/immap_5253.h | 26 +- arch/m68k/include/asm/immap_5271.h | 72 +-- arch/m68k/include/asm/immap_5272.h | 36 +- arch/m68k/include/asm/immap_5275.h | 76 +-- arch/m68k/include/asm/immap_5282.h | 72 +-- arch/m68k/include/asm/immap_5301x.h | 80 ++-- arch/m68k/include/asm/immap_5307.h | 18 +- arch/m68k/include/asm/m5249.h | 16 +- arch/m68k/include/asm/m5271.h | 12 +- arch/m68k/include/asm/m5282.h | 374 +++++++-------- arch/m68k/lib/bdinfo.c | 4 +- arch/m68k/lib/cache.c | 24 +- arch/mips/mach-mtmips/mt7621/spl/start.S | 2 +- arch/powerpc/cpu/mpc83xx/cpu_init.c | 46 +- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 14 +- arch/powerpc/cpu/mpc83xx/spl_minimal.c | 8 +- arch/powerpc/cpu/mpc83xx/start.S | 48 +- arch/powerpc/cpu/mpc83xx/sysio/sysio.h | 8 +- arch/powerpc/cpu/mpc85xx/b4860_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +- arch/powerpc/cpu/mpc85xx/cpu.c | 18 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 52 +-- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 22 +- arch/powerpc/cpu/mpc85xx/fdt.c | 32 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 14 +- arch/powerpc/cpu/mpc85xx/p2041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p3041_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/p5040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/release.S | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 42 +- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 +- arch/powerpc/cpu/mpc85xx/start.S | 130 +++--- arch/powerpc/cpu/mpc85xx/t1024_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t1040_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t2080_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 8 +- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 +- arch/powerpc/cpu/mpc8xx/start.S | 4 +- arch/powerpc/cpu/mpc8xxx/fsl_pamu.c | 8 +- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 8 +- arch/powerpc/include/asm/config_mpc85xx.h | 42 +- arch/powerpc/include/asm/fsl_lbc.h | 2 +- arch/powerpc/include/asm/fsl_liodn.h | 18 +- arch/powerpc/include/asm/fsl_secure_boot.h | 20 +- arch/powerpc/include/asm/immap_83xx.h | 10 +- arch/powerpc/include/asm/immap_85xx.h | 44 +- arch/powerpc/lib/spl.c | 2 +- arch/sh/include/asm/config.h | 4 +- arch/x86/lib/physmem.c | 2 +- arch/xtensa/include/asm/addrspace.h | 4 +- board/BuS/eb_cpu5282/eb_cpu5282.c | 6 +- board/LaCie/net2big_v2/net2big_v2.c | 12 +- board/Synology/common/legacy.c | 4 +- board/armltd/integrator/timer.c | 14 +- board/armltd/vexpress64/vexpress64.c | 4 +- board/cadence/xtfpga/xtfpga.c | 10 +- board/cavium/thunderx/atf.c | 2 +- board/cavium/thunderx/thunderx.c | 4 +- board/cobra5272/flash.c | 10 +- board/cortina/presidio-asic/lowlevel_init.S | 2 +- board/cortina/presidio-asic/presidio.c | 2 +- board/davinci/da8xxevm/da850evm.c | 16 +- board/egnite/ethernut5/ethernut5.c | 2 +- board/emulation/qemu-ppce500/qemu-ppce500.c | 6 +- board/esd/meesc/meesc.c | 2 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/common/fsl_validate.c | 14 +- board/freescale/common/p_corenet/law.c | 14 +- board/freescale/common/p_corenet/tlb.c | 48 +- board/freescale/common/qixis.c | 10 +- board/freescale/common/qixis.h | 6 +- board/freescale/ls1012aqds/ls1012aqds.c | 4 +- board/freescale/ls1021aqds/ls1021aqds.c | 2 +- board/freescale/ls1021atwr/ls1021atwr.c | 12 +- board/freescale/ls1043aqds/ls1043aqds.c | 48 +- board/freescale/ls1043ardb/cpld.c | 4 +- board/freescale/ls1043ardb/ls1043ardb.c | 32 +- board/freescale/ls1046aqds/ls1046aqds.c | 48 +- board/freescale/ls1046ardb/cpld.c | 4 +- board/freescale/ls1088a/ls1088a.c | 30 +- board/freescale/ls2080aqds/README | 4 +- board/freescale/ls2080aqds/ls2080aqds.c | 2 +- board/freescale/lx2160a/lx2160a.c | 6 +- board/freescale/m5249evb/m5249evb.c | 6 +- board/freescale/m5253demo/flash.c | 18 +- board/freescale/m5253demo/m5253demo.c | 4 +- board/freescale/m53017evb/README | 6 +- board/freescale/m5329evb/nand.c | 2 +- board/freescale/m5373evb/README | 6 +- board/freescale/m5373evb/nand.c | 2 +- board/freescale/mpc837xerdb/mpc837xerdb.c | 28 +- board/freescale/mpc8548cds/law.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 12 +- board/freescale/mpc8548cds/tlb.c | 16 +- board/freescale/mx53loco/mx53loco.c | 4 +- board/freescale/p1010rdb/law.c | 4 +- board/freescale/p1010rdb/p1010rdb.c | 14 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/tlb.c | 30 +- board/freescale/p1_p2_rdb_pc/ddr.c | 56 +-- board/freescale/p1_p2_rdb_pc/law.c | 6 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 22 +- board/freescale/p1_p2_rdb_pc/tlb.c | 38 +- board/freescale/p2041rdb/eth.c | 24 +- board/freescale/p2041rdb/p2041rdb.c | 4 +- board/freescale/t102xrdb/cpld.c | 4 +- board/freescale/t102xrdb/ddr.c | 2 +- board/freescale/t102xrdb/law.c | 18 +- board/freescale/t102xrdb/t102xrdb.c | 6 +- board/freescale/t102xrdb/tlb.c | 54 +-- board/freescale/t104xrdb/cpld.c | 6 +- board/freescale/t104xrdb/ddr.c | 2 +- board/freescale/t104xrdb/eth.c | 18 +- board/freescale/t104xrdb/law.c | 18 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 6 +- board/freescale/t104xrdb/tlb.c | 58 +-- board/freescale/t208xqds/law.c | 14 +- board/freescale/t208xqds/t208xqds.c | 4 +- board/freescale/t208xqds/tlb.c | 46 +- board/freescale/t208xrdb/cpld.c | 4 +- board/freescale/t208xrdb/law.c | 18 +- board/freescale/t208xrdb/t208xrdb.c | 4 +- board/freescale/t208xrdb/tlb.c | 50 +- board/freescale/t4rdb/cpld.c | 6 +- board/freescale/t4rdb/law.c | 18 +- board/freescale/t4rdb/t4240rdb.c | 4 +- board/freescale/t4rdb/tlb.c | 50 +- board/gdsys/mpc8308/sdram.c | 24 +- board/isee/igep00x0/igep00x0.c | 2 +- board/keymile/common/qrio.c | 36 +- board/keymile/km83xx/km83xx.c | 30 +- board/keymile/kmcent2/kmcent2.c | 6 +- board/keymile/kmcent2/law.c | 10 +- board/keymile/kmcent2/tlb.c | 40 +- .../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 2 +- board/nokia/rx51/rx51.c | 2 +- board/samsung/goni/onenand.c | 2 +- board/samsung/universal_c210/onenand.c | 2 +- board/siemens/smartweb/smartweb.c | 2 +- board/siemens/taurus/taurus.c | 2 +- board/socrates/law.c | 10 +- board/socrates/sdram.c | 22 +- board/socrates/socrates.c | 10 +- board/socrates/tlb.c | 22 +- board/sysam/amcore/amcore.c | 2 +- board/ti/ks2_evm/board.c | 8 +- board/ti/omap5_uevm/evm.c | 2 +- board/xes/common/fsl_8xxx_misc.c | 4 +- boot/Kconfig | 2 +- boot/image-board.c | 4 +- cmd/date.c | 4 +- cmd/i2c.c | 16 +- common/board_f.c | 4 +- common/board_r.c | 8 +- common/spl/Kconfig.nxp | 4 +- common/spl/spl.c | 6 +- common/spl/spl_fit.c | 2 +- common/spl/spl_nor.c | 2 +- common/spl/spl_spi.c | 8 +- common/spl/spl_ubi.c | 2 +- common/spl/spl_xip.c | 2 +- doc/README.atmel_mci | 4 +- doc/README.cfi | 4 +- doc/README.davinci | 2 +- doc/README.generic_usb_ohci | 2 +- doc/README.mpc85xx | 16 +- doc/README.nand | 2 +- doc/README.serial_multi | 2 +- doc/arch/m68k.rst | 18 +- doc/develop/driver-model/migration.rst | 2 +- doc/device-tree-bindings/video/exynos-dp.txt | 4 +- doc/device-tree-bindings/video/exynos-fb.txt | 10 +- doc/imx/common/imx5.txt | 2 +- doc/usage/environment.rst | 6 +- drivers/bootcount/Kconfig | 2 +- drivers/bootcount/bootcount_i2c.c | 4 +- drivers/clk/at91/compat.c | 2 +- drivers/core/Kconfig | 6 +- drivers/ddr/fsl/main.c | 4 +- drivers/fpga/ACEX1K.c | 6 +- drivers/fpga/cyclon2.c | 6 +- drivers/fpga/spartan2.c | 16 +- drivers/fpga/spartan3.c | 16 +- drivers/fpga/virtex2.c | 28 +- drivers/fpga/zynqpl.c | 14 +- drivers/gpio/pca953x.c | 10 +- drivers/gpio/tca642x.c | 6 +- drivers/i2c/davinci_i2c.c | 2 +- drivers/i2c/fsl_i2c.c | 2 +- drivers/i2c/i2c_core.c | 6 +- drivers/i2c/kona_i2c.c | 2 +- drivers/i2c/mvtwsi.c | 6 +- drivers/i2c/mxc_i2c.c | 4 +- drivers/misc/fsl_ifc.c | 438 +++++++++--------- drivers/misc/fsl_portals.c | 28 +- drivers/misc/fsl_sec_mon.c | 6 +- drivers/mmc/fsl_esdhc_spl.c | 18 +- drivers/mmc/gen_atmel_mci.c | 8 +- drivers/mmc/sh_sdhi.c | 2 +- drivers/mtd/cfi_flash.c | 32 +- drivers/mtd/nand/raw/fsl_ifc_nand.c | 4 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 8 +- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 6 +- drivers/mtd/onenand/onenand_spl.c | 6 +- drivers/mtd/onenand/onenand_uboot.c | 2 +- drivers/mtd/spi/fsl_espi_spl.c | 12 +- drivers/mtd/stm32_flash.c | 2 +- drivers/net/fm/eth.c | 2 +- drivers/net/fm/fm.c | 4 +- drivers/net/fm/init.c | 4 +- drivers/net/fsl-mc/dpio/qbman_sys.h | 4 +- drivers/net/fsl-mc/mc.c | 48 +- drivers/net/fsl_mcdmafec.c | 26 +- drivers/net/mcffec.c | 8 +- drivers/net/qe/uec.h | 14 +- drivers/net/tsec.c | 4 +- drivers/net/vsc7385.c | 12 +- drivers/power/power_dialog.c | 2 +- drivers/qe/uec.h | 14 +- drivers/qe/uec_phy.c | 10 +- drivers/rtc/ds1307.c | 8 +- drivers/rtc/ds1337.c | 4 +- drivers/rtc/ds1374.c | 16 +- drivers/rtc/ds3231.c | 4 +- drivers/rtc/m41t62.c | 10 +- drivers/rtc/max6900.c | 8 +- drivers/rtc/pcf8563.c | 4 +- drivers/rtc/pt7c4338.c | 4 +- drivers/rtc/rs5c372.c | 12 +- drivers/rtc/rx8010sj.c | 12 +- drivers/rtc/x1205.c | 4 +- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 4 +- drivers/spi/davinci_spi.c | 4 +- drivers/spi/kirkwood_spi.c | 4 +- drivers/sysreset/sysreset_xtfpga.c | 4 +- drivers/timer/arm_global_timer.c | 2 +- drivers/timer/imx-gpt-timer.c | 10 +- drivers/timer/orion-timer.c | 4 +- drivers/timer/stm32_timer.c | 4 +- drivers/usb/host/ohci-hcd.c | 2 +- drivers/video/imx/ipu_common.c | 6 +- env/Kconfig | 2 +- env/embedded.c | 2 +- include/config_fallbacks.h | 4 +- include/configs/M5208EVBE.h | 42 +- include/configs/M5235EVB.h | 52 +-- include/configs/M5249EVB.h | 66 +-- include/configs/M5253DEMO.h | 84 ++-- include/configs/M5272C3.h | 48 +- include/configs/M5275EVB.h | 48 +- include/configs/M5282EVB.h | 68 +-- include/configs/M53017EVB.h | 54 +-- include/configs/M5329EVB.h | 56 +-- include/configs/M5373EVB.h | 56 +-- include/configs/MCR3000.h | 8 +- include/configs/MPC837XERDB.h | 60 +-- include/configs/MPC8548CDS.h | 58 +-- include/configs/P1010RDB.h | 146 +++--- include/configs/P2041RDB.h | 132 +++--- include/configs/SBx81LIFKW.h | 4 +- include/configs/SBx81LIFXCAT.h | 4 +- include/configs/T102xRDB.h | 209 ++++----- include/configs/T104xRDB.h | 228 ++++----- include/configs/T208xQDS.h | 226 ++++----- include/configs/T208xRDB.h | 192 ++++---- include/configs/T4240RDB.h | 206 ++++---- include/configs/am335x_evm.h | 4 +- include/configs/am3517_evm.h | 2 +- include/configs/am43xx_evm.h | 4 +- include/configs/am57xx_evm.h | 6 +- include/configs/amcore.h | 44 +- include/configs/ap121.h | 4 +- include/configs/ap143.h | 4 +- include/configs/ap152.h | 4 +- include/configs/apalis_imx6.h | 4 +- include/configs/arbel.h | 6 +- include/configs/aristainetos2.h | 6 +- include/configs/aspeed-common.h | 8 +- include/configs/astro_mcf5373l.h | 68 +-- include/configs/at91-sama5_common.h | 4 +- include/configs/at91sam9260ek.h | 12 +- include/configs/at91sam9261ek.h | 10 +- include/configs/at91sam9263ek.h | 56 +-- include/configs/at91sam9m10g45ek.h | 12 +- include/configs/at91sam9n12ek.h | 12 +- include/configs/at91sam9rlek.h | 8 +- include/configs/at91sam9x5ek.h | 12 +- include/configs/ax25-ae350.h | 8 +- include/configs/axs10x.h | 4 +- include/configs/bcm7260.h | 2 +- include/configs/bcm7445.h | 2 +- include/configs/bcm963138.h | 2 +- include/configs/bcmstb.h | 4 +- include/configs/bk4r1.h | 4 +- include/configs/blanche.h | 8 +- include/configs/bmips_bcm3380.h | 2 +- include/configs/bmips_bcm6318.h | 2 +- include/configs/bmips_bcm63268.h | 2 +- include/configs/bmips_bcm6328.h | 2 +- include/configs/bmips_bcm6338.h | 4 +- include/configs/bmips_bcm6348.h | 4 +- include/configs/bmips_bcm6358.h | 4 +- include/configs/bmips_bcm6362.h | 2 +- include/configs/bmips_bcm6368.h | 4 +- include/configs/bmips_bcm6838.h | 2 +- include/configs/bmips_common.h | 2 +- include/configs/boston.h | 2 +- include/configs/brppt2.h | 6 +- include/configs/bur_am335x_common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/ci20.h | 2 +- include/configs/cl-som-imx7.h | 8 +- include/configs/cm_fx6.h | 6 +- include/configs/cm_t43.h | 4 +- include/configs/cobra5272.h | 48 +- include/configs/colibri-imx6ull.h | 4 +- include/configs/colibri_imx6.h | 4 +- include/configs/colibri_imx7.h | 4 +- include/configs/colibri_vf.h | 4 +- include/configs/corvus.h | 12 +- include/configs/da850evm.h | 36 +- include/configs/dart_6ul.h | 4 +- include/configs/devkit3250.h | 4 +- include/configs/dh_imx6.h | 4 +- include/configs/display5.h | 10 +- include/configs/dra7xx_evm.h | 10 +- include/configs/draak.h | 4 +- include/configs/dragonboard845c.h | 2 +- include/configs/eb_cpu5282.h | 86 ++-- include/configs/ebisu.h | 4 +- include/configs/edison.h | 2 +- include/configs/el6x_common.h | 4 +- include/configs/embestmx6boards.h | 4 +- include/configs/etamin.h | 2 +- include/configs/ethernut5.h | 16 +- include/configs/evb_ast2500.h | 2 +- include/configs/evb_ast2600.h | 2 +- include/configs/exynos5-dt-common.h | 2 +- include/configs/exynos78x0-common.h | 2 +- .../configs/gardena-smart-gateway-at91sam.h | 12 +- .../configs/gardena-smart-gateway-mt7688.h | 8 +- include/configs/gazerbeam.h | 14 +- include/configs/ge_b1x5v2.h | 4 +- include/configs/ge_bx50v3.h | 6 +- include/configs/gw_ventana.h | 4 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 4 +- include/configs/hsdk.h | 4 +- include/configs/imx27lite-common.h | 2 +- include/configs/imx6-engicam.h | 4 +- include/configs/imx6_logic.h | 4 +- include/configs/imx6dl-mamoj.h | 4 +- include/configs/imx6q-bosch-acc.h | 4 +- include/configs/imx6ulz_smm_m2.h | 4 +- include/configs/imx7-cm.h | 4 +- include/configs/imx8mm-cl-iot-gate.h | 6 +- include/configs/imx8mm_beacon.h | 6 +- include/configs/imx8mm_data_modul_edm_sbc.h | 4 +- include/configs/imx8mm_evk.h | 8 +- include/configs/imx8mm_icore_mx8mm.h | 6 +- include/configs/imx8mm_venice.h | 6 +- include/configs/imx8mn_beacon.h | 6 +- include/configs/imx8mn_bsh_smm_s2_common.h | 6 +- include/configs/imx8mn_evk.h | 6 +- include/configs/imx8mn_var_som.h | 6 +- include/configs/imx8mn_venice.h | 6 +- include/configs/imx8mp_dhcom_pdk2.h | 4 +- include/configs/imx8mp_evk.h | 6 +- include/configs/imx8mp_icore_mx8mp.h | 6 +- include/configs/imx8mp_rsb3720.h | 6 +- include/configs/imx8mp_venice.h | 6 +- include/configs/imx8mq_cm.h | 4 +- include/configs/imx8mq_evk.h | 4 +- include/configs/imx8mq_phanbell.h | 4 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8ulp_evk.h | 6 +- include/configs/imx93_evk.h | 6 +- include/configs/imxrt1020-evk.h | 2 +- include/configs/imxrt1050-evk.h | 2 +- include/configs/imxrt1170-evk.h | 2 +- include/configs/integrator-common.h | 4 +- include/configs/integratorap.h | 4 +- include/configs/integratorcp.h | 2 +- include/configs/j721e_evm.h | 6 +- include/configs/j721s2_evm.h | 4 +- include/configs/km/keymile-common.h | 2 +- include/configs/km/km-mpc832x.h | 32 +- include/configs/km/km-mpc8360.h | 32 +- include/configs/km/km-mpc83xx.h | 20 +- include/configs/km/pg-wcom-ls102xa.h | 86 ++-- include/configs/kmcent2.h | 204 ++++---- include/configs/kmcoge5ne.h | 6 +- include/configs/kmeter1.h | 2 +- include/configs/kontron-sl-mx6ul.h | 6 +- include/configs/kontron-sl-mx8mm.h | 4 +- include/configs/kontron_pitx_imx8m.h | 4 +- include/configs/kontron_sl28.h | 8 +- include/configs/kp_imx53.h | 4 +- include/configs/kp_imx6q_tpc.h | 4 +- include/configs/lacie_kw.h | 2 +- include/configs/legoev3.h | 10 +- include/configs/librem5.h | 4 +- include/configs/linkit-smart-7688.h | 8 +- include/configs/liteboard.h | 4 +- include/configs/ls1012a_common.h | 6 +- include/configs/ls1012aqds.h | 4 +- include/configs/ls1021aiot.h | 10 +- include/configs/ls1021aqds.h | 174 +++---- include/configs/ls1021atsn.h | 10 +- include/configs/ls1021atwr.h | 74 +-- include/configs/ls1028a_common.h | 6 +- include/configs/ls1028aqds.h | 12 +- include/configs/ls1028ardb.h | 10 +- include/configs/ls1043a_common.h | 20 +- include/configs/ls1043aqds.h | 224 ++++----- include/configs/ls1043ardb.h | 140 +++--- include/configs/ls1046a_common.h | 8 +- include/configs/ls1046afrwy.h | 22 +- include/configs/ls1046aqds.h | 236 +++++----- include/configs/ls1046ardb.h | 54 +-- include/configs/ls1088a_common.h | 36 +- include/configs/ls1088aqds.h | 216 ++++----- include/configs/ls1088ardb.h | 80 ++-- include/configs/ls2080a_common.h | 36 +- include/configs/ls2080aqds.h | 158 +++---- include/configs/ls2080ardb.h | 110 ++--- include/configs/lx2160a_common.h | 40 +- include/configs/lx2160aqds.h | 2 +- include/configs/lx2160ardb.h | 2 +- include/configs/lx2162aqds.h | 2 +- include/configs/m53menlo.h | 10 +- include/configs/malta.h | 6 +- include/configs/mccmon6.h | 14 +- include/configs/meerkat96.h | 4 +- include/configs/meesc.h | 8 +- include/configs/microblaze-generic.h | 4 +- include/configs/msc_sm2s_imx8mp.h | 6 +- include/configs/mt7620.h | 6 +- include/configs/mt7621.h | 6 +- include/configs/mt7622.h | 4 +- include/configs/mt7628.h | 8 +- include/configs/mt7629.h | 2 +- include/configs/mt7981.h | 4 +- include/configs/mt7986.h | 4 +- include/configs/mt8512.h | 2 +- include/configs/mv-common.h | 6 +- include/configs/mvebu_alleycat-5.h | 4 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 4 +- include/configs/mx51evk.h | 10 +- include/configs/mx53cx9020.h | 4 +- include/configs/mx53loco.h | 6 +- include/configs/mx53ppd.h | 6 +- include/configs/mx6_common.h | 2 +- include/configs/mx6cuboxi.h | 4 +- include/configs/mx6memcal.h | 4 +- include/configs/mx6sabre_common.h | 4 +- include/configs/mx6sabreauto.h | 4 +- include/configs/mx6slevk.h | 4 +- include/configs/mx6sllevk.h | 4 +- include/configs/mx6sxsabreauto.h | 4 +- include/configs/mx6sxsabresd.h | 4 +- include/configs/mx6ul_14x14_evk.h | 4 +- include/configs/mx6ullevk.h | 4 +- include/configs/mx7dsabresd.h | 4 +- include/configs/mx7ulp_com.h | 6 +- include/configs/mx7ulp_evk.h | 6 +- include/configs/mxs.h | 6 +- include/configs/mys_6ulx.h | 4 +- include/configs/nitrogen6x.h | 4 +- include/configs/nokia_rx51.h | 10 +- include/configs/novena.h | 4 +- include/configs/npi_imx6ull.h | 4 +- include/configs/nsim.h | 4 +- include/configs/o4-imx6ull-nano.h | 4 +- include/configs/octeon_common.h | 4 +- include/configs/odroid.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_igep00x0.h | 4 +- include/configs/omap3_logic.h | 4 +- include/configs/omap5_uevm.h | 4 +- include/configs/omapl138_lcdk.h | 32 +- include/configs/opos6uldev.h | 4 +- include/configs/p1_p2_bootsrc.h | 6 +- include/configs/p1_p2_rdb_pc.h | 158 +++---- include/configs/pcl063.h | 4 +- include/configs/pcl063_ull.h | 4 +- include/configs/pcm052.h | 4 +- include/configs/pcm058.h | 4 +- include/configs/pg-wcom-expu1.h | 16 +- include/configs/pg-wcom-seli8.h | 16 +- include/configs/phycore_imx8mm.h | 6 +- include/configs/phycore_imx8mp.h | 6 +- include/configs/pic32mzdask.h | 6 +- include/configs/pico-imx6.h | 4 +- include/configs/pico-imx6ul.h | 4 +- include/configs/pico-imx7d.h | 4 +- include/configs/pico-imx8mq.h | 4 +- include/configs/pm9261.h | 52 +-- include/configs/pm9263.h | 56 +-- include/configs/pm9g45.h | 12 +- include/configs/poleg.h | 4 +- include/configs/presidio_asic.h | 16 +- include/configs/qcs404-evb.h | 2 +- include/configs/qemu-ppce500.h | 34 +- include/configs/r2dplus.h | 6 +- include/configs/rcar-gen2-common.h | 6 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rpi.h | 6 +- include/configs/rv1108_common.h | 6 +- include/configs/s5p_goni.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/salvator-x.h | 4 +- include/configs/sam9x60_curiosity.h | 4 +- include/configs/sam9x60ek.h | 4 +- include/configs/sama5d27_som1_ek.h | 4 +- include/configs/sama5d27_wlsom1_ek.h | 4 +- include/configs/sama5d2_icp.h | 4 +- include/configs/sama5d2_ptc_ek.h | 4 +- include/configs/sama5d3xek.h | 2 +- include/configs/sama7g5ek.h | 4 +- include/configs/sandbox.h | 2 +- include/configs/sdm845.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/smartweb.h | 18 +- include/configs/smdkc100.h | 2 +- include/configs/smegw01.h | 4 +- include/configs/snapper9g45.h | 8 +- include/configs/sniper.h | 4 +- include/configs/socfpga_arria10_socdk.h | 2 +- include/configs/socfpga_arria5_secu1.h | 4 +- include/configs/socfpga_chameleonv3.h | 2 +- include/configs/socfpga_common.h | 24 +- include/configs/socfpga_soc64_common.h | 4 +- include/configs/socrates.h | 66 +-- include/configs/somlabs_visionsom_6ull.h | 4 +- include/configs/stemmy.h | 2 +- include/configs/stih410-b2260.h | 4 +- include/configs/stm32f429-discovery.h | 4 +- include/configs/stm32f429-evaluation.h | 6 +- include/configs/stm32f469-discovery.h | 6 +- include/configs/stm32f746-disco.h | 8 +- include/configs/stm32h743-disco.h | 6 +- include/configs/stm32h743-eval.h | 6 +- include/configs/stm32h750-art-pi.h | 6 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp13_st_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stm32mp15_st_common.h | 2 +- include/configs/stmark2.h | 42 +- include/configs/stv0991.h | 6 +- include/configs/sunxi-common.h | 4 +- include/configs/synquacer.h | 8 +- include/configs/taurus.h | 18 +- include/configs/tb100.h | 4 +- include/configs/tbs2910.h | 6 +- include/configs/tegra-common.h | 10 +- include/configs/ten64.h | 2 +- include/configs/thunderx_88xx.h | 6 +- include/configs/ti814x_evm.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 8 +- include/configs/ti_omap3_common.h | 4 +- include/configs/ti_omap4_common.h | 4 +- include/configs/ti_omap5_common.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/tplink_wdr4300.h | 4 +- include/configs/tqma6.h | 4 +- include/configs/tqma6_wru4.h | 4 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- include/configs/turris_mox.h | 2 +- include/configs/udoo.h | 4 +- include/configs/udoo_neo.h | 4 +- include/configs/ulcb.h | 4 +- include/configs/uniphier.h | 6 +- include/configs/usb_a9263.h | 8 +- include/configs/usbarmory.h | 4 +- include/configs/vcoreiii.h | 2 +- include/configs/verdin-imx8mm.h | 6 +- include/configs/verdin-imx8mp.h | 6 +- include/configs/vexpress_aemv8.h | 4 +- include/configs/vexpress_common.h | 18 +- include/configs/vf610twr.h | 4 +- include/configs/vinco.h | 4 +- include/configs/vining_2000.h | 4 +- include/configs/vocore2.h | 6 +- include/configs/wandboard.h | 4 +- include/configs/warp7.h | 4 +- include/configs/work_92105.h | 2 +- include/configs/x530.h | 2 +- include/configs/x86-common.h | 2 +- include/configs/xea.h | 6 +- include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_versal_net.h | 2 +- include/configs/xilinx_zynqmp.h | 8 +- include/configs/xilinx_zynqmp_r5.h | 6 +- include/configs/xpress.h | 4 +- include/configs/xtfpga.h | 40 +- include/configs/zynq-common.h | 20 +- include/configs/zynq_cse.h | 8 +- include/fsl-mc/fsl_mc.h | 2 +- include/fsl_ifc.h | 2 +- include/i2c.h | 16 +- include/mpc85xx.h | 34 +- include/mpc86xx.h | 6 +- include/mtd/cfi_flash.h | 4 +- include/mvebu_mmc.h | 2 +- include/post.h | 4 +- include/spl.h | 2 +- include/system-constants.h | 4 +- include/tca642x.h | 8 +- include/tsec.h | 4 +- lib/time.c | 14 +- post/drivers/memory.c | 4 +- post/tests.c | 8 +- tools/envcrc.c | 6 +- 744 files changed, 5915 insertions(+), 5914 deletions(-) diff --git a/.checkpatch.conf b/.checkpatch.conf index 9e40ea060b..c368d41472 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -4,7 +4,7 @@ # Temporary for false positive in checkpatch --ignore COMPLEX_MACRO -# For CONFIG_SYS_I2C_NOPROBES +# For CFG_SYS_I2C_NOPROBES --ignore MULTISTATEMENT_MACRO_USE_DO_WHILE # For simple_strtoul diff --git a/Kconfig b/Kconfig index 67f46467b1..297281e474 100644 --- a/Kconfig +++ b/Kconfig @@ -264,8 +264,8 @@ config HAS_CUSTOM_SYS_INIT_SP_ADDR default y if TFABOOT help Typically, we use an initial stack pointer address that is calculated - by taking the statically defined CONFIG_SYS_INIT_RAM_ADDR, adding the - statically defined CONFIG_SYS_INIT_RAM_SIZE and then subtracting the + by taking the statically defined CFG_SYS_INIT_RAM_ADDR, adding the + statically defined CFG_SYS_INIT_RAM_SIZE and then subtracting the build-time constant of GENERATED_GBL_DATA_SIZE. On MIPS a different but statica calculation is performed. However, some platforms will take a different approach. Say Y here to define the address statically @@ -333,7 +333,7 @@ config SPL_SYS_MALLOC_F_LEN particular needs this to operate, so that it can allocate the initial serial device and any others that are needed. - It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new + It is possible to enable CFG_SYS_SPL_MALLOC_START to start a new malloc() region in SDRAM once it is inited. config TPL_SYS_MALLOC_F_LEN diff --git a/Makefile b/Makefile index de5746399a..d48f52f294 100644 --- a/Makefile +++ b/Makefile @@ -1138,10 +1138,10 @@ endif $(call deprecated,CONFIG_WDT,DM watchdog,v2019.10,\ $(CONFIG_WATCHDOG)$(CONFIG_HW_WATCHDOG)) $(call deprecated,CONFIG_DM_I2C,I2C drivers,v2022.04,$(CONFIG_SYS_I2C_LEGACY)) - @# CONFIG_SYS_TIMER_RATE has brackets in it for some boards which + @# CFG_SYS_TIMER_RATE has brackets in it for some boards which @# confuses this rule. Use if() to send just a single character which @# is enable to tell 'deprecated' that one of these symbols exists - $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CONFIG_SYS_TIMER_RATE)$(CONFIG_SYS_TIMER_COUNTER)),x)) + $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) @# Check that this build does not use CONFIG options that we do not @@ -1361,8 +1361,8 @@ u-boot.ldr.hex u-boot.ldr.srec: u-boot.ldr FORCE # U-Boot entry point, needed for booting of full-blown U-Boot # from the SPL U-Boot version. # -ifndef CONFIG_SYS_UBOOT_START -CONFIG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) +ifndef CFG_SYS_UBOOT_START +CFG_SYS_UBOOT_START := $(CONFIG_TEXT_BASE) endif # Boards with more complex image requirements can provide an .its source file @@ -1387,7 +1387,7 @@ endif ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -p $(CONFIG_FIT_EXTERNAL_OFFSET) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \ @@ -1395,10 +1395,10 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) else MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" MKIMAGEFLAGS_u-boot-ivt.img = -A $(ARCH) -T firmware_ivt -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" u-boot-ivt.img: MKIMAGEOUTPUT = u-boot-ivt.img.log endif @@ -1429,7 +1429,7 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ UBOOT_BIN := u-boot.bin MKIMAGEFLAGS_u-boot-lzma.img = -A $(ARCH) -T standalone -C lzma -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" u-boot.bin.lzma: u-boot.bin FORCE diff --git a/README b/README index bb35a895b7..0a7635d1a2 100644 --- a/README +++ b/README @@ -341,7 +341,7 @@ The following options need to be configured: CFG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the - same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + same as CFG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. - MIPS CPU options: @@ -352,7 +352,7 @@ The following options need to be configured: be swapped if a flash programmer is used. - ARM options: - CONFIG_SYS_EXCEPTION_VECTORS_HIGH + CFG_SYS_EXCEPTION_VECTORS_HIGH Select high exception vectors of the ARM core, e.g., do not clear the V bit of the c1 register of CP15. @@ -415,7 +415,7 @@ The following options need to be configured: the defaults discussed just above. - Cache Configuration for ARM: - CONFIG_SYS_PL310_BASE - Physical base address of PL310 + CFG_SYS_PL310_BASE - Physical base address of PL310 controller register space - Serial Ports: @@ -485,7 +485,7 @@ The following options need to be configured: - GPIO Support: CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO - The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of + The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of pins supported by a particular chip. @@ -927,21 +927,21 @@ The following options need to be configured: CONFIG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. - if CONFIG_SYS_I2C_MAX_HOPS is not defined or == 0 you can + if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can omit this define. - CONFIG_SYS_I2C_MAX_HOPS + CFG_SYS_I2C_MAX_HOPS define how many muxes are maximal consecutively connected on one i2c bus. If you not use i2c muxes, omit this define. - CONFIG_SYS_I2C_BUSES + CFG_SYS_I2C_BUSES hold a list of buses you want to use, only used if CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example - a board with CONFIG_SYS_I2C_MAX_HOPS = 1 and + a board with CFG_SYS_I2C_MAX_HOPS = 1 and CFG_SYS_NUM_I2C_BUSES = 9: - CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ + CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 1}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 2}}}, \ {0, {{I2C_MUX_PCA9547, 0x70, 3}}}, \ @@ -1044,7 +1044,7 @@ The following options need to be configured: active. To switch to a different bus, use the 'i2c dev' command. Note that bus numbering is zero-based. - CONFIG_SYS_I2C_NOPROBES + CFG_SYS_I2C_NOPROBES This option specifies a list of I2C devices that will be skipped when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS @@ -1053,16 +1053,16 @@ The following options need to be configured: e.g. #undef CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_NOPROBES {0x50,0x68} + #define CFG_SYS_I2C_NOPROBES {0x50,0x68} will skip addresses 0x50 and 0x68 on a board with one I2C bus #define CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CONFIG_SYS_RTC_BUS_NUM + CFG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. If not defined, then U-Boot assumes that RTC is on I2C bus 0. @@ -1120,19 +1120,19 @@ The following options need to be configured: configuration if the INIT_B line goes low (which indicated a CRC error). - CONFIG_SYS_FPGA_WAIT_INIT + CFG_SYS_FPGA_WAIT_INIT Maximum time to wait for the INIT_B line to de-assert after PROB_B has been de-asserted during a Virtex II FPGA configuration sequence. The default time is 500 ms. - CONFIG_SYS_FPGA_WAIT_BUSY + CFG_SYS_FPGA_WAIT_BUSY Maximum time to wait for BUSY to de-assert during Virtex II FPGA configuration. The default is 5 ms. - CONFIG_SYS_FPGA_WAIT_CONFIG + CFG_SYS_FPGA_WAIT_CONFIG Time to wait after FPGA configuration. The default is 200 ms. @@ -1429,12 +1429,12 @@ Configuration Settings: - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to prompt for user input. -- CONFIG_SYS_BAUDRATE_TABLE: +- CFG_SYS_BAUDRATE_TABLE: List of legal baudrate settings for this board. -- CONFIG_SYS_MEM_RESERVE_SECURE +- CFG_SYS_MEM_RESERVE_SECURE Only implemented for ARMv8 for now. - If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory + If defined, the size of CFG_SYS_MEM_RESERVE_SECURE memory is substracted from total RAM and won't be reported to OS. This memory can be used as secure memory. A variable gd->arch.secure_ram is used to track the location. In systems @@ -1444,7 +1444,7 @@ Configuration Settings: - CFG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. -- CONFIG_SYS_FLASH_BASE: +- CFG_SYS_FLASH_BASE: Physical start address of Flash memory. - CONFIG_SYS_MALLOC_LEN: @@ -1468,16 +1468,16 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC). -- CONFIG_SYS_BOOTMAPSZ: +- CFG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by the Linux kernel (bd_info, boot arguments, FDT blob if used) must be put below this limit, unless "bootm_low" environment variable is defined and non-zero. In such case all data for the Linux kernel must be between "bootm_low" - and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. The environment + and "bootm_low" + CFG_SYS_BOOTMAPSZ. The environment variable "bootm_mapsize" will override the value of - CONFIG_SYS_BOOTMAPSZ. If CONFIG_SYS_BOOTMAPSZ is undefined, + CFG_SYS_BOOTMAPSZ. If CFG_SYS_BOOTMAPSZ is undefined, then the value in "bootm_size" will be used instead. - CONFIG_SYS_BOOT_GET_CMDLINE: @@ -1638,11 +1638,11 @@ Low Level (hardware related) configuration options: Default (power-on reset) physical address of CCSR on Freescale PowerPC SOCs. -- CONFIG_SYS_CCSRBAR: +- CFG_SYS_CCSRBAR: Virtual address of CCSR. On a 32-bit build, this is typically the same value as CONFIG_SYS_CCSRBAR_DEFAULT. -- CONFIG_SYS_CCSRBAR_PHYS: +- CFG_SYS_CCSRBAR_PHYS: Physical address of CCSR. CCSR can be relocated to a new physical address, if desired. In this case, this macro should be set to that address. Otherwise, it should be set to the @@ -1650,17 +1650,17 @@ Low Level (hardware related) configuration options: is typically relocated on 36-bit builds. It is recommended that this macro be defined via the _HIGH and _LOW macros: - #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH - * 1ull) << 32 | CONFIG_SYS_CCSRBAR_PHYS_LOW) + #define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH + * 1ull) << 32 | CFG_SYS_CCSRBAR_PHYS_LOW) -- CONFIG_SYS_CCSRBAR_PHYS_HIGH: - Bits 33-36 of CONFIG_SYS_CCSRBAR_PHYS. This value is typically +- CFG_SYS_CCSRBAR_PHYS_HIGH: + Bits 33-36 of CFG_SYS_CCSRBAR_PHYS. This value is typically either 0 (32-bit build) or 0xF (36-bit build). This macro is used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL"). -- CONFIG_SYS_CCSRBAR_PHYS_LOW: - Lower 32-bits of CONFIG_SYS_CCSRBAR_PHYS. This macro is +- CFG_SYS_CCSRBAR_PHYS_LOW: + Lower 32-bits of CFG_SYS_CCSRBAR_PHYS. This macro is used in assembly code, so it must not contain typecasts or integer size suffixes (e.g. "ULL"). @@ -1668,7 +1668,7 @@ Low Level (hardware related) configuration options: DO NOT CHANGE unless you know exactly what you're doing! (11-4) [MPC8xx systems only] -- CONFIG_SYS_INIT_RAM_ADDR: +- CFG_SYS_INIT_RAM_ADDR: Start address of memory area that can be used for initial data and stack; please note that this must be @@ -2737,7 +2737,7 @@ locked as (mis-) used as memory, etc. cause you grief during the initial boot! It is frequently not used. - CONFIG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere + CFG_SYS_INIT_RAM_ADDR should be somewhere that won't interfere with your processor/board/system design. The default value you will find in any recent u-boot distribution in walnut.h should work for you. I'd set it to a value larger diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 5a1536539d..9e76a4a9e0 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -18,7 +18,7 @@ #include #ifndef CONFIG_SYS_PHY_UBOOT_BASE -#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE +#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE #endif /* diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index aca7793c57..c882bd39ea 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -95,7 +95,7 @@ flush_dcache: mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ -#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#ifdef CFG_SYS_EXCEPTION_VECTORS_HIGH orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ #else bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ diff --git a/arch/arm/cpu/armv7/arch_timer.c b/arch/arm/cpu/armv7/arch_timer.c index d96406f762..17bd53dae8 100644 --- a/arch/arm/cpu/armv7/arch_timer.c +++ b/arch/arm/cpu/armv7/arch_timer.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_HZ_CLOCK +#ifndef CFG_SYS_HZ_CLOCK static inline u32 read_cntfrq(void) { u32 frq; @@ -29,8 +29,8 @@ int timer_init(void) gd->arch.tbl = 0; gd->arch.tbu = 0; -#ifdef CONFIG_SYS_HZ_CLOCK - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#ifdef CFG_SYS_HZ_CLOCK + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = read_cntfrq(); #endif diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index d09c21d5d9..25e4b49c70 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -313,9 +313,9 @@ int cpu_eth_init(struct bd_info *bis) int arch_cpu_init(void) { - void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = - (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); + (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; u32 state; diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 0e7d5fa06d..599b7e18ef 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -183,7 +183,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT, - CONFIG_SYS_IFC_ADDR); + CFG_SYS_IFC_ADDR); fdt_set_node_status(blob, off, FDT_STATUS_DISABLED); #else off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT, diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index 954fa5f8b4..dbb0766a9c 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -42,7 +42,7 @@ static void __secure ls1_save_ddr_head(void) static void __secure ls1_fsm_setup(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *dcsr_rcpm_base = (void *)SYS_FSL_DCSR_RCPM_ADDR; out_be32(dcsr_rcpm_base + DCSR_RCPM_CSTTACR0, 0x00001001); @@ -118,7 +118,7 @@ static void __secure ls1_delay(unsigned int loop) static void __secure ls1_start_fsm(void) { - void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; diff --git a/arch/arm/cpu/armv7/stv0991/timer.c b/arch/arm/cpu/armv7/stv0991/timer.c index 67764ccf66..f7cc45772f 100644 --- a/arch/arm/cpu/armv7/stv0991/timer.c +++ b/arch/arm/cpu/armv7/stv0991/timer.c @@ -18,7 +18,7 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) -#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) +#define GPT_RESOLUTION (CFG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -67,7 +67,7 @@ void __udelay(unsigned long usec) { ulong tmo; ulong start = get_timer_masked(); - ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100); + ulong tenudelcnt = CFG_SYS_HZ_CLOCK / (1000 * 100); ulong rndoff; rndoff = (usec % 10) ? 1 : 0; diff --git a/arch/arm/cpu/armv7m/systick-timer.c b/arch/arm/cpu/armv7m/systick-timer.c index 556eaf8c74..c30af4ff7a 100644 --- a/arch/arm/cpu/armv7m/systick-timer.c +++ b/arch/arm/cpu/armv7m/systick-timer.c @@ -18,7 +18,7 @@ * The number of reference clock ticks that correspond to 10ms is normally * defined in the SysTick Calibration register's TENMS field. However, on some * devices this is wrong, so this driver allows the clock rate to be defined - * using CONFIG_SYS_HZ_CLOCK. + * using CFG_SYS_HZ_CLOCK. */ #include @@ -76,10 +76,10 @@ int timer_init(void) /* * If the TENMS field is inexact or wrong, specify the clock rate using - * CONFIG_SYS_HZ_CLOCK. + * CFG_SYS_HZ_CLOCK. */ -#if defined(CONFIG_SYS_HZ_CLOCK) - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; +#if defined(CFG_SYS_HZ_CLOCK) + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK; #else gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bbaa91f0e1..99413ef52e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -114,7 +114,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, + { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -130,9 +130,9 @@ static struct mm_region early_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #ifdef CONFIG_FSL_IFC - /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ + /* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, + CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, #endif @@ -391,7 +391,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE {}, /* space holder for secure mem */ #endif {}, @@ -445,7 +445,7 @@ static inline void early_mmu_setup(void) if (el == 3) gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE; else - gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; + gd->arch.tlb_addr = CFG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; gd->arch.tlb_size = EARLY_PGTABLE_SIZE; @@ -568,7 +568,7 @@ static inline void final_mmu_setup(void) } } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { if (el == 3) { /* @@ -580,7 +580,7 @@ static inline void final_mmu_setup(void) gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; final_map[index].virt = gd->arch.secure_ram & ~0x3; final_map[index].phys = final_map[index].virt; - final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; + final_map[index].size = CFG_SYS_MEM_RESERVE_SECURE; final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; tlb_addr_save = gd->arch.tlb_addr; @@ -1323,10 +1323,10 @@ phys_size_t get_effective_memsize(void) ea_size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* Check if we have enough space for secure memory */ - if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) - ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + if (ea_size > CFG_SYS_MEM_RESERVE_SECURE) + ea_size -= CFG_SYS_MEM_RESERVE_SECURE; else printf("Error: No enough space for secure memory.\n"); #endif @@ -1433,7 +1433,7 @@ int dram_init_banksize(void) * gd->arch.secure_ram should be done to avoid running it repeatedly. */ -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { debug("No need to run again, skip %s\n", __func__); @@ -1442,11 +1442,11 @@ int dram_init_banksize(void) #endif gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + if (gd->ram_size > CFG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CFG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CFG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; + CFG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_DDR_BLOCK3_BASE if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; @@ -1458,17 +1458,17 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[0].size = gd->ram_size; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->bd->bi_dram[0].size > - CONFIG_SYS_MEM_RESERVE_SECURE) { + CFG_SYS_MEM_RESERVE_SECURE) { gd->bd->bi_dram[0].size -= - CONFIG_SYS_MEM_RESERVE_SECURE; + CFG_SYS_MEM_RESERVE_SECURE; gd->arch.secure_ram = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->ram_size -= CFG_SYS_MEM_RESERVE_SECURE; } -#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ +#endif /* CFG_SYS_MEM_RESERVE_SECURE */ #if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD) /* Assign memory for MC */ @@ -1520,7 +1520,7 @@ int dram_init_banksize(void) } #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE debug("%s is called. gd->ram_size is reduced to %lu\n", __func__, (ulong)gd->ram_size); #endif @@ -1580,7 +1580,7 @@ void update_early_mmu_table(void) } else { mmu_change_region_attr( CFG_SYS_SDRAM_BASE, - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | @@ -1589,10 +1589,10 @@ void update_early_mmu_table(void) #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE" #endif - if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE > + if (gd->ram_size - CFG_SYS_DDR_BLOCK1_SIZE > CONFIG_SYS_DDR_BLOCK2_SIZE) { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1601,7 +1601,7 @@ void update_early_mmu_table(void) mmu_change_region_attr( CONFIG_SYS_DDR_BLOCK3_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE - + CFG_SYS_DDR_BLOCK1_SIZE - CONFIG_SYS_DDR_BLOCK2_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1611,9 +1611,9 @@ void update_early_mmu_table(void) #endif { mmu_change_region_attr( - CONFIG_SYS_DDR_BLOCK2_BASE, + CFG_SYS_DDR_BLOCK2_BASE, gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE, + CFG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS | diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 9119d60ffb..6f3fe7ca6e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -116,10 +116,10 @@ Flash Layout Environment Variables ===================== mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value - CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. mcinitcmd: This environment variable is defined to initiate MC and DPL deployment from the location where it is stored(NOR, NAND, SD, SATA, USB)during diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 4880a313ea..e3c3fc6bfb 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -10,7 +10,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c index e47d3af85e..333d7e2fa2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c @@ -9,7 +9,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 89a6262c12..359cbc0430 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -531,7 +531,7 @@ static void erratum_a010539(void) porsr1 = in_be32(&gur->porsr1); porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; - out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((void *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif @@ -643,8 +643,8 @@ void init_pfe_scfg_dcfg_regs(void) out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS | SCFG_RD_QOS1_PFE2_QOS)); - ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); - out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, + ecccr2 = in_be32(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); + out_be32((void *)CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, ecccr2 | (unsigned int)DISABLE_PFE_ECC); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 3a4b665f24..61fced451e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -116,7 +116,7 @@ void board_init_f(ulong dummy) #endif dram_init(); #ifdef CONFIG_SPL_FSL_LS_PPA -#ifndef CONFIG_SYS_MEM_RESERVE_SECURE +#ifndef CFG_SYS_MEM_RESERVE_SECURE #error Need secure RAM for PPA #endif /* diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 540436ba02..c0e8726346 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -198,7 +198,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, goto out; } -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * The SEC Firmware must be stored in secure memory. * Append SEC Firmware to secure mmu table. @@ -211,7 +211,7 @@ static int sec_firmware_load_image(const void *sec_firmware_img, sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) + gd->arch.tlb_size; #else -#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" +#error "The CFG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" #endif /* Align SEC Firmware base address to 4K */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 0669222fed..c9c72e3271 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -20,13 +20,13 @@ * Reserve secure memory * To be aligned with MMU block size */ -#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ +#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ #ifdef CONFIG_ARCH_LS2080A #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) @@ -37,8 +37,8 @@ #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -96,7 +96,7 @@ #elif defined(CONFIG_ARCH_LS1088A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 #define SRDS_BITS_PER_LANE 4 @@ -122,8 +122,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -141,15 +141,15 @@ #endif #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } -#define CONFIG_SYS_PAGE_SIZE 0x10000 +#define CFG_SYS_PAGE_SIZE 0x10000 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -192,8 +192,8 @@ #define SMMU_BASE 0x05000000 /* GR0 Base */ /* DDR */ -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SEC */ @@ -212,8 +212,8 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -251,15 +251,15 @@ #elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 9cddb41a89..d5f63f4a7e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -75,7 +75,7 @@ void fdt_fixup_icid(void *blob); #define SET_USB_ICID(usb_num, compat, streamid) \ SET_SCFG_ICID(compat, streamid, usb##usb_num##_icid,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR) #define SET_SATA_ICID(compat, streamid) \ SET_SCFG_ICID(compat, streamid, sata_icid,\ @@ -142,7 +142,7 @@ extern int fman_icid_tbl_sz; #define SET_USB_ICID(usb_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\ - CONFIG_SYS_XHCI_USB##usb_num##_ADDR) + CFG_SYS_XHCI_USB##usb_num##_ADDR) #define SET_SATA_ICID(sata_num, compat, streamid) \ SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 64dc7c88b7..9794db0449 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,11 +11,11 @@ #include #endif -#define CONFIG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) +#define CFG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) @@ -30,37 +30,37 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CFG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CFG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CFG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CFG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 -#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ - CONFIG_SYS_BMAN_MEM_BASE) -#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0x508000000 +#define CFG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ + CFG_SYS_BMAN_MEM_BASE) +#define CFG_SYS_BMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x10000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0x3E80 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0x500000000 +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_SIZE 0x08000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x10000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0x3680 #define CFG_SYS_FSL_TIMER_ADDR 0x02b00000 @@ -134,20 +134,20 @@ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ #define TP_INIT_PER_CLUSTER 4 -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR 0x01000000 +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0x01000000 #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW 0x01000000 #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index cd112402e0..ca5e33379b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -33,7 +33,7 @@ #define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) #endif #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) @@ -67,8 +67,8 @@ #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -105,7 +105,7 @@ #define GPU_BASE_ADDR (CONFIG_SYS_IMMR + 0x0e0c0000) /* SFP */ -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) /* SEC */ #define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull @@ -173,7 +173,7 @@ #endif /* Security Monitor */ -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 6de431f6bb..3ad78cb1e6 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -23,7 +23,7 @@ #define CFG_SYS_NS16550_CLK 13000000 #endif -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } /* NAND */ @@ -49,7 +49,7 @@ /* USB OHCI */ #if defined(CONFIG_USB_OHCI_LPC32XX) -#define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE +#define CFG_SYS_USB_OHCI_REGS_BASE USB_BASE #endif #endif /* _LPC32XX_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 62026bda9e..6413a307d2 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,36 +11,36 @@ #define OCRAM_BASE_S_ADDR 0x10010000 #define OCRAM_S_SIZE 0x00010000 -#define CONFIG_SYS_DCSRBAR 0x20000000 +#define CFG_SYS_DCSRBAR 0x20000000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) -#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) +#define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000) +#define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000) #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) #define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) +#define CFG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) #define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) #define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) -#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) -#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) +#define CFG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) +#define CFG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) #define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) -#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CFG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 #define CFG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 -#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 +#define CFG_SYS_TSEC1_OFFSET 0x01d10000 +#define CFG_SYS_MDIO1_OFFSET 0x01d24000 -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0acf67798..a0c3da7f46 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -42,24 +42,24 @@ #define DCFG_DCSR_PORCR1 0 -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_IMMR #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index fb5ded8907..acd8c69f69 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -12,14 +12,14 @@ { .compat = name, \ .id = { idA }, .num_ids = 1, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ .reg_offset = off + CONFIG_SYS_IMMR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } /* diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index d5c0ed8e6c..a0ab3a0e66 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -899,9 +899,9 @@ struct esdc_regs { * Generic timer support */ #ifdef CONFIG_MX31_CLK32 -#define CONFIG_SYS_TIMER_RATE CONFIG_MX31_CLK32 +#define CFG_SYS_TIMER_RATE CONFIG_MX31_CLK32 #else -#define CONFIG_SYS_TIMER_RATE 32768 +#define CFG_SYS_TIMER_RATE 32768 #endif #endif /* __ASM_ARCH_MX31_IMX_REGS_H */ diff --git a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h index 5b12d90d58..eb1ddca600 100644 --- a/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h +++ b/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h @@ -36,6 +36,6 @@ struct gpt_regs *const gpt1_regs_ptr = #define GPT_FREE_RUNNING 0xFFFF /* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) +#define CFG_SYS_HZ_CLOCK ((27 * 1000 * 1000) / GPT_PRESCALER_128) #endif diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 3525f22e7d..241b44928a 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -18,6 +18,6 @@ #endif /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ -#define CONFIG_SYS_TCLK 24000000 +#define CFG_SYS_TCLK 24000000 #endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index cd6112dfcd..9e746e380a 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -54,7 +54,7 @@ struct arch_global_data { unsigned long tlb_emerg; #endif #endif -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE #define MEM_RESERVE_SECURE_SECURED 0x1 #define MEM_RESERVE_SECURE_MAINTAINED 0x2 #define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c index 826e09e72c..5e6eaad968 100644 --- a/arch/arm/lib/bdinfo.c +++ b/arch/arm/lib/bdinfo.c @@ -29,7 +29,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd; bdinfo_print_num_l("arch_number", bd->bi_arch_number); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) { bdinfo_print_num_ll("Secure ram", gd->arch.secure_ram & diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c index bbaaaa4157..d05314ee57 100644 --- a/arch/arm/lib/cache-pl310.c +++ b/arch/arm/lib/cache-pl310.c @@ -11,7 +11,7 @@ #include #include -struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static void pl310_cache_sync(void) { diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index a2bf2e57b9..1a589c7e2a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -152,7 +152,7 @@ __weak int arm_reserve_mmu(void) debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CFG_SYS_MEM_RESERVE_SECURE /* * Record allocated tlb_addr in case gd->tlb_addr to be overwritten * with location within secure ram. diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index a54c84b062..7cf7d1636f 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -83,8 +83,8 @@ */ _start: -#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG - .word CONFIG_SYS_DV_NOR_BOOT_CFG +#ifdef CFG_SYS_DV_NOR_BOOT_CFG + .word CFG_SYS_DV_NOR_BOOT_CFG #endif ARM_VECTORS #endif /* !defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK) */ diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c index c7440278d8..09ac66d619 100644 --- a/arch/arm/mach-at91/arm920t/clock.c +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -107,7 +107,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -120,7 +120,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c index 44c079c0fd..9bf03fd68e 100644 --- a/arch/arm/mach-at91/arm920t/cpu.c +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -16,11 +16,11 @@ #include #include -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 3b91a0cba3..6b7d3cbc71 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -94,11 +94,11 @@ SMRDATA: .word AT91_ASM_MC_SMC_CSR0 .word CONFIG_SYS_SMC_CSR0_VAL .word AT91_ASM_PMC_PLLAR - .word CONFIG_SYS_PLLAR_VAL + .word CFG_SYS_PLLAR_VAL .word AT91_ASM_PMC_PLLBR .word CONFIG_SYS_PLLBR_VAL .word AT91_ASM_PMC_MCKR - .word CONFIG_SYS_MCKR_VAL + .word CFG_SYS_MCKR_VAL SMRDATAE: /* here there's a delay */ SMRDATA1: @@ -107,17 +107,17 @@ SMRDATA1: .word AT91_ASM_PIOC_BSR .word CONFIG_SYS_PIOC_BSR_VAL .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL + .word CFG_SYS_PIOC_PDR_VAL .word AT91_ASM_MC_EBI_CSA .word CONFIG_SYS_EBI_CSA_VAL .word AT91_ASM_MC_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL + .word CFG_SYS_SDRC_MR_VAL .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word CFG_SYS_SDRAM @@ -135,15 +135,15 @@ SMRDATA1: .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRC_MR_VAL2 .word CFG_SYS_SDRAM1 .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL + .word CFG_SYS_SDRC_TR_VAL .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRC_MR_VAL3 .word CFG_SYS_SDRAM .word CFG_SYS_SDRAM_VAL SMRDATA1E: diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c index c400e87813..8ef5764e31 100644 --- a/arch/arm/mach-at91/arm920t/timer.c +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; /* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) +#define TIMER_LOAD_VAL (CFG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) int timer_init(void) { @@ -92,7 +92,7 @@ void __udelay(unsigned long usec) u32 endtime; signed long diff; - tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo = CFG_SYS_HZ_CLOCK / 1000; tmo *= usec; tmo /= 1000; diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c index c68e0c0c3c..013daf43b7 100644 --- a/arch/arm/mach-at91/arm926ejs/clock.c +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -26,7 +26,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -115,7 +115,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -128,7 +128,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c index 761edb6df5..5e84b0a40e 100644 --- a/arch/arm/mach-at91/arm926ejs/cpu.c +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -15,13 +15,13 @@ #include #include -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) { - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); } void arch_preboot_os(void) diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index ecfe589e45..e159a74eea 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -21,8 +21,8 @@ #ifdef CONFIG_ATMEL_LEGACY #include #endif -#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL -#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#ifndef CFG_SYS_MATRIX_EBICSA_VAL +#define CFG_SYS_MATRIX_EBICSA_VAL CFG_SYS_MATRIX_EBI0CSA_VAL #endif .globl lowlevel_init @@ -67,7 +67,7 @@ POS1: ldr r1, =(AT91_ASM_PMC_MOR) ldr r2, =(AT91_ASM_PMC_SR) /* Main oscillator Enable register PMC_MOR: */ - ldr r0, =CONFIG_SYS_MOR_VAL + ldr r0, =CFG_SYS_MOR_VAL str r0, [r1] /* Reading the PMC Status to detect when the Main Oscillator is enabled */ @@ -85,7 +85,7 @@ MOSCS_Loop: * ---------------------------------------------------------------------------- */ ldr r1, =(AT91_ASM_PMC_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL + ldr r0, =CFG_SYS_PLLAR_VAL str r0, [r1] /* Reading the PMC Status register to detect when the PLLA is locked */ @@ -105,7 +105,7 @@ MOSCS_Loop1: ldr r1, =(AT91_ASM_PMC_MCKR) /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL + ldr r0, =CFG_SYS_MCKR1_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ @@ -116,7 +116,7 @@ MCKRDY_Loop: cmp r3, #AT91_PMC_IXR_MCKRDY bne MCKRDY_Loop - ldr r0, =CONFIG_SYS_MCKR2_VAL + ldr r0, =CFG_SYS_MCKR2_VAL str r0, [r1] /* Reading the PMC Status to detect when the Master clock is ready */ @@ -158,53 +158,53 @@ SDRAM_setup_end: SMRDATA: .word AT91_ASM_WDT_MR - .word CONFIG_SYS_WDTC_WDMR_VAL + .word CFG_SYS_WDTC_WDMR_VAL /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) .word AT91_ASM_PIOD_PDR - .word CONFIG_SYS_PIOD_PDR_VAL1 + .word CFG_SYS_PIOD_PDR_VAL1 .word AT91_ASM_PIOD_PUDR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL .word AT91_ASM_PIOD_ASR - .word CONFIG_SYS_PIOD_PPUDR_VAL + .word CFG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ || defined(CONFIG_AT91SAM9G20) .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL1 + .word CFG_SYS_PIOC_PDR_VAL1 .word AT91_ASM_PIOC_PUDR - .word CONFIG_SYS_PIOC_PPUDR_VAL + .word CFG_SYS_PIOC_PPUDR_VAL #endif .word AT91_ASM_MATRIX_CSA0 - .word CONFIG_SYS_MATRIX_EBICSA_VAL + .word CFG_SYS_MATRIX_EBICSA_VAL /* flash */ .word AT91_ASM_SMC_MODE0 - .word CONFIG_SYS_SMC0_MODE0_VAL + .word CFG_SYS_SMC0_MODE0_VAL .word AT91_ASM_SMC_CYCLE0 - .word CONFIG_SYS_SMC0_CYCLE0_VAL + .word CFG_SYS_SMC0_CYCLE0_VAL .word AT91_ASM_SMC_PULSE0 - .word CONFIG_SYS_SMC0_PULSE0_VAL + .word CFG_SYS_SMC0_PULSE0_VAL .word AT91_ASM_SMC_SETUP0 - .word CONFIG_SYS_SMC0_SETUP0_VAL + .word CFG_SYS_SMC0_SETUP0_VAL SMRDATA1: .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 + .word CFG_SYS_SDRC_MR_VAL1 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL1 + .word CFG_SYS_SDRC_TR_VAL1 .word AT91_ASM_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL + .word CFG_SYS_SDRC_CR_VAL .word AT91_ASM_SDRAMC_MDR - .word CONFIG_SYS_SDRC_MDR_VAL + .word CFG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 + .word CFG_SYS_SDRC_MR_VAL2 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 + .word CFG_SYS_SDRC_MR_VAL3 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL2 .word CFG_SYS_SDRAM_BASE @@ -222,20 +222,20 @@ SMRDATA1: .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL4 + .word CFG_SYS_SDRC_MR_VAL4 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL5 + .word CFG_SYS_SDRC_MR_VAL5 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL2 + .word CFG_SYS_SDRC_TR_VAL2 .word CFG_SYS_SDRAM_BASE .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR - .word CONFIG_SYS_RSTC_RMR_VAL + .word CFG_SYS_RSTC_RMR_VAL #ifdef CONFIG_SYS_MATRIX_MCFG_REMAP /* MATRIX_MCFG - REMAP all masters */ .word AT91_ASM_MATRIX_MCFG diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c index aa6bb6bf31..6bfa02d1d0 100644 --- a/arch/arm/mach-at91/armv7/clock.c +++ b/arch/arm/mach-at91/armv7/clock.c @@ -28,7 +28,7 @@ static unsigned long at91_css_to_rate(unsigned long css) { switch (css) { case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: return gd->arch.main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: @@ -58,7 +58,7 @@ int at91_clock_init(unsigned long main_clock) { unsigned freq, mckr; struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#ifndef CFG_SYS_AT91_MAIN_CLOCK unsigned tmp; /* * When the bootloader initialized the main oscillator correctly, @@ -71,7 +71,7 @@ int at91_clock_init(unsigned long main_clock) tmp = readl(&pmc->mcfr); } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + main_clock = tmp * (CFG_SYS_AT91_SLOW_CLOCK / 16); } #endif gd->arch.main_clk_rate_hz = main_clock; @@ -271,7 +271,7 @@ u32 at91_get_periph_generated_clk(u32 id) clk_source = regval & AT91_PMC_PCR_GCKCSS; switch (clk_source) { case AT91_PMC_PCR_GCKCSS_SLOW_CLK: - freq = CONFIG_SYS_AT91_SLOW_CLOCK; + freq = CFG_SYS_AT91_SLOW_CLOCK; break; case AT91_PMC_PCR_GCKCSS_MAIN_CLK: freq = gd->arch.main_clk_rate_hz; diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index 9b3753491e..616621a1f9 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -18,8 +18,8 @@ #include #include -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#ifndef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 0 #endif int arch_cpu_init(void) @@ -27,7 +27,7 @@ int arch_cpu_init(void) #if defined(CONFIG_CLK_CCF) return 0; #else - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + return at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); #endif } diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h index 2daeb4fef8..103db26953 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9260.h +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -128,7 +128,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index d5de8d5551..2b252f1e1e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h index c9fff934da..0aa1862567 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9263.h +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -127,7 +127,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h index 588032582b..22116f375b 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -132,7 +132,7 @@ #define ATMEL_BASE_CS7 0x80000000 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h index 8f9155c9ea..b2c074e93e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9rl.h +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h @@ -112,7 +112,7 @@ #define ATMEL_BASE_CS5 0x60000000 /* Compact Flash Slot 1 */ /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffd3c +#define CFG_SYS_TIMER_COUNTER 0xfffffd3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h index e3c494c5d5..0efb4a9f6d 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9x5.h +++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h @@ -162,7 +162,7 @@ #endif /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sam9x60.h b/arch/arm/mach-at91/include/mach/sam9x60.h index c08d19c691..47c7c7209e 100644 --- a/arch/arm/mach-at91/include/mach/sam9x60.h +++ b/arch/arm/mach-at91/include/mach/sam9x60.h @@ -140,7 +140,7 @@ #define ATMEL_CPU_NAME get_cpu_name() /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c +#define CFG_SYS_TIMER_COUNTER 0xfffffe4c /* * Other misc defines diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index 5ff20e9573..567cdd3cba 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -238,7 +238,7 @@ #define cpu_is_sama5d2 _cpu_is_sama5d2 /* PIT Timer(PIT_PIIR) */ -#define CONFIG_SYS_TIMER_COUNTER 0xf804803c +#define CFG_SYS_TIMER_COUNTER 0xf804803c #ifndef __ASSEMBLY__ unsigned int get_chip_id(void); diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h index 83f18a8148..9efcf5f4fa 100644 --- a/arch/arm/mach-at91/include/mach/sama5d3.h +++ b/arch/arm/mach-at91/include/mach/sama5d3.h @@ -185,7 +185,7 @@ #define CPU_HAS_PCR /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c +#define CFG_SYS_TIMER_COUNTER 0xfffffe3c /* * PMECC table in ROM diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h index e2edb6a51b..9c80286ade 100644 --- a/arch/arm/mach-at91/include/mach/sama5d4.h +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -217,7 +217,7 @@ (get_extension_chip_id() == ARCH_EXID_SAMA5D44)) /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c /* * No PMECC Galois table in ROM diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index ea19ec322e..dfba9f730c 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -101,17 +101,17 @@ void board_init_f(ulong dummy) at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ - at91_plla_init(CONFIG_SYS_AT91_PLLA); + at91_plla_init(CFG_SYS_AT91_PLLA); /* PCK = PLLA = 2 * MCK */ - at91_mck_init(CONFIG_SYS_MCKR); + at91_mck_init(CFG_SYS_MCKR); /* Switch MCK on PLLA output */ - at91_mck_init(CONFIG_SYS_MCKR_CSS); + at91_mck_init(CFG_SYS_MCKR_CSS); -#if defined(CONFIG_SYS_AT91_PLLB) +#if defined(CFG_SYS_AT91_PLLB) /* Configure PLLB */ - at91_pllb_init(CONFIG_SYS_AT91_PLLB); + at91_pllb_init(CFG_SYS_AT91_PLLB); #endif /* Enable External Reset */ @@ -120,7 +120,7 @@ void board_init_f(ulong dummy) /* Initialize matrix */ matrix_init(); - gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + gd->arch.mck_rate_hz = CFG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c index 217ed12e31..a30c4f6c07 100644 --- a/arch/arm/mach-at91/spl_atmel.c +++ b/arch/arm/mach-at91/spl_atmel.c @@ -124,7 +124,7 @@ void board_init_f(ulong dummy) /* PMC configuration */ at91_pmc_init(); - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); matrix_init(); diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index 0f68f9fe59..dae60262f5 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -42,7 +42,7 @@ int clk_get(enum davinci_clk_ids id) int pll_out; unsigned int pll_base; - pll_out = CONFIG_SYS_OSCIN_FREQ; + pll_out = CFG_SYS_OSCIN_FREQ; if (id == DAVINCI_AUXCLK_CLKID) goto out; diff --git a/arch/arm/mach-davinci/da850_lowlevel.c b/arch/arm/mach-davinci/da850_lowlevel.c index 2319ac6d56..08c8f59252 100644 --- a/arch/arm/mach-davinci/da850_lowlevel.c +++ b/arch/arm/mach-davinci/da850_lowlevel.c @@ -185,9 +185,9 @@ static int da850_ddr_setup(void) setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); } setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); - writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); + writel(CFG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { + if (CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) { /* DDR2 */ clrbits_le32(&davinci_syscfg1_regs->ddr_slew, (1 << DDR_SLEW_DDR_PDENA_BIT) | @@ -211,19 +211,19 @@ static int da850_ddr_setup(void) * At the same time, set the TIMUNLOCK bit to allow changing * the timing registers */ - tmp = CONFIG_SYS_DA850_DDR2_SDBCR; + tmp = CFG_SYS_DA850_DDR2_SDBCR; tmp &= ~DV_DDR_BOOTUNLOCK; tmp |= DV_DDR_TIMUNLOCK; writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); /* write memory configuration and timing */ - if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { + if (!(CFG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) { /* MOBILE DDR only*/ - writel(CONFIG_SYS_DA850_DDR2_SDBCR2, + writel(CFG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2); } - writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); + writel(CFG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); + writel(CFG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); /* clear the TIMUNLOCK bit and write the value of the CL field */ tmp &= ~DV_DDR_TIMUNLOCK; @@ -233,7 +233,7 @@ static int da850_ddr_setup(void) * LPMODEN and MCLKSTOPEN must be set! * Without this bits set, PSC don;t switch states !! */ - writel(CONFIG_SYS_DA850_DDR2_SDRCR | + writel(CFG_SYS_DA850_DDR2_SDRCR | (1 << DV_DDR_SRCR_LPMODEN_SHIFT) | (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT), &dv_ddr2_regs_ctrl->sdrcr); @@ -246,7 +246,7 @@ static int da850_ddr_setup(void) /* disable self refresh */ clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN); - writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); + writel(CFG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); return 0; } @@ -265,7 +265,7 @@ int arch_cpu_init(void) writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); dv_maskbits(&davinci_syscfg_regs->suspsrc, - CONFIG_SYS_DA850_SYSCFG_SUSPSRC); + CFG_SYS_DA850_SYSCFG_SUSPSRC); /* configure pinmux settings */ if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size)) @@ -273,8 +273,8 @@ int arch_cpu_init(void) #if defined(CONFIG_SYS_DA850_PLL_INIT) /* PLL setup */ - da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM); - da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM); + da850_pll_init(davinci_pllc0_regs, CFG_SYS_DA850_PLL0_PLLM); + da850_pll_init(davinci_pllc1_regs, CFG_SYS_DA850_PLL1_PLLM); #endif /* setup CSn config */ #if defined(CONFIG_SYS_DA850_CS2CFG) diff --git a/arch/arm/mach-davinci/timer.c b/arch/arm/mach-davinci/timer.c index 43e0574901..83c190b620 100644 --- a/arch/arm/mach-davinci/timer.c +++ b/arch/arm/mach-davinci/timer.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct davinci_timer * const timer = - (struct davinci_timer *)CONFIG_SYS_TIMERBASE; + (struct davinci_timer *)CFG_SYS_TIMERBASE; #define TIMER_LOAD_VAL 0xffffffff @@ -47,7 +47,7 @@ int timer_init(void) writel(0x0, &timer->tim34); writel(TIMER_LOAD_VAL, &timer->prd34); writel(2 << 22, &timer->tcr); - gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV; + gd->arch.timer_rate_hz = CFG_SYS_HZ_CLOCK / TIM_CLK_DIV; gd->arch.timer_reset_value = 0; return(0); diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c index f518539057..553dac75b6 100644 --- a/arch/arm/mach-exynos/spl_boot.c +++ b/arch/arm/mach-exynos/spl_boot.c @@ -141,7 +141,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) { int upto, todo; int i, timeout = 100; - struct exynos_spi *regs = (struct exynos_spi *)CONFIG_SYS_SPI_BASE; + struct exynos_spi *regs = (struct exynos_spi *)CFG_SYS_SPI_BASE; set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ /* set the spi1 GPIO */ diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 0e76786482..06ee608c4a 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -248,13 +248,13 @@ unsigned long spl_nor_get_uboot_base(void) int end; /* Calculate the image set end, - * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000), - * we use CONFIG_SYS_UBOOT_BASE + * if it is less than CFG_SYS_UBOOT_BASE(0x8281000), + * we use CFG_SYS_UBOOT_BASE * Otherwise, use the calculated address */ end = get_imageset_end((void *)NULL, QSPI_NOR_DEV); - if (end <= CONFIG_SYS_UBOOT_BASE) - end = CONFIG_SYS_UBOOT_BASE; + if (end <= CFG_SYS_UBOOT_BASE) + end = CFG_SYS_UBOOT_BASE; else end = ROUND(end, SZ_1K); diff --git a/arch/arm/mach-imx/mx5/lowlevel_init.S b/arch/arm/mach-imx/mx5/lowlevel_init.S index b42cc3e9e4..6ec38dcfa4 100644 --- a/arch/arm/mach-imx/mx5/lowlevel_init.S +++ b/arch/arm/mach-imx/mx5/lowlevel_init.S @@ -205,7 +205,7 @@ setup_pll_func: /* Switch peripheral to PLL 3 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000010C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] @@ -215,7 +215,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x19239145 str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C0 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] setup_pll PLL3_BASE_ADDR, 216 @@ -240,10 +240,10 @@ setup_pll_func: /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL + ldr r1, =0x000020C2 | CFG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =CONFIG_SYS_CLKTL_CBCDR + ldr r1, =CFG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] /* Restore the default values in the Gate registers */ @@ -378,7 +378,7 @@ ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ -#if defined(CONFIG_SYS_MAIN_PWR_ON) +#if defined(CFG_SYS_MAIN_PWR_ON) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] orr r1, r1, #1 << 23 diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk index 9cc1f9eb24..7bc8af813a 100644 --- a/arch/arm/mach-k3/config_secure.mk +++ b/arch/arm/mach-k3/config_secure.mk @@ -30,7 +30,7 @@ tispl.bin_HS: $(obj)/u-boot-spl-nodtb.bin_HS $(patsubst %,$(obj)/dts/%.dtb_HS,$( $(call if_changed,mkfitimage) MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c index 4734e4c714..dc97bac855 100644 --- a/arch/arm/mach-keystone/cmd_mon.c +++ b/arch/arm/mach-keystone/cmd_mon.c @@ -23,7 +23,7 @@ static int do_mon_install(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 2) return CMD_RET_USAGE; - freq = CONFIG_SYS_HZ_CLOCK; + freq = CFG_SYS_HZ_CLOCK; addr = hextoul(argv[1], NULL); diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index 98a8f058df..424c32a4be 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -263,7 +263,7 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 #define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) -#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ +#define KS2_MSMC_DST_SEG_BASE (CFG_SYS_LPAE_SDRAM_BASE >> \ KS2_MSMC_SEG_SIZE_SHIFT) /* Device speed */ diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 5186f6e4f9..a2781e25a2 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -52,8 +52,8 @@ /* Use common timer */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK +#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) +#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK #endif #endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h index c44eacfc1b..d3a3a83657 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h @@ -15,6 +15,6 @@ #define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */ #endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index f86cd0bb60..7f8e156a6b 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,7 +15,7 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE /* TCLK Core Clock definition */ -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ 166666667 : 200000000) #endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1f8cdf8744..67ad5e5907 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -659,7 +659,7 @@ void enable_caches(void) void v7_outer_cache_enable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; /* The L2 cache is already disabled at this point */ @@ -691,7 +691,7 @@ void v7_outer_cache_enable(void) void v7_outer_cache_disable(void) { struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); } diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3b9618852c..e6383d4a86 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -54,7 +54,7 @@ #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000)) -#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE +#define CFG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) #define MVEBU_TWSI1_BASE (MVEBU_REGISTER(0x11100)) #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) @@ -146,7 +146,7 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ @@ -169,7 +169,7 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ @@ -188,7 +188,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +#define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) @@ -209,7 +209,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ #endif #endif /* _MVEBU_SOC_H */ diff --git a/arch/arm/mach-mvebu/lowlevel.S b/arch/arm/mach-mvebu/lowlevel.S index 60c2072c35..6c9783aa63 100644 --- a/arch/arm/mach-mvebu/lowlevel.S +++ b/arch/arm/mach-mvebu/lowlevel.S @@ -35,10 +35,10 @@ ENTRY(arch_very_early_init) * Disable L2 cache * * NOTE: Internal registers are still at address INTREG_BASE_ADDR_REG - * but CONFIG_SYS_PL310_BASE is already calculated from base + * but CFG_SYS_PL310_BASE is already calculated from base * address SOC_REGS_PHY_BASE. */ - ldr r1, =(CONFIG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) + ldr r1, =(CFG_SYS_PL310_BASE - SOC_REGS_PHY_BASE + INTREG_BASE_ADDR_REG) ldr r0, [r1, #L2X0_CTRL_OFF] bic r0, #L2X0_CTRL_EN str r0, [r1, #L2X0_CTRL_OFF] diff --git a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c index cba2e342dc..ed4b1ca5c9 100644 --- a/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c +++ b/arch/arm/mach-npcm/npcm7xx/l2_cache_pl310.c @@ -11,7 +11,7 @@ void l2_pl310_init(void); void set_pl310_ctrl(u32 enable) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; writel(enable, &pl310->pl310_ctrl); } diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk index f76262bb0c..24ddcdb961 100644 --- a/arch/arm/mach-omap2/config_secure.mk +++ b/arch/arm/mach-omap2/config_secure.mk @@ -102,7 +102,7 @@ u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin FORCE ifdef CONFIG_SPL_LOAD_FIT MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -a $(CONFIG_TEXT_BASE) -e $(CFG_SYS_UBOOT_START) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) diff --git a/arch/arm/mach-omap2/mem-common.c b/arch/arm/mach-omap2/mem-common.c index 803dc7fb71..19197482aa 100644 --- a/arch/arm/mach-omap2/mem-common.c +++ b/arch/arm/mach-omap2/mem-common.c @@ -124,11 +124,11 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_NOR) case MTD_DEV_TYPE_NOR: gpmc_regs = gpmc_regs_nor; - base = CONFIG_SYS_FLASH_BASE; - size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + base = CFG_SYS_FLASH_BASE; + size = (CFG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + ((CFG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + ((CFG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + ((CFG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : GPMC_SIZE_16M))); break; #endif @@ -142,7 +142,7 @@ void set_gpmc_cs0(int flash_type) #if defined(CONFIG_CMD_ONENAND) case MTD_DEV_TYPE_ONENAND: gpmc_regs = gpmc_regs_onenand; - base = CONFIG_SYS_ONENAND_BASE; + base = CFG_SYS_ONENAND_BASE; size = GPMC_SIZE_128M; break; #endif diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 00d91c1013..71fdf5bf48 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; +static struct gptimer *timer_base = (struct gptimer *)CFG_SYS_TIMERBASE; static ulong get_timer_masked(void); /* diff --git a/arch/arm/mach-orion5x/include/mach/mv88f5182.h b/arch/arm/mach-orion5x/include/mach/mv88f5182.h index 0e9fe0dc51..ee0aa94bf2 100644 --- a/arch/arm/mach-orion5x/include/mach/mv88f5182.h +++ b/arch/arm/mach-orion5x/include/mach/mv88f5182.h @@ -18,6 +18,6 @@ #define ORION5X_REGS_PHY_BASE F88F5182_REGS_PHYS_BASE /* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ +#define CFG_SYS_TCLK 166000000 /* 166MHz */ #endif /* _CONFIG_88F5182_H */ diff --git a/arch/arm/mach-orion5x/timer.c b/arch/arm/mach-orion5x/timer.c index d7ea2e3943..b373e59e6f 100644 --- a/arch/arm/mach-orion5x/timer.c +++ b/arch/arm/mach-orion5x/timer.c @@ -74,7 +74,7 @@ struct orion5x_tmr_registers *orion5x_tmr_regs = static inline ulong read_timer(void) { return readl(CNTMR_VAL_REG(UBOOT_CNTR)) - / (CONFIG_SYS_TCLK / 1000); + / (CFG_SYS_TCLK / 1000); } DECLARE_GLOBAL_DATA_PTR; @@ -92,7 +92,7 @@ static ulong get_timer_masked(void) } else { /* we have an overflow ... */ timestamp += lastdec + - (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + (TIMER_LOAD_VAL / (CFG_SYS_TCLK / 1000)) - now; } lastdec = now; @@ -115,7 +115,7 @@ void __udelay(unsigned long usec) ulong delayticks; current = uboot_cntr_val(); - delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + delayticks = (usec * (CFG_SYS_TCLK / 1000000)); if (current < delayticks) { delayticks -= current; diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index 28669e3c77..485ea7e28d 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -24,7 +24,7 @@ #define MSTP11_BITS 0x00000000 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 4 #define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index 37d134c5bf..2006ad58a5 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -14,7 +14,7 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h index 06db64af6c..cc1b00db33 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -24,6 +24,6 @@ #define MSTP11_BITS 0x00000008 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 1 #endif /* __ASM_ARCH_R8A7792_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 85f59d9771..02f4286ef1 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -15,7 +15,7 @@ */ /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define DBSC3_1_QOS_R0_BASE 0xE67A1000 #define DBSC3_1_QOS_R1_BASE 0xE67A1100 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 2bd6e469c8..a2a949d4d6 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -24,7 +24,7 @@ #define MSTP11_BITS 0x000001C0 /* SDHI */ -#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 +#define CFG_SYS_SH_SDHI_NR_CHANNEL 3 #define R8A7794_CUT_ES2 2 #define IS_R8A7794_ES2() \ diff --git a/arch/arm/mach-rmobile/timer.c b/arch/arm/mach-rmobile/timer.c index ba06535e4c..293c23b5e2 100644 --- a/arch/arm/mach-rmobile/timer.c +++ b/arch/arm/mach-rmobile/timer.c @@ -40,8 +40,8 @@ static u64 get_time_us(void) { u64 timer = get_cpu_global_timer(); - timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); - do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); + timer = ((timer << 2) + (CLK2MHZ(CFG_SYS_CPU_CLK) >> 1)); + do_div(timer, CLK2MHZ(CFG_SYS_CPU_CLK)); return timer; } @@ -65,7 +65,7 @@ void __udelay(unsigned long usec) u64 wait; start = get_cpu_global_timer(); - wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2); + wait = (u64)((usec * CLK2MHZ(CFG_SYS_CPU_CLK)) >> 2); do { current = get_cpu_global_timer(); } while ((current - start) < wait); @@ -83,5 +83,5 @@ unsigned long long get_ticks(void) ulong get_tbclk(void) { - return (ulong)(CONFIG_SYS_CPU_CLK >> 2); + return (ulong)(CFG_SYS_CPU_CLK >> 2); } diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 9c19157de7..5b5a81a255 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -34,7 +34,7 @@ phys_addr_t socfpga_sysmgr_base __section(".data"); #ifdef CONFIG_SYS_L2_PL310 static const struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; #endif struct bsel bsel_str[] = { diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7ce888d197..93c9e8b0fb 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -60,7 +60,7 @@ static Altera_desc altera_fpga[] = { #if defined(CONFIG_SPL_BUILD) static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base = (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS; @@ -256,7 +256,7 @@ void dram_bank_mmu_setup(int bank) /* If we're still in OCRAM, don't set the XN bit on it */ if (!(gd->flags & GD_FLG_RELOC)) { set_section_dcache( - CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, DCACHE_WRITETHROUGH); } diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 4edf4f9b5c..e7500c16f7 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static struct scu_registers *scu_regs = diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index 2c567edd50..9edbbf4a29 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ -#define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ +#define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \ SOCFPGA_PHYS_OCRAM_SIZE - \ BOOTROM_SHARED_MEM_SIZE) #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) diff --git a/arch/arm/mach-socfpga/timer.c b/arch/arm/mach-socfpga/timer.c index a58f1cf9d3..d9e8c84bfc 100644 --- a/arch/arm/mach-socfpga/timer.c +++ b/arch/arm/mach-socfpga/timer.c @@ -10,7 +10,7 @@ #define TIMER_LOAD_VAL 0xFFFFFFFF -static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; +static const struct socfpga_timer *timer_base = (void *)CFG_SYS_TIMERBASE; /* * Timer initialization diff --git a/arch/arm/mach-u8500/cache.c b/arch/arm/mach-u8500/cache.c index f9fd4fe7d3..05a91346a8 100644 --- a/arch/arm/mach-u8500/cache.c +++ b/arch/arm/mach-u8500/cache.c @@ -22,7 +22,7 @@ void enable_caches(void) #ifdef CONFIG_SYS_L2_PL310 void v7_outer_cache_disable(void) { - struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; + struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; /* * Linux expects the L2 cache to be turned off by the bootloader. diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c index a40bdf1705..58247c2738 100644 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ b/arch/arm/mach-uniphier/arm32/timer.c @@ -10,7 +10,7 @@ #include "arm-mpcore.h" #define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1) +#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1) static void *get_global_timer_base(void) { diff --git a/arch/arm/mach-versatile/timer.c b/arch/arm/mach-versatile/timer.c index 739cb2997a..b471412186 100644 --- a/arch/arm/mach-versatile/timer.c +++ b/arch/arm/mach-versatile/timer.c @@ -36,9 +36,9 @@ int timer_init (void) ulong tmr_ctrl_val; /* 1st disable the Timer */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~TIMER_ENABLE; - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; /* * The Timer Control Register has one Undefined/Shouldn't Use Bit @@ -52,11 +52,11 @@ int timer_init (void) * Tmr Siz : 16 Bit Counter * Tmr in Wrapping Mode */ - tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8); + tmr_ctrl_val = *(volatile ulong *)(CFG_SYS_TIMERBASE + 8); tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = tmr_ctrl_val; return 0; } diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index e44656db5f..6d87908965 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -92,7 +92,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); wdog_module |= (wdog_module / 8192); out_be16(&wdp->mr, wdog_module); diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c index 87effa71dc..10be73822f 100644 --- a/arch/m68k/cpu/mcf523x/cpu_init.c +++ b/arch/m68k/cpu/mcf523x/cpu_init.c @@ -47,36 +47,36 @@ void cpu_init_f(void) out_be16(&wdog->cr, 0); #endif - out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); + out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE); /* Port configuration */ out_8(&gpio->par_cs, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1); - out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2); - out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3); - out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -108,8 +108,8 @@ void cpu_init_f(void) #endif #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif icache_enable(); diff --git a/arch/m68k/cpu/mcf523x/speed.c b/arch/m68k/cpu/mcf523x/speed.c index f41f977d7f..6b08a12af0 100644 --- a/arch/m68k/cpu/mcf523x/speed.c +++ b/arch/m68k/cpu/mcf523x/speed.c @@ -29,7 +29,7 @@ int get_clocks(void) while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) ; - gd->bus_clk = CONFIG_SYS_CLK; + gd->bus_clk = CFG_SYS_CLK; gd->cpu_clk = (gd->bus_clk * 2); #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 4c9c96d783..d2a21c3279 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -91,10 +91,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -116,7 +116,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index 8f72ef567f..d21d82fef7 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -132,11 +132,11 @@ int print_cpuinfo(void) if (cpu_model) printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", - cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK)); + cpu_model, prn, strmhz(buf, CFG_SYS_CLK)); else printf("CPU: Unknown - Freescale ColdFire MCF5271 family" " (PIN: 0x%x) rev. %hu, at %s MHz\n", - pin, prn, strmhz(buf, CONFIG_SYS_CLK)); + pin, prn, strmhz(buf, CFG_SYS_CLK)); return 0; } @@ -284,7 +284,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; }; #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -370,7 +370,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ @@ -394,7 +394,7 @@ int print_cpuinfo(void) unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CLK)); + strmhz(buf, CFG_SYS_CLK)); if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", diff --git a/arch/m68k/cpu/mcf52x2/cpu_init.c b/arch/m68k/cpu/mcf52x2/cpu_init.c index 9d4a10f028..99eb61f167 100644 --- a/arch/m68k/cpu/mcf52x2/cpu_init.c +++ b/arch/m68k/cpu/mcf52x2/cpu_init.c @@ -36,31 +36,31 @@ void init_fbcs(void) { fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ && defined(CONFIG_SYS_CS4_CTRL)) @@ -214,9 +214,9 @@ void cpu_init_f(void) init_fbcs(); #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG = - CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG = + CFG_SYS_I2C_PINMUX_REG & CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #ifdef CONFIG_SYS_I2C2_OFFSET CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR; CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET; @@ -335,21 +335,21 @@ void cpu_init_f(void) * already initialized. */ #ifndef CONFIG_MONITOR_IS_IN_RAM - sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR); + sysctrl_t *sysctrl = (sysctrl_t *) (CFG_SYS_MBAR); gpio_t *gpio = (gpio_t *) (MMAP_GPIO); csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); - out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR); - out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR); + out_be16(&sysctrl->sc_scr, CFG_SYS_SCR); + out_be16(&sysctrl->sc_spr, CFG_SYS_SPR); /* Setup Ports: */ - out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT); - out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR); - out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT); - out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT); - out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR); - out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT); - out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT); + out_be32(&gpio->gpio_pacnt, CFG_SYS_PACNT); + out_be16(&gpio->gpio_paddr, CFG_SYS_PADDR); + out_be16(&gpio->gpio_padat, CFG_SYS_PADAT); + out_be32(&gpio->gpio_pbcnt, CFG_SYS_PBCNT); + out_be16(&gpio->gpio_pbddr, CFG_SYS_PBDDR); + out_be16(&gpio->gpio_pbdat, CFG_SYS_PBDAT); + out_be32(&gpio->gpio_pdcnt, CFG_SYS_PDCNT); /* Memory Controller: */ out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM); @@ -472,8 +472,8 @@ void cpu_init_f(void) #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ #ifdef CONFIG_SYS_I2C_FSL - CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR; - CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET; + CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR; + CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET; #endif /* enable instruction cache now */ @@ -560,8 +560,8 @@ void cpu_init_f(void) #ifndef CONFIG_MONITOR_IS_IN_RAM /* Set speed /PLL */ MCFCLOCK_SYNCR = - MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) | - MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD); + MCFCLOCK_SYNCR_MFD(CFG_SYS_MFD) | + MCFCLOCK_SYNCR_RFD(CFG_SYS_RFD); while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; MCFGPIO_PBCDPAR = 0xc0; @@ -573,17 +573,17 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PFPAR MCFGPIO_PFPAR = CONFIG_SYS_PFPAR; #endif -#ifdef CONFIG_SYS_PJPAR - MCFGPIO_PJPAR = CONFIG_SYS_PJPAR; +#ifdef CFG_SYS_PJPAR + MCFGPIO_PJPAR = CFG_SYS_PJPAR; #endif #ifdef CONFIG_SYS_PSDPAR MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR; #endif -#ifdef CONFIG_SYS_PASPAR - MCFGPIO_PASPAR = CONFIG_SYS_PASPAR; +#ifdef CFG_SYS_PASPAR + MCFGPIO_PASPAR = CFG_SYS_PASPAR; #endif -#ifdef CONFIG_SYS_PEHLPAR - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; +#ifdef CFG_SYS_PEHLPAR + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; #endif #ifdef CONFIG_SYS_PQSPAR MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR; @@ -600,15 +600,15 @@ void cpu_init_f(void) #ifdef CONFIG_SYS_PTDPAR MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR; #endif -#ifdef CONFIG_SYS_PUAPAR - MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR; +#ifdef CFG_SYS_PUAPAR + MCFGPIO_PUAPAR = CFG_SYS_PUAPAR; #endif #if defined(CONFIG_SYS_DDRD) MCFGPIO_DDRD = CONFIG_SYS_DDRD; #endif -#ifdef CONFIG_SYS_DDRUA - MCFGPIO_DDRUA = CONFIG_SYS_DDRUA; +#ifdef CFG_SYS_DDRUA + MCFGPIO_DDRUA = CFG_SYS_DDRUA; #endif /* FlexBus Chipselect */ @@ -652,10 +652,10 @@ int fecpin_setclear(fec_info_t *info, int setclear) { if (setclear) { MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR = CFG_SYS_PEHLPAR; } else { MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR; + MCFGPIO_PEHLPAR &= ~CFG_SYS_PEHLPAR; } return 0; } @@ -678,12 +678,12 @@ void cpu_init_f(void) * which is their primary function. * ~Jeremy */ - mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC); - mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC); - mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN); - mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN); - mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT); - mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT); + mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC); + mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC); + mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN); + mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN); + mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT); + mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT); /* * dBug Compliance: diff --git a/arch/m68k/cpu/mcf52x2/speed.c b/arch/m68k/cpu/mcf52x2/speed.c index 045908a13d..6c7628252b 100644 --- a/arch/m68k/cpu/mcf52x2/speed.c +++ b/arch/m68k/cpu/mcf52x2/speed.c @@ -23,19 +23,19 @@ int get_clocks(void) #if defined(CONFIG_M5208) pll_t *pll = (pll_t *) MMAP_PLL; - out_8(&pll->odr, CONFIG_SYS_PLL_ODR); - out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); + out_8(&pll->odr, CFG_SYS_PLL_ODR); + out_8(&pll->fdr, CFG_SYS_PLL_FDR); #endif #if defined(CONFIG_M5249) || defined(CONFIG_M5253) volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); unsigned long pllcr; -#ifndef CONFIG_SYS_PLL_BYPASS +#ifndef CFG_SYS_PLL_BYPASS #ifdef CONFIG_M5249 /* Setup the PLL to run at the specified speed */ -#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ #else pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ @@ -43,7 +43,7 @@ int get_clocks(void) #endif /* CONFIG_M5249 */ #ifdef CONFIG_M5253 - pllcr = CONFIG_SYS_PLLCR; + pllcr = CFG_SYS_PLLCR; #endif /* CONFIG_M5253 */ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ @@ -52,7 +52,7 @@ int get_clocks(void) pllcr ^= 0x00000001; /* Set pll bypass to 1 */ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ udelay(0x20); /* Wait for a lock ... */ -#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */ +#endif /* #ifndef CFG_SYS_PLL_BYPASS */ #endif /* CONFIG_M5249 || CONFIG_M5253 */ @@ -68,7 +68,7 @@ int get_clocks(void) ; #endif - gd->cpu_clk = CONFIG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CLK; #if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \ defined(CONFIG_M5271) || defined(CONFIG_M5275) gd->bus_clk = gd->cpu_clk / 2; diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index 6dddbe76f3..d48d0192ee 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -35,7 +35,7 @@ */ _vectors: .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -81,9 +81,9 @@ _vectors: .text -#if defined(CONFIG_SYS_INT_FLASH_BASE) && \ +#if defined(CFG_SYS_INT_FLASH_BASE) && \ (defined(CONFIG_M5282) || defined(CONFIG_M5281)) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ .long 0xFFFFFFFF /* all sectors protected */ .long 0x00000000 /* supervisor/User restriction */ @@ -100,53 +100,53 @@ _start: #if defined(CONFIG_M5208) /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR /*** The 5249 has MBAR2 as well ***/ -#ifdef CONFIG_SYS_MBAR2 +#ifdef CFG_SYS_MBAR2 /* Get MBAR2 address */ - move.l #(CONFIG_SYS_MBAR2 + 1), %d0 + move.l #(CFG_SYS_MBAR2 + 1), %d0 /* Set MBAR2 */ movec %d0, #0xc0e #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* Initialize RAMBAR1: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #if defined(CONFIG_M5282) -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) /* * Setup code in SRAM to initialize FLASHBAR, * if start from internal Flash */ - move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 + move.l #(_flashbar_setup-CFG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CFG_SYS_INT_FLASH_BASE), %a1 + move.l #(CFG_SYS_INIT_RAM_ADDR), %a2 _copy_flash: move.l (%a0)+, (%a2)+ cmp.l %a0, %a1 bgt.s _copy_flash - jmp CONFIG_SYS_INIT_RAM_ADDR + jmp CFG_SYS_INIT_RAM_ADDR _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: @@ -154,9 +154,9 @@ _flashbar_setup_end: _after_flashbar_copy: #else /* Setup code to initialize FLASHBAR, if start from external Memory */ - move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 + move.l #(CFG_SYS_INT_FLASH_BASE + CFG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR -#endif /* (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */ +#endif /* (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) */ #endif #endif @@ -165,22 +165,22 @@ _after_flashbar_copy: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) -#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - move.l #CONFIG_SYS_INT_FLASH_BASE, %d0 +#if defined(CONFIG_M5282) && (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) + move.l #CFG_SYS_INT_FLASH_BASE, %d0 #else - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 #endif movec %d0, %VBR #endif #ifdef CONFIG_M5275 /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* movec %d0, %MBAR */ /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 0x21), %d0 movec %d0, %RAMBAR1 #endif @@ -195,7 +195,7 @@ _after_flashbar_copy: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c index 0659bf6558..53a25d8362 100644 --- a/arch/m68k/cpu/mcf530x/cpu.c +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -33,7 +33,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", - strmhz(buf, CONFIG_SYS_CPU_CLK)); + strmhz(buf, CFG_SYS_CPU_CLK)); return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c index 83529408eb..dad47d87ab 100644 --- a/arch/m68k/cpu/mcf530x/cpu_init.c +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -40,35 +40,35 @@ void init_csm(void) { csm_t *csm = (csm_t *)(MMAP_CSM); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && \ - defined(CONFIG_SYS_CS0_CTRL)) - out_be16(&csm->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&csm->csmr0, CONFIG_SYS_CS0_MASK); - out_be16(&csm->cscr0, CONFIG_SYS_CS0_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE, csm->csmr0); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && \ + defined(CFG_SYS_CS0_CTRL)) + out_be16(&csm->csar0, CFG_SYS_CS0_BASE); + out_be32(&csm->csmr0, CFG_SYS_CS0_MASK); + out_be16(&csm->cscr0, CFG_SYS_CS0_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS0_BASE, csm->csmr0); #else #warning "Chip Select 0 are not initialized/used" #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && \ - defined(CONFIG_SYS_CS1_CTRL)) - out_be16(&csm->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&csm->csmr1, CONFIG_SYS_CS1_MASK); - out_be16(&csm->cscr1, CONFIG_SYS_CS1_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE, csm->csmr1); +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && \ + defined(CFG_SYS_CS1_CTRL)) + out_be16(&csm->csar1, CFG_SYS_CS1_BASE); + out_be32(&csm->csmr1, CFG_SYS_CS1_MASK); + out_be16(&csm->cscr1, CFG_SYS_CS1_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS1_BASE, csm->csmr1); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && \ - defined(CONFIG_SYS_CS2_CTRL)) - out_be16(&csm->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&csm->csmr2, CONFIG_SYS_CS2_MASK); - out_be16(&csm->cscr2, CONFIG_SYS_CS2_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE, csm->csmr2); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && \ + defined(CFG_SYS_CS2_CTRL)) + out_be16(&csm->csar2, CFG_SYS_CS2_BASE); + out_be32(&csm->csmr2, CFG_SYS_CS2_MASK); + out_be16(&csm->cscr2, CFG_SYS_CS2_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS2_BASE, csm->csmr2); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && \ - defined(CONFIG_SYS_CS3_CTRL)) - out_be16(&csm->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&csm->csmr3, CONFIG_SYS_CS3_MASK); - out_be16(&csm->cscr3, CONFIG_SYS_CS3_CTRL); - MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE, csm->csmr3); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && \ + defined(CFG_SYS_CS3_CTRL)) + out_be16(&csm->csar3, CFG_SYS_CS3_BASE); + out_be32(&csm->csmr3, CFG_SYS_CS3_MASK); + out_be16(&csm->cscr3, CFG_SYS_CS3_CTRL); + MCF5307_SP_ERR_FIX(CFG_SYS_CS3_BASE, csm->csmr3); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && \ defined(CONFIG_SYS_CS4_CTRL)) diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c index 03d9abeb18..c8d079016f 100644 --- a/arch/m68k/cpu/mcf530x/speed.c +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -16,8 +16,8 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #if defined(CONFIG_M5307) - gd->bus_clk = CONFIG_SYS_CLK; - gd->cpu_clk = CONFIG_SYS_CPU_CLK; + gd->bus_clk = CFG_SYS_CLK; + gd->cpu_clk = CFG_SYS_CPU_CLK; #endif return 0; diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index 644c372bdd..dbe2b54e41 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -39,7 +39,7 @@ _vectors: /* Flash offset is 0 until we setup CS0 */ .long 0x00000000 #if defined(CONFIG_M5307) && \ - (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) + (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) .long _start - CONFIG_TEXT_BASE #else .long _START @@ -92,10 +92,10 @@ _start: move.w #0x2700,%sr /* set MBAR address + valid flag */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 + move.l #(CFG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + 1), %d0 move.c %d0, %RAMBAR /* DS 4.8.2 (Cache Organization) invalidate and disable cache */ @@ -110,7 +110,7 @@ _start: * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif @@ -125,7 +125,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 1dadffd4ca..8a48d73475 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -131,7 +131,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); #ifdef CONFIG_M5329 out_be16(&wdp->mr, wdog_module / 8192); #else diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c index 1311f3967c..844d2cd760 100644 --- a/arch/m68k/cpu/mcf532x/cpu_init.c +++ b/arch/m68k/cpu/mcf532x/cpu_init.c @@ -37,34 +37,34 @@ void cpu_init_f(void) out_be32(&scm1->pacrf, 0); out_be32(&scm1->pacrg, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0); - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -102,8 +102,8 @@ int cpu_init_r(void) rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE); rtcex_t *rtcex = (rtcex_t *) &rtc->extended; - out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT); - out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP); + out_be32(&rtcex->gocu, CFG_SYS_RTC_CNT); + out_be32(&rtcex->gocl, CFG_SYS_RTC_SETUP); #endif #ifdef CONFIG_MCFFEC @@ -236,36 +236,36 @@ void cpu_init_f(void) /* Port configuration */ out_8(&gpio->par_cs, 0); -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ - && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) \ + && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ - && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) \ + && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ setbits_8(&gpio->par_cs, GPIO_PAR_CS1); - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ - && defined(CONFIG_SYS_CS2_CTRL)) +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) \ + && defined(CFG_SYS_CS2_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS2); - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ - && defined(CONFIG_SYS_CS3_CTRL)) +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) \ + && defined(CFG_SYS_CS3_CTRL)) setbits_8(&gpio->par_cs, GPIO_PAR_CS3); - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ @@ -327,7 +327,7 @@ void uart_port_conf(int port) clrbits_8(&gpio->par_feci2c, 0x00ff); setbits_8(&gpio->par_feci2c, GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2); -#elif defined(CONFIG_SYS_UART2_ALT3_GPIO) +#elif defined(CFG_SYS_UART2_ALT3_GPIO) clrbits_be16(&gpio->par_ssi, 0x0f00); setbits_be16(&gpio->par_ssi, GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2)); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index dac2229f72..32ffac0813 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -252,7 +252,7 @@ int clock_pll(int fsys, int flags) /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ int get_clocks(void) { - gd->bus_clk = clock_pll(CONFIG_SYS_CLK / 1000, 0) * 1000; + gd->bus_clk = clock_pll(CFG_SYS_CLK / 1000, 0) * 1000; gd->cpu_clk = (gd->bus_clk * 3); #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index 2672891916..72a2f99b7d 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -98,11 +98,11 @@ _start: #if !defined(CONFIG_MONITOR_IS_IN_RAM) /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* invalidate and disable cache */ @@ -131,7 +131,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c index 9b3f9f0fe1..1ce244872f 100644 --- a/arch/m68k/cpu/mcf5445x/cpu_init.c +++ b/arch/m68k/cpu/mcf5445x/cpu_init.c @@ -29,30 +29,30 @@ void init_fbcs(void) fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS; #if !defined(CONFIG_SERIAL_BOOT) -#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); - out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); - out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); +#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL)) + out_be32(&fbcs->csar0, CFG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CFG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK); #endif #endif -#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) +#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL)) /* Latch chipselect */ - out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); - out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); - out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); + out_be32(&fbcs->csar1, CFG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CFG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK); #endif -#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); - out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); - out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); +#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL)) + out_be32(&fbcs->csar2, CFG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CFG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK); #endif -#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); - out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); - out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); +#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL)) + out_be32(&fbcs->csar3, CFG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CFG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) @@ -208,14 +208,14 @@ void cpu_init_f(void) /* FlexBus Chipselect */ init_fbcs(); -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* * now the flash base address is no longer at 0 (Newer ColdFire family * boot at address 0 instead of 0xFFnn_nnnn). The vector table must * also move to the new location. */ - if (CONFIG_SYS_CS0_BASE != 0) - setvbr(CONFIG_SYS_CS0_BASE); + if (CFG_SYS_CS0_BASE != 0) + setvbr(CFG_SYS_CS0_BASE); #endif icache_enable(); diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index aea8f3090f..a083c3d45d 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -27,10 +27,10 @@ #if defined(CONFIG_SERIAL_BOOT) #define ASM_DRAMINIT (asm_dram_init - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_TEXT_BASE) #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_TEXT_BASE + \ - CONFIG_SYS_INIT_RAM_ADDR) + CFG_SYS_INIT_RAM_ADDR) #endif .text @@ -123,18 +123,18 @@ asm_dram_init: #ifdef CONFIG_SYS_NAND_BOOT /* for assembly stack */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- #endif #ifdef CONFIG_CF_SBF - move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0 + move.l #CFG_SYS_INIT_RAM_ADDR, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -145,7 +145,7 @@ asm_dram_init: move.l %d0, (%a2) /* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -153,17 +153,17 @@ asm_dram_init: movec %d0, %ACR2 movec %d0, %ACR3 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_SP_OFFSET), %sp clr.l %sp@- -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif #endif /* CONFIG_CF_SBF */ @@ -216,8 +216,8 @@ asm_dspi_init: move.l (%a1)+, %d5 move.l (%a1), %a4 - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0 - move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SYS_SBFHDR_SIZE), %d4 move.l #0xFC05C02C, %a1 /* dspi status */ @@ -334,14 +334,14 @@ asm_nand_init: movec %d0, %ACR2 movec %d0, %ACR3 -#ifdef CONFIG_SYS_CS0_BASE +#ifdef CFG_SYS_CS0_BASE /* Must disable global address */ move.l #0xFC008000, %a1 - move.l #(CONFIG_SYS_CS0_BASE), (%a1) + move.l #(CFG_SYS_CS0_BASE), (%a1) move.l #0xFC008008, %a1 - move.l #(CONFIG_SYS_CS0_CTRL), (%a1) + move.l #(CFG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 - move.l #(CONFIG_SYS_CS0_MASK), (%a1) + move.l #(CFG_SYS_CS0_MASK), (%a1) #endif /* NAND port configuration */ @@ -442,10 +442,10 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ - move.l #CONFIG_SYS_FLASH_BASE, %d0 + move.l #CFG_SYS_FLASH_BASE, %d0 movec %d0, %VBR - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 /* initialize general use internal ram */ @@ -456,7 +456,7 @@ _start: move.l %d0, (%a2) /* invalidate and disable cache */ - move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 + move.l #(CFG_SYS_ICACHE_INV + CFG_SYS_DCACHE_INV), %d0 movec %d0, %CACR /* Invalidate cache */ move.l #0, %d0 movec %d0, %ACR0 @@ -464,7 +464,7 @@ _start: movec %d0, %ACR2 movec %d0, %ACR3 #else - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 #endif @@ -472,7 +472,7 @@ _start: move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index ceb462f438..c05356fc93 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -135,28 +135,28 @@ #endif /* CONFIG_CF_V4 */ -#ifndef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_ICACR 0 +#ifndef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_ICACR 0 #endif -#ifndef CONFIG_SYS_CACHE_DCACR -#ifdef CONFIG_SYS_CACHE_ICACR -#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR +#ifndef CFG_SYS_CACHE_DCACR +#ifdef CFG_SYS_CACHE_ICACR +#define CFG_SYS_CACHE_DCACR CFG_SYS_CACHE_ICACR #else -#define CONFIG_SYS_CACHE_DCACR 0 +#define CFG_SYS_CACHE_DCACR 0 #endif #endif -#ifndef CONFIG_SYS_CACHE_ACR0 -#define CONFIG_SYS_CACHE_ACR0 0 +#ifndef CFG_SYS_CACHE_ACR0 +#define CFG_SYS_CACHE_ACR0 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR1 -#define CONFIG_SYS_CACHE_ACR1 0 +#ifndef CFG_SYS_CACHE_ACR1 +#define CFG_SYS_CACHE_ACR1 0 #endif -#ifndef CONFIG_SYS_CACHE_ACR2 -#define CONFIG_SYS_CACHE_ACR2 0 +#ifndef CFG_SYS_CACHE_ACR2 +#define CFG_SYS_CACHE_ACR2 0 #endif #ifndef CONFIG_SYS_CACHE_ACR3 diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 672aa0bb14..dab8b26a70 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -14,7 +14,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -37,7 +37,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -59,7 +59,7 @@ #include #include -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -82,7 +82,7 @@ #include #include -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -105,7 +105,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -128,7 +128,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -152,7 +152,7 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (192) @@ -175,7 +175,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) #define CONFIG_SYS_NUM_IRQS (128) @@ -198,7 +198,7 @@ #include #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x40)) + (CFG_SYS_UART_PORT * 0x40)) #define CONFIG_SYS_INTR_BASE (MMAP_INTC) #define CONFIG_SYS_NUM_IRQS (64) @@ -223,7 +223,7 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -246,7 +246,7 @@ #include #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000)) /* Timer */ #ifdef CONFIG_MCFTMR @@ -271,12 +271,12 @@ #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) -#if (CONFIG_SYS_UART_PORT < 4) +#if (CFG_SYS_UART_PORT < 4) #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ - (CONFIG_SYS_UART_PORT * 0x4000)) + (CFG_SYS_UART_PORT * 0x4000)) #else #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ - ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) + ((CFG_SYS_UART_PORT - 4) * 0x4000)) #endif #define MMAP_DSPI MMAP_DSPI0 @@ -320,7 +320,7 @@ #define FEC1_TX_INIT 31 #endif -#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) @@ -339,7 +339,7 @@ #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) #define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) -#define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) +#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR) #define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/include/asm/immap_520x.h b/arch/m68k/include/asm/immap_520x.h index bb1237453f..7c7443b968 100644 --- a/arch/m68k/include/asm/immap_520x.h +++ b/arch/m68k/include/asm/immap_520x.h @@ -9,32 +9,32 @@ #ifndef __IMMAP_520X__ #define __IMMAP_520X__ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000A8000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000) #include #include diff --git a/arch/m68k/include/asm/immap_5235.h b/arch/m68k/include/asm/immap_5235.h index 27d905ef94..a1825c2a94 100644 --- a/arch/m68k/include/asm/immap_5235.h +++ b/arch/m68k/include/asm/immap_5235.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5235__ #define __IMMAP_5235__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) #include #include diff --git a/arch/m68k/include/asm/immap_5249.h b/arch/m68k/include/asm/immap_5249.h index b599ca6e81..aa4c3ef42f 100644 --- a/arch/m68k/include/asm/immap_5249.h +++ b/arch/m68k/include/asm/immap_5249.h @@ -8,13 +8,13 @@ #ifndef __IMMAP_5249__ #define __IMMAP_5249__ -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) #include #include diff --git a/arch/m68k/include/asm/immap_5253.h b/arch/m68k/include/asm/immap_5253.h index 883782aa97..1ab7243dfd 100644 --- a/arch/m68k/include/asm/immap_5253.h +++ b/arch/m68k/include/asm/immap_5253.h @@ -9,20 +9,20 @@ #ifndef __IMMAP_5253__ #define __IMMAP_5253__ -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_I2C0 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x00010000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x00011000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_I2C0 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000400) +#define MMAP_CAN0 (CFG_SYS_MBAR + 0x00010000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x00011000) -#define MMAP_PAR (CONFIG_SYS_MBAR2 + 0x0000019C) -#define MMAP_I2C1 (CONFIG_SYS_MBAR2 + 0x00000440) -#define MMAP_UART2 (CONFIG_SYS_MBAR2 + 0x00000C00) +#define MMAP_PAR (CFG_SYS_MBAR2 + 0x0000019C) +#define MMAP_I2C1 (CFG_SYS_MBAR2 + 0x00000440) +#define MMAP_UART2 (CFG_SYS_MBAR2 + 0x00000C00) #include #include diff --git a/arch/m68k/include/asm/immap_5271.h b/arch/m68k/include/asm/immap_5271.h index 27d7861399..a5bf18c4b8 100644 --- a/arch/m68k/include/asm/immap_5271.h +++ b/arch/m68k/include/asm/immap_5271.h @@ -9,42 +9,42 @@ #ifndef __IMMAP_5271__ #define __IMMAP_5271__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN1 (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_ETPU (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CAN2 (CFG_SYS_MBAR + 0x001F0000) #include #include diff --git a/arch/m68k/include/asm/immap_5272.h b/arch/m68k/include/asm/immap_5272.h index cd7b67256c..c5c3cc7512 100644 --- a/arch/m68k/include/asm/immap_5272.h +++ b/arch/m68k/include/asm/immap_5272.h @@ -8,24 +8,24 @@ #ifndef __IMMAP_5272__ #define __IMMAP_5272__ -#define MMAP_CFG (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000020) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x000000A0) -#define MMAP_PWM (CONFIG_SYS_MBAR + 0x000000C0) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x000000E0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_TMR0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_TMR1 (CONFIG_SYS_MBAR + 0x00000220) -#define MMAP_TMR2 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_TMR3 (CONFIG_SYS_MBAR + 0x00000260) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_PLIC (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00000840) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x00001000) +#define MMAP_CFG (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000020) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000040) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000080) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x000000A0) +#define MMAP_PWM (CFG_SYS_MBAR + 0x000000C0) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x000000E0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000180) +#define MMAP_TMR0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_TMR1 (CFG_SYS_MBAR + 0x00000220) +#define MMAP_TMR2 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_TMR3 (CFG_SYS_MBAR + 0x00000260) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00000280) +#define MMAP_PLIC (CFG_SYS_MBAR + 0x00000300) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00000840) +#define MMAP_USB (CFG_SYS_MBAR + 0x00001000) #include diff --git a/arch/m68k/include/asm/immap_5275.h b/arch/m68k/include/asm/immap_5275.h index 8b1a08b4f2..9b8d71d30d 100644 --- a/arch/m68k/include/asm/immap_5275.h +++ b/arch/m68k/include/asm/immap_5275.h @@ -10,44 +10,44 @@ #ifndef __IMMAP_5275__ #define __IMMAP_5275__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800) -#define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000110) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000120) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x00000130) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FEC0FIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00001800) +#define MMAP_FEC1FIFO (CFG_SYS_MBAR + 0x00001C00) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110004) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_MDHA (CFG_SYS_MBAR + 0x00190000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_SKHA (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_USB (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_PWM0 (CFG_SYS_MBAR + 0x001D0000) #include #include diff --git a/arch/m68k/include/asm/immap_5282.h b/arch/m68k/include/asm/immap_5282.h index d7c68f5749..f810a4dd5c 100644 --- a/arch/m68k/include/asm/immap_5282.h +++ b/arch/m68k/include/asm/immap_5282.h @@ -8,42 +8,42 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ -#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_SDRAMC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) -#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) -#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) -#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) -#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) -#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) -#define MMAP_QADC (CONFIG_SYS_MBAR + 0x00190000) -#define MMAP_GPTMRA (CONFIG_SYS_MBAR + 0x001A0000) -#define MMAP_GPTMRB (CONFIG_SYS_MBAR + 0x001B0000) -#define MMAP_CAN (CONFIG_SYS_MBAR + 0x001C0000) -#define MMAP_CFMC (CONFIG_SYS_MBAR + 0x001D0000) -#define MMAP_CFMMEM (CONFIG_SYS_MBAR + 0x04000000) +#define MMAP_SCM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_SDRAMC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DMA0 (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DMA1 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DMA2 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_DMA3 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000240) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00000280) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00000300) +#define MMAP_QSPI (CFG_SYS_MBAR + 0x00000340) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000400) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000440) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00000480) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x000004C0) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00000C00) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x00000D00) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00000F00) +#define MMAP_FEC (CFG_SYS_MBAR + 0x00001000) +#define MMAP_FECFIFO (CFG_SYS_MBAR + 0x00001400) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00100000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x00110000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x00120000) +#define MMAP_EPORT (CFG_SYS_MBAR + 0x00130000) +#define MMAP_WDOG (CFG_SYS_MBAR + 0x00140000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00150000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00160000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00170000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x00180000) +#define MMAP_QADC (CFG_SYS_MBAR + 0x00190000) +#define MMAP_GPTMRA (CFG_SYS_MBAR + 0x001A0000) +#define MMAP_GPTMRB (CFG_SYS_MBAR + 0x001B0000) +#define MMAP_CAN (CFG_SYS_MBAR + 0x001C0000) +#define MMAP_CFMC (CFG_SYS_MBAR + 0x001D0000) +#define MMAP_CFMMEM (CFG_SYS_MBAR + 0x04000000) #include #include diff --git a/arch/m68k/include/asm/immap_5301x.h b/arch/m68k/include/asm/immap_5301x.h index 29e60863bf..e1f7858b10 100644 --- a/arch/m68k/include/asm/immap_5301x.h +++ b/arch/m68k/include/asm/immap_5301x.h @@ -9,46 +9,46 @@ #ifndef __IMMAP_5301X__ #define __IMMAP_5301X__ -#define MMAP_SCM1 (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_XBS (CONFIG_SYS_MBAR + 0x00004000) -#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00008000) -#define MMAP_MPU (CONFIG_SYS_MBAR + 0x00014000) -#define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00030000) -#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00034000) -#define MMAP_SCM2 (CONFIG_SYS_MBAR + 0x00040000) -#define MMAP_EDMA (CONFIG_SYS_MBAR + 0x00044000) -#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00048000) -#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x0004C000) -#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00054000) -#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00058000) -#define MMAP_DSPI (CONFIG_SYS_MBAR + 0x0005C000) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00060000) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00064000) -#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00068000) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00070000) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00074000) -#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00078000) -#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x0007C000) -#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00080000) -#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00084000) -#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00088000) -#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x0008C000) -#define MMAP_EPORT0 (CONFIG_SYS_MBAR + 0x00090000) -#define MMAP_EPORT1 (CONFIG_SYS_MBAR + 0x00094000) -#define MMAP_VOICOD (CONFIG_SYS_MBAR + 0x0009C000) -#define MMAP_RCM (CONFIG_SYS_MBAR + 0x000A0000) -#define MMAP_CCM (CONFIG_SYS_MBAR + 0x000A0004) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x000A4000) -#define MMAP_RTC (CONFIG_SYS_MBAR + 0x000A8000) -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x000AC000) -#define MMAP_USBOTG (CONFIG_SYS_MBAR + 0x000B0000) -#define MMAP_USBH (CONFIG_SYS_MBAR + 0x000B4000) -#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x000B8000) -#define MMAP_SSI (CONFIG_SYS_MBAR + 0x000BC000) -#define MMAP_PLL (CONFIG_SYS_MBAR + 0x000C0000) -#define MMAP_RNG (CONFIG_SYS_MBAR + 0x000C4000) -#define MMAP_IIM (CONFIG_SYS_MBAR + 0x000C8000) -#define MMAP_ESDHC (CONFIG_SYS_MBAR + 0x000CC000) +#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000) +#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000) +#define MMAP_MPU (CFG_SYS_MBAR + 0x00014000) +#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000) +#define MMAP_FEC1 (CFG_SYS_MBAR + 0x00034000) +#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000) +#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000) +#define MMAP_INTC1 (CFG_SYS_MBAR + 0x0004C000) +#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000) +#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000) +#define MMAP_DSPI (CFG_SYS_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000) +#define MMAP_PIT2 (CFG_SYS_MBAR + 0x00088000) +#define MMAP_PIT3 (CFG_SYS_MBAR + 0x0008C000) +#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00090000) +#define MMAP_EPORT1 (CFG_SYS_MBAR + 0x00094000) +#define MMAP_VOICOD (CFG_SYS_MBAR + 0x0009C000) +#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000) +#define MMAP_RTC (CFG_SYS_MBAR + 0x000A8000) +#define MMAP_SIM (CFG_SYS_MBAR + 0x000AC000) +#define MMAP_USBOTG (CFG_SYS_MBAR + 0x000B0000) +#define MMAP_USBH (CFG_SYS_MBAR + 0x000B4000) +#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000B8000) +#define MMAP_SSI (CFG_SYS_MBAR + 0x000BC000) +#define MMAP_PLL (CFG_SYS_MBAR + 0x000C0000) +#define MMAP_RNG (CFG_SYS_MBAR + 0x000C4000) +#define MMAP_IIM (CFG_SYS_MBAR + 0x000C8000) +#define MMAP_ESDHC (CFG_SYS_MBAR + 0x000CC000) #include #include diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h index 930e0899e8..d6442d95b4 100644 --- a/arch/m68k/include/asm/immap_5307.h +++ b/arch/m68k/include/asm/immap_5307.h @@ -7,15 +7,15 @@ #ifndef __IMMAP_5307__ #define __IMMAP_5307__ -#define MMAP_SIM (CONFIG_SYS_MBAR + 0x00000000) -#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) -#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) -#define MMAP_DRAMC (CONFIG_SYS_MBAR + 0x00000100) -#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) -#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) -#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) -#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) -#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000244) +#define MMAP_SIM (CFG_SYS_MBAR + 0x00000000) +#define MMAP_INTC (CFG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CFG_SYS_MBAR + 0x00000080) +#define MMAP_DRAMC (CFG_SYS_MBAR + 0x00000100) +#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CFG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CFG_SYS_MBAR + 0x00000200) +#define MMAP_GPIO (CFG_SYS_MBAR + 0x00000244) typedef struct sim { u8 rsr; diff --git a/arch/m68k/include/asm/m5249.h b/arch/m68k/include/asm/m5249.h index 9303629e4b..afafb4e547 100644 --- a/arch/m68k/include/asm/m5249.h +++ b/arch/m68k/include/asm/m5249.h @@ -14,14 +14,14 @@ /* * useful definitions for reading/writing MBAR offset memory */ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y -#define mbar2_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) -#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR2 + x)) = y -#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR2 + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y +#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) +#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR2 + x)) = y +#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR2 + x)) = y /* * Size of internal RAM diff --git a/arch/m68k/include/asm/m5271.h b/arch/m68k/include/asm/m5271.h index 7ebeddbb68..e63b42c00d 100644 --- a/arch/m68k/include/asm/m5271.h +++ b/arch/m68k/include/asm/m5271.h @@ -11,12 +11,12 @@ #ifndef _MCF5271_H_ #define _MCF5271_H_ -#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) -#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) -#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) -#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y -#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_readLong(x) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) +#define mbar_readShort(x) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) +#define mbar_readByte(x) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_SYS_MBAR + x)) = y #define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 diff --git a/arch/m68k/include/asm/m5282.h b/arch/m68k/include/asm/m5282.h index 0c91cf491e..180f20386f 100644 --- a/arch/m68k/include/asm/m5282.h +++ b/arch/m68k/include/asm/m5282.h @@ -108,112 +108,112 @@ /* General Purpose I/O Module GPIO */ -#define MCFGPIO_PORTA (*(vu_char *) (CONFIG_SYS_MBAR+0x100000)) -#define MCFGPIO_PORTB (*(vu_char *) (CONFIG_SYS_MBAR+0x100001)) -#define MCFGPIO_PORTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100002)) -#define MCFGPIO_PORTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100003)) -#define MCFGPIO_PORTE (*(vu_char *) (CONFIG_SYS_MBAR+0x100004)) -#define MCFGPIO_PORTF (*(vu_char *) (CONFIG_SYS_MBAR+0x100005)) -#define MCFGPIO_PORTG (*(vu_char *) (CONFIG_SYS_MBAR+0x100006)) -#define MCFGPIO_PORTH (*(vu_char *) (CONFIG_SYS_MBAR+0x100007)) -#define MCFGPIO_PORTJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100008)) -#define MCFGPIO_PORTDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100009)) -#define MCFGPIO_PORTEH (*(vu_char *) (CONFIG_SYS_MBAR+0x10000A)) -#define MCFGPIO_PORTEL (*(vu_char *) (CONFIG_SYS_MBAR+0x10000B)) -#define MCFGPIO_PORTAS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000C)) -#define MCFGPIO_PORTQS (*(vu_char *) (CONFIG_SYS_MBAR+0x10000D)) -#define MCFGPIO_PORTSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10000E)) -#define MCFGPIO_PORTTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10000F)) -#define MCFGPIO_PORTTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100010)) -#define MCFGPIO_PORTUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100011)) +#define MCFGPIO_PORTA (*(vu_char *) (CFG_SYS_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CFG_SYS_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CFG_SYS_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CFG_SYS_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CFG_SYS_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CFG_SYS_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CFG_SYS_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CFG_SYS_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CFG_SYS_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CFG_SYS_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CFG_SYS_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CFG_SYS_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CFG_SYS_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CFG_SYS_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CFG_SYS_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CFG_SYS_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CFG_SYS_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CFG_SYS_MBAR+0x100011)) -#define MCFGPIO_DDRA (*(vu_char *) (CONFIG_SYS_MBAR+0x100014)) -#define MCFGPIO_DDRB (*(vu_char *) (CONFIG_SYS_MBAR+0x100015)) -#define MCFGPIO_DDRC (*(vu_char *) (CONFIG_SYS_MBAR+0x100016)) -#define MCFGPIO_DDRD (*(vu_char *) (CONFIG_SYS_MBAR+0x100017)) -#define MCFGPIO_DDRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100018)) -#define MCFGPIO_DDRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100019)) -#define MCFGPIO_DDRG (*(vu_char *) (CONFIG_SYS_MBAR+0x10001A)) -#define MCFGPIO_DDRH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001B)) -#define MCFGPIO_DDRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x10001C)) -#define MCFGPIO_DDRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x10001D)) -#define MCFGPIO_DDREH (*(vu_char *) (CONFIG_SYS_MBAR+0x10001E)) -#define MCFGPIO_DDREL (*(vu_char *) (CONFIG_SYS_MBAR+0x10001F)) -#define MCFGPIO_DDRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100020)) -#define MCFGPIO_DDRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100021)) -#define MCFGPIO_DDRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100022)) -#define MCFGPIO_DDRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100023)) -#define MCFGPIO_DDRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100024)) -#define MCFGPIO_DDRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100025)) +#define MCFGPIO_DDRA (*(vu_char *) (CFG_SYS_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CFG_SYS_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CFG_SYS_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CFG_SYS_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CFG_SYS_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CFG_SYS_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CFG_SYS_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CFG_SYS_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CFG_SYS_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CFG_SYS_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CFG_SYS_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CFG_SYS_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CFG_SYS_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CFG_SYS_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CFG_SYS_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CFG_SYS_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CFG_SYS_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CFG_SYS_MBAR+0x100025)) -#define MCFGPIO_PORTAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_PORTBP (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_PORTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_PORTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_PORTEP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_PORTFP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_PORTGP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_PORTHP (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_PORTJP (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_PORTDDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_PORTEHP (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_PORTELP (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_PORTASP (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_PORTQSP (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_PORTSDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_PORTTCP (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_PORTTDP (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_PORTUAP (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) +#define MCFGPIO_PORTAP (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_SYS_MBAR+0x100039)) -#define MCFGPIO_SETA (*(vu_char *) (CONFIG_SYS_MBAR+0x100028)) -#define MCFGPIO_SETB (*(vu_char *) (CONFIG_SYS_MBAR+0x100029)) -#define MCFGPIO_SETC (*(vu_char *) (CONFIG_SYS_MBAR+0x10002A)) -#define MCFGPIO_SETD (*(vu_char *) (CONFIG_SYS_MBAR+0x10002B)) -#define MCFGPIO_SETE (*(vu_char *) (CONFIG_SYS_MBAR+0x10002C)) -#define MCFGPIO_SETF (*(vu_char *) (CONFIG_SYS_MBAR+0x10002D)) -#define MCFGPIO_SETG (*(vu_char *) (CONFIG_SYS_MBAR+0x10002E)) -#define MCFGPIO_SETH (*(vu_char *) (CONFIG_SYS_MBAR+0x10002F)) -#define MCFGPIO_SETJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100030)) -#define MCFGPIO_SETDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100031)) -#define MCFGPIO_SETEH (*(vu_char *) (CONFIG_SYS_MBAR+0x100032)) -#define MCFGPIO_SETEL (*(vu_char *) (CONFIG_SYS_MBAR+0x100033)) -#define MCFGPIO_SETAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100034)) -#define MCFGPIO_SETQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100035)) -#define MCFGPIO_SETSD (*(vu_char *) (CONFIG_SYS_MBAR+0x100036)) -#define MCFGPIO_SETTC (*(vu_char *) (CONFIG_SYS_MBAR+0x100037)) -#define MCFGPIO_SETTD (*(vu_char *) (CONFIG_SYS_MBAR+0x100038)) -#define MCFGPIO_SETUA (*(vu_char *) (CONFIG_SYS_MBAR+0x100039)) +#define MCFGPIO_SETA (*(vu_char *) (CFG_SYS_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CFG_SYS_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CFG_SYS_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CFG_SYS_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CFG_SYS_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CFG_SYS_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_SYS_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_SYS_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_SYS_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_SYS_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_SYS_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_SYS_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_SYS_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_SYS_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_SYS_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_SYS_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_SYS_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_SYS_MBAR+0x100039)) -#define MCFGPIO_CLRA (*(vu_char *) (CONFIG_SYS_MBAR+0x10003C)) -#define MCFGPIO_CLRB (*(vu_char *) (CONFIG_SYS_MBAR+0x10003D)) -#define MCFGPIO_CLRC (*(vu_char *) (CONFIG_SYS_MBAR+0x10003E)) -#define MCFGPIO_CLRD (*(vu_char *) (CONFIG_SYS_MBAR+0x10003F)) -#define MCFGPIO_CLRE (*(vu_char *) (CONFIG_SYS_MBAR+0x100040)) -#define MCFGPIO_CLRF (*(vu_char *) (CONFIG_SYS_MBAR+0x100041)) -#define MCFGPIO_CLRG (*(vu_char *) (CONFIG_SYS_MBAR+0x100042)) -#define MCFGPIO_CLRH (*(vu_char *) (CONFIG_SYS_MBAR+0x100043)) -#define MCFGPIO_CLRJ (*(vu_char *) (CONFIG_SYS_MBAR+0x100044)) -#define MCFGPIO_CLRDD (*(vu_char *) (CONFIG_SYS_MBAR+0x100045)) -#define MCFGPIO_CLREH (*(vu_char *) (CONFIG_SYS_MBAR+0x100046)) -#define MCFGPIO_CLREL (*(vu_char *) (CONFIG_SYS_MBAR+0x100047)) -#define MCFGPIO_CLRAS (*(vu_char *) (CONFIG_SYS_MBAR+0x100048)) -#define MCFGPIO_CLRQS (*(vu_char *) (CONFIG_SYS_MBAR+0x100049)) -#define MCFGPIO_CLRSD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004A)) -#define MCFGPIO_CLRTC (*(vu_char *) (CONFIG_SYS_MBAR+0x10004B)) -#define MCFGPIO_CLRTD (*(vu_char *) (CONFIG_SYS_MBAR+0x10004C)) -#define MCFGPIO_CLRUA (*(vu_char *) (CONFIG_SYS_MBAR+0x10004D)) +#define MCFGPIO_CLRA (*(vu_char *) (CFG_SYS_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_SYS_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_SYS_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_SYS_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_SYS_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_SYS_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_SYS_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_SYS_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_SYS_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_SYS_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_SYS_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_SYS_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_SYS_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_SYS_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_SYS_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_SYS_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_SYS_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_SYS_MBAR+0x10004D)) -#define MCFGPIO_PBCDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100050)) -#define MCFGPIO_PFPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100051)) -#define MCFGPIO_PEPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100052)) -#define MCFGPIO_PJPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100054)) -#define MCFGPIO_PSDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100055)) -#define MCFGPIO_PASPAR (*(vu_short *)(CONFIG_SYS_MBAR+0x100056)) -#define MCFGPIO_PEHLPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100058)) -#define MCFGPIO_PQSPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x100059)) -#define MCFGPIO_PTCPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005A)) -#define MCFGPIO_PTDPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005B)) -#define MCFGPIO_PUAPAR (*(vu_char *) (CONFIG_SYS_MBAR+0x10005C)) +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_SYS_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_SYS_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_SYS_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_SYS_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_SYS_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_SYS_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_SYS_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_SYS_MBAR+0x10005C)) /* Bit level definitions and macros */ #define MCFGPIO_PORT7 (0x80) @@ -310,25 +310,25 @@ /* System Conrol Module SCM */ -#define MCFSCM_RAMBAR (*(vu_long *) (CONFIG_SYS_MBAR+0x00000008)) -#define MCFSCM_CRSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000010)) -#define MCFSCM_CWCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000011)) -#define MCFSCM_LPICR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000012)) -#define MCFSCM_CWSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000013)) +#define MCFSCM_RAMBAR (*(vu_long *) (CFG_SYS_MBAR+0x00000008)) +#define MCFSCM_CRSR (*(vu_char *) (CFG_SYS_MBAR+0x00000010)) +#define MCFSCM_CWCR (*(vu_char *) (CFG_SYS_MBAR+0x00000011)) +#define MCFSCM_LPICR (*(vu_char *) (CFG_SYS_MBAR+0x00000012)) +#define MCFSCM_CWSR (*(vu_char *) (CFG_SYS_MBAR+0x00000013)) -#define MCFSCM_MPARK (*(vu_long *) (CONFIG_SYS_MBAR+0x0000001C)) -#define MCFSCM_MPR (*(vu_char *) (CONFIG_SYS_MBAR+0x00000020)) -#define MCFSCM_PACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000024)) -#define MCFSCM_PACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000025)) -#define MCFSCM_PACR2 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000026)) -#define MCFSCM_PACR3 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000027)) -#define MCFSCM_PACR4 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000028)) -#define MCFSCM_PACR5 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002A)) -#define MCFSCM_PACR6 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002B)) -#define MCFSCM_PACR7 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002C)) -#define MCFSCM_PACR8 (*(vu_char *) (CONFIG_SYS_MBAR+0x0000002E)) -#define MCFSCM_GPACR0 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000030)) -#define MCFSCM_GPACR1 (*(vu_char *) (CONFIG_SYS_MBAR+0x00000031)) +#define MCFSCM_MPARK (*(vu_long *) (CFG_SYS_MBAR+0x0000001C)) +#define MCFSCM_MPR (*(vu_char *) (CFG_SYS_MBAR+0x00000020)) +#define MCFSCM_PACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000024)) +#define MCFSCM_PACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000025)) +#define MCFSCM_PACR2 (*(vu_char *) (CFG_SYS_MBAR+0x00000026)) +#define MCFSCM_PACR3 (*(vu_char *) (CFG_SYS_MBAR+0x00000027)) +#define MCFSCM_PACR4 (*(vu_char *) (CFG_SYS_MBAR+0x00000028)) +#define MCFSCM_PACR5 (*(vu_char *) (CFG_SYS_MBAR+0x0000002A)) +#define MCFSCM_PACR6 (*(vu_char *) (CFG_SYS_MBAR+0x0000002B)) +#define MCFSCM_PACR7 (*(vu_char *) (CFG_SYS_MBAR+0x0000002C)) +#define MCFSCM_PACR8 (*(vu_char *) (CFG_SYS_MBAR+0x0000002E)) +#define MCFSCM_GPACR0 (*(vu_char *) (CFG_SYS_MBAR+0x00000030)) +#define MCFSCM_GPACR1 (*(vu_char *) (CFG_SYS_MBAR+0x00000031)) #define MCFSCM_CRSR_EXT (0x80) #define MCFSCM_CRSR_CWDR (0x20) @@ -337,8 +337,8 @@ /* Reset Controller Module RCM */ -#define MCFRESET_RCR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110000)) -#define MCFRESET_RSR (*(vu_char *) (CONFIG_SYS_MBAR+0x00110001)) +#define MCFRESET_RCR (*(vu_char *) (CFG_SYS_MBAR+0x00110000)) +#define MCFRESET_RSR (*(vu_char *) (CFG_SYS_MBAR+0x00110001)) #define MCFRESET_RCR_SOFTRST (0x80) #define MCFRESET_RCR_FRCRSTOUT (0x40) @@ -360,9 +360,9 @@ /* Chip Configuration Module CCM */ -#define MCFCCM_CCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00110004)) -#define MCFCCM_RCON (*(vu_short *)(CONFIG_SYS_MBAR+0x00110008)) -#define MCFCCM_CIR (*(vu_short *)(CONFIG_SYS_MBAR+0x0011000A)) +#define MCFCCM_CCR (*(vu_short *)(CFG_SYS_MBAR+0x00110004)) +#define MCFCCM_RCON (*(vu_short *)(CFG_SYS_MBAR+0x00110008)) +#define MCFCCM_CIR (*(vu_short *)(CFG_SYS_MBAR+0x0011000A)) /* Bit level definitions and macros */ #define MCFCCM_CCR_LOAD (0x8000) @@ -377,18 +377,18 @@ /* Clock Module */ -#define MCFCLOCK_SYNCR (*(vu_short *)(CONFIG_SYS_MBAR+0x120000)) -#define MCFCLOCK_SYNSR (*(vu_char *) (CONFIG_SYS_MBAR+0x120002)) +#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_SYS_MBAR+0x120000)) +#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_SYS_MBAR+0x120002)) #define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) #define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) #define MCFCLOCK_SYNSR_LOCK 0x08 -#define MCFSDRAMC_DCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00000040)) -#define MCFSDRAMC_DACR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000048)) -#define MCFSDRAMC_DMR0 (*(vu_long *) (CONFIG_SYS_MBAR+0x0000004c)) -#define MCFSDRAMC_DACR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000050)) -#define MCFSDRAMC_DMR1 (*(vu_long *) (CONFIG_SYS_MBAR+0x00000054)) +#define MCFSDRAMC_DCR (*(vu_short *)(CFG_SYS_MBAR+0x00000040)) +#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_SYS_MBAR+0x00000048)) +#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_SYS_MBAR+0x0000004c)) +#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000050)) +#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_SYS_MBAR+0x00000054)) #define MCFSDRAMC_DCR_NAM (0x2000) #define MCFSDRAMC_DCR_COC (0x1000) @@ -418,60 +418,60 @@ #define MCFSDRAMC_DMR_UD (0x00000002) #define MCFSDRAMC_DMR_V (0x00000001) -#define MCFWTM_WCR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140000)) -#define MCFWTM_WMR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140002)) -#define MCFWTM_WCNTR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140004)) -#define MCFWTM_WSR (*(vu_short *)(CONFIG_SYS_MBAR+0x00140006)) +#define MCFWTM_WCR (*(vu_short *)(CFG_SYS_MBAR+0x00140000)) +#define MCFWTM_WMR (*(vu_short *)(CFG_SYS_MBAR+0x00140002)) +#define MCFWTM_WCNTR (*(vu_short *)(CFG_SYS_MBAR+0x00140004)) +#define MCFWTM_WSR (*(vu_short *)(CFG_SYS_MBAR+0x00140006)) /********************************************************************* * General Purpose Timer (GPT) Module *********************************************************************/ -#define MCFGPTA_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0000)) -#define MCFGPTA_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0001)) -#define MCFGPTA_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0002)) -#define MCFGPTA_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0003)) -#define MCFGPTA_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0004)) -#define MCFGPTA_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0006)) -#define MCFGPTA_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0008)) -#define MCFGPTA_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0009)) -#define MCFGPTA_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000B)) -#define MCFGPTA_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000C)) -#define MCFGPTA_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000D)) -#define MCFGPTA_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000E)) -#define MCFGPTA_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1A000F)) -#define MCFGPTA_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0010)) -#define MCFGPTA_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0012)) -#define MCFGPTA_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0014)) -#define MCFGPTA_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1A0016)) -#define MCFGPTA_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0018)) -#define MCFGPTA_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1A0019)) -#define MCFGPTA_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1A001A)) -#define MCFGPTA_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001D)) -#define MCFGPTA_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1A001E)) +#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1A0000)) +#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1A0001)) +#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1A0002)) +#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1A0003)) +#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1A0004)) +#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0006)) +#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1A0008)) +#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1A0009)) +#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000B)) +#define MCFGPTA_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1A000C)) +#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000D)) +#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1A000E)) +#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1A000F)) +#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1A0010)) +#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1A0012)) +#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1A0014)) +#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1A0016)) +#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1A0018)) +#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1A0019)) +#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1A001A)) +#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1A001D)) +#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1A001E)) -#define MCFGPTB_GPTIOS (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0000)) -#define MCFGPTB_GPTCFORC (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0001)) -#define MCFGPTB_GPTOC3M (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0002)) -#define MCFGPTB_GPTOC3D (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0003)) -#define MCFGPTB_GPTCNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0004)) -#define MCFGPTB_GPTSCR1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0006)) -#define MCFGPTB_GPTTOV (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0008)) -#define MCFGPTB_GPTCTL1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0009)) -#define MCFGPTB_GPTCTL2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000B)) -#define MCFGPTB_GPTIE (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000C)) -#define MCFGPTB_GPTSCR2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000D)) -#define MCFGPTB_GPTFLG1 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000E)) -#define MCFGPTB_GPTFLG2 (*(vu_char *)(CONFIG_SYS_MBAR+0x1B000F)) -#define MCFGPTB_GPTC0 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0010)) -#define MCFGPTB_GPTC1 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0012)) -#define MCFGPTB_GPTC2 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0014)) -#define MCFGPTB_GPTC3 (*(vu_short *)(CONFIG_SYS_MBAR+0x1B0016)) -#define MCFGPTB_GPTPACTL (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0018)) -#define MCFGPTB_GPTPAFLG (*(vu_char *)(CONFIG_SYS_MBAR+0x1B0019)) -#define MCFGPTB_GPTPACNT (*(vu_short *)(CONFIG_SYS_MBAR+0x1B001A)) -#define MCFGPTB_GPTPORT (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001D)) -#define MCFGPTB_GPTDDR (*(vu_char *)(CONFIG_SYS_MBAR+0x1B001E)) +#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_SYS_MBAR+0x1B0000)) +#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_SYS_MBAR+0x1B0001)) +#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_SYS_MBAR+0x1B0002)) +#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_SYS_MBAR+0x1B0003)) +#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_SYS_MBAR+0x1B0004)) +#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0006)) +#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_SYS_MBAR+0x1B0008)) +#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_SYS_MBAR+0x1B0009)) +#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000B)) +#define MCFGPTB_GPTIE (*(vu_char *)(CFG_SYS_MBAR+0x1B000C)) +#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000D)) +#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_SYS_MBAR+0x1B000E)) +#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_SYS_MBAR+0x1B000F)) +#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_SYS_MBAR+0x1B0010)) +#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_SYS_MBAR+0x1B0012)) +#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_SYS_MBAR+0x1B0014)) +#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_SYS_MBAR+0x1B0016)) +#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_SYS_MBAR+0x1B0018)) +#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_SYS_MBAR+0x1B0019)) +#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_SYS_MBAR+0x1B001A)) +#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_SYS_MBAR+0x1B001D)) +#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_SYS_MBAR+0x1B001E)) /* Bit level definitions and macros */ #define MCFGPT_GPTIOS_IOS3 (0x08) @@ -556,7 +556,7 @@ /* Coldfire Flash Module CFM */ -#define MCFCFM_MCR (*(vu_short *)(CONFIG_SYS_MBAR+0x1D0000)) +#define MCFCFM_MCR (*(vu_short *)(CFG_SYS_MBAR+0x1D0000)) #define MCFCFM_MCR_LOCK (0x0400) #define MCFCFM_MCR_PVIE (0x0200) #define MCFCFM_MCR_AEIE (0x0100) @@ -564,23 +564,23 @@ #define MCFCFM_MCR_CCIE (0x0040) #define MCFCFM_MCR_KEYACC (0x0020) -#define MCFCFM_CLKD (*(vu_char *)(CONFIG_SYS_MBAR+0x1D0002)) +#define MCFCFM_CLKD (*(vu_char *)(CFG_SYS_MBAR+0x1D0002)) -#define MCFCFM_SEC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0008)) +#define MCFCFM_SEC (*(vu_long*) (CFG_SYS_MBAR+0x1D0008)) #define MCFCFM_SEC_KEYEN (0x80000000) #define MCFCFM_SEC_SECSTAT (0x40000000) -#define MCFCFM_PROT (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0010)) -#define MCFCFM_SACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0014)) -#define MCFCFM_DACC (*(vu_long*) (CONFIG_SYS_MBAR+0x1D0018)) -#define MCFCFM_USTAT (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0020)) +#define MCFCFM_PROT (*(vu_long*) (CFG_SYS_MBAR+0x1D0010)) +#define MCFCFM_SACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0014)) +#define MCFCFM_DACC (*(vu_long*) (CFG_SYS_MBAR+0x1D0018)) +#define MCFCFM_USTAT (*(vu_char*) (CFG_SYS_MBAR+0x1D0020)) #define MCFCFM_USTAT_CBEIF 0x80 #define MCFCFM_USTAT_CCIF 0x40 #define MCFCFM_USTAT_PVIOL 0x20 #define MCFCFM_USTAT_ACCERR 0x10 #define MCFCFM_USTAT_BLANK 0x04 -#define MCFCFM_CMD (*(vu_char*) (CONFIG_SYS_MBAR+0x1D0024)) +#define MCFCFM_CMD (*(vu_char*) (CFG_SYS_MBAR+0x1D0024)) #define MCFCFM_CMD_ERSVER 0x05 #define MCFCFM_CMD_PGERSVER 0x06 #define MCFCFM_CMD_PGM 0x20 diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c index 7eca6725a6..0b4629f1c8 100644 --- a/arch/m68k/lib/bdinfo.c +++ b/arch/m68k/lib/bdinfo.c @@ -16,7 +16,7 @@ int arch_setup_bdinfo(void) { struct bd_info *bd = gd->bd; - bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ + bd->bi_mbar_base = CFG_SYS_MBAR; /* base of internal registers */ bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ @@ -38,7 +38,7 @@ void arch_print_bdinfo(void) struct bd_info *bd = gd->bd; bdinfo_print_mhz("busfreq", bd->bi_busfreq); -#if defined(CONFIG_SYS_MBAR) +#if defined(CFG_SYS_MBAR) bdinfo_print_num_l("mbar", bd->bi_mbar_base); #endif bdinfo_print_mhz("cpufreq", bd->bi_intfreq); diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c index aa2b93e0e0..4ddda69f5a 100644 --- a/arch/m68k/lib/cache.c +++ b/arch/m68k/lib/cache.c @@ -34,18 +34,18 @@ void icache_enable(void) *cf_icache_status = 1; #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2)); + __asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2)); __asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6)); __asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7)); #endif #else - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #endif - __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_ICACR)); } void icache_disable(void) @@ -72,9 +72,9 @@ void icache_invalid(void) { u32 temp; - temp = CONFIG_SYS_ICACHE_INV; + temp = CFG_SYS_ICACHE_INV; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR; __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); } @@ -89,15 +89,15 @@ void dcache_enable(void) *cf_dcache_status = 1; #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) - __asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0)); - __asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1)); + __asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0)); + __asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1)); #if defined(CONFIG_CF_V4E) __asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4)); __asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5)); #endif #endif - __asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR)); + __asm__ __volatile__("movec %0, %%cacr"::"r"(CFG_SYS_CACHE_DCACR)); } void dcache_disable(void) @@ -124,11 +124,11 @@ void dcache_invalid(void) #if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E) u32 temp; - temp = CONFIG_SYS_DCACHE_INV; + temp = CFG_SYS_DCACHE_INV; if (*cf_dcache_status) - temp |= CONFIG_SYS_CACHE_DCACR; + temp |= CFG_SYS_CACHE_DCACR; if (*cf_icache_status) - temp |= CONFIG_SYS_CACHE_ICACR; + temp |= CFG_SYS_CACHE_ICACR; __asm__ __volatile__("movec %0, %%cacr"::"r"(temp)); #endif diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 6b9f253952..7063f32610 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -19,7 +19,7 @@ #ifndef CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) + CFG_SYS_INIT_SP_OFFSET) #endif #define SP_ADDR_TEMP 0xbe10dff0 diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 33835eeec2..63c2729411 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -77,10 +77,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ SCCR_TSECCM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ SCCR_TSEC1CM | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ SCCR_TSEC2CM | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ @@ -92,10 +92,10 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ SCCR_USBMPHCM | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ SCCR_USBDRCM | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ SCCR_SATACM | #endif 0; @@ -115,11 +115,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ - (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ + (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ - (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | +#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ + (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | #endif #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | @@ -130,11 +130,11 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ - (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | +#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ + (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | #endif -#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ - (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | +#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ + (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | #endif 0; @@ -175,26 +175,26 @@ void cpu_init_f (volatile immap_t * im) setbits_be32(&im->sysconf.spcr, SPCR_TBEN); /* System General Purpose Register */ -#ifdef CONFIG_SYS_SICRH +#ifdef CFG_SYS_SICRH #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ - __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, + __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH, &im->sysconf.sicrh); #else - __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); + __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh); #endif #endif -#ifdef CONFIG_SYS_SICRL - __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); +#ifdef CFG_SYS_SICRL + __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl); #endif -#ifdef CONFIG_SYS_GPR1 - __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); +#ifdef CFG_SYS_GPR1 + __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1); #endif -#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ - __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); +#ifdef CFG_SYS_DDRCDR /* DDR control driver register */ + __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr); #endif -#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ - __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); +#ifdef CFG_SYS_OBIR /* Output buffer impedance register */ + __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir); #endif #if !defined(CONFIG_PINCTRL) diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 6d1c6b055c..4f982b8303 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -59,9 +59,9 @@ void board_add_ram_info(int use_default) printf(", %s MHz)", strmhz(buf, gd->mem_clk)); -#if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE) +#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE) puts("\nSDRAM: "); - print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); + print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)"); #endif } @@ -204,12 +204,12 @@ long int spd_sdram() return 0; } -#ifdef CONFIG_SYS_DDRCDR_VALUE +#ifdef CFG_SYS_DDRCDR_VALUE /* * Adjust DDR II IO voltage biasing. It just makes it work. */ if(spd.mem_type == SPD_MEMTYPE_DDR2) { - immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; } udelay(50000); #endif @@ -693,7 +693,7 @@ long int spd_sdram() ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ -#ifdef CONFIG_SYS_DDR_MODE_WEAK +#ifdef CFG_SYS_DDR_MODE_WEAK | (1 << (16 + 1)) /* weak driver (~60%) */ #endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ @@ -767,8 +767,8 @@ long int spd_sdram() debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2); } -#ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; +#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */ + ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; #endif debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl); diff --git a/arch/powerpc/cpu/mpc83xx/spl_minimal.c b/arch/powerpc/cpu/mpc83xx/spl_minimal.c index 8fcf20854e..7cc0383afb 100644 --- a/arch/powerpc/cpu/mpc83xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc83xx/spl_minimal.c @@ -54,12 +54,12 @@ void cpu_init_f (volatile immap_t * im) im->sysconf.spcr |= SPCR_TBEN; /* DDR control driver register */ -#ifdef CONFIG_SYS_DDRCDR - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; +#ifdef CFG_SYS_DDRCDR + im->sysconf.ddrcdr = CFG_SYS_DDRCDR; #endif /* Output buffer impedance register */ -#ifdef CONFIG_SYS_OBIR - im->sysconf.obir = CONFIG_SYS_OBIR; +#ifdef CFG_SYS_OBIR + im->sysconf.obir = CFG_SYS_OBIR; #endif /* diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 8a351b927c..52326f0ec1 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -246,7 +246,7 @@ in_flash: #if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif @@ -486,7 +486,7 @@ init_e300_core: /* time t 10 */ #if defined(CONFIG_WATCHDOG) /* Initialise the Watchdog values and reset it (if req) */ /*------------------------------------------------------*/ - lis r4, CONFIG_SYS_WATCHDOG_VALUE + lis r4, CFG_SYS_WATCHDOG_VALUE ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) stw r4, SWCRR(r3) @@ -1048,10 +1048,10 @@ trap_init: lock_ram_in_cache: /* Allocate Initial RAM in data cache. */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: dcbz r0, r3 @@ -1070,10 +1070,10 @@ lock_ram_in_cache: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 + lis r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR & ~31)@l + li r4, ((CFG_SYS_INIT_RAM_SIZE & ~31) + \ + (CFG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 mtctr r4 1: icbi r0, r3 dcbi r0, r3 @@ -1122,14 +1122,14 @@ map_flash_by_law1: * LBIU Local Access Widow 0 will not cover this memory space. So, we * need another window to map in it. */ - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR1 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b @@ -1150,24 +1150,24 @@ remap_flash_by_law0: lwz r4, BR0(r3) li r5, 0x7FFF and r4, r4, r5 - lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h - ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l + lis r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@h + ori r5, r5, (CFG_SYS_FLASH_BASE & 0xFFFF8000)@l or r5, r5, r4 - stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ + stw r5, BR0(r3) /* r5 <= (CFG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ lwz r4, OR0(r3) - lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1) + lis r5, ~((CFG_SYS_FLASH_SIZE << 4) - 1) or r4, r4, r5 stw r4, OR0(r3) - lis r4, (CONFIG_SYS_FLASH_BASE)@h - ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l - stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */ + lis r4, (CFG_SYS_FLASH_BASE)@h + ori r4, r4, (CFG_SYS_FLASH_BASE)@l + stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_SYS_FLASH_BASE */ - /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */ + /* Store 0x80000012 + log2(CFG_SYS_FLASH_SIZE) into LBLAWAR0 */ lis r4, (0x80000012)@h ori r4, r4, (0x80000012)@l - li r5, CONFIG_SYS_FLASH_SIZE + li r5, CFG_SYS_FLASH_SIZE 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */ addi r4, r4, 1 bne 1b diff --git a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h index f8c2f104c1..b2f98074fc 100644 --- a/arch/powerpc/cpu/mpc83xx/sysio/sysio.h +++ b/arch/powerpc/cpu/mpc83xx/sysio/sysio.h @@ -1,7 +1,7 @@ #ifdef CONFIG_ARCH_MPC8308 -#ifndef CONFIG_SYS_SICRL -#define CONFIG_SYS_SICRL (\ +#ifndef CFG_SYS_SICRL +#define CFG_SYS_SICRL (\ CONFIG_SICRL_SPI |\ CONFIG_SICRL_UART |\ CONFIG_SICRL_IRQ |\ @@ -10,8 +10,8 @@ ) #endif -#ifndef CONFIG_SYS_SICRH -#define CONFIG_SYS_SICRH (\ +#ifndef CFG_SYS_SICRH +#define CFG_SYS_SICRH (\ CONFIG_SICRH_ESDHC_A |\ CONFIG_SICRH_ESDHC_B |\ CONFIG_SICRH_ESDHC_C |\ diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 3dccc0e106..013a171ed8 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ed890114ec..c7d473d4a1 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -23,7 +23,7 @@ */ static void check_erratum_a4849(uint32_t svr) { - void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; + void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000; unsigned int i; #if defined(CONFIG_ARCH_P2041) || defined(CONFIG_ARCH_P3041) @@ -120,7 +120,7 @@ static void check_erratum_a4580(uint32_t svr) */ static void check_erratum_a007212(void) { - u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20); if (in_be32(plldgdcr) & 0x1fe) { /* check if PLL ratio is set by workaround */ diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 6acd31d284..74ad7483dc 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -417,7 +417,7 @@ void print_reginfo(void) /* Common ddr init for non-corenet fsl 85xx platforms */ #ifndef CONFIG_FSL_CORENET #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \ - !defined(CONFIG_SYS_INIT_L2_ADDR) + !defined(CFG_SYS_INIT_L2_ADDR) int dram_init(void) { #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \ @@ -486,7 +486,7 @@ int dram_init(void) #endif /* CONFIG_SYS_RAMBOOT */ #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CONFIG_POST & CFG_SYS_POST_MEMORY /* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, @@ -591,7 +591,7 @@ static void dump_spd_ddr_reg(void) /* invalid the TLBs for DDR and setup new ones to cover p_addr */ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; int ddr_esel; @@ -624,8 +624,8 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); #if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) test_cap = p_size; #else test_cap = gd->ram_size; @@ -635,7 +635,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; printf("Testing 0x%08llx - 0x%08llx\n", (u64)(*vstart) + (*phys_offset), @@ -651,13 +651,13 @@ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); - *vstart = CONFIG_SYS_DDR_SDRAM_BASE; + *vstart = CFG_SYS_DDR_SDRAM_BASE; *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0; #if !defined(CONFIG_PHYS_64BIT) || \ - !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \ - (CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) + !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ + (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { puts("Cannot test more than "); print_size(CONFIG_MAX_MEM_MAPPED, diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c320b202e..f07e8ab388 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -165,7 +165,7 @@ void disable_cpc_sram(void) for (i = 0; i < CFG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { /* find and disable LAW of SRAM */ - struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); + struct law_entry law = find_law(CFG_SYS_INIT_L3_ADDR); if (law.index == -1) { printf("\nFatal error happened\n"); @@ -315,15 +315,15 @@ void fsl_erratum_a007212_workaround(void) { ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_pll_ratio; - u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); - u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); - u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); + u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20); + u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28); + u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2) - u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); - u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); + u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40); + u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48); #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3) - u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); - u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); + u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60); + u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68); #endif #endif /* @@ -378,7 +378,7 @@ void fsl_erratum_a007212_workaround(void) ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) @@ -403,7 +403,7 @@ ulong cpu_init_f(void) #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ - law = find_law(CONFIG_SYS_PBI_FLASH_BASE); + law = find_law(CFG_SYS_PBI_FLASH_BASE); if (law.index != -1) disable_law(law.index); @@ -430,7 +430,7 @@ ulong cpu_init_f(void) /* Invalidate the CPC before DDR gets enabled */ invalidate_cpc(); - #ifdef CONFIG_SYS_DCSRBAR_PHYS + #ifdef CFG_SYS_DCSRBAR_PHYS /* set DCSRCR so that DCSR space is 1G */ setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); in_be32(&gur->dcsrcr); @@ -533,7 +533,7 @@ int l2cache_init(void) asm("msync;isync"); cache_ctl = l2cache->l2ctl; -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L2_ADDR) if (cache_ctl & MPC85xx_L2CTL_L2E) { /* Clear L2 SRAM memory-mapped base address */ out_be32(&l2cache->l2srbar0, 0x0); @@ -590,15 +590,15 @@ int l2cache_init(void) if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { puts("already enabled"); -#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) +#if defined(CFG_SYS_INIT_L2_ADDR) && defined(CFG_SYS_FLASH_BASE) u32 l2srbar = l2cache->l2srbar0; if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE - && l2srbar >= CONFIG_SYS_FLASH_BASE) { - l2srbar = CONFIG_SYS_INIT_L2_ADDR; + && l2srbar >= CFG_SYS_FLASH_BASE) { + l2srbar = CFG_SYS_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); + printf(", moving to 0x%08x", CFG_SYS_INIT_L2_ADDR); } -#endif /* CONFIG_SYS_INIT_L2_ADDR */ +#endif /* CFG_SYS_INIT_L2_ADDR */ puts("\n"); } else { asm("msync;isync"); @@ -625,9 +625,9 @@ int l2cache_init(void) #endif /* enable the cache */ - mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + mtspr(SPRN_L2CSR0, CFG_SYS_INIT_L2CSR0); - if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { + if (CFG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) ; print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); @@ -656,7 +656,7 @@ skip_l2: int cpu_init_r(void) { __maybe_unused u32 svr = get_svr(); -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) @@ -763,13 +763,13 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { int i; - __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; + __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c; for (i = 0; i < 12; i++) { p += i + (i > 5 ? 11 : 0); out_be32(p, 0x2); } - p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; + p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108; out_be32(p, 0x34); } #endif @@ -799,18 +799,18 @@ int cpu_init_r(void) { if (SVR_MAJ(svr) < 3) { void *p; - p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; + p = (void *)CFG_SYS_DCSRBAR + 0x20520; setbits_be32(p, 1 << (31 - 14)); } } #endif -#ifdef CONFIG_SYS_LBC_LCRR +#ifdef CFG_SYS_LBC_LCRR /* * Modify the CLKDIV field of LCRR register to improve the writing * speed for NOR flash. */ - clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); + clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CFG_SYS_LBC_LCRR); __raw_readl(&lbc->lcrr); isync(); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 @@ -850,7 +850,7 @@ int cpu_init_r(void) */ if (IS_SVR_REV(get_svr(), 1, 0)) { struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) - (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); + (CFG_SYS_DCSRBAR + CFG_SYS_DCSR_DCFG_OFFSET); setbits_be32(&dcfg->ecccr1, (DCSR_DCFG_ECC_DISABLE_USB1 | DCSR_DCFG_ECC_DISABLE_USB2)); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 18bfa2aed1..a67f37e3af 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -17,15 +17,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_A003399_NOR_WORKAROUND void setup_ifc(void) { - struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc_regs = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; u32 _mas0, _mas1, _mas2, _mas3, _mas7; - phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS; + phys_addr_t flash_phys = CFG_SYS_FLASH_BASE_PHYS; /* * Adjust the TLB we were running out of to match the phys addr of the * chip select we are adjusting and will return to. */ - flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024; + flash_phys += (~CFG_SYS_AMASK0) + 1 - 4*1024*1024; _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15); _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | @@ -52,7 +52,7 @@ void setup_ifc(void) * * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * bacause flash's physical address is going to change as - * CONFIG_SYS_FLASH_BASE_PHYS. + * CFG_SYS_FLASH_BASE_PHYS. */ _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB); @@ -72,9 +72,9 @@ void setup_ifc(void) #endif /* Change flash's physical address */ - ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0); - ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0); - ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0); + ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CFG_SYS_CSPR0); + ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CFG_SYS_CSOR0); + ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CFG_SYS_AMASK0); return; } @@ -101,7 +101,7 @@ void cpu_init_early_f(void *fdt) #ifdef CONFIG_ARCH_QEMU_E500 /* - * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, + * CFG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems, * so we need to populate it before it accesses it. */ gd->fdt_blob = fdt; @@ -109,9 +109,9 @@ void cpu_init_early_f(void *fdt) mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13); mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M); - mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS); + mas2 = FSL_BOOKE_MAS2(CFG_SYS_CCSRBAR, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CFG_SYS_CCSRBAR_PHYS); write_tlb(mas0, mas1, mas2, mas3, mas7); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 32348b4e14..a7e1df104d 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -144,14 +144,14 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_SPL_MMC_BOOT - off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START, - CONFIG_SYS_MMC_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_MMC_U_BOOT_START, + CFG_SYS_MMC_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SD deep sleep: %s\n", fdt_strerror(off)); #elif defined(CONFIG_SPL_SPI_BOOT) - off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START, - CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE); + off = fdt_add_mem_rsv(blob, CFG_SYS_SPI_FLASH_U_BOOT_START, + CFG_SYS_SPI_FLASH_U_BOOT_SIZE); if (off < 0) printf("Failed to reserve memory for SPI deep sleep: %s\n", fdt_strerror(off)); @@ -448,7 +448,7 @@ void fdt_add_enet_stashing(void *fdt) static void ft_fixup_clks(void *blob, const char *compat, u32 offset, unsigned long freq) { - phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS; + phys_addr_t phys = offset + CFG_SYS_CCSRBAR_PHYS; int off = fdt_node_offset_by_compat_reg(blob, compat, phys); if (off >= 0) { @@ -679,17 +679,17 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) ft_fixup_dpaa_clks(blob); -#if defined(CONFIG_SYS_BMAN_MEM_PHYS) +#if defined(CFG_SYS_BMAN_MEM_PHYS) fdt_portal(blob, "fsl,bman-portal", "bman-portals", - (u64)CONFIG_SYS_BMAN_MEM_PHYS, - CONFIG_SYS_BMAN_MEM_SIZE); + (u64)CFG_SYS_BMAN_MEM_PHYS, + CFG_SYS_BMAN_MEM_SIZE); fdt_fixup_bportals(blob); #endif -#if defined(CONFIG_SYS_QMAN_MEM_PHYS) +#if defined(CFG_SYS_QMAN_MEM_PHYS) fdt_portal(blob, "fsl,qman-portal", "qman-portals", - (u64)CONFIG_SYS_QMAN_MEM_PHYS, - CONFIG_SYS_QMAN_MEM_SIZE); + (u64)CFG_SYS_QMAN_MEM_PHYS, + CFG_SYS_QMAN_MEM_SIZE); fdt_fixup_qportals(blob); #endif @@ -737,7 +737,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) * beginning of CCSR. */ #define CCSR_VIRT_TO_PHYS(x) \ - (CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR)) + (CFG_SYS_CCSRBAR_PHYS + ((x) - CFG_SYS_CCSRBAR)) static void msg(const char *name, uint64_t uaddr, uint64_t daddr) { @@ -783,8 +783,8 @@ int ft_verify_fdt(void *fdt) return 0; } - if (addr != CONFIG_SYS_CCSRBAR_PHYS) { - msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr); + if (addr != CFG_SYS_CCSRBAR_PHYS) { + msg("CCSR", CFG_SYS_CCSRBAR_PHYS, addr); /* No point in checking anything else */ return 0; } @@ -818,12 +818,12 @@ int ft_verify_fdt(void *fdt) * the 'reg' property to be wrong, so check it here. For now, we * only check for "fsl,elbc" nodes. */ -#ifdef CONFIG_SYS_LBC_ADDR +#ifdef CFG_SYS_LBC_ADDR off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc"); if (off > 0) { const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL); if (reg) { - uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR); + uint64_t uaddr = CCSR_VIRT_TO_PHYS(CFG_SYS_LBC_ADDR); addr = fdt_translate_address(fdt, off, reg); if (uaddr != addr) { diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 3a6ce32f7e..9b6577e547 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -203,7 +203,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 struct ccsr_sfp_regs __iomem *sfp_regs = - (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR); + (struct ccsr_sfp_regs __iomem *)(CFG_SYS_SFP_ADDR); u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; u32 bc_status, fc_status, dc_status, pll_sr2; serdes_corenet_t __iomem *srds_regs = (void *)sd_addr; diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 437ecde615..7c2de02c4c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -264,9 +264,9 @@ void serdes_reset_rx(enum srds_prtcl device) } #endif -#ifndef CONFIG_SYS_DCSRBAR_PHYS -#define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ -#define CONFIG_SYS_DCSRBAR 0x80000000 +#ifndef CFG_SYS_DCSRBAR_PHYS +#define CFG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ +#define CFG_SYS_DCSRBAR 0x80000000 #define __DCSR_NOT_DEFINED_BY_CONFIG #endif @@ -315,16 +315,16 @@ static void enable_bank(ccsr_gur_t *gur, int bank) */ { #ifdef __DCSR_NOT_DEFINED_BY_CONFIG - struct law_entry law = find_law(CONFIG_SYS_DCSRBAR_PHYS); + struct law_entry law = find_law(CFG_SYS_DCSRBAR_PHYS); int law_index; if (law.index == -1) - law_index = set_next_law(CONFIG_SYS_DCSRBAR_PHYS, + law_index = set_next_law(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); else - set_law(law.index, CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, + set_law(law.index, CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_DCSR); #endif - u32 *p = (void *)CONFIG_SYS_DCSRBAR + 0x20114; + u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114; out_be32(p, rcw5); #ifdef __DCSR_NOT_DEFINED_BY_CONFIG if (law.index == -1) diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 2b790868e1..540a6e6e19 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7db05d9672..8f645258a5 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index ba54b0310a..db41116202 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO( 1, 2, 1, 0), SET_QP_INFO( 3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 6f11c81aba..bd05eae255 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 2, 1, 0), SET_QP_INFO(3, 4, 2, 1), diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S index d37e1ccf1e..391751ce1e 100644 --- a/arch/powerpc/cpu/mpc85xx/release.S +++ b/arch/powerpc/cpu/mpc85xx/release.S @@ -276,8 +276,8 @@ __secondary_start_page: mtspr SPRN_L2CSR1,r3 #endif - lis r3,CONFIG_SYS_INIT_L2CSR0@h - ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l + lis r3,CFG_SYS_INIT_L2CSR0@h + ori r3,r3,CFG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 isync 2: diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index e2bdc2f9f1..a6e352ceab 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -218,22 +218,22 @@ void get_sys_info(sys_info_t *sys_info) #ifndef CONFIG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK]; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK]; break; case 2: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 2; break; case 3: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 3; break; case 4: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK] / 4; break; case 6: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 2; break; case 7: - sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3; + sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK + 1] / 3; break; default: printf("Error: Unknown PME clock select!\n"); @@ -243,7 +243,7 @@ void get_sys_info(sys_info_t *sys_info) } #else - sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK; + sys_info->freq_pme = sys_info->freq_systembus / CFG_SYS_PME_CLK; #endif #endif @@ -380,25 +380,25 @@ void get_sys_info(sys_info_t *sys_info) #ifndef CONFIG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK]; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK]; break; case 2: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 2; break; case 3: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 3; break; case 4: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK] / 4; break; case 5: sys_info->freq_fman[0] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 2; break; case 7: - sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3; + sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK + 1] / 3; break; default: printf("Error: Unknown FMan1 clock select!\n"); @@ -407,31 +407,31 @@ void get_sys_info(sys_info_t *sys_info) break; } #if (CFG_SYS_NUM_FMAN) == 2 -#ifdef CONFIG_SYS_FM2_CLK +#ifdef CFG_SYS_FM2_CLK #define FM2_CLK_SEL 0x00000038 #define FM2_CLK_SHIFT 3 rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) { case 1: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1]; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1]; break; case 2: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 2; break; case 3: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 3; break; case 4: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK + 1] / 4; break; case 5: sys_info->freq_fman[1] = sys_info->freq_systembus; break; case 6: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 2; break; case 7: - sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3; + sys_info->freq_fman[1] = freq_c_pll[CFG_SYS_FM2_CLK] / 3; break; default: printf("Error: Unknown FMan2 clock select!\n"); @@ -442,7 +442,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #endif /* CFG_SYS_NUM_FMAN == 2 */ #else - sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK; + sys_info->freq_fman[0] = sys_info->freq_systembus / CFG_SYS_FM1_CLK; #endif #endif diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 47df3c2ce1..ce2b9c2166 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -14,10 +14,10 @@ DECLARE_GLOBAL_DATA_PTR; ulong cpu_init_f(void) { -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; - out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR); /* set MBECCDIS=1, SBECCDIS=1 */ out_be32(&l2cache->l2errdis, diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 5341756974..562b6993b9 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -128,7 +128,7 @@ bootsect: .Lconf_pair_start: .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ - .long CONFIG_SYS_INIT_L2_ADDR + .long CFG_SYS_INIT_L2_ADDR .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC @@ -428,12 +428,12 @@ l2_disabled: mtspr SPRN_BUCSR,r0 #endif -#if defined(CONFIG_SYS_INIT_DBCR) +#if defined(CFG_SYS_INIT_DBCR) lis r1,0xffff ori r1,r1,0xffff mtspr DBSR,r1 /* Clear all status bits */ - lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ - ori r0,r0,CONFIG_SYS_INIT_DBCR@l + lis r0,CFG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */ + ori r0,r0,CFG_SYS_INIT_DBCR@l mtspr DBCR0,r0 #endif @@ -573,34 +573,34 @@ nexti: mflr r1 /* R1 = our PC */ * As a general rule, TLB0 is used for short-term TLBs, and TLB1 is used for * long-term TLBs, so we use TLB0 here. */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) -#if !defined(CONFIG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CONFIG_SYS_CCSRBAR_PHYS_LOW) -#error "CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW) must be defined." +#if !defined(CFG_SYS_CCSRBAR_PHYS_HIGH) || !defined(CFG_SYS_CCSRBAR_PHYS_LOW) +#error "CFG_SYS_CCSRBAR_PHYS_HIGH and CFG_SYS_CCSRBAR_PHYS_LOW) must be defined." #endif create_ccsr_new_tlb: /* * Create a TLB for the new location of CCSR. Register R8 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR). */ - lis r8, CONFIG_SYS_CCSRBAR@h - ori r8, r8, CONFIG_SYS_CCSRBAR@l - lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h - ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l + lis r8, CFG_SYS_CCSRBAR@h + ori r8, r8, CFG_SYS_CCSRBAR@l + lis r9, (CFG_SYS_CCSRBAR + 0x1000)@h + ori r9, r9, (CFG_SYS_CCSRBAR + 0x1000)@l create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 /* * Create a TLB for the current location of CCSR. Register R9 is reserved - * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). + * for the virtual address of this TLB (CFG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: create_tlb0_entry 1, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ 0, r3 /* The default CCSR address is always a 32-bit number */ @@ -634,7 +634,7 @@ infinite_debug_loop: #ifdef CONFIG_FSL_CORENET -#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define CCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_4K 0xb #define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K) #define CCSRAR_C 0x80000000 /* Commit */ @@ -644,10 +644,10 @@ create_temp_law: * On CoreNet systems, we create the temporary LAW using a special LAW * target ID of 0x1e. LAWBARH is at offset 0xc00 in CCSR. */ - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRBAR_LAWAR@h ori r2, r2, CCSRBAR_LAWAR@l @@ -683,10 +683,10 @@ read_old_ccsrbar: * instruction. */ write_new_ccsrbar: - lis r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r0, r0, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l - lis r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@h - ori r1, r1, CONFIG_SYS_CCSRBAR_PHYS_LOW@l + lis r0, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r0, r0, CFG_SYS_CCSRBAR_PHYS_HIGH@l + lis r1, CFG_SYS_CCSRBAR_PHYS_LOW@h + ori r1, r1, CFG_SYS_CCSRBAR_PHYS_LOW@l lis r2, CCSRAR_C@h ori r2, r2, CCSRAR_C@l @@ -723,9 +723,9 @@ write_new_ccsrbar: lwz r0, 0(r9) isync -/* CONFIG_SYS_CCSRBAR_PHYS right shifted by 12 */ -#define CCSRBAR_PHYS_RS12 ((CONFIG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ - (CONFIG_SYS_CCSRBAR_PHYS_LOW >> 12)) +/* CFG_SYS_CCSRBAR_PHYS right shifted by 12 */ +#define CCSRBAR_PHYS_RS12 ((CFG_SYS_CCSRBAR_PHYS_HIGH << 20) | \ + (CFG_SYS_CCSRBAR_PHYS_LOW >> 12)) /* Write the new value to CCSRBAR. */ lis r0, CCSRBAR_PHYS_RS12@h @@ -752,10 +752,10 @@ write_new_ccsrbar: /* Delete the temporary TLBs */ delete_temp_tlbs: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 - delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 1, CFG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3 -#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */ +#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CFG_SYS_CCSRBAR_PHYS) */ #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) create_ccsr_l2_tlb: @@ -765,14 +765,14 @@ create_ccsr_l2_tlb: */ create_tlb0_entry 0, \ 0, BOOKE_PAGESZ_4K, \ - CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ - CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3 + CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ + CFG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ + CFG_SYS_CCSRBAR_PHYS_HIGH, r3 enable_l2_cluster_l2: /* enable L2 cache */ - lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h - ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l + lis r3, (CFG_SYS_CCSRBAR + 0xC20000)@h + ori r3, r3, (CFG_SYS_CCSRBAR + 0xC20000)@l li r4, 33 /* stash id */ stw r4, 4(r3) lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h @@ -813,7 +813,7 @@ enable_l2_cluster_l2: beq 1b delete_ccsr_l2_tlb: - delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 + delete_tlb0_entry 0, CFG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif /* @@ -863,7 +863,7 @@ delete_ccsr_l2_tlb: andi. r1,r3,L1CSR0_DCE@l beq 2b #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 -#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000) +#define DCSR_LAWBARH0 (CFG_SYS_CCSRBAR + 0x1000) #define LAW_SIZE_1M 0x13 #define DCSRBAR_LAWAR (LAW_EN | (0x1d << 20) | LAW_SIZE_1M) @@ -884,13 +884,13 @@ delete_ccsr_l2_tlb: rlwimi r0, r8, 16, MAS0_ESEL_MSK lis r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@h ori r1, r1, FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)@l - lis r7, CONFIG_SYS_CCSRBAR@h - ori r7, r7, CONFIG_SYS_CCSRBAR@l + lis r7, CFG_SYS_CCSRBAR@h + ori r7, r7, CFG_SYS_CCSRBAR@l ori r2, r7, MAS2_I|MAS2_G - lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h - ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l - lis r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h - ori r4, r4, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l + lis r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h + ori r3, r3, FSL_BOOKE_MAS3(CFG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l + lis r4, CFG_SYS_CCSRBAR_PHYS_HIGH@h + ori r4, r4, CFG_SYS_CCSRBAR_PHYS_HIGH@l mtspr MAS0, r0 mtspr MAS1, r1 mtspr MAS2, r2 @@ -1132,7 +1132,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 /* @@ -1148,7 +1148,7 @@ create_init_ram_area: create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_VAL(SYS_MONITOR_BASE) & 0xfff00000, MAS2_I|MAS2_G, \ - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #else @@ -1164,19 +1164,19 @@ create_init_ram_area: #endif /* create a temp mapping in AS=1 to the stack */ -#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ - defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) +#if defined(CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ + defined(CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH) create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6 #else create_tlb1_entry 14, \ 1, BOOKE_PAGESZ_16K, \ - CONFIG_SYS_INIT_RAM_ADDR, 0, \ - CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ + CFG_SYS_INIT_RAM_ADDR, 0, \ + CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 #endif @@ -1194,8 +1194,8 @@ switch_as: /* Allocate Initial RAM in data cache. */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l mfspr r2, L1CFG0 andi. r2, r2, 0x1ff /* cache size * 1024 / (2 * L1 line size) */ @@ -1230,11 +1230,11 @@ switch_as: .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ + lis r3,(CFG_SYS_INIT_RAM_ADDR)@h + ori r3,r3,((CFG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ #if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CFG_SYS_INIT_RAM_SIZE #error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif @@ -1243,8 +1243,8 @@ _start_cont: #endif /* End of RAM */ - lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h - ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l + lis r4,(CFG_SYS_INIT_RAM_ADDR)@h + ori r4,r4,(CFG_SYS_INIT_RAM_SIZE)@l li r0,0 @@ -1826,8 +1826,8 @@ trap_init: .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ - lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h - ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l + lis r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h + ori r3,r3,(CFG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l mfspr r4,L1CFG0 andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) @@ -1844,8 +1844,8 @@ unlock_ram_in_cache: sync /* Invalidate the TLB entries for the cache */ - lis r3,CONFIG_SYS_INIT_RAM_ADDR@h - ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l + lis r3,CFG_SYS_INIT_RAM_ADDR@h + ori r3,r3,CFG_SYS_INIT_RAM_ADDR@l tlbivax 0,r3 addi r3,r3,0x1000 tlbivax 0,r3 diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c index d2744bb9f8..bab076b2b1 100644 --- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index 99b52bacda..59f4f9c669 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 17521dc3a4..390bb11537 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 8fe4e96a11..37ea7788cc 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -8,7 +8,7 @@ #include #ifdef CONFIG_SYS_DPAA_QBMAN -struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { +struct qportal_info qp_info[CFG_SYS_QMAN_NUM_PORTALS] = { /* dqrr liodn, frame data liodn, liodn off, sdest */ SET_QP_INFO(1, 27, 1, 0), SET_QP_INFO(2, 28, 1, 0), diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 81e60722f9..5d21bef587 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -302,7 +302,7 @@ uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size, unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; + unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE; u64 memsize = (u64)memsize_in_meg << 20; u64 size; @@ -324,13 +324,13 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { return - setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } /* Invalidate the DDR TLBs for the requested size */ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { - u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE; + u32 vstart = CFG_SYS_DDR_SDRAM_BASE; unsigned long epn; u32 tsize, valid, ptr; phys_addr_t rpn = 0; @@ -351,7 +351,7 @@ void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) void clear_ddr_tlbs(unsigned int memsize_in_meg) { - clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg); + clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg); } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index f28826c5d1..d918b4395b 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -64,7 +64,7 @@ SECTIONS _end = .; #if CONFIG_IS_ENABLED(SYS_MPC85XX_NO_RESETVEC) -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif @@ -101,7 +101,7 @@ SECTIONS .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff -#if defined(CONFIG_SDCARD) && !defined(CONFIG_SYS_MMC_U_BOOT_OFFS) +#if defined(CONFIG_SDCARD) && !defined(CFG_SYS_MMC_U_BOOT_OFFS) mmc_u_boot_offs = .; #endif #endif diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 0ebb7b33a8..1f1107e61d 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -141,8 +141,8 @@ in_flash: mtspr DER, r2 /* set up the stack on top of internal DPRAM */ - lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l stw r0, -4(r3) stw r0, -8(r3) addi r1, r3, -8 diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 1101b9138f..1c051d1898 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -230,7 +230,7 @@ static int pamu_config_spaace(uint32_t liodn, int pamu_init(void) { - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; u32 i = 0; u64 ppaact_phys, ppaact_lim, ppaact_size; @@ -292,7 +292,7 @@ int pamu_init(void) void pamu_enable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { setbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE); @@ -304,7 +304,7 @@ void pamu_enable(void) void pamu_reset(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; struct ccsr_pamu *regs; for (i = 0; i < CONFIG_NUM_PAMU; i++) { @@ -328,7 +328,7 @@ void pamu_reset(void) void pamu_disable(void) { u32 i = 0; - u32 base_addr = CONFIG_SYS_PAMU_ADDR; + u32 base_addr = CFG_SYS_PAMU_ADDR; for (i = 0; i < CONFIG_NUM_PAMU; i++) { diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 71496ab294..caad6670cc 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -21,17 +21,17 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; -#ifdef CONFIG_SYS_FLASH_BASE_PHYS +#ifdef CFG_SYS_FLASH_BASE_PHYS tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS); + (uint64_t)virt_to_phys((void *)CFG_SYS_FLASH_BASE_PHYS); tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; #endif -#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) +#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR)) tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + (uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR); tbl->size[i] = 256 * 1024; /* 256K CPC flash */ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2edf0d6f83..d9e5a7d621 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -43,9 +43,9 @@ #elif defined(CONFIG_ARCH_P1023) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 +#define CFG_SYS_QMAN_NUM_PORTALS 3 +#define CFG_SYS_BMAN_NUM_PORTALS 3 +#define CFG_SYS_FM_MURAM_SIZE 0x10000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) @@ -68,7 +68,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -78,7 +78,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -90,7 +90,7 @@ #define CFG_SYS_NUM_FM2_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -103,7 +103,7 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_DTSEC 5 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) @@ -134,11 +134,11 @@ #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 #define CFG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_PME_CLK 0 +#define CFG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 3 -#define CONFIG_SYS_FM2_CLK 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM1_CLK 3 +#define CFG_SYS_FM2_CLK 3 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -147,9 +147,9 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 @@ -173,11 +173,11 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_FM_PLAT_CLK_DIV 1 -#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -191,9 +191,9 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -212,10 +212,10 @@ #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif #define CONFIG_PME_PLAT_CLK_DIV 1 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5038cb9f59..a03f091c30 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -469,7 +469,7 @@ extern void print_lbc_regs(void); extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size); -#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR) #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr)) #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr)) #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index de85bcfdcf..0af3d8902a 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -70,22 +70,22 @@ extern void fdt_fixup_liodn(void *blob); { .compat[0] = name1, \ .compat[1] = name2, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3e707600f2..e8b2680206 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,11 +9,11 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#define CFG_SYS_PBI_FLASH_BASE 0xc0000000 #else -#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 +#define CFG_SYS_PBI_FLASH_BASE 0xce000000 #endif -#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000 #if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ @@ -21,18 +21,18 @@ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#undef CFG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #if defined(CONFIG_RAMBOOT_PBL) -#undef CONFIG_SYS_INIT_L3_ADDR -#ifdef CONFIG_SYS_INIT_L3_VADDR -#define CONFIG_SYS_INIT_L3_ADDR \ - (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ +#undef CFG_SYS_INIT_L3_ADDR +#ifdef CFG_SYS_INIT_L3_VADDR +#define CFG_SYS_INIT_L3_ADDR \ + (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 0xbff00000 #else -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8e18202670..19774f3053 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -871,11 +871,11 @@ struct ccsr_gpio { #define CFG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET) -#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) +#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9ae698743e..283fdf3b45 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2445,10 +2445,10 @@ struct ccsr_pman { #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ -#define CONFIG_SYS_OSPR_OFFSET 0x200 -#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#define CFG_SYS_OSPR_OFFSET 0x200 +#define CFG_SYS_SFP_OFFSET (0xE8000 + CFG_SYS_OSPR_OFFSET) #else -#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#define CFG_SYS_SFP_OFFSET 0xE8000 #endif #define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 @@ -2489,7 +2489,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CFG_SYS_FSL_SEC_OFFSET 0x300000 #define CFG_SYS_FSL_JR0_OFFSET 0x301000 -#define CONFIG_SYS_SEC_MON_OFFSET 0x314000 +#define CFG_SYS_SEC_MON_OFFSET 0x314000 #define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CFG_SYS_FSL_QMAN_OFFSET 0x318000 #define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2542,13 +2542,13 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 #ifdef CONFIG_TSECV2 -#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#define CFG_SYS_TSEC1_OFFSET 0xB0000 #elif defined(CONFIG_TSECV2_1) -#define CONFIG_SYS_TSEC1_OFFSET 0x10000 +#define CFG_SYS_TSEC1_OFFSET 0x10000 #else -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #endif -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_OFFSET 0x80000 @@ -2559,8 +2559,8 @@ struct ccsr_pman { #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 -#define CONFIG_SYS_SFP_OFFSET 0xE7000 +#define CFG_SYS_SEC_MON_OFFSET 0xE6000 +#define CFG_SYS_SFP_OFFSET 0xE7000 #define CFG_SYS_FSL_QMAN_OFFSET 0x88000 #define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 #define CFG_SYS_FSL_FM1_OFFSET 0x100000 @@ -2574,9 +2574,9 @@ struct ccsr_pman { #define CFG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CFG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) #define CFG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) #define CFG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) #define CFG_SYS_FSL_BMAN_ADDR \ @@ -2603,9 +2603,9 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) #define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) -#define CONFIG_SYS_LBC_ADDR \ +#define CFG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_IFC_ADDR \ +#define CFG_SYS_IFC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) #define CFG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) @@ -2659,7 +2659,7 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) #define CFG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) -#define CONFIG_SYS_PAMU_ADDR \ +#define CFG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) #define CFG_SYS_PCIE1_ADDR \ @@ -2667,14 +2667,14 @@ struct ccsr_pman { #define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_SFP_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define CFG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET) -#define CONFIG_SYS_SEC_MON_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) +#define CFG_SYS_SEC_MON_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET) -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 struct ccsr_cluster_l2 { @@ -2735,7 +2735,7 @@ struct ccsr_cluster_l2 { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ -#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 +#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000 struct dcsr_dcfg_regs { u8 res_0[0x520]; u32 ecccr1; diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index d4a6057527..b638ea7be6 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -23,7 +23,7 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point; - image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, + image_entry(spl_image->arg, 0, 0, EPAPR_MAGIC, CFG_SYS_BOOTMAPSZ, 0, 0); } #endif /* CONFIG_SPL_OS_BOOT */ diff --git a/arch/sh/include/asm/config.h b/arch/sh/include/asm/config.h index 99d8797a54..03c196fec3 100644 --- a/arch/sh/include/asm/config.h +++ b/arch/sh/include/asm/config.h @@ -9,7 +9,7 @@ #include /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 4) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 4) #endif diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index c11101b44e..1eb97ac5bb 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -144,7 +144,7 @@ static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c, /* Make sure the window is below U-Boot. */ assert(window + LARGE_PAGE_SIZE < - gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE); + gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CFG_SYS_STACK_SIZE); /* Map the page into the window and then memset the appropriate part. */ x86_phys_map_page(window, map_addr, 1); memset((void *)(window + offset), c, size); diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h index 3b27f9308a..920b5fd26b 100644 --- a/arch/xtensa/include/asm/addrspace.h +++ b/arch/xtensa/include/asm/addrspace.h @@ -22,8 +22,8 @@ * The actual location of memory and IO is the board property. */ -#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) -#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) +#define IOADDR(x) (CFG_SYS_IO_BASE + (x)) +#define MEMADDR(x) (CFG_SYS_MEMORY_BASE + (x)) #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ XCHAL_VECBASE_RESET_PADDR) diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index f9a37e7215..ea49c7a99c 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard (void) { puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n"); -#if (CONFIG_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +#if (CONFIG_TEXT_BASE == CFG_SYS_INT_FLASH_BASE) puts(" Boot from Internal FLASH\n"); #endif return 0; @@ -38,7 +38,7 @@ int dram_init(void) size = 0; MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | - MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); + MCFSDRAMC_DCR_RC((15 * CFG_SYS_CLK / 1000000) >> 4); asm (" nop"); #ifdef CFG_SYS_SDRAM_BASE0 MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE0)| @@ -94,7 +94,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 695d6f6ed4..9170913400 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -88,7 +88,7 @@ int board_init(void) #if defined(CONFIG_MISC_INIT_R) -#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_G762_ADDR) +#if defined(CONFIG_CMD_I2C) && defined(CFG_SYS_I2C_G762_ADDR) /* * Start I2C fan (GMT G762 controller) */ @@ -100,11 +100,11 @@ static void init_fan(void) /* Enable open-loop and PWM modes */ data = 0x20; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_FAN_CMD1, 1, &data, 1) != 0) goto err; data = 0; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_SET_CNT, 1, &data, 1) != 0) goto err; /* @@ -124,18 +124,18 @@ static void init_fan(void) * Start fan at low speed (2800 RPM): */ data = 0x08; - if (i2c_write(CONFIG_SYS_I2C_G762_ADDR, + if (i2c_write(CFG_SYS_I2C_G762_ADDR, G762_REG_SET_OUT, 1, &data, 1) != 0) goto err; return; err: printf("Error: failed to start I2C fan @%02x\n", - CONFIG_SYS_I2C_G762_ADDR); + CFG_SYS_I2C_G762_ADDR); } #else static void init_fan(void) {} -#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_G762_ADDR */ +#endif /* CONFIG_CMD_I2C && CFG_SYS_I2C_G762_ADDR */ #if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO) /* diff --git a/board/Synology/common/legacy.c b/board/Synology/common/legacy.c index 06f964f53a..a0bace7b46 100644 --- a/board/Synology/common/legacy.c +++ b/board/Synology/common/legacy.c @@ -56,8 +56,8 @@ void setup_board_tags(struct tag **in_params) t = (struct tag_mv_uboot *)¶ms->u; t->uboot_version = VER_NUM | syno_board_id(); - t->tclk = CONFIG_SYS_TCLK; - t->sysclk = CONFIG_SYS_TCLK * 2; + t->tclk = CFG_SYS_TCLK; + t->sysclk = CFG_SYS_TCLK * 2; t->isusbhost = usb_port_modes(); for (i = 0; i < ETHADDR_MAX; i++) { diff --git a/board/armltd/integrator/timer.c b/board/armltd/integrator/timer.c index d220b877d6..9db5135a8f 100644 --- a/board/armltd/integrator/timer.c +++ b/board/armltd/integrator/timer.c @@ -41,10 +41,10 @@ static unsigned long long div_clock = DIV_CLOCK_INIT; static unsigned long long div_timer = 1; /* Divisor to convert timer reading * change to U-Boot ticks */ -/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */ +/* CONFIG_SYS_HZ = CFG_SYS_HZ_CLOCK/(div_clock * div_timer) */ static ulong timestamp; /* U-Boot ticks since startup */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) +#define READ_TIMER (*(volatile ulong *)(CFG_SYS_TIMERBASE+4)) /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec * - unless otherwise stated @@ -55,7 +55,7 @@ static ulong timestamp; /* U-Boot ticks since startup */ int timer_init (void) { /* Load timer with initial value */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; #ifdef CONFIG_ARCH_CINTEGRATOR /* Set timer to be * enabled 1 @@ -66,7 +66,7 @@ int timer_init (void) * 32 bit 1 * wrapping 0 */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x000000C2; #else /* Set timer to be * enabled 1 @@ -75,7 +75,7 @@ int timer_init (void) * divider 256 10 * XX 00 */ - *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088; + *(volatile ulong *)(CFG_SYS_TIMERBASE + 8) = 0x00000088; #endif /* init the timestamp */ @@ -85,7 +85,7 @@ int timer_init (void) /* start "advancing" time stamp from 0 */ timestamp = 0L; - div_timer = CONFIG_SYS_HZ_CLOCK; + div_timer = CFG_SYS_HZ_CLOCK; do_div(div_timer, CONFIG_SYS_HZ); do_div(div_timer, div_clock); @@ -156,7 +156,7 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - unsigned long long tmp = CONFIG_SYS_HZ_CLOCK; + unsigned long long tmp = CFG_SYS_HZ_CLOCK; do_div(tmp, div_clock); diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index af326dc6f4..4ca544f101 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -108,7 +108,7 @@ unsigned long __section(".data") prior_stage_fdt_address[2]; #define JUNO_FLASH_SEC_SIZE (256 * 1024) static phys_addr_t find_dtb_in_nor_flash(const char *partname) { - phys_addr_t sector = CONFIG_SYS_FLASH_BASE; + phys_addr_t sector = CFG_SYS_FLASH_BASE; int i; for (i = 0; @@ -140,7 +140,7 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname) imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg; reg = readl(imginfo + 0x54); - return CONFIG_SYS_FLASH_BASE + + return CFG_SYS_FLASH_BASE + reg * JUNO_FLASH_SEC_SIZE; } } diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index ade7f9d120..f38f5564a0 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -58,8 +58,8 @@ unsigned long get_board_sys_clk(void) * else non-zero (hang). */ -#ifdef CONFIG_SYS_FPGAREG_FREQ - return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); +#ifdef CFG_SYS_FPGAREG_FREQ + return (*(volatile unsigned long *)CFG_SYS_FPGAREG_FREQ); #else /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ return 50000000; @@ -90,7 +90,7 @@ int misc_init_r(void) if (s == 0) { unsigned int x; char s[] = __stringify(CONFIG_ETHBASE); - x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) + x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW) & FPGAREG_MAC_MASK; sprintf(&s[15], "%02x", x); env_set("ethaddr", s); @@ -106,9 +106,9 @@ U_BOOT_DRVINFO(sysreset) = { static struct ethoc_eth_pdata ethoc_pdata = { .eth_pdata = { - .iobase = CONFIG_SYS_ETHOC_BASE, + .iobase = CFG_SYS_ETHOC_BASE, }, - .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, + .packet_base = CFG_SYS_ETHOC_BUFFER_ADDR, }; U_BOOT_DRVINFO(ethoc) = { diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c index 1a039c53c1..37340fe970 100644 --- a/board/cavium/thunderx/atf.c +++ b/board/cavium/thunderx/atf.c @@ -187,7 +187,7 @@ static void atf_print_part_table(void) int ret; char *ptype; - struct storage_partition *part = (void *)CONFIG_SYS_LOWMEM_BASE; + struct storage_partition *part = (void *)CFG_SYS_LOWMEM_BASE; pcount = atf_get_pcount(); diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index a8f8c78558..ab20825ed3 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -20,7 +20,7 @@ #include static const struct pl01x_serial_plat serial0 = { - .base = CONFIG_SYS_SERIAL0, + .base = CFG_SYS_SERIAL0, .type = TYPE_PL011, .clock = 0, .skip_init = true, @@ -32,7 +32,7 @@ U_BOOT_DRVINFO(thunderx_serial0) = { }; static const struct pl01x_serial_plat serial1 = { - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, .clock = 0, .skip_init = true, diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 5d15ed4e69..8416af163a 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -12,7 +12,7 @@ #include #include -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_1 CFG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; @@ -102,8 +102,8 @@ unsigned long flash_init(void) } flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]); + CFG_SYS_FLASH_BASE, + CFG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]); return size; } @@ -117,8 +117,8 @@ unsigned long flash_init(void) #define CMD_PROGRAM 0x00A0 #define CMD_UNLOCK_BYPASS 0x0020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_SYS_FLASH_BASE + (0x000002AA<<1))) #define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 diff --git a/board/cortina/presidio-asic/lowlevel_init.S b/board/cortina/presidio-asic/lowlevel_init.S index cbf8134346..8d8842ebed 100644 --- a/board/cortina/presidio-asic/lowlevel_init.S +++ b/board/cortina/presidio-asic/lowlevel_init.S @@ -27,7 +27,7 @@ skip_smp_setup: #if defined(CONFIG_SOC_CA8277B) /* Enable CPU Timer */ - ldr x0, =CONFIG_SYS_TIMER_BASE + ldr x0, =CFG_SYS_TIMER_BASE mov x1, #1 str w1, [x0] #endif diff --git a/board/cortina/presidio-asic/presidio.c b/board/cortina/presidio-asic/presidio.c index f344622b02..aae0a5dac0 100644 --- a/board/cortina/presidio-asic/presidio.c +++ b/board/cortina/presidio-asic/presidio.c @@ -84,7 +84,7 @@ int board_init(void) unsigned int reg_data, jtag_id; /* Enable timer */ - writel(1, CONFIG_SYS_TIMER_BASE); + writel(1, CFG_SYS_TIMER_BASE); /* Enable snoop in CCI400 slave port#4 */ writel(3, 0xF5595000); diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 2436aab71c..e3a0f266a4 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -371,20 +371,20 @@ int rmii_hw_init(void) /* Set polarity to non-inverted */ buf[0] = 0x0; buf[1] = 0x0; - ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); + ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); return ret; } /* Configure P07-P05 as outputs */ buf[0] = 0x1f; buf[1] = 0xff; - ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); + ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); } /* For Ethernet RMII selection @@ -392,16 +392,16 @@ int rmii_hw_init(void) * P06(SelB)=1 * P05(SelC)=1 */ - if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x read FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); } buf[0] &= 0x1f; buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); - if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { + if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x write FAILED!!!\n", - CONFIG_SYS_I2C_EXPANDER_ADDR); + CFG_SYS_I2C_EXPANDER_ADDR); } /* Set the output as high */ diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index 913c2ea166..ceb0d2cf0a 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -193,6 +193,6 @@ int board_mmc_init(struct bd_info *bd) int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_pio_value(CFG_SYS_MMC_CD_PIN); } #endif diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index a4254250bb..a39bcb4fa0 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -41,7 +41,7 @@ static void *get_fdt_virt(void) if (gd->flags & GD_FLG_RELOC) return (void *)gd->fdt_blob; else - return (void *)CONFIG_SYS_TMPVIRT; + return (void *)CFG_SYS_TMPVIRT; } static uint64_t get_fdt_phys(void) @@ -163,7 +163,7 @@ int misc_init_r(void) * U-Boot is relocated to RAM already, let's delete the temporary FDT * virtual-physical mapping that was used in the pre-relocation phase. */ - disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1)); + disable_tlb(find_tlb_idx((void *)CFG_SYS_TMPVIRT, 1)); /* * Detect the presence of the platform bus node, and @@ -248,7 +248,7 @@ void init_tlbs(void) init_used_tlb_cams(); /* Create a dynamic AS=0 CCSRBAR mapping */ - assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + assert(!tlb_map_range(CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, 1024 * 1024, TLB_MAP_IO)); /* Create a RAM map that spans all accessible RAM */ diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 2304e9e8ec..21f4ba98b5 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -240,7 +240,7 @@ int misc_init_r(void) if (str && (strcmp(str, "4") == 0)) { writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | AT91SAM9_PMC_MDIV_4, &pmc->mckr); - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + at91_clock_init(CFG_SYS_AT91_MAIN_CLOCK); serial_setbrg(); /* Notify the user that the clock is not default */ printf("Setting master clock to %s MHz\n", diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index d31ad02656..9ca350ed46 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -43,7 +43,7 @@ int fsl_check_boot_mode_secure(void) { uint32_t val; - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); struct ccsr_gur __iomem *gur = (void *)(CONFIG_DCFG_ADDR); val = sfp_in32(&sfp_regs->ospr) & ITS_MASK; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 3424d49208..285ed9afcc 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -85,7 +85,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); - u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); + u32 csf_flash_offset = csf_hdr_addr & ~(CFG_SYS_PBI_FLASH_BASE); u32 flash_addr, addr; int found = 0; int i = 0; @@ -160,7 +160,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) */ #if defined(CONFIG_FSL_TRUST_ARCH_v1) && defined(CONFIG_FSL_CORENET) sg_tbl = (struct fsl_secboot_sg_table *) - (((u32)hdr->psgtable & ~(CONFIG_SYS_PBI_FLASH_BASE)) + + (((u32)hdr->psgtable & ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else sg_tbl = (struct fsl_secboot_sg_table *)(uintptr_t)(csf_addr + @@ -170,7 +170,7 @@ static int get_ie_info_addr(uintptr_t *ie_addr) /* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) *ie_addr = (uintptr_t)((sg_tbl->src_addr & - ~(CONFIG_SYS_PBI_FLASH_BASE)) + + ~(CFG_SYS_PBI_FLASH_BASE)) + flash_base_addr); #else *ie_addr = (uintptr_t)sg_tbl->src_addr; @@ -203,7 +203,7 @@ static u32 check_srk(struct fsl_secboot_img_priv *img) /* This function returns ospr's key_revoc values.*/ static u32 get_key_revoc(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); return (sfp_in32(&sfp_regs->ospr) & OSPR_KEY_REVOC_MASK) >> OSPR_KEY_REVOC_SHIFT; } @@ -342,7 +342,7 @@ static inline u32 get_key_len(struct fsl_secboot_img_priv *img) */ static void fsl_secboot_header_verification_failure(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); /* 29th bit of OSPR is ITS */ u32 its = sfp_in32(&sfp_regs->ospr) >> 2; @@ -367,7 +367,7 @@ static void fsl_secboot_header_verification_failure(void) */ static void fsl_secboot_image_verification_failure(void) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); u32 its = (sfp_in32(&sfp_regs->ospr) & ITS_MASK) >> ITS_BIT; @@ -871,7 +871,7 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr) int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, uintptr_t *img_addr_ptr) { - struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); + struct ccsr_sfp_regs *sfp_regs = (void *)(CFG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; char hash_str[NUM_HEX_CHARS + 1]; struct fsl_secboot_img_priv *img; diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 8951fae32d..1a1e9343d2 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -11,12 +11,12 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), #endif #ifdef PIXIS_BASE_PHYS SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), @@ -24,9 +24,9 @@ struct law_entry law_table[] = { #ifdef CPLD_BASE_PHYS SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 7302b76066..1a2d9cbfc0 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -11,20 +11,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), #ifdef CPLD_BASE @@ -41,25 +41,25 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) #if !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #else /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot - * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * the physical address of the SRAM is at CFG_SYS_INIT_L3_ADDR, * and virtual address is CONFIG_SYS_MONITOR_BASE */ SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, - CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + CFG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #endif @@ -80,13 +80,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -112,26 +112,26 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x00100000, + CFG_SYS_BMAN_MEM_PHYS + 0x00100000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x00100000, + CFG_SYS_QMAN_MEM_PHYS + 0x00100000, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 2bb838cea6..da2c1de078 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -29,15 +29,15 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #endif -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { #if !CONFIG_IS_ENABLED(DM_I2C) - return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg); + return i2c_reg_read(CFG_SYS_I2C_FPGA_ADDR, reg); #else struct udevice *dev; - if (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + if (i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) return 0xff; return dm_i2c_reg_read(dev, reg); @@ -48,11 +48,11 @@ void qixis_write_i2c(unsigned int reg, u8 value) { u8 val = value; #if !CONFIG_IS_ENABLED(DM_I2C) - i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val); + i2c_reg_write(CFG_SYS_I2C_FPGA_ADDR, reg, val); #else struct udevice *dev; - if (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev)) + if (!i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev)) dm_i2c_reg_write(dev, reg, val); #endif diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index af76327e4d..784046ac4e 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,12 +100,12 @@ u16 qixis_read_minor(void); char *qixis_read_time(char *result); char *qixis_read_tag(char *buf); const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif -#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CFG_SYS_I2C_FPGA_ADDR) #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) \ qixis_write_i2c(offsetof(struct qixis, reg), value) @@ -114,7 +114,7 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) #endif -#ifdef CONFIG_SYS_I2C_FPGA_ADDR +#ifdef CFG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ qixis_write_i2c(offsetof(struct qixis, reg), value) diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index f17a6c186d..194b5d2729 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -117,7 +117,7 @@ int misc_init_r(void) struct udevice *dev; int ret; - ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, @@ -128,7 +128,7 @@ int misc_init_r(void) #else i2c_set_bus_num(bus_num); - i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + i2c_write(CFG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); #endif return 0; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d0674d014a..d5cb731209 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -196,7 +196,7 @@ void board_init_f(ulong dummy) porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | DCFG_CCSR_PORSR1_RCW_SRC_I2C); - out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), pinctl); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 8b74d45823..4f5834347d 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -98,7 +98,7 @@ struct cpld_data { #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) static void cpld_show(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", in_8(&cpld_data->cpld_ver) & VERSION_MASK, @@ -248,7 +248,7 @@ int board_eth_init(struct bd_info *bis) static void convert_serdes_mux(int type, int need_reset) { char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); current_serdes = cpld_data->serdes_mux; @@ -322,7 +322,7 @@ int config_serdes_mux(void) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) int config_board_mux(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); int conflict_flag; conflict_flag = 0; @@ -610,7 +610,7 @@ u16 flash_read16(void *addr) && !defined(CONFIG_SPL_BUILD) static void convert_flash_bank(char bank) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); printf("Now switch to boot from flash bank %d.\n", bank); cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; @@ -644,7 +644,7 @@ U_BOOT_CMD( static int cpld_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); if (argc > 2) return CMD_RET_USAGE; @@ -671,7 +671,7 @@ U_BOOT_CMD( static void print_serdes_mux(void) { char current_serdes; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); current_serdes = cpld_data->serdes_mux; diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 5fe40c4bdb..841d8b59bb 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -57,8 +57,8 @@ enum { struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -71,8 +71,8 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -97,15 +97,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -126,8 +126,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -139,8 +139,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -152,15 +152,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 232035638b..9db3aa5860 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -12,14 +12,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index a8a7263a65..741a4d64ea 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -60,15 +60,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "cpld", - CONFIG_SYS_CPLD_CSPR, - CONFIG_SYS_CPLD_CSPR_EXT, - CONFIG_SYS_CPLD_AMASK, - CONFIG_SYS_CPLD_CSOR, + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, { - CONFIG_SYS_CPLD_FTIM0, - CONFIG_SYS_CPLD_FTIM1, - CONFIG_SYS_CPLD_FTIM2, - CONFIG_SYS_CPLD_FTIM3 + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 }, } }; @@ -102,15 +102,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "cpld", - CONFIG_SYS_CPLD_CSPR, - CONFIG_SYS_CPLD_CSPR_EXT, - CONFIG_SYS_CPLD_AMASK, - CONFIG_SYS_CPLD_CSOR, + CFG_SYS_CPLD_CSPR, + CFG_SYS_CPLD_CSPR_EXT, + CFG_SYS_CPLD_AMASK, + CFG_SYS_CPLD_CSOR, { - CONFIG_SYS_CPLD_FTIM0, - CONFIG_SYS_CPLD_FTIM1, - CONFIG_SYS_CPLD_FTIM2, - CONFIG_SYS_CPLD_FTIM3 + CFG_SYS_CPLD_FTIM0, + CFG_SYS_CPLD_FTIM1, + CFG_SYS_CPLD_FTIM2, + CFG_SYS_CPLD_FTIM3 }, } }; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 97d71dbf2a..3d0881643c 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -55,8 +55,8 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -81,15 +81,15 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -110,8 +110,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -123,8 +123,8 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -136,15 +136,15 @@ struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; diff --git a/board/freescale/ls1046ardb/cpld.c b/board/freescale/ls1046ardb/cpld.c index 548601a5ae..ee19d4ff8a 100644 --- a/board/freescale/ls1046ardb/cpld.c +++ b/board/freescale/ls1046ardb/cpld.c @@ -12,14 +12,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index ff3abc8302..0d3f22ce2b 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR_EARLY, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR0_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK, CFG_SYS_NOR_CSOR, { @@ -52,13 +52,13 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { CFG_SYS_NOR_FTIM3 }, 0, - CONFIG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR, 0, }, { "nor1", - CONFIG_SYS_NOR1_CSPR_EARLY, - CONFIG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR1_CSPR_EARLY, + CFG_SYS_NOR0_CSPR_EXT, CFG_SYS_NOR_AMASK_EARLY, CFG_SYS_NOR_CSOR, { @@ -68,7 +68,7 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { CFG_SYS_NOR_FTIM3 }, 0, - CONFIG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR, CFG_SYS_NOR_AMASK, }, { @@ -86,10 +86,10 @@ struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSOR, { SYS_FPGA_CS_FTIM0, SYS_FPGA_CS_FTIM1, @@ -121,10 +121,10 @@ struct ifc_regs ifc_cfg_qspi_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSOR, { SYS_FPGA_CS_FTIM0, SYS_FPGA_CS_FTIM1, @@ -746,12 +746,12 @@ int set_serdes_volt(int svdd) /* Read the BRDCFG54 via CLPD */ #if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_read(CFG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); #else struct udevice *dev; - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev); + ret = i2c_get_chip_for_busnum(0, CFG_SYS_I2C_FPGA_ADDR, 1, &dev); if (!ret) ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET, (void *)&brdcfg4, 1); @@ -766,7 +766,7 @@ int set_serdes_volt(int svdd) /* Write to the BRDCFG4 */ #if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, + ret = i2c_write(CFG_SYS_I2C_FPGA_ADDR, QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1); #else ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET, diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 971633c9c8..a4cb1a6cac 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -118,10 +118,10 @@ Kernel.itb 0x01000000 0x08000 Environment Variables --------------------- - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined - the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + the value CFG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. - mcmemsize: MC DRAM block size. If this variable is not defined - the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + the value CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) ------------------------------------------------------------------- diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 5df85722d1..91db618227 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -217,7 +217,7 @@ int board_init(void) #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT #if CONFIG_IS_ENABLED(DM_I2C) - rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); + rtc_enable_32khz_output(0, CFG_SYS_I2C_RTC_ADDR); #else rtc_enable_32khz_output(); #endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 437675517e..cf5b1ee46e 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -57,9 +57,9 @@ DECLARE_GLOBAL_DATA_PTR; static struct pl01x_serial_plat serial0 = { #if CONFIG_CONS_INDEX == 0 - .base = CONFIG_SYS_SERIAL0, + .base = CFG_SYS_SERIAL0, #elif CONFIG_CONS_INDEX == 1 - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, #else #error "Unsupported console index value." #endif @@ -72,7 +72,7 @@ U_BOOT_DRVINFO(nxp_serial0) = { }; static struct pl01x_serial_plat serial1 = { - .base = CONFIG_SYS_SERIAL1, + .base = CFG_SYS_SERIAL1, .type = TYPE_PL011, }; diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index efff055140..d67db24d58 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -26,7 +26,7 @@ int checkboard (void) { /* * Set LED on */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_SYS_GPIO1_LED; mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ return 0; @@ -42,13 +42,13 @@ int dram_init(void) * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 */ -#ifdef CONFIG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK /* * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 */ mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CONFIG_SYS_PLL_BYPASS +#elif CFG_SYS_PLL_BYPASS /* * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index bff1ac5fb1..fbd4835416 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -42,7 +42,7 @@ ulong flash_init(void) ulong size = 0; ulong fbase = 0; - fbase = (ulong) CONFIG_SYS_FLASH_BASE; + fbase = (ulong) CFG_SYS_FLASH_BASE; flash_get_size((FPWV *) fbase, &flash_info[0]); flash_get_offsets((ulong) fbase, &flash_info[0]); fbase += flash_info[0].size; @@ -64,9 +64,9 @@ int flash_get_offsets(ulong base, flash_info_t * info) info->start[0] = base; info->protect[0] = 0; - for (i = 1; i < CONFIG_SYS_SST_SECT; i++) { + for (i = 1; i < CFG_SYS_SST_SECT; i++) { info->start[i] = info->start[i - 1] - + CONFIG_SYS_SST_SECTSZ; + + CFG_SYS_SST_SECTSZ; info->protect[i] = 0; } } @@ -162,8 +162,8 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info) info->sector_count = 0; info->size = 0; - info->sector_count = CONFIG_SYS_SST_SECT; - info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ; + info->sector_count = CFG_SYS_SST_SECT; + info->size = CFG_SYS_SST_SECT * CFG_SYS_SST_SECTSZ; /* reset ID mode */ *addr = (FPWV) 0x00F000F0; @@ -222,7 +222,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) start = get_timer(0); - if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { + if ((s_last - s_first) == (CFG_SYS_SST_SECT - 1)) { if (prot == 0) { addr = (FPWV *) info->start[0]; @@ -259,7 +259,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) enable_interrupts(); return 0; - } else if (prot == CONFIG_SYS_SST_SECT) { + } else if (prot == CFG_SYS_SST_SECT) { return 1; } } @@ -282,7 +282,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) flag = disable_interrupts(); - base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */ + base = (FPWV *) (CFG_SYS_FLASH_BASE); /* First sector */ base[FLASH_CYCLE1] = 0x00AA; /* unlock */ base[FLASH_CYCLE2] = 0x0055; /* unlock */ @@ -411,7 +411,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data) return (2); } - base = (FPWV *) (CONFIG_SYS_FLASH_BASE); + base = (FPWV *) (CFG_SYS_FLASH_BASE); /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 179a2a242a..c1cff52fb3 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -36,7 +36,7 @@ int dram_init(void) if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, temp; - RC = (CONFIG_SYS_CLK / 1000000) >> 1; + RC = (CFG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ @@ -113,7 +113,7 @@ void ide_set_reset(int idereset) mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); #define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ + period = 1000000000 / (CFG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ out_8(&ata->t1, CALC_TIMING(piotms[2][0])); diff --git a/board/freescale/m53017evb/README b/board/freescale/m53017evb/README index 0de36a7f74..34f05f3fdc 100644 --- a/board/freescale/m53017evb/README +++ b/board/freescale/m53017evb/README @@ -68,7 +68,7 @@ CONFIG_M53015 -- define for MCF53015 CPUs CONFIG_M53017EVB -- define for M53017EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver @@ -96,11 +96,11 @@ CONFIG_SYS_I2C_SLAVE -- define for I2C slave address CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset -CONFIG_SYS_MBAR -- define MBAR offset +CFG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5301x internal SRAM CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index a10c365ec3..d921eef8b6 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -23,7 +23,7 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/board/freescale/m5373evb/README b/board/freescale/m5373evb/README index bfbcd5dc81..7240648796 100644 --- a/board/freescale/m5373evb/README +++ b/board/freescale/m5373evb/README @@ -67,7 +67,7 @@ CONFIG_M5373 -- define for all Freescale MCF5373 CPUs CONFIG_M5373EVB -- define for M5373EVB board CONFIG_MCFUART -- define to use common CF Uart driver -CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 +CFG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2 CONFIG_BAUDRATE -- define UART baudrate CONFIG_MCFRTC -- define to use common CF RTC driver @@ -95,11 +95,11 @@ CONFIG_SYS_I2C_SLAVE -- define for I2C slave address CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset CONFIG_SYS_IMMR -- define for MBAR offset -CONFIG_SYS_MBAR -- define MBAR offset +CFG_SYS_MBAR -- define MBAR offset CONFIG_MONITOR_IS_IN_RAM -- Not support -CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM +CFG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index fdf3e0ac1b..6d825a66e3 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -23,7 +23,7 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd_to_nand(mtdinfo); - volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; + volatile u16 *nCE = (u16 *) CFG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 85d43cccd1..4a14554026 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -22,7 +22,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { @@ -103,25 +103,25 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].bar = CFG_SYS_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; + im->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE; udelay(50000); - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL; udelay(1000); - im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.csbnds[0].csbnds = CFG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_SYS_DDR_CS0_CONFIG; udelay(1000); - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CFG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CFG_SYS_DDR_INTERVAL; sync(); udelay(1000); diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index d194388991..7b6ef5b11c 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -12,7 +12,7 @@ struct law_entry law_table[] = { /* LBC window - maps 256M */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index e4c951feb5..73e024eaa0 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -103,11 +103,11 @@ void lbc_sdram_init(void) uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; + uint *sdram_addr = (uint *)CFG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; puts("LBC SDRAM: "); - print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, + print_size(CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* @@ -115,17 +115,17 @@ void lbc_sdram_init(void) */ set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->lbcr = CFG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CFG_SYS_LBC_LSRT; + lbc->mrtpr = CFG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8548 uses "new" 15-16 style addressing. */ - lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common = CFG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516; /* diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index 9c8e948600..994a32dd92 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -11,16 +11,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -29,7 +29,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 0: * FLASH(cover boot page) 16M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 1: * CCSRBAR 1M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), @@ -45,8 +45,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * Entry 2: * LBC SDRAM 64M Cacheable, non-guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, - CONFIG_SYS_LBC_SDRAM_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_LBC_SDRAM_BASE, + CFG_SYS_LBC_SDRAM_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 2, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 4f27d3e8ec..d447ad840a 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -42,7 +42,7 @@ u32 get_board_rev(void) int rev = readl(&fuse->gp[6]); - if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) + if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) rev = 0; return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; @@ -81,7 +81,7 @@ static int power_init(void) int ret; struct pmic *p; - if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { + if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) { ret = pmic_dialog_init(I2C_PMIC); if (ret) return ret; diff --git a/board/freescale/p1010rdb/law.c b/board/freescale/p1010rdb/law.c index 2dcee79b3a..13fc2fa2e3 100644 --- a/board/freescale/p1010rdb/law.c +++ b/board/freescale/p1010rdb/law.c @@ -8,8 +8,8 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), }; diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index ab3b2e3e69..0f014823c9 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -83,7 +83,7 @@ struct cpld_data { int board_early_init_f(void) { ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); /* @@ -97,7 +97,7 @@ int board_early_init_f(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -118,12 +118,12 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_16M, 1); set_tlb(1, flashbase + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel+1, BOOKE_PAGESZ_16M, 1); return 0; @@ -138,7 +138,7 @@ int config_board_mux(int ctrl_type) struct udevice *dev; int ret; #if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); ret = i2c_get_chip_for_busnum(I2C_PCA9557_BUS_NUM, I2C_PCA9557_ADDR1, 1, &dev); @@ -254,7 +254,7 @@ int config_board_mux(int ctrl_type) #endif #else #if defined(CONFIG_TARGET_P1010RDB_PA) - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); switch (ctrl_type) { case MUX_TYPE_IFC: @@ -404,7 +404,7 @@ int i2c_pca9557_read(int type) int checkboard(void) { struct cpu_type *cpu; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); u8 val; cpu = gd->arch.cpu; diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 9bf948cb5c..e450f626e0 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -29,7 +29,7 @@ void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; console_init_f(); diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c index 5e1fa70bca..265cde81a3 100644 --- a/board/freescale/p1010rdb/tlb.c +++ b/board/freescale/p1010rdb/tlb.c @@ -8,19 +8,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -36,17 +36,17 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), #ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE + 0x1000000, + CFG_SYS_FLASH_BASE_PHYS + 0x1000000, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 3, BOOKE_PAGESZ_16M, 1), @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G - Board CPLD */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), @@ -73,14 +73,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #endif -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1) #endif diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index f896fd7ccc..5f16779aba 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -201,7 +201,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif /* CONFIG_SYS_DDR_RAW_TIMING */ -#ifdef CONFIG_SYS_DDR_CS0_BNDS +#ifdef CFG_SYS_DDR_CS0_BNDS /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { @@ -209,35 +209,35 @@ phys_size_t fixed_sdram(void) char buf[32]; size_t ddr_size; fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[0].bnds = CFG_SYS_DDR_CS0_BNDS, + .cs[0].config = CFG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CFG_SYS_DDR_CS0_CONFIG_2, #if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, + .cs[1].bnds = CFG_SYS_DDR_CS1_BNDS, + .cs[1].config = CFG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CFG_SYS_DDR_CS1_CONFIG_2, #endif - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .timing_cfg_3 = CFG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CFG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CFG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CFG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CFG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CFG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CFG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CFG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CFG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CFG_SYS_DDR_INTERVAL, .ddr_data_init = 0xdeadbeef, /* Poison value */ - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + .ddr_sdram_clk_cntl = CFG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CFG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CFG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CFG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CFG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CFG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CFG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CFG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CFG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CFG_SYS_DDR_RCW_2 }; get_sys_info(&sysinfo); @@ -248,7 +248,7 @@ phys_size_t fixed_sdram(void) fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + if (set_ddr_laws(CFG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { printf("ERROR setting Local Access Windows for DDR\n"); return 0; diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 8f3f4840e6..6085984eab 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -8,11 +8,11 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #ifdef CONFIG_VSC7385_ENET - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 2999c85d0a..ab79724429 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -90,20 +90,20 @@ void board_reset_prepare(void) * This ensures that external watchdog does not trigger * another reset or possible infinite reset loop. */ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); in_8(&cpld_data->wd_cfg); /* Read back to sync write */ } void board_reset_last(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); out_8(&cpld_data->system_rst, 1); } void board_cpld_init(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); u8 prev_wd_cfg = in_8(&cpld_data->wd_cfg); out_8(&cpld_data->wd_cfg, CPLD_WD_CFG); @@ -226,7 +226,7 @@ int board_early_init_f(void) int checkboard(void) { - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + struct cpld_data *cpld_data = (void *)(CFG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, invert, io_config, val; int bus_num = CONFIG_SYS_SPD_BUS_NUM; @@ -246,7 +246,7 @@ int checkboard(void) struct udevice *dev; int ret; - ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR, + ret = i2c_get_chip_for_busnum(bus_num, CFG_SYS_I2C_PCA9557_ADDR, 1, &dev); if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, @@ -264,10 +264,10 @@ int checkboard(void) #else /* Non DM I2C support - will be removed */ i2c_set_bus_num(bus_num); - if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || - i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { + if (i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 2, 1, &invert, 1) < 0 || + i2c_read(CFG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) { printf("Error reading i2c boot information!\n"); return 0; /* Don't want to hang() on this error */ } @@ -319,7 +319,7 @@ int checkboard(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); #ifdef CONFIG_VSC7385_ENET unsigned int vscfw_addr; @@ -344,7 +344,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */ 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 4cc5e01f57..94773969e9 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -8,20 +8,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -32,14 +32,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), #ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_64M, 1), @@ -57,13 +57,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #ifdef CONFIG_VSC7385_ENET /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_1M, 1), #endif #endif /* not SPL */ - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), @@ -76,27 +76,27 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #if defined(CONFIG_TARGET_P1020RDB_PD) /* **M** - 2G DDR on P1020MBG, map the second 1G */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif #endif /* RAMBOOT/SPL */ -#ifdef CONFIG_SYS_INIT_L2_ADDR +#ifdef CFG_SYS_INIT_L2_ADDR /* ***G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000, + CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 0, 12, BOOKE_PAGESZ_256K, 1) #endif diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 23ec32b7f9..3e12c816ab 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -35,10 +35,10 @@ static u8 lane_to_slot[] = { }; static int riser_phy_addr[] = { - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, }; /* @@ -101,12 +101,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, slot = lane_to_slot[lane]; if (slot) { sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } else { sprintf(phy, "phy_sgmii_%x", - CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + CFG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1)); fdt_set_phy_handle(fdt, compat, addr, phy); } @@ -158,9 +158,9 @@ int board_eth_init(struct bd_info *bis) * is RGMII, we'll also override its PHY address later. We assume that * DTSEC4 and DTSEC5 are used for RGMII. */ - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR); for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) { int idx = i - FM1_DTSEC1; @@ -180,8 +180,8 @@ int board_eth_init(struct bd_info *bis) case PHY_INTERFACE_MODE_RGMII_ID: /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + CFG_SYS_FM1_DTSEC5_PHY_ADDR : + CFG_SYS_FM1_DTSEC4_PHY_ADDR); break; default: printf("Fman1: DTSEC%u set to unknown interface %i\n", @@ -198,7 +198,7 @@ int board_eth_init(struct bd_info *bis) slot = lane_to_slot[lane]; if (slot) fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); + CFG_SYS_FM1_10GEC1_PHY_ADDR); } fm_info_set_mdio(FM1_10GEC1, diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1b1263091e..575259b19c 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -119,7 +119,7 @@ void board_config_lanes_mux(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -140,7 +140,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t102xrdb/cpld.c b/board/freescale/t102xrdb/cpld.c index 47c3b1627e..17a6226caf 100644 --- a/board/freescale/t102xrdb/cpld.c +++ b/board/freescale/t102xrdb/cpld.c @@ -14,14 +14,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index 818c20cf1b..1b41739899 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -222,7 +222,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; /* does not provide HW signals for power management */ clrbits_8(cpld_base + 0x17, 0x40); diff --git a/board/freescale/t102xrdb/law.c b/board/freescale/t102xrdb/law.c index 850ece0110..d636bef325 100644 --- a/board/freescale/t102xrdb/law.c +++ b/board/freescale/t102xrdb/law.c @@ -9,19 +9,19 @@ struct law_entry law_table[] = { #ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f777f5a2fe..baa59615b3 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -130,8 +130,8 @@ int board_early_init_f(void) int board_early_init_r(void) { -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited @@ -150,7 +150,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c index 74744c8ab0..2519a9e4db 100644 --- a/board/freescale/t102xrdb/tlb.c +++ b/board/freescale/t102xrdb/tlb.c @@ -8,31 +8,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), #else @@ -42,13 +42,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -64,27 +64,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif @@ -93,18 +93,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index ac34095f3b..9ac57bbd83 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -7,7 +7,7 @@ * * The following macros need to be defined: * - * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map + * CFG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map */ #include @@ -18,14 +18,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 539a36d2a9..02ddb66141 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -115,7 +115,7 @@ found: #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void) { - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE; + void __iomem *cpld_base = (void *)CFG_SYS_CPLD_BASE; /* does not provide HW signals for power management */ clrbits_8(cpld_base + 0x17, 0x40); diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 5ce24b4096..fe51d68c7b 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -49,7 +49,7 @@ int board_eth_init(struct bd_info *bis) * DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_SGMII1_PHY_ADDR); + CFG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_TARGET_T1042RDB @@ -59,7 +59,7 @@ int board_eth_init(struct bd_info *bis) fm_info_set_phy_address(i, 0); /* T1042RDB only supports SGMII on DTSEC3 */ fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_SGMII1_PHY_ADDR); + CFG_SYS_SGMII1_PHY_ADDR); break; #endif #ifdef CONFIG_TARGET_T1042D4RDB @@ -68,11 +68,11 @@ int board_eth_init(struct bd_info *bis) * & DTSEC3 */ if (FM1_DTSEC1 == i) - phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + phy_addr = CFG_SYS_SGMII1_PHY_ADDR; if (FM1_DTSEC2 == i) - phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + phy_addr = CFG_SYS_SGMII2_PHY_ADDR; if (FM1_DTSEC3 == i) - phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + phy_addr = CFG_SYS_SGMII3_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; #endif @@ -81,9 +81,9 @@ int board_eth_init(struct bd_info *bis) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: if (FM1_DTSEC4 == i) - phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; + phy_addr = CFG_SYS_RGMII1_PHY_ADDR; if (FM1_DTSEC5 == i) - phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; + phy_addr = CFG_SYS_RGMII2_PHY_ADDR; fm_info_set_phy_address(i, phy_addr); break; case PHY_INTERFACE_MODE_QSGMII: @@ -112,7 +112,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { for (i = 0; i < 4; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; + phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i; phy_int = PHY_INTERFACE_MODE_QSGMII; vsc9953_port_info_set_mdio(i, bus); @@ -124,7 +124,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { for (i = 4; i < 8; i++) { bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; + phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; phy_int = PHY_INTERFACE_MODE_QSGMII; vsc9953_port_info_set_mdio(i, bus); diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c index 2f00d80106..a0d6eb5b27 100644 --- a/board/freescale/t104xrdb/law.c +++ b/board/freescale/t104xrdb/law.c @@ -9,19 +9,19 @@ struct law_entry law_table[] = { #ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 66a142b3ad..dd8283f3c6 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -46,7 +46,7 @@ void board_init_f(ulong bootflag) porsr1 = in_be32(&gur->porsr1); pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), + out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000), pinctl); } #endif diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 7d3fd291a0..45ebdd3000 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -62,8 +62,8 @@ int board_early_init_f(void) int board_early_init_r(void) { -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -84,7 +84,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); #endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 905e4771c9..10be580b81 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -8,32 +8,32 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) && \ !defined(CONFIG_NXP_ESBC) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), @@ -44,8 +44,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * and virtual address is 0xfffc0000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, - CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_VADDR, + CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), #else @@ -55,13 +55,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -77,27 +77,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), #endif @@ -111,18 +111,18 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000, + CFG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 13, BOOKE_PAGESZ_1G, 1) #endif diff --git a/board/freescale/t208xqds/law.c b/board/freescale/t208xqds/law.c index f97467e844..3cdd493768 100644 --- a/board/freescale/t208xqds/law.c +++ b/board/freescale/t208xqds/law.c @@ -11,19 +11,19 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif #ifdef QIXIS_BASE_PHYS SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 82710cf897..8be55e52e5 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -282,7 +282,7 @@ static void esdhc_adapter_card_ident(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -303,7 +303,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c index f2448e86c0..3d220afc16 100644 --- a/board/freescale/t208xqds/tlb.c +++ b/board/freescale/t208xqds/tlb.c @@ -11,31 +11,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -143,7 +143,7 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t208xrdb/cpld.c b/board/freescale/t208xrdb/cpld.c index b9ba62adff..933fa0decc 100644 --- a/board/freescale/t208xrdb/cpld.c +++ b/board/freescale/t208xrdb/cpld.c @@ -11,14 +11,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t208xrdb/law.c b/board/freescale/t208xrdb/law.c index 3ff4c773d5..53a1369450 100644 --- a/board/freescale/t208xrdb/law.c +++ b/board/freescale/t208xrdb/law.c @@ -11,19 +11,19 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1c8017b593..04cb313e8c 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -77,7 +77,7 @@ int checkboard(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited @@ -96,7 +96,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c index 45c27c0812..688a208c62 100644 --- a/board/freescale/t208xrdb/tlb.c +++ b/board/freescale/t208xrdb/tlb.c @@ -11,31 +11,31 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) @@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -126,8 +126,8 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif @@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 18, BOOKE_PAGESZ_1M, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 19, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index d484509bc2..8b1012086e 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -9,7 +9,7 @@ * * The following macros need to be defined: * - * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CFG_SYS_CPLD_BASE - The virtual address of the base of the * CPLD register map * */ @@ -22,14 +22,14 @@ u8 cpld_read(unsigned int reg) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; return in_8(p + reg); } void cpld_write(unsigned int reg, u8 value) { - void *p = (void *)CONFIG_SYS_CPLD_BASE; + void *p = (void *)CFG_SYS_CPLD_BASE; out_8(p + reg, value); } diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c index 438589604f..43eeb884e2 100644 --- a/board/freescale/t4rdb/law.c +++ b/board/freescale/t4rdb/law.c @@ -8,19 +8,19 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif -#ifdef CONFIG_SYS_CPLD_BASE_PHYS - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CFG_SYS_CPLD_BASE_PHYS + SET_LAW(CFG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS +#ifdef CFG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), #endif #ifdef CFG_SYS_NAND_BASE_PHYS SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 20ce7523e5..0bd0ba9396 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -54,7 +54,7 @@ int checkboard(void) int board_early_init_r(void) { - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -75,7 +75,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c index c57af3046f..f5af893c2d 100644 --- a/board/freescale/t4rdb/tlb.c +++ b/board/freescale/t4rdb/tlb.c @@ -8,29 +8,29 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR) /* * *I*G - L3SRAM. When L3 is used as 512K SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_512K, 1), #else @@ -40,13 +40,13 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -73,28 +73,28 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 6, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, +#ifdef CFG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, +#ifdef CFG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 12, BOOKE_PAGESZ_16M, 1), #endif #endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, +#ifdef CFG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_32M, 1), #endif @@ -108,13 +108,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif -#ifdef CONFIG_SYS_CPLD_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, +#ifdef CFG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), #endif #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 18, BOOKE_PAGESZ_2G, 1) #endif diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 4889a6a4f3..4fac146353 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -40,26 +40,26 @@ static long fixed_sdram(void) out_be32(&im->sysconf.ddrlaw[0].bar, CFG_SYS_SDRAM_BASE & 0xfffff000); out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); - out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + out_be32(&im->sysconf.ddrcdr, CFG_SYS_DDRCDR_VALUE); out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); /* Currently we use only one CS, so disable the other bank. */ out_be32(&im->ddr.cs_config[1], 0); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); sync(); /* enable DDR controller */ diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 6c5e6fbbcb..f1599306e6 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -82,7 +82,7 @@ int onenand_board_init(struct mtd_info *mtd) { if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; return 0; } return 1; diff --git a/board/keymile/common/qrio.c b/board/keymile/common/qrio.c index 5401bddf06..b433f69675 100644 --- a/board/keymile/common/qrio.c +++ b/board/keymile/common/qrio.c @@ -20,7 +20,7 @@ void show_qrio(void) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); printf("QRIO: id = %u, revision = %u\n", @@ -33,7 +33,7 @@ bool qrio_get_selftest_pin(void) { u8 slftest; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; slftest = in_8(qrio_base + SLFTEST_OFF); @@ -46,7 +46,7 @@ bool qrio_get_pgy_pres_pin(void) { u8 pgy_pres; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; pgy_pres = in_8(qrio_base + BPRTH_OFF); @@ -57,7 +57,7 @@ int qrio_get_gpio(u8 port_off, u8 gpio_nr) { u32 gprt; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; gprt = in_be32(qrio_base + port_off + GPRT_OFF); @@ -68,7 +68,7 @@ void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value) { u32 gprt, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -85,7 +85,7 @@ void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value) { u32 direct, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -100,7 +100,7 @@ void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr) { u32 direct, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -113,7 +113,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) { u32 direct, mask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; mask = 1U << gpio_nr; @@ -133,7 +133,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val) void qrio_wdmask(u8 bit, bool wden) { u16 wdmask; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; wdmask = in_be16(qrio_base + WDMASK_OFF); @@ -150,7 +150,7 @@ void qrio_wdmask(u8 bit, bool wden) void qrio_prst(u8 bit, bool en, bool wden) { u16 prst; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; qrio_wdmask(bit, wden); @@ -170,7 +170,7 @@ void qrio_prstcfg(u8 bit, u8 mode) { unsigned long prstcfg; u8 i; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; prstcfg = in_be32(qrio_base + PRSTCFG_OFF); @@ -191,7 +191,7 @@ void qrio_prstcfg(u8 bit, u8 mode) void qrio_set_leds(void) { u8 ctrlh; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; /* set UNIT LED to RED and BOOT LED to ON */ ctrlh = in_8(qrio_base + CTRLH_OFF); @@ -205,7 +205,7 @@ void qrio_set_leds(void) void qrio_enable_app_buffer(void) { u8 ctrll; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; /* enable application buffer */ ctrll = in_8(qrio_base + CTRLL_OFF); @@ -219,7 +219,7 @@ void qrio_enable_app_buffer(void) void qrio_cpuwd_flag(bool flag) { u8 reason1; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; reason1 = in_8(qrio_base + REASON1_OFF); if (flag) @@ -246,7 +246,7 @@ void qrio_cpuwd_flag(bool flag) bool qrio_reason_unitrst(void) { u16 reason; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; reason = in_be16(qrio_base + REASON1_OFF); @@ -258,7 +258,7 @@ bool qrio_reason_unitrst(void) void qrio_uprstreq(u8 mode) { u32 rstcfg; - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; rstcfg = in_8(qrio_base + RSTCFG_OFF); @@ -277,7 +277,7 @@ void qrio_uprstreq(u8 mode) ulong early_bootcount_load(void) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); u8 id = (id_rev >> 8) & 0xff; u8 rev = id_rev & 0xff; @@ -295,7 +295,7 @@ ulong early_bootcount_load(void) void early_bootcount_store(ulong ebootcount) { - void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; + void __iomem *qrio_base = (void *)CFG_SYS_QRIO_BASE; u16 id_rev = in_be16(qrio_base + ID_REV_OFF); u8 id = (id_rev >> 8) & 0xff; u8 rev = id_rev & 0xff; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index ddd8f7a13e..88afc76bbb 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -40,7 +40,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; static int piggy_present(void) { struct km_bec_fpga __iomem *base = - (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga __iomem *)CFG_SYS_KMBEC_FPGA_BASE; return in_8(&base->bprth) & PIGGY_PRESENT; } @@ -53,7 +53,7 @@ int ethernet_present(void) int board_early_init_r(void) { struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; #if defined(CONFIG_ARCH_MPC8360) unsigned short svid; @@ -126,18 +126,18 @@ static int fixed_sdram(void) u32 ddr_size_log2; out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); - out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); - out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); - out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); - out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); - out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); - out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); - out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); - out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); + out_be32(&im->ddr.csbnds[0].csbnds, (CFG_SYS_DDR_CS0_BNDS) | 0x7f); + out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); + out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); + out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); + out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); + out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); udelay(200); setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); @@ -215,7 +215,7 @@ int post_hotkeys_pressed(void) { int testpin = 0; struct km_bec_fpga *base = - (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; + (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 6a1711092b..9f68c215f3 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -44,7 +44,7 @@ int checkboard(void) int board_early_init_f(void) { - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); bool cpuwd_flag = false; @@ -141,7 +141,7 @@ int board_early_init_r(void) { int ret = 0; - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const unsigned int flashbase = CFG_SYS_FLASH_BASE; int flash_esel = find_tlb_idx((void *)flashbase, 1); /* @@ -162,7 +162,7 @@ int board_early_init_r(void) disable_tlb(flash_esel); } - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, flash_esel, BOOKE_PAGESZ_256M, 1); diff --git a/board/keymile/kmcent2/law.c b/board/keymile/kmcent2/law.c index b04a8e20dc..ec3bb8fe80 100644 --- a/board/keymile/kmcent2/law.c +++ b/board/keymile/kmcent2/law.c @@ -10,12 +10,12 @@ #include struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), + SET_LAW(CFG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), + SET_LAW(CFG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), + SET_LAW(CFG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), SET_LAW(CFG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CFG_SYS_QRIO_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(SYS_LAWAPP_BASE_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_IFC), /* other application LAW are not used in u-boot */ }; diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c index 0f6dc6063a..41b24e3943 100644 --- a/board/keymile/kmcent2/tlb.c +++ b/board/keymile/kmcent2/tlb.c @@ -11,20 +11,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, + CFG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024, + CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -35,13 +35,13 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), /* *I*G* - Flash, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS, MAS3_SX | MAS3_SR, MAS2_W | MAS2_G, 0, 2, BOOKE_PAGESZ_128M, 1), @@ -56,22 +56,22 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_256K, 1), /* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000, + CFG_SYS_BMAN_MEM_PHYS + 0x01000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000, + CFG_SYS_QMAN_MEM_PHYS + 0x01000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_4M, 1), @@ -80,11 +80,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), /* QRIO */ - SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_QRIO_BASE, CFG_SYS_QRIO_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 11, BOOKE_PAGESZ_64K, 1), /* MRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 12, BOOKE_PAGESZ_128M, 1), /* BFTIC */ @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * in cpu_init_f, so do not use them here!!. */ /* PAXE */ - SET_TLB_ENTRY(1, CONFIG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_PAXE_BASE, SYS_PAXE_BASE_PHYS, MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 16, BOOKE_PAGESZ_128M, 1) }; diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 1a7fa3fc1e..e005ece469 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -52,7 +52,7 @@ int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; + struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; /* Disable unused MCK1 */ setbits_be32(&gur->ddrclkdr, 2); diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index fa95886fa3..238b9637ba 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -232,7 +232,7 @@ int board_init(void) gpmc_init(); #if defined(CONFIG_CMD_ONENAND) enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0], - CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M); + CFG_SYS_ONENAND_BASE, GPMC_SIZE_256M); #endif /* Enable the clks & power */ per_clocks_enable(); diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index 9f21795437..c67c107b16 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -14,7 +14,7 @@ int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc110_chip_probe; diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index 37e911c430..265a2cde4b 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -13,7 +13,7 @@ int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - this->base = (void *)CONFIG_SYS_ONENAND_BASE; + this->base = (void *)CFG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc210_chip_probe; diff --git a/board/siemens/smartweb/smartweb.c b/board/siemens/smartweb/smartweb.c index 3d0f7341a3..15044c7d0e 100644 --- a/board/siemens/smartweb/smartweb.c +++ b/board/siemens/smartweb/smartweb.c @@ -246,7 +246,7 @@ void mem_init(void) setting.cr = SDRAM_BASE_CONF; setting.mdr = AT91_SDRAMC_MD_SDRAM; - setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000; /* * I write here directly in this register, because this diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 1eee972d49..ad44a7c0d2 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -168,7 +168,7 @@ void sdramc_configure(unsigned int mask) at91_sdram_hw_init(); setting.cr = SDRAM_BASE_CONF | mask; setting.mdr = AT91_SDRAMC_MD_SDRAM; - setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000; + setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000; writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC | AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL, diff --git a/board/socrates/law.c b/board/socrates/law.c index 840941b63e..e4427ecff1 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -30,12 +30,12 @@ */ struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), -#if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#if defined(CFG_SYS_FPGA_BASE) + SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ad49999dc2..61402a554b 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -34,20 +34,20 @@ phys_size_t fixed_sdram(void) ddr->cs0_config = 0; ddr->sdram_cfg = 0; - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; + ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CFG_SYS_DDR_MODE; + ddr->sdram_interval = CFG_SYS_DDR_INTERVAL; + ddr->sdram_cfg_2 = CFG_SYS_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CFG_SYS_DDR_CLK_CONTROL; asm ("sync;isync;msync"); udelay(1000); - ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; + ddr->sdram_cfg = CFG_SYS_DDR_CONFIG; asm ("sync; isync; msync"); udelay(1000); @@ -62,7 +62,7 @@ phys_size_t fixed_sdram(void) } #endif -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) int testdram(void) { uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index eaba87542e..9c4dd186fc 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -83,7 +83,7 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + if (gd->bd->bi_flashsize < (0 - CFG_SYS_FLASH0)) { set_lbc_or(0, gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); set_lbc_br(0, gd->bd->bi_flashstart | @@ -98,7 +98,7 @@ int misc_init_r (void) /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CFG_SYS_FLASH0)) { set_lbc_or(1, 0); set_lbc_br(1, 0); @@ -143,7 +143,7 @@ void local_bus_init (void) sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; - uint lcrr = CONFIG_SYS_LBC_LCRR; + uint lcrr = CFG_SYS_LBC_LCRR; get_sys_info (&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; @@ -204,8 +204,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ - val[i++] = CONFIG_SYS_FPGA_BASE; - val[i++] = CONFIG_SYS_FPGA_SIZE; + val[i++] = CFG_SYS_FPGA_BASE; + val[i++] = CFG_SYS_FPGA_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index 1ab403d145..631f6c3407 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -14,16 +14,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR, CFG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 , CFG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 , CFG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 , CFG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -33,7 +33,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -53,12 +53,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#if defined(CONFIG_SYS_FPGA_BASE) +#if defined(CFG_SYS_FPGA_BASE) /* * TLB 4: 1M Non-cacheable, guarded * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, + SET_TLB_ENTRY(1, CFG_SYS_FPGA_BASE, CFG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), #endif @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * (0xcbfc0000 256K LIME GDC MMIO) * MMIO is relocatable and could be at 0xcbfc0000 */ - SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, + SET_TLB_ENTRY(1, CFG_SYS_LIME_BASE, CFG_SYS_LIME_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -79,7 +79,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -91,11 +91,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, CFG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c index 5426fc4ffd..429f886771 100644 --- a/board/sysam/amcore/amcore.c +++ b/board/sysam/amcore/amcore.c @@ -77,7 +77,7 @@ int dram_init(void) * DCR * set proper RC as per specification */ - RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1; + RC = (CFG_SYS_CPU_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* 0x8000 is the faster option */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 34818736a4..1683f780a3 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -121,7 +121,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* adjust memory start address for LPAE */ if (lpae) { start[0] -= CFG_SYS_SDRAM_BASE; - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + start[0] += CFG_SYS_LPAE_SDRAM_BASE; } if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { @@ -175,11 +175,11 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) if (prop1 && prop2) { initrd_start = __be64_to_cpu(*prop1); initrd_start -= CFG_SYS_SDRAM_BASE; - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start += CFG_SYS_LPAE_SDRAM_BASE; initrd_start = __cpu_to_be64(initrd_start); initrd_end = __be64_to_cpu(*prop2); initrd_end -= CFG_SYS_SDRAM_BASE; - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end += CFG_SYS_LPAE_SDRAM_BASE; initrd_end = __cpu_to_be64(initrd_end); err = fdt_delprop(blob, nodeoffset, @@ -223,7 +223,7 @@ void ft_board_setup_ex(void *blob, struct bd_info *bd) if (size) { *reserve_start -= CFG_SYS_SDRAM_BASE; *reserve_start += - CONFIG_SYS_LPAE_SDRAM_BASE; + CFG_SYS_LPAE_SDRAM_BASE; *reserve_start = __cpu_to_be64(*reserve_start); } else { diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 929668ebaa..09cbd6bf71 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -146,7 +146,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ - tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init); + tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init); return 0; } diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index 9d921032ea..bc7e5c5764 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -13,7 +13,7 @@ */ int board_flash_wp_on(void) { - if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + if (pca953x_get_val(CFG_SYS_I2C_PCA953X_ADDR0) & CONFIG_SYS_PCA953X_NVM_WP) return 1; @@ -30,7 +30,7 @@ uint get_board_derivative(void) #if defined(CONFIG_MPC85xx) volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; #elif defined(CONFIG_MPC86xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR; + volatile immap_t *immap = (immap_t *)CFG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; #endif diff --git a/boot/Kconfig b/boot/Kconfig index 4a001bcee8..668270cc66 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -654,7 +654,7 @@ config SYS_MONITOR_BASE default TEXT_BASE help The physical start address of boot monitor code (which is the same as - CONFIG_TEXT_BASE when linking) and the same as CONFIG_SYS_FLASH_BASE + CONFIG_TEXT_BASE when linking) and the same as CFG_SYS_FLASH_BASE when booting from flash. config SPL_SYS_MONITOR_BASE diff --git a/boot/image-board.c b/boot/image-board.c index 8813be544b..0fd63291d3 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -161,8 +161,8 @@ phys_size_t env_get_bootm_mapsize(void) return tmp; } -#if defined(CONFIG_SYS_BOOTMAPSZ) - return CONFIG_SYS_BOOTMAPSZ; +#if defined(CFG_SYS_BOOTMAPSZ) + return CFG_SYS_BOOTMAPSZ; #else return env_get_bootm_size(); #endif diff --git a/cmd/date.c b/cmd/date.c index 0e2dfbc4fc..58505e6e1d 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -51,10 +51,10 @@ static int do_date(struct cmd_tbl *cmdtp, int flag, int argc, } #elif CONFIG_IS_ENABLED(SYS_I2C_LEGACY) old_bus = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM); + i2c_set_bus_num(CFG_SYS_RTC_BUS_NUM); #else old_bus = I2C_GET_BUS(); - I2C_SET_BUS(CONFIG_SYS_RTC_BUS_NUM); + I2C_SET_BUS(CFG_SYS_RTC_BUS_NUM); #endif switch (argc) { diff --git a/cmd/i2c.c b/cmd/i2c.c index 7b84378f7c..da8b4c2555 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -97,19 +97,19 @@ static uint i2c_mm_last_alen; * When multiple buses are present, the list is an array of bus-address * pairs. The following macros take care of this */ -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) static struct { uchar bus; uchar addr; -} i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; +} i2c_no_probes[] = CFG_SYS_I2C_NOPROBES; #define GET_BUS_NUM i2c_get_bus_num() #define COMPARE_BUS(b,i) (i2c_no_probes[(i)].bus == (b)) #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)].addr == (a)) #define NO_PROBE_ADDR(i) i2c_no_probes[(i)].addr #else /* single bus */ -static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; +static uchar i2c_no_probes[] = CFG_SYS_I2C_NOPROBES; #define GET_BUS_NUM 0 #define COMPARE_BUS(b,i) ((b) == 0) /* Make compiler happy */ #define COMPARE_ADDR(a,i) (i2c_no_probes[(i)] == (a)) @@ -912,7 +912,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, int j; int addr = -1; int found = 0; -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) int k, skip; unsigned int bus = GET_BUS_NUM; #endif /* NOPROBES */ @@ -932,7 +932,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, if ((0 <= addr) && (j != addr)) continue; -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) skip = 0; for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) { if (COMPARE_BUS(bus, k) && COMPARE_ADDR(j, k)) { @@ -955,7 +955,7 @@ static int do_i2c_probe(struct cmd_tbl *cmdtp, int flag, int argc, } putc ('\n'); -#if defined(CONFIG_SYS_I2C_NOPROBES) +#if defined(CFG_SYS_I2C_NOPROBES) puts ("Excluded chip addresses:"); for (k = 0; k < ARRAY_SIZE(i2c_no_probes); k++) { if (COMPARE_BUS(bus,k)) @@ -1702,7 +1702,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; - for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { + for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; printf("->%s@0x%2x:%d", @@ -1737,7 +1737,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); #ifndef CONFIG_SYS_I2C_DIRECT_BUS int j; - for (j = 0; j < CONFIG_SYS_I2C_MAX_HOPS; j++) { + for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) break; printf("->%s@0x%2x:%d", diff --git a/common/board_f.c b/common/board_f.c index aab1130763..e027248db5 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -900,9 +900,9 @@ static const init_fnc_t init_sequence_f[] = { post_init_f, #endif INIT_FUNC_WATCHDOG_RESET -#if defined(CONFIG_SYS_DRAM_TEST) +#if defined(CFG_SYS_DRAM_TEST) testdram, -#endif /* CONFIG_SYS_DRAM_TEST */ +#endif /* CFG_SYS_DRAM_TEST */ INIT_FUNC_WATCHDOG_RESET #ifdef CONFIG_POST diff --git a/common/board_r.c b/common/board_r.c index f7fb7df54a..347bb7f7c0 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -346,7 +346,7 @@ static int initr_flash(void) * NOTE: Maybe we should add some schedule()? XXX */ if (env_get_yesno("flashchecksum") == 1) { - const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE; + const uchar *flash_base = (const uchar *)CFG_SYS_FLASH_BASE; printf(" CRC: %08X", crc32(0, flash_base, @@ -356,8 +356,8 @@ static int initr_flash(void) putc('\n'); /* update start of FLASH memory */ -#ifdef CONFIG_SYS_FLASH_BASE - bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#ifdef CFG_SYS_FLASH_BASE + bd->bi_flashstart = CFG_SYS_FLASH_BASE; #endif /* size of FLASH memory (final value) */ bd->bi_flashsize = flash_size; @@ -370,7 +370,7 @@ static int initr_flash(void) #if defined(CONFIG_OXC) || defined(CONFIG_RMU) /* flash mapped at end of memory map */ bd->bi_flashoffset = CONFIG_TEXT_BASE + flash_size; -#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE +#elif CONFIG_SYS_MONITOR_BASE == CFG_SYS_FLASH_BASE bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ #endif return 0; diff --git a/common/spl/Kconfig.nxp b/common/spl/Kconfig.nxp index 8da85539af..fc696cf0ce 100644 --- a/common/spl/Kconfig.nxp +++ b/common/spl/Kconfig.nxp @@ -26,7 +26,7 @@ config SPL_SYS_CCSR_DO_NOT_RELOCATE bool "Ensures that CCSR is not relocated" depends on PPC help - If this is defined, then CONFIG_SYS_CCSRBAR_PHYS will be forced to a + If this is defined, then CFG_SYS_CCSRBAR_PHYS will be forced to a value that ensures that CCSR is not relocated. config TPL_SYS_CCSR_DO_NOT_RELOCATE @@ -59,7 +59,7 @@ config SPL_RELOC_TEXT_BASE config SPL_RELOC_STACK hex "Address of the start of the stack SPL will use after relocation." help - If unspecified, this is equal to CONFIG_SYS_SPL_MALLOC_START. Starting + If unspecified, this is equal to CFG_SYS_SPL_MALLOC_START. Starting address of the malloc pool used in SPL. When this option is set the full malloc is used in SPL and it is set up by spl_init() and before that, the simple malloc() can be used if CONFIG_SYS_MALLOC_F is defined. diff --git a/common/spl/spl.c b/common/spl/spl.c index 22d2a0621e..1d2e8fda72 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -43,8 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; DECLARE_BINMAN_MAGIC_SYM; -#ifndef CONFIG_SYS_UBOOT_START -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#ifndef CFG_SYS_UBOOT_START +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE #endif u32 *boot_params_ptr = NULL; @@ -250,7 +250,7 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) spl_image->entry_point = u_boot_pos; spl_image->load_addr = u_boot_pos; } else { - spl_image->entry_point = CONFIG_SYS_UBOOT_START; + spl_image->entry_point = CFG_SYS_UBOOT_START; spl_image->load_addr = CONFIG_TEXT_BASE; } spl_image->os = IH_OS_U_BOOT; diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index c1ed31e367..08da7fed88 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -828,7 +828,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, } /* - * If a platform does not provide CONFIG_SYS_UBOOT_START, U-Boot's + * If a platform does not provide CFG_SYS_UBOOT_START, U-Boot's * Makefile will set it to 0 and it will end up as the entry point * here. What it actually means is: use the load address. */ diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index eaa95fb9b5..1ef5e41262 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -20,7 +20,7 @@ static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, unsigned long __weak spl_nor_get_uboot_base(void) { - return CONFIG_SYS_UBOOT_BASE; + return CFG_SYS_UBOOT_BASE; } static int spl_nor_load_image(struct spl_image_info *spl_image, diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index da6742416e..2aff025f76 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -31,7 +31,7 @@ static int spi_load_image_os(struct spl_image_info *spl_image, int err; /* Read for a header, parse or error out. */ - spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), + spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, sizeof(*header), (void *)header); if (image_get_magic(header) != IH_MAGIC) @@ -41,12 +41,12 @@ static int spi_load_image_os(struct spl_image_info *spl_image, if (err) return err; - spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, + spi_flash_read(flash, CFG_SYS_SPI_KERNEL_OFFS, spl_image->size, (void *)spl_image->load_addr); /* Read device tree. */ - spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, - CONFIG_SYS_SPI_ARGS_SIZE, + spi_flash_read(flash, CFG_SYS_SPI_ARGS_OFFS, + CFG_SYS_SPI_ARGS_SIZE, (void *)CONFIG_SYS_SPL_ARGS_ADDR); return 0; diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index fb804f0208..bcac25cd02 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -31,7 +31,7 @@ int spl_ubi_load_image(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_ONENAND_SUPPORT case BOOT_DEVICE_ONENAND: info.read = onenand_spl_read_block; - info.peb_size = CONFIG_SYS_ONENAND_BLOCK_SIZE; + info.peb_size = CFG_SYS_ONENAND_BLOCK_SIZE; break; #endif default: diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c index 1258d85e63..77c23ba059 100644 --- a/common/spl/spl_xip.c +++ b/common/spl/spl_xip.c @@ -25,6 +25,6 @@ static int spl_xip(struct spl_image_info *spl_image, } #endif return(spl_parse_image_header(spl_image, bootdev, - (const struct legacy_img_hdr *)CONFIG_SYS_UBOOT_BASE)); + (const struct legacy_img_hdr *)CFG_SYS_UBOOT_BASE)); } SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip); diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index 00e64ba0c7..0b6d2c53db 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -60,7 +60,7 @@ int board_mmc_init(struct bd_info *bd) /* this is a weak define that we are overriding */ int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN); } #endif @@ -70,5 +70,5 @@ and the board definition files needs: /* SD/MMC card */ #define CONFIG_GENERIC_ATMEL_MCI 1 #define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */ -#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 +#define CFG_SYS_MMC_CD_PIN AT91_PIN_PC9 #define CONFIG_CMD_MMC 1 diff --git a/doc/README.cfi b/doc/README.cfi index ad52850818..3818574702 100644 --- a/doc/README.cfi +++ b/doc/README.cfi @@ -35,12 +35,12 @@ In addition, the t3corp board defines the routine thusly: void flash_cmd_reset(flash_info_t *info) { /* - * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and + * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and * needs the Spansion type reset commands. The other flash chip * is located behind a FPGA (Xilinx DS617) and needs the Intel type * reset command. */ - if (info->start[0] == CONFIG_SYS_FLASH_BASE) + if (info->start[0] == CFG_SYS_FLASH_BASE) flash_write_cmd(info, 0, 0, AMD_CMD_RESET); else flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); diff --git a/doc/README.davinci b/doc/README.davinci index 607531af2a..326efa0a2d 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -75,7 +75,7 @@ http://www.ti.com/tool/TMDXLCDK138 Davinci special defines ======================= -CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode +CFG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode need a "NOR Boot Configuration Word" stored in the NOR Flash. This define adds this. More Info about this, see: diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 82fea6201d..767614cbc6 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,7 +11,7 @@ Configuration options CONFIG_USB_OHCI_NEW: enable the new OHCI driver - CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI + CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 3c6ebbdb0e..bafffe6dc5 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) Invalidate unproctected TLB Entries @@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 8) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT @@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "create_init_ram_area" TLB Entry : 15 #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 12) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT diff --git a/doc/README.nand b/doc/README.nand index a3c3ab4b95..3765751253 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -134,7 +134,7 @@ Configuration Options: chip.IO_ADDR_R = ...; chip.IO_ADDR_W = ...; - if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL)) + if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL)) error out /* diff --git a/doc/README.serial_multi b/doc/README.serial_multi index c9049fd01d..0446fe9593 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -35,7 +35,7 @@ just after switching the console: setenv sout serial_scc; setenv baudrate 38400 After that press 'enter' at the SCC console. Note that baudrates <38400 -are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in +are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in include/configs/lwmon.h). diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 584503eb12..770327fea2 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -112,16 +112,16 @@ CONFIG_M5272: Other options, generally set inside include/configs/.h, they may apply to one or more cpu for the ColdFire family: -CONFIG_SYS_MBAR: +CFG_SYS_MBAR: defines the base address of the MCF5272 configuration registers -CONFIG_SYS_SCR: +CFG_SYS_SCR: defines the contents of the System Configuration Register -CONFIG_SYS_SPR: +CFG_SYS_SPR: defines the contents of the System Protection Register -CONFIG_SYS_MFD: +CFG_SYS_MFD: defines the PLL Multiplication Factor Divider (see table 9-4 of MCF user manual) -CONFIG_SYS_RFD: +CFG_SYS_RFD: defines the PLL Reduce Frequency Devider (see table 9-4 of MCF user manual) CONFIG_SYS_CSx_BASE: @@ -136,9 +136,9 @@ CONFIG_SYS_CSx_RO: if set to 0 chip select x is read/write else chip select is read only CONFIG_SYS_CSx_WS: defines the number of wait states of chip select x -CONFIG_SYS_CACHE_ICACR: +CFG_SYS_CACHE_ICACR: cache-related registers config -CONFIG_SYS_CACHE_DCACR: +CFG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config @@ -162,7 +162,7 @@ CFG_SYS_SDRAM_EMOD: these options are used. CONFIG_MCFUART: defines enabling of ColdFire UART driver -CONFIG_SYS_UART_PORT: +CFG_SYS_UART_PORT: defines the UART port to be used (only a single UART can be actually enabled) -CONFIG_SYS_SBFHDR_SIZE: +CFG_SYS_SBFHDR_SIZE: size of the prepended SBF header, if any diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst index 43665de64f..fe1ae210de 100644 --- a/doc/develop/driver-model/migration.rst +++ b/doc/develop/driver-model/migration.rst @@ -99,7 +99,7 @@ The I2C subsystem has supported the driver model since early 2015. Maintainers should submit patches switching over to using CONFIG_DM_I2C and other base driver model options in time for inclusion in the 2021.10 release. -CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER +CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER -------------------------------------------------- Deadline: 2023.01 diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt index 464a85302e..273d8fc796 100644 --- a/doc/device-tree-bindings/video/exynos-dp.txt +++ b/doc/device-tree-bindings/video/exynos-dp.txt @@ -30,9 +30,9 @@ Optional properties: 8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), 10(MOBILE_WHITEBAR_64) samsung,h-sync-polarity: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,v-sync-polarity: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,interlaced: Progressive if 0, else Interlaced samsung,color-space: input video data format COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index b022f6163f..bff0cecfcf 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -23,15 +23,15 @@ Board(panel specific): samsung,vl-height: Height of display area in mm samsung,vl-clkp: Clock polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-oep: Output Enable polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-hsp: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-vsp: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-dp: Data polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-cmd-allow-len: Wait end of frame samsung,winid: Window number on which data is to be displayed diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt index ea0e144ced..6c8c2e594f 100644 --- a/doc/imx/common/imx5.txt +++ b/doc/imx/common/imx5.txt @@ -16,7 +16,7 @@ i.MX5x SoCs. of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. -1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. +1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. This option should be enabled for boards having a SYS_ON_OFF_CTL signal connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the reference designs. diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 15897f63dd..83f210d2d0 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -162,7 +162,7 @@ bootm_low for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and + kernel -- see the description of CFG_SYS_BOOTMAPSZ and bootm_mapsize. bootm_mapsize @@ -170,7 +170,7 @@ bootm_mapsize This variable is given as a hexadecimal number and it defines the size of the memory region starting at base address bootm_low that is accessible by the Linux kernel - during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used + during early boot. If unset, CFG_SYS_BOOTMAPSZ is used as the default value if it is defined, and bootm_size is used otherwise. @@ -228,7 +228,7 @@ initrd_high is usually what you want since it allows for maximum initrd size. If for some reason you want to make sure that the initrd image is loaded below the - CONFIG_SYS_BOOTMAPSZ limit, you can set this environment + CFG_SYS_BOOTMAPSZ limit, you can set this environment variable to a value of "no" or "off" or "0". Alternatively, you can set it to a maximum upper address to use (U-Boot will still check that it diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 8d6424c9da..570252d186 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -83,7 +83,7 @@ config BOOTCOUNT_I2C bool "Boot counter on I2C device" help Enable support for the bootcounter on an i2c (like RTC) device. - CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CFG_SYS_I2C_RTC_ADDR = i2c chip address CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for the bootcounter. diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c index 496741d63f..b3ac67ea35 100644 --- a/drivers/bootcount/bootcount_i2c.c +++ b/drivers/bootcount/bootcount_i2c.c @@ -17,7 +17,7 @@ void bootcount_store(ulong a) buf[0] = BC_MAGIC; buf[1] = (a & 0xff); - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, CONFIG_BOOTCOUNT_ALEN, buf, 2); if (ret != 0) puts("Error writing bootcount\n"); @@ -28,7 +28,7 @@ ulong bootcount_load(void) unsigned char buf[3]; int ret; - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, CONFIG_BOOTCOUNT_ALEN, buf, 2); if (ret != 0) { puts("Error loading bootcount\n"); diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index b2bfb529cc..2fdc2fbd55 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -150,7 +150,7 @@ static int at91_slow_clk_enable(struct clk *clk) static ulong at91_slow_clk_get_rate(struct clk *clk) { - return CONFIG_SYS_AT91_SLOW_CLOCK; + return CFG_SYS_AT91_SLOW_CLOCK; } static struct clk_ops at91_slow_clk_ops = { diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index b79e99b63d..8fde77c23e 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -14,7 +14,7 @@ config SPL_DM help Enable driver model in SPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses @@ -27,7 +27,7 @@ config TPL_DM help Enable driver model in TPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_TPL_SYS_MALLOC_SIMPLE. In that case you must provide CONFIG_SPL_SYS_MALLOC_F_LEN to set the size. In most cases driver model will only allocate a few uclasses @@ -42,7 +42,7 @@ config VPL_DM help Enable driver model in VPL. You will need to provide a suitable malloc() implementation. If you are not using the - full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + full malloc() enabled by CFG_SYS_SPL_MALLOC_START, consider using CONFIG_SPL_SYS_MALLOC_SIMPLE. config DM_WARN diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 4975dbb821..cd332718b6 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -22,7 +22,7 @@ /* * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view - * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * of DDR controllers. It is the same as CFG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff @@ -32,7 +32,7 @@ #ifdef CONFIG_MPC83xx #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_SDRAM_BASE #else -#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CFG_SYS_DDR_SDRAM_BASE #endif #endif diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index a1ff47035b..ca49ee40a7 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -24,8 +24,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */ #endif static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -138,7 +138,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); return FPGA_FAIL; diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index f264ff8c0e..3eed461e1e 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -22,8 +22,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */ #endif static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize); @@ -130,7 +130,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) ts = get_timer(0); /* get current time */ do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index f72dfdec94..57a4532f73 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -21,8 +21,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -149,7 +149,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT and BUSY to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -182,7 +182,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -214,7 +214,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ ret_val = FPGA_FAIL; @@ -333,7 +333,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); return FPGA_FAIL; } @@ -347,7 +347,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); return FPGA_FAIL; } @@ -404,7 +404,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) putc ('*'); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); ret_val = FPGA_FAIL; break; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index b7a063a95f..fdec89bb81 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -26,8 +26,8 @@ #define CONFIG_FPGA_DELAY() #endif -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -154,7 +154,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT and BUSY to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -187,7 +187,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ return FPGA_FAIL; @@ -221,7 +221,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) CONFIG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ ret_val = FPGA_FAIL; @@ -340,7 +340,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) ts = get_timer (0); /* get current time */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); if (*fn->abort) (*fn->abort) (cookie); @@ -356,7 +356,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Now wait for INIT to go high */ do { CONFIG_FPGA_DELAY (); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); if (*fn->abort) (*fn->abort) (cookie); @@ -423,7 +423,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) putc ('*'); - if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ + if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); ret_val = FPGA_FAIL; break; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 0d536f0d04..8871deaea6 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -49,8 +49,8 @@ * which yields 11.44 mS. So let's make it bigger in order to handle * an XC2V1000, if anyone can ever get ahold of one. */ -#ifndef CONFIG_SYS_FPGA_WAIT_INIT -#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ +#ifndef CFG_SYS_FPGA_WAIT_INIT +#define CFG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */ #endif /* @@ -58,15 +58,15 @@ * This is normally not necessary since for most reasonable configuration * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. */ -#ifndef CONFIG_SYS_FPGA_WAIT_BUSY -#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ +#ifndef CFG_SYS_FPGA_WAIT_BUSY +#define CFG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/ #endif /* Default timeout for waiting for FPGA to enter operational mode after * configuration data has been written. */ -#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG -#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ +#ifndef CFG_SYS_FPGA_WAIT_CONFIG +#define CFG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */ #endif static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); @@ -190,9 +190,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) udelay(10); ts = get_timer(0); do { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -209,9 +209,9 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) ts = get_timer(0); do { CONFIG_FPGA_DELAY(); - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); (*fn->abort)(cookie); return FPGA_FAIL; } @@ -260,9 +260,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, break; } - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_CONFIG) { printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n", - __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); + __func__, __LINE__, CFG_SYS_FPGA_WAIT_CONFIG); (*fn->abort)(cookie); ret_val = FPGA_FAIL; break; @@ -350,10 +350,10 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer(0); while ((*fn->busy)(cookie)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT_BUSY) { printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n", __func__, __LINE__, - CONFIG_SYS_FPGA_WAIT_BUSY); + CFG_SYS_FPGA_WAIT_BUSY); (*fn->abort)(cookie); return FPGA_FAIL; } diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 0c83df46da..53dd780a6c 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,8 +36,8 @@ #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif #ifndef CONFIG_SYS_FPGA_PROG_TIME @@ -232,7 +232,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to clear\n", __func__); return FPGA_FAIL; @@ -246,7 +246,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) ts = get_timer(0); while (!(readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to set\n", __func__); return FPGA_FAIL; @@ -400,7 +400,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -484,7 +484,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -561,7 +561,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 2fd2996798..b5ed35256e 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -14,8 +14,8 @@ #include /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_PCA953X_ADDR -#define CONFIG_SYS_I2C_PCA953X_ADDR (~0) +#ifndef CFG_SYS_I2C_PCA953X_ADDR +#define CFG_SYS_I2C_PCA953X_ADDR (~0) #endif enum { @@ -26,14 +26,14 @@ enum { PCA953X_CMD_INVERT, }; -#ifdef CONFIG_SYS_I2C_PCA953X_WIDTH +#ifdef CFG_SYS_I2C_PCA953X_WIDTH struct pca953x_chip_ngpio { uint8_t chip; uint8_t ngpio; }; static struct pca953x_chip_ngpio pca953x_chip_ngpios[] = - CONFIG_SYS_I2C_PCA953X_WIDTH; + CFG_SYS_I2C_PCA953X_WIDTH; /* * Determine the number of GPIO pins supported. If we don't know we assume @@ -204,7 +204,7 @@ static struct cmd_tbl cmd_pca953x[] = { static int do_pca953x(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - static uint8_t chip = CONFIG_SYS_I2C_PCA953X_ADDR; + static uint8_t chip = CFG_SYS_I2C_PCA953X_ADDR; int ret = CMD_RET_USAGE, val; ulong ul_arg2 = 0; ulong ul_arg3 = 0; diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c index 7f67f96b0e..b07496e6e4 100644 --- a/drivers/gpio/tca642x.c +++ b/drivers/gpio/tca642x.c @@ -52,7 +52,7 @@ static int tca642x_reg_write(uchar chip, uint8_t addr, int ret; org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); if (i2c_read(chip, addr, 1, (uint8_t *)&valw, 1)) { printf("Could not read before writing\n"); @@ -76,7 +76,7 @@ static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data) int ret = 0; org_bus_num = i2c_get_bus_num(); - i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM); + i2c_set_bus_num(CFG_SYS_I2C_TCA642X_BUS_NUM); if (i2c_read(chip, addr, 1, (u8 *)&valw, 1)) { ret = -1; goto error; @@ -242,7 +242,7 @@ static struct cmd_tbl cmd_tca642x[] = { static int do_tca642x(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - static uchar chip = CONFIG_SYS_I2C_TCA642X_ADDR; + static uchar chip = CFG_SYS_I2C_TCA642X_ADDR; int ret = CMD_RET_USAGE, val; int gpio_bank = 0; uint8_t bank_shift; diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index ae177227de..25ef937dc0 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -91,7 +91,7 @@ static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base, psc = 2; /* SCLL + SCLH */ - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; + div = (CFG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index edbcd83b64..187db92b75 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_M68K -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR +#define CONFIG_SYS_IMMR CFG_SYS_MBAR #endif #if !CONFIG_IS_ENABLED(DM_I2C) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index c3f6a1251f..7f65db2320 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -35,7 +35,7 @@ struct i2c_adapter *i2c_get_adapter(int index) #if !defined(CONFIG_SYS_I2C_DIRECT_BUS) struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = - CONFIG_SYS_I2C_BUSES; + CFG_SYS_I2C_BUSES; #endif DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +114,7 @@ static int i2c_mux_set_all(void) /* Connect requested bus if behind muxes */ if (i2c_bus_tmp->next_hop[0].chip != 0) { /* Set all muxes along the path to that bus */ - for (i = 0; i < CONFIG_SYS_I2C_MAX_HOPS; i++) { + for (i = 0; i < CFG_SYS_I2C_MAX_HOPS; i++) { int ret; if (i2c_bus_tmp->next_hop[i].chip == 0) @@ -143,7 +143,7 @@ static int i2c_mux_disconnect_all(void) /* Disconnect current bus (turn off muxes if any) */ if ((i2c_bus_tmp->next_hop[0].chip != 0) && (I2C_ADAP->init_done != 0)) { - i = CONFIG_SYS_I2C_MAX_HOPS; + i = CFG_SYS_I2C_MAX_HOPS; do { uint8_t chip; int ret; diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c index 4edcba2911..b9b0ff1c39 100644 --- a/drivers/i2c/kona_i2c.c +++ b/drivers/i2c/kona_i2c.c @@ -129,7 +129,7 @@ struct bcm_kona_i2c_dev { #define DEF_DEVICE(num) \ {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} -static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { +static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = { #ifdef CONFIG_SYS_I2C_BASE0 DEF_DEVICE(0), #endif diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index f48a4f25aa..a9c7d6e1bc 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* CONFIG_DM_I2C */ /* - * On SUNXI, we get CONFIG_SYS_TCLK from this include, so we want to + * On SUNXI, we get CFG_SYS_TCLK from this include, so we want to * always have it. */ #if CONFIG_IS_ENABLED(DM_I2C) && defined(CONFIG_ARCH_SUNXI) @@ -427,9 +427,9 @@ static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) static uint twsi_calc_freq(const int n, const int m) { #ifdef CONFIG_ARCH_SUNXI - return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); + return CFG_SYS_TCLK / (10 * (m + 1) * (1 << n)); #else - return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); + return CFG_SYS_TCLK / (10 * (m + 1) * (2 << n)); #endif } diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index f80ff5383b..9a1599dcd9 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -39,8 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #define VF610_I2C_REGSHIFT 0 #define I2C_EARLY_INIT_INDEX 0 -#ifdef CONFIG_SYS_I2C_IFDR_DIV -#define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV +#ifdef CFG_SYS_I2C_IFDR_DIV +#define I2C_IFDR_DIV_CONSERVATIVE CFG_SYS_I2C_IFDR_DIV #else #define I2C_IFDR_DIV_CONSERVATIVE 0x7e #endif diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 8fdaacd5e0..58b0058736 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -12,37 +12,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "cs0", -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - CONFIG_SYS_CSPR0, -#ifdef CONFIG_SYS_CSPR0_EXT - CONFIG_SYS_CSPR0_EXT, +#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0) + CFG_SYS_CSPR0, +#ifdef CFG_SYS_CSPR0_EXT + CFG_SYS_CSPR0_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK0 - CONFIG_SYS_AMASK0, +#ifdef CFG_SYS_AMASK0 + CFG_SYS_AMASK0, #else 0, #endif - CONFIG_SYS_CSOR0, + CFG_SYS_CSOR0, { - CONFIG_SYS_CS0_FTIM0, - CONFIG_SYS_CS0_FTIM1, - CONFIG_SYS_CS0_FTIM2, - CONFIG_SYS_CS0_FTIM3, + CFG_SYS_CS0_FTIM0, + CFG_SYS_CS0_FTIM1, + CFG_SYS_CS0_FTIM2, + CFG_SYS_CS0_FTIM3, }, -#ifdef CONFIG_SYS_CSOR0_EXT - CONFIG_SYS_CSOR0_EXT, +#ifdef CFG_SYS_CSOR0_EXT + CFG_SYS_CSOR0_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR0_FINAL - CONFIG_SYS_CSPR0_FINAL, +#ifdef CFG_SYS_CSPR0_FINAL + CFG_SYS_CSPR0_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK0_FINAL - CONFIG_SYS_AMASK0_FINAL, +#ifdef CFG_SYS_AMASK0_FINAL + CFG_SYS_AMASK0_FINAL, #else 0, #endif @@ -52,37 +52,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 2 { "cs1", -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - CONFIG_SYS_CSPR1, -#ifdef CONFIG_SYS_CSPR1_EXT - CONFIG_SYS_CSPR1_EXT, +#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1) + CFG_SYS_CSPR1, +#ifdef CFG_SYS_CSPR1_EXT + CFG_SYS_CSPR1_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK1 - CONFIG_SYS_AMASK1, +#ifdef CFG_SYS_AMASK1 + CFG_SYS_AMASK1, #else 0, #endif - CONFIG_SYS_CSOR1, + CFG_SYS_CSOR1, { - CONFIG_SYS_CS1_FTIM0, - CONFIG_SYS_CS1_FTIM1, - CONFIG_SYS_CS1_FTIM2, - CONFIG_SYS_CS1_FTIM3, + CFG_SYS_CS1_FTIM0, + CFG_SYS_CS1_FTIM1, + CFG_SYS_CS1_FTIM2, + CFG_SYS_CS1_FTIM3, }, -#ifdef CONFIG_SYS_CSOR1_EXT - CONFIG_SYS_CSOR1_EXT, +#ifdef CFG_SYS_CSOR1_EXT + CFG_SYS_CSOR1_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR1_FINAL - CONFIG_SYS_CSPR1_FINAL, +#ifdef CFG_SYS_CSPR1_FINAL + CFG_SYS_CSPR1_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK1_FINAL - CONFIG_SYS_AMASK1_FINAL, +#ifdef CFG_SYS_AMASK1_FINAL + CFG_SYS_AMASK1_FINAL, #else 0, #endif @@ -93,37 +93,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 3 { "cs2", -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - CONFIG_SYS_CSPR2, -#ifdef CONFIG_SYS_CSPR2_EXT - CONFIG_SYS_CSPR2_EXT, +#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2) + CFG_SYS_CSPR2, +#ifdef CFG_SYS_CSPR2_EXT + CFG_SYS_CSPR2_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK2 - CONFIG_SYS_AMASK2, +#ifdef CFG_SYS_AMASK2 + CFG_SYS_AMASK2, #else 0, #endif - CONFIG_SYS_CSOR2, + CFG_SYS_CSOR2, { - CONFIG_SYS_CS2_FTIM0, - CONFIG_SYS_CS2_FTIM1, - CONFIG_SYS_CS2_FTIM2, - CONFIG_SYS_CS2_FTIM3, + CFG_SYS_CS2_FTIM0, + CFG_SYS_CS2_FTIM1, + CFG_SYS_CS2_FTIM2, + CFG_SYS_CS2_FTIM3, }, -#ifdef CONFIG_SYS_CSOR2_EXT - CONFIG_SYS_CSOR2_EXT, +#ifdef CFG_SYS_CSOR2_EXT + CFG_SYS_CSOR2_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR2_FINAL - CONFIG_SYS_CSPR2_FINAL, +#ifdef CFG_SYS_CSPR2_FINAL + CFG_SYS_CSPR2_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK2_FINAL - CONFIG_SYS_AMASK2_FINAL, +#ifdef CFG_SYS_AMASK2_FINAL + CFG_SYS_AMASK2_FINAL, #else 0, #endif @@ -134,37 +134,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 4 { "cs3", -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - CONFIG_SYS_CSPR3, -#ifdef CONFIG_SYS_CSPR3_EXT - CONFIG_SYS_CSPR3_EXT, +#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3) + CFG_SYS_CSPR3, +#ifdef CFG_SYS_CSPR3_EXT + CFG_SYS_CSPR3_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK3 - CONFIG_SYS_AMASK3, +#ifdef CFG_SYS_AMASK3 + CFG_SYS_AMASK3, #else 0, #endif - CONFIG_SYS_CSOR3, + CFG_SYS_CSOR3, { - CONFIG_SYS_CS3_FTIM0, - CONFIG_SYS_CS3_FTIM1, - CONFIG_SYS_CS3_FTIM2, - CONFIG_SYS_CS3_FTIM3, + CFG_SYS_CS3_FTIM0, + CFG_SYS_CS3_FTIM1, + CFG_SYS_CS3_FTIM2, + CFG_SYS_CS3_FTIM3, }, -#ifdef CONFIG_SYS_CSOR3_EXT - CONFIG_SYS_CSOR3_EXT, +#ifdef CFG_SYS_CSOR3_EXT + CFG_SYS_CSOR3_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR3_FINAL - CONFIG_SYS_CSPR3_FINAL, +#ifdef CFG_SYS_CSPR3_FINAL + CFG_SYS_CSPR3_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK3_FINAL - CONFIG_SYS_AMASK3_FINAL, +#ifdef CFG_SYS_AMASK3_FINAL + CFG_SYS_AMASK3_FINAL, #else 0, #endif @@ -175,37 +175,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 5 { "cs4", -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - CONFIG_SYS_CSPR4, -#ifdef CONFIG_SYS_CSPR4_EXT - CONFIG_SYS_CSPR4_EXT, +#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4) + CFG_SYS_CSPR4, +#ifdef CFG_SYS_CSPR4_EXT + CFG_SYS_CSPR4_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK4 - CONFIG_SYS_AMASK4, +#ifdef CFG_SYS_AMASK4 + CFG_SYS_AMASK4, #else 0, #endif - CONFIG_SYS_CSOR4, + CFG_SYS_CSOR4, { - CONFIG_SYS_CS4_FTIM0, - CONFIG_SYS_CS4_FTIM1, - CONFIG_SYS_CS4_FTIM2, - CONFIG_SYS_CS4_FTIM3, + CFG_SYS_CS4_FTIM0, + CFG_SYS_CS4_FTIM1, + CFG_SYS_CS4_FTIM2, + CFG_SYS_CS4_FTIM3, }, -#ifdef CONFIG_SYS_CSOR4_EXT - CONFIG_SYS_CSOR4_EXT, +#ifdef CFG_SYS_CSOR4_EXT + CFG_SYS_CSOR4_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR4_FINAL - CONFIG_SYS_CSPR4_FINAL, +#ifdef CFG_SYS_CSPR4_FINAL + CFG_SYS_CSPR4_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK4_FINAL - CONFIG_SYS_AMASK4_FINAL, +#ifdef CFG_SYS_AMASK4_FINAL + CFG_SYS_AMASK4_FINAL, #else 0, #endif @@ -257,37 +257,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 7 { "cs6", -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - CONFIG_SYS_CSPR6, -#ifdef CONFIG_SYS_CSPR6_EXT - CONFIG_SYS_CSPR6_EXT, +#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6) + CFG_SYS_CSPR6, +#ifdef CFG_SYS_CSPR6_EXT + CFG_SYS_CSPR6_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK6 - CONFIG_SYS_AMASK6, +#ifdef CFG_SYS_AMASK6 + CFG_SYS_AMASK6, #else 0, #endif - CONFIG_SYS_CSOR6, + CFG_SYS_CSOR6, { - CONFIG_SYS_CS6_FTIM0, - CONFIG_SYS_CS6_FTIM1, - CONFIG_SYS_CS6_FTIM2, - CONFIG_SYS_CS6_FTIM3, + CFG_SYS_CS6_FTIM0, + CFG_SYS_CS6_FTIM1, + CFG_SYS_CS6_FTIM2, + CFG_SYS_CS6_FTIM3, }, -#ifdef CONFIG_SYS_CSOR6_EXT - CONFIG_SYS_CSOR6_EXT, +#ifdef CFG_SYS_CSOR6_EXT + CFG_SYS_CSOR6_EXT, #else 0, #endif -#ifdef CONFIG_SYS_CSPR6_FINAL - CONFIG_SYS_CSPR6_FINAL, +#ifdef CFG_SYS_CSPR6_FINAL + CFG_SYS_CSPR6_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK6_FINAL - CONFIG_SYS_AMASK6_FINAL, +#ifdef CFG_SYS_AMASK6_FINAL + CFG_SYS_AMASK6_FINAL, #else 0, #endif @@ -298,37 +298,37 @@ struct ifc_regs ifc_cfg_default_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { #if CONFIG_SYS_FSL_IFC_BANK_COUNT >= 8 { "cs7", -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - CONFIG_SYS_CSPR7, -#ifdef CONFIG_SYS_CSPR7_EXT - CONFIG_SYS_CSPR7_EXT, +#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7) + CFG_SYS_CSPR7, +#ifdef CFG_SYS_CSPR7_EXT + CFG_SYS_CSPR7_EXT, #else 0, #endif -#ifdef CONFIG_SYS_AMASK7 - CONFIG_SYS_AMASK7, +#ifdef CFG_SYS_AMASK7 + CFG_SYS_AMASK7, #else 0, #endif - CONFIG_SYS_CSOR7, -#ifdef CONFIG_SYS_CSOR7_EXT - CONFIG_SYS_CSOR7_EXT, + CFG_SYS_CSOR7, +#ifdef CFG_SYS_CSOR7_EXT + CFG_SYS_CSOR7_EXT, #else 0, #endif { - CONFIG_SYS_CS7_FTIM0, - CONFIG_SYS_CS7_FTIM1, - CONFIG_SYS_CS7_FTIM2, - CONFIG_SYS_CS7_FTIM3, + CFG_SYS_CS7_FTIM0, + CFG_SYS_CS7_FTIM1, + CFG_SYS_CS7_FTIM2, + CFG_SYS_CS7_FTIM3, }, -#ifdef CONFIG_SYS_CSPR7_FINAL - CONFIG_SYS_CSPR7_FINAL, +#ifdef CFG_SYS_CSPR7_FINAL + CFG_SYS_CSPR7_FINAL, #else 0, #endif -#ifdef CONFIG_SYS_AMASK7_FINAL - CONFIG_SYS_AMASK7_FINAL, +#ifdef CFG_SYS_AMASK7_FINAL + CFG_SYS_AMASK7_FINAL, #else 0, #endif @@ -412,91 +412,91 @@ void init_final_memctl_regs(void) #else void init_early_memctl_regs(void) { -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); +#if defined(CFG_SYS_CSPR0) && defined(CFG_SYS_CSOR0) + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CFG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CFG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CFG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CFG_SYS_CS0_FTIM3); #ifndef CONFIG_A003399_NOR_WORKAROUND -#ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#ifdef CFG_SYS_CSPR0_EXT + set_ifc_cspr_ext(IFC_CS0, CFG_SYS_CSPR0_EXT); #endif -#ifdef CONFIG_SYS_CSOR0_EXT - set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); +#ifdef CFG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CFG_SYS_CSOR0_EXT); #endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); + set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CFG_SYS_CSOR0); #endif #endif -#ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); +#ifdef CFG_SYS_CSPR1_EXT + set_ifc_cspr_ext(IFC_CS1, CFG_SYS_CSPR1_EXT); #endif -#ifdef CONFIG_SYS_CSOR1_EXT - set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#ifdef CFG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CFG_SYS_CSOR1_EXT); #endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); +#if defined(CFG_SYS_CSPR1) && defined(CFG_SYS_CSOR1) + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CFG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CFG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CFG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CFG_SYS_CS1_FTIM3); - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); + set_ifc_csor(IFC_CS1, CFG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1); #endif -#ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); +#ifdef CFG_SYS_CSPR2_EXT + set_ifc_cspr_ext(IFC_CS2, CFG_SYS_CSPR2_EXT); #endif -#ifdef CONFIG_SYS_CSOR2_EXT - set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#ifdef CFG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CFG_SYS_CSOR2_EXT); #endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); +#if defined(CFG_SYS_CSPR2) && defined(CFG_SYS_CSOR2) + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CFG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CFG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CFG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CFG_SYS_CS2_FTIM3); - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); + set_ifc_csor(IFC_CS2, CFG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2); #endif -#ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); +#ifdef CFG_SYS_CSPR3_EXT + set_ifc_cspr_ext(IFC_CS3, CFG_SYS_CSPR3_EXT); #endif -#ifdef CONFIG_SYS_CSOR3_EXT - set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#ifdef CFG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CFG_SYS_CSOR3_EXT); #endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); +#if defined(CFG_SYS_CSPR3) && defined(CFG_SYS_CSOR3) + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CFG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CFG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CFG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CFG_SYS_CS3_FTIM3); - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); + set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CFG_SYS_CSOR3); #endif -#ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); +#ifdef CFG_SYS_CSPR4_EXT + set_ifc_cspr_ext(IFC_CS4, CFG_SYS_CSPR4_EXT); #endif -#ifdef CONFIG_SYS_CSOR4_EXT - set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#ifdef CFG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CFG_SYS_CSOR4_EXT); #endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); +#if defined(CFG_SYS_CSPR4) && defined(CFG_SYS_CSOR4) + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CFG_SYS_CS4_FTIM0); + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CFG_SYS_CS4_FTIM1); + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CFG_SYS_CS4_FTIM2); + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CFG_SYS_CS4_FTIM3); - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); + set_ifc_cspr(IFC_CS4, CFG_SYS_CSPR4); + set_ifc_amask(IFC_CS4, CFG_SYS_AMASK4); + set_ifc_csor(IFC_CS4, CFG_SYS_CSOR4); #endif #ifdef CONFIG_SYS_CSPR5_EXT @@ -516,66 +516,66 @@ void init_early_memctl_regs(void) set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); #endif -#ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); +#ifdef CFG_SYS_CSPR6_EXT + set_ifc_cspr_ext(IFC_CS6, CFG_SYS_CSPR6_EXT); #endif -#ifdef CONFIG_SYS_CSOR6_EXT - set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#ifdef CFG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CFG_SYS_CSOR6_EXT); #endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); +#if defined(CFG_SYS_CSPR6) && defined(CFG_SYS_CSOR6) + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CFG_SYS_CS6_FTIM0); + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CFG_SYS_CS6_FTIM1); + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CFG_SYS_CS6_FTIM2); + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CFG_SYS_CS6_FTIM3); - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); + set_ifc_cspr(IFC_CS6, CFG_SYS_CSPR6); + set_ifc_amask(IFC_CS6, CFG_SYS_AMASK6); + set_ifc_csor(IFC_CS6, CFG_SYS_CSOR6); #endif -#ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); +#ifdef CFG_SYS_CSPR7_EXT + set_ifc_cspr_ext(IFC_CS7, CFG_SYS_CSPR7_EXT); #endif -#ifdef CONFIG_SYS_CSOR7_EXT - set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#ifdef CFG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CFG_SYS_CSOR7_EXT); #endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); +#if defined(CFG_SYS_CSPR7) && defined(CFG_SYS_CSOR7) + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CFG_SYS_CS7_FTIM0); + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CFG_SYS_CS7_FTIM1); + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CFG_SYS_CS7_FTIM2); + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CFG_SYS_CS7_FTIM3); - set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); + set_ifc_cspr(IFC_CS7, CFG_SYS_CSPR7); + set_ifc_amask(IFC_CS7, CFG_SYS_AMASK7); + set_ifc_csor(IFC_CS7, CFG_SYS_CSOR7); #endif } void init_final_memctl_regs(void) { -#ifdef CONFIG_SYS_CSPR0_FINAL - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0_FINAL); +#ifdef CFG_SYS_CSPR0_FINAL + set_ifc_cspr(IFC_CS0, CFG_SYS_CSPR0_FINAL); #endif -#ifdef CONFIG_SYS_AMASK0_FINAL - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); +#ifdef CFG_SYS_AMASK0_FINAL + set_ifc_amask(IFC_CS0, CFG_SYS_AMASK0); #endif -#ifdef CONFIG_SYS_CSPR1_FINAL - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1_FINAL); +#ifdef CFG_SYS_CSPR1_FINAL + set_ifc_cspr(IFC_CS1, CFG_SYS_CSPR1_FINAL); #endif -#ifdef CONFIG_SYS_AMASK1_FINAL - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1_FINAL); +#ifdef CFG_SYS_AMASK1_FINAL + set_ifc_amask(IFC_CS1, CFG_SYS_AMASK1_FINAL); #endif -#ifdef CONFIG_SYS_CSPR2_FINAL - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2_FINAL); +#ifdef CFG_SYS_CSPR2_FINAL + set_ifc_cspr(IFC_CS2, CFG_SYS_CSPR2_FINAL); #endif -#ifdef CONFIG_SYS_AMASK2_FINAL - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); +#ifdef CFG_SYS_AMASK2_FINAL + set_ifc_amask(IFC_CS2, CFG_SYS_AMASK2); #endif -#ifdef CONFIG_SYS_CSPR3_FINAL - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3_FINAL); +#ifdef CFG_SYS_CSPR3_FINAL + set_ifc_cspr(IFC_CS3, CFG_SYS_CSPR3_FINAL); #endif -#ifdef CONFIG_SYS_AMASK3_FINAL - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); +#ifdef CFG_SYS_AMASK3_FINAL + set_ifc_amask(IFC_CS3, CFG_SYS_AMASK3); #endif } #endif diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 9c4b4d7e46..6b831281e9 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -20,25 +20,25 @@ #endif #include -#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE) -#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE) +#define MAX_BPORTALS (CFG_SYS_BMAN_CINH_SIZE / CFG_SYS_BMAN_SP_CINH_SIZE) +#define MAX_QPORTALS (CFG_SYS_QMAN_CINH_SIZE / CFG_SYS_QMAN_SP_CINH_SIZE) void setup_qbman_portals(void) { - void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE + - CONFIG_SYS_BMAN_SWP_ISDR_REG; - void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + - CONFIG_SYS_QMAN_SWP_ISDR_REG; + void __iomem *bpaddr = (void *)CFG_SYS_BMAN_CINH_BASE + + CFG_SYS_BMAN_SWP_ISDR_REG; + void __iomem *qpaddr = (void *)CFG_SYS_QMAN_CINH_BASE + + CFG_SYS_QMAN_SWP_ISDR_REG; struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR; /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ #ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); + out_be32(&qman->qcsp_bare, (u32)(CFG_SYS_QMAN_MEM_PHYS >> 32)); #endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); + out_be32(&qman->qcsp_bar, (u32)CFG_SYS_QMAN_MEM_PHYS); #ifdef CONFIG_FSL_CORENET int i; - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; u16 dliodn = qp_info[i].dliodn; @@ -53,7 +53,7 @@ void setup_qbman_portals(void) #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) int i; - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { + for (i = 0; i < CFG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 ficid = qp_info[i].ficid; u16 dicid = qp_info[i].dicid; @@ -68,10 +68,10 @@ void setup_qbman_portals(void) #endif /* Change default state of BMan ISDR portals to all 1s */ - inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, - CONFIG_SYS_BMAN_SP_CINH_SIZE); - inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, - CONFIG_SYS_QMAN_SP_CINH_SIZE); + inhibit_portals(bpaddr, CFG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS, + CFG_SYS_BMAN_SP_CINH_SIZE); + inhibit_portals(qpaddr, CFG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS, + CFG_SYS_QMAN_SP_CINH_SIZE); } void inhibit_portals(void __iomem *addr, int max_portals, diff --git a/drivers/misc/fsl_sec_mon.c b/drivers/misc/fsl_sec_mon.c index 321bd27fd3..3597ee2224 100644 --- a/drivers/misc/fsl_sec_mon.c +++ b/drivers/misc/fsl_sec_mon.c @@ -10,7 +10,7 @@ static u32 get_sec_mon_state(void) { struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); return sec_mon_in32(&sec_mon_regs->hp_stat) & HPSR_SSM_ST_MASK; } @@ -19,7 +19,7 @@ static int set_sec_mon_state_non_sec(void) u32 sts; int timeout = 10; struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); sts = get_sec_mon_state(); @@ -120,7 +120,7 @@ static int set_sec_mon_state_soft_fail(void) u32 sts; int timeout = 10; struct ccsr_sec_mon_regs *sec_mon_regs = (void *) - (CONFIG_SYS_SEC_MON_ADDR); + (CFG_SYS_SEC_MON_ADDR); printf("SEC_MON state transitioning to Soft Fail.\n"); sec_mon_setbits32(&sec_mon_regs->hp_com, HPCOMR_SW_FSV); diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index aa00d7e201..6d7c0cff22 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -9,7 +9,7 @@ #include #include -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS extern uchar mmc_u_boot_offs[]; #endif @@ -97,7 +97,7 @@ void __noreturn mmc_boot(void) } #ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_MMC_U_BOOT_OFFS; + offset = CFG_SYS_MMC_U_BOOT_OFFS; #else sector = 0; again: @@ -153,16 +153,16 @@ again: val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } -#ifndef CONFIG_SYS_MMC_U_BOOT_OFFS +#ifndef CFG_SYS_MMC_U_BOOT_OFFS offset += (ulong)&mmc_u_boot_offs - CONFIG_SPL_TEXT_BASE; #else - offset += CONFIG_SYS_MMC_U_BOOT_OFFS; + offset += CFG_SYS_MMC_U_BOOT_OFFS; #endif #endif /* * Load U-Boot image from mmc into RAM */ - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; + code_len = CFG_SYS_MMC_U_BOOT_SIZE; blk_start = offset / mmc->read_bl_len; blk_off = offset % mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; @@ -176,7 +176,7 @@ again: blk_start++; } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (uchar *)CFG_SYS_MMC_U_BOOT_DST + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); @@ -189,18 +189,18 @@ again: * after SDHC DMA transfer. */ if (blk_off) - memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + memcpy((uchar *)CFG_SYS_MMC_U_BOOT_DST, tmp_buf + blk_off, mmc->read_bl_len - blk_off); /* * Clean d-cache and invalidate i-cache, to * make sure that no stale data is executed. */ - flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE); + flush_cache(CFG_SYS_MMC_U_BOOT_DST, CFG_SYS_MMC_U_BOOT_SIZE); /* * Jump to U-Boot image */ - uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START; + uboot = (void *)CFG_SYS_MMC_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 607a22368c..d91819acfd 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -24,8 +24,8 @@ #include #include "atmel_mci.h" -#ifndef CONFIG_SYS_MMC_CLK_OD -# define CONFIG_SYS_MMC_CLK_OD 150000 +#ifndef CFG_SYS_MMC_CLK_OD +# define CFG_SYS_MMC_CLK_OD 150000 #endif #define MMC_DEFAULT_BLKLEN 512 @@ -448,9 +448,9 @@ static int mci_init(struct mmc *mmc) /* Set default clocks and blocklen */ #ifdef CONFIG_DM_MMC - mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(dev, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #else - mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); + mci_set_mode(mmc, CFG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); #endif return 0; diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index b2d0fac963..3ce7cbf71f 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -761,7 +761,7 @@ int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks) struct mmc *mmc; struct sh_sdhi_host *host = NULL; - if (ch >= CONFIG_SYS_SH_SDHI_NR_CHANNEL) + if (ch >= CFG_SYS_SH_SDHI_NR_CHANNEL) return -ENODEV; host = malloc(sizeof(struct sh_sdhi_host)); diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index d34d8ee976..c1cdd2cbc3 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -53,7 +53,7 @@ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * - * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between + * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between * reading and writing ... (yes there is such a Hardware). */ @@ -119,14 +119,14 @@ phys_addr_t cfi_flash_bank_addr(int i) #else __weak phys_addr_t cfi_flash_bank_addr(int i) { - return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; + return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i]; } #endif __weak unsigned long cfi_flash_bank_size(int i) { -#ifdef CONFIG_SYS_FLASH_BANKS_SIZES - return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; +#ifdef CFG_SYS_FLASH_BANKS_SIZES + return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i]; #else return 0; #endif @@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr) */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \ (defined(CONFIG_SYS_MONITOR_BASE) && \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)) + (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE)) static flash_info_t *flash_get_info(ulong base) { int i; @@ -227,7 +227,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) int i; int cword_offset; int cp_offset; -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) u32 cmd_le = cpu_to_le32(cmd); #endif uchar val; @@ -235,7 +235,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) for (i = info->portwidth; i > 0; i--) { cword_offset = (info->portwidth - i) % info->chipwidth; -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) cp_offset = info->portwidth - i; val = *((uchar *)&cmd_le + cword_offset); #else @@ -292,7 +292,7 @@ static inline uchar flash_read_uchar(flash_info_t *info, uint offset) uchar retval; cp = flash_map(info, 0, offset); -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) retval = flash_read8(cp); #else retval = flash_read8(cp + info->portwidth - 1); @@ -335,7 +335,7 @@ static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, for (x = 0; x < 4 * info->portwidth; x++) debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); #endif -#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA) retval = ((flash_read8(addr) << 16) | (flash_read8(addr + info->portwidth) << 24) | (flash_read8(addr + 2 * info->portwidth)) | @@ -580,7 +580,7 @@ static int flash_status_check(flash_info_t *info, flash_sect_t sector, #endif /* Wait for command completion */ -#ifdef CONFIG_SYS_LOW_RES_TIMER +#ifdef CFG_SYS_LOW_RES_TIMER reset_timer(); #endif start = get_timer(0); @@ -673,7 +673,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, #endif /* Wait for command completion */ -#ifdef CONFIG_SYS_LOW_RES_TIMER +#ifdef CFG_SYS_LOW_RES_TIMER reset_timer(); #endif start = get_timer(0); @@ -713,7 +713,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst, */ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) { -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) unsigned short w; unsigned int l; unsigned long long ll; @@ -724,7 +724,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) cword->w8 = c; break; case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) w = c; w <<= 8; cword->w16 = (cword->w16 >> 8) | w; @@ -733,7 +733,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) #endif break; case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) l = c; l <<= 24; cword->w32 = (cword->w32 >> 8) | l; @@ -742,7 +742,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) #endif break; case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; cword->w64 = (cword->w64 >> 8) | ll; @@ -2359,7 +2359,7 @@ static void flash_protect_default(void) /* Monitor protection ON by default */ #if defined(CONFIG_SYS_MONITOR_BASE) && \ - (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ + (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \ (!defined(CONFIG_MONITOR_IS_IN_RAM)) flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c index 59de325640..18abd75441 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c @@ -780,10 +780,10 @@ static void fsl_ifc_ctrl_init(void) ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) ifc_ctrl->regs.rregs = - (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; + (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; else ifc_ctrl->regs.rregs = - (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; + (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; /* clear event registers */ ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U); diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 7d4b77dd11..3b464ce10c 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -54,14 +54,14 @@ static inline int check_read_ecc(uchar *buf, u32 *eccstat, static inline struct fsl_ifc_runtime *runtime_regs_address(void) { - struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL}; + struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL}; int ver = 0; ver = ifc_in32(®s.gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) - regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; + regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET; else - regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; + regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET; return regs.rregs; } @@ -108,7 +108,7 @@ static inline int bad_block(uchar *marker, int port_size) int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { - struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR; + struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR; struct fsl_ifc_runtime *ifc = NULL; uchar *buf = (uchar *)CFG_SYS_NAND_BASE; int page_size; diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 5bc5301d63..a884c65d18 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -84,8 +84,8 @@ struct lpc32xx_nand_mlc_registers { static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE; -#if !defined(CONFIG_SYS_MAX_NAND_CHIPS) -#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#if !defined(CFG_SYS_MAX_NAND_CHIPS) +#define CFG_SYS_MAX_NAND_CHIPS 1 #endif #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o) @@ -586,7 +586,7 @@ void board_nand_init(void) lpc32xx_nand_init(); /* identify chip */ - ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL); + ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL); if (ret) { pr_err("nand_scan_ident returned %i", ret); return; diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index ab6f1a8be3..2699958a5d 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -49,12 +49,12 @@ static inline int onenand_bufferram_address(int block) static inline uint16_t onenand_readw(uint32_t addr) { - return readw(CONFIG_SYS_ONENAND_BASE + addr); + return readw(CFG_SYS_ONENAND_BASE + addr); } static inline void onenand_writew(uint16_t value, uint32_t addr) { - writew(value, CONFIG_SYS_ONENAND_BASE + addr); + writew(value, CFG_SYS_ONENAND_BASE + addr); } static enum onenand_spl_pagesize onenand_spl_get_geometry(void) @@ -82,7 +82,7 @@ static enum onenand_spl_pagesize onenand_spl_get_geometry(void) static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf, enum onenand_spl_pagesize pagesize) { - const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM; + const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM; uint32_t offset; onenand_writew(onenand_block_address(block), diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 3a8c7b867e..04791df69b 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -35,7 +35,7 @@ void onenand_init(void) /* It's used for some board init required */ err = onenand_board_init(&onenand_mtd); #else - onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE; + onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE; #endif if (!err && !(onenand_scan(&onenand_mtd, 1))) { diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index 5c41d7558c..dfc35d6eab 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -49,8 +49,8 @@ void fsl_spi_boot(void) } #ifdef CONFIG_FSL_CORENET - offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; - code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE; + offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS; + code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE; #else /* * Load U-Boot image from SPI flash into RAM @@ -66,7 +66,7 @@ void fsl_spi_boot(void) flash->page_size, (void *)buf); offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR); /* Skip spl code */ - offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS; + offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS; /* Get the code size from offset 0x48 */ code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE); /* Skip spl code */ @@ -76,7 +76,7 @@ void fsl_spi_boot(void) printf("Loading second stage boot loader "); while (copy_len <= code_len) { spi_flash_read(flash, offset + copy_len, 0x2000, - (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST + (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST + copy_len)); copy_len = copy_len + 0x2000; putc('.'); @@ -85,7 +85,7 @@ void fsl_spi_boot(void) /* * Jump to U-Boot image */ - flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len); - uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START; + flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len); + uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START; (*uboot)(); } diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c index 95afa2d6bc..4523344ba6 100644 --- a/drivers/mtd/stm32_flash.c +++ b/drivers/mtd/stm32_flash.c @@ -39,7 +39,7 @@ unsigned long flash_init(void) for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_STM32; flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20); + flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20); flash_info[i].size = sect_sz_kb[0]; for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) { flash_info[i].start[j] = flash_info[i].start[j - 1] diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index c23e0c0770..c8381cc713 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -128,7 +128,7 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR; /* Assign a Physical address to the TBI */ - out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); + out_be32(®s->tbipa, CFG_SYS_TBIPA_VALUE); #endif if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII || diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 1d3b7aa058..c476cb3120 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -67,9 +67,9 @@ static void fm_init_muram(int fm_idx, void *reg) void *base = reg; muram[fm_idx].base = base; - muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE; muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE; - muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE; + muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE; } /* diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 8443cbb6b6..618c1bccbe 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -244,9 +244,9 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { int off; uint32_t ph; - phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; + phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset; #ifndef CONFIG_SYS_FMAN_V3 - u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + + u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS + CFG_SYS_FSL_FM1_DTSEC1_OFFSET; #endif diff --git a/drivers/net/fsl-mc/dpio/qbman_sys.h b/drivers/net/fsl-mc/dpio/qbman_sys.h index 8be38e11a8..ff998d49dc 100644 --- a/drivers/net/fsl-mc/dpio/qbman_sys.h +++ b/drivers/net/fsl-mc/dpio/qbman_sys.h @@ -256,12 +256,12 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s, s->addr_cena = d->cena_bar; s->addr_cinh = d->cinh_bar; - s->cena = (void *)valloc(CONFIG_SYS_PAGE_SIZE); + s->cena = (void *)valloc(CFG_SYS_PAGE_SIZE); if (!s->cena) { printf("Could not allocate page for cena shadow\n"); return -1; } - memset((void *)s->cena, 0x00, CONFIG_SYS_PAGE_SIZE); + memset((void *)s->cena, 0x00, CFG_SYS_PAGE_SIZE); #ifdef QBMAN_CHECKING /* We should never be asked to initialise for a portal that isn't in diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 68833f9ddd..69da465eaa 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -54,7 +54,7 @@ static int mc_memset_resv_ram; static struct mc_version mc_ver_info; static int mc_boot_status = -1; static int mc_dpl_applied = -1; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET static int mc_aiop_applied = -1; #endif struct fsl_mc_io *root_mc_io = NULL; @@ -500,13 +500,13 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) int dpc_size; #endif -#ifdef CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET - BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); +#ifdef CFG_SYS_LS_MC_DRAM_DPC_OFFSET + BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPC_OFFSET & 0x3) != 0 || + CFG_SYS_LS_MC_DRAM_DPC_OFFSET > 0xffffffff); - mc_dpc_offset = CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET; + mc_dpc_offset = CFG_SYS_LS_MC_DRAM_DPC_OFFSET; #else -#error "CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" +#error "CFG_SYS_LS_MC_DRAM_DPC_OFFSET not defined" #endif /* @@ -531,7 +531,7 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) } dpc_size = fdt_totalsize(dpc_fdt_hdr); - if (dpc_size > CONFIG_SYS_LS_MC_DPC_MAX_LENGTH) { + if (dpc_size > CFG_SYS_LS_MC_DPC_MAX_LENGTH) { printf("\nfsl-mc: ERROR: Bad DPC image (too large: %d)\n", dpc_size); return -EINVAL; @@ -576,13 +576,13 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) int dpl_size; #endif -#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET - BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); +#ifdef CFG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON((CFG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CFG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); - mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; + mc_dpl_offset = CFG_SYS_LS_MC_DRAM_DPL_OFFSET; #else -#error "CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" +#error "CFG_SYS_LS_MC_DRAM_DPL_OFFSET not defined" #endif /* @@ -603,7 +603,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) } dpl_size = fdt_totalsize(dpl_fdt_hdr); - if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { + if (dpl_size > CFG_SYS_LS_MC_DPL_MAX_LENGTH) { printf("\nfsl-mc: ERROR: Bad DPL image (too large: %d)\n", dpl_size); return -EINVAL; @@ -624,7 +624,7 @@ static int load_mc_dpl(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpl_addr) */ static unsigned long get_mc_boot_timeout_ms(void) { - unsigned long timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + unsigned long timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS; char *timeout_ms_env_var = env_get(MC_BOOT_TIMEOUT_ENV_VAR); @@ -636,14 +636,14 @@ static unsigned long get_mc_boot_timeout_ms(void) "\' environment variable: %lu\n", timeout_ms); - timeout_ms = CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS; + timeout_ms = CFG_SYS_LS_MC_BOOT_TIMEOUT_MS; } } return timeout_ms; } -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET __weak bool soc_has_aiop(void) { @@ -666,12 +666,12 @@ static int load_mc_aiop_img(u64 aiop_fw_addr) #ifdef CONFIG_SYS_LS_MC_DPC_IN_DDR printf("MC AIOP is preloaded to %#llx\n", mc_ram_addr + - CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #else aiop_img = (void *)aiop_fw_addr; mc_copy_image("MC AIOP image", - (u64)aiop_img, CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, - mc_ram_addr + CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); + (u64)aiop_img, CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH, + mc_ram_addr + CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET); #endif mc_aiop_applied = 0; @@ -896,7 +896,7 @@ int get_mc_boot_status(void) return mc_boot_status; } -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void) { return mc_aiop_applied; @@ -938,14 +938,14 @@ u64 mc_get_dram_addr(void) */ unsigned long mc_get_dram_block_size(void) { - unsigned long dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; + unsigned long dram_block_size = CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; char *dram_block_size_env_var = env_get(MC_MEM_SIZE_ENV_VAR); if (dram_block_size_env_var) { dram_block_size = hextoul(dram_block_size_env_var, NULL); - if (dram_block_size < CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { + if (dram_block_size < CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE) { printf("fsl-mc: WARNING: Invalid value for \'" MC_MEM_SIZE_ENV_VAR "\' environment variable: %lu\n", @@ -1838,7 +1838,7 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, case 's': { char sub_cmd; u64 mc_fw_addr, mc_dpc_addr; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET u64 aiop_fw_addr; #endif if (argc < 3) @@ -1864,7 +1864,7 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, err = mc_init_object(); break; -#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET +#ifdef CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET case 'a': if (argc < 4) goto usage; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 6825f9e27c..cc61a10740 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -43,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR; static void init_eth_info(struct fec_info_dma *info) { /* setup Receive and Transmit buffer descriptor */ -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifdef CFG_SYS_FEC_BUF_USE_SRAM static u32 tmp; if (info->index == 0) - tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; else info->rxbd = (cbd_t *)DBUF_LENGTH; @@ -59,7 +59,7 @@ static void init_eth_info(struct fec_info_dma *info) tmp = (u32)info->txbd; info->txbuf = (char *)((u32)info->txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)info->txbuf; #else info->rxbd = @@ -67,7 +67,7 @@ static void init_eth_info(struct fec_info_dma *info) (PKTBUFSRX * sizeof(cbd_t))); info->txbd = (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); info->txbuf = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); #endif @@ -283,15 +283,15 @@ static int fec_init(struct udevice *dev) /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) * Settings: Last, Tx CRC */ - for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) { + for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) { info->txbd[i].cbd_sc = 0; info->txbd[i].cbd_datlen = 0; info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); } - info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; info->used_tbd_idx = 0; - info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER; + info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER; /* Set Rx FIFO alarm and granularity value */ fecp->rfcr = 0x0c000000; @@ -352,7 +352,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status); /* process all the consumed TBDs */ - while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) { + while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) { p_used_tbd = &info->txbd[info->used_tbd_idx]; if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) { #ifdef ET_DEBUG @@ -363,7 +363,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) } /* clean this buffer descriptor */ - if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1)) + if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1)) p_used_tbd->cbd_sc = BD_ENET_TX_WRAP; else p_used_tbd->cbd_sc = 0; @@ -371,7 +371,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) /* update some indeces for a correct handling of TBD ring */ info->clean_tbd_num++; info->used_tbd_idx = (info->used_tbd_idx + 1) - % CONFIG_SYS_TX_ETH_BUFFER; + % CFG_SYS_TX_ETH_BUFFER; } /* Check for valid length of data. */ @@ -389,7 +389,7 @@ static int mcdmafec_send(struct udevice *dev, void *packet, int length) p_tbd->cbd_datlen = length; p_tbd->cbd_bufaddr = (u32)packet; p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER; + info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER; /* Enable DMA transmit task */ MCD_continDma(info->tx_task); @@ -524,8 +524,8 @@ static int mcdmafec_probe(struct udevice *dev) if (val) info->tx_init = fdt32_to_cpu(*val); -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM - u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; +#ifdef CFG_SYS_FEC_BUF_USE_SRAM + u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; #endif init_eth_info(info); diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 4dd848932b..ec1fae9688 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -39,11 +39,11 @@ DECLARE_GLOBAL_DATA_PTR; static void init_eth_info(struct fec_info_s *info) { -#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifdef CFG_SYS_FEC_BUF_USE_SRAM static u32 tmp; if (info->index == 0) - tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000; + tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; else info->rxbd = (cbd_t *)DBUF_LENGTH; @@ -56,7 +56,7 @@ static void init_eth_info(struct fec_info_s *info) tmp = (u32)info->txbd; info->txbuf = (char *)((u32)info->txbuf + tmp + - (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); + (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); tmp = (u32)info->txbuf; #else info->rxbd = @@ -387,7 +387,7 @@ static int mcffec_send(struct udevice *dev, void *packet, int length) /* Activate transmit Buffer Descriptor polling */ fecp->tdar = 0x01000000; /* Descriptor polling active */ -#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM +#ifndef CFG_SYS_FEC_BUF_USE_SRAM /* * FEC unable to initial transmit data packet. * A nop will ensure the descriptor polling active completed. diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h index 32b7d3e561..551d7061cc 100644 --- a/drivers/net/qe/uec.h +++ b/drivers/net/qe/uec.h @@ -605,10 +605,10 @@ enum uec_num_of_threads { #define STD_UEC_INFO(num) \ { \ .uf_info = { \ - .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ }, \ .num_threads_tx = UEC_NUM_OF_THREADS_1, \ .num_threads_rx = UEC_NUM_OF_THREADS_1, \ @@ -616,9 +616,9 @@ enum uec_num_of_threads { .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ - .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ + .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ } struct uec_inf { diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index d69a9ff477..8b6f034ea1 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -764,7 +764,7 @@ static int tsec_initialize(struct bd_info *bis, priv->phyregs_sgmii = tsec_info->miiregs_sgmii; priv->phyaddr = tsec_info->phyaddr; - priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE; + priv->tbiaddr = CFG_SYS_TBIPA_VALUE; priv->flags = tsec_info->flags; strcpy(dev->name, tsec_info->devname); @@ -832,7 +832,7 @@ int tsec_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_plat(dev); struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; - u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; + u32 tbiaddr = CFG_SYS_TBIPA_VALUE; struct tsec_data *data; ofnode parent, child; fdt_addr_t reg; diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c index af8d99cefb..09883f06be 100644 --- a/drivers/net/vsc7385.c +++ b/drivers/net/vsc7385.c @@ -39,13 +39,13 @@ int vsc7385_upload_firmware(void *firmware, unsigned int size) u8 *fw = firmware; unsigned int i; - u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050); - u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040); - u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044); - u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048); - u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070); + u32 *gloreset = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c050); + u32 *icpu_ctrl = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c040); + u32 *icpu_addr = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c044); + u32 *icpu_data = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c048); + u32 *icpu_rom_map = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c070); #ifdef DEBUG - u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060); + u32 *chipid = (u32 *) (CFG_SYS_VSC7385_BASE + 0x1c060); #endif out_be32(gloreset, 3); diff --git a/drivers/power/power_dialog.c b/drivers/power/power_dialog.c index e286dd108f..ad7aaf35a9 100644 --- a/drivers/power/power_dialog.c +++ b/drivers/power/power_dialog.c @@ -24,7 +24,7 @@ int pmic_dialog_init(unsigned char bus) p->number_of_regs = DIALOG_NUM_OF_REGS; p->interface = PMIC_I2C; - p->hw.i2c.addr = CONFIG_SYS_DIALOG_PMIC_I2C_ADDR; + p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h index 83461c024c..63371e71bf 100644 --- a/drivers/qe/uec.h +++ b/drivers/qe/uec.h @@ -605,10 +605,10 @@ enum uec_num_of_threads { #define STD_UEC_INFO(num) \ { \ .uf_info = { \ - .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ + .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ + .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ + .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ + .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ }, \ .num_threads_tx = UEC_NUM_OF_THREADS_1, \ .num_threads_rx = UEC_NUM_OF_THREADS_1, \ @@ -616,9 +616,9 @@ enum uec_num_of_threads { .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ .tx_bd_ring_len = 16, \ .rx_bd_ring_len = 16, \ - .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ + .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ + .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ + .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ } struct uec_inf { diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 9d429c832f..fcf06d1032 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -52,7 +52,7 @@ * * Some boards do not have a PHY for each ethernet port. These ports are known * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate - * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) + * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network * speed and duplex should be for the port. @@ -61,10 +61,10 @@ * #define CONFIG_FIXED_PHY 0xFFFFFFFF * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) * - * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02 - * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04 + * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CFG_SYS_UEC2_PHY_ADDR 0x02 + * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR + * #define CFG_SYS_UEC4_PHY_ADDR 0x04 * * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ * {name, speed, duplex}, diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 40ca66bdce..0e9d3d24dd 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -80,8 +80,8 @@ enum ds_type { #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) @@ -212,13 +212,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #endif /* !CONFIG_DM_RTC */ diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 486c01f9ba..2c780ab8ed 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -184,13 +184,13 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static uchar rtc_read(struct udevice *dev, uchar reg) diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index 9f2647d707..89442f9386 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -29,8 +29,8 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000) @@ -194,21 +194,21 @@ void rtc_reset (void){ */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write(uchar reg, uchar val, bool set) { if (set == true) { - val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + val |= i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } else { - val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val; - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + val = i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg) & ~val; + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } } static void rtc_write_raw (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } diff --git a/drivers/rtc/ds3231.c b/drivers/rtc/ds3231.c index 5b72e86768..bd32ed2dbf 100644 --- a/drivers/rtc/ds3231.c +++ b/drivers/rtc/ds3231.c @@ -164,13 +164,13 @@ void rtc_enable_32khz_output(void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static int ds3231_rtc_get(struct udevice *dev, struct rtc_time *tmp) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 8be532c3e3..66a0faa0ec 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -319,7 +319,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); m41t62_update_rtc_time(tm, buf); return 0; @@ -329,10 +329,10 @@ int rtc_set(struct rtc_time *tm) { u8 buf[M41T62_DATETIME_REG_SIZE]; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); + i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE); m41t62_set_rtc_buf(tm, buf); - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, + if (i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) { printf("I2C write failed in %s()\n", __func__); return -1; @@ -349,8 +349,8 @@ void rtc_reset(void) * M41T82: Make sure HT (Halt Update) bit is cleared. * This bit is 0 in M41T62 so its save to clear it always. */ - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + i2c_read(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); val &= ~M41T80_ALHOUR_HT; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); + i2c_write(CFG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1); } #endif /* CONFIG_DM_RTC */ diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c index 11928839dc..e03a87f94d 100644 --- a/drivers/rtc/max6900.c +++ b/drivers/rtc/max6900.c @@ -16,20 +16,20 @@ #include #include -#ifndef CONFIG_SYS_I2C_RTC_ADDR -#define CONFIG_SYS_I2C_RTC_ADDR 0x50 +#ifndef CFG_SYS_I2C_RTC_ADDR +#define CFG_SYS_I2C_RTC_ADDR 0x50 #endif /* ------------------------------------------------------------------------- */ static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); udelay(2500); } diff --git a/drivers/rtc/pcf8563.c b/drivers/rtc/pcf8563.c index 19faefba7c..91a412440b 100644 --- a/drivers/rtc/pcf8563.c +++ b/drivers/rtc/pcf8563.c @@ -111,12 +111,12 @@ void rtc_reset (void) static uchar rtc_read (uchar reg) { - return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); + return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); } static void rtc_write (uchar reg, uchar val) { - i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); } #else static int pcf8563_rtc_get(struct udevice *dev, struct rtc_time *tmp) diff --git a/drivers/rtc/pt7c4338.c b/drivers/rtc/pt7c4338.c index c987494b66..e0a7bd3662 100644 --- a/drivers/rtc/pt7c4338.c +++ b/drivers/rtc/pt7c4338.c @@ -53,12 +53,12 @@ /****** Helper functions ****************************************/ static u8 rtc_read(u8 reg) { - return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg); + return i2c_reg_read(CFG_SYS_I2C_RTC_ADDR, reg); } static void rtc_write(u8 reg, u8 val) { - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val); + i2c_reg_write(CFG_SYS_I2C_RTC_ADDR, reg, val); } /****************************************************************/ diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c index 97ec001aef..6b1c23ca5d 100644 --- a/drivers/rtc/rs5c372.c +++ b/drivers/rtc/rs5c372.c @@ -39,8 +39,8 @@ static unsigned int rtc_debug = DEBUG; #define rtc_debug 0 /* gcc will remove all the debug code for us */ #endif -#ifndef CONFIG_SYS_I2C_RTC_ADDR -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#ifndef CFG_SYS_I2C_RTC_ADDR +#define CFG_SYS_I2C_RTC_ADDR 0x32 #endif #define RS5C372_RAM_SIZE 0x10 @@ -63,7 +63,7 @@ rs5c372_readram(unsigned char *buf, int len) { int ret; - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); if (ret != 0) { printf("%s: failed to read\n", __FUNCTION__); return ret; @@ -103,7 +103,7 @@ rs5c372_enable(void) buf[14] = 0; /* reg. 13 */ buf[15] = 0; /* reg. 14 */ buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); if (ret != 0) { printf("%s: failed\n", __FUNCTION__); return; @@ -204,7 +204,7 @@ int rtc_set (struct rtc_time *tmp) memset(buf, 0, sizeof(buf)); /* only read register 15 */ - ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); + ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); if (ret == 0) { /* need to save register 15 */ @@ -233,7 +233,7 @@ int rtc_set (struct rtc_time *tmp) printf("WARNING: year should be between 1970 and 2069!\n"); buf[7] = bin2bcd(tmp->tm_year % 100); - ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); + ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); if (ret != 0) { printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); return -1; diff --git a/drivers/rtc/rx8010sj.c b/drivers/rtc/rx8010sj.c index d513561b82..bf93b55774 100644 --- a/drivers/rtc/rx8010sj.c +++ b/drivers/rtc/rx8010sj.c @@ -33,8 +33,8 @@ #endif /*---------------------------------------------------------------------*/ -#ifndef CONFIG_SYS_I2C_RTC_ADDR -# define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#ifndef CFG_SYS_I2C_RTC_ADDR +# define CFG_SYS_I2C_RTC_ADDR 0x32 #endif /* @@ -313,7 +313,7 @@ static int rx8010sj_rtc_reset(DEV_TYPE *dev) int rtc_get(struct rtc_time *tm) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; return rx8010sj_rtc_get(&dev, tm); @@ -322,7 +322,7 @@ int rtc_get(struct rtc_time *tm) int rtc_set(struct rtc_time *tm) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; return rx8010sj_rtc_set(&dev, tm); @@ -331,7 +331,7 @@ int rtc_set(struct rtc_time *tm) void rtc_reset(void) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; rx8010sj_rtc_reset(&dev); @@ -340,7 +340,7 @@ void rtc_reset(void) void rtc_init(void) { struct ludevice dev = { - .chip = CONFIG_SYS_I2C_RTC_ADDR, + .chip = CFG_SYS_I2C_RTC_ADDR, }; rx8010sj_rtc_init(&dev); diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c index ce23427b17..4a8d1c5903 100644 --- a/drivers/rtc/x1205.c +++ b/drivers/rtc/x1205.c @@ -77,7 +77,7 @@ static void rtc_write(int reg, u8 val) { - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); + i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); } /* @@ -89,7 +89,7 @@ int rtc_get(struct rtc_time *tm) { u8 buf[8]; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); + i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 83cda1f204..8a489a2e3f 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * Table with supported baudrates (defined in config_xyz.h) */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; +static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE; #if CONFIG_IS_ENABLED(SERIAL_PRESENT) static int serial_check_stdout(const void *blob, struct udevice **devp) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 6cdbb89841..4d54965094 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -22,7 +22,7 @@ static struct serial_device *serial_current; /* * Table with supported baudrates (defined in config_xyz.h) */ -static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; +static const unsigned long baudrate_table[] = CFG_SYS_BAUDRATE_TABLE; /** * serial_null() - Void registration routine of a serial driver @@ -459,7 +459,7 @@ void default_serial_puts(const char *s) } #if CONFIG_POST & CONFIG_SYS_POST_UART -static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE; +static const int bauds[] = CFG_SYS_BAUDRATE_TABLE; /** * uart_post_test() - Test the currently selected serial port using POST diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0ee6171108..9ebc4ed48f 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -225,7 +225,7 @@ static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); /* setup format */ - scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + scalar = ((CFG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; /* * Use following format: @@ -314,7 +314,7 @@ static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) struct davinci_spi_slave *ds = dev_get_priv(bus); debug("%s speed %u\n", __func__, max_hz); - if (max_hz > CONFIG_SYS_SPI_CLK / 2) + if (max_hz > CFG_SYS_SPI_CLK / 2) return -EINVAL; ds->freq = max_hz; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index bc5da0a1e6..2bb7390bbf 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -131,7 +131,7 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz) * follows: * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR)) */ - divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz); + divider = DIV_ROUND_UP(CFG_SYS_TCLK, hz); if (divider < 16) { /* This is the easy case, divider is less than 16 */ spr = divider; @@ -205,7 +205,7 @@ static void mvebu_spi_50mhz_ac_timing_erratum(struct udevice *bus, uint mode) data = readl(®->timing1); data &= ~KW_SPI_TMISO_SAMPLE_MASK; - if (CONFIG_SYS_TCLK == 250000000 && + if (CFG_SYS_TCLK == 250000000 && mode & SPI_CPOL && mode & SPI_CPHA) data |= KW_SPI_TMISO_SAMPLE_2; diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c index ad1781e6c0..84fbc79016 100644 --- a/drivers/sysreset/sysreset_xtfpga.c +++ b/drivers/sysreset/sysreset_xtfpga.c @@ -15,8 +15,8 @@ static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type) { switch (type) { case SYSRESET_COLD: - writel(CONFIG_SYS_FPGAREG_RESET_CODE, - CONFIG_SYS_FPGAREG_RESET); + writel(CFG_SYS_FPGAREG_RESET_CODE, + CFG_SYS_FPGAREG_RESET); break; default: return -EPROTONOSUPPORT; diff --git a/drivers/timer/arm_global_timer.c b/drivers/timer/arm_global_timer.c index 065f10bb74..2e50d9fbc5 100644 --- a/drivers/timer/arm_global_timer.c +++ b/drivers/timer/arm_global_timer.c @@ -59,7 +59,7 @@ static int arm_global_timer_probe(struct udevice *dev) return ret; uc_priv->clock_rate = ret; } else { - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; } /* init timer */ diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c index 72be297754..9c3b64ae5b 100644 --- a/drivers/timer/imx-gpt-timer.c +++ b/drivers/timer/imx-gpt-timer.c @@ -28,9 +28,9 @@ #define GPT_CLKSRC_IPG_CLK (1 << 6) #define GPT_CLKSRC_IPG_CLK_24M (5 << 6) -/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ -#ifndef CONFIG_SYS_HZ_CLOCK -#define CONFIG_SYS_HZ_CLOCK 3000000 +/* If CFG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ +#ifndef CFG_SYS_HZ_CLOCK +#define CFG_SYS_HZ_CLOCK 3000000 #endif struct imx_gpt_timer_regs { @@ -60,7 +60,7 @@ static u64 imx_gpt_timer_get_count(struct udevice *dev) static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate) { - u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + u32 prescaler = (rate / CFG_SYS_HZ_CLOCK) - 1; /* Reset the timer */ setbits_le32(®s->cr, GPT_CR_SWR); @@ -138,7 +138,7 @@ static int imx_gpt_timer_probe(struct udevice *dev) return ret; } - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; return 0; } diff --git a/drivers/timer/orion-timer.c b/drivers/timer/orion-timer.c index d0eab3ce78..d588f0cbcd 100644 --- a/drivers/timer/orion-timer.c +++ b/drivers/timer/orion-timer.c @@ -72,7 +72,7 @@ unsigned long notrace timer_early_get_rate(void) if (IS_ENABLED(CONFIG_ARCH_MVEBU)) return MVEBU_TIMER_FIXED_RATE_25MHZ; else - return CONFIG_SYS_TCLK; + return CFG_SYS_TCLK; } /** @@ -117,7 +117,7 @@ static int orion_timer_probe(struct udevice *dev) if (type == INPUT_CLOCK_25MHZ) uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ; else - uc_priv->clock_rate = CONFIG_SYS_TCLK; + uc_priv->clock_rate = CFG_SYS_TCLK; orion_timer_init(priv->base, type); return 0; diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index f07251e54c..1213a14ef1 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -97,11 +97,11 @@ static int stm32_timer_probe(struct udevice *dev) rate = clk_get_rate(&clk); /* we set timer prescaler to obtain a 1MHz timer counter frequency */ - psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + psc = (rate / CFG_SYS_HZ_CLOCK) - 1; writel(psc, ®s->psc); /* Set timer frequency to 1MHz */ - uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + uc_priv->clock_rate = CFG_SYS_HZ_CLOCK; /* Configure timer for auto-reload */ setbits_le32(®s->cr1, CR1_ARPE); diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 9acef5ee4f..3f4418198c 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1993,7 +1993,7 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) gohci.disabled = 1; gohci.sleeping = 0; gohci.irq = -1; - gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE; + gohci.regs = (struct ohci_regs *)CFG_SYS_USB_OHCI_REGS_BASE; gohci.flags = 0; gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 54d1efc8f5..b0a99c9cd5 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -221,13 +221,13 @@ static struct clk ipu_clk = { .usecount = 0, }; -#if !defined CONFIG_SYS_LDB_CLOCK -#define CONFIG_SYS_LDB_CLOCK 65000000 +#if !defined CFG_SYS_LDB_CLOCK +#define CFG_SYS_LDB_CLOCK 65000000 #endif static struct clk ldb_clk = { .name = "ldb_clk", - .rate = CONFIG_SYS_LDB_CLOCK, + .rate = CFG_SYS_LDB_CLOCK, .usecount = 0, }; diff --git a/env/Kconfig b/env/Kconfig index 24111dfaf4..4e506ae262 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -140,7 +140,7 @@ config ENV_IS_IN_FLASH type flash chips the second sector can be used: the offset for this sector is given here. - CONFIG_ENV_OFFSET is used relative to CONFIG_SYS_FLASH_BASE. + CONFIG_ENV_OFFSET is used relative to CFG_SYS_FLASH_BASE. CONFIG_ENV_ADDR: diff --git a/env/embedded.c b/env/embedded.c index 9f26e6cad9..27fb45bf8c 100644 --- a/env/embedded.c +++ b/env/embedded.c @@ -92,6 +92,6 @@ unsigned long env_size __UBOOT_ENV_SECTION__(env_size) = sizeof(env_t); /* * Add in absolutes. */ -GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)); +GEN_ABS(env_offset, (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE)); #endif /* ENV_IS_EMBEDDED */ diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 17c76bcf3d..d60f494b58 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -17,8 +17,8 @@ #endif #endif -#ifndef CONFIG_SYS_BAUDRATE_TABLE -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifndef CFG_SYS_BAUDRATE_TABLE +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif #endif /* __CONFIG_FALLBACKS_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 6dfa3dd0f0..246437a51e 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -13,7 +13,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 @@ -41,11 +41,11 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ -#define CONFIG_SYS_PLL_ODR 0x36 -#define CONFIG_SYS_PLL_FDR 0x7D +#define CFG_SYS_CLK 166666666 /* CPU Core Clock */ +#define CFG_SYS_PLL_ODR 0x36 +#define CFG_SYS_PLL_FDR 0x7D -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -53,9 +53,9 @@ * You should know what you are doing if you make changes here. */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration @@ -75,14 +75,14 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* * Configuration for environment @@ -95,15 +95,15 @@ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -117,8 +117,8 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007F0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0 #endif /* _M5208EVBE_H */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index e28662c6e5..128ef50b47 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -18,14 +18,14 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) -#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) -#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) +#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) +#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) +#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ #ifdef CONFIG_MCFFEC @@ -50,10 +50,10 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 75000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 +#define CFG_SYS_CLK 75000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2 -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /* * Low Level Configuration Settings @@ -63,9 +63,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x21 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -81,16 +81,16 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -104,15 +104,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -130,13 +130,13 @@ * CS7 - Available */ #ifdef CONFIG_NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC00000 -# define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D00 +# define CFG_SYS_CS0_BASE 0xFFC00000 +# define CFG_SYS_CS0_MASK 0x003f0001 +# define CFG_SYS_CS0_CTRL 0x00001D00 #else -# define CONFIG_SYS_CS0_BASE 0xFFE00000 -# define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D80 +# define CFG_SYS_CS0_BASE 0xFFE00000 +# define CFG_SYS_CS0_MASK 0x001f0001 +# define CFG_SYS_CS0_CTRL 0x00001D80 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index f1da278d51..0e38eeb4a3 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -18,7 +18,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ @@ -26,9 +26,9 @@ * Clock configuration: enable only one of the following options */ -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ +#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ /* * Low Level Configuration Settings @@ -36,14 +36,14 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -56,7 +56,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #if 0 /* test-only */ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ @@ -67,33 +67,33 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(2) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) /*----------------------------------------------------------------------- @@ -101,25 +101,25 @@ */ /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ +#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ /* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CS1_BASE 0xe0000000 -#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ +#define CFG_SYS_CS1_BASE 0xe0000000 +#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ +#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #endif /* M5249 */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index bd3c57d143..7e37c6d119 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* Configuration for environment @@ -20,7 +20,7 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) +# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300) # define DM9000_IO CONFIG_DM9000_BASE # define DM9000_DATA (CONFIG_DM9000_BASE + 4) # undef CONFIG_DM9000_DEBUG @@ -45,18 +45,18 @@ #define CONFIG_HOSTNAME "M5253DEMO" /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) -#define CONFIG_SYS_I2C_PINMUX_SET (0) +#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) +#define CFG_SYS_I2C_PINMUX_SET (0) -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK -#ifdef CONFIG_SYS_FAST_CLK -# define CONFIG_SYS_PLLCR 0x1243E054 -# define CONFIG_SYS_CLK 140000000 +#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ +#define CFG_SYS_FAST_CLK +#ifdef CFG_SYS_FAST_CLK +# define CFG_SYS_PLLCR 0x1243E054 +# define CFG_SYS_CLK 140000000 #else -# define CONFIG_SYS_PLLCR 0x135a4140 -# define CONFIG_SYS_CLK 70000000 +# define CFG_SYS_PLLCR 0x135a4140 +# define CFG_SYS_CLK 70000000 #endif /* @@ -65,14 +65,14 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /* * Start addresses for the final memory configuration @@ -87,10 +87,10 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) +#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #define FLASH_SST6401B 0x200 #define SST_ID_xF6401B 0x236D236D @@ -101,45 +101,45 @@ * Amd/Atmel use 0x30 for sector erase, SST use 0x50. * 0x30 is block erase in SST */ -# define CONFIG_SYS_FLASH_SIZE 0x800000 +# define CFG_SYS_FLASH_SIZE 0x800000 #else -# define CONFIG_SYS_SST_SECT 2048 -# define CONFIG_SYS_SST_SECTSZ 0x1000 +# define CFG_SYS_SST_SECT 2048 +# define CFG_SYS_SST_SECTSZ 0x1000 #endif /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \ CF_ADDRMASK(8) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ +#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ CF_CACR_DBWE) -#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK 0x007F0021 -#define CONFIG_SYS_CS0_CTRL 0x00001D80 +#define CFG_SYS_CS0_BASE 0xFF800000 +#define CFG_SYS_CS0_MASK 0x007F0021 +#define CFG_SYS_CS0_CTRL 0x00001D80 -#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK 0x00000001 -#define CONFIG_SYS_CS1_CTRL 0x00003DD8 +#define CFG_SYS_CS1_BASE 0xE0000000 +#define CFG_SYS_CS1_MASK 0x00000001 +#define CFG_SYS_CS1_CTRL 0x00003DD8 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ +#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ +#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ +#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ +#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ +#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ +#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */ #endif /* _M5253DEMO_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 7c3bc032bf..847b4c2593 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -17,7 +17,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ @@ -51,22 +51,22 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000 /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -75,35 +75,35 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /* * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -111,11 +111,11 @@ /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x00000000 -#define CONFIG_SYS_PADDR 0x0000 -#define CONFIG_SYS_PADAT 0x0000 -#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 -#define CONFIG_SYS_PBDAT 0x0000 -#define CONFIG_SYS_PDCNT 0x00000000 +#define CFG_SYS_PACNT 0x00000000 +#define CFG_SYS_PADDR 0x0000 +#define CFG_SYS_PADAT 0x0000 +#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ +#define CFG_SYS_PBDDR 0x0000 +#define CFG_SYS_PBDAT 0x0000 +#define CFG_SYS_PDCNT 0x00000000 #endif /* _M5272C3_H */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 4eb4abea72..ff9f853589 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -21,7 +21,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -34,9 +34,9 @@ /* Available command configuration */ /* I2C */ -#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) -#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) +#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) +#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) +#define CFG_SYS_I2C_PINMUX_SET (0x000F) #ifdef CONFIG_MCFFEC # define CONFIG_OVERWRITE_ETHADDR_ONCE @@ -54,7 +54,7 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 150000000 +#define CFG_SYS_CLK 150000000 /* * Low Level Configuration Settings @@ -62,13 +62,13 @@ * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -77,34 +77,34 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_FLASH_SIZE 0x200000 +#define CFG_SYS_FLASH_SIZE 0x200000 /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -112,12 +112,12 @@ /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xffe00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001 -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_CTRL 0x00001900 -#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_BASE 0x30000000 +#define CFG_SYS_CS1_CTRL 0x00001900 +#define CFG_SYS_CS1_MASK 0x00070001 #endif /* _M5275EVB_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index eda394467e..bde9e770e5 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -17,7 +17,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ @@ -49,25 +49,25 @@ "save\0" \ "" -#define CONFIG_SYS_CLK 64000000 +#define CFG_SYS_CLK 64000000 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. */ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -76,65 +76,65 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xf0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP) /*----------------------------------------------------------------------- * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CFG_SYS_CS0_BASE 0xFFE00000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x001F0001 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000 -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF #endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 159993a46b..0e9ba4c3ad 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -18,17 +18,17 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 #ifdef CONFIG_MCFFEC -# define CONFIG_SYS_TX_ETH_BUFFER 8 -# define CONFIG_SYS_FEC_BUF_USE_SRAM +# define CFG_SYS_TX_ETH_BUFFER 8 +# define CFG_SYS_FEC_BUF_USE_SRAM #endif -#define CONFIG_SYS_RTC_CNT (0x8000) -#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) +#define CFG_SYS_RTC_CNT (0x8000) +#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) /* I2C */ @@ -54,10 +54,10 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Low Level Configuration Settings @@ -67,9 +67,9 @@ /* * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration @@ -89,17 +89,17 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI # define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -113,15 +113,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -135,12 +135,12 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_CTRL 0x00001FA0 -#define CONFIG_SYS_CS1_BASE 0xC0000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001FA0 +#define CFG_SYS_CS1_BASE 0xC0000000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x00001FA0 #endif /* _M53017EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d7ece63934..8f83810f16 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -18,7 +18,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ @@ -46,12 +46,12 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -61,9 +61,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -83,22 +83,22 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif #ifdef CONFIG_CMD_NAND -# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 #endif -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -112,15 +112,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -134,18 +134,18 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0 -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780 #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif #endif /* _M5329EVB_H */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index b2fc6923e0..43c642edeb 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -20,7 +20,7 @@ * (easy to change) */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ @@ -48,12 +48,12 @@ #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) +#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000) /* * Low Level Configuration Settings @@ -63,9 +63,9 @@ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_CTRL 0x221 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -85,20 +85,20 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) /*----------------------------------------------------------------------- * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif -# define CFG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE +# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE # define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } # define NAND_ALLOW_ERASE_ALL 1 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash @@ -112,15 +112,15 @@ * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) /*----------------------------------------------------------------------- @@ -134,16 +134,16 @@ * CS4 - Available * CS5 - Available */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x007f0001 +#define CFG_SYS_CS0_CTRL 0x00001fa0 -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 +#define CFG_SYS_CS1_BASE 0x10000000 +#define CFG_SYS_CS1_MASK 0x001f0001 +#define CFG_SYS_CS1_CTRL 0x002A3780 -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK (16 << 20) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK (16 << 20) +#define CFG_SYS_CS2_CTRL 0x00001f60 #endif /* _M5373EVB_H */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 2e7140cd86..232cf9e998 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -59,21 +59,21 @@ /* Miscellaneous configurable options */ /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) -#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) +#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) +#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) /* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE +#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Environment Configuration */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index d9627e393d..85c080cf27 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -25,20 +25,20 @@ */ /* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ +#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ +#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ /* * System IO Config */ -#define CONFIG_SYS_SICRH 0x08200000 -#define CONFIG_SYS_SICRL 0x00000000 +#define CFG_SYS_SICRH 0x08200000 +#define CFG_SYS_SICRL 0x00000000 /* * Output Buffer Impedance */ -#define CONFIG_SYS_OBIR 0x30100000 +#define CFG_SYS_OBIR 0x30100000 /* * Device configurations @@ -60,9 +60,9 @@ * DDR Setup */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 +#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) +#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ @@ -70,14 +70,14 @@ * Manually set up DDR parameters */ #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | (0 << TIMING_CFG0_WRT_SHIFT) \ | (0 << TIMING_CFG0_RRT_SHIFT) \ | (0 << TIMING_CFG0_WWT_SHIFT) \ @@ -86,7 +86,7 @@ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) /* 0x00260802 */ /* DDR400 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | (7 << TIMING_CFG1_CASLAT_SHIFT) \ @@ -95,7 +95,7 @@ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | (2 << TIMING_CFG1_WRTORD_SHIFT)) /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ +#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | (5 << TIMING_CFG2_CPO_SHIFT) \ | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ @@ -104,23 +104,23 @@ | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) /* 0x02984cc8 */ -#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ +#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ +#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) /* 0x04400442 */ /* DDR400 */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 +#define CFG_SYS_DDR_MODE2 0x00000000 /* * Memory test */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ /* * The reserved memory @@ -129,14 +129,14 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ /* * NAND Flash on the Local Bus @@ -146,14 +146,14 @@ /* Vitesse 7385 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 +#define CFG_SYS_VSC7385_BASE 0xF0000000 /* * Serial Port */ #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) @@ -165,13 +165,13 @@ #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x51} } /* * Config on-board RTC */ #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* * General PCI @@ -198,7 +198,7 @@ #ifdef CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 2 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #define TSEC1_PHYIDX 0 @@ -226,7 +226,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 25b4fe0c7d..ff02c2cd84 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -28,16 +28,16 @@ * Only possible on E500 Version 2 or newer cores. */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ @@ -112,32 +112,32 @@ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ +#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST \ + {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_HWCONFIG /* enable hwconfig */ /* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ +#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull +#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull #else -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE +#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE #endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. + * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR2, need: * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 @@ -149,12 +149,12 @@ * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into * FIXME: the top 17 bits of BR2. */ /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR2, need: * 64MB mask for AM, OR2[0:7] = 1111 1100 @@ -167,10 +167,10 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* * Common settings for all Local Bus SDRAM commands. @@ -178,7 +178,7 @@ * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ +#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ | LSDMR_PRETOACT7 \ | LSDMR_ACTTORW7 \ | LSDMR_BL8 \ @@ -226,25 +226,25 @@ #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR #endif -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* * I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x69} } #endif /* @@ -326,7 +326,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ /* * Environment Configuration diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 21491b9f97..a8af0a101c 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -16,10 +16,10 @@ #include #ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x11000000) +#define CFG_SYS_MMC_U_BOOT_START (0x11000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10) #endif #ifdef CONFIG_SPIFLASH @@ -27,10 +27,10 @@ #define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) #endif #endif @@ -111,11 +111,11 @@ extern unsigned long get_sdram_size(void); #endif #define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* * Memory map @@ -136,15 +136,15 @@ extern unsigned long get_sdram_size(void); */ /* NOR Flash on IFC */ -#define CONFIG_SYS_FLASH_BASE 0xee000000 +#define CFG_SYS_FLASH_BASE 0xee000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -161,7 +161,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NOR_TWP(0x1c) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* CFI for NOR Flash */ @@ -237,85 +237,85 @@ extern unsigned long get_sdram_size(void); /* Set up IFC registers for boot location NOR/NAND */ #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffb00000 +#define CFG_SYS_CPLD_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xD0000000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #endif #endif @@ -324,11 +324,11 @@ extern unsigned long get_sdram_size(void); #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* I2C */ #define I2C_PCA9557_ADDR1 0x18 @@ -343,7 +343,7 @@ extern unsigned long get_sdram_size(void); /* RTC */ #define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* * SPI interface will not be available in case of NAND boot SPI CS0 will be @@ -393,7 +393,7 @@ extern unsigned long get_sdram_size(void); */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif @@ -410,7 +410,7 @@ extern unsigned long get_sdram_size(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c3ef216333..1e02855fef 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -39,32 +39,32 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ +#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ CONFIG_RAMBOOT_TEXT_BASE) #else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR #endif #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x52 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -74,18 +74,18 @@ */ /* Set the local bus clock 1/8 of platform clock */ -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 +#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8 /* * This board doesn't have a promjet connector. * However, it uses commone corenet board LAW and TLB. * It is necessary to use the same start address with proper offset. */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif #define CONFIG_FSL_CPLD @@ -130,28 +130,28 @@ | OR_FCM_EHTR) #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -159,13 +159,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -244,52 +244,52 @@ #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull /* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#define CFG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf4200000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_MEM_SIZE 0x00200000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 +#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f +#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 +#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0 -#define CONFIG_SYS_TBIPA_VALUE 8 +#define CFG_SYS_TBIPA_VALUE 8 #endif #ifdef CONFIG_MMC @@ -305,7 +305,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ /* * Environment Configuration diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index 417b9ae7b2..bad34d9771 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -12,7 +12,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* @@ -32,7 +32,7 @@ * U-Boot bootcode configuration */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 87b68227a0..9a9663b34b 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -12,7 +12,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #define CFG_SYS_NS16550_COM1 KW_UART0_BASE /* @@ -37,7 +37,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ /* size in bytes reserved for initial data */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b567b63980..b5fb0a9b52 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -29,18 +29,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -93,7 +93,7 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -101,20 +101,20 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) #define SPD_EEPROM_ADDRESS 0x51 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -125,15 +125,15 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE 0xe8000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -160,30 +160,30 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #ifdef CONFIG_TARGET_T1024RDB /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 #endif /* NAND Flash on IFC */ @@ -235,72 +235,72 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -315,7 +315,7 @@ */ #define RTC #define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* * eSPI - Enhanced SPI @@ -363,36 +363,37 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull #else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE #endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull #else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE #endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 + #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -421,7 +422,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 37dfe32e21..bee4b704a2 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -36,18 +36,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x30000000) +#define CFG_SYS_MMC_U_BOOT_START (0x30000000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif @@ -63,7 +63,7 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif @@ -71,24 +71,24 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 /* - * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence - * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address - * (CONFIG_SYS_INIT_L3_VADDR) will be different. + * For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence + * Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address + * (CFG_SYS_INIT_L3_VADDR) will be different. */ -#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x51 @@ -97,11 +97,11 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #define CFG_SYS_NOR_CSPR_EXT (0xf) -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -128,7 +128,7 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ #define CPLD_LBMAP_MASK 0x3F @@ -157,25 +157,25 @@ #define CPLD_INT_MASK_TDMR2 0x01 #endif -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -213,55 +213,55 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -269,13 +269,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR 0x70 @@ -289,7 +289,7 @@ */ #define RTC #define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /*DVI encoder*/ #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 @@ -344,58 +344,58 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 +#define CFG_SYS_SGMII1_PHY_ADDR 0x03 #elif defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x01 #elif defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 -#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 -#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 +#define CFG_SYS_SGMII1_PHY_ADDR 0x02 +#define CFG_SYS_SGMII2_PHY_ADDR 0x03 +#define CFG_SYS_SGMII3_PHY_ADDR 0x01 #endif #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 +#define CFG_SYS_RGMII1_PHY_ADDR 0x04 +#define CFG_SYS_RGMII2_PHY_ADDR 0x05 #else -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 +#define CFG_SYS_RGMII1_PHY_ADDR 0x01 +#define CFG_SYS_RGMII2_PHY_ADDR 0x02 #endif /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) #define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 #else -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c +#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 +#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c #endif #endif #endif @@ -409,7 +409,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Dynamic MTD Partition support with mtdparts diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 798822e503..be8c30db26 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -31,18 +31,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -69,18 +69,18 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -90,16 +90,16 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -121,8 +121,8 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} #define QIXIS_BASE 0xffdf0000 #define QIXIS_LBMAP_SWITCH 6 @@ -141,23 +141,23 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -195,81 +195,81 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* * I2C @@ -360,28 +360,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -418,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ea366b671c..795873f423 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -31,18 +31,18 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) #endif #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST (0x00200000) +#define CFG_SYS_MMC_U_BOOT_START (0x00200000) +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif /* CONFIG_RAMBOOT_PBL */ @@ -69,18 +69,18 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -90,10 +90,10 @@ /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -116,29 +116,29 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS } /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR2_EXT (0xf) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 +#define CFG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR2 0x0 /* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 +#define CFG_SYS_CS2_FTIM3 0x0 /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -176,65 +176,65 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* * I2C @@ -319,28 +319,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 18 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 18 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN @@ -384,7 +384,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index cc86c9d4a5..ffd5645493 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -24,10 +24,10 @@ #ifdef CONFIG_SDCARD #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST 0x00200000 +#define CFG_SYS_MMC_U_BOOT_START 0x00200000 +#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10) #endif #endif @@ -51,39 +51,39 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * IFC Definitions */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe0000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -91,13 +91,13 @@ */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CFG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CFG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600) +#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500) +#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600) /* I2C */ @@ -135,7 +135,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration @@ -159,14 +159,14 @@ /* * IFC Definitions */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR0_CSPR_EXT (0xf) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR_EXT (0xf) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -188,8 +188,8 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC */ #define CFG_SYS_NAND_BASE 0xff800000 @@ -227,71 +227,71 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 /* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ +#define CFG_SYS_CPLD_BASE 0xffdf0000 +#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) +#define CFG_SYS_CSPR3_EXT (0xf) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 0x0 /* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 /* I2C */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ @@ -318,28 +318,28 @@ /* Qman/Bman */ #ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 50 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 50 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 25d9c96e16..69b8b048ce 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -205,8 +205,8 @@ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) */ #if defined(CONFIG_NOR) -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE 0x01000000 #endif /* NOR support */ #endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index a9a4c8d17f..c57a0ddc21 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -89,7 +89,7 @@ /* on one chip */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #endif #endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4ff8528cf8..bcdff2e98a 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -9,7 +9,7 @@ #define __CONFIG_AM43XX_EVM_H #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include @@ -25,7 +25,7 @@ /* SPL defines. */ /* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 /* * When building U-Boot such that there is no previous loader diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 84555f3b13..340a8ce6dc 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -53,9 +53,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index eba78d3894..ee0be972d2 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -10,7 +10,7 @@ #define CONFIG_HOSTNAME "AMCORE" -#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0 #define CONFIG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ @@ -24,21 +24,21 @@ "erase 0xfff00000 0xffffffff; " \ "cp.b 0x20000 0xfff00000 ${filesize}\0" -#define CONFIG_SYS_CLK 45000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) +#define CFG_SYS_CLK 45000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2) /* Register Base Addrs */ -#define CONFIG_SYS_MBAR 0x10000000 +#define CFG_SYS_MBAR 0x10000000 /* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 /* size of internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 +#define CFG_SYS_FLASH_BASE 0xffc00000 /* amcore design has flash data bytes wired swapped */ -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ #define LDS_BOARD_TEXT \ @@ -46,7 +46,7 @@ env/embedded.o(.text*); /* memory map space for linux boot data */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Cache Configuration @@ -56,25 +56,25 @@ * sdram - single region - no masks */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ CF_ACR_EN) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ CF_CACR_EC) /* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) +#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16) /* 4MB, AA=0,V=1 C/I BIT for errata */ -#define CONFIG_SYS_CS0_MASK 0x003f0001 +#define CFG_SYS_CS0_MASK 0x003f0001 /* WS=10, AA=1, PS=16bit (10) */ -#define CONFIG_SYS_CS0_CTRL 0x1980 +#define CFG_SYS_CS0_CTRL 0x1980 /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ -#define CONFIG_SYS_CS1_BASE 0x3000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x0100 +#define CFG_SYS_CS1_BASE 0x3000 +#define CFG_SYS_CS1_MASK 0x00070001 +#define CFG_SYS_CS1_CTRL 0x0100 #endif /* __AMCORE_CONFIG_H */ diff --git a/include/configs/ap121.h b/include/configs/ap121.h index 63c7dfc1fe..9c6f76383d 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Miscellaneous configurable options */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 865aad2a3f..034cd7a7cd 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* * Serial Port diff --git a/include/configs/ap152.h b/include/configs/ap152.h index 0464a69e82..c56b35150a 100644 --- a/include/configs/ap152.h +++ b/include/configs/ap152.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x2000 /* * Serial Port diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 356d4c35ee..c9375b4d16 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -107,7 +107,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/arbel.h b/include/configs/arbel.h index ed32e772f8..60758b0ca0 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -7,9 +7,9 @@ #define __CONFIG_ARBEL_H #define CFG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_BOOTMAPSZ (20 << 20) -#define CONFIG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_BOOTMAPSZ (20 << 20) +#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ #define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 90cf4705f4..c1eec5d06c 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -20,7 +20,7 @@ #endif /* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 28341000 +#define CFG_SYS_LDB_CLOCK 28341000 #include "mx6_common.h" @@ -407,8 +407,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index cbd0d6cea0..bb1bd50838 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -17,11 +17,11 @@ #define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE #ifdef CONFIG_PRE_CON_BUF_SZ -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ) #else -#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) -#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE) +#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE) #endif /* diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index b142ea3c33..f5922fc416 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -55,19 +55,19 @@ * interface etc. */ -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) +#define CFG_SYS_CLK 80000000 +#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3) #define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ /* * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected * in u-boot command interface */ -#define CONFIG_SYS_UART_PORT (2) -#define CONFIG_SYS_UART2_ALT3_GPIO +#define CFG_SYS_UART_PORT (2) +#define CFG_SYS_UART2_ALT3_GPIO /* * Watchdog configuration; Watchdog is disabled for running from RAM @@ -125,7 +125,7 @@ * it needs non-blocking CFI routines. */ -#define CONFIG_SYS_FPGA_WAIT 1000 +#define CFG_SYS_FPGA_WAIT 1000 /* End of user parameters to be customized */ @@ -139,19 +139,19 @@ /* Base register address */ -#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ /* System Conf. Reg. & System Protection Reg. */ -#define CONFIG_SYS_SCR 0x0003; -#define CONFIG_SYS_SPR 0xffff; +#define CFG_SYS_SCR 0x0003; +#define CFG_SYS_SPR 0xffff; /* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 /* * Start addresses for the final memory configuration @@ -170,23 +170,23 @@ * CS4 - unused * CS5 - unused */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00ff0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fc0 +#define CFG_SYS_CS0_BASE 0 +#define CFG_SYS_CS0_MASK 0x00ff0001 +#define CFG_SYS_CS0_CTRL 0x00001fc0 -#define CONFIG_SYS_CS1_BASE 0x01000000 -#define CONFIG_SYS_CS1_MASK 0x00ff0001 -#define CONFIG_SYS_CS1_CTRL 0x00001fc0 +#define CFG_SYS_CS1_BASE 0x01000000 +#define CFG_SYS_CS1_MASK 0x00ff0001 +#define CFG_SYS_CS1_CTRL 0x00001fc0 -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK 0x00ff0001 -#define CONFIG_SYS_CS2_CTRL 0x0000fec0 +#define CFG_SYS_CS2_BASE 0x20000000 +#define CFG_SYS_CS2_MASK 0x00ff0001 +#define CFG_SYS_CS2_CTRL 0x0000fec0 -#define CONFIG_SYS_CS3_BASE 0x21000000 -#define CONFIG_SYS_CS3_MASK 0x00ff0001 -#define CONFIG_SYS_CS3_CTRL 0x0000fec0 +#define CFG_SYS_CS3_BASE 0x21000000 +#define CFG_SYS_CS3_MASK 0x00ff0001 +#define CFG_SYS_CS3_CTRL 0x0000fec0 -#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_BASE 0x00000000 /* Reserve 256 kB for Monitor */ @@ -195,12 +195,12 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ (CFG_SYS_SDRAM_SIZE << 20)) /* FLASH organization */ -#define CONFIG_SYS_FLASH_SIZE 0x2000000 +#define CFG_SYS_FLASH_SIZE 0x2000000 #define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ @@ -208,15 +208,15 @@ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ CF_CACR_DCM_P) #endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 4631acfd66..4aa876a9f7 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -12,7 +12,7 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 0d76f419db..b9cc7ba974 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -24,8 +24,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* * SDRAM: 1 bank, min 32, max 128 MB @@ -34,11 +34,11 @@ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) #ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM #else -# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 #endif /* NAND flash */ @@ -51,6 +51,6 @@ #endif /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index dcc1cca479..56247e390b 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -11,16 +11,16 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #include /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -42,6 +42,6 @@ #define CONFIG_DM9000_NO_SROM /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ #endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index aefa9fc60c..afdb74785f 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -19,20 +19,20 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NOR flash, if populated */ #ifdef CONFIG_SYS_USE_NORFLASH #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* Address and size of Primary Environment Sector */ @@ -50,9 +50,9 @@ #define MASTER_PLL_OUT 3 /* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | \ AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ AT91_PMC_PLLXR_PLLCOUNT(63) | \ @@ -60,31 +60,31 @@ AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -98,10 +98,10 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -110,35 +110,35 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_MR_URSTEN | \ AT91_RSTC_MR_ERSTL(15)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -160,6 +160,6 @@ #endif /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 08cfee1a4e..2ceb8067d5 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x70000000 @@ -41,9 +41,9 @@ 56, 57, 58, 59, 60, 61, 62, 63, } #endif -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 76f87c1619..0f9e2cfb58 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -10,8 +10,8 @@ #define __AT91SAM9N12_CONFIG_H_ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ /* Misc CPU related */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -35,9 +35,9 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20953f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20953f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e1111b6dd3..cad00f647b 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -13,15 +13,15 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index eb1d1ad60d..509c458e5f 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -9,8 +9,8 @@ #define __CONFIG_H__ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* general purpose I/O */ @@ -38,9 +38,9 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 83ac87b10a..03e04e6e68 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -39,15 +39,15 @@ /* support JEDEC */ #define PHYS_FLASH_1 0x88000000 /* BANK 0 */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } /* max number of memory banks */ /* * There are 4 banks supported for this Controller, * but we have only 1 bank connected to flash on board */ -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} +#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000} /* max number of sectors on one chip */ #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) @@ -63,7 +63,7 @@ */ /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Increase max gunzip size */ /* Support autoboot from RAM (kernel image is loaded via debug port) */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 6d82712186..04dc50b1cb 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -19,8 +19,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_512M /* diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h index cba109b74a..43edc91b10 100644 --- a/include/configs/bcm7260.h +++ b/include/configs/bcm7260.h @@ -12,7 +12,7 @@ #define CFG_SYS_NS16550_COM1 0xf040c000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 +#define CFG_SYS_INIT_RAM_ADDR 0x10200000 #include "bcmstb.h" diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h index a07f1b7ad0..114337294e 100644 --- a/include/configs/bcm7445.h +++ b/include/configs/bcm7445.h @@ -12,7 +12,7 @@ #define CFG_SYS_NS16550_COM1 0xf040ab00 -#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80200000 #include "bcmstb.h" diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h index f1b68ba673..c61acf6b86 100644 --- a/include/configs/bcm963138.h +++ b/include/configs/bcm963138.h @@ -7,6 +7,6 @@ #define __BCM963138_H #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_HZ_CLOCK 500000000 +#define CFG_SYS_HZ_CLOCK 500000000 #endif diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 9769a71409..57360b60ca 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -82,7 +82,7 @@ extern phys_addr_t prior_stage_fdt_address; * initramfs images, in which case this limitation is eliminated. */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CFG_SYS_INIT_RAM_SIZE 0x100000 /* * CONFIG_SYS_LOAD_ADDR - 1 MiB. @@ -102,7 +102,7 @@ extern phys_addr_t prior_stage_fdt_address; /* * Serial console configuration. */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index a075a5b2f3..0842a4a8f5 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -200,7 +200,7 @@ #define PHYS_SDRAM_SIZE (SZ_512M) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 0b1fc91d9e..cb28ae28dd 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -26,10 +26,10 @@ #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } +#define CFG_SYS_FLASH_BASE 0x00000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) } #endif /* Board Clock */ diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h index e40f110cac..0d254cd7f9 100644 --- a/include/configs/bmips_bcm3380.h +++ b/include/configs/bmips_bcm3380.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 508317f231..7865b9c17e 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index c5bda16d2b..93426d2661 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 32397c26e8..e992fe6a56 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h index 18c99727a0..224b697774 100644 --- a/include/configs/bmips_bcm6338.h +++ b/include/configs/bmips_bcm6338.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000 #endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index f8d7148d49..3211d23049 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 +#define CFG_SYS_FLASH_BASE 0xbfc00000 #endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index d564a32ee5..7e2449ca24 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xbe000000 +#define CFG_SYS_FLASH_BASE 0xbe000000 #endif /* __CONFIG_BMIPS_BCM6358_H */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h index f982a4363d..443ee47010 100644 --- a/include/configs/bmips_bcm6362.h +++ b/include/configs/bmips_bcm6362.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index 11d623c28b..c550f97b93 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,9 +14,9 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif -#define CONFIG_SYS_FLASH_BASE 0xb8000000 +#define CFG_SYS_FLASH_BASE 0xb8000000 #endif /* __CONFIG_BMIPS_BCM6368_H */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h index 30965c85bf..f212914072 100644 --- a/include/configs/bmips_bcm6838.h +++ b/include/configs/bmips_bcm6838.h @@ -14,7 +14,7 @@ /* U-Boot */ #if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K +#define CFG_SYS_INIT_SP_OFFSET SZ_8K #endif #endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 7e358a6314..3cdd0e47ea 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -9,7 +9,7 @@ #include /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } #endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h index 0033a7fb02..14ce8a4c0f 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -27,7 +27,7 @@ # define CFG_SYS_SDRAM_BASE 0x80000000 #endif -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* * Console diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 78b2000aa2..d35c7c4a59 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -13,7 +13,7 @@ /* -- i.mx6 specifica -- */ #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */ #define CONFIG_MXC_GPT_HCLK @@ -77,8 +77,8 @@ BUR_COMMON_ENV \ /* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Ethernet */ #define CONFIG_FEC_FIXED_SPEED _1000BASET diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index f1734aaca7..3e0b425078 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -22,7 +22,7 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6f2b8245b9..6f3396bad4 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -19,7 +19,7 @@ /* Flat Device Tree Definitions */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/ci20.h b/include/configs/ci20.h index f268dfd094..3329c24fa6 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -12,7 +12,7 @@ /* Memory configuration */ #define CFG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* NS16550-ish UARTs */ #define CFG_SYS_NS16550_CLK 48000000 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index eb899c4557..b1f9470d9c 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -23,8 +23,8 @@ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } +#define CFG_SYS_I2C_PCA953X_ADDR 0x20 +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } #undef CONFIG_EXTRA_ENV_SETTINGS @@ -83,8 +83,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* SPI Flash support */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 47c4aacc43..d5c0395797 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -22,8 +22,8 @@ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR #define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Serial console */ #define CONFIG_MXC_UART_BASE UART4_BASE @@ -139,7 +139,7 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Boot */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* misc */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8f058213e9..8ad1cfb5de 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -9,7 +9,7 @@ #define __CONFIG_CM_T43_H #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include @@ -32,7 +32,7 @@ #define CONFIG_POWER_TPS65218 /* Enabling L2 Cache */ -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 /* * Since SPL did pll and ddr initialization for us, diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 65b9074cd9..01828ea201 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -29,18 +29,18 @@ * --- */ -#define CONFIG_SYS_CLK 66000000 +#define CFG_SYS_CLK 66000000 #define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ /* --- * Define baudrate for UART1 (console output, tftp, ...) * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command + * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command * interface * --- */ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) /* --- * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change @@ -133,21 +133,21 @@ enter a valid image address in flash */ * --- */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ +#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ /* --- * System Conf. Reg. & System Protection Reg. * --- */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff +#define CFG_SYS_SCR 0x0003 +#define CFG_SYS_SPR 0xffff /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -168,28 +168,28 @@ enter a valid image address in flash */ *----------------------------------------------------------------------- */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 +#define CFG_SYS_FLASH_BASE 0xffe00000 /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ CF_CACR_DISD | CF_CACR_INVI | \ CF_CACR_CEIB | CF_CACR_DCM | \ CF_CACR_EUSP) @@ -209,15 +209,15 @@ enter a valid image address in flash */ /*----------------------------------------------------------------------- * Port configuration (GPIO) */ -#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external +#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external GPIO*/ -#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs +#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs (1^=output, 0^=input) */ -#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ -#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART +#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ +#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ -#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ -#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ +#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ +#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */ +#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */ #endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index ca8445a3d0..12dc946fc7 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -117,8 +117,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 14278e9ca4..c6a79debd6 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -101,7 +101,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index c08095561d..32a79b0255 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -161,8 +161,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 1128307139..fa778ec9e2 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -86,8 +86,8 @@ #define PHYS_SDRAM_SIZE (256 * SZ_1M) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Host Support */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index c7a3e47437..8a61086ecc 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -24,8 +24,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* serial console */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU @@ -63,10 +63,10 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index e2e1cfedbd..578277fc75 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -17,13 +17,13 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) +#define CFG_SYS_DV_NOR_BOOT_CFG (0x11) #endif /* @@ -36,7 +36,7 @@ /* memtest will be run on 16MB */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -47,17 +47,17 @@ * PLL configuration */ -#define CONFIG_SYS_DA850_PLL0_PLLM 24 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 24 +#define CFG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -67,9 +67,9 @@ (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0 -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -79,7 +79,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (0 << DV_DDR_SDTMR1_WTR_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -88,20 +88,20 @@ (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (0 << DV_DDR_SDTMR2_CKE_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000494 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) /* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment @@ -125,7 +125,7 @@ #endif #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE +#define CFG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ #endif diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b16f3d48e3..4b31bbf4e1 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -43,8 +43,8 @@ #define PHYS_SDRAM_SIZE SZ_512M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index c473f3d86e..66aa6d5c3c 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -29,8 +29,8 @@ /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE -#define CONFIG_SYS_FLASH_SIZE SZ_4M +#define CFG_SYS_FLASH_BASE EMC_CS0_BASE +#define CFG_SYS_FLASH_SIZE SZ_4M /* * NAND controller diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index ddc436d501..f9b3d19480 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -73,8 +73,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment */ diff --git a/include/configs/display5.h b/include/configs/display5.h index 0a7428b02c..7636d2869a 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -30,9 +30,9 @@ */ /* Below values are "dummy" - only to avoid build break */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x150000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x10000 #define CONFIG_MXC_UART_BASE UART5_BASE @@ -285,8 +285,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* ENV config */ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index bb335a0a47..8217712e39 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -63,9 +63,9 @@ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) * 0x9E0000 - 0x2000000 : USERLAND */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CFG_SYS_SPI_ARGS_OFFS 0x140000 +#define CFG_SYS_SPI_ARGS_SIZE 0x80000 /* SPI SPL */ @@ -87,8 +87,8 @@ /* Parallel NOR Support */ #if defined(CONFIG_NOR) /* NOR: device related configs */ -#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ +#define CFG_SYS_FLASH_BASE (0x08000000) /* Reduce SPL size by removing unlikey targets */ #endif /* NOR support */ diff --git a/include/configs/draak.h b/include/configs/draak.h index 8bfba78dc8..8140bc469c 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __DRAAK_H */ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index 677a485623..bd88c42a3b 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 80de73d15d..426155dbdb 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -12,7 +12,7 @@ * High Level Configuration Options (easy to change) * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_UART_PORT (0) +#define CFG_SYS_UART_PORT (0) #undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ @@ -27,18 +27,18 @@ * Environment is in the second sector of the first 256k of flash * *----------------------------------------------------------------------*/ -/*#define CONFIG_SYS_DRAM_TEST 1 */ -#undef CONFIG_SYS_DRAM_TEST +/*#define CFG_SYS_DRAM_TEST 1 */ +#undef CFG_SYS_DRAM_TEST /*----------------------------------------------------------------------* * Clock and PLL Configuration * *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ +#define CFG_SYS_CLK 80000000 /* 8MHz * 8 */ /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ +#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ +#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ /*----------------------------------------------------------------------* * Network * @@ -54,14 +54,14 @@ * You should know what you are doing if you make changes here. *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBAR 0x40000000 +#define CFG_SYS_MBAR 0x40000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) *-----------------------------------------------------------------------*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR 0x20000000 +#define CFG_SYS_INIT_RAM_SIZE 0x10000 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration @@ -79,34 +79,34 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization ?? */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 +#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE +#define CFG_SYS_INT_FLASH_BASE 0xF0000000 +#define CFG_SYS_INT_FLASH_ENABLE 0x21 -#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 +#define CFG_SYS_FLASH_SIZE 16*1024*1024 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /*----------------------------------------------------------------------- * Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) +#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ CF_CACR_CEIB | CF_CACR_DBWE | \ CF_CACR_EUSP) @@ -114,36 +114,36 @@ * Memory bank definitions */ -#define CONFIG_SYS_CS0_BASE 0xFF000000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 +#define CFG_SYS_CS0_BASE 0xFF000000 +#define CFG_SYS_CS0_CTRL 0x00001980 +#define CFG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS2_BASE 0xE0000000 -#define CONFIG_SYS_CS2_CTRL 0x00001980 -#define CONFIG_SYS_CS2_MASK 0x000F0001 +#define CFG_SYS_CS2_BASE 0xE0000000 +#define CFG_SYS_CS2_CTRL 0x00001980 +#define CFG_SYS_CS2_MASK 0x000F0001 -#define CONFIG_SYS_CS3_BASE 0xE0100000 -#define CONFIG_SYS_CS3_CTRL 0x00001980 -#define CONFIG_SYS_CS3_MASK 0x000F0001 +#define CFG_SYS_CS3_BASE 0xE0100000 +#define CFG_SYS_CS3_CTRL 0x00001980 +#define CFG_SYS_CS3_MASK 0x000F0001 /*----------------------------------------------------------------------- * Port configuration */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 +#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_SYS_PADDR 0x0000000 +#define CFG_SYS_PADAT 0x0000000 -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 +#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_SYS_PBDDR 0x0000000 +#define CFG_SYS_PBDAT 0x0000000 -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PASPAR 0x0F0F -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF +#define CFG_SYS_PASPAR 0x0F0F +#define CFG_SYS_PEHLPAR 0xC0 +#define CFG_SYS_PUAPAR 0x0F +#define CFG_SYS_DDRUA 0x05 +#define CFG_SYS_PJPAR 0xFF /*----------------------------------------------------------------------- * I2C diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 597efd6745..d1882a9646 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -16,7 +16,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __EBISU_H */ diff --git a/include/configs/edison.h b/include/configs/edison.h index b05141ad64..455a889b64 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -10,6 +10,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024) #endif diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index d24bc56f34..141f9913e6 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -51,8 +51,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index e39bb94314..29b7748e78 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -28,8 +28,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 6cae663cb8..6647148c96 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -16,7 +16,7 @@ /* NAND specific changes for etamin due to different page size */ #undef CFG_SYS_NAND_ECCPOS -#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ +#define CFG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 97a8ffb4f6..52eb0be676 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -18,19 +18,19 @@ /* CPU information */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ /* 32kB internal SRAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10) +#define CFG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CFG_SYS_INIT_RAM_SIZE (32 << 10) /* 128MB SDRAM in 1 bank */ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE (128 << 20) /* 512kB on-chip NOR flash */ -# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ /* bootstrap + u-boot + env + linux in dataflash on CS0 */ @@ -53,16 +53,16 @@ /* MMC */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 +#define CFG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 #endif /* RTC */ #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #endif /* I2C */ -#define CONFIG_SYS_MAX_I2C_BUS 1 +#define CFG_SYS_MAX_I2C_BUS 1 #define I2C_SOFT_DECLARATIONS diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index cd6cb062ec..bec1660cf4 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -11,7 +11,7 @@ #include -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index ecd05fe15c..c9c988b937 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -8,7 +8,7 @@ #include -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ #define STR_HELPER(s) #s diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index a94f5a15f0..c9e0c13172 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -15,7 +15,7 @@ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" -#define CONFIG_SYS_SPI_BASE 0x12D30000 +#define CFG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) #define CONFIG_SPI_BOOTING diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index 68c36dc2fd..8672b9e952 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -18,7 +18,7 @@ #define CPU_RELEASE_ADDR secondary_boot_addr -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600} #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index f5353ec79a..89e531649a 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -14,8 +14,8 @@ #endif /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -32,10 +32,10 @@ /* SPL */ -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #define CFG_SYS_NAND_U_BOOT_SIZE 0xa0000 #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h index a755714440..0ba4efe67a 100644 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ b/include/configs/gardena-smart-gateway-mt7688.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -25,7 +25,7 @@ #endif /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* RAM */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 6cdfe8c4c3..36dcee87c5 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -14,7 +14,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ /* TODO: Check: Can this be unified with CFG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE CFG_SYS_SDRAM_BASE /* * Memory test @@ -28,16 +28,16 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ +#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} /* @@ -49,7 +49,7 @@ * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Environment Configuration diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 85ceaf8ccb..97fe76cfa8 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -38,8 +38,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Command definition */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 1dba2e92fb..cbaf03c2a2 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -92,11 +92,11 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index fe00272a1b..b855bbc25f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -54,8 +54,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* * MTD Command for mtdparts diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 0d281a3379..4aef0b4abd 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) +#define CFG_SYS_BOOTMAPSZ (16 << 20) #define CONFIG_PL011_CLOCK 150000000 diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 775f166f1d..c5ef2f99b0 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -26,7 +26,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xf6801000 diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index 914c3ad9ef..fad1f98048 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -18,7 +18,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0xe82b1000 diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index fcb2dec54e..59ea896007 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -21,8 +21,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_1G /* diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index 0ae935208c..fbfcded471 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -20,8 +20,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_1G /* diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 594aa4f75e..b0abd54882 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -80,7 +80,7 @@ /* CS2 Base address */ #define PHYS_FLASH_1 0xc0000000 /* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* Address and size of Redundant Environment Sector */ /* diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index d4e2583ee8..1f30798550 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -110,8 +110,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* UART */ #ifdef CONFIG_MXC_UART diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 1b08c5e9a7..4e23f1a2dc 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -106,8 +106,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index a074df5829..402f83c18e 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -56,7 +56,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 855af29ec9..99da081cda 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -86,8 +86,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* SPL */ #ifdef CONFIG_SPL diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 0a688afe6c..2d9d3c34b0 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -64,8 +64,8 @@ #define PHYS_SDRAM_SIZE SZ_128M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index e5118f1158..76771fd66c 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -70,8 +70,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index e62f9c5462..c228cf7f37 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -123,8 +123,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 143da00110..03325e6c3a 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -71,8 +71,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index c7669305f5..80321cf2d8 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -18,8 +18,8 @@ #endif /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 9937071874..8a694c88a5 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -15,10 +15,10 @@ #define UBOOT_ITB_OFFSET_FSPI \ (UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE) #ifdef CONFIG_FSPI_CONF_HEADER -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI) #else -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #endif @@ -53,8 +53,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index cd47d842ff..41ab930779 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -38,8 +38,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 58e165c35a..28ce834769 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -29,8 +29,8 @@ "splblk=0x42\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index f532c1052f..85fd5e2371 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Initial environment variables */ @@ -75,8 +75,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index 415248eadf..204fc4b316 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define MEM_LAYOUT_ENV_SETTINGS \ @@ -23,8 +23,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 8857bc7c59..024b86c7f1 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define BOOT_TARGET_DEVICES(func) \ @@ -45,8 +45,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 628bb5813f..4633843d1b 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #define BOOT_TARGET_DEVICES(func) \ @@ -43,8 +43,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a169be35a4..a585cbf87e 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Enable Distro Boot */ @@ -23,8 +23,8 @@ "splblk=0x40\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 62bcef5eec..5443022b04 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -11,8 +11,8 @@ #include /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index d394762e3b..738677ff37 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -50,8 +50,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 3e995c9721..d67bad8971 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ @@ -52,8 +52,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 2GB DDR */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 1943a24b79..58f7dc6518 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,7 +12,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* GUIDs for capsule updatable firmware images */ #define IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID \ @@ -131,8 +131,8 @@ "fi;\0" /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 /* Totally 6GB or 4G DDR */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 7d360583c4..e79aa57075 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Enable Distro Boot */ @@ -23,8 +23,8 @@ "splblk=0x40\0" \ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 271376cb9f..4df98e3f37 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -46,8 +46,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 672a9fa7a3..aa29e7884f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -52,8 +52,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index dd354b0265..3b4cd65622 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -84,8 +84,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index fe27ac36a3..2e2e5ed43c 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 592df2795b..d313bdc2a4 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD #define CONFIG_MALLOC_F_ADDR 0x22040000 @@ -50,8 +50,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 077a4d843d..895c50f602 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -124,8 +124,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 #define CFG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM 0x80000000 diff --git a/include/configs/imxrt1020-evk.h b/include/configs/imxrt1020-evk.h index a2c004880a..e180387c68 100644 --- a/include/configs/imxrt1020-evk.h +++ b/include/configs/imxrt1020-evk.h @@ -22,6 +22,6 @@ * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD #endif /* __IMXRT1020_EVK_H */ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index d1a7dab37c..84228676c7 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -29,6 +29,6 @@ * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_UBOOT_START 0x800023FD +#define CFG_SYS_UBOOT_START 0x800023FD #endif /* __IMXRT1050_EVK_H */ diff --git a/include/configs/imxrt1170-evk.h b/include/configs/imxrt1170-evk.h index 2459fe24e2..f83429082a 100644 --- a/include/configs/imxrt1170-evk.h +++ b/include/configs/imxrt1170-evk.h @@ -23,7 +23,7 @@ #define DMAMEM_BASE (PHYS_SDRAM + PHYS_SDRAM_SIZE - \ DMAMEM_SZ_ALL) /* For SPL */ -#define CONFIG_SYS_UBOOT_START 0x202403FD +#define CFG_SYS_UBOOT_START 0x202403FD /* For SPL ends */ #endif /* __IMXRT1170_EVK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 8d0458d1d6..7a55c6aeef 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -6,7 +6,7 @@ * Common ARM Integrator configuration settings */ -#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ +#define CFG_SYS_TIMERBASE 0x13000100 /* Timer1 */ /* * The ARM boot monitor initializes the board. @@ -41,6 +41,6 @@ * - SIB block * - U-Boot environment */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CFG_SYS_FLASH_BASE 0x24000000 /* Timeout values in ticks */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index c8457d9716..6bee098d6a 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -17,10 +17,10 @@ #include "integrator-common.h" /* Integrator/AP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CFG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ /* Flash settings */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ +#define CFG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ /*----------------------------------------------------------------------- * PCI definitions diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index bf09510d02..25bb41ebc4 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -17,7 +17,7 @@ #include "integrator-common.h" /* Integrator CP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ #define CONFIG_SERVERIP 192.168.1.100 #define CONFIG_IPADDR 192.168.1.104 diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 2a0b0c7163..e66f994a37 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -18,14 +18,14 @@ /* DDR Configuration */ #define CFG_SYS_SDRAM_BASE1 0x880000000 /* FLASH Configuration */ -#define CONFIG_SYS_FLASH_BASE 0x000000000 +#define CFG_SYS_FLASH_BASE 0x000000000 /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif /* HyperFlash related configuration */ diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index e690ef9590..ab204c62b7 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -21,10 +21,10 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_UBOOT_BASE 0x50280000 +#define CFG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else -#define CONFIG_SYS_UBOOT_BASE 0x50080000 +#define CFG_SYS_UBOOT_BASE 0x50080000 #endif /* U-Boot general configuration */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 35cf27a2eb..cc5ec219b8 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -13,7 +13,7 @@ * Miscellaneous configurable options */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index 888bb2981f..f64c0eee1b 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -1,34 +1,34 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS +#define CFG_SYS_SICRL SICRL_IRQ_CKS -#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ DDRCDR_NZ_MAXZ | \ DDRCDR_M_ODR) -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CFG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ODT_WR_CFG | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860242 +#define CFG_SYS_DDR_MODE2 0x8080c000 -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ @@ -37,7 +37,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -46,7 +46,7 @@ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ +#define CFG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ @@ -54,7 +54,7 @@ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 128 diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index fb43fb81bc..5c9f912383 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -1,6 +1,6 @@ /* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 +#define CFG_SYS_KMBEC_FPGA_BASE 0xE8000000 +#define CFG_SYS_KMBEC_FPGA_SIZE 64 /* * High Level Configuration Options @@ -9,34 +9,34 @@ /* * System IO Setup */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) +#define CFG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) /** * DDR RAM settings */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ +#define CFG_SYS_DDR_SDRAM_CFG (\ SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_SREN | \ SDRAM_CFG_HSE) -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CFG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (\ +#define CFG_SYS_DDR_CLK_CNTL (\ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL (\ +#define CFG_SYS_DDR_INTERVAL (\ (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f +#define CFG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDRCDR (\ +#define CFG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 +#define CFG_SYS_DDR_MODE 0x47860452 +#define CFG_SYS_DDR_MODE2 0x8080c000 -#define CONFIG_SYS_DDR_TIMING_0 (\ +#define CFG_SYS_DDR_TIMING_0 (\ (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ @@ -46,7 +46,7 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CFG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ (3 << TIMING_CFG1_WRREC_SHIFT) | \ @@ -55,7 +55,7 @@ (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ (3 << TIMING_CFG1_PRETOACT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 (\ +#define CFG_SYS_DDR_TIMING_2 (\ (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ @@ -64,11 +64,11 @@ (5 << TIMING_CFG2_CPO_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CFG_SYS_DDR_TIMING_3 0x00000000 /* EEprom support */ /* * PAXE on the local bus CS3 */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CFG_SYS_PAXE_BASE 0xA0000000 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index db1daee136..e6a3613b7a 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -9,7 +9,7 @@ */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ +#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CFG_83XX_DDR_USES_CS0 @@ -22,15 +22,15 @@ /* * The reserved memory */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CFG_SYS_FLASH_BASE 0xF0000000 /* Reserve 768 kB for Mon */ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ /* * Init Local Bus Memory Controller: * @@ -44,21 +44,21 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } /* I2C */ #define CFG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ {1, {I2C_NULL_HOP} } } #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 -#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif /* @@ -66,7 +66,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* * Environment diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index b5913ed700..7307c495c3 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -9,8 +9,8 @@ /* include common defines/options for all Keymile boards */ #include "keymile-common.h" -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ CONFIG_KM_PHRAM + \ @@ -19,24 +19,24 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* * IFC Definitions */ /* NOR Flash Definitions */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_TE | \ CSPR_MSEL_NOR | \ @@ -63,18 +63,18 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* NAND Flash Definitions */ #define CFG_SYS_NAND_BASE 0x68000000 @@ -110,40 +110,40 @@ FTIM2_NAND_TWHRE(0x3c)) #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO FPGA Definitions */ -#define CONFIG_SYS_QRIO_BASE 0x70000000 -#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE +#define CFG_SYS_QRIO_BASE 0x70000000 +#define CFG_SYS_QRIO_BASE_PHYS CFG_SYS_QRIO_BASE -#define CONFIG_SYS_CSPR2_EXT (0x00) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define CFG_SYS_CSPR2_EXT (0x00) +#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_TE | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_20 | \ CSOR_GPCM_BCTLD) -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ +#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ FTIM0_GPCM_TEADC(0x8) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x6)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ +#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) -#define CONFIG_SYS_CS2_FTIM3 0x04000000 +#define CFG_SYS_CS2_FTIM3 0x04000000 /* * Serial Port @@ -155,11 +155,11 @@ */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CFG_SYS_I2C_MAX_HOPS 1 #define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x0 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ +#define CFG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {1, {I2C_NULL_HOP} }, \ } @@ -205,12 +205,12 @@ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ "set_fdthigh=true\0" \ @@ -238,6 +238,6 @@ "ethrotate=no\0" \ "" -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index dbf038cefa..e152714b11 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -25,10 +25,10 @@ #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) /* Application IFC CS4 MRAM */ -#define CONFIG_SYS_MRAM_BASE SYS_LAWAPP_BASE +#define CFG_SYS_MRAM_BASE SYS_LAWAPP_BASE #define SYS_MRAM_BASE_PHYS SYS_LAWAPP_BASE_PHYS #define SYS_MRAM_CSPR_EXT (0x0f) -#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_MRAM_BASE) | \ +#define SYS_MRAM_CSPR (CSPR_PHYS_ADDR(CFG_SYS_MRAM_BASE) | \ CSPR_PORT_SIZE_8 | /* 8 bit */ \ CSPR_MSEL_GPCM | /* msel = gpcm */ \ CSPR_V /* bank is valid */) @@ -44,14 +44,14 @@ FTIM2_GPCM_TCH(0x2) | \ FTIM2_GPCM_TWP(0x8)) #define SYS_MRAM_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT -#define CONFIG_SYS_CSPR4 SYS_MRAM_CSPR -#define CONFIG_SYS_AMASK4 SYS_MRAM_AMASK -#define CONFIG_SYS_CSOR4 SYS_MRAM_CSOR -#define CONFIG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 -#define CONFIG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 -#define CONFIG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 -#define CONFIG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 +#define CFG_SYS_CSPR4_EXT SYS_MRAM_CSPR_EXT +#define CFG_SYS_CSPR4 SYS_MRAM_CSPR +#define CFG_SYS_AMASK4 SYS_MRAM_AMASK +#define CFG_SYS_CSOR4 SYS_MRAM_CSOR +#define CFG_SYS_CS4_FTIM0 SYS_MRAM_FTIM0 +#define CFG_SYS_CS4_FTIM1 SYS_MRAM_FTIM1 +#define CFG_SYS_CS4_FTIM2 SYS_MRAM_FTIM2 +#define CFG_SYS_CS4_FTIM3 SYS_MRAM_FTIM3 /* Application IFC CS6: BFTIC */ #define SYS_BFTIC_BASE 0xd0000000 @@ -73,20 +73,20 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_BFTIC_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT -#define CONFIG_SYS_CSPR6 SYS_BFTIC_CSPR -#define CONFIG_SYS_AMASK6 SYS_BFTIC_AMASK -#define CONFIG_SYS_CSOR6 SYS_BFTIC_CSOR -#define CONFIG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 -#define CONFIG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 -#define CONFIG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 -#define CONFIG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 +#define CFG_SYS_CSPR6_EXT SYS_BFTIC_CSPR_EXT +#define CFG_SYS_CSPR6 SYS_BFTIC_CSPR +#define CFG_SYS_AMASK6 SYS_BFTIC_AMASK +#define CFG_SYS_CSOR6 SYS_BFTIC_CSOR +#define CFG_SYS_CS6_FTIM0 SYS_BFTIC_FTIM0 +#define CFG_SYS_CS6_FTIM1 SYS_BFTIC_FTIM1 +#define CFG_SYS_CS6_FTIM2 SYS_BFTIC_FTIM2 +#define CFG_SYS_CS6_FTIM3 SYS_BFTIC_FTIM3 /* Application IFC CS7 PAXE */ -#define CONFIG_SYS_PAXE_BASE 0xd8000000 -#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CONFIG_SYS_PAXE_BASE) +#define CFG_SYS_PAXE_BASE 0xd8000000 +#define SYS_PAXE_BASE_PHYS (0xf00000000ull | CFG_SYS_PAXE_BASE) #define SYS_PAXE_CSPR_EXT (0x0f) -#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_PAXE_BASE) | \ +#define SYS_PAXE_CSPR (CSPR_PHYS_ADDR(CFG_SYS_PAXE_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ CSPR_V) /* valid */ @@ -102,14 +102,14 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) #define SYS_PAXE_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT -#define CONFIG_SYS_CSPR7 SYS_PAXE_CSPR -#define CONFIG_SYS_AMASK7 SYS_PAXE_AMASK -#define CONFIG_SYS_CSOR7 SYS_PAXE_CSOR -#define CONFIG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 -#define CONFIG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 -#define CONFIG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 -#define CONFIG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 +#define CFG_SYS_CSPR7_EXT SYS_PAXE_CSPR_EXT +#define CFG_SYS_CSPR7 SYS_PAXE_CSPR +#define CFG_SYS_AMASK7 SYS_PAXE_AMASK +#define CFG_SYS_CSOR7 SYS_PAXE_CSOR +#define CFG_SYS_CS7_FTIM0 SYS_PAXE_FTIM0 +#define CFG_SYS_CS7_FTIM1 SYS_PAXE_FTIM1 +#define CFG_SYS_CS7_FTIM2 SYS_PAXE_FTIM2 +#define CFG_SYS_CS7_FTIM3 SYS_PAXE_FTIM3 /* PRST */ #define KM_BFTIC4_RST 0 @@ -145,25 +145,25 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E /* POST memory regions test */ -#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS +#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS /* * Config the L3 Cache as L3 SRAM */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 +#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#define CFG_SYS_DCSRBAR 0xf0000000 +#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define SPD_EEPROM_ADDRESS 0x54 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -189,12 +189,12 @@ * IFC Definitions */ /* NOR flash on IFC CS0 */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ - CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE 0xe8000000 +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | \ + CFG_SYS_FLASH_BASE) #define CFG_SYS_NOR_CSPR_EXT (0x0f) -#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ +#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \ CSPR_PORT_SIZE_16 | /* Port size = 16 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_NOR | /* MSEL = NOR */\ @@ -217,18 +217,18 @@ FTIM2_NOR_TWPH(0x6)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 /* More NOR Flash params */ -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* NAND Flash on IFC CS1*/ #define CFG_SYS_NAND_BASE 0xfa000000 @@ -266,23 +266,23 @@ FTIM2_NAND_TWHRE(0x3c)) #define CFG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 /* More NAND Flash Params */ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } /* QRIO on IFC CS2 */ -#define CONFIG_SYS_QRIO_BASE 0xfb000000 -#define CONFIG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CONFIG_SYS_QRIO_BASE) +#define CFG_SYS_QRIO_BASE 0xfb000000 +#define CFG_SYS_QRIO_BASE_PHYS (0xf00000000ull | CFG_SYS_QRIO_BASE) #define SYS_QRIO_CSPR_EXT (0x0f) -#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ +#define SYS_QRIO_CSPR (CSPR_PHYS_ADDR(CFG_SYS_QRIO_BASE) | \ CSPR_PORT_SIZE_8 | /* Port size = 8 bit */\ 0x00000010 | /* drive TE high */\ CSPR_MSEL_GPCM | /* MSEL = GPCM */\ @@ -300,28 +300,28 @@ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x7)) #define SYS_QRIO_FTIM3 0x04000000 -#define CONFIG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT -#define CONFIG_SYS_CSPR2 SYS_QRIO_CSPR -#define CONFIG_SYS_AMASK2 SYS_QRIO_AMASK -#define CONFIG_SYS_CSOR2 SYS_QRIO_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 +#define CFG_SYS_CSPR2_EXT SYS_QRIO_CSPR_EXT +#define CFG_SYS_CSPR2 SYS_QRIO_CSPR +#define CFG_SYS_AMASK2 SYS_QRIO_AMASK +#define CFG_SYS_CSOR2 SYS_QRIO_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_QRIO_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_QRIO_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 +#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* * Serial Port - controlled on board with jumper J8 @@ -331,7 +331,7 @@ */ #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500) #endif #ifndef __ASSEMBLY__ @@ -351,30 +351,30 @@ int get_scl(void); #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_BMAN_NUM_PORTALS 10 +#define CFG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CFG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \ + CFG_SYS_BMAN_CENA_SIZE) +#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1) +#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08 +#define CFG_SYS_QMAN_NUM_PORTALS 10 +#define CFG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CFG_SYS_QMAN_MEM_SIZE 0x02000000 +#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000 +#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \ + CFG_SYS_QMAN_CENA_SIZE) +#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1) +#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08 /* Qman / Bman */ /* RGMII (FM1@DTESC5) is local managemant interface */ -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x11 +#define CFG_SYS_RGMII2_PHY_ADDR 0x11 /* * Hardware Watchdog @@ -387,7 +387,7 @@ int get_scl(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration @@ -412,12 +412,12 @@ int get_scl(void); __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +${filesize}\0" \ - "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + "erase " __stringify(CFG_SYS_FLASH_BASE) \ " +${filesize} && " \ "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ "set_fdthigh=true\0" \ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index b954029874..2be996aaaf 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -12,7 +12,7 @@ #define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 -#define CFG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ +#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" @@ -26,7 +26,7 @@ /** * KMCOGE5NE has 512 MB RAM */ -#define CONFIG_SYS_DDR_CS0_CONFIG (\ +#define CFG_SYS_DDR_CS0_CONFIG (\ CSCONFIG_EN | \ CSCONFIG_AP | \ CSCONFIG_ODT_WR_ONLY_CURRENT | \ @@ -35,7 +35,7 @@ CSCONFIG_COL_BIT_10) /* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) +#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) #define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 4245875e39..910fc1b2cb 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -16,7 +16,7 @@ #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ +#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ CSCONFIG_ODT_WR_ONLY_CURRENT) diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index e2808ec02d..6fcacdb0c6 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -16,10 +16,10 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Board and environment settings */ #define CONFIG_MXC_UART_BASE UART4_BASE diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 73b5951762..80a3230460 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -19,8 +19,8 @@ #define PHYS_SDRAM_SIZE (SZ_4G) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 /* Board and environment settings */ #define CONFIG_HOSTNAME "kontron-mx8mm" diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 9b452818c1..2abcb849a2 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -61,8 +61,8 @@ BOOTENV -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index bbf0761814..9c3174d0e0 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -12,17 +12,17 @@ /* we don't have secure memory unless we have a BL31 */ #ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#undef CONFIG_SYS_MEM_RESERVE_SECURE +#undef CFG_SYS_MEM_RESERVE_SECURE #endif /* DDR */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* early stack pointer */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index 967de66f3c..c551585a20 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -68,8 +68,8 @@ #define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* environment organization */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index de1fc0bfa4..136e228682 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -87,8 +87,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 9b70eed46f..828f910963 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -31,7 +31,7 @@ #ifdef CONFIG_CMD_I2C /* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ #if defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_I2C_G762_ADDR 0x3e +#define CFG_SYS_I2C_G762_ADDR 0x3e #endif #endif /* CONFIG_CMD_I2C */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index bee064c6f3..2664982715 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -17,10 +17,10 @@ /* * SoC Configuration */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* * Memory Info @@ -38,7 +38,7 @@ */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) /* * U-Boot general configuration diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 3a2c508ffa..11b3fa6c85 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -79,8 +79,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h index b913450885..f16c7e9122 100644 --- a/include/configs/linkit-smart-7688.h +++ b/include/configs/linkit-smart-7688.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -26,7 +26,7 @@ #endif /* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* RAM */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index d1ebd99ae1..721da81863 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -88,8 +88,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* FLASH and environment organization */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 0712437077..7598e54ed2 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,10 +10,10 @@ #include #include -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL /*SPI device */ #define CFG_SYS_FSL_QSPI_BASE 0x40000000 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 54555b34dd..e772c01907 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -17,7 +17,7 @@ */ #ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_BRDCFG_REG 0x04 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x08 @@ -47,7 +47,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Voltage monitor on channel 2*/ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 49a77fd6b6..b058308ecd 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* * DDR: 800 MHz ( 1600 MT/s data rate ) @@ -41,8 +41,8 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * Serial Port @@ -104,7 +104,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1f5a80ff08..5494b71e2b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) @@ -19,8 +19,8 @@ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_DDR_ECC #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -30,16 +30,16 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -61,10 +61,10 @@ #define CFG_SYS_NOR_FTIM3 0 #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} /* * NAND Flash Definitions @@ -111,7 +111,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -131,96 +131,96 @@ #define QIXIS_PWR_CTL2 0x21 #define QIXIS_PWR_CTL2_PCTL 0x2 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ FTIM0_GPCM_TEADC(0xe) | \ FTIM0_GPCM_TEAHC(0xe)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ FTIM2_GPCM_TCH(0xe) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif /* @@ -296,7 +296,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 4954606611..bc9eac700e 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -6,8 +6,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ @@ -56,8 +56,8 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* Serial Port */ #define CFG_SYS_NS16550_CLK get_serial_clock() @@ -141,7 +141,7 @@ "bootm $load_addr#$board\0" /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d77224934c..f1ccb5fc08 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -7,8 +7,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf @@ -59,18 +59,18 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -94,52 +94,52 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_FPGA_FTIM3 /* * Serial Port @@ -298,7 +298,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CFG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_LS102XA_STREAM_ID diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 064c4f069c..bdd3951e85 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -13,10 +13,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL /* * SMP Definitinos diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 2539115186..228fb122f5 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -17,7 +17,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 1 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 5 @@ -35,19 +35,19 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 1 +#define CFG_SYS_RTC_BUS_NUM 1 #define I2C_MUX_CH_RTC 0xB /* Store environment at top of flash */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index e7b2543b73..5c13461257 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -10,7 +10,7 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* Store environment at top of flash */ @@ -21,7 +21,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_LBMAP_MASK 0xe0 #define QIXIS_LBMAP_SHIFT 0x5 @@ -39,12 +39,12 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e940dff998..b4048744b1 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -32,10 +32,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr @@ -82,14 +82,14 @@ #if defined(CONFIG_TFABOOT) || \ (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -104,7 +104,7 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 87751f786c..dab57382ed 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -39,13 +39,13 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -66,10 +66,10 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions @@ -125,7 +125,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -143,130 +143,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 76251fde57..12c4853ea9 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -21,7 +21,7 @@ #define CFG_SYS_NOR_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -41,11 +41,11 @@ FTIM2_NOR_TWPH(0x8) | \ FTIM2_NOR_TWP(0x10)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions @@ -91,97 +91,97 @@ /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ FTIM0_GPCM_TEADC(0xf) | \ FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 /* * Environment diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ce254d8b3f..cac30e4679 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -32,10 +32,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL #define CPU_RELEASE_ADDR secondary_boot_addr @@ -68,7 +68,7 @@ /* FMan ucode */ #ifndef SPL_NO_FMAN #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #endif #endif diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 8402eac418..58ae0fb0a6 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -8,7 +8,7 @@ #include "ls1046a_common.h" -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 /* * NAND Flash Definitions @@ -48,14 +48,14 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 @@ -67,8 +67,8 @@ /* RTC */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ +#define CFG_SYS_RTC_BUS_NUM 0 /* * Environment diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d565492f1d..553ae841ca 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -33,14 +33,14 @@ /* IFC */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) /* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x60000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x60000000 +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -58,13 +58,13 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ +#define CFG_SYS_NOR1_CSPR_EXT (0x0) +#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ @@ -86,10 +86,10 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ + CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_WRITE_SWAPPED_DATA /* * NAND Flash Definitions @@ -145,7 +145,7 @@ #ifdef CONFIG_FSL_QIXIS #define QIXIS_BASE 0x7fb00000 #define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -163,130 +163,130 @@ #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_NOR_MODE_AVD_NOR | \ CSOR_NOR_TRHZ_80) /* * QIXIS Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ FTIM0_GPCM_TEADC(0x20) | \ FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ FTIM2_GPCM_TCH(0x8) | \ FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_FPGA_FTIM3 0x0 #endif #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else #ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK3 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS3_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS3_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS3_FTIM3 CFG_SYS_FPGA_FTIM3 #endif #endif diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 0df6891598..f3904e7b3f 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -16,7 +16,7 @@ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CFG_SYS_UBOOT_BASE 0x40100000 #endif #define CFG_SYS_NAND_BASE 0x7e800000 @@ -55,46 +55,46 @@ /* * CPLD */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ +#define CFG_SYS_CPLD_CSPR_EXT (0x0) +#define CFG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) +#define CFG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) /* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 +#define CFG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_CPLD_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_CPLD_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_CPLD_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_CPLD_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_CPLD_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_CPLD_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_CPLD_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_CPLD_FTIM3 /* EEPROM */ #define I2C_RETIMER_ADDR 0x18 diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index f8eaee881d..bacc84f629 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -30,10 +30,10 @@ #define CFG_SYS_FSL_QSPI_BASE 0x20000000 #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos */ @@ -64,18 +64,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -92,12 +92,12 @@ unsigned long long get_qixis_addr(void); /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -107,7 +107,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Miscellaneous configurable options */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index b75d4ccf5c..d84622f322 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -22,27 +22,27 @@ * IFC Definitions */ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -59,13 +59,13 @@ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #endif @@ -101,7 +101,7 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_QMAP_MASK 0xe0 #define QIXIS_QMAP_SHIFT 5 @@ -127,8 +127,8 @@ #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_NO_ADAPTER 0x7 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -139,9 +139,9 @@ #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) #else -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) #endif /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ @@ -155,102 +155,102 @@ #define SYS_FPGA_CS_FTIM3 0x0 #ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK3 SYS_FPGA_AMASK +#define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * I2C bus multiplexer @@ -281,7 +281,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #ifdef CONFIG_FSL_DSPI #if !defined(CONFIG_TFABOOT) && \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 27510adae6..187b3072f0 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -20,17 +20,17 @@ #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -44,12 +44,12 @@ FTIM2_NOR_TCH(0x0) | \ FTIM2_NOR_TWP(0x1)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif #endif @@ -85,7 +85,7 @@ #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_BRDCFG4_OFFSET 0x54 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_QMAP_MASK 0xe0 @@ -107,8 +107,8 @@ #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) @@ -117,8 +117,8 @@ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) /* QIXIS Timing parameters*/ #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ @@ -132,36 +132,36 @@ #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR +#define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL +#define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 +#define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 +#define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 +#define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #define I2C_MUX_CH_VOL_MONITOR 0xA /* Voltage monitor on channel 2*/ @@ -191,7 +191,7 @@ * RTC configuration */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #endif #ifndef SPL_NO_ENV diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 21c097ecbb..18defd5e5a 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -17,10 +17,10 @@ /* Link Definitions */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* * SMP Definitinos @@ -56,18 +56,18 @@ * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) * * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address + * CFG_SYS_FLASH_BASE has the final address (core view) + * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) + * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address * CONFIG_TEXT_BASE is linked to 0x30000000 for booting */ -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 +#define CFG_SYS_FLASH_BASE 0x580000000ULL +#define CFG_SYS_FLASH_BASE_PHYS 0x80000000 +#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 +#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000 +#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); @@ -84,13 +84,13 @@ unsigned long long get_qixis_addr(void); /* MC firmware */ /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 /* For LS2085A */ -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 +#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 +#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -99,7 +99,7 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif /* Miscellaneous configurable options */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7315790f1f..067587b53c 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -10,10 +10,10 @@ #include "ls2080a_common.h" #ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_I2C_IFDR_DIV 0x7e +#define CFG_SYS_I2C_IFDR_DIV 0x7e #endif -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) #define CONFIG_MEM_INIT_VALUE 0xdeadbeef @@ -25,27 +25,27 @@ #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ +#define CFG_SYS_NOR1_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR1_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -61,13 +61,13 @@ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #define CFG_SYS_NAND_CSPR_EXT (0x0) @@ -119,92 +119,92 @@ #define QIXIS_RCW_SRC_QSPI 0x62 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 #if defined(CONFIG_SPL) #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY +#define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR +#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY +#define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * I2C @@ -229,7 +229,7 @@ */ #define RTC #define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index daca3be16c..32a1194872 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -32,17 +32,17 @@ #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CFG_SYS_NOR0_CSPR_EXT (0x0) #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ +#define CFG_SYS_NOR0_CSPR \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ +#define CFG_SYS_NOR0_CSPR_EARLY \ + (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) @@ -58,13 +58,13 @@ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 +#define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ + CFG_SYS_FLASH_BASE + 0x40000000} #endif #define CFG_SYS_NAND_CSPR_EXT (0x0) @@ -113,70 +113,70 @@ #define QIXIS_RCW_SRC_NAND 0x119 #define QIXIS_RST_FORCE_MEM 0x01 -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ +#define CFG_SYS_CSPR3_EXT (0x0) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ +#define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) +#define CFG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) /* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ FTIM0_GPCM_TEADC(0x0e) | \ FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ FTIM2_GPCM_TCH(0xf) | \ FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 +#define CFG_SYS_CS3_FTIM3 0x0 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024) #else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 +#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY +#define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 +#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif #endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #ifdef CONFIG_TARGET_LS2081ARDB #define QIXIS_QMAP_MASK 0x07 @@ -197,7 +197,7 @@ * I2C */ #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 #endif #define I2C_MUX_PCA_ADDR 0x75 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ @@ -212,10 +212,10 @@ */ #define RTC #ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 #else #define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index ad85e2de6e..bbee9df404 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -10,15 +10,15 @@ #include #include -#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CFG_SYS_FLASH_BASE 0x20000000 /* DDR */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL +#define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CFG_SYS_SDRAM_SIZE 0x200000000UL -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -42,22 +42,22 @@ /* Serial Port */ #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) -#define CONFIG_SYS_SERIAL0 0x21c0000 -#define CONFIG_SYS_SERIAL1 0x21d0000 -#define CONFIG_SYS_SERIAL2 0x21e0000 -#define CONFIG_SYS_SERIAL3 0x21f0000 +#define CFG_SYS_SERIAL0 0x21c0000 +#define CFG_SYS_SERIAL1 0x21d0000 +#define CFG_SYS_SERIAL2 0x21e0000 +#define CFG_SYS_SERIAL3 0x21f0000 /*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3 } +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1, \ + (void *)CFG_SYS_SERIAL2, \ + (void *)CFG_SYS_SERIAL3 } /* MC firmware */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 +#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 +#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -66,7 +66,7 @@ * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #endif /* I2C bus multiplexer */ @@ -75,10 +75,10 @@ /* RTC */ #define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Qixis */ -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define CFG_SYS_I2C_FPGA_ADDR 0x66 /* USB */ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 4e8a904859..9f891064bd 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h" /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* MAC/PHY configuration */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index bb9239cc59..58c0ff3657 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -9,7 +9,7 @@ #include "lx2160a_common.h" /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 4 +#define CFG_SYS_RTC_BUS_NUM 4 /* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index b70abb013f..157688ef7d 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -11,7 +11,7 @@ /* USB */ /* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 +#define CFG_SYS_RTC_BUS_NUM 0 /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index cbdb2fa135..f87bbf7ccf 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -21,8 +21,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* * U-Boot general configurations @@ -58,13 +58,13 @@ #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif -#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ +#define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ /* * RTC */ #ifdef CONFIG_CMD_DATE -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 #endif /* @@ -77,7 +77,7 @@ #endif /* LVDS display */ -#define CONFIG_SYS_LDB_CLOCK 33260000 +#define CFG_SYS_LDB_CLOCK 33260000 #define CONFIG_IMX_VIDEO_SKIP /* IIM Fuses */ diff --git a/include/configs/malta.h b/include/configs/malta.h index c9aee00cd3..65f4b05649 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -28,7 +28,7 @@ #endif #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* * Serial driver @@ -38,9 +38,9 @@ * Flash configuration */ #ifdef CONFIG_64BIT -# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 +# define CFG_SYS_FLASH_BASE 0xffffffffbe000000 #else -# define CONFIG_SYS_FLASH_BASE 0xbe000000 +# define CFG_SYS_FLASH_BASE 0xbe000000 #endif /* diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 8aa3b0cd80..7c401a2cfd 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -9,7 +9,7 @@ #include "mx6_common.h" -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + 0x80000) /* * Below defines are set but NOT really used since we by @@ -24,12 +24,12 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* NOR 16-bit mode */ -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #define CONFIG_FLASH_VERIFY /* NOR Flash MTD */ -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } +#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } +#define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 @@ -116,7 +116,7 @@ "nor_img_addr=0x11000000\0" \ "nor_img_file=core-image-lwn-mccmon6.nor\0" \ "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ - "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ + "nor_bank_start=" __stringify(CFG_SYS_FLASH_BASE) "\0" \ "nor_img_size=0x02000000\0" \ "factory_script_file=factory.scr\0" \ "factory_load_script=" \ @@ -215,8 +215,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 2422cbf9f0..9e480fe055 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -18,8 +18,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment configs */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 2e07886c19..d190e4b503 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -28,8 +28,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ +#define CFG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ /* Misc CPU related */ @@ -47,8 +47,8 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM #define CFG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM0 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 139b5bca10..edd2466caa 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -13,7 +13,7 @@ /* uart */ /* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ +# define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} #define CONFIG_HOSTNAME "microblaze-generic" @@ -95,6 +95,6 @@ /* SPL part */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE #endif /* __CONFIG_H */ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index ac5ff9289a..cfe926c0a1 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -14,7 +14,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 @@ -46,8 +46,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 diff --git a/include/configs/mt7620.h b/include/configs/mt7620.h index 65cd6f5bc4..d5bd492634 100644 --- a/include/configs/mt7620.h +++ b/include/configs/mt7620.h @@ -10,13 +10,13 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7620_H */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1211bb4748..7c8c67f446 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -13,7 +13,7 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x800000 +#define CFG_SYS_INIT_SP_OFFSET 0x800000 /* MMC */ #define MMC_SUPPORTS_TUNING @@ -27,10 +27,10 @@ #endif /* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7621_H */ diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index e5d60e1cd2..8c297266d8 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -10,10 +10,10 @@ #define __MT7622_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7628.h b/include/configs/mt7628.h index 9c5034f5f0..9df2715fc7 100644 --- a/include/configs/mt7628.h +++ b/include/configs/mt7628.h @@ -10,7 +10,7 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x80000 +#define CFG_SYS_INIT_SP_OFFSET 0x80000 /* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) @@ -19,14 +19,14 @@ #endif /* Serial common */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600 } /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 #endif /* __CONFIG_MT7628_H */ diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index d330adbc01..bfa44aacc7 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -18,7 +18,7 @@ /* Defines for SPL */ #define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) +#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 249f0b9662..14c885ec55 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -10,10 +10,10 @@ #define __MT7981_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index 990e411a64..0c41af1fc3 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -10,10 +10,10 @@ #define __MT7986_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* DRAM */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index d15941660a..3a35527da1 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -10,7 +10,7 @@ #define __MT8512_H /* Uboot definition */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE #define ENV_BOOT_READ_IMAGE \ "boot_rd_img=mmc dev 0" \ diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index e45bfd76b6..fa275d61d1 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -32,13 +32,13 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif -#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE) -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#if defined(CONFIG_ARMADA_38X) && !defined(CFG_SYS_BAUDRATE_TABLE) +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 9c4038be8b..5c9620371e 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -11,7 +11,7 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x200000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } /* Default Env vars */ @@ -37,6 +37,6 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 325000000 +#define CFG_SYS_TCLK 325000000 #endif /* _CONFIG_MVEBU_ALLEYCAY_5_H */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 7641b56221..9bfc48c52d 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -15,7 +15,7 @@ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 358e06fd20..beac3ae649 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -9,14 +9,14 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#define CFG_SYS_TCLK 250000000 /* 250MHz */ /* additions for new ARM relocation support */ #define CFG_SYS_SDRAM_BASE 0x00000000 /* auto boot */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 115200, 230400, 460800, 921600 } /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 2229980db3..3c99b70a2b 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -113,12 +113,12 @@ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON +#define CFG_SYS_DDR_CLKSEL 0 +#define CFG_SYS_CLKTL_CBCDR 0x59E35100 +#define CFG_SYS_MAIN_PWR_ON /*----------------------------------------------------------------------- * environment organization diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index e84bac67ef..2bc462cc37 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -61,8 +61,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* environment organization */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 9e837a3883..b52e70c95a 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -24,7 +24,7 @@ /* PMIC Controller */ #define CONFIG_POWER_FSL #define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 +#define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8 /* Command definition */ @@ -96,8 +96,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* Framebuffer and LCD */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 52ff7b00b4..7160654eb3 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -87,7 +87,7 @@ /* Miscellaneous configurable options */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ /* Physical Memory Map */ #define PHYS_SDRAM_1 CSD0_BASE_ADDR @@ -97,8 +97,8 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) +#define CFG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CFG_SYS_INIT_RAM_SIZE (IRAM_SIZE) /* FLASH and environment organization */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 4314556754..245530aa64 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -12,7 +12,7 @@ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE +#define CFG_SYS_PL310_BASE L2_PL310_BASE #endif #endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 3c4ba095e4..12741c08de 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -86,8 +86,8 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index 9c160c41ec..f6d3b2eeb9 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -28,8 +28,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 711b5a334a..5e95e430c4 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -140,8 +140,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 3fdf829e96..1a2160cce5 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -16,7 +16,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" @@ -26,7 +26,7 @@ #endif #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #endif #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 3c2621d8c9..358d9f47c0 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -83,8 +83,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index a3a12aeb39..6632e4ea29 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -83,8 +83,8 @@ #define PHYS_SDRAM_SIZE SZ_2G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index f0e239fdb6..0dd40563c2 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -79,8 +79,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index a0f9c537e5..6f5dffe4fb 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -107,8 +107,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 8199b4b831..cb1019bd56 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -109,8 +109,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 827385c65e..4154d328de 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -103,8 +103,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index c39b3572b8..6c165521f7 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -82,8 +82,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 362de482f5..85922fa436 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -18,7 +18,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1MHz from TSTMR */ /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -48,8 +48,8 @@ "bootz ${loadaddr} - ${fdt_addr}; " \ "fi;\0" \ -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 9ef1eea5e6..99e01896c7 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -15,7 +15,7 @@ /* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG1_RBASE -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ /* UART */ #define LPUART_BASE LPUART4_RBASE @@ -92,7 +92,7 @@ "bootz; " \ "fi;\0" \ -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE SZ_256K #endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 9d6b3d4048..5df080ade4 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -46,11 +46,11 @@ /* Memory sizes */ /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CFG_SYS_INIT_RAM_ADDR 0x00000000 #if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (32 * 1024) #elif defined(CONFIG_MX28) -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) +#define CFG_SYS_INIT_RAM_SIZE (128 * 1024) #endif /* Point initial SP in SRAM so SPL can use it too. */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index cdd12866ac..a32fcd57f8 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -23,8 +23,8 @@ #define PHYS_SDRAM_SIZE SZ_256M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 9d09811316..dd7f951319 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -91,8 +91,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 9ad4f59069..9c364adc63 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -47,7 +47,7 @@ */ #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } /* USB device configuration */ #define CONFIG_USB_DEVICE @@ -64,7 +64,7 @@ * Board ONENAND Info. */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BASE ONENAND_MAP /* Environment information */ #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -150,7 +150,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) /* * Physical Memory Map @@ -162,8 +162,8 @@ */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CFG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CFG_SYS_INIT_RAM_SIZE 0x800 /* * Attached kernel image diff --git a/include/configs/novena.h b/include/configs/novena.h index 8d39d75a42..6f588f99c3 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -31,8 +31,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* I2C */ #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 080c659b6e..09c4ddb664 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -24,8 +24,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/nsim.h b/include/configs/nsim.h index b930a53864..013a3491a3 100644 --- a/include/configs/nsim.h +++ b/include/configs/nsim.h @@ -12,8 +12,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_256M /* diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 5ac951a370..ea1edab9fc 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -8,8 +8,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #if IS_ENABLED(CONFIG_CMD_USB) # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index b475354bbc..c0ea9e852d 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,10 +8,10 @@ #define __OCTEON_COMMON_H__ #if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_INIT_SP_OFFSET 0x20180000 +#define CFG_SYS_INIT_SP_OFFSET 0x20180000 #else /* No DDR init -> run in L2 cache with limited resources */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000 +#define CFG_SYS_INIT_SP_OFFSET 0x00180000 #endif #define CFG_SYS_SDRAM_BASE 0xffffffff80000000 diff --git a/include/configs/odroid.h b/include/configs/odroid.h index ce8ea583fa..8b00a27921 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -14,7 +14,7 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0890f51eff..f4e23bbb0f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -20,7 +20,7 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 6eec955e88..8bb8521f1c 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -25,7 +25,7 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CFG_SYS_FLASH_BASE NAND_BASE #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CFG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 10f6ba6360..a6b5e55b54 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -66,8 +66,8 @@ BOOTENV /* OneNAND config */ -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) +#define CFG_SYS_ONENAND_BASE ONENAND_MAP +#define CFG_SYS_ONENAND_BLOCK_SIZE (128*1024) /* NAND config */ #define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 6001037ae8..3895537751 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -144,9 +144,9 @@ /* **** PISMO SUPPORT *** */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif -#define CONFIG_SYS_FLASH_SIZE 0x4000000 +#define CFG_SYS_FLASH_SIZE 0x4000000 #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 883cc0b99c..1634db8606 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -37,8 +37,8 @@ /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 -#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 +#define CFG_SYS_I2C_TCA642X_BUS_NUM 4 +#define CFG_SYS_I2C_TCA642X_ADDR 0x22 /* Enabled commands */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 5b0d87a336..788a111386 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -17,9 +17,9 @@ /* * SoC Configuration */ -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) +#define CFG_SYS_OSCIN_FREQ 24000000 +#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE +#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) /* * Memory Info @@ -32,7 +32,7 @@ /* memtest will be run on 16MB */ -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ +#define CFG_SYS_DA850_SYSCFG_SUSPSRC ( \ DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ DAVINCI_SYSCFG_SUSPSRC_UART2 | \ @@ -44,17 +44,17 @@ */ /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ -#define CONFIG_SYS_DA850_PLL0_PLLM 18 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 +#define CFG_SYS_DA850_PLL0_PLLM 18 +#define CFG_SYS_DA850_PLL1_PLLM 21 /* * DDR2 memory configuration */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ +#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ DV_DDR_PHY_EXT_STRBEN | \ (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ +#define CFG_SYS_DA850_DDR2_SDBCR ( \ (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ @@ -64,9 +64,9 @@ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 +#define CFG_SYS_DA850_DDR2_SDBCR2 0 -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR ( \ (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ @@ -76,7 +76,7 @@ (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ (1 << DV_DDR_SDTMR1_WTR_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ +#define CFG_SYS_DA850_DDR2_SDTIMR2 ( \ (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ @@ -85,21 +85,21 @@ (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ (2 << DV_DDR_SDTMR2_CKE_SHIFT)) -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 +#define CFG_SYS_DA850_DDR2_SDRCR 0x00000492 +#define CFG_SYS_DA850_DDR2_PBBPR 0x30 /* * Serial Driver info */ #define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) +#define CFG_SYS_SPI_BASE DAVINCI_SPI1_BASE +#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) /* * I2C Configuration */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 +#define CFG_SYS_I2C_EXPANDER_ADDR 0x20 /* * Flash & Environment diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 53889d699b..e42a736136 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -15,8 +15,8 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB */ #ifdef CONFIG_USB_EHCI_MX6 diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h index d155e553e2..c96deda61d 100644 --- a/include/configs/p1_p2_bootsrc.h +++ b/include/configs/p1_p2_bootsrc.h @@ -7,11 +7,11 @@ #include -#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR) -#error "CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required" +#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CFG_SYS_I2C_PCA9557_ADDR) +#error "CONFIG_SYS_SPD_BUS_NUM and CFG_SYS_I2C_PCA9557_ADDR are required" #endif -#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1 +#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CFG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CFG_SYS_I2C_PCA9557_ADDR 3 msk 1 #define __VAR_CMD(var, cmd) __stringify(var=cmd\0) #define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 14d702e1ef..e8b752785b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -83,19 +83,19 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE #ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR -#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) +#define CFG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512) #else -#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO #endif #elif defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) +#define CFG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CFG_SYS_NAND_U_BOOT_SIZE (832 << 10) @@ -118,8 +118,8 @@ */ #define CONFIG_L2_CACHE -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xffe00000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 @@ -130,40 +130,40 @@ #define CFG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G #endif #define CFG_SYS_SDRAM_SIZE (1u << (CFG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE /* Default settings for DDR3 */ #ifndef CONFIG_TARGET_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000003f +#define CFG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CFG_SYS_DDR_CS1_BNDS 0x0040007f +#define CFG_SYS_DDR_CS1_CONFIG 0x80014302 +#define CFG_SYS_DDR_CS1_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CFG_SYS_DDR_INIT_ADDR 0x00000000 +#define CFG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CFG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 +#define CFG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CFG_SYS_DDR_WRLVL_CONTROL 0x8655A608 +#define CFG_SYS_DDR_SR_CNTR 0x00000000 +#define CFG_SYS_DDR_RCW_1 0x00000000 +#define CFG_SYS_DDR_RCW_2 0x00000000 +#define CFG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CFG_SYS_DDR_CONTROL_2 0x04401050 +#define CFG_SYS_DDR_TIMING_4 0x00220001 +#define CFG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 +#define CFG_SYS_DDR_TIMING_3 0x00020000 +#define CFG_SYS_DDR_TIMING_0 0x00330004 +#define CFG_SYS_DDR_TIMING_1 0x6f6B4846 +#define CFG_SYS_DDR_TIMING_2 0x0FA8C8CF +#define CFG_SYS_DDR_CLK_CTRL 0x03000000 +#define CFG_SYS_DDR_MODE_1 0x40461520 +#define CFG_SYS_DDR_MODE_2 0x8000c000 +#define CFG_SYS_DDR_INTERVAL 0x0C300000 #endif /* @@ -186,23 +186,23 @@ * Local Bus Definitions */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_FLASH_BASE 0xec000000 +#define CFG_SYS_FLASH_BASE 0xec000000 #else -#define CONFIG_SYS_FLASH_BASE 0xef000000 +#define CFG_SYS_FLASH_BASE 0xef000000 #endif #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) #else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* Nand Flash */ @@ -241,42 +241,42 @@ #endif #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) #else /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS #endif /* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_CPLD_BASE 0xffa00000 +#define CFG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull +#define CFG_SYS_CPLD_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE +#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE #endif /* CPLD config size: 1Mb */ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" -#define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#define CFG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#define CFG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull #else -#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#define CFG_SYS_VSC7385_BASE_PHYS CFG_SYS_VSC7385_BASE #endif /* The size of the VSC7385 firmware image */ @@ -292,18 +292,18 @@ */ #if defined(CONFIG_SPL_BUILD) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) +#define CFG_SYS_INIT_L2_ADDR 0xf8f80000 +#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR +#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif /* CONFIG_TPL_BUILD */ #endif #endif @@ -315,15 +315,15 @@ #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500) +#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600) /* I2C */ #if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } +#define CFG_SYS_I2C_NOPROBES { {0, 0x29} } #endif /* @@ -331,8 +331,8 @@ */ #define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 +#define CFG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ @@ -397,7 +397,7 @@ */ #if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) +#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif @@ -418,7 +418,7 @@ * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ /* * Environment Configuration diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 85cedde098..2a1660bf18 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -35,8 +35,8 @@ #define PHYS_SDRAM_SIZE SZ_256M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index f7e36f22ce..4421e740d9 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -37,8 +37,8 @@ #define PHYS_SDRAM_SIZE SZ_256M #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* NAND */ #define CFG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 586cddf418..5c2ff5d02e 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -119,8 +119,8 @@ #define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index cf705dcb19..3674e4cdda 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -16,8 +16,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ #define ENV_MMC \ diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h index e08d941412..1b72739d14 100644 --- a/include/configs/pg-wcom-expu1.h +++ b/include/configs/pg-wcom-expu1.h @@ -13,23 +13,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* CLIPS FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000 /* PRST */ #define WCOM_CLIPS_RST 0 diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h index 9a7669c940..e4bcae5bb5 100644 --- a/include/configs/pg-wcom-seli8.h +++ b/include/configs/pg-wcom-seli8.h @@ -12,23 +12,23 @@ #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* PAXK FPGA Definitions */ -#define CONFIG_SYS_CSPR3_EXT (0x00) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ +#define CFG_SYS_CSPR3_EXT (0x00) +#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ CSPR_PORT_SIZE_8 | \ CSPR_MSEL_GPCM | \ CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ +#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ CSOR_GPCM_TRHZ_40) -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ +#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ FTIM0_GPCM_TEADC(0x7) | \ FTIM0_GPCM_TEAHC(0x2)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ +#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ FTIM1_GPCM_TRAD(0x12)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ +#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ FTIM2_GPCM_TCH(0x1) | \ FTIM2_GPCM_TWP(0x12)) -#define CONFIG_SYS_CS3_FTIM3 0x04000000 +#define CFG_SYS_CS3_FTIM3 0x04000000 /* PRST */ #define KM_LIU_RST 0 diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index ac68c933a0..7f73117ac1 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -60,8 +60,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index aedaf806e5..11a833bb12 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,7 +10,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -59,8 +59,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index d9abbbc28b..3cc2a693ce 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -18,9 +18,9 @@ * Memory Layout */ /* Initial RAM for temporary stack, global data */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_ADDR \ + (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CFG_SYS_INIT_RAM_SIZE) /* SDRAM Configuration (for final code, data, stack, heap) */ #define CFG_SYS_SDRAM_BASE 0x88000000 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index fc2cab960c..9e6c210c40 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -92,8 +92,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 22b4976d72..8af8883fad 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -92,8 +92,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #ifdef CONFIG_VIDEO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index f5b9eed2bc..7028264d72 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -94,8 +94,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ #define CONFIG_POWER_PFUZE3000 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 91baff9638..f9301a5524 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -63,8 +63,8 @@ /* Link Definitions */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE 0x80000 #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 3fbddd903a..a233fb8ed7 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -22,47 +22,47 @@ #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* clocks */ /* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOC_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 /* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ +#define CFG_SYS_MATRIX_EBICSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +#define CFG_SYS_SDRC_TR_VAL1 0x13C /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -76,10 +76,10 @@ (1 << 28)) /* Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -88,37 +88,37 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -139,10 +139,10 @@ /* NOR flash */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 #define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index c1f6334d6a..9fd897958a 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -22,14 +22,14 @@ #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ /* clocks */ -#define CONFIG_SYS_MOR_VAL \ +#define CFG_SYS_MOR_VAL \ (AT91_PMC_MOR_MOSCEN | \ (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ +#define CFG_SYS_PLLAR_VAL \ (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ AT91_PMC_PLLXR_OUT(3) | \ AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ @@ -38,43 +38,43 @@ #if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_2) #else /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ +#define CFG_SYS_MCKR1_VAL \ (AT91_PMC_MCKR_CSS_SLOW | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ +#define CFG_SYS_MCKR2_VAL \ (AT91_PMC_MCKR_CSS_PLLA | \ AT91_PMC_MCKR_PRES_1 | \ AT91_PMC_MCKR_MDIV_4) #endif /* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ +#define CFG_SYS_MATRIX_EBI0CSA_VAL \ (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CFG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +#define CFG_SYS_SDRC_TR_VAL1 0x3AA /* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ +#define CFG_SYS_SDRC_CR_VAL \ (AT91_SDRAMC_NC_9 | \ AT91_SDRAMC_NR_13 | \ AT91_SDRAMC_NB_4 | \ @@ -88,10 +88,10 @@ (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -100,37 +100,37 @@ #define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ +#define CFG_SYS_SMC0_SETUP0_VAL \ (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ +#define CFG_SYS_SMC0_PULSE0_VAL \ (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ +#define CFG_SYS_SMC0_CYCLE0_VAL \ (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ +#define CFG_SYS_SMC0_MODE0_VAL \ (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ AT91_SMC_MODE_DBW_16 | \ AT91_SMC_MODE_TDF | \ AT91_SMC_MODE_TDF_CYCLE(6)) /* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ +#define CFG_SYS_RSTC_RMR_VAL \ (AT91_RSTC_KEY | \ AT91_RSTC_CR_PROCRST | \ AT91_RSTC_MR_ERSTL(1) | \ AT91_RSTC_MR_ERSTL(2)) /* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ +#define CFG_SYS_WDTC_WDMR_VAL \ (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ AT91_WDT_MR_WDV(0xfff) | \ AT91_WDT_MR_WDDIS | \ @@ -142,7 +142,7 @@ /* NOR flash, if populated */ #define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -166,7 +166,7 @@ AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ +#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ #define CONFIG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 4a0a16818e..686411eee2 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -16,8 +16,8 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x70000000 @@ -53,9 +53,9 @@ 56, 57, 58, 59, 60, 61, 62, 63, } #endif -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 +#define CFG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_AT91_PLLA 0x20c73f03 +#define CFG_SYS_MCKR 0x1301 +#define CFG_SYS_MCKR_CSS 0x1302 #endif diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 365fdd30c0..518d7a3639 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -7,10 +7,10 @@ #define __CONFIG_POLEG_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ +#define CFG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #endif -#define CONFIG_SYS_BOOTMAPSZ (0x30 << 20) +#define CFG_SYS_BOOTMAPSZ (0x30 << 20) #define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index bee1ef6494..2b25c31b1d 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -9,8 +9,8 @@ #define __PRESIDIO_ASIC_H /* Generic Timer Definitions */ -#define CONFIG_SYS_TIMER_RATE 25000000 -#define CONFIG_SYS_TIMER_COUNTER 0xf4321008 +#define CFG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMER_COUNTER 0xf4321008 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE * does not yet support DT. Thus define it here. @@ -18,7 +18,7 @@ #define GICD_BASE 0xf7011000 #define GICC_BASE 0xf7012000 -#define CONFIG_SYS_TIMER_BASE 0xf4321000 +#define CFG_SYS_TIMER_BASE 0xf4321000 /* Use external clock source */ #define PRESIDIO_APB_CLK 125000000 @@ -26,11 +26,11 @@ /* Cortina Serial Configuration */ #define CORTINA_UART_CLOCK (PRESIDIO_APB_CLK) -#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CORTINA_SERIAL_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1} -#define CONFIG_SYS_SERIAL0 PER_UART0_CFG -#define CONFIG_SYS_SERIAL1 PER_UART1_CFG +#define CFG_SYS_SERIAL0 PER_UART0_CFG +#define CFG_SYS_SERIAL1 PER_UART1_CFG /* SDRAM Bank #1 */ #define DDR_BASE 0x00000000 @@ -58,7 +58,7 @@ /* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC - #define CFG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE + #define CFG_SYS_NAND_BASE CFG_SYS_FLASH_BASE #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index 58020ae95b..c41bb341d8 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index e7c810957d..aa9cae017d 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -12,39 +12,39 @@ /* Needed to fill the ccsrbar pointer */ /* Virtual address to CCSRBAR */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CFG_SYS_CCSRBAR 0xe0000000 /* Physical address should be a function call */ #ifndef __ASSEMBLY__ extern unsigned long long get_phys_ccsrbar_addr_early(void); -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) -#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() +#define CFG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) +#define CFG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0x0 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR #endif /* Virtual address to a temporary map if we need it (max 128MB) */ -#define CONFIG_SYS_TMPVIRT 0xe8000000 +#define CFG_SYS_TMPVIRT 0xe8000000 /* * DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_HWCONFIG -#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR 0x00100000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 +#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 /* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CFG_SYS_INIT_RAM_ADDR_PHYS \ + ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CFG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CFG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* RTC */ #define CONFIG_RTC_PT7C4338 @@ -58,7 +58,7 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ /* * Environment Configuration diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index f6ee7201eb..bad74cc620 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -10,12 +10,12 @@ #define CFG_SYS_SDRAM_SIZE 0x04000000 /* Address of u-boot image in Flash */ -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) +#define CFG_SYS_BOOTMAPSZ (8 * 1024 * 1024) /* * NOR Flash ( Spantion S29GL256P ) */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CFG_SYS_FLASH_BASE (0xA0000000) +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /* __CONFIG_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 606a0a7ecd..a86180ead5 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -15,14 +15,14 @@ #endif /* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } #define CFG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ #define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (get_board_sys_clk() / 8) +#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ +#define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) #endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 5853072597..e9cbd25382 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -18,7 +18,7 @@ #define GICC_BASE 0xF1020000 /* console */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } /* PHY needs a longer autoneg timeout */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index b4c1972747..a4cae69718 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -8,7 +8,7 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index fac27a7d27..302546630a 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 6889ba591b..58ad62afe1 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -8,7 +8,7 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0x10080000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 4aa7e0449d..6b55c57dd7 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -9,7 +9,7 @@ #include #include "rockchip-common.h" -#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CFG_SYS_HZ_CLOCK 24000000 #define CONFIG_IRAM_BASE 0xff700000 diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 2c24944d9c..e354927513 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -17,14 +17,14 @@ /* Use SoC timer for AArch32, but architected timer for AArch64 */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER \ +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER \ (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) #endif /* Memory layout */ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* * The board really has 256M. However, the VC (VideoCore co-processor) shares * the RAM, and uses a configurable portion at the top. We tell U-Boot that a diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 76836add30..84a5ae6965 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -10,10 +10,10 @@ #define CONFIG_IRAM_BASE 0x10080000 -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CFG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ -#define CONFIG_SYS_TIMER_BASE 0x10350020 -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CFG_SYS_TIMER_BASE 0x10350020 +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMER_BASE + 8) #define CFG_SYS_SDRAM_BASE 0x60000000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index ed891ab22a..3d49d52b38 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -124,6 +124,6 @@ /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_SYS_ONENAND_BASE 0xB0000000 +#define CFG_SYS_ONENAND_BASE 0xB0000000 #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 614d04fda0..06be9c0f65 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -87,7 +87,7 @@ "mmcrootpart=3\0" \ "opts=always_resume=1" -#define CONFIG_SYS_ONENAND_BASE 0x0C000000 +#define CFG_SYS_ONENAND_BASE 0x0C000000 #ifndef __ASSEMBLY__ void universal_spi_scl(int bit); diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 41e52546ed..2e422cd241 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __SALVATOR_X_H */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 75302bf5c0..f44ce909b9 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -10,8 +10,8 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 22813d4c54..27b39ebf41 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -11,8 +11,8 @@ #define __CONFIG_H__ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 79f354d2e6..d62146e779 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -11,8 +11,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SPL */ diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index f826eab9ff..1979cb366e 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index 01ed1a3c8e..a072b21dfb 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -11,8 +11,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 2e3c1ea400..bf3c92bdf3 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -12,8 +12,8 @@ #include "at91-sama5_common.h" -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#undef CFG_SYS_AT91_MAIN_CLOCK +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 3f58928565..4f579ad9c5 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -27,7 +27,7 @@ /* NOR flash */ #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CFG_SYS_FLASH_BASE 0x10000000 #endif /* SDRAM */ diff --git a/include/configs/sama7g5ek.h b/include/configs/sama7g5ek.h index 68fa31fe76..59f13edbc8 100644 --- a/include/configs/sama7g5ek.h +++ b/include/configs/sama7g5ek.h @@ -9,8 +9,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x60000000 #define CFG_SYS_SDRAM_SIZE 0x20000000 diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5a7f5e135b..1081e0bbc4 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -17,7 +17,7 @@ #define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} #ifndef SANDBOX_NO_SDL diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index af5fe27e68..f7cdd5a195 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -11,7 +11,7 @@ #include #include -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 31552f4619..5a001716fb 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -35,7 +35,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_DRAM_1 /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ /* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index d2bc73a400..794475942a 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -36,8 +36,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ /* misc settings */ @@ -87,8 +87,8 @@ * leaving the correct space for initial global data structure above that * address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* Defines for SPL */ @@ -102,11 +102,11 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK (198656000/2) +#define CFG_SYS_MASTER_CLOCK (198656000/2) #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x2060bf09 -#define CONFIG_SYS_MCKR 0x100 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10483f0e +#define CFG_SYS_AT91_PLLA 0x2060bf09 +#define CFG_SYS_MCKR 0x100 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10483f0e #endif /* __CONFIG_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 64963eebe5..ffa1a1fcb0 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -88,7 +88,7 @@ * Boot configuration */ -#define CONFIG_SYS_ONENAND_BASE 0xE7100000 +#define CFG_SYS_ONENAND_BASE 0xE7100000 /* * Ethernet Contoller driver diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 44b9109d44..14f9cf5602 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -39,7 +39,7 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 9b1cb372ec..b7aa49ce43 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -15,16 +15,16 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* CPU */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CFG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM /* Mem test settings */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 9551680079..afca7e18e9 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -15,7 +15,7 @@ * Clocks */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CFG_SYS_TIMERBASE OMAP34XX_GPT2 #define V_NS16550_CLK 48000000 #define V_OSCK 26000000 @@ -55,7 +55,7 @@ #define CFG_SYS_NS16550_CLK V_NS16550_CLK #define CFG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ 115200 } /* diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 49883ea7a3..35c777b774 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -18,7 +18,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} /* * L4 OSC1 Timer 0 diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 261ae56c1d..29b4b22b39 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -10,7 +10,7 @@ #include /* Eternal oscillator */ -#define CONFIG_SYS_TIMER_RATE 40000000 +#define CFG_SYS_TIMER_RATE 40000000 /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */ @@ -21,7 +21,7 @@ * the last two bytes of the 128 bytes large NVRAM in the * RTC which begin at address 0x20 */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Environment settings */ diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index 7012097276..aa13878177 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -17,7 +17,7 @@ /* * Serial / UART configurations */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_EXTRA_ENV_SETTINGS \ "autoload=no\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 7ef7c5da82..bbbdea6664 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -12,12 +12,12 @@ */ #define PHYS_SDRAM_1 0x0 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ CONFIG_SYS_SPL_MALLOC_SIZE) #endif @@ -27,9 +27,9 @@ * at this address to not overwrite the bootcounter by checking, if the * bootcounter address is located in the internal SRAM. */ -#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ - (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE))) +#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) && \ + (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE))) #endif /* @@ -48,16 +48,16 @@ /* * Cache */ -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS +#define CFG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* * L4 OSC1 Timer 0 */ #ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifndef CONFIG_SYS_TIMER_RATE -#define CONFIG_SYS_TIMER_RATE 25000000 +#define CFG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +#define CFG_SYS_TIMER_COUNTER (CFG_SYS_TIMERBASE + 0x4) +#ifndef CFG_SYS_TIMER_RATE +#define CFG_SYS_TIMER_RATE 25000000 #endif #endif diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 9403e2f430..47089f312d 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -26,8 +26,8 @@ /* * U-Boot run time memory configurations */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CFG_SYS_INIT_RAM_SIZE 0x40000 /* * U-Boot environment configurations diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c628860eac..0a2d581517 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -42,20 +42,20 @@ */ #define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ +#define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ +#undef CFG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR 0xE0000000 +#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ @@ -63,46 +63,46 @@ /* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 +#define CFG_SYS_DDR_CS0_BNDS 0x0000000f +#define CFG_SYS_DDR_CS0_CONFIG 0x80010102 +#define CFG_SYS_DDR_TIMING_0 0x00260802 +#define CFG_SYS_DDR_TIMING_1 0x3935D322 +#define CFG_SYS_DDR_TIMING_2 0x14904CC8 +#define CFG_SYS_DDR_MODE 0x00480432 +#define CFG_SYS_DDR_INTERVAL 0x030C0100 +#define CFG_SYS_DDR_CONFIG_2 0x04400000 +#define CFG_SYS_DDR_CONFIG 0xC3008000 +#define CFG_SYS_DDR_CLK_CONTROL 0x03800000 #define CFG_SYS_SDRAM_SIZE 256 /* in Megs */ /* * Flash on the LocalBus */ -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } +#define CFG_SYS_FLASH0 0xFE000000 +#define CFG_SYS_FLASH1 0xFC000000 +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH1, CFG_SYS_FLASH0 } -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_SYS_LBC_FLASH_BASE CFG_SYS_FLASH1 /* Localbus flash start */ +#define CFG_SYS_FLASH_BASE CFG_SYS_LBC_FLASH_BASE /* start of FLASH */ -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ +#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ +#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_SYS_FPGA_BASE 0xc0000000 +#define CFG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CFG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) +#define CFG_SYS_NAND_BASE (CFG_SYS_FPGA_BASE + 0x70) /* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 +#define CFG_SYS_LIME_BASE 0xc8000000 /* * General PCI @@ -137,7 +137,7 @@ * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 008aa50010..de0f48b79a 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -54,8 +54,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index 3c70856fc7..a5987c5e17 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -15,7 +15,7 @@ */ /* FIXME: This should be loaded from device tree... */ -#define CONFIG_SYS_PL310_BASE 0xa0412000 +#define CFG_SYS_PL310_BASE 0xa0412000 /* Linux does not boot if FDT / initrd is loaded to end of RAM */ #define BOOT_ENV \ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 806323e375..9294d57ca8 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ +#define CFG_SYS_HZ_CLOCK 750000000 /* 750 MHz */ /* Environment */ @@ -22,7 +22,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 51f69010b1..afd7d50428 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -7,13 +7,13 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 221b7abe1a..c8aad47966 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -10,15 +10,15 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 55e70ce925..573a6b1795 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -10,15 +10,15 @@ #include /* For booting Linux, use the first 12MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M +#define CFG_SYS_BOOTMAPSZ SZ_8M + SZ_4M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index c7d6d9368a..14e883a358 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -10,15 +10,15 @@ #include /* For booting Linux, use the first 6MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M +#define CFG_SYS_BOOTMAPSZ SZ_4M + SZ_2M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 /* * Configuration of the external SDRAM memory */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ +#define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) @@ -33,7 +33,7 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ +#define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) /* For splashcreen */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index f959fcf26f..67e6a3a19d 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -11,11 +11,11 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index c8688e9ca7..4786eb001b 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -11,11 +11,11 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ SZ_16M +#define CFG_SYS_BOOTMAPSZ SZ_16M -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index f7fa8c51d8..e667fe6f6a 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -11,11 +11,11 @@ #include /* For booting Linux, use the first 16MB of memory */ -#define CONFIG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) +#define CFG_SYS_BOOTMAPSZ (SZ_16M + SZ_8M) -#define CONFIG_SYS_FLASH_BASE 0x90000000 +#define CFG_SYS_FLASH_BASE 0x90000000 -#define CONFIG_SYS_HZ_CLOCK 1000000 +#define CFG_SYS_HZ_CLOCK 1000000 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index d711149314..c259a61613 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -19,7 +19,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M /* NAND support */ diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h index c51022b40d..ad8126f610 100644 --- a/include/configs/stm32mp13_st_common.h +++ b/include/configs/stm32mp13_st_common.h @@ -15,7 +15,7 @@ #include /* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000, 4000000} diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index f78ce41ed8..c9cfadd9ce 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -19,7 +19,7 @@ * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ SZ_256M +#define CFG_SYS_BOOTMAPSZ SZ_256M /* NAND support */ diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 6bdc286cfc..38b5aa7319 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -14,7 +14,7 @@ #include /* uart with on-board st-link */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ +#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 921600, \ 1000000, 2000000 } diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 234327e017..faff8d6ed6 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -10,7 +10,7 @@ #define CONFIG_HOSTNAME "stmark2" -#define CONFIG_SYS_UART_PORT 0 +#define CFG_SYS_UART_PORT 0 #define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) @@ -34,24 +34,24 @@ "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ "" -#define CONFIG_SYS_SBFHDR_SIZE 0x7 +#define CFG_SYS_SBFHDR_SIZE 0x7 /* Input, PCI, Flexbus, and VCO */ #define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_MBAR 0xFC000000 +#define CFG_SYS_MBAR 0xFC000000 /* * Definitions for initial stack pointer and data area (in internal SRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_INIT_SP_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ +#define CFG_SYS_INIT_RAM_SIZE 0x10000 +#define CFG_SYS_INIT_RAM_CTRL 0x221 +#define CFG_SYS_INIT_SP_OFFSET ((CFG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) +#define CFG_SYS_SBFHDR_DATA_OFFSET (CFG_SYS_INIT_RAM_SIZE - 32) /* * Start addresses for the final memory configuration @@ -61,7 +61,7 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 #define CFG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_DRAM_TEST +#define CFG_SYS_DRAM_TEST #if defined(CONFIG_CF_SBF) #define CONFIG_SERIAL_BOOT @@ -75,7 +75,7 @@ * the maximum mapped by the Linux kernel during initialization ?? */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ +#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ (CFG_SYS_SDRAM_SIZE << 20)) /* Configuration for environment @@ -83,22 +83,22 @@ */ /* Cache Configuration */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ +#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 4) +#define CFG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) +#define CFG_SYS_DCACHE_INV (CF_CACR_DCINVA) +#define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \ CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ +#define CFG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ +#define CFG_SYS_CACHE_DCACR ((CFG_SYS_CACHE_ICACR | \ CF_CACR_DEC | CF_CACR_DDCM_P | \ CF_CACR_DCINVA) & ~CF_CACR_ICINVA) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) +#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \ + CFG_SYS_INIT_RAM_SIZE - 12) #endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index b2dcb6058b..7eadb6d421 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_STV0991_H #define __CONFIG_STV0991_H -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH +#define CFG_SYS_EXCEPTION_VECTORS_HIGH /* ram memory-related information */ #define PHYS_SDRAM_1 0x00000000 @@ -16,8 +16,8 @@ /* user interface */ /* MISC */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0x00190000 /* U-Boot Load Address */ /* Misc configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e1a66f53ff..1677aafad0 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -62,9 +62,9 @@ * is known yet. * H6 has SRAM A1 at 0x00020000. */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +#define CFG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* FIXME: this may be larger on some SoCs */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ #define PHYS_SDRAM_0 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index daa9bbec88..6992689001 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -6,7 +6,7 @@ #define __CONFIG_H /* Timers for fasp(TIMCLK) */ -#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ +#define CFG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */ /* * SDRAM (for initialize) @@ -28,7 +28,7 @@ */ /* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Serial (pl011) */ #define UART_CLK (62500000) @@ -36,8 +36,8 @@ #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CFG_SYS_FLASH_BASE (0x08000000) +#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE} /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 1aba986e1e..baaf94e2dd 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -29,8 +29,8 @@ */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ /* Misc CPU related */ @@ -49,8 +49,8 @@ * leaving the correct space for initial global data structure above * that address while providing maximum stack area below. */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND @@ -136,11 +136,11 @@ 48, 49, 50, 51, 52, 53, 54, 55, \ 56, 57, 58, 59, 60, 61, 62, 63, } -#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CFG_SYS_MASTER_CLOCK 132096000 #define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x202A3F01 -#define CONFIG_SYS_MCKR 0x1300 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10193F05 +#define CFG_SYS_AT91_PLLA 0x202A3F01 +#define CFG_SYS_MCKR 0x1300 +#define CFG_SYS_MCKR_CSS (0x02 | CFG_SYS_MCKR) +#define CFG_SYS_AT91_PLLB 0x10193F05 #endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h index cd1309b3b8..1318f5e5ee 100644 --- a/include/configs/tb100.h +++ b/include/configs/tb100.h @@ -12,8 +12,8 @@ * Memory configuration */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CFG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_DDR_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE SZ_128M /* diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 2d8bde1cee..f6544f6226 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -15,10 +15,10 @@ /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_BOOTMAPSZ 0x10000000 +#define CFG_SYS_BOOTMAPSZ 0x10000000 /* Framebuffer */ #define CONFIG_IMX_HDMI diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7e764b0000..66cf7ae584 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,8 @@ /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif /* Environment */ @@ -42,11 +42,11 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ +#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #ifndef CONFIG_ARM64 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN +#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN /* Defines for SPL */ #endif diff --git a/include/configs/ten64.h b/include/configs/ten64.h index 04772c9e4e..57724719a9 100644 --- a/include/configs/ten64.h +++ b/include/configs/ten64.h @@ -10,7 +10,7 @@ #include "ls1088a_common.h" -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 +#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd" #define SD_BOOTCOMMAND "run distro_bootcmd" diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 1f60b9b497..7becf1eb7c 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -8,7 +8,7 @@ #define MEM_BASE 0x00500000 -#define CONFIG_SYS_LOWMEM_BASE MEM_BASE +#define CFG_SYS_LOWMEM_BASE MEM_BASE /* Link Definitions */ @@ -22,8 +22,8 @@ /* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) #define GICR_BASE (0x801000002000) -#define CONFIG_SYS_SERIAL0 0x87e024000000 -#define CONFIG_SYS_SERIAL1 0x87e025000000 +#define CFG_SYS_SERIAL0 0x87e024000000 +#define CFG_SYS_SERIAL1 0x87e025000000 /* Miscellaneous configurable options */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index e5b23d2a54..03849adb5a 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -74,7 +74,7 @@ /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000 /* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK (48000000) diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 4a7c3d5b44..7b04292d21 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -25,7 +25,7 @@ /** * Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CFG_SYS_TIMERBASE 0x4802E000 /* * NS16550 Configuration diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 00eb329faa..ed17b42920 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_AM335X_COMMON_H__ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 65abb187d9..ea45bba409 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -14,7 +14,7 @@ /* SoC Configuration */ /* Memory Configuration */ -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 #define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #ifdef CONFIG_SYS_MALLOC_F_LEN @@ -44,7 +44,7 @@ #endif /* SPI Configuration */ -#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) /* Keystone net */ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR @@ -176,9 +176,9 @@ #include #include #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) +#define CFG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) +#define CFG_SYS_HZ_CLOCK get_external_clk(sys_clk) #endif #endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index d282c3956e..36a05b6896 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -27,7 +27,7 @@ /* NS16550 Configuration */ #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CFG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ +#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} /* Select serial console configuration */ @@ -46,7 +46,7 @@ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CFG_SYS_TIMERBASE (OMAP34XX_GPT2) /* SPL */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index ce50e35d8d..9a068e2614 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -12,7 +12,7 @@ #define __CONFIG_TI_OMAP4_COMMON_H #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x48242000 +#define CFG_SYS_PL310_BASE 0x48242000 #endif /* Get CPU defs */ @@ -20,7 +20,7 @@ #include /* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE #include diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index c49c177390..37ab2e4467 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -17,7 +17,7 @@ #define __CONFIG_TI_OMAP5_COMMON_H /* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE +#define CFG_SYS_TIMERBASE GPT2_BASE #include diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index a609aa3a2a..0f28690612 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -41,6 +41,6 @@ * Else boot FIT image. */ -#define CONFIG_SYS_FLASH_BASE 0x0C000000 +#define CFG_SYS_FLASH_BASE 0x0C000000 #endif /* __TOTAL_COMPUTE_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 1378981991..24943c8dcf 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -8,8 +8,8 @@ #define CFG_SYS_SDRAM_BASE 0xa0000000 -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CFG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* * Serial Port diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index f8e3a2d017..9c3454add4 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -269,8 +269,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* * All the defines above are for the TQMa6 SoM diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 999130600c..ce897fcd93 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -17,8 +17,8 @@ /* Config on-board RTC */ #define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CFG_SYS_RTC_BUS_NUM 2 +#define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ #define CONFIG_RTC_DS1337_NOOSC diff --git a/include/configs/trats.h b/include/configs/trats.h index 23dcf20c1f..5bd0ca2a96 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -12,7 +12,7 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif /* TRATS has 4 banks of DRAM */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 9c6433ccfd..cef563696b 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -13,7 +13,7 @@ #include #ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_PL310_BASE 0x10502000 +#define CFG_SYS_PL310_BASE 0x10502000 #endif /* TRATS2 has 4 banks of DRAM */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index 4ca8eafc91..fdb420ed87 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -9,7 +9,7 @@ #define _CONFIG_TURRIS_MOX_H #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ +#define CFG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \ 9600, 19200, 38400, 57600, 115200, \ 230400, 460800, 500000, 576000, \ 921600, 1000000, 1152000, 1500000, \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index c1e80b44c8..fac8c1eeb4 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -50,8 +50,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index f73092661a..0e0d5b5b3e 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -58,8 +58,8 @@ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ #define CONFIG_POWER_PFUZE3000 diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index a977271c1e..ab199bc726 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -14,7 +14,7 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_WRITE_SWAPPED_DATA +#define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CFG_SYS_WRITE_SWAPPED_DATA #endif /* __ULCB_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index a57ecffd59..8cd81f1cdd 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -37,7 +37,7 @@ #if !defined(CONFIG_ARM64) /* Time clock 1MHz */ -#define CONFIG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_RATE 1000000 #endif #define CFG_SYS_NAND_REGS_BASE 0x68100000 @@ -162,11 +162,11 @@ LINUXBOOT_ENV_SETTINGS \ BOOTENV -#define CONFIG_SYS_BOOTMAPSZ 0x20000000 +#define CFG_SYS_BOOTMAPSZ 0x20000000 /* only for SPL */ /* subtract sizeof(struct legacy_img_hdr) */ -#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) +#define CFG_SYS_UBOOT_BASE (0x130000 - 0x40) #endif /* __CONFIG_UNIPHIER_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index d2fd23e1d9..657dbadd33 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -17,8 +17,8 @@ #include /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* * Hardware drivers @@ -28,8 +28,8 @@ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 #define CFG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024) -#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 +#define CFG_SYS_INIT_RAM_SIZE (16 * 1024) +#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1 /* NAND flash */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index e944e78603..da68d7a0da 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -61,7 +61,7 @@ #define PHYS_SDRAM_SIZE (gd->ram_size) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index d9e5dfacea..b03159805c 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -10,7 +10,7 @@ /* Onboard devices */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 #define CFG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index b209d97e5e..18ac6b2b08 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -53,8 +53,8 @@ "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x2 " \ "${blkcnt}; fi\0" -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M #if defined(CONFIG_ENV_IS_IN_MMC) /* Environment in eMMC, before config block at the end of 1st "boot sector" */ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 1b9f2ca26f..88839a6e56 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,7 +9,7 @@ #include #include -#define CONFIG_SYS_UBOOT_BASE \ +#define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD @@ -65,8 +65,8 @@ "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \ "${blkcnt}; fi\0" -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_512K /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */ #define CFG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 9a46d50c6f..30c1f5025b 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -254,9 +254,9 @@ BOOTENV #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_FLASH_BASE 0x08000000 +#define CFG_SYS_FLASH_BASE 0x08000000 #else -#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) +#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000) #endif #endif /* __VEXPRESS_AEMV8_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index de571f63ee..e8b6acf8b8 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -112,16 +112,16 @@ #define SCTL_BASE V2M_SYSCTL #define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) +#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) /* PL011 Serial Configuration */ #define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ + (void *)CFG_SYS_SERIAL1} -#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 +#define CFG_SYS_SERIAL0 V2M_UART0 +#define CFG_SYS_SERIAL1 V2M_UART1 /* Miscellaneous configurable options */ #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) @@ -135,7 +135,7 @@ /* additions for new relocation code */ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Basic environment settings */ #define BOOT_TARGET_DEVICES(func) \ @@ -164,7 +164,7 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* FLASH and environment organization */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 +#define CFG_SYS_FLASH_SIZE 0x04000000 /* Timeout values in ticks */ @@ -177,6 +177,6 @@ */ /* Store environment at top of flash */ -#define CONFIG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } +#define CFG_SYS_FLASH_BANKS_LIST { V2M_NOR0, V2M_NOR1 } #endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 7b526f725a..14e6b2bac9 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -124,7 +124,7 @@ #define PHYS_SDRAM_SIZE (128 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h index df0e269b5d..9f72bdde81 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -21,7 +21,7 @@ #define CONFIG_USART_ID 30 /* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c +#define CFG_SYS_TIMER_COUNTER 0xfc06863c /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 @@ -31,7 +31,7 @@ #ifdef CONFIG_CMD_MMC #define ATMEL_BASE_MMCI 0xfc000000 -#define CONFIG_SYS_MMC_CLK_OD 500000 +#define CFG_SYS_MMC_CLK_OD 500000 /* For generating MMC partitions */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7555d97c81..ab5cd5cf63 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -24,8 +24,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR diff --git a/include/configs/vocore2.h b/include/configs/vocore2.h index 38b940d35e..43050d61c3 100644 --- a/include/configs/vocore2.h +++ b/include/configs/vocore2.h @@ -9,14 +9,14 @@ /* RAM */ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 +#define CFG_SYS_INIT_SP_OFFSET 0x400000 /* SPL */ -#define CONFIG_SYS_UBOOT_START CONFIG_TEXT_BASE +#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE /* Dummy value */ -#define CONFIG_SYS_UBOOT_BASE 0 +#define CFG_SYS_UBOOT_BASE 0 /* Serial SPL */ #define CFG_SYS_NS16550_CLK 40000000 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 3acef22132..23027b1d3d 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -90,8 +90,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment organization */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index cba215c379..56c90aa103 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -85,8 +85,8 @@ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* environment organization */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 32555c9b6a..065006f912 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -42,7 +42,7 @@ */ /* driver configuration */ -#define CONFIG_SYS_MAX_NAND_CHIPS 1 +#define CFG_SYS_MAX_NAND_CHIPS 1 #define CFG_SYS_NAND_BASE MLC_NAND_BASE /* diff --git a/include/configs/x530.h b/include/configs/x530.h index a0162cab21..dee87cb773 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -13,7 +13,7 @@ /* * NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK CONFIG_SYS_TCLK +#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK #if !defined(CONFIG_DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f76c1f8be0..3e17b53dde 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -30,7 +30,7 @@ * CPU Features */ -#define CONFIG_SYS_STACK_SIZE (32 * 1024) +#define CFG_SYS_STACK_SIZE (32 * 1024) /*----------------------------------------------------------------------- * Environment configuration diff --git a/include/configs/xea.h b/include/configs/xea.h index 87f628d4ab..b432ab2dc8 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -16,9 +16,9 @@ /* SPL */ -#define CONFIG_SYS_SPI_KERNEL_OFFS SZ_1M -#define CONFIG_SYS_SPI_ARGS_OFFS SZ_512K -#define CONFIG_SYS_SPI_ARGS_SIZE SZ_32K +#define CFG_SYS_SPI_KERNEL_OFFS SZ_1M +#define CFG_SYS_SPI_ARGS_OFFS SZ_512K +#define CFG_SYS_SPI_ARGS_SIZE SZ_32K /* Memory configuration */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 8caf5394ed..ee3130ed32 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -15,7 +15,7 @@ #define GICR_BASE 0xF9080000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } /* GUID for capsule updatable firmware image */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 0ccd38b7e6..7d77189693 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -20,7 +20,7 @@ #define GICR_BASE 0xF9060000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } #if defined(CONFIG_CMD_DFU) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 60f007a10f..efe241df97 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -15,7 +15,7 @@ #define GICC_BASE 0xF9020000 /* Serial setup */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } /* GUIDs for capsule updatable firmware images */ @@ -192,9 +192,9 @@ #endif #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 -# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 -# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 +# define CFG_SYS_SPI_KERNEL_OFFS 0x80000 +# define CFG_SYS_SPI_ARGS_OFFS 0xa0000 +# define CFG_SYS_SPI_ARGS_SIZE 0xa0000 #endif /* u-boot is like dtb */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index b6bc402a7e..3a7b7e03d6 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -10,13 +10,13 @@ /* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /* Boot configuration */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Extend size of kernel image for uncompression */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 613ed95955..3e604894ad 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -22,8 +22,8 @@ #define PHYS_SDRAM_SIZE (128 << 20) #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Environment is in stored in the eMMC boot partition */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 8739bb2484..9201dac7ab 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -21,12 +21,12 @@ /*===================*/ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_SYS_MEMORY_BASE \ +#define CFG_SYS_MEMORY_BASE \ (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) -#define CONFIG_SYS_IO_BASE 0xf0000000 +#define CFG_SYS_IO_BASE 0xf0000000 #else -#define CONFIG_SYS_MEMORY_BASE 0x60000000 -#define CONFIG_SYS_IO_BASE 0x90000000 +#define CFG_SYS_MEMORY_BASE 0x60000000 +#define CFG_SYS_IO_BASE 0x90000000 #define CONFIG_MAX_MEM_MAPPED 0x10000000 #endif @@ -100,16 +100,16 @@ */ /* FPGA core clock frequency in Hz (also input to UART) */ -#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ +#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ /* * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): * Bits 0..5 set the lower 6 bits of the default ethernet MAC. * Bit 6 is reserved for future use by Tensilica. - * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to + * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to * the base of flash * (when on/1) or to the base of RAM (when off/0). */ -#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) +#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ #define FPGAREG_MAC_WIDTH 6 #define FPGAREG_MAC_MASK 0x3f @@ -120,8 +120,8 @@ #define FPGAREG_BOOT_FLASH (1<cspr_cs[i].cspr_ext)) diff --git a/include/i2c.h b/include/i2c.h index c07e60b04b..51390f8fd8 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -633,10 +633,10 @@ void i2c_early_init_f(void); */ #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */ -#if !defined(CONFIG_SYS_I2C_MAX_HOPS) +#if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ #define CONFIG_SYS_I2C_DIRECT_BUS 1 -#define CONFIG_SYS_I2C_MAX_HOPS 0 +#define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ @@ -644,8 +644,8 @@ void i2c_early_init_f(void); #endif /* define the I2C bus number for RTC and DTT if not already done */ -#if !defined(CONFIG_SYS_RTC_BUS_NUM) -#define CONFIG_SYS_RTC_BUS_NUM 0 +#if !defined(CFG_SYS_RTC_BUS_NUM) +#define CFG_SYS_RTC_BUS_NUM 0 #endif struct i2c_adapter { @@ -705,7 +705,7 @@ struct i2c_next_hop { struct i2c_bus_hose { int adapter; - struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS]; + struct i2c_next_hop next_hop[CFG_SYS_I2C_MAX_HOPS]; }; #define I2C_NULL_HOP {{-1, ""}, 0, 0} extern struct i2c_bus_hose i2c_bus[]; @@ -931,12 +931,12 @@ unsigned int i2c_get_bus_speed(void); * completely to new multibus support. */ #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) -# if !defined(CONFIG_SYS_MAX_I2C_BUS) -# define CONFIG_SYS_MAX_I2C_BUS 2 +# if !defined(CFG_SYS_MAX_I2C_BUS) +# define CFG_SYS_MAX_I2C_BUS 2 # endif # define I2C_MULTI_BUS 1 #else -# define CONFIG_SYS_MAX_I2C_BUS 1 +# define CFG_SYS_MAX_I2C_BUS 1 # define I2C_MULTI_BUS 0 #endif diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 053b68a10a..636734dd3c 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -26,38 +26,38 @@ * Define default values for some CCSR macros to make header files cleaner* * * To completely disable CCSR relocation in a board header file, define - * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS - * to a value that is the same as CONFIG_SYS_CCSRBAR. + * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS + * to a value that is the same as CFG_SYS_CCSRBAR. */ -#ifdef CONFIG_SYS_CCSRBAR_PHYS -#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ -CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." +#ifdef CFG_SYS_CCSRBAR_PHYS +#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \ +CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead." #endif #if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE) -#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH -#undef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#undef CFG_SYS_CCSRBAR_PHYS_HIGH +#undef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif -#ifndef CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR +#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH +#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf #else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 +#define CFG_SYS_CCSRBAR_PHYS_HIGH 0 #endif #endif -#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT +#ifndef CFG_SYS_CCSRBAR_PHYS_LOW +#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT #endif -#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ - CONFIG_SYS_CCSRBAR_PHYS_LOW) +#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ + CFG_SYS_CCSRBAR_PHYS_LOW) #endif /* __MPC85xx_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fe4748032..ea8d17d557 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -16,9 +16,9 @@ * platform register addresses */ -#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) +#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) +#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) +#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008) /* * l2cr values. Look in config_.h for the actual setup diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 1321da1910..52cd1c4dbc 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -147,8 +147,8 @@ struct cfi_pri_hdr { u8 minor_version; } __attribute__((packed)); -#ifndef CONFIG_SYS_FLASH_BANKS_LIST -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#ifndef CFG_SYS_FLASH_BANKS_LIST +#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif /* diff --git a/include/mvebu_mmc.h b/include/mvebu_mmc.h index e75c3fa328..0f6f5c23de 100644 --- a/include/mvebu_mmc.h +++ b/include/mvebu_mmc.h @@ -21,7 +21,7 @@ #define MVEBU_MMC_CLOCKRATE_MAX 50000000 #define MVEBU_MMC_BASE_DIV_MAX 0x7ff -#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK +#define MVEBU_MMC_BASE_FAST_CLOCK CFG_SYS_TCLK #define MVEBU_MMC_BASE_FAST_CLK_100 100000000 #define MVEBU_MMC_BASE_FAST_CLK_200 200000000 diff --git a/include/post.h b/include/post.h index ec03556e91..867a66f300 100644 --- a/include/post.h +++ b/include/post.h @@ -142,7 +142,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_RTC 0x00000001 #define CONFIG_SYS_POST_WATCHDOG 0x00000002 -#define CONFIG_SYS_POST_MEMORY 0x00000004 +#define CFG_SYS_POST_MEMORY 0x00000004 #define CONFIG_SYS_POST_CPU 0x00000008 #define CONFIG_SYS_POST_I2C 0x00000010 #define CONFIG_SYS_POST_CACHE 0x00000020 @@ -163,7 +163,7 @@ extern int memory_post_test(int flags); #define CONFIG_SYS_POST_CODEC 0x00200000 #define CONFIG_SYS_POST_COPROC 0x00400000 #define CONFIG_SYS_POST_FLASH 0x00800000 -#define CONFIG_SYS_POST_MEM_REGIONS 0x01000000 +#define CFG_SYS_POST_MEM_REGIONS 0x01000000 #endif /* CONFIG_POST */ diff --git a/include/spl.h b/include/spl.h index 3eb27de616..fb8c279d72 100644 --- a/include/spl.h +++ b/include/spl.h @@ -470,7 +470,7 @@ void spl_set_bd(void); * spl_set_header_raw_uboot() - Set up a standard SPL image structure * * This sets up the given spl_image which the standard values obtained from - * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START, + * config options: CONFIG_SYS_MONITOR_LEN, CFG_SYS_UBOOT_START, * CONFIG_TEXT_BASE. * * @spl_image: Image description to set up diff --git a/include/system-constants.h b/include/system-constants.h index 07c3505e8f..0d6b71b35a 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -12,10 +12,10 @@ #define SYS_INIT_SP_ADDR CONFIG_CUSTOM_SYS_INIT_SP_ADDR #else #ifdef CONFIG_MIPS -#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET) +#define SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + CFG_SYS_INIT_SP_OFFSET) #else #define SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #endif #endif diff --git a/include/tca642x.h b/include/tca642x.h index bda86c1ed8..c0a3cef5bd 100644 --- a/include/tca642x.h +++ b/include/tca642x.h @@ -41,13 +41,13 @@ enum { #define TCA642X_DIR_IN 1 /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_ADDR -#define CONFIG_SYS_I2C_TCA642X_ADDR (~0) +#ifndef CFG_SYS_I2C_TCA642X_ADDR +#define CFG_SYS_I2C_TCA642X_ADDR (~0) #endif /* Default to an address that hopefully won't corrupt other i2c devices */ -#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM (0) +#ifndef CFG_SYS_I2C_TCA642X_BUS_NUM +#define CFG_SYS_I2C_TCA642X_BUS_NUM (0) #endif struct tca642x_bank_info { diff --git a/include/tsec.h b/include/tsec.h index 72f34851ad..de279b2117 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -124,8 +124,8 @@ #define RCTRL_PROM 0x00000008 -#ifndef CONFIG_SYS_TBIPA_VALUE -# define CONFIG_SYS_TBIPA_VALUE 0x1f +#ifndef CFG_SYS_TBIPA_VALUE +# define CFG_SYS_TBIPA_VALUE 0x1f #endif #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN diff --git a/lib/time.c b/lib/time.c index f3aaf472d1..82350260ea 100644 --- a/lib/time.c +++ b/lib/time.c @@ -25,21 +25,21 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SYS_TIMER_RATE +#ifdef CFG_SYS_TIMER_RATE /* Returns tick rate in ticks per second */ ulong notrace get_tbclk(void) { - return CONFIG_SYS_TIMER_RATE; + return CFG_SYS_TIMER_RATE; } #endif -#ifdef CONFIG_SYS_TIMER_COUNTER +#ifdef CFG_SYS_TIMER_COUNTER unsigned long notrace timer_read_counter(void) { #ifdef CONFIG_SYS_TIMER_COUNTS_DOWN - return ~readl(CONFIG_SYS_TIMER_COUNTER); + return ~readl(CFG_SYS_TIMER_COUNTER); #else - return readl(CONFIG_SYS_TIMER_COUNTER); + return readl(CFG_SYS_TIMER_COUNTER); #endif } @@ -47,8 +47,8 @@ ulong timer_get_boot_us(void) { ulong count = timer_read_counter(); -#ifdef CONFIG_SYS_TIMER_RATE - const ulong timer_rate = CONFIG_SYS_TIMER_RATE; +#ifdef CFG_SYS_TIMER_RATE + const ulong timer_rate = CFG_SYS_TIMER_RATE; if (timer_rate == 1000000) return count; diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 8deac75ebb..71dad7b8c0 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -138,7 +138,7 @@ #include #include -#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS) +#if CONFIG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) DECLARE_GLOBAL_DATA_PTR; @@ -535,4 +535,4 @@ int memory_post_test(int flags) return ret; } -#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */ +#endif /* CONFIG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ diff --git a/post/tests.c b/post/tests.c index 5c019b643d..fc36e738f7 100644 --- a/post/tests.c +++ b/post/tests.c @@ -109,7 +109,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_RTC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEMORY +#if CONFIG_POST & CFG_SYS_POST_MEMORY { "Memory test", "memory", @@ -118,7 +118,7 @@ struct post_test post_list[] = &memory_post_test, NULL, NULL, - CONFIG_SYS_POST_MEMORY + CFG_SYS_POST_MEMORY }, #endif #if CONFIG_POST & CONFIG_SYS_POST_CPU @@ -286,7 +286,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_FLASH }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS +#if CONFIG_POST & CFG_SYS_POST_MEM_REGIONS { "Memory regions test", "mem_regions", @@ -295,7 +295,7 @@ struct post_test post_list[] = &memory_regions_post_test, NULL, NULL, - CONFIG_SYS_POST_MEM_REGIONS + CFG_SYS_POST_MEM_REGIONS }, #endif }; diff --git a/tools/envcrc.c b/tools/envcrc.c index bce7790247..a021c785ae 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -23,13 +23,13 @@ #if defined(CONFIG_ENV_IS_IN_FLASH) # ifndef CONFIG_ENV_ADDR -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +# define CONFIG_ENV_ADDR (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif # ifndef CONFIG_ENV_OFFSET -# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CFG_SYS_FLASH_BASE) # endif # if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND) -# define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND) +# define CONFIG_ENV_ADDR_REDUND (CFG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND) # endif # ifndef CONFIG_ENV_SIZE # define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE From 518c5dfab0e378891088edce07bde732882b8f1f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:08 -0500 Subject: [PATCH 028/424] power: pmic: Guard non-DM_PMIC drivers with a check for POWER_LEGACY As we have more legacy PMIC drivers to move to Kconfig, guard them all with POWER_LEGACY or SPL_POWER_LEGACY. Do the same kind of check for building the drivers too. This also means that we need to resort the list slightly in the Makefile. Cc: Jaehoon Chung Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- drivers/power/pmic/Kconfig | 5 ++++- drivers/power/pmic/Makefile | 10 ++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 628d3a94bc..d30bb4d4e9 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -393,10 +393,13 @@ config PMIC_TPS65217 only, and you can enable the regulator/charger drivers separately if required. +if POWER_LEGACY || SPL_POWER_LEGACY + config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" - depends on !DM_PMIC ---help--- The MC34VR500 is used in conjunction with the FSL T1 and LS1 series SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed via an I2C interface. + +endif diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 58c6507c58..e78dc1e205 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -30,17 +30,19 @@ obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o +obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o +obj-$(CONFIG_PMIC_TPS65219) += tps65219.o +obj-$(CONFIG_PMIC_TPS65941) += tps65941.o +ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o -obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o -obj-$(CONFIG_POWER_TPS65218) += pmic_tps62362.o +obj-$(CONFIG_POWER_TPS62362) += pmic_tps62362.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o -obj-$(CONFIG_PMIC_TPS65941) += tps65941.o -obj-$(CONFIG_PMIC_TPS65219) += tps65219.o +endif From 2a776c79dbfadeac094cd420d2d7b22937aac0c9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:09 -0500 Subject: [PATCH 029/424] Convert CONFIG_FSL_CADMUS to Kconfig This converts the following to Kconfig: CONFIG_FSL_CADMUS Signed-off-by: Tom Rini --- board/freescale/mpc8548cds/Kconfig | 3 +++ include/configs/MPC8548CDS.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig index bd9153bc0d..723ead51e5 100644 --- a/board/freescale/mpc8548cds/Kconfig +++ b/board/freescale/mpc8548cds/Kconfig @@ -3,6 +3,9 @@ if TARGET_MPC8548CDS config PCI1 def_bool y +config FSL_CADMUS + def_bool y + config SYS_BOARD default "mpc8548cds" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index ff02c2cd84..e41b8e0843 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -217,8 +217,6 @@ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 */ -#define CONFIG_FSL_CADMUS - #define CADMUS_BASE_ADDR 0xf8000000 #ifdef CONFIG_PHYS_64BIT #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull From 345c09de5e7ca2c015faaf58c1e6c6b15883a63b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:10 -0500 Subject: [PATCH 030/424] Convert CONFIG_FSL_DEVICE_DISABLE to Kconfig This converts the following to Kconfig: CONFIG_FSL_DEVICE_DISABLE Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++ include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atsn.h | 2 -- include/configs/ls1021atwr.h | 2 -- 6 files changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e75a895e00..369e68b819 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,5 +1,6 @@ config ARCH_LS1021A bool + select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR @@ -30,6 +31,9 @@ config ARCH_LS1021A menu "LS102xA architecture" depends on ARCH_LS1021A +config FSL_DEVICE_DISABLE + bool + config LS1_DEEP_SLEEP bool "Deep sleep" diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7307c495c3..6ccb4f07e3 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -168,7 +168,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE /* * Miscellaneous configurable options diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index b058308ecd..3063635592 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -95,8 +95,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5494b71e2b..137d459c29 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -279,8 +279,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index bc9eac700e..052a15658d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -70,8 +70,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f1ccb5fc08..f39c7c0884 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -160,8 +160,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_FSL_DEVICE_DISABLE - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ From 060613f119837fafc7c90a5dcc1aa1bf81ff319b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:11 -0500 Subject: [PATCH 031/424] Convert CONFIG_FSL_IIM to Kconfig This converts the following to Kconfig: CONFIG_FSL_IIM Signed-off-by: Tom Rini --- configs/m53menlo_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/usbarmory_defconfig | 1 + doc/README.fsl_iim | 2 +- drivers/misc/Kconfig | 4 ++++ include/configs/m53menlo.h | 3 --- include/configs/mx51evk.h | 1 - include/configs/mx53ppd.h | 2 -- include/configs/usbarmory.h | 3 --- 10 files changed, 9 insertions(+), 10 deletions(-) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index b4ada56a36..a5760242be 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -80,6 +80,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 89597c0574..d76ebe8fd2 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" CONFIG_ARP_TIMEOUT=200 +CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PHYLIB=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index 328f546c5b..ed4ebbbe3c 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -52,6 +52,7 @@ CONFIG_SYS_I2C_MXC=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y +CONFIG_FSL_IIM=y CONFIG_I2C_EEPROM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index 510e215bff..ed2bcc69fc 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_IIM=y CONFIG_FSL_ESDHC_IMX=y CONFIG_MTD=y CONFIG_PINCTRL=y diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim index e087f5e0e4..78d3cb8b3e 100644 --- a/doc/README.fsl_iim +++ b/doc/README.fsl_iim @@ -45,4 +45,4 @@ Fuse operations: Configuration: CONFIG_FSL_IIM - Define this to enable the fsl_iim driver. + Enable this to enable the fsl_iim driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index a6da6e215d..fb3bbb3b91 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -267,6 +267,10 @@ config DS4510 and a configurable timer for the supervisor function. The device is connected over I2C. +config FSL_IIM + bool "Enable FSL IC Identification Module (IIM) driver" + depends on ARCH_MX31 || ARCH_MX5 + config FSL_SEC_MON bool "Enable FSL SEC_MON Driver" help diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index f87bbf7ccf..eca86a9451 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -80,9 +80,6 @@ #define CFG_SYS_LDB_CLOCK 33260000 #define CONFIG_IMX_VIDEO_SKIP -/* IIM Fuses */ -#define CONFIG_FSL_IIM - /* Watchdog */ /* diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3c99b70a2b..6d9b954587 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -17,7 +17,6 @@ /* * Hardware drivers */ -#define CONFIG_FSL_IIM #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 7160654eb3..913bc1996d 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -102,8 +102,6 @@ /* FLASH and environment organization */ -#define CONFIG_FSL_IIM - /* Backlight Control */ #define CONFIG_IMX6_PWM_PER_CLK 66666000 diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index da68d7a0da..a2bc3cd23a 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -27,9 +27,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Fuse */ -#define CONFIG_FSL_IIM - /* Linux boot */ #define CONFIG_HOSTNAME "usbarmory" From d58d0663cbaa6a1ff9a71cafe777a2346ef24dc6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:12 -0500 Subject: [PATCH 032/424] Convert CONFIG_FSL_LBC to Kconfig This converts the following to Kconfig: CONFIG_FSL_LBC Signed-off-by: Tom Rini --- arch/powerpc/Kconfig | 4 ++++ arch/powerpc/include/asm/config.h | 8 -------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index cf93a7b1da..0fc4ceda00 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -34,6 +34,10 @@ config MPC8xx endchoice +config FSL_LBC + def_bool y + depends on (MPC85xx || MPC83xx) && !FSL_IFC + config HIGH_BATS bool "Enable high BAT registers" help diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index b0ad7d7aa7..983c6f70cf 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -32,14 +32,6 @@ #define BPTR_VIRT_ADDR 0xfffff000 #endif -/* Since so many PPC SOCs have a semi-common LBC, define this here */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ - defined(CONFIG_MPC83xx) -#if !defined(CONFIG_FSL_IFC) -#define CONFIG_FSL_LBC -#endif -#endif - /* The TSEC driver uses the PHYLIB infrastructure */ #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) #include From 5cafaedeac41c966b8f554182944d9dc0b531190 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:13 -0500 Subject: [PATCH 033/424] Convert CONFIG_FSL_SERDES to Kconfig This converts the following to Kconfig: CONFIG_FSL_SERDES Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/Kconfig | 4 ++++ arch/powerpc/cpu/mpc83xx/serdes.c | 4 ---- configs/MPC837XERDB_defconfig | 1 + include/configs/MPC837XERDB.h | 1 - 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index ec3405e967..563f52c5fd 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -196,6 +196,10 @@ config 83XX_PCICLK config FSL_ELBC bool +config FSL_SERDES + bool "SerDes initialization" + depends on !MPC83XX_SERDES + source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" diff --git a/arch/powerpc/cpu/mpc83xx/serdes.c b/arch/powerpc/cpu/mpc83xx/serdes.c index bb963ee5e2..d4848b2ec4 100644 --- a/arch/powerpc/cpu/mpc83xx/serdes.c +++ b/arch/powerpc/cpu/mpc83xx/serdes.c @@ -8,8 +8,6 @@ * Author: Li Yang */ -#ifndef CONFIG_MPC83XX_SERDES - #include #include #include @@ -151,5 +149,3 @@ void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) tmp |= FSL_SRDSRSTCTL_RST; out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp); } - -#endif /* !CONFIG_MPC83XX_SERDES */ diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 7054333d73..e6289fe104 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -147,6 +147,7 @@ CONFIG_ACR_RPTCNT_4=y CONFIG_SPCR_TSECEP_3=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_CLKDIV_8=y +CONFIG_FSL_SERDES=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 85c080cf27..717320c34a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -160,7 +160,6 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ -#define CONFIG_FSL_SERDES #define CONFIG_FSL_SERDES1 0xe3000 #define CONFIG_FSL_SERDES2 0xe3100 From 022dc9e505ea70ea5e5c81f78a629a6016d4fd9d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:14 -0500 Subject: [PATCH 034/424] Convert CONFIG_HIKEY_GPIO et al to Kconfig This converts the following to Kconfig: CONFIG_HIKEY_GPIO CONFIG_TCA642X Signed-off-by: Tom Rini --- configs/hikey_defconfig | 1 + configs/omap5_uevm_defconfig | 2 +- drivers/gpio/Kconfig | 9 +++++++++ include/configs/hikey.h | 2 -- include/configs/omap5_uevm.h | 1 - 5 files changed, 11 insertions(+), 4 deletions(-) diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 9eec928184..d023653815 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -30,6 +30,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_HIKEY_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_POWER_LEGACY=y diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index d12199766a..91878c11ed 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -47,7 +47,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SCSI_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y -CONFIG_CMD_TCA642X=y +CONFIG_TCA642X=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ff87fbfb39..e007b38fac 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -169,6 +169,10 @@ config FXL6408_GPIO This driver supports the Fairchild FXL6408 device. FXL6408 is a fully configurable 8-bit I2C-controlled GPIO expander. +config HIKEY_GPIO + bool "HI6220 GPIO driver" + depends on DM_GPIO + config INTEL_BROADWELL_GPIO bool "Intel Broadwell GPIO driver" depends on DM @@ -374,8 +378,13 @@ config XILINX_GPIO help This config enable the Xilinx GPIO driver for Microblaze. +config TCA642X + bool "TCA642x legacy GPIO driver" + config CMD_TCA642X bool "tca642x - Command to access tca642x state" + depends on TCA642X + default y help DEPRECATED - This needs conversion to driver model diff --git a/include/configs/hikey.h b/include/configs/hikey.h index c5ef2f99b0..eefdbd6ed1 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -32,8 +32,6 @@ #define GICD_BASE 0xf6801000 #define GICC_BASE 0xf6802000 -#define CONFIG_HIKEY_GPIO - /* Initial environment variables */ /* diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 1634db8606..d7fa2d4391 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -36,7 +36,6 @@ #define CONFIG_HSMMC2_8BIT /* Required support for the TCA642X GPIO we have on the uEVM */ -#define CONFIG_TCA642X #define CFG_SYS_I2C_TCA642X_BUS_NUM 4 #define CFG_SYS_I2C_TCA642X_ADDR 0x22 From d9feb83505b3a7c06487a1748db4f20ad189e33a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:15 -0500 Subject: [PATCH 035/424] Convert CONFIG_POWER_LTC3676 et al to Kconfig This converts the following to Kconfig: CONFIG_POWER_FSL CONFIG_POWER_FSL_MC13892 CONFIG_POWER_HI6553 CONFIG_POWER_LTC3676 CONFIG_POWER_PFUZE100 CONFIG_POWER_PFUZE3000 CONFIG_POWER_SPI CONFIG_POWER_TPS65090_EC CONFIG_POWER_TPS65218 CONFIG_POWER_TPS65910 Signed-off-by: Tom Rini --- board/freescale/common/Makefile | 2 ++ configs/am335x_baltos_defconfig | 1 + configs/am335x_boneblack_vboot_defconfig | 1 + configs/am335x_evm_defconfig | 1 + configs/am335x_evm_spiboot_defconfig | 1 + configs/am335x_hs_evm_defconfig | 1 + configs/am335x_hs_evm_uart_defconfig | 1 + configs/am335x_sl50_defconfig | 1 + configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_qspiboot_defconfig | 2 ++ configs/am43xx_evm_rtconly_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am43xx_hs_evm_qspi_defconfig | 2 ++ configs/cl-som-imx7_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ configs/hikey_defconfig | 1 + configs/imx8mq_evk_defconfig | 1 + configs/kontron_pitx_imx8m_defconfig | 1 + configs/mx51evk_defconfig | 2 ++ configs/mx53loco_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/novena_defconfig | 1 + configs/pcm051_rev3_defconfig | 1 + configs/phycore-am335x-r2-regor_defconfig | 1 + configs/phycore-am335x-r2-wega_defconfig | 1 + configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/vining_2000_defconfig | 1 + drivers/power/Kconfig | 21 ++++++++++++++++++ drivers/power/pmic/Kconfig | 27 +++++++++++++++++++++++ drivers/power/pmic/Makefile | 7 +++--- drivers/power/power_fsl.c | 2 -- include/configs/am335x_evm.h | 3 --- include/configs/am335x_sl50.h | 7 ------ include/configs/am43xx_evm.h | 8 ------- include/configs/baltos.h | 3 --- include/configs/cl-som-imx7.h | 1 - include/configs/cm_t43.h | 3 --- include/configs/el6x_common.h | 1 - include/configs/gw_ventana.h | 2 -- include/configs/hikey.h | 2 -- include/configs/imx8mq_evk.h | 1 - include/configs/kontron_pitx_imx8m.h | 1 - include/configs/mx51evk.h | 2 -- include/configs/mx53loco.h | 2 -- include/configs/mx6sabreauto.h | 1 - include/configs/mx6sabresd.h | 1 - include/configs/novena.h | 1 - include/configs/peach-pi.h | 2 -- include/configs/phycore_am335x_r2.h | 2 -- include/configs/pico-imx7d.h | 1 - include/configs/tqma6.h | 1 - include/configs/udoo_neo.h | 1 - include/configs/vining_2000.h | 1 - 64 files changed, 101 insertions(+), 52 deletions(-) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 377c6aa077..cc1371867d 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -61,7 +61,9 @@ obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_ZM7300) += zm7300.o +ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_PFUZE100) += pfuze.o +endif obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o ifneq (,$(filter $(SOC), imx8ulp imx9)) diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index bd23b71b09..9976cee81f 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -79,6 +79,7 @@ CONFIG_PHY_SMSC=y CONFIG_DM_MDIO=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index 66b7fb6e06..442783a9d0 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -76,6 +76,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index f73123e0b7..78e63c9175 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -102,6 +102,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 7f422010c1..335a43d87b 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -93,6 +93,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index 8d3a4548d9..5dc9ba98fd 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -80,6 +80,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index 7080b14c46..68513c1b6a 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -81,6 +81,7 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_DM_PMIC=y # CONFIG_SPL_DM_PMIC is not set CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 65b20550c0..673824cfec 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -75,6 +75,7 @@ CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_PMIC_TPS65217=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 2dfd936057..2faf1322f9 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -88,6 +88,8 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_OMAP_USB2_PHY=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index fc6cad59cf..9c90924020 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -53,6 +53,8 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 357da192b8..4241070930 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -72,6 +72,8 @@ CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 0e58221c82..91270d032b 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -91,6 +91,8 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_OMAP_USB2_PHY=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 2b5a7fb259..b6b74af735 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -86,6 +86,8 @@ CONFIG_DRIVER_TI_CPSW=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_OMAP_USB2_PHY=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index 08cac404c6..03e46dde0f 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -55,6 +55,8 @@ CONFIG_SF_DEFAULT_SPEED=48000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_POWER_TPS65218=y +CONFIG_POWER_TPS62362=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_TI_QSPI=y diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index f3ee559d21..3571dba6d2 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -95,6 +95,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_DM_REGULATOR=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 0a5ce2046f..867ca30320 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -95,6 +95,7 @@ CONFIG_PHY_ATHEROS=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_TPS65218=y CONFIG_POWER_I2C=y CONFIG_DM_SERIAL=y CONFIG_SPI=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index cabe09e6d3..ce81b558ee 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -119,6 +119,8 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_LTC3676=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index f58abd9c5e..3ef909a1ce 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -123,6 +123,8 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_LTC3676=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index a41b3c4c97..d3d4876658 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -129,6 +129,8 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_LTC3676=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index d023653815..152459ece8 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -34,6 +34,7 @@ CONFIG_HIKEY_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_HI6553=y CONFIG_CONS_INDEX=4 CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 274cdb948d..79a27dedb3 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -88,6 +88,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index d2726b1c20..898a0b45e8 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -95,6 +95,7 @@ CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index d76ebe8fd2..774523bc84 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -54,6 +54,8 @@ CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_POWER_FSL=y +CONFIG_POWER_SPI=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index 193120f71a..08bcd35f07 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -58,6 +58,7 @@ CONFIG_POWER_LEGACY=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_POWER_FSL=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_USB=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 2aa15ce8c6..634473f307 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -95,6 +95,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 766ce0edc4..4f7d370420 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -102,6 +102,7 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_POWER_I2C=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index f6690b4ac8..5f761799a2 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -79,6 +79,7 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 373c609d21..3ed55916d2 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index b6b5274f03..1b31676568 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -83,6 +83,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS=0x20000 CONFIG_DM_SPI_FLASH=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 5012049fed..c5ffb41274 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -84,6 +84,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 CONFIG_DM_SPI_FLASH=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 821357827a..46777e04fd 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 759866ce11..fb354d1cde 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 8631f81f33..35e6f1d549 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -77,6 +77,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_CONS_INDEX=4 CONFIG_MXC_UART=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index a84954d22f..13cc97bb73 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 821357827a..46777e04fd 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index dec4280974..6e92366bef 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -81,6 +81,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_POWER_I2C=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 95428e1993..f62a585b1c 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -57,6 +57,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE3000=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_ANATOP=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 3b5658ddc8..7f84209b65 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -89,6 +89,7 @@ CONFIG_PCIE_IMX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_POWER_LEGACY=y +CONFIG_POWER_PFUZE100=y CONFIG_POWER_I2C=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index bc47cf144d..5dbcde333b 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -430,6 +430,10 @@ config PALMAS_POWER bool "Palmas power support" depends on OMAP54XX +config POWER_FSL + bool "Power control (legacy) for Freescale / NXP platforms" + depends on POWER_LEGACY + config POWER_I2C bool "I2C-based power control for legacy power" depends on POWER_LEGACY @@ -440,6 +444,10 @@ config POWER_I2C Not to be used for new designs and existing ones should be moved to the new PMIC interface based on driver model. +config POWER_SPI + bool "SPI-based power control for legacy power_fsl driver" + depends on POWER_FSL && !POWER_I2C + config SPL_POWER_I2C bool "I2C-based power control for legacy power" depends on SPL_POWER_LEGACY @@ -451,4 +459,17 @@ config SPL_POWER_I2C Not to be used for new designs and existing ones should be moved to the new PMIC interface based on driver model. +choice + prompt "PMIC chip" + default POWER_FSL_MC13892 + depends on POWER_FSL && POWER_I2C + +config POWER_FSL_MC13892 + bool "MC13892" + +config POWER_FSL_MC34704 + bool "MC34704" + +endchoice + endif diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index d30bb4d4e9..d94048db5f 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -393,8 +393,35 @@ config PMIC_TPS65217 only, and you can enable the regulator/charger drivers separately if required. +config POWER_TPS65218 + bool "Enable legacy driver for TPS65218 PMIC" + +config POWER_TPS62362 + bool "Enable legacy driver for TPS62362 PMIC" + +config SPL_POWER_TPS62362 + bool "Enable legacy driver for TPS62362 PMIC in SPL" + default y if POWER_TPS62362 + depends on SPL + +config SPL_POWER_TPS65910 + bool "Enable legacy driver for TPS65910 PMIC in SPL" + depends on SPL + if POWER_LEGACY || SPL_POWER_LEGACY +config POWER_HI6553 + bool "Enable legacy driver for HI6553 PMIC" + +config POWER_LTC3676 + bool "Enable legacy driver for LTC3676 PMIC" + +config POWER_PFUZE100 + bool "Enable legacy driver for PFUZE100 PMIC" + +config POWER_PFUZE3000 + bool "Enable legacy driver for PFUZE3000 PMIC" + config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" ---help--- diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index e78dc1e205..c3180c5820 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o obj-$(CONFIG_PMIC_TPS65219) += tps65219.o obj-$(CONFIG_PMIC_TPS65941) += tps65941.o +obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o @@ -40,9 +41,9 @@ obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o -obj-$(CONFIG_POWER_TPS62362) += pmic_tps62362.o -obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o -obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o obj-$(CONFIG_POWER_HI6553) += pmic_hi6553.o obj-$(CONFIG_POWER_MC34VR500) += pmic_mc34vr500.o endif + +obj-$(CONFIG_$(SPL_)POWER_TPS62362) += pmic_tps62362.o +obj-$(CONFIG_SPL_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 7180b5127a..9bb7e39f2c 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -49,8 +49,6 @@ int pmic_init(unsigned char bus) p->interface = PMIC_I2C; p->hw.i2c.addr = CFG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; -#else -#error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C" #endif return 0; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 69b8b048ce..755f7fae3e 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -165,9 +165,6 @@ #define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 4af9edafca..342a068c85 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -43,11 +43,4 @@ #define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - -/* SPL */ - -/* Network. */ - #endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index bcdff2e98a..7659c1cc06 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -16,14 +16,6 @@ /* NS16550 Configuration */ #define CFG_SYS_NS16550_CLK 48000000 -/* I2C Configuration */ - -/* Power */ -#define CONFIG_POWER_TPS65218 -#define CONFIG_POWER_TPS62362 - -/* SPL defines. */ - /* Enabling L2 Cache */ #define CFG_SYS_PL310_BASE 0x48242000 diff --git a/include/configs/baltos.h b/include/configs/baltos.h index f29729d09b..6f6552e6dc 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -188,9 +188,6 @@ #define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ #define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - /* SPL */ #ifndef CONFIG_NOR_BOOT diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b1f9470d9c..4aaa52f269 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -19,7 +19,6 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define CONFIG_PCA953X diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8ad1cfb5de..fcc17fc6b7 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -28,9 +28,6 @@ 42, 43, 44, 45, 46, 47, 48, 49, \ 50, 51, 52, 53, 54, 55, 56, 57, } -/* Power */ -#define CONFIG_POWER_TPS65218 - /* Enabling L2 Cache */ #define CFG_SYS_PL310_BASE 0x48242000 diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 141f9913e6..89e071c0df 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -17,7 +17,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Commands */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index b855bbc25f..65283afd2a 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -30,9 +30,7 @@ /* * PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676 #define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index eefdbd6ed1..d4280decc9 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -13,8 +13,6 @@ #include -#define CONFIG_POWER_HI6553 - /* Physical Memory Map */ /* CONFIG_TEXT_BASE needs to align with where ATF loads bl33.bin */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index aa29e7884f..688c0bf700 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -18,7 +18,6 @@ #define CONFIG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 2abcb849a2..17c63d8341 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -20,7 +20,6 @@ /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 6d9b954587..d9d76d7c08 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -21,8 +21,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index b52e70c95a..d0107fcc8c 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -22,8 +22,6 @@ #define CONFIG_MXC_USB_FLAGS 0 /* PMIC Controller */ -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 #define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 #define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8 diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 1a2160cce5..f5f95a1bd1 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -37,7 +37,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 0d06b6dc46..78a554d0cc 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -25,7 +25,6 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 6f588f99c3..16a89b97b0 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -50,7 +50,6 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index bfc0011fbf..fb6eb572cf 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -22,8 +22,6 @@ #define CFG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_POWER_TPS65090_EC - /* DRAM Memory Banks */ #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index 43a60825b5..f922491637 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -79,8 +79,6 @@ #define V_OSCK 25000000 /* Clock output from T2 */ #define V_SCLK V_OSCK -#define CONFIG_POWER_TPS65910 - #ifdef CONFIG_MTD_RAW_NAND /* NAND: device related configs */ /* NAND: driver related configs */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 7028264d72..83907b06eb 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -98,7 +98,6 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 /* FLASH and environment organization */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 9c3454add4..7a1ad9544a 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -31,7 +31,6 @@ #define CONFIG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 #endif diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 0e0d5b5b3e..d4c92233ac 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -62,7 +62,6 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index ab5cd5cf63..1a71b300fc 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -31,7 +31,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ From 19b4040df03813ffeb3af77d4f44b1b08013bf77 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:16 -0500 Subject: [PATCH 036/424] Convert CONFIG_HWCONFIG to Kconfig This converts the following to Kconfig: CONFIG_HWCONFIG Signed-off-by: Tom Rini --- common/Kconfig | 4 ++++ configs/MCR3000_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/da850evm_direct_nor_defconfig | 1 + configs/da850evm_nand_defconfig | 1 + configs/gazerbeam_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kontron_sl28_defconfig | 1 + configs/legoev3_defconfig | 1 + configs/socrates_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + doc/README.hwconfig | 3 --- include/configs/MPC837XERDB.h | 2 -- include/configs/MPC8548CDS.h | 2 -- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 2 -- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 2 -- include/configs/da850evm.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 2 -- include/configs/legoev3.h | 1 - include/configs/ls1012a_common.h | 1 - include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atsn.h | 1 - include/configs/ls1021atwr.h | 1 - include/configs/ls1028a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/qemu-ppce500.h | 2 -- 47 files changed, 22 insertions(+), 40 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index 21434c5cf1..053e93eb1a 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -676,6 +676,10 @@ config CLOCKS bool "Call set_cpu_clk_info" depends on ARM +config HWCONFIG + bool "hwconfig infrastructure" + default y if PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 + config SYS_FSL_CLK bool depends on ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3 || \ diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 6c41d7c88d..d8d6417d21 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -29,6 +29,7 @@ CONFIG_AUTOBOOT_DELAY_STR="root" CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run flashboot" CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y # CONFIG_AUTO_COMPLETE is not set diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index ec80edf293..9b1b619817 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -35,6 +35,7 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_SPL_PAD_TO=0x8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 01cdc4f784..9332c8cb3f 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -29,6 +29,7 @@ CONFIG_BOOTCOMMAND="run envboot; run mmcboot; " # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=1050 diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index a7aaf46ea5..f979c45a3b 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_SPL_PAD_TO=0x8000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0xc0000000 diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 3974e3d2bd..d2946971b4 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -131,6 +131,7 @@ CONFIG_DISPLAY_CPUINFO=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_CBSIZE=1024 diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index ce81b558ee..b275247d25 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -39,6 +39,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 3ef909a1ce..6169042c7e 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -39,6 +39,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index d3d4876658..6d57ad49a1 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -39,6 +39,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HWCONFIG=y CONFIG_MISC_INIT_R=y CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 298ff16b7e..71d196533f 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -167,6 +167,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 9386f2c512..66ec936cce 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -137,6 +137,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 173306668f..3ba334c240 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -150,6 +150,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c281611dd4..4a02e5e88f 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -130,6 +130,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index e099f74de1..55158864ea 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -150,6 +150,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index f044334e80..9b90ed478c 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -39,6 +39,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 CONFIG_USE_BOOTARGS=y CONFIG_BOARD_LATE_INIT=y +# CONFIG_HWCONFIG is not set CONFIG_PCI_INIT_R=y CONFIG_SPL_MAX_SIZE=0x20000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 98e37f18b4..90c1b94b02 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTCOMMAND="if mmc rescan; then if run loadbootscr; then run bootscript; CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y CONFIG_CLOCKS=y +CONFIG_HWCONFIG=y CONFIG_HUSH_PARSER=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index b89c348e5a..ab52ea26a0 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -23,6 +23,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="echo;echo Welcome on the ABB Socrates Board;echo" CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=276 CONFIG_CMD_REGINFO=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 3b8560f3e0..894a79df59 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -130,6 +130,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 04ce0b3afe..6e66e6ce30 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -152,6 +152,7 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit key to stop autoboot in %2ds\n" CONFIG_AUTOBOOT_STOP_STR=" " CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_HWCONFIG is not set CONFIG_LAST_STAGE_INIT=y CONFIG_MISC_INIT_R=y CONFIG_HUSH_PARSER=y diff --git a/doc/README.hwconfig b/doc/README.hwconfig index b6ddb438cf..5408a22bb6 100644 --- a/doc/README.hwconfig +++ b/doc/README.hwconfig @@ -1,6 +1,3 @@ -To enable this feature just define CONFIG_HWCONFIG in your board -config file. - This implements a simple hwconfig infrastructure: an interface for software knobs to control hardware. diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 717320c34a..2796adbdcd 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -14,8 +14,6 @@ * High Level Configuration Options */ -#define CONFIG_HWCONFIG - /* * On-board devices */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e41b8e0843..75ac269570 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -122,8 +122,6 @@ #define CFG_SYS_FLASH_BANKS_LIST \ {CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS} -#define CONFIG_HWCONFIG /* enable hwconfig */ - /* * SDRAM on the Local Bus */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a8af0a101c..0a1b932e94 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -96,7 +96,6 @@ #endif #endif -#define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1e02855fef..acbd43419f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -132,8 +132,6 @@ #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b5fb0a9b52..e394237daf 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -270,8 +270,6 @@ #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index bee4b704a2..f681a21822 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -248,8 +248,6 @@ #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index be8c30db26..a93e05dd4d 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -246,8 +246,6 @@ #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 795873f423..cf65a0da18 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -211,8 +211,6 @@ #define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3 #endif -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index ffd5645493..b51762264a 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -70,8 +70,6 @@ #define CFG_SYS_FLASH_BASE 0xe0000000 #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 578277fc75..a818a4b39f 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -137,7 +137,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ #define DEFAULT_LINUX_BOOT_ENV \ "loadaddr=0xc0700000\0" \ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 65283afd2a..6c5ca0a520 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -45,7 +45,6 @@ #define CONFIG_IMX_VIDEO_SKIP /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG /* Memory configuration */ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 6ccb4f07e3..bbd2b36c45 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -166,7 +166,6 @@ #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 /* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e152714b11..89c5a24ee9 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -309,8 +309,6 @@ #define CFG_SYS_CS2_FTIM2 SYS_QRIO_FTIM2 #define CFG_SYS_CS2_FTIM3 SYS_QRIO_FTIM3 -#define CONFIG_HWCONFIG - /* define to use L1 as initial stack */ #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 2664982715..abe470fe89 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -48,7 +48,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ #define CONFIG_SETUP_INITRD_TAG #define CONFIG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 7598e54ed2..9e4f949016 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -24,7 +24,6 @@ #define CFG_SYS_NS16550_CLK (get_serial_clock()) -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 3063635592..a968014980 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -92,7 +92,6 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 137d459c29..34d4c2fdec 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -276,7 +276,6 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #ifdef CONFIG_LPUART diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 052a15658d..a5b7364435 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -67,7 +67,6 @@ /* PCIe */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f39c7c0884..059941e713 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -157,7 +157,6 @@ #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 256 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index bdd3951e85..b190bfe9c8 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -34,7 +34,6 @@ /* Physical Memory Map */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index b4048744b1..a3fa92d1ff 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -110,7 +110,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index cac30e4679..4ed5481c3e 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -74,7 +74,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index bacc84f629..57429d4bbe 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -114,7 +114,6 @@ unsigned long long get_qixis_addr(void); /* Physical Memory Map */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_ENV diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 18defd5e5a..e82456fd81 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -107,7 +107,6 @@ unsigned long long get_qixis_addr(void); /* Physical Memory Map */ /* fixme: these need to be checked against the board */ -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index bbee9df404..ff85d966e6 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -84,7 +84,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4) -#define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e8b752785b..eda2d43d0c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -112,7 +112,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_HWCONFIG /* * These can be toggled for performance analysis, otherwise use default. */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index aa9cae017d..d1b20da24a 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -33,8 +33,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_HWCONFIG - #define CFG_SYS_INIT_RAM_ADDR 0x00100000 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 From 98cb4c6b8ed1b1b5d18a3b0af5172b87f9a4b202 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:17 -0500 Subject: [PATCH 037/424] arm920t: Remove unused imx code This code is currently unused, remove it. Signed-off-by: Tom Rini --- arch/arm/cpu/arm920t/imx/Makefile | 8 --- arch/arm/cpu/arm920t/imx/generic.c | 76 ---------------------- arch/arm/cpu/arm920t/imx/speed.c | 86 ------------------------- arch/arm/cpu/arm920t/imx/timer.c | 100 ----------------------------- 4 files changed, 270 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/imx/Makefile delete mode 100644 arch/arm/cpu/arm920t/imx/generic.c delete mode 100644 arch/arm/cpu/arm920t/imx/speed.c delete mode 100644 arch/arm/cpu/arm920t/imx/timer.c diff --git a/arch/arm/cpu/arm920t/imx/Makefile b/arch/arm/cpu/arm920t/imx/Makefile deleted file mode 100644 index 04bc129592..0000000000 --- a/arch/arm/cpu/arm920t/imx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += generic.o -obj-y += speed.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/imx/generic.c b/arch/arm/cpu/arm920t/imx/generic.c deleted file mode 100644 index dbb908ecdc..0000000000 --- a/arch/arm/cpu/arm920t/imx/generic.c +++ /dev/null @@ -1,76 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * arch/arm/mach-imx/generic.c - * - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX machines - */ - -#include - -#ifdef CONFIG_IMX - -#include - -void imx_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; - unsigned int tmp; - - /* Pullup enable */ - if(gpio_mode & GPIO_PUEN) - PUEN(port) |= (1< - */ - - -#include -#if defined (CONFIG_IMX) -#include - -#include - -/* ------------------------------------------------------------------------- */ -/* NOTE: This describes the proper use of this file. - * - * get_board_sys_clk() should be defined as the input frequency of the PLL. - * SH FIXME: 16780000 in our case - * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -ulong get_systemPLLCLK(void) -{ - /* FIXME: We assume System_SEL = 0 here */ - u32 spctl0 = SPCTL0; - u32 mfi = (spctl0 >> 10) & 0xf; - u32 mfn = spctl0 & 0x3f; - u32 mfd = (spctl0 >> 16) & 0x3f; - u32 pd = (spctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); -} - -ulong get_mcuPLLCLK(void) -{ - /* FIXME: We assume System_SEL = 0 here */ - u32 mpctl0 = MPCTL0; - u32 mfi = (mpctl0 >> 10) & 0xf; - u32 mfn = mpctl0 & 0x3f; - u32 mfd = (mpctl0 >> 16) & 0x3f; - u32 pd = (mpctl0 >> 26) & 0xf; - - mfi = mfi<=5 ? 5 : mfi; - - return (2*(get_board_sys_clk()>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); -} - -ulong get_FCLK(void) -{ - return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); -} - -/* return HCLK frequency */ -ulong get_HCLK(void) -{ - u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; - printf("bclkdiv: %d\n", bclkdiv); - return get_systemPLLCLK() / bclkdiv; -} - -/* return BCLK frequency */ -ulong get_BCLK(void) -{ - return get_HCLK(); -} - -ulong get_PERCLK1(void) -{ - return get_systemPLLCLK() / (((PCDR) & 0xf)+1); -} - -ulong get_PERCLK2(void) -{ - return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); -} - -ulong get_PERCLK3(void) -{ - return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); -} - -#endif /* defined (CONFIG_IMX) */ diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c deleted file mode 100644 index 0cd3a03981..0000000000 --- a/arch/arm/cpu/arm920t/imx/timer.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - */ - -#include -#include -#include -#if defined (CONFIG_IMX) - -#include -#include - -int timer_init (void) -{ - int i; - /* setup GP Timer 1 */ - TCTL1 = TCTL_SWR; - for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */ - TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */ - TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */ - - /* Reset the timer */ - TCTL1 &= ~TCTL_TEN; - TCTL1 |= TCTL_TEN; /* Enable timer */ - - return (0); -} - -/* - * timer without interrupts - */ -static ulong get_timer_masked (void) -{ - return TCN1; -} - -ulong get_timer (ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - ulong endtime = get_timer_masked() + usec; - signed long diff; - - do { - ulong now = get_timer_masked (); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} - -/* - * Reset the cpu by setting up the watchdog timer and let him time out - */ -void reset_cpu(void) -{ - /* Disable watchdog and set Time-Out field to 0 */ - WCR = 0x00000000; - - /* Write Service Sequence */ - WSR = 0x00005555; - WSR = 0x0000AAAA; - - /* Enable watchdog */ - WCR = 0x00000001; - - while (1); - /*NOTREACHED*/ -} - -#endif /* defined (CONFIG_IMX) */ From 4eea76574062e9079b6a267229962d6ec0be910a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:18 -0500 Subject: [PATCH 038/424] pwm: imx: Remove unused references to CONFIG_IMX6_PWM_PER_CLK On platforms that use DM_PWM, we do not need to define this value anymore, so remove it from config files. Signed-off-by: Tom Rini --- include/configs/aristainetos2.h | 2 -- include/configs/ge_b1x5v2.h | 3 --- include/configs/ge_bx50v3.h | 2 -- include/configs/mx53ppd.h | 3 --- 4 files changed, 10 deletions(-) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index c1eec5d06c..b1ec8ef269 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -424,8 +424,6 @@ /* check this console not needed, after test remove it */ #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 97fe76cfa8..a8a6229f52 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -12,9 +12,6 @@ #include "mx6_common.h" -/* PWM */ -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - /* UART */ #define CONFIG_MXC_UART_BASE UART3_BASE diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index cbaf03c2a2..705cb763a6 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -106,6 +106,4 @@ #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 913bc1996d..963dd92dd7 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -102,9 +102,6 @@ /* FLASH and environment organization */ -/* Backlight Control */ -#define CONFIG_IMX6_PWM_PER_CLK 66666000 - #define CONFIG_IMX_VIDEO_SKIP #endif /* __CONFIG_H */ From 0ea156ba00f34b3b9c8735d25c8ec7b8dffffb45 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:19 -0500 Subject: [PATCH 039/424] Convert CONFIG_IMX_VIDEO_SKIP et al to Kconfig This converts the following to Kconfig: CONFIG_IMX_VIDEO_SKIP CONFIG_IMX_HDMI Signed-off-by: Tom Rini --- configs/aristainetos2c_defconfig | 1 + configs/aristainetos2ccslb_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/ge_b1x5v2_defconfig | 1 + configs/ge_bx50v3_defconfig | 2 ++ configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ configs/imx6dl_icore_nand_defconfig | 1 + configs/imx6q_icore_nand_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_nand_defconfig | 1 + configs/m53menlo_defconfig | 1 + configs/marsboard_defconfig | 2 ++ configs/mx53cx9020_defconfig | 1 + configs/mx53ppd_defconfig | 1 + configs/mx6cuboxi_defconfig | 2 ++ configs/mx6qsabrelite_defconfig | 2 ++ configs/mx6sabreauto_defconfig | 2 ++ configs/mx6sabresd_defconfig | 2 ++ configs/nitrogen6dl2g_defconfig | 2 ++ configs/nitrogen6dl_defconfig | 2 ++ configs/nitrogen6q2g_defconfig | 2 ++ configs/nitrogen6q_defconfig | 2 ++ configs/nitrogen6s1g_defconfig | 2 ++ configs/nitrogen6s_defconfig | 2 ++ configs/novena_defconfig | 2 ++ configs/pico-imx6_defconfig | 2 ++ configs/riotboard_defconfig | 2 ++ configs/tbs2910_defconfig | 2 ++ configs/wandboard_defconfig | 2 ++ drivers/video/imx/Kconfig | 7 +++++++ include/configs/apalis_imx6.h | 2 -- include/configs/aristainetos2.h | 4 ---- include/configs/cm_fx6.h | 3 --- include/configs/colibri_imx6.h | 4 ---- include/configs/embestmx6boards.h | 4 ---- include/configs/ge_b1x5v2.h | 3 --- include/configs/ge_bx50v3.h | 4 ---- include/configs/gw_ventana.h | 4 ---- include/configs/imx6-engicam.h | 10 ---------- include/configs/m53menlo.h | 1 - include/configs/mx53cx9020.h | 3 --- include/configs/mx53ppd.h | 2 -- include/configs/mx6cuboxi.h | 4 ---- include/configs/mx6sabre_common.h | 4 ---- include/configs/nitrogen6x.h | 4 ---- include/configs/novena.h | 4 ---- include/configs/pico-imx6.h | 4 ---- include/configs/tbs2910.h | 4 ---- include/configs/wandboard.h | 4 ---- 51 files changed, 58 insertions(+), 72 deletions(-) diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 5ff29548b0..4c7ded9d22 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -118,6 +118,7 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 0a208543df..a23c77af89 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -118,6 +118,7 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index ea7596611c..217752cbd4 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -116,6 +116,7 @@ CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SOURCE=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index 180a6a8568..353942dd78 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -133,6 +133,7 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 CONFIG_IMX_WATCHDOG=y CONFIG_BCH=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index d9fbdbd640..e35788fd85 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -98,6 +98,8 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y CONFIG_BCH=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index b275247d25..f999b44775 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -163,6 +163,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_HIDE_LOGO_VERSION=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 6169042c7e..4c6291f0c5 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -167,6 +167,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_HIDE_LOGO_VERSION=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 6d57ad49a1..4e062e477e 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -173,6 +173,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_HIDE_LOGO_VERSION=y diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig index fe4866e2f5..759bbf9b34 100644 --- a/configs/imx6dl_icore_nand_defconfig +++ b/configs/imx6dl_icore_nand_defconfig @@ -74,6 +74,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig index 2cb995e7ae..c7d31d502b 100644 --- a/configs/imx6q_icore_nand_defconfig +++ b/configs/imx6q_icore_nand_defconfig @@ -75,6 +75,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 9f6d29a268..f5a7e96978 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -98,6 +98,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig index 2cb995e7ae..c7d31d502b 100644 --- a/configs/imx6qdl_icore_nand_defconfig +++ b/configs/imx6qdl_icore_nand_defconfig @@ -75,6 +75,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index a5760242be..e332de2aa9 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -122,6 +122,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_SPLASH_SOURCE=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index a6cffa2db6..27c5ebe000 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -67,6 +67,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig index b34f2e7e6b..c20c6a40a1 100644 --- a/configs/mx53cx9020_defconfig +++ b/configs/mx53cx9020_defconfig @@ -40,3 +40,4 @@ CONFIG_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig index ed4ebbbe3c..d8cb654a59 100644 --- a/configs/mx53ppd_defconfig +++ b/configs/mx53ppd_defconfig @@ -81,6 +81,7 @@ CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y CONFIG_WATCHDOG_TIMEOUT_MSECS=8000 CONFIG_IMX_WATCHDOG=y CONFIG_BCH=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 0904bd1101..a9957aba7c 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -84,6 +84,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index becf36e01c..6869b903b7 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -89,6 +89,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 634473f307..8e94a84409 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -120,6 +120,8 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 4f7d370420..9472e032c8 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -125,6 +125,8 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig index 3ec4df14a8..87ca8487fb 100644 --- a/configs/nitrogen6dl2g_defconfig +++ b/configs/nitrogen6dl2g_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig index 6a6510e12e..1bdd2f02e9 100644 --- a/configs/nitrogen6dl_defconfig +++ b/configs/nitrogen6dl_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig index e2acce8757..dc010b02a9 100644 --- a/configs/nitrogen6q2g_defconfig +++ b/configs/nitrogen6q2g_defconfig @@ -97,6 +97,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig index ceb843f15e..fe3291d22b 100644 --- a/configs/nitrogen6q_defconfig +++ b/configs/nitrogen6q_defconfig @@ -97,6 +97,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig index bb0d6f5439..b31652495f 100644 --- a/configs/nitrogen6s1g_defconfig +++ b/configs/nitrogen6s1g_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig index 0232d0c9d7..eb11959e4a 100644 --- a/configs/nitrogen6s_defconfig +++ b/configs/nitrogen6s_defconfig @@ -94,6 +94,8 @@ CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_GZIP=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 5f761799a2..3999ae1c82 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -99,5 +99,7 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_BMP_16BPP=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 9b3f76d8e5..a6ed013f8b 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -99,6 +99,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1bf40270e8..9f8fbc85c8 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -84,6 +84,8 @@ CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y # CONFIG_PANEL is not set CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 4c5b98bc65..0df8a68900 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -114,6 +114,8 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDCONSOLE_AS_LCD=y CONFIG_I2C_EDID=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_VIDEO_BMP_RLE8=y # CONFIG_GZIP is not set CONFIG_OF_LIBFDT_ASSUME_MASK=0xff diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 525f55ee00..a6baff1e24 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -83,6 +83,8 @@ CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_VIDEO_SKIP=y +CONFIG_IMX_HDMI=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_BMP_16BPP=y diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index afe950b6df..34e8b64059 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -6,3 +6,10 @@ config VIDEO_IPUV3 This enables framebuffer driver for i.MX processors working on the IPUv3(Image Processing Unit) internal graphic processor. +config IMX_VIDEO_SKIP + bool "Enable calling board_video_skip function" + depends on VIDEO_IPUV3 + +config IMX_HDMI + bool "Enable HDMI support in IPUv3" + depends on VIDEO_IPUV3 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index c9375b4d16..a3c86545f0 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -32,8 +32,6 @@ #define CONFIG_USBD_HS /* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP /* Command definition */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index b1ec8ef269..6faf544d21 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -420,10 +420,6 @@ /* UBI support */ -/* Framebuffer */ -/* check this console not needed, after test remove it */ -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index d5c0395797..9df8baa8a9 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -143,9 +143,6 @@ /* misc */ -/* Display */ -#define CONFIG_IMX_HDMI - /* EEPROM */ #endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index c6a79debd6..60a3862a4d 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -28,10 +28,6 @@ /* Client */ #define CONFIG_USBD_HS -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Command definition */ #undef CONFIG_IPADDR diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 29b7748e78..22e0fa5aab 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -43,10 +43,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #include "mx6_common.h" /* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index a8a6229f52..1458b187de 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -28,9 +28,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS -/* Video */ -#define CONFIG_IMX_VIDEO_SKIP - /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 705cb763a6..f62b8f175e 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -102,8 +102,4 @@ #define CFG_SYS_FSL_USDHC_NUM 3 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 6c5ca0a520..4d0a78c626 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -40,10 +40,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USBD_HS -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Miscellaneous configurable options */ /* Memory configuration */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 1f30798550..36b6b95b84 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -132,14 +132,4 @@ /* MTD device */ #endif -/* Falcon Mode */ -#ifdef CONFIG_SPL_OS_BOOT -/* MMC support: args@1MB kernel@2MB */ -#endif - -/* Framebuffer */ -#ifdef CONFIG_VIDEO_IPUV3 -# define CONFIG_IMX_VIDEO_SKIP -#endif - #endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index eca86a9451..66591390d9 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -78,7 +78,6 @@ /* LVDS display */ #define CFG_SYS_LDB_CLOCK 33260000 -#define CONFIG_IMX_VIDEO_SKIP /* Watchdog */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 2bc462cc37..cd806cb698 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -66,7 +66,4 @@ /* environment organization */ -/* Framebuffer and LCD */ -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 963dd92dd7..9464d6e44a 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -102,6 +102,4 @@ /* FLASH and environment organization */ -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 12741c08de..f7f209c20b 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,10 +14,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 5e95e430c4..6294fd1e2c 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -145,10 +145,6 @@ /* Environment organization */ -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_USBD_HS #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index dd7f951319..5020b3bb71 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -26,10 +26,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Framebuffer and LCD */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) #else diff --git a/include/configs/novena.h b/include/configs/novena.h index 16a89b97b0..4e46dfc526 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -63,10 +63,6 @@ #define CONFIG_USBD_HS #endif -/* Video output */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* Extra U-Boot environment. */ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 9e6c210c40..6d7873daa0 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -100,8 +100,4 @@ /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #endif /* __CONFIG_H * */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index f6544f6226..fcc9674942 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -20,10 +20,6 @@ #define CFG_SYS_BOOTMAPSZ 0x10000000 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - /* PCI */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 23027b1d3d..6923009d45 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -20,10 +20,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Framebuffer */ -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ From 500dfebf22cbf0adbef02b80c75a93892ee861ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:20 -0500 Subject: [PATCH 040/424] mpc8548cds: Migrate CONFIG_INTERRUPTS to Kconfig Only this platform sets this option, define it in the board Kconfig file. Signed-off-by: Tom Rini --- board/freescale/mpc8548cds/Kconfig | 3 +++ include/configs/MPC8548CDS.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig index 723ead51e5..bb0a075896 100644 --- a/board/freescale/mpc8548cds/Kconfig +++ b/board/freescale/mpc8548cds/Kconfig @@ -6,6 +6,9 @@ config PCI1 config FSL_CADMUS def_bool y +config INTERRUPTS + def_bool y + config SYS_BOARD default "mpc8548cds" diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 75ac269570..83eb18c3b7 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - #ifndef __ASSEMBLY__ #include #endif From d5c77533b422eabc469e9f55d14afc3ac9ac49f6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:21 -0500 Subject: [PATCH 041/424] Convert CONFIG_IODELAY_RECALIBRATION to Kconfig This converts the following to Kconfig: CONFIG_IODELAY_RECALIBRATION Signed-off-by: Tom Rini --- arch/arm/mach-omap2/omap5/Kconfig | 4 ++++ include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 18a6676422..0787d192b6 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -1,7 +1,11 @@ if OMAP54XX +config IODELAY_RECALIBRATION + bool + config DRA7XX bool + select IODELAY_RECALIBRATION select SYS_OMAP_ABE_SYSCK help DRA7xx is an OMAP based SOC with Dual Core A-15s. diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 340a8ce6dc..dacfd41cce 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -14,8 +14,6 @@ #include #include -#define CONFIG_IODELAY_RECALIBRATION - #define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ #define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ #define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 8217712e39..ac3fcacc68 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,8 +13,6 @@ #include -#define CONFIG_IODELAY_RECALIBRATION - #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x80000000 From c136a861054e698dec86f5f7b2a326ad38cd197f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:22 -0500 Subject: [PATCH 042/424] Convert CONFIG_IOMUX_SHARE_CONF_REG et al to Kconfig This converts the following to Kconfig: CONFIG_IOMUX_LPSR CONFIG_IOMUX_SHARE_CONF_REG Signed-off-by: Tom Rini --- arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-vf610/imx-regs.h | 3 --- arch/arm/mach-imx/Kconfig | 6 ++++++ arch/arm/mach-imx/mx6/Kconfig | 3 +++ arch/arm/mach-imx/mx7/Kconfig | 1 + include/configs/colibri-imx6ull.h | 1 - include/configs/mx6sllevk.h | 2 -- include/configs/mx6ullevk.h | 2 -- include/configs/mx7_common.h | 3 --- 9 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f68d0988b..eb5e3b69d8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1245,6 +1245,7 @@ config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A select GPIO_EXTRA_HEADER + select IOMUX_SHARE_CONF_REG select MACH_IMX select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 97211f4b12..fa3a97824f 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -103,9 +103,6 @@ #define QSPI0_AMBA_BASE 0x20000000 -/* MUX mode and PAD ctrl are in one register */ -#define CONFIG_IOMUX_SHARE_CONF_REG - #define FEC_QUIRK_ENET_MAC #define I2C_QUIRK_REG diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b72b6af434..ee5f1996a8 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -195,3 +195,9 @@ config IMX_CONTAINER_CFG help This is to specific the cfg file for generating container image which will be loaded by SPL. + +config IOMUX_LPSR + bool + +config IOMUX_SHARE_CONF_REG + bool diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 752c57f52d..e6b0ee7579 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -168,6 +168,7 @@ config TARGET_COLIBRI_IMX6ULL select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR config TARGET_DART_6UL bool "Variscite imx6ULL dart(DART-SOM-6ULL)" @@ -396,6 +397,7 @@ config TARGET_MX6SLLEVK select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR imply CMD_DM config TARGET_MX6SXSABRESD @@ -464,6 +466,7 @@ config TARGET_MX6ULL_14X14_EVK select BOARD_LATE_INIT select DM select DM_THERMAL + select IOMUX_LPSR imply CMD_DM config TARGET_MX6ULZ_SMM_M2 diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 3c388183bc..0bb18f6520 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -6,6 +6,7 @@ config MX7 select ARCH_SUPPORT_PSCI select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select IOMUX_LPSR select ROM_UNIFIED_SECTIONS select SYSCOUNTER_TIMER imply CMD_FUSE diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 12dc946fc7..c0c3b4e035 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -11,7 +11,6 @@ #define __COLIBRI_IMX6ULL_CONFIG_H #include "mx6_common.h" -#define CONFIG_IOMUX_LPSR #define PHYS_SDRAM_SIZE SZ_1G diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 6632e4ea29..8731f6a3e4 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -92,8 +92,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IOMUX_LPSR - /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 4154d328de..0e986093f3 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -108,8 +108,6 @@ /* environment organization */ -#define CONFIG_IOMUX_LPSR - #ifdef CONFIG_CMD_NET #define CONFIG_FEC_ENET_DEV 1 #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 4704276a74..d5af699010 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -17,9 +17,6 @@ #define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -/* Enable iomux-lpsr support */ -#define CONFIG_IOMUX_LPSR - /* Miscellaneous configurable options */ /* UART */ From 68e54040ccc3c5432be720e0cc6da3489eaceef6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:23 -0500 Subject: [PATCH 043/424] sandbox: Move CONFIG_IO_TRACE to Kconfig This is only used on sandbox, so select it there. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/Kconfig | 1 + common/Kconfig | 3 +++ include/configs/sandbox.h | 2 -- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index ae39716697..51d46a45fe 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -146,6 +146,7 @@ config SANDBOX select DM_SPI select DM_SPI_FLASH select GZIP_COMPRESSED + select IO_TRACE select LZO select OF_BOARD_SETUP select PCI_ENDPOINT diff --git a/common/Kconfig b/common/Kconfig index 053e93eb1a..8c71d3c972 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1086,3 +1086,6 @@ config FDT_SIMPLEFB These functions can be used by board to indicate to the OS the presence of the simple frame buffer with associated reserved memory + +config IO_TRACE + bool diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1081e0bbc4..1779f1894e 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,8 +6,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_IO_TRACE - #define CONFIG_MALLOC_F_ADDR 0x0010000 /* Size of our emulated memory */ From d5596cbc6e4d189e006f0422b162cd12e07c5b97 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:24 -0500 Subject: [PATCH 044/424] arm: lpc32xx: Remove unused hsuart driver This driver is not enabled in any config currently, remove it. Cc: Trevor Woerner Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-lpc32xx/config.h | 8 -- arch/arm/mach-lpc32xx/devices.c | 16 --- drivers/serial/Makefile | 1 - drivers/serial/lpc32xx_hsuart.c | 112 --------------------- include/dm/platform_data/lpc32xx_hsuart.h | 18 ---- 5 files changed, 155 deletions(-) delete mode 100644 drivers/serial/lpc32xx_hsuart.c delete mode 100644 include/dm/platform_data/lpc32xx_hsuart.h diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index 3ad78cb1e6..41160384a4 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -11,14 +11,6 @@ /* Basic CPU architecture */ -/* UART configuration */ -#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \ - (CONFIG_CONS_INDEX == 7) -#if !defined(CONFIG_LPC32XX_HSUART) -#define CONFIG_LPC32XX_HSUART -#endif -#endif - #if !defined(CFG_SYS_NS16550_CLK) #define CFG_SYS_NS16550_CLK 13000000 #endif diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c index 3fcf8facb4..6a67a3591a 100644 --- a/arch/arm/mach-lpc32xx/devices.c +++ b/arch/arm/mach-lpc32xx/devices.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include @@ -53,26 +52,11 @@ static const struct ns16550_plat lpc32xx_uart[] = { .clock = CFG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, }, }; -#if defined(CONFIG_LPC32XX_HSUART) -static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = { - { HS_UART1_BASE, }, - { HS_UART2_BASE, }, - { HS_UART7_BASE, }, -}; -#endif - U_BOOT_DRVINFOS(lpc32xx_uarts) = { -#if defined(CONFIG_LPC32XX_HSUART) - { "lpc32xx_hsuart", &lpc32xx_hsuart[0], }, - { "lpc32xx_hsuart", &lpc32xx_hsuart[1], }, -#endif { "ns16550_serial", &lpc32xx_uart[0], }, { "ns16550_serial", &lpc32xx_uart[1], }, { "ns16550_serial", &lpc32xx_uart[2], }, { "ns16550_serial", &lpc32xx_uart[3], }, -#if defined(CONFIG_LPC32XX_HSUART) - { "lpc32xx_hsuart", &lpc32xx_hsuart[2], }, -#endif }; #endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 45cf94c74c..33fa568221 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o obj-$(CONFIG_CORTINA_UART) += serial_cortina.o obj-$(CONFIG_DEBUG_SBI_CONSOLE) += serial_sbi.o obj-$(CONFIG_EFI_APP) += serial_efi.o -obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o obj-$(CONFIG_MCFUART) += serial_mcf.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P_SERIAL) += serial_s5p.o diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c deleted file mode 100644 index d39a3c0494..0000000000 --- a/drivers/serial/lpc32xx_hsuart.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2011-2015 Vladimir Zapolskiy - */ - -#include -#include -#include -#include -#include - -#include -#include - -struct lpc32xx_hsuart_priv { - struct hsuart_regs *hsuart; -}; - -static int lpc32xx_serial_setbrg(struct udevice *dev, int baudrate) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - u32 div; - - /* UART rate = PERIPH_CLK / ((HSU_RATE + 1) x 14) */ - div = (get_serial_clock() / 14 + baudrate / 2) / baudrate - 1; - if (div > 255) - div = 255; - - writel(div, &hsuart->rate); - - return 0; -} - -static int lpc32xx_serial_getc(struct udevice *dev) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - - if (!(readl(&hsuart->level) & HSUART_LEVEL_RX)) - return -EAGAIN; - - return readl(&hsuart->rx) & HSUART_RX_DATA; -} - -static int lpc32xx_serial_putc(struct udevice *dev, const char c) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - - /* Wait for empty FIFO */ - if (readl(&hsuart->level) & HSUART_LEVEL_TX) - return -EAGAIN; - - writel(c, &hsuart->tx); - - return 0; -} - -static int lpc32xx_serial_pending(struct udevice *dev, bool input) -{ - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - struct hsuart_regs *hsuart = priv->hsuart; - - if (input) { - if (readl(&hsuart->level) & HSUART_LEVEL_RX) - return 1; - } else { - if (readl(&hsuart->level) & HSUART_LEVEL_TX) - return 1; - } - - return 0; -} - -static int lpc32xx_serial_init(struct hsuart_regs *hsuart) -{ - /* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */ - writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) | - HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0, - &hsuart->ctrl); - - return 0; -} - -static int lpc32xx_hsuart_probe(struct udevice *dev) -{ - struct lpc32xx_hsuart_plat *plat = dev_get_plat(dev); - struct lpc32xx_hsuart_priv *priv = dev_get_priv(dev); - - priv->hsuart = (struct hsuart_regs *)plat->base; - - lpc32xx_serial_init(priv->hsuart); - - return 0; -} - -static const struct dm_serial_ops lpc32xx_hsuart_ops = { - .setbrg = lpc32xx_serial_setbrg, - .getc = lpc32xx_serial_getc, - .putc = lpc32xx_serial_putc, - .pending = lpc32xx_serial_pending, -}; - -U_BOOT_DRIVER(lpc32xx_hsuart) = { - .name = "lpc32xx_hsuart", - .id = UCLASS_SERIAL, - .probe = lpc32xx_hsuart_probe, - .ops = &lpc32xx_hsuart_ops, - .priv_auto = sizeof(struct lpc32xx_hsuart_priv), - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/include/dm/platform_data/lpc32xx_hsuart.h b/include/dm/platform_data/lpc32xx_hsuart.h deleted file mode 100644 index 6f41e0e734..0000000000 --- a/include/dm/platform_data/lpc32xx_hsuart.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Vladimir Zapolskiy - */ - -#ifndef _LPC32XX_HSUART_PLAT_H -#define _LPC32XX_HSUART_PLAT_H - -/** - * struct lpc32xx_hsuart_plat - NXP LPC32xx HSUART platform data - * - * @base: Base register address - */ -struct lpc32xx_hsuart_plat { - unsigned long base; -}; - -#endif From 00faea644a0afb8eccb332af446c4ca9d0abe095 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:25 -0500 Subject: [PATCH 045/424] arm: ls102xa: Migrate LS102XA_STREAM_ID This symbol appears to be globally used in the architecture, select it. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/Kconfig | 4 ++++ include/configs/km/pg-wcom-ls102xa.h | 6 ------ include/configs/ls1021aiot.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atsn.h | 2 -- include/configs/ls1021atwr.h | 2 -- 6 files changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 369e68b819..7e138e0cc5 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -2,6 +2,7 @@ config ARCH_LS1021A bool select FSL_DEVICE_DISABLE select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI + select LS102XA_STREAM_ID select SYS_FSL_DDR_BE if SYS_FSL_DDR select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR select SYS_FSL_IFC_BE @@ -37,6 +38,9 @@ config FSL_DEVICE_DISABLE config LS1_DEEP_SLEEP bool "Deep sleep" +config LS102XA_STREAM_ID + bool + config MAX_CPUS int "Maximum number of CPUs permitted for LS102xA" default 2 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index bbd2b36c45..c1174b87ab 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -168,12 +168,6 @@ #define HWCONFIG_BUFFER_SIZE 256 -/* - * Miscellaneous configurable options - */ - -#define CONFIG_LS102XA_STREAM_ID - /* * Environment */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index a968014980..024a718527 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -103,8 +103,6 @@ */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - #include #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 34d4c2fdec..5a91cc3efe 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -295,8 +295,6 @@ */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - /* * Environment */ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index a5b7364435..5612c60ae9 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -140,8 +140,6 @@ /* Miscellaneous configurable options */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - /* Environment */ #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 059941e713..3c4c207edd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -297,8 +297,6 @@ */ #define CFG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_LS102XA_STREAM_ID - /* * Environment */ From 4982e123b293b1fd44164b6760ee3647720d72ba Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:26 -0500 Subject: [PATCH 046/424] arm: samsung: Move CONFIG_MISC_COMMON to Kconfig This option controls using board/samsung/common/misc.c, so add a Kconfig file there as well and select it from the boards which use this functionality. Signed-off-by: Tom Rini Reviewed-by: Simon Glass Reviewed-by: Minkyu Kang --- arch/arm/Kconfig | 1 + arch/arm/mach-exynos/Kconfig | 5 +++++ arch/arm/mach-s5pc1xx/Kconfig | 1 + board/samsung/common/Kconfig | 2 ++ include/configs/odroid.h | 6 ------ include/configs/odroid_xu3.h | 1 - include/configs/s5p_goni.h | 2 -- include/configs/s5pc210_universal.h | 3 --- include/configs/trats.h | 3 --- include/configs/trats2.h | 3 --- 10 files changed, 9 insertions(+), 18 deletions(-) create mode 100644 board/samsung/common/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eb5e3b69d8..fb696abac8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2342,6 +2342,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/samsung/common/Kconfig" source "board/siemens/common/Kconfig" source "board/seeed/npi_imx6ull/Kconfig" source "board/socionext/developerbox/Kconfig" diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8410290856..29e35e443c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -67,10 +67,12 @@ config TARGET_SMDKV310 select SUPPORT_SPL config TARGET_TRATS + select MISC_COMMON bool "Exynos4210 Trats board" config TARGET_S5PC210_UNIVERSAL bool "EXYNOS4210 Universal C210 board" + select MISC_COMMON config TARGET_ORIGEN bool "Exynos4412 Origen board" @@ -79,9 +81,11 @@ config TARGET_ORIGEN config TARGET_TRATS2 bool "Exynos4412 Trat2 board" + select MISC_COMMON config TARGET_ODROID bool "Exynos4412 Odroid board" + select MISC_COMMON endchoice endif @@ -113,6 +117,7 @@ config TARGET_ODROID_XU3 bool "Exynos5422 Odroid board" select EXYNOS5_DT select EXYNOS5420 + select MISC_COMMON select OF_CONTROL config TARGET_ARNDALE diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig index 8cffced551..b6a4b0b653 100644 --- a/arch/arm/mach-s5pc1xx/Kconfig +++ b/arch/arm/mach-s5pc1xx/Kconfig @@ -9,6 +9,7 @@ config TARGET_S5P_GONI select OF_CONTROL select BLK select DM_MMC + select MISC_COMMON config TARGET_SMDKC100 bool "Support smdkc100 board" diff --git a/board/samsung/common/Kconfig b/board/samsung/common/Kconfig new file mode 100644 index 0000000000..849aeff613 --- /dev/null +++ b/board/samsung/common/Kconfig @@ -0,0 +1,2 @@ +config MISC_COMMON + bool diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 8b00a27921..f252b34943 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -143,10 +143,4 @@ "kernel_addr_r=0x41000000\0" \ BOOTENV -/* - * Supported Odroid boards: X3, U3 - * TODO: Add Odroid X support - */ -#define CONFIG_MISC_COMMON - #endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index d2d7fca544..5bbe7aadcb 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -57,7 +57,6 @@ "params.bin raw 0x1880 0x20\0" /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ -#define CONFIG_MISC_COMMON #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 3d49d52b38..fdade1ee66 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -61,8 +61,6 @@ #define COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_MISC_COMMON - #define CONFIG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 06be9c0f65..80d3fc9258 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -95,9 +95,6 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trats.h b/include/configs/trats.h index 5bd0ca2a96..ec18842bbe 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -125,9 +125,6 @@ /* GPT */ -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index cef563696b..0aa331e393 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -115,9 +115,6 @@ /* GPT */ -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - /* Download menu - definitions for check keys */ #ifndef __ASSEMBLY__ From 2568bd6db760b384f7c17f5afdfc1cb63b17ed53 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:27 -0500 Subject: [PATCH 047/424] arm: Remove unused mx27 code We no longer have any i.MX27 platforms, remove the remaining support code. Signed-off-by: Tom Rini --- arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/mx27/Makefile | 7 - arch/arm/cpu/arm926ejs/mx27/generic.c | 378 ------------------------- arch/arm/cpu/arm926ejs/mx27/relocate.S | 50 ---- arch/arm/cpu/arm926ejs/mx27/reset.c | 41 --- arch/arm/cpu/arm926ejs/mx27/timer.c | 166 ----------- arch/arm/lib/asm-offsets.c | 29 +- drivers/gpio/mxc_gpio.c | 12 +- drivers/mtd/nand/raw/mxc_nand.c | 3 +- drivers/mtd/nand/raw/mxc_nand.h | 2 +- drivers/net/fec_mxc.c | 3 - drivers/spi/mxc_spi.c | 8 - include/configs/imx27lite-common.h | 134 --------- 13 files changed, 9 insertions(+), 825 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mx27/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/mx27/generic.c delete mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S delete mode 100644 arch/arm/cpu/arm926ejs/mx27/reset.c delete mode 100644 arch/arm/cpu/arm926ejs/mx27/timer.c delete mode 100644 include/configs/imx27lite-common.h diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index 7f1436d76e..7e7ad4f35d 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -12,7 +12,6 @@ extra-y := endif endif -obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter spear,$(SOC)),y) += spear/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile deleted file mode 100644 index ac5ebaf5ef..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# - -obj-y += generic.o timer.o reset.o relocate.o diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c deleted file mode 100644 index 8b9d3a272a..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/generic.c +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2008 Eric Jarrige - * Copyright (c) 2009 Ilya Yanok - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_MMC_MXC -#include -#endif - -/* - * get the system pll clock in Hz - * - * mfi + mfn / (mfd +1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ -static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) -{ - unsigned int mfi = (pll >> 10) & 0xf; - unsigned int mfn = pll & 0x3ff; - unsigned int mfd = (pll >> 16) & 0x3ff; - unsigned int pd = (pll >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn), - (mfd + 1) * (pd + 1)); -} - -static ulong clk_in_32k(void) -{ - return 1024 * CONFIG_MX27_CLK32; -} - -static ulong clk_in_26m(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { - /* divide by 1.5 */ - return 26000000 * 2 / 3; - } else { - return 26000000; - } -} - -static ulong imx_get_mpllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_MCU_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->mpctl0), fref); -} - -static ulong imx_get_armclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - if (!(cscr & CSCR_ARM_SRC_MPLL)) - fref = lldiv((fref * 2), 3); - - div = ((cscr >> 12) & 0x3) + 1; - - return lldiv(fref, div); -} - -static ulong imx_get_ahbclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref = imx_get_mpllclk(); - ulong div; - - div = ((cscr >> 8) & 0x3) + 1; - - return lldiv(fref * 2, 3 * div); -} - -static __attribute__((unused)) ulong imx_get_spllclk(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - ulong cscr = readl(&pll->cscr); - ulong fref; - - if (cscr & CSCR_SP_SEL) - fref = clk_in_26m(); - else - fref = clk_in_32k(); - - return imx_decode_pll(readl(&pll->spctl0), fref); -} - -static ulong imx_decode_perclk(ulong div) -{ - return lldiv((imx_get_mpllclk() * 2), (div * 3)); -} - -static ulong imx_get_perclk1(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); -} - -static ulong imx_get_perclk2(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); -} - -static __attribute__((unused)) ulong imx_get_perclk3(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); -} - -static __attribute__((unused)) ulong imx_get_perclk4(void) -{ - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); -} - -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return imx_get_armclk(); - case MXC_I2C_CLK: - return imx_get_ahbclk()/2; - case MXC_UART_CLK: - return imx_get_perclk1(); - case MXC_FEC_CLK: - return imx_get_ahbclk(); - case MXC_ESDHC_CLK: - return imx_get_perclk2(); - } - return -1; -} - - -u32 get_cpu_rev(void) -{ - return MXC_CPU_MX27 << 12; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - char buf[32]; - - printf("CPU: Freescale i.MX27 at %s MHz\n\n", - strmhz(buf, imx_get_mpllclk())); - return 0; -} -#endif - -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_FEC_MXC) - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* enable FEC clock */ - writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); - writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0); - return fecmxc_initialize(bis); -#else - return 0; -#endif -} - -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(struct bd_info *bis) -{ -#ifdef CONFIG_MMC_MXC - return mxc_mmc_init(bis); -#else - return 0; -#endif -} - -void imx_gpio_mode(int gpio_mode) -{ - struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE; - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; - unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - if (gpio_mode & GPIO_PUEN) { - writel(readl(®s->port[port].puen) | (1 << pin), - ®s->port[port].puen); - } else { - writel(readl(®s->port[port].puen) & ~(1 << pin), - ®s->port[port].puen); - } - - /* Data direction */ - if (gpio_mode & GPIO_OUT) { - writel(readl(®s->port[port].gpio_dir) | 1 << pin, - ®s->port[port].gpio_dir); - } else { - writel(readl(®s->port[port].gpio_dir) & ~(1 << pin), - ®s->port[port].gpio_dir); - } - - /* Primary / alternate function */ - if (gpio_mode & GPIO_AF) { - writel(readl(®s->port[port].gpr) | (1 << pin), - ®s->port[port].gpr); - } else { - writel(readl(®s->port[port].gpr) & ~(1 << pin), - ®s->port[port].gpr); - } - - /* use as gpio? */ - if (!(gpio_mode & (GPIO_PF | GPIO_AF))) { - writel(readl(®s->port[port].gius) | (1 << pin), - ®s->port[port].gius); - } else { - writel(readl(®s->port[port].gius) & ~(1 << pin), - ®s->port[port].gius); - } - - /* Output / input configuration */ - if (pin < 16) { - tmp = readl(®s->port[port].ocr1); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr1); - - writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfa1) | aout << (pin * 2), - ®s->port[port].iconfa1); - writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)), - ®s->port[port].iconfb1); - writel(readl(®s->port[port].iconfb1) | bout << (pin * 2), - ®s->port[port].iconfb1); - } else { - pin -= 16; - - tmp = readl(®s->port[port].ocr2); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - writel(tmp, ®s->port[port].ocr2); - - writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfa2) | aout << (pin * 2), - ®s->port[port].iconfa2); - writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)), - ®s->port[port].iconfb2); - writel(readl(®s->port[port].iconfb2) | bout << (pin * 2), - ®s->port[port].iconfb2); - } -} - -#ifdef CONFIG_MXC_UART -void mx27_uart1_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MXC_UART */ - -#ifdef CONFIG_FEC_MXC -void mx27_fec_init_pins(void) -{ - int i; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_CLR, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); -} - -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) -{ - int i; - struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; - struct fuse_bank *bank = &iim->bank[0]; - struct fuse_bank0_regs *fuse = - (struct fuse_bank0_regs *)bank->fuse_regs; - - for (i = 0; i < 6; i++) - mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff; -} -#endif /* CONFIG_FEC_MXC */ - -#ifdef CONFIG_MMC_MXC -void mx27_sd1_init_pins(void) -{ - int i; - unsigned int mode[] = { - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} - -void mx27_sd2_init_pins(void) -{ - int i; - unsigned int mode[] = { - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - -} -#endif /* CONFIG_MMC_MXC */ diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S deleted file mode 100644 index 5dfa272be2..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/relocate.S +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * relocate - i.MX27-specific vector relocation - * - * Copyright (c) 2013 Albert ARIBAUD - */ - -#include -#include -#include - -/* - * The i.MX27 SoC is very specific with respect to exceptions: it - * does not provide RAM at the high vectors address (0xFFFF0000), - * thus only the low address (0x00000000) is useable; but that is - * in ROM. Therefore, vectors cannot be changed at all. - * - * However, these ROM-based vectors actually just perform indirect - * calls through pointers located in RAM at SoC-specific addresses, - * as follows: - * - * Offset Exception Use by ROM code - * 0x00000000 reset indirect branch to [0x00000014] - * 0x00000004 undefined instruction indirect branch to [0xfffffef0] - * 0x00000008 software interrupt indirect branch to [0xfffffef4] - * 0x0000000c prefetch abort indirect branch to [0xfffffef8] - * 0x00000010 data abort indirect branch to [0xfffffefc] - * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 - * 0x00000018 IRQ indirect branch to [0xffffff00] - * 0x0000001c FIQ indirect branch to [0xffffff04] - * - * In order to initialize exceptions on i.MX27, we must copy U-Boot's - * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 - * taking care not to copy vectors number 5 (reserved exception). - */ - - .section .text.relocate_vectors,"ax",%progbits - -ENTRY(relocate_vectors) - - ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ - ldr r1, =32 /* size of vector table */ - add r0, r0, r1 /* skip to indirect table */ - ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ - ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ - stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ - - bx lr - -ENDPROC(relocate_vectors) diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c deleted file mode 100644 index 496fb30817..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - */ - -#include -#include -#include -#include - -/* - * Reset the cpu by setting up the watchdog timer and let it time out - */ -void reset_cpu(void) -{ - struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; - /* Disable watchdog and set Time-Out field to 0 */ - writew(0x0000, ®s->wcr); - - /* Write Service Sequence */ - writew(0x5555, ®s->wsr); - writew(0xAAAA, ®s->wsr); - - /* Enable watchdog */ - writew(WCR_WDE, ®s->wcr); - - while (1); - /*NOTREACHED*/ -} diff --git a/arch/arm/cpu/arm926ejs/mx27/timer.c b/arch/arm/cpu/arm926ejs/mx27/timer.c deleted file mode 100644 index 4fd6a80596..0000000000 --- a/arch/arm/cpu/arm926ejs/mx27/timer.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 - * Ilya Yanok, Emcraft Systems Ltd, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1 << 15) /* Software reset */ -#define GPTCR_FRR (1 << 8) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */ -#define GPTCR_TEN 1 /* Timer enable */ - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp (gd->arch.tbl) -#define lastinc (gd->arch.lastinc) - -/* - * "time" is measured in 1 / CONFIG_SYS_HZ seconds, - * "tick" is internal timer period - */ -#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION -/* ~0.4% error - measured with stop-watch on 100s boot-delay */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_MX27_CLK32); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_MX27_CLK32; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_MX27_CLK32 + 999999; - do_div(us, 1000000); - return us; -} -#else -/* ~2% error */ -#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \ - CONFIG_SYS_HZ) -#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32) - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - do_div(tick, TICK_PER_TIME); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - return time * TICK_PER_TIME; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us += US_PER_TICK - 1; - do_div(us, US_PER_TICK); - return us; -} -#endif - -/* nothing really to do with interrupts, just starts up a counter. */ -/* The 32768Hz 32-bit timer overruns in 131072 seconds */ -int timer_init(void) -{ - int i; - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; - - /* setup GP Timer 1 */ - writel(GPTCR_SWR, ®s->gpt_tctl); - - writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0); - writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1); - - for (i = 0; i < 100; i++) - writel(0, ®s->gpt_tctl); /* We have no udelay by now */ - writel(0, ®s->gpt_tprer); /* 32Khz */ - /* Freerun Mode, PERCLK1 input */ - writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, - ®s->gpt_tctl); - writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl); - - return 0; -} - -unsigned long long get_ticks(void) -{ - struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; - ulong now = readl(®s->gpt_tcn); /* current tick value */ - - if (now >= lastinc) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (now - lastinc); - } else { - /* we have rollover of incrementer */ - timestamp += (0xFFFFFFFF - lastinc) + now; - } - lastinc = now; - return timestamp; -} - -static ulong get_timer_masked(void) -{ - /* - * get_ticks() returns a long long (64 bit), it wraps in - * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ - * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in - * 5 * 10^6 days - long enough. - */ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timstamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = us_to_tick(usec); - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp) /* loop till event */ - /*NOP*/; -} - -ulong get_tbclk(void) -{ - return CONFIG_MX27_CLK32; -} diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index 22fd541f9a..6de0ce9152 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,8 +15,7 @@ #include #include -#if defined(CONFIG_MX27) \ - || defined(CONFIG_MX51) || defined(CONFIG_MX53) +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include #endif @@ -35,32 +34,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */ -#if defined(CONFIG_MX27) - DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); - DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0)); - DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1)); - - DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); - DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); - DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); - DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); - DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); - DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); - DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); - - DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0)); - DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0)); - DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1)); - DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1)); - DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc)); - - DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, gpcr)); - DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + - offsetof(struct system_control_regs, fmcr)); -#endif - #if defined(CONFIG_MX51) || defined(CONFIG_MX53) /* Round up to make sure size gives nice stack alignment */ DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 03471db9e8..1dec4e35e0 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -44,13 +44,13 @@ static unsigned long gpio_ports[] = { [0] = GPIO1_BASE_ADDR, [1] = GPIO2_BASE_ADDR, [2] = GPIO3_BASE_ADDR, -#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) [3] = GPIO4_BASE_ADDR, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) [4] = GPIO5_BASE_ADDR, @@ -352,12 +352,12 @@ static const struct mxc_gpio_plat mxc_plat[] = { { 0, (struct gpio_regs *)GPIO1_BASE_ADDR }, { 1, (struct gpio_regs *)GPIO2_BASE_ADDR }, { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, -#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, #ifndef CONFIG_IMX8M @@ -376,12 +376,12 @@ U_BOOT_DRVINFOS(mxc_gpios) = { { "gpio_mxc", &mxc_plat[0] }, { "gpio_mxc", &mxc_plat[1] }, { "gpio_mxc", &mxc_plat[2] }, -#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ +#if defined(CONFIG_MX51) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[3] }, #endif -#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) { "gpio_mxc", &mxc_plat[4] }, #ifndef CONFIG_IMX8M diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index fa903e324c..8aa5f73421 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -12,8 +12,7 @@ #include #include #include -#if defined(CONFIG_MX27) || \ - defined(CONFIG_MX51) || defined(CONFIG_MX53) +#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #include #endif #include "mxc_nand.h" diff --git a/drivers/mtd/nand/raw/mxc_nand.h b/drivers/mtd/nand/raw/mxc_nand.h index 771f61e249..084fac705a 100644 --- a/drivers/mtd/nand/raw/mxc_nand.h +++ b/drivers/mtd/nand/raw/mxc_nand.h @@ -24,7 +24,7 @@ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. * Also some of registers are moved and/or changed meaning as seen below. */ -#if defined(CONFIG_MX27) || defined(CONFIG_MX31) +#if defined(CONFIG_MX31) #define MXC_NFC_V1 #define is_mxc_nfc_1() 1 #define is_mxc_nfc_21() 0 diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bbc4434ddb..a61a1fc757 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -251,9 +251,6 @@ static int miiphy_restart_aneg(struct eth_device *dev) * Wake up from sleep if necessary * Reset PHY, then delay 300ns */ -#ifdef CONFIG_MX27 - fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); -#endif fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); udelay(1000); diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 5adfdf8b5f..ea9cc3d1f9 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -91,14 +91,6 @@ struct cspi_regs { #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ #endif -#ifdef CONFIG_MX27 -/* i.MX27 has a completely wrong register layout and register definitions in the - * datasheet, the correct one is in the Freescale's Linux driver */ - -#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \ -"See linux mxc_spi driver from Freescale for details." -#endif - __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) { return -1; diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h deleted file mode 100644 index b0abd54882..0000000000 --- a/include/configs/imx27lite-common.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Heiko Schocher - * - * based on: - * Copyright (C) 2009 Ilya Yanok - */ - -#ifndef __IMX27LITE_COMMON_CONFIG_H -#define __IMX27LITE_COMMON_CONFIG_H - -/* - * SoC Configuration - */ -#define CONFIG_MX27 -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* memtest start address */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) - -/* - * Flash & Environment - */ -/* Use buffered writes (~10x faster) */ -/* Use hardware sector protection */ -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CFG_SYS_FLASH_BASE PHYS_FLASH_1 -/* Address and size of Redundant Environment Sector */ - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * MTD - */ - -/* - * NAND - */ -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CFG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_MXC_NAND_HWECC - -/* - * U-Boot general configuration - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -/* additions for new relocation code, must be added to all boards */ -#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#endif /* __IMX27LITE_COMMON_CONFIG_H */ From 6c03a652755ca415e3a1fa92525b5a8c230c9289 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:28 -0500 Subject: [PATCH 048/424] Convert CONFIG_MXS_OCOTP to Kconfig This converts the following to Kconfig: CONFIG_MXS_OCOTP Signed-off-by: Tom Rini --- drivers/misc/Kconfig | 8 ++++++++ include/configs/mxs.h | 5 ----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index fb3bbb3b91..122d605a53 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -330,6 +330,14 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config MXS_OCOTP + bool "Enable MXS OCOTP Driver" + depends on ARCH_MX23 || ARCH_MX28 + help + If you say Y here, you will get support for the One Time + Programmable memory pages that are stored on the + Freescale i.MXS family of processors. + config NPCM_HOST bool "Enable support espi or LPC for Host" depends on REGMAP && SYSCON diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 5df080ade4..30f27e7f0c 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -86,11 +86,6 @@ #define CFG_SYS_NAND_BASE 0x60000000 #endif -/* OCOTP */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXS_OCOTP -#endif - /* SPI */ #ifdef CONFIG_CMD_SPI #define CONFIG_SPI_HALF_DUPLEX From 9200011e9563c2deb71eae3c6769a92ea4e6c733 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:29 -0500 Subject: [PATCH 049/424] Convert CONFIG_NAND_KMETER1 et al to Kconfig This converts the following to Kconfig: CONFIG_NAND_ECC_BCH CONFIG_NAND_KIRKWOOD CONFIG_NAND_KMETER1 Signed-off-by: Tom Rini --- arch/arm/mach-kirkwood/include/mach/config.h | 1 - configs/kmcoge5ne_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 13 +++++++++++++ include/configs/km/km-mpc83xx.h | 1 - include/configs/kmcoge5ne.h | 2 -- 5 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index a2781e25a2..a6de767629 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -34,7 +34,6 @@ * NAND configuration */ #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD #define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ #define NAND_ALLOW_ERASE_ALL 1 #endif diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 71d196533f..c2a17c6212 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -235,6 +235,7 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_KMETER1=y CONFIG_DM_ETH_PHY=y CONFIG_QE_UEC=y # CONFIG_PCI is not set diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index eb37b62759..338a3562a4 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -225,6 +225,19 @@ config NAND_FSL_IFC help Enable the Freescale Integrated Flash Controller NAND driver. +config NAND_KIRKWOOD + bool "Support for Kirkwood NAND controller" + depends on ARCH_KIRKWOOD + default y + +config NAND_ECC_BCH + bool + +config NAND_KMETER1 + bool "Support KMETER1 NAND controller" + depends on VENDOR_KM + select NAND_ECC_BCH + config NAND_LPC32XX_MLC bool "Support LPC32XX_MLC controller" select SYS_NAND_SELF_INIT diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index e6a3613b7a..840a4d5401 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -57,7 +57,6 @@ {1, {I2C_NULL_HOP} } } #if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 2be996aaaf..c24d6ad8bc 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -9,8 +9,6 @@ #define __CONFIG_H #define CONFIG_HOSTNAME "kmcoge5ne" -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 #define NAND_MAX_CHIPS 1 #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ From c3187fb1448baf142d43fcc3d6f0e88e082050b9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:30 -0500 Subject: [PATCH 050/424] Convert CONFIG_PCA953X to Kconfig This converts the following to Kconfig: CONFIG_PCA953X Cc: Uri Mashiach Signed-off-by: Tom Rini --- README | 2 -- configs/cl-som-imx7_defconfig | 1 + drivers/gpio/Kconfig | 4 ++++ include/configs/cl-som-imx7.h | 1 - include/configs/imx8qxp_mek.h | 4 ---- include/configs/mx6sabreauto.h | 1 - 6 files changed, 5 insertions(+), 8 deletions(-) diff --git a/README b/README index 0a7635d1a2..eb76c73ac3 100644 --- a/README +++ b/README @@ -483,8 +483,6 @@ The following options need to be configured: must also be configured. See I2C Support, below. - GPIO Support: - CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO - The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of pins supported by a particular chip. diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 3571dba6d2..d1a044e3f7 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -74,6 +74,7 @@ CONFIG_ETHPRIME="FEC" CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_PCA953X=y +CONFIG_PCA953X=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e007b38fac..1e4b50ef72 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -520,6 +520,10 @@ config SPL_DM_PCA953X Now, max 24 bits chips and PCA953X compatible chips are supported +config PCA953X + bool "NXP's PCA953X series I2C GPIO (legacy driver)" + depends on !DM_PCA953X + config MPC8XXX_GPIO bool "Freescale MPC8XXX GPIO driver" depends on DM_GPIO diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 4aaa52f269..5c9004cbd9 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -21,7 +21,6 @@ /* PMIC */ #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define CONFIG_PCA953X #define CFG_SYS_I2C_PCA953X_ADDR 0x20 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 19f1dba047..d75b8bf0c1 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -110,10 +110,6 @@ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ -#ifndef CONFIG_DM_PCA953X -#define CONFIG_PCA953X -#endif - /* Misc configuration */ #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index f5f95a1bd1..888da7ce36 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -15,7 +15,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_PCA953X #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } #include "mx6sabre_common.h" From ea467ea1cda0c9f6b85be34b5e1bbb6f905fa814 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:31 -0500 Subject: [PATCH 051/424] Convert CONFIG_RTC_DS1337 et al to Kconfig This converts the following to Kconfig: CONFIG_RTC_DS1337 CONFIG_RTC_DS1337_NOOSC CONFIG_RTC_DS1338 CONFIG_RTC_DS1374 CONFIG_RTC_DS3231 CONFIG_RTC_MC13XXX CONFIG_RTC_MXS CONFIG_RTC_PT7C4338 Signed-off-by: Tom Rini --- README | 22 ---------- configs/MPC837XERDB_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/mx28evk_defconfig | 1 + configs/mx51evk_defconfig | 1 + configs/qemu-ppce500_defconfig | 1 + configs/work_92105_defconfig | 1 + drivers/rtc/Kconfig | 42 ++++++++++++++++++- include/configs/MPC837XERDB.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/T102xRDB.h | 2 - include/configs/T104xRDB.h | 2 - include/configs/eb_cpu5282.h | 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 3 -- include/configs/ls2080aqds.h | 2 - include/configs/ls2080ardb.h | 2 - include/configs/lx2160a_common.h | 1 - include/configs/mx28evk.h | 5 --- include/configs/mx51evk.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/qemu-ppce500.h | 3 -- include/configs/tqma6_wru4.h | 2 - include/configs/work_92105.h | 2 - 84 files changed, 105 insertions(+), 55 deletions(-) diff --git a/README b/README index eb76c73ac3..dd43a0c08d 100644 --- a/README +++ b/README @@ -460,28 +460,6 @@ The following options need to be configured: to 0 disables calling WATCHDOG_RESET() from the timer interrupt. -- Real-Time Clock: - - When CONFIG_CMD_DATE is selected, the type of the RTC - has to be selected, too. Define exactly one of the - following options: - - CONFIG_RTC_PCF8563 - use Philips PCF8563 RTC - CONFIG_RTC_MC13XXX - use MC13783 or MC13892 RTC - CONFIG_RTC_MC146818 - use MC146818 RTC - CONFIG_RTC_DS1307 - use Maxim, Inc. DS1307 RTC - CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC - CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC - CONFIG_RTC_DS1339 - use Maxim, Inc. DS1339 RTC - CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC - CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC - CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337 - CONFIG_SYS_RV3029_TCR - enable trickle charger on - RV3029 RTC. - - Note that if the RTC uses I2C, then the I2C interface - must also be configured. See I2C Support, below. - - GPIO Support: The CFG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index e6289fe104..b00655824e 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -207,6 +207,7 @@ CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y CONFIG_TSEC_ENET=y +CONFIG_RTC_DS1374=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index a3d9a8b4b7..b32837c778 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 2ca0250399..575d5bffcb 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -93,6 +93,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 5d57aa3ba4..21c752d974 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -114,6 +114,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index a13b48c20e..a514d4ba36 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -116,6 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index a9c7652fab..db71e9bce4 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -128,6 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index a0277d0aa6..291c4a4038 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -92,6 +92,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index f43a5a0c54..8237da39c2 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -113,6 +113,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index ef52f94882..9cb53d64e2 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -115,6 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 2b2744dd74..9574697108 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -132,6 +132,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 29b7d84809..7b3919dc16 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -95,6 +95,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 98164d2bad..3ad137dbd5 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -116,6 +116,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index d74fbecfaa..cde657ce00 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -118,6 +118,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index efd0a7eb89..1faeab2c3b 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -131,6 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 44e98b9520..190d02fa50 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -94,6 +94,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 9c65043766..5e32768c28 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -115,6 +115,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 4b967352f4..bce763c73b 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -117,6 +117,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index b65e651878..79df4a8f01 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -142,6 +142,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 034a971bc8..d70db00236 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -124,6 +124,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 9476c28e98..b885a2a5f3 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -126,6 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index ecd5e978c8..710a41915c 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -104,6 +104,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 80f4d22518..f40e001b51 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -141,6 +141,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 50fc0c124e..e320ea9b42 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index dafb430e4c..d6a188c27e 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -125,6 +125,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 411b4f05a4..b369b2fad3 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -103,6 +103,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 8b0b6e4e68..7e31f130be 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -144,6 +144,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 6a17f085a7..f671d0b1d5 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -126,6 +126,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 2738b208f1..109f03b3b8 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -128,6 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index fdd7703f72..7f8cba1483 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -106,6 +106,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 5904aa54b2..228c5f9e89 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -147,6 +147,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 938148df93..ca2b37fcb2 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -129,6 +129,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index c4a41c4c0e..f83360a87a 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -131,6 +131,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index a4ed8fb39c..524101022d 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -109,6 +109,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 9b4ca39d34..4f22e240b2 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -146,6 +146,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index a6d98b42ce..84e0b4e1a1 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -128,6 +128,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index b3e4a1f0d0..a0ce9a9533 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -130,6 +130,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index f1a9c058ca..e15c487c42 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -108,6 +108,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index f21c53d59f..e51db83263 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 6f9f5a2603..5472cccff8 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 76a59604f2..0dd725128c 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -126,6 +126,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index a4825909e7..8a2096c56d 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -98,6 +98,7 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FW_ADDR=0xEFE00000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 1aa0e9eec1..cc6a80447c 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -129,6 +129,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index ba1820e93a..cb270adc37 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 98cd9b71e0..79530eac8f 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -126,6 +126,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index f6301a57cf..a671ae3d87 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -98,6 +98,7 @@ CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xEFF10000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_DM_RTC=y +CONFIG_RTC_DS1337=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index f904bb313b..a831c1c5d2 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -52,4 +52,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_RTC_DS1338=y CONFIG_MCFUART=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 2ce6ff9140..6a673c9181 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -50,4 +50,5 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 CONFIG_MCFFEC=y CONFIG_MII=y +CONFIG_RTC_DS1338=y CONFIG_MCFUART=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index f66f529836..d449b42aa3 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -95,6 +95,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index d601c083e2..973537aaeb 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -98,6 +98,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index e2b6044d1f..4fc4419493 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -111,6 +111,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 8abd58d53e..4cd1c85852 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -91,6 +91,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 389b32b2d6..52566582ca 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -105,6 +105,7 @@ CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index e4d15dda14..15bc69ec47 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -92,6 +92,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 4030fd4693..88b5d23926 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -95,6 +95,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index b6e154b78b..8339cf7232 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -114,6 +114,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 09df15154e..a9faa1525a 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -111,6 +111,7 @@ CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_SYS_NS16550_SERIAL=y CONFIG_SPI=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 8cdfe5cc0b..d3a113332d 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -80,6 +80,7 @@ CONFIG_MII=y CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 84c9f15266..f94142d073 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -87,6 +87,7 @@ CONFIG_MII=y CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index 3ac03305c7..1dd7c1dd80 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -98,6 +98,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 41891d83ac..246ab40375 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -106,6 +106,7 @@ CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y +CONFIG_RTC_DS3231=y CONFIG_DM_SCSI=y CONFIG_CONS_INDEX=2 CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 996dd5c970..dad8839a6c 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -61,6 +61,7 @@ CONFIG_PINCTRL_MXS=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RTC_MXS=y CONFIG_CONS_INDEX=0 CONFIG_SPI=y CONFIG_USB=y diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig index 774523bc84..b173648c8e 100644 --- a/configs/mx51evk_defconfig +++ b/configs/mx51evk_defconfig @@ -56,6 +56,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_POWER_FSL=y CONFIG_POWER_SPI=y +CONFIG_RTC_MC13XXX=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index d6ff4ac2c2..cdad1b0995 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -52,6 +52,7 @@ CONFIG_E1000=y CONFIG_TSEC_ENET=y CONFIG_PCI_MPC85XX=y CONFIG_DM_RTC=y +CONFIG_RTC_PT7C4338=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_SYSRESET=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 127bbf715f..167a07860f 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -72,6 +72,7 @@ CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000 CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y +CONFIG_RTC_DS1374=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_CONS_INDEX=5 CONFIG_SYS_NS16550=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2396327192..b698722569 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -68,9 +68,38 @@ config RTC_DS1307 bool "Enable DS1307 driver" depends on DM_RTC help - Support for Dallas Semiconductor (now Maxim) DS1307 and DS1338/9 and + Support for Dallas Semiconductor (now Maxim) DS1307 and DS1339 and compatible Real Time Clock devices. +config RTC_DS1337 + bool "Enable DS1337 driver" + help + Support for Dallas Semiconductor (now Maxim) DS1337/8/9 compatible + Real Time Clock devices. + +config RTC_DS1337_NOOSC + bool "Enable support for no oscillator output in DS1337 driver" + depends on RTC_DS1337 + +config RTC_DS1338 + bool "Enable DS1338 driver" + help + Support for Dallas Semiconductor (now Maxim) DS1338 and compatible + Real Time Clock devices. + +config RTC_DS1374 + bool "Enable DS1374 driver" + depends on !DM_RTC + help + Support for Dallas Semiconductor (now Maxim) DS1374 and compatible + Real Time Clock devices. + +config RTC_DS3231 + bool "Enable DS3231 driver" + help + Support for Dallas Semiconductor (now Maxim) DS3231 compatible + Real Time Clock devices. + config RTC_DS3232 bool "Enable DS3232 driver" depends on DM_RTC @@ -111,6 +140,9 @@ config RTC_PCF8563 If you say yes here you get support for the Philips PCF8563 RTC and compatible chips. +config RTC_PT7C4338 + bool "Enable Pericom Technology PT7C4338 RTC driver" + config RTC_RV3028 bool "Enable RV3028 driver" depends on DM_RTC @@ -169,6 +201,10 @@ config RTC_S35392A help Enable s35392a driver which provides rtc get and set function. +config RTC_MC13XXX + bool "Enable MC13XXX RTC driver" + depends on !DM_RTC + config RTC_MC146818 bool "Enable MC146818 driver" help @@ -185,6 +221,10 @@ config SYS_MCFRTC_BASE hex "Base address for RTC in immap.h" depends on MCFRTC +config RTC_MXS + bool "Enable i.MXS RTC driver" + depends on ARCH_MX23 || ARCH_MX28 + config RTC_M41T62 bool "Enable M41T62 driver" help diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 2796adbdcd..de63a0f199 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -167,7 +167,6 @@ /* * Config on-board RTC */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ #define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ /* diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0a1b932e94..c0805f979b 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -341,7 +341,6 @@ extern unsigned long get_sdram_size(void); /* enable read and write access to EEPROM */ /* RTC */ -#define CONFIG_RTC_PT7C4338 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e394237daf..623d4cf556 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -311,8 +311,6 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS1337 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index f681a21822..d3fd10526b 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -285,8 +285,6 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS1337 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 /*DVI encoder*/ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 426155dbdb..21eab9b3a4 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -150,7 +150,6 @@ */ #ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 #define CONFIG_I2C_RTC_ADDR 0x68 #endif diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index e772c01907..495bb3911b 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -46,7 +46,6 @@ /* * RTC configuration */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 58ae0fb0a6..1759d25f3a 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -66,7 +66,6 @@ #define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ /* RTC */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ #define CFG_SYS_RTC_BUS_NUM 0 diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index d84622f322..a35045d640 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -280,7 +280,6 @@ /* * RTC configuration */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #ifdef CONFIG_FSL_DSPI diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 187b3072f0..7bc4fc6a66 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -186,13 +186,10 @@ #define I2C_MUX_CH_DEFAULT 0x8 #define I2C_MUX_CH5 0xD -#ifndef SPL_NO_RTC /* * RTC configuration */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#endif #ifndef SPL_NO_ENV /* Initial environment variables */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 067587b53c..924d4057d9 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -227,8 +227,6 @@ /* * RTC configuration */ -#define RTC -#define CONFIG_RTC_DS3231 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 32a1194872..c50b603068 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -210,11 +210,9 @@ /* * RTC configuration */ -#define RTC #ifdef CONFIG_TARGET_LS2081ARDB #define CFG_SYS_I2C_RTC_ADDR 0x51 #else -#define CONFIG_RTC_DS3231 1 #define CFG_SYS_I2C_RTC_ADDR 0x68 #endif diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index ff85d966e6..a469c83fa4 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -74,7 +74,6 @@ #define I2C_MUX_CH_DEFAULT 0x8 /* RTC */ -#define RTC #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* Qixis */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index bc8c893370..c740d85332 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -17,11 +17,6 @@ /* UBI and NAND partitioning */ -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif - /* Extra Environment */ #define CONFIG_EXTRA_ENV_SETTINGS \ "ubifs_file=filesystem.ubifs\0" \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index d9d76d7c08..ddd37b3936 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -26,7 +26,6 @@ #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX /* * MMC Configs diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index eda2d43d0c..c8acce8b06 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -329,7 +329,6 @@ * I2C2 EEPROM */ -#define CONFIG_RTC_PT7C4338 #define CFG_SYS_I2C_RTC_ADDR 0x68 #define CFG_SYS_I2C_PCA9557_ADDR 0x18 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index d1b20da24a..30a9eae852 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -44,9 +44,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* RTC */ -#define CONFIG_RTC_PT7C4338 - /* * Miscellaneous configurable options */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index ce897fcd93..4d8839b6e6 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -16,11 +16,9 @@ /* Watchdog */ /* Config on-board RTC */ -#define CONFIG_RTC_DS1337 #define CFG_SYS_RTC_BUS_NUM 2 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Turn off RTC square-wave output to save battery */ -#define CONFIG_RTC_DS1337_NOOSC /* LED */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 065006f912..010da1531f 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -19,8 +19,6 @@ #define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE #define CFG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_RTC_DS1374 - /* * U-Boot General Configurations */ From 1c34f7885d7dc109b3ffa6e2c071bf777ed917e8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:32 -0500 Subject: [PATCH 052/424] Convert CONFIG_SH_GPIO_PFC et al to Kconfig This converts the following to Kconfig: CONFIG_SH_GPIO_PFC CONFIG_TMU_TIMER Signed-off-by: Tom Rini --- arch/arm/mach-rmobile/Kconfig.32 | 4 ++++ drivers/gpio/Kconfig | 5 +++++ include/configs/rcar-gen2-common.h | 5 ----- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index a07eff71df..31badc5a47 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -8,6 +8,7 @@ config RCAR_GEN2 bool "Renesas RCar Gen2" select PHY select PHY_RCAR_GEN2 + select TMU_TIMER config R8A7740 bool "Renesas SoC R8A7740" @@ -121,6 +122,9 @@ config TARGET_STOUT endchoice +config TMU_TIMER + bool + config SYS_SOC default "rmobile" diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1e4b50ef72..365615a53f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -596,6 +596,11 @@ config ZYNQMP_GPIO_MODEPIN are accessed using xilinx firmware. In modepin register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits set/clear IO. +config SH_GPIO_PFC + bool "Pinmuxed GPIO support for SuperH" + depends on RCAR_GEN2 && !PINCTRL_PFC + default y + config SL28CPLD_GPIO bool "Kontron sl28cpld GPIO driver" depends on DM_GPIO && SL28CPLD diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index a86180ead5..291c2a43d4 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -10,10 +10,6 @@ #include -#ifndef CONFIG_PINCTRL_PFC -#define CONFIG_SH_GPIO_PFC -#endif - /* console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } @@ -21,7 +17,6 @@ #define CFG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) /* Timer */ -#define CONFIG_TMU_TIMER #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (get_board_sys_clk() / 8) From d91365203c06e0fbfa329e707196e9aa51241e4c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:33 -0500 Subject: [PATCH 053/424] Convert CONFIG_SMSC_LPC47M et al to Kconfig This converts the following to Kconfig: CONFIG_SMSC_LPC47M CONFIG_SMSC_SIO1007 Signed-off-by: Tom Rini --- configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + drivers/misc/Kconfig | 6 ++++++ include/configs/cougarcanyon2.h | 2 -- include/configs/crownbay.h | 2 -- 5 files changed, 8 insertions(+), 4 deletions(-) diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 203eff8e16..8b47f2d89f 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -52,6 +52,7 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y +CONFIG_SMSC_SIO1007=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SPI=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index cb0f0d7c8d..038cbbe5b9 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -56,6 +56,7 @@ CONFIG_SYSCON=y CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_CPU=y +CONFIG_SMSC_LPC47M=y CONFIG_E1000=y CONFIG_SYS_NS16550_PORT_MAPPED=y CONFIG_SOUND=y diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 122d605a53..b07261d3db 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -112,6 +112,12 @@ config SIFIVE_OTP Enable support for reading and writing the eMemory OTP on the SiFive SoCs. +config SMSC_LPC47M + bool "LPC47M SMSC driver" + +config SMSC_SIO1007 + bool "SIO1007 SMSC driver" + config VEXPRESS_CONFIG bool "Enable support for Arm Versatile Express config bus" depends on MISC diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h index efd0b77843..b64c7df1b2 100644 --- a/include/configs/cougarcanyon2.h +++ b/include/configs/cougarcanyon2.h @@ -8,8 +8,6 @@ #include -#define CONFIG_SMSC_SIO1007 - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vga\0" \ "stderr=serial,vga\0" diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index e8a8af7e64..ff74deb3d4 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -12,8 +12,6 @@ #include -#define CONFIG_SMSC_LPC47M - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" From 8ce59b5932946b10d5abdd4b06577e7413bbec13 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:34 -0500 Subject: [PATCH 054/424] Convert CONFIG_SPD_EEPROM to Kconfig This converts the following to Kconfig: CONFIG_SPD_EEPROM Cc: Stefan Roese Signed-off-by: Tom Rini --- README | 7 ------- configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/socrates_defconfig | 1 + drivers/ddr/Kconfig | 8 ++++++++ include/configs/MPC8548CDS.h | 1 - include/configs/db-mv784mp-gp.h | 3 --- include/configs/socrates.h | 1 - 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/README b/README index dd43a0c08d..0acc0b4109 100644 --- a/README +++ b/README @@ -1683,13 +1683,6 @@ Low Level (hardware related) configuration options: Sets the EBC0_CFG register for the NDFC. If not defined a default value will be used. -- CONFIG_SPD_EEPROM - Get DDR timing information from an I2C EEPROM. Common - with pluggable memory modules such as SODIMMs - - SPD_EEPROM_ADDRESS - I2C address of the SPD EEPROM - - CONFIG_SYS_SPD_BUS_NUM If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 86a67d7b21..517fd785dd 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -45,6 +45,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 2ac4f26685..5c83e808d5 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index faabd7bc04..b354237db3 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -44,6 +44,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index ab52ea26a0..f45f570764 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xFFF20000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="TSEC0" +CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFE001001 diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index 738b788401..fa873cc487 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -37,3 +37,11 @@ config SYS_SPD_BUS_NUM source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" + +config SPD_EEPROM + bool "DDR controller makes use of an SPD EEPROM for JEDEC information" + depends on SYS_FSL_DDR || SYS_FSL_MMDC || CONFIG_ARMADA_XP + help + Get DDR timing information from an I2C EEPROM. Common with pluggable + memory modules such as SODIMMs. You must define SPD_EEPROM_ADDRESS + to the I2C address of the SPD EEPROM. diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 83eb18c3b7..780ee5ae86 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -30,7 +30,6 @@ #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 7b305955c9..bf8b35102a 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -45,7 +45,4 @@ /* SPL */ /* Defines for SPL */ -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SPD_EEPROM 0x4e - #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 0a2d581517..95393d3ab2 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -50,7 +50,6 @@ #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef From fcd7ba655e24c736c7f3a1d12fb98f1c9c2705b6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:35 -0500 Subject: [PATCH 055/424] Convert CONFIG_TPS6586X_POWER et al to Kconfig This converts the following to Kconfig: CONFIG_TPS6586X_POWER CONFIG_TWL6030_POWER Signed-off-by: Tom Rini --- configs/omap4_panda_defconfig | 1 + configs/omap4_sdp4430_defconfig | 1 + configs/seaboard_defconfig | 1 + drivers/power/Kconfig | 7 +++++++ include/configs/seaboard.h | 1 - include/configs/ti_omap4_common.h | 3 --- 6 files changed, 10 insertions(+), 4 deletions(-) diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig index 0cae1c6150..79807f104f 100644 --- a/configs/omap4_panda_defconfig +++ b/configs/omap4_panda_defconfig @@ -45,6 +45,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y +CONFIG_TWL6030_POWER=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig index e15c6d5cb1..e2f1bc67df 100644 --- a/configs/omap4_sdp4430_defconfig +++ b/configs/omap4_sdp4430_defconfig @@ -42,6 +42,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y +CONFIG_TWL6030_POWER=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550_SERIAL=y CONFIG_USB=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 686a3c062b..2375040a9e 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_TPS6586X_POWER=y CONFIG_PWM_TEGRA=y CONFIG_SYS_NS16550=y CONFIG_USB=y diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 5dbcde333b..7f3b990d23 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -411,6 +411,9 @@ config SY8106A_VOUT1_VOLT is typically used to power the VDD-CPU and should be 1200mV. Values can range from 680mV till 1950mV. +config TPS6586X_POWER + bool "Enable legacy driver for TI TPS6586x power management chip" + config TWL4030_POWER depends on OMAP34XX bool "Enable driver for TI TWL4030 power management chip" @@ -419,6 +422,10 @@ config TWL4030_POWER The TWL4030 in a combination audio CODEC/power management with GPIO and it is commonly used with the OMAP3 family of processors +config TWL6030_POWER + depends on OMAP44XX + bool "Enable driver for TI TWL6030 power management chip" + config POWER_MT6323 bool "Poweroff driver for mediatek mt6323" select CMD_POWEROFF diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 4887747968..73b738bd09 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -12,7 +12,6 @@ /* LP0 suspend / resume */ #define CONFIG_TEGRA_LP0 #define CONFIG_TEGRA_PMU -#define CONFIG_TPS6586X_POWER #define CONFIG_TEGRA_CLOCK_SCALING #include "tegra20-common.h" diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 9a068e2614..64ec59d78e 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -32,9 +32,6 @@ #define CFG_SYS_NS16550_COM3 UART3_BASE #endif -/* TWL6030 */ -#define CONFIG_TWL6030_POWER 1 - /* * Environment setup */ From b43295a27712c136afc68b0cf272e0356474642c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:36 -0500 Subject: [PATCH 056/424] Convert CONFIG_TEGRA_CLOCK_SCALING et al to Kconfig This converts the following to Kconfig: CONFIG_TEGRA_CLOCK_SCALING CONFIG_TEGRA_LP0 CONFIG_TEGRA_PMU Signed-off-by: Tom Rini --- arch/arm/mach-tegra/tegra20/Kconfig | 12 ++++++++++++ arch/arm/mach-tegra/tegra20/warmboot.c | 4 ---- include/configs/seaboard.h | 5 ----- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 5c4d35b567..345563fc78 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -1,5 +1,15 @@ if TEGRA20 +config TEGRA_LP0 + bool + select TEGRA_CLOCK_SCALING + +config TEGRA_PMU + bool + +config TEGRA_CLOCK_SCALING + bool + choice prompt "Tegra20 board select" optional @@ -23,6 +33,8 @@ config TARGET_PLUTUX config TARGET_SEABOARD bool "NVIDIA Seaboard" select BOARD_LATE_INIT + select TEGRA_LP0 + select TEGRA_PMU config TARGET_TEC bool "Avionic Design Tamonten Evaluation Carrier" diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 3d3758f6e6..5e3a9ebace 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -23,10 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_TEGRA_CLOCK_SCALING -#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0" -#endif - /* * This is the place in SRAM where the SDRAM parameters are stored. There * are 4 blocks, one for each RAM code diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 73b738bd09..f272fe9bf8 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -9,11 +9,6 @@ #include -/* LP0 suspend / resume */ -#define CONFIG_TEGRA_LP0 -#define CONFIG_TEGRA_PMU -#define CONFIG_TEGRA_CLOCK_SCALING - #include "tegra20-common.h" /* High-level configuration options */ From 08d01cda45d60af377e94fca05445d2fac232b8d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:37 -0500 Subject: [PATCH 057/424] Nokia RX-51: Migrate legacy USB device options to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move a number of legacy USB UDC options to Kconfig, over from the config header. Cc: Pali Rohár Signed-off-by: Tom Rini --- README | 7 ------- board/nokia/rx51/Kconfig | 30 ++++++++++++++++++++++++++++++ include/configs/nokia_rx51.h | 9 --------- 3 files changed, 30 insertions(+), 16 deletions(-) diff --git a/README b/README index 0acc0b4109..103562bbbe 100644 --- a/README +++ b/README @@ -629,13 +629,6 @@ The following options need to be configured: variable usbtty to be cdc_acm should suffice. The following might be defined in YourBoardName.h - CONFIG_USB_DEVICE - Define this to build a UDC device - - CONFIG_USB_TTY - Define this to have a tty type of device available to - talk to the UDC device - CONFIG_USBD_HS Define this to enable the high speed support for usb device and usbtty. If this feature is enabled, a routine diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig index 7cf05077da..c884543a3d 100644 --- a/board/nokia/rx51/Kconfig +++ b/board/nokia/rx51/Kconfig @@ -1,5 +1,35 @@ if TARGET_NOKIA_RX51 +config USB_DEVICE + def_bool y + help + Legacy UDC device support + +config USB_TTY + def_bool y + help + Legacy tty type of device available to talk to the UDC device + +config USBD_VENDORID + hex + default 0x0421 + +config USBD_PRODUCTID_CDCACM + hex + default 0x01c8 + +config USBD_PRODUCTID_GSERIAL + hex + default 0x01c8 + +config USBD_MANUFACTURER + string + default "Nokia" + +config USBD_PRODUCT_NAME + string + default "N900 (U-Boot)" + config NR_DRAM_BANKS default 2 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 9c364adc63..caaa9ed86b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -49,15 +49,6 @@ #define CFG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY -#define CONFIG_USBD_VENDORID 0x0421 -#define CONFIG_USBD_PRODUCTID_CDCACM 0x01c8 -#define CONFIG_USBD_PRODUCTID_GSERIAL 0x01c8 -#define CONFIG_USBD_MANUFACTURER "Nokia" -#define CONFIG_USBD_PRODUCT_NAME "N900 (U-Boot)" - #define GPIO_SLIDE 71 /* From a9c3bce3626686efc9528c048e9296bb734d988c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:38 -0500 Subject: [PATCH 058/424] Convert CONFIG_USB_GADGET_AT91 to Kconfig This converts the following to Kconfig: CONFIG_USB_GADGET_AT91 Signed-off-by: Tom Rini --- configs/smartweb_defconfig | 1 + configs/taurus_defconfig | 1 + drivers/usb/gadget/Kconfig | 4 ++++ include/configs/smartweb.h | 4 ---- include/configs/taurus.h | 4 ---- 5 files changed, 6 insertions(+), 8 deletions(-) diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 601353c67a..ed0ed2c7bb 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -97,6 +97,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 +CONFIG_USB_GADGET_AT91=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index ef9e444a67..9a1dac78f1 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -115,6 +115,7 @@ CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" CONFIG_USB_GADGET_VENDOR_NUM=0x0908 CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2 +CONFIG_USB_GADGET_AT91=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index e8da73c788..e120efeb00 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -82,6 +82,10 @@ config USB_GADGET_BCM_UDC_OTG_PHY help Enable the Broadcom UDC OTG physical device interface. +config USB_GADGET_AT91 + bool "Atmel AT91 USB Gadget Controller" + depends on ARCH_AT91 + config USB_GADGET_DWC2_OTG bool "DesignWare USB2.0 HS OTG controller (gadget mode)" select USB_GADGET_DUALSPEED diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 794475942a..b988b96e58 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -64,10 +64,6 @@ #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index baaf94e2dd..30f8425582 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -62,10 +62,6 @@ #endif #if defined(CONFIG_BOARD_TAURUS) -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 #endif From be3bea2ba33bc731dbca72576f8b30c587c2e3b3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:39 -0500 Subject: [PATCH 059/424] Convert CONFIG_VSC7385_ENET et al to Kconfig This converts the following to Kconfig: CONFIG_VSC7385_ENET CONFIG_VSC9953 Signed-off-by: Tom Rini --- configs/MPC837XERDB_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + drivers/net/Kconfig | 6 ++++++ include/configs/MPC837XERDB.h | 5 ----- include/configs/T104xRDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 3 --- 25 files changed, 27 insertions(+), 9 deletions(-) diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index b00655824e..1a571cf6bc 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -206,6 +206,7 @@ CONFIG_DM_MDIO=y CONFIG_DM_ETH_PHY=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_RTC_DS1374=y CONFIG_SYS_NS16550_SERIAL=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 79df4a8f01..b9d52a755d 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -139,6 +139,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index d70db00236..f86bc553da 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -121,6 +121,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index b885a2a5f3..0b9e108ba5 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -123,6 +123,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 710a41915c..9f68ede4be 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -101,6 +101,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index f40e001b51..3dd2475643 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -138,6 +138,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index e320ea9b42..bd64dcc9ef 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -120,6 +120,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index d6a188c27e..140d271a19 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -122,6 +122,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index b369b2fad3..3f653895ab 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -100,6 +100,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 7e31f130be..abe064c04e 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -141,6 +141,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index f671d0b1d5..78a54dd461 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -123,6 +123,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 109f03b3b8..a8bdb5a220 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -125,6 +125,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 7f8cba1483..7a533ed41d 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -103,6 +103,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 228c5f9e89..3abb9d7f75 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -144,6 +144,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index ca2b37fcb2..551b5fca8e 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -126,6 +126,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index f83360a87a..493e2c94c1 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -128,6 +128,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 524101022d..fc82fa8ab9 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -106,6 +106,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 4f22e240b2..b6ae81dd42 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -143,6 +143,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 84e0b4e1a1..cfbb3c274e 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -125,6 +125,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index a0ce9a9533..36c6c7e26e 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -127,6 +127,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index e15c487c42..691df7cc21 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -105,6 +105,7 @@ CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_VSC7385_ENET=y CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 029bf3872a..13e434e591 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -676,6 +676,12 @@ config XILINX_AXIMRMAC rates from 10GE to 100GE. This could be present in some of the Xilinx Versal designs. +config VSC7385_ENET + bool "Vitesse 7385 Switch Firmware Upload driver" + +config VSC9953 + bool "Vitesse VSC9953 L2 Switch driver" + config XILINX_EMACLITE select PHYLIB select MII diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index de63a0f199..95a90199a4 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -14,11 +14,6 @@ * High Level Configuration Options */ -/* - * On-board devices - */ -#define CONFIG_VSC7385_ENET - /* System performance - define the value i.e. CONFIG_SYS_XXX */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index d3fd10526b..b6938056bb 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -385,7 +385,6 @@ /* Enable VSC9953 L2 Switch driver on T1040 SoC */ #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_VSC9953 #ifdef CONFIG_TARGET_T1040RDB #define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 #define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c8acce8b06..9738e9fa9c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -13,7 +13,6 @@ #include #if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x5c @@ -43,7 +42,6 @@ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x64 @@ -63,7 +61,6 @@ #endif #if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 From 5afc87eadb0bf3ba55e68dd9ec2f1741ba81508e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:40 -0500 Subject: [PATCH 060/424] net: ftmac100: Remove non-DM_ETH code At this point all users of this driver enable DM_ETH, so remove the legacy code paths. Signed-off-by: Tom Rini Reviewed-by: Ramon Fried --- drivers/net/ftmac100.c | 91 +----------------------------------------- 1 file changed, 2 insertions(+), 89 deletions(-) diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index c30ace96bb..f710c271c6 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -17,10 +17,10 @@ #include #include "ftmac100.h" -#ifdef CONFIG_DM_ETH #include + DECLARE_GLOBAL_DATA_PTR; -#endif + #define ETH_ZLEN 60 struct ftmac100_data { @@ -231,92 +231,6 @@ static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length) return 0; } -#ifndef CONFIG_DM_ETH -/* - * disable transmitter, receiver - */ -static void ftmac100_halt(struct eth_device *dev) -{ - struct ftmac100_data *priv = dev->priv; - return _ftmac100_halt(priv); -} - -static int ftmac100_init(struct eth_device *dev, struct bd_info *bd) -{ - struct ftmac100_data *priv = dev->priv; - return _ftmac100_init(priv , dev->enetaddr); -} - -static int _ftmac100_recv(struct ftmac100_data *priv) -{ - struct ftmac100_rxdes *curr_des; - unsigned short len; - curr_des = &priv->rxdes[priv->rx_index]; - len = __ftmac100_recv(priv); - if (len) { - /* pass the packet up to the protocol layers. */ - net_process_received_packet((void *)curr_des->rxdes2, len); - _ftmac100_free_pkt(priv); - } - return len ? 1 : 0; -} - -/* - * Get a data block via Ethernet - */ -static int ftmac100_recv(struct eth_device *dev) -{ - struct ftmac100_data *priv = dev->priv; - return _ftmac100_recv(priv); -} - -/* - * Send a data block via Ethernet - */ -static int ftmac100_send(struct eth_device *dev, void *packet, int length) -{ - struct ftmac100_data *priv = dev->priv; - return _ftmac100_send(priv , packet , length); -} - -int ftmac100_initialize (struct bd_info *bd) -{ - struct eth_device *dev; - struct ftmac100_data *priv; - dev = malloc (sizeof *dev); - if (!dev) { - printf ("%s(): failed to allocate dev\n", __func__); - goto out; - } - /* Transmit and receive descriptors should align to 16 bytes */ - priv = memalign (16, sizeof (struct ftmac100_data)); - if (!priv) { - printf ("%s(): failed to allocate priv\n", __func__); - goto free_dev; - } - memset (dev, 0, sizeof (*dev)); - memset (priv, 0, sizeof (*priv)); - - strcpy(dev->name, "FTMAC100"); - dev->iobase = CONFIG_FTMAC100_BASE; - dev->init = ftmac100_init; - dev->halt = ftmac100_halt; - dev->send = ftmac100_send; - dev->recv = ftmac100_recv; - dev->priv = priv; - priv->iobase = dev->iobase; - eth_register (dev); - - return 1; - -free_dev: - free (dev); -out: - return 0; -} -#endif - -#ifdef CONFIG_DM_ETH static int ftmac100_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -445,4 +359,3 @@ U_BOOT_DRIVER(ftmac100) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif From 5bacad64627447c4c890ff0b41757cfb09c2204a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:41 -0500 Subject: [PATCH 061/424] configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini --- scripts/config_whitelist.txt | 734 ----------------------------------- 1 file changed, 734 deletions(-) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 3e717bb72a..ccc3a73197 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -37,24 +37,18 @@ CONFIG_FLASH_SHOW_PROGRESS CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FM_PLAT_CLK_DIV -CONFIG_FSL_CADMUS CONFIG_FSL_CPLD -CONFIG_FSL_DEVICE_DISABLE CONFIG_FSL_ESDHC_PIN_MUX CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -CONFIG_FSL_IIM CONFIG_FSL_ISBC_KEY_EXT -CONFIG_FSL_LBC CONFIG_FSL_PMIC_BITLEN CONFIG_FSL_PMIC_BUS CONFIG_FSL_PMIC_CLK CONFIG_FSL_PMIC_CS CONFIG_FSL_PMIC_MODE CONFIG_FSL_SDHC_V2_3 -CONFIG_FSL_SERDES CONFIG_FSL_SERDES1 CONFIG_FSL_SERDES2 -CONFIG_FTMAC100_BASE CONFIG_FTRTC010_EXTCLK CONFIG_FTRTC010_PCLK CONFIG_GATEWAYIP @@ -64,10 +58,8 @@ CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_HDMI_ENCODER_I2C_ADDR -CONFIG_HIKEY_GPIO CONFIG_HOSTNAME CONFIG_HSMMC2_8BIT -CONFIG_HWCONFIG CONFIG_HW_ENV_SETTINGS CONFIG_I2C_ENV_EEPROM_BUS CONFIG_I2C_MULTI_BUS @@ -77,15 +69,7 @@ CONFIG_I2C_MVTWSI_BASE0 CONFIG_I2C_MVTWSI_BASE1 CONFIG_I2C_RTC_ADDR CONFIG_ICS307_REFCLK_HZ -CONFIG_IMX CONFIG_IMX6_PWM_PER_CLK -CONFIG_IMX_HDMI -CONFIG_IMX_VIDEO_SKIP -CONFIG_INTERRUPTS -CONFIG_IODELAY_RECALIBRATION -CONFIG_IOMUX_LPSR -CONFIG_IOMUX_SHARE_CONF_REG -CONFIG_IO_TRACE CONFIG_IPADDR CONFIG_IRAM_BASE CONFIG_IRAM_END @@ -122,7 +106,6 @@ CONFIG_L2_CACHE CONFIG_LEGACY_BOOTCMD_ENV CONFIG_LOWPOWER_ADDR CONFIG_LOWPOWER_FLAG -CONFIG_LPC32XX_HSUART CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY CONFIG_LPC32XX_NAND_MLC_NAND_TA CONFIG_LPC32XX_NAND_MLC_RD_HIGH @@ -138,7 +121,6 @@ CONFIG_LPC32XX_NAND_SLC_WDR_CLKS CONFIG_LPC32XX_NAND_SLC_WHOLD CONFIG_LPC32XX_NAND_SLC_WSETUP CONFIG_LPC32XX_NAND_SLC_WWIDTH -CONFIG_LS102XA_STREAM_ID CONFIG_MACB_SEARCH_PHY CONFIG_MALLOC_F_ADDR CONFIG_MALTA @@ -149,7 +131,6 @@ CONFIG_MEMSIZE_IN_BYTES CONFIG_MEM_INIT_VALUE CONFIG_MFG_ENV_SETTINGS CONFIG_MII_DEFAULT_TSEC -CONFIG_MISC_COMMON CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MIU_2BIT_INTERLEAVED CONFIG_MMC_DEFAULT_DEV @@ -161,8 +142,6 @@ CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MTD_PARTITION CONFIG_MVGBE_PORTS CONFIG_MVS -CONFIG_MX27 -CONFIG_MX27_CLK32 CONFIG_MXC_GPT_HCLK CONFIG_MXC_NAND_HWECC CONFIG_MXC_NAND_IP_REGS_BASE @@ -172,25 +151,19 @@ CONFIG_MXC_USB_FLAGS CONFIG_MXC_USB_PORT CONFIG_MXC_USB_PORTSC CONFIG_MXS -CONFIG_MXS_OCOTP CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC CONFIG_NAND_CS_INIT -CONFIG_NAND_ECC_BCH -CONFIG_NAND_KIRKWOOD -CONFIG_NAND_KMETER1 CONFIG_NAND_OMAP_GPMC_WSCFG CONFIG_NAND_SECBOOT CONFIG_NAND_SPL CONFIG_NETDEV CONFIG_NETMASK CONFIG_NEVER_ASSERT_ODT_TO_CPU -CONFIG_NOBQFMAN CONFIG_NORBOOT CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN CONFIG_OTHBOOTARGS CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_PCA953X CONFIG_PCIE_IMX_PERST_GPIO CONFIG_PCIE_IMX_POWER_GPIO CONFIG_PEN_ADDR_BIG_ENDIAN @@ -207,20 +180,9 @@ CONFIG_POST CONFIG_POSTBOOTMENU CONFIG_POST_EXTERNAL_WORD_FUNCS CONFIG_POST_SKIP_ENV_FLAGS -CONFIG_POWER_FSL -CONFIG_POWER_FSL_MC13892 -CONFIG_POWER_HI6553 -CONFIG_POWER_LTC3676 CONFIG_POWER_LTC3676_I2C_ADDR -CONFIG_POWER_PFUZE100 CONFIG_POWER_PFUZE100_I2C_ADDR -CONFIG_POWER_PFUZE3000 CONFIG_POWER_PFUZE3000_I2C_ADDR -CONFIG_POWER_SPI -CONFIG_POWER_TPS62362 -CONFIG_POWER_TPS65090_EC -CONFIG_POWER_TPS65218 -CONFIG_POWER_TPS65910 CONFIG_PPC_SPINTABLE_COMPATIBLE CONFIG_PRAM CONFIG_PSRAM_SCFG @@ -232,14 +194,6 @@ CONFIG_RD_LVL CONFIG_RESET_VECTOR_ADDRESS CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_ROOTPATH -CONFIG_RTC_DS1337 -CONFIG_RTC_DS1337_NOOSC -CONFIG_RTC_DS1338 -CONFIG_RTC_DS1374 -CONFIG_RTC_DS3231 -CONFIG_RTC_MC13XXX -CONFIG_RTC_MXS -CONFIG_RTC_PT7C4338 CONFIG_SANDBOX_ARCH CONFIG_SANDBOX_SDL CONFIG_SANDBOX_SPI_MAX_BUS @@ -261,700 +215,25 @@ CONFIG_SH_ETHER_PHY_ADDR CONFIG_SH_ETHER_PHY_MODE CONFIG_SH_ETHER_SH7734_MII CONFIG_SH_ETHER_USE_PORT -CONFIG_SH_GPIO_PFC CONFIG_SH_QSPI_BASE CONFIG_SLIC CONFIG_SMDK5420 CONFIG_SMP_PEN_ADDR -CONFIG_SMSC_LPC47M -CONFIG_SMSC_SIO1007 CONFIG_SOCRATES CONFIG_SOFT_I2C_READ_REPEATED_START -CONFIG_SPD_EEPROM CONFIG_SPI_ADDR CONFIG_SPI_BOOTING CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET -CONFIG_SPL_NS16550_MIN_FUNCTIONS -CONFIG_SRIO1 -CONFIG_SRIO2 -CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET -CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 -CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 -CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS -CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE -CONFIG_SRIO_PCIE_BOOT_MASTER -CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK -CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS -CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS -CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE CONFIG_STACKBASE CONFIG_STANDALONE_LOAD_ADDR CONFIG_STD_DEVICES_SETTINGS -CONFIG_SYS_AMASK0 -CONFIG_SYS_AMASK1 -CONFIG_SYS_AMASK1_FINAL -CONFIG_SYS_AMASK2 -CONFIG_SYS_AMASK2_FINAL -CONFIG_SYS_AMASK3 -CONFIG_SYS_AMASK4 -CONFIG_SYS_AMASK6 -CONFIG_SYS_AMASK7 -CONFIG_SYS_AT91_MAIN_CLOCK -CONFIG_SYS_AT91_PLLA -CONFIG_SYS_AT91_PLLB -CONFIG_SYS_AT91_SLOW_CLOCK CONFIG_SYS_BAUDRATE_TABLE -CONFIG_SYS_BMAN_CENA_BASE -CONFIG_SYS_BMAN_CENA_SIZE -CONFIG_SYS_BMAN_CINH_BASE -CONFIG_SYS_BMAN_CINH_SIZE -CONFIG_SYS_BMAN_MEM_BASE -CONFIG_SYS_BMAN_MEM_PHYS -CONFIG_SYS_BMAN_MEM_SIZE -CONFIG_SYS_BMAN_NUM_PORTALS -CONFIG_SYS_BMAN_SP_CENA_SIZE -CONFIG_SYS_BMAN_SP_CINH_SIZE -CONFIG_SYS_BMAN_SWP_ISDR_REG -CONFIG_SYS_BOOTMAPSZ -CONFIG_SYS_CACHE_ACR0 -CONFIG_SYS_CACHE_ACR1 -CONFIG_SYS_CACHE_ACR2 -CONFIG_SYS_CACHE_DCACR -CONFIG_SYS_CACHE_ICACR -CONFIG_SYS_CCSRBAR -CONFIG_SYS_CCSRBAR_PHYS -CONFIG_SYS_CCSRBAR_PHYS_HIGH -CONFIG_SYS_CCSRBAR_PHYS_LOW -CONFIG_SYS_CLK -CONFIG_SYS_CLKTL_CBCDR -CONFIG_SYS_CPLD_AMASK -CONFIG_SYS_CPLD_BASE -CONFIG_SYS_CPLD_BASE_PHYS -CONFIG_SYS_CPLD_CSOR -CONFIG_SYS_CPLD_CSPR -CONFIG_SYS_CPLD_CSPR_EXT -CONFIG_SYS_CPLD_FTIM0 -CONFIG_SYS_CPLD_FTIM1 -CONFIG_SYS_CPLD_FTIM2 -CONFIG_SYS_CPLD_FTIM3 -CONFIG_SYS_CPU_CLK -CONFIG_SYS_CS0_BASE -CONFIG_SYS_CS0_CTRL -CONFIG_SYS_CS0_FTIM0 -CONFIG_SYS_CS0_FTIM1 -CONFIG_SYS_CS0_FTIM2 -CONFIG_SYS_CS0_FTIM3 -CONFIG_SYS_CS0_MASK -CONFIG_SYS_CS1_BASE -CONFIG_SYS_CS1_CTRL -CONFIG_SYS_CS1_FTIM0 -CONFIG_SYS_CS1_FTIM1 -CONFIG_SYS_CS1_FTIM2 -CONFIG_SYS_CS1_FTIM3 -CONFIG_SYS_CS1_MASK -CONFIG_SYS_CS2_BASE -CONFIG_SYS_CS2_CTRL -CONFIG_SYS_CS2_FTIM0 -CONFIG_SYS_CS2_FTIM1 -CONFIG_SYS_CS2_FTIM2 -CONFIG_SYS_CS2_FTIM3 -CONFIG_SYS_CS2_MASK -CONFIG_SYS_CS3_BASE -CONFIG_SYS_CS3_CTRL -CONFIG_SYS_CS3_FTIM0 -CONFIG_SYS_CS3_FTIM1 -CONFIG_SYS_CS3_FTIM2 -CONFIG_SYS_CS3_FTIM3 -CONFIG_SYS_CS3_MASK -CONFIG_SYS_CS4_FTIM0 -CONFIG_SYS_CS4_FTIM1 -CONFIG_SYS_CS4_FTIM2 -CONFIG_SYS_CS4_FTIM3 -CONFIG_SYS_CS6_FTIM0 -CONFIG_SYS_CS6_FTIM1 -CONFIG_SYS_CS6_FTIM2 -CONFIG_SYS_CS6_FTIM3 -CONFIG_SYS_CS7_FTIM0 -CONFIG_SYS_CS7_FTIM1 -CONFIG_SYS_CS7_FTIM2 -CONFIG_SYS_CS7_FTIM3 -CONFIG_SYS_CSOR0 -CONFIG_SYS_CSOR1 -CONFIG_SYS_CSOR2 -CONFIG_SYS_CSOR3 -CONFIG_SYS_CSOR4 -CONFIG_SYS_CSOR6 -CONFIG_SYS_CSOR7 -CONFIG_SYS_CSPR0 -CONFIG_SYS_CSPR0_EXT -CONFIG_SYS_CSPR0_FINAL -CONFIG_SYS_CSPR1 -CONFIG_SYS_CSPR1_EXT -CONFIG_SYS_CSPR1_FINAL -CONFIG_SYS_CSPR2 -CONFIG_SYS_CSPR2_EXT -CONFIG_SYS_CSPR2_FINAL -CONFIG_SYS_CSPR3 -CONFIG_SYS_CSPR3_EXT -CONFIG_SYS_CSPR3_FINAL -CONFIG_SYS_CSPR4 -CONFIG_SYS_CSPR4_EXT -CONFIG_SYS_CSPR6 -CONFIG_SYS_CSPR6_EXT -CONFIG_SYS_CSPR7 -CONFIG_SYS_CSPR7_EXT -CONFIG_SYS_DA850_DDR2_DDRPHYCR -CONFIG_SYS_DA850_DDR2_PBBPR -CONFIG_SYS_DA850_DDR2_SDBCR -CONFIG_SYS_DA850_DDR2_SDBCR2 -CONFIG_SYS_DA850_DDR2_SDRCR -CONFIG_SYS_DA850_DDR2_SDTIMR -CONFIG_SYS_DA850_DDR2_SDTIMR2 -CONFIG_SYS_DA850_PLL0_PLLM -CONFIG_SYS_DA850_PLL1_PLLM -CONFIG_SYS_DA850_SYSCFG_SUSPSRC -CONFIG_SYS_DCACHE_INV -CONFIG_SYS_DCSRBAR -CONFIG_SYS_DCSRBAR_PHYS -CONFIG_SYS_DCSR_DCFG_ADDR -CONFIG_SYS_DCSR_DCFG_OFFSET -CONFIG_SYS_DDRCDR -CONFIG_SYS_DDRCDR_VALUE -CONFIG_SYS_DDRUA -CONFIG_SYS_DDR_BLOCK1_SIZE -CONFIG_SYS_DDR_BLOCK2_BASE -CONFIG_SYS_DDR_CLKSEL -CONFIG_SYS_DDR_CLK_CNTL -CONFIG_SYS_DDR_CLK_CONTROL -CONFIG_SYS_DDR_CLK_CTRL -CONFIG_SYS_DDR_CONFIG -CONFIG_SYS_DDR_CONFIG_2 -CONFIG_SYS_DDR_CONTROL -CONFIG_SYS_DDR_CONTROL_2 -CONFIG_SYS_DDR_CS0_BNDS -CONFIG_SYS_DDR_CS0_CONFIG -CONFIG_SYS_DDR_CS0_CONFIG_2 -CONFIG_SYS_DDR_CS1_BNDS -CONFIG_SYS_DDR_CS1_CONFIG -CONFIG_SYS_DDR_CS1_CONFIG_2 -CONFIG_SYS_DDR_INIT_ADDR -CONFIG_SYS_DDR_INIT_EXT_ADDR -CONFIG_SYS_DDR_INTERVAL -CONFIG_SYS_DDR_MODE -CONFIG_SYS_DDR_MODE2 -CONFIG_SYS_DDR_MODE_1 -CONFIG_SYS_DDR_MODE_2 -CONFIG_SYS_DDR_MODE_CONTROL -CONFIG_SYS_DDR_RCW_1 -CONFIG_SYS_DDR_RCW_2 -CONFIG_SYS_DDR_SDRAM_BASE -CONFIG_SYS_DDR_SDRAM_CFG -CONFIG_SYS_DDR_SDRAM_CFG2 -CONFIG_SYS_DDR_SDRAM_CLK_CNTL -CONFIG_SYS_DDR_SR_CNTR -CONFIG_SYS_DDR_TIMING_0 -CONFIG_SYS_DDR_TIMING_1 -CONFIG_SYS_DDR_TIMING_2 -CONFIG_SYS_DDR_TIMING_3 -CONFIG_SYS_DDR_TIMING_4 -CONFIG_SYS_DDR_TIMING_5 -CONFIG_SYS_DDR_WRLVL_CONTROL -CONFIG_SYS_DDR_ZQ_CONTROL -CONFIG_SYS_DIALOG_PMIC_I2C_ADDR -CONFIG_SYS_DPAA_DCE -CONFIG_SYS_DPAA_FMAN -CONFIG_SYS_DPAA_PME -CONFIG_SYS_DPAA_RMAN -CONFIG_SYS_DRAM_TEST -CONFIG_SYS_DV_NOR_BOOT_CFG -CONFIG_SYS_ENV_SECT_SIZE -CONFIG_SYS_ETHOC_BASE -CONFIG_SYS_ETHOC_BUFFER_ADDR -CONFIG_SYS_EXCEPTION_VECTORS_HIGH -CONFIG_SYS_FAST_CLK -CONFIG_SYS_FEC_BUF_USE_SRAM -CONFIG_SYS_FLASH0 -CONFIG_SYS_FLASH1 -CONFIG_SYS_FLASH1_BASE_PHYS -CONFIG_SYS_FLASH1_BASE_PHYS_EARLY -CONFIG_SYS_FLASH_BANKS_LIST -CONFIG_SYS_FLASH_BANKS_SIZES -CONFIG_SYS_FLASH_BASE -CONFIG_SYS_FLASH_BASE_PHYS -CONFIG_SYS_FLASH_BASE_PHYS_EARLY -CONFIG_SYS_FLASH_PARMSECT_SZ -CONFIG_SYS_FLASH_SIZE -CONFIG_SYS_FM1_10GEC1_PHY_ADDR -CONFIG_SYS_FM1_CLK -CONFIG_SYS_FM1_DTSEC1_PHY_ADDR -CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR -CONFIG_SYS_FM1_DTSEC2_PHY_ADDR -CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR -CONFIG_SYS_FM1_DTSEC3_PHY_ADDR -CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR -CONFIG_SYS_FM1_DTSEC4_PHY_ADDR -CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR -CONFIG_SYS_FM1_DTSEC5_PHY_ADDR -CONFIG_SYS_FM1_QSGMII11_PHY_ADDR -CONFIG_SYS_FM1_QSGMII21_PHY_ADDR -CONFIG_SYS_FM2_CLK -CONFIG_SYS_FM_MURAM_SIZE -CONFIG_SYS_FPGAREG_DIPSW -CONFIG_SYS_FPGAREG_FREQ -CONFIG_SYS_FPGAREG_RESET -CONFIG_SYS_FPGAREG_RESET_CODE -CONFIG_SYS_FPGA_AMASK -CONFIG_SYS_FPGA_BASE -CONFIG_SYS_FPGA_CSOR -CONFIG_SYS_FPGA_CSPR -CONFIG_SYS_FPGA_CSPR_EXT -CONFIG_SYS_FPGA_FTIM0 -CONFIG_SYS_FPGA_FTIM1 -CONFIG_SYS_FPGA_FTIM2 -CONFIG_SYS_FPGA_FTIM3 -CONFIG_SYS_FPGA_SIZE -CONFIG_SYS_FPGA_WAIT -CONFIG_SYS_GPIO1_EN -CONFIG_SYS_GPIO1_FUNC -CONFIG_SYS_GPIO1_LED -CONFIG_SYS_GPIO1_OUT -CONFIG_SYS_GPIO_EN -CONFIG_SYS_GPIO_FUNC -CONFIG_SYS_GPIO_OUT -CONFIG_SYS_GPR1 -CONFIG_SYS_HZ_CLOCK -CONFIG_SYS_I2C_BUSES -CONFIG_SYS_I2C_EXPANDER_ADDR -CONFIG_SYS_I2C_FPGA_ADDR -CONFIG_SYS_I2C_G762_ADDR -CONFIG_SYS_I2C_IFDR_DIV -CONFIG_SYS_I2C_MAX_HOPS -CONFIG_SYS_I2C_NOPROBES -CONFIG_SYS_I2C_PCA953X_ADDR -CONFIG_SYS_I2C_PCA953X_WIDTH -CONFIG_SYS_I2C_PCA9557_ADDR -CONFIG_SYS_I2C_PINMUX_CLR -CONFIG_SYS_I2C_PINMUX_REG -CONFIG_SYS_I2C_PINMUX_SET -CONFIG_SYS_I2C_RTC_ADDR -CONFIG_SYS_I2C_TCA642X_ADDR -CONFIG_SYS_I2C_TCA642X_BUS_NUM -CONFIG_SYS_ICACHE_INV -CONFIG_SYS_IFC_ADDR -CONFIG_SYS_IFC_CCR -CONFIG_SYS_INIT_DBCR -CONFIG_SYS_INIT_L2CSR0 -CONFIG_SYS_INIT_L2_ADDR -CONFIG_SYS_INIT_L2_ADDR_PHYS -CONFIG_SYS_INIT_L2_END -CONFIG_SYS_INIT_L3_ADDR -CONFIG_SYS_INIT_L3_ADDR_PHYS -CONFIG_SYS_INIT_L3_VADDR -CONFIG_SYS_INIT_RAM_ADDR -CONFIG_SYS_INIT_RAM_ADDR_PHYS -CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH -CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW -CONFIG_SYS_INIT_RAM_CTRL -CONFIG_SYS_INIT_RAM_SIZE -CONFIG_SYS_INIT_SP_OFFSET -CONFIG_SYS_INT_FLASH_BASE -CONFIG_SYS_INT_FLASH_ENABLE -CONFIG_SYS_IO_BASE -CONFIG_SYS_KMBEC_FPGA_BASE -CONFIG_SYS_KMBEC_FPGA_SIZE -CONFIG_SYS_LATCH_ADDR -CONFIG_SYS_LBC_ADDR -CONFIG_SYS_LBC_FLASH_BASE -CONFIG_SYS_LBC_LBCR -CONFIG_SYS_LBC_LCRR -CONFIG_SYS_LBC_LSDMR_COMMON -CONFIG_SYS_LBC_LSRT -CONFIG_SYS_LBC_MRTPR -CONFIG_SYS_LBC_SDRAM_BASE -CONFIG_SYS_LBC_SDRAM_BASE_PHYS -CONFIG_SYS_LBC_SDRAM_SIZE -CONFIG_SYS_LDB_CLOCK -CONFIG_SYS_LIME_BASE -CONFIG_SYS_LOW -CONFIG_SYS_LOWMEM_BASE -CONFIG_SYS_LPAE_SDRAM_BASE -CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH -CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS -CONFIG_SYS_LS_MC_DPC_MAX_LENGTH -CONFIG_SYS_LS_MC_DPL_MAX_LENGTH -CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET -CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE -CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET -CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET -CONFIG_SYS_MAIN_PWR_ON -CONFIG_SYS_MASTER_CLOCK -CONFIG_SYS_MATRIX_EBI0CSA_VAL -CONFIG_SYS_MATRIX_EBICSA_VAL -CONFIG_SYS_MAX_I2C_BUS -CONFIG_SYS_MAX_NAND_CHIPS -CONFIG_SYS_MBAR -CONFIG_SYS_MBAR2 -CONFIG_SYS_MCKR -CONFIG_SYS_MCKR1_VAL -CONFIG_SYS_MCKR2_VAL -CONFIG_SYS_MCKR_CSS -CONFIG_SYS_MDIO1_OFFSET -CONFIG_SYS_MEMORY_BASE -CONFIG_SYS_MEM_RESERVE_SECURE -CONFIG_SYS_MFD -CONFIG_SYS_MMC_CD_PIN -CONFIG_SYS_MMC_CLK_OD -CONFIG_SYS_MMC_U_BOOT_DST -CONFIG_SYS_MMC_U_BOOT_OFFS -CONFIG_SYS_MMC_U_BOOT_SIZE -CONFIG_SYS_MMC_U_BOOT_START -CONFIG_SYS_MOR_VAL -CONFIG_SYS_MRAM_BASE -CONFIG_SYS_NAND_AMASK -CONFIG_SYS_NAND_BASE -CONFIG_SYS_NAND_BASE2 -CONFIG_SYS_NAND_BASE_LIST -CONFIG_SYS_NAND_BASE_PHYS -CONFIG_SYS_NAND_BR_PRELIM -CONFIG_SYS_NAND_CS -CONFIG_SYS_NAND_CSOR -CONFIG_SYS_NAND_CSPR -CONFIG_SYS_NAND_CSPR_EXT -CONFIG_SYS_NAND_DATA_BASE -CONFIG_SYS_NAND_DBW_8 -CONFIG_SYS_NAND_DDR_LAW -CONFIG_SYS_NAND_ECCBYTES -CONFIG_SYS_NAND_ECCPOS -CONFIG_SYS_NAND_ECCSIZE -CONFIG_SYS_NAND_ECCSTEPS -CONFIG_SYS_NAND_ECCTOTAL -CONFIG_SYS_NAND_ECC_BASE -CONFIG_SYS_NAND_ENABLE_PIN -CONFIG_SYS_NAND_ENABLE_PIN_SPL -CONFIG_SYS_NAND_FTIM0 -CONFIG_SYS_NAND_FTIM1 -CONFIG_SYS_NAND_FTIM2 -CONFIG_SYS_NAND_FTIM3 -CONFIG_SYS_NAND_HW_ECC -CONFIG_SYS_NAND_HW_ECC_OOBFIRST -CONFIG_SYS_NAND_LARGEPAGE -CONFIG_SYS_NAND_MASK_ALE -CONFIG_SYS_NAND_MASK_CLE -CONFIG_SYS_NAND_MAX_ECCPOS -CONFIG_SYS_NAND_MAX_OOBFREE -CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES -CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -CONFIG_SYS_NAND_OR_PRELIM -CONFIG_SYS_NAND_PAGE_2K -CONFIG_SYS_NAND_PAGE_4K -CONFIG_SYS_NAND_READY_PIN -CONFIG_SYS_NAND_REGS_BASE -CONFIG_SYS_NAND_SIZE -CONFIG_SYS_NAND_U_BOOT_DST -CONFIG_SYS_NAND_U_BOOT_RELOC_SP -CONFIG_SYS_NAND_U_BOOT_SIZE -CONFIG_SYS_NAND_U_BOOT_START -CONFIG_SYS_NOR0_CSPR -CONFIG_SYS_NOR0_CSPR_EARLY -CONFIG_SYS_NOR0_CSPR_EXT -CONFIG_SYS_NOR1_CSPR -CONFIG_SYS_NOR1_CSPR_EARLY -CONFIG_SYS_NOR1_CSPR_EXT -CONFIG_SYS_NOR_AMASK -CONFIG_SYS_NOR_AMASK_EARLY -CONFIG_SYS_NOR_CSOR -CONFIG_SYS_NOR_CSPR -CONFIG_SYS_NOR_CSPR_EXT -CONFIG_SYS_NOR_FTIM0 -CONFIG_SYS_NOR_FTIM1 -CONFIG_SYS_NOR_FTIM2 -CONFIG_SYS_NOR_FTIM3 -CONFIG_SYS_NS16550_CLK -CONFIG_SYS_NS16550_COM1 -CONFIG_SYS_NS16550_COM2 -CONFIG_SYS_NS16550_COM3 -CONFIG_SYS_NS16550_COM4 -CONFIG_SYS_NS16550_COM5 -CONFIG_SYS_NS16550_COM6 -CONFIG_SYS_NS16550_MEM32 -CONFIG_SYS_NS16550_PORT_MAPPED -CONFIG_SYS_NS16550_REG_SIZE -CONFIG_SYS_NS16550_SERIAL -CONFIG_SYS_NUM_CPC -CONFIG_SYS_NUM_FM1_10GEC -CONFIG_SYS_NUM_FM1_DTSEC -CONFIG_SYS_NUM_FM2_10GEC -CONFIG_SYS_NUM_FM2_DTSEC -CONFIG_SYS_NUM_FMAN -CONFIG_SYS_NUM_I2C_BUSES -CONFIG_SYS_NVRAM_BASE_ADDR -CONFIG_SYS_NVRAM_SIZE -CONFIG_SYS_OBIR -CONFIG_SYS_OMAP_ABE_SYSCK -CONFIG_SYS_ONENAND_BASE -CONFIG_SYS_ONENAND_BLOCK_SIZE -CONFIG_SYS_OSCIN_FREQ -CONFIG_SYS_OSPR_OFFSET -CONFIG_SYS_PACNT -CONFIG_SYS_PADAT -CONFIG_SYS_PADDR -CONFIG_SYS_PAGE_SIZE -CONFIG_SYS_PAMU_ADDR -CONFIG_SYS_PASPAR -CONFIG_SYS_PAXE_BASE -CONFIG_SYS_PAXE_SIZE -CONFIG_SYS_PBCNT -CONFIG_SYS_PBDAT -CONFIG_SYS_PBDDR -CONFIG_SYS_PBI_FLASH_BASE -CONFIG_SYS_PBI_FLASH_WINDOW -CONFIG_SYS_PCCNT -CONFIG_SYS_PCDAT -CONFIG_SYS_PCDDR -CONFIG_SYS_PCI -CONFIG_SYS_PCI1_ADDR -CONFIG_SYS_PCI1_IO_BASE -CONFIG_SYS_PCI1_IO_BUS -CONFIG_SYS_PCI1_IO_PHYS -CONFIG_SYS_PCI1_IO_SIZE -CONFIG_SYS_PCI1_IO_VIRT -CONFIG_SYS_PCI1_MEM_BASE -CONFIG_SYS_PCI1_MEM_BUS -CONFIG_SYS_PCI1_MEM_PHYS -CONFIG_SYS_PCI1_MEM_SIZE -CONFIG_SYS_PCI1_MEM_VIRT -CONFIG_SYS_PCI2_ADDR -CONFIG_SYS_PCIE -CONFIG_SYS_PCIE1_ADDR -CONFIG_SYS_PCIE1_CFG_BASE -CONFIG_SYS_PCIE1_CFG_SIZE -CONFIG_SYS_PCIE1_IO_PHYS -CONFIG_SYS_PCIE1_IO_VIRT -CONFIG_SYS_PCIE1_MEM_PHYS -CONFIG_SYS_PCIE1_MEM_VIRT -CONFIG_SYS_PCIE1_PHYS_ADDR -CONFIG_SYS_PCIE1_PHYS_BASE -CONFIG_SYS_PCIE1_VIRT_ADDR -CONFIG_SYS_PCIE2_ADDR -CONFIG_SYS_PCIE2_CFG_BASE -CONFIG_SYS_PCIE2_CFG_SIZE -CONFIG_SYS_PCIE2_IO_PHYS -CONFIG_SYS_PCIE2_IO_VIRT -CONFIG_SYS_PCIE2_MEM_PHYS -CONFIG_SYS_PCIE2_MEM_VIRT -CONFIG_SYS_PCIE2_PHYS_ADDR -CONFIG_SYS_PCIE2_PHYS_BASE -CONFIG_SYS_PCIE2_VIRT_ADDR -CONFIG_SYS_PCIE3_ADDR -CONFIG_SYS_PCIE3_IO_PHYS -CONFIG_SYS_PCIE3_IO_VIRT -CONFIG_SYS_PCIE3_MEM_PHYS -CONFIG_SYS_PCIE3_MEM_VIRT -CONFIG_SYS_PCIE3_PHYS_ADDR -CONFIG_SYS_PCIE3_PHYS_SIZE -CONFIG_SYS_PCIE4_ADDR -CONFIG_SYS_PCIE4_IO_PHYS -CONFIG_SYS_PCIE4_IO_VIRT -CONFIG_SYS_PCIE4_MEM_BUS -CONFIG_SYS_PCIE4_MEM_PHYS -CONFIG_SYS_PCIE4_MEM_VIRT -CONFIG_SYS_PCIE4_PHYS_ADDR -CONFIG_SYS_PCIE_MMAP_SIZE -CONFIG_SYS_PDCNT -CONFIG_SYS_PEHLPAR -CONFIG_SYS_PIOC_PDR_VAL -CONFIG_SYS_PIOC_PDR_VAL1 -CONFIG_SYS_PIOC_PPUDR_VAL -CONFIG_SYS_PIOD_PDR_VAL1 -CONFIG_SYS_PIOD_PPUDR_VAL -CONFIG_SYS_PJPAR -CONFIG_SYS_PL310_BASE -CONFIG_SYS_PLLAR_VAL -CONFIG_SYS_PLLCR -CONFIG_SYS_PLL_BYPASS -CONFIG_SYS_PLL_FDR -CONFIG_SYS_PLL_ODR -CONFIG_SYS_PLL_SETTLING_TIME -CONFIG_SYS_PMAN -CONFIG_SYS_PME_CLK -CONFIG_SYS_POST_MEMORY -CONFIG_SYS_POST_MEM_REGIONS -CONFIG_SYS_PUAPAR -CONFIG_SYS_QMAN_CENA_BASE -CONFIG_SYS_QMAN_CENA_SIZE -CONFIG_SYS_QMAN_CINH_BASE -CONFIG_SYS_QMAN_CINH_SIZE -CONFIG_SYS_QMAN_MEM_BASE -CONFIG_SYS_QMAN_MEM_PHYS -CONFIG_SYS_QMAN_MEM_SIZE -CONFIG_SYS_QMAN_NUM_PORTALS -CONFIG_SYS_QMAN_SP_CENA_SIZE -CONFIG_SYS_QMAN_SP_CINH_SIZE -CONFIG_SYS_QMAN_SWP_ISDR_REG -CONFIG_SYS_QRIO_BASE -CONFIG_SYS_QRIO_BASE_PHYS -CONFIG_SYS_RCAR_I2C0_BASE -CONFIG_SYS_RCAR_I2C1_BASE -CONFIG_SYS_RCAR_I2C2_BASE -CONFIG_SYS_RCAR_I2C3_BASE -CONFIG_SYS_RFD -CONFIG_SYS_RGMII1_PHY_ADDR -CONFIG_SYS_RGMII2_PHY_ADDR -CONFIG_SYS_ROM_BASE -CONFIG_SYS_RSTC_RMR_VAL -CONFIG_SYS_RTC_BUS_NUM -CONFIG_SYS_RTC_CNT -CONFIG_SYS_RTC_SETUP -CONFIG_SYS_SATA -CONFIG_SYS_SATA_FAT_BOOT_PARTITION -CONFIG_SYS_SBFHDR_DATA_OFFSET -CONFIG_SYS_SBFHDR_SIZE -CONFIG_SYS_SCCR_SATACM -CONFIG_SYS_SCCR_TSEC1CM -CONFIG_SYS_SCCR_TSEC2CM -CONFIG_SYS_SCCR_USBDRCM -CONFIG_SYS_SCR -CONFIG_SYS_SDRAM -CONFIG_SYS_SDRAM_BASE -CONFIG_SYS_SDRAM_BASE0 -CONFIG_SYS_SDRAM_BASE1 -CONFIG_SYS_SDRAM_BASE2 -CONFIG_SYS_SDRAM_CFG1 -CONFIG_SYS_SDRAM_CFG2 -CONFIG_SYS_SDRAM_CTRL -CONFIG_SYS_SDRAM_EMOD -CONFIG_SYS_SDRAM_MODE -CONFIG_SYS_SDRAM_SIZE -CONFIG_SYS_SDRAM_SIZE0 -CONFIG_SYS_SDRAM_SIZE_LAW -CONFIG_SYS_SDRAM_VAL -CONFIG_SYS_SDRAM_VAL1 -CONFIG_SYS_SDRAM_VAL10 -CONFIG_SYS_SDRAM_VAL11 -CONFIG_SYS_SDRAM_VAL12 -CONFIG_SYS_SDRAM_VAL2 -CONFIG_SYS_SDRAM_VAL3 -CONFIG_SYS_SDRAM_VAL4 -CONFIG_SYS_SDRAM_VAL5 -CONFIG_SYS_SDRAM_VAL6 -CONFIG_SYS_SDRAM_VAL7 -CONFIG_SYS_SDRAM_VAL8 -CONFIG_SYS_SDRAM_VAL9 -CONFIG_SYS_SDRC_CR_VAL -CONFIG_SYS_SDRC_MDR_VAL -CONFIG_SYS_SDRC_MR_VAL -CONFIG_SYS_SDRC_MR_VAL1 -CONFIG_SYS_SDRC_MR_VAL2 -CONFIG_SYS_SDRC_MR_VAL3 -CONFIG_SYS_SDRC_MR_VAL4 -CONFIG_SYS_SDRC_MR_VAL5 -CONFIG_SYS_SDRC_TR_VAL -CONFIG_SYS_SDRC_TR_VAL1 -CONFIG_SYS_SDRC_TR_VAL2 -CONFIG_SYS_SEC_MON_ADDR -CONFIG_SYS_SEC_MON_OFFSET -CONFIG_SYS_SERIAL0 -CONFIG_SYS_SERIAL1 -CONFIG_SYS_SERIAL2 -CONFIG_SYS_SERIAL3 -CONFIG_SYS_SFP_ADDR -CONFIG_SYS_SFP_OFFSET -CONFIG_SYS_SGMII1_PHY_ADDR -CONFIG_SYS_SGMII2_PHY_ADDR -CONFIG_SYS_SGMII3_PHY_ADDR -CONFIG_SYS_SGMII_LINERATE_MHZ -CONFIG_SYS_SGMII_RATESCALE -CONFIG_SYS_SGMII_REFCLK_MHZ -CONFIG_SYS_SH_SDHI0_BASE -CONFIG_SYS_SH_SDHI1_BASE -CONFIG_SYS_SH_SDHI2_BASE -CONFIG_SYS_SH_SDHI3_BASE -CONFIG_SYS_SH_SDHI_NR_CHANNEL -CONFIG_SYS_SICRH -CONFIG_SYS_SICRL -CONFIG_SYS_SMC0_CYCLE0_VAL -CONFIG_SYS_SMC0_MODE0_VAL -CONFIG_SYS_SMC0_PULSE0_VAL -CONFIG_SYS_SMC0_SETUP0_VAL -CONFIG_SYS_SPI_ARGS_OFFS -CONFIG_SYS_SPI_ARGS_SIZE -CONFIG_SYS_SPI_BASE -CONFIG_SYS_SPI_CLK -CONFIG_SYS_SPI_FLASH_U_BOOT_DST -CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS -CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE -CONFIG_SYS_SPI_FLASH_U_BOOT_START -CONFIG_SYS_SPI_KERNEL_OFFS -CONFIG_SYS_SPI_ST_ENABLE_WP_PIN -CONFIG_SYS_SPI_U_BOOT_SIZE -CONFIG_SYS_SPL_MALLOC_START -CONFIG_SYS_SPR -CONFIG_SYS_SRIO -CONFIG_SYS_SRIO1_MEM_PHYS -CONFIG_SYS_SRIO1_MEM_SIZE -CONFIG_SYS_SRIO1_MEM_VIRT -CONFIG_SYS_SRIO2_MEM_PHYS -CONFIG_SYS_SRIO2_MEM_SIZE -CONFIG_SYS_SRIO2_MEM_VIRT -CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR -CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS -CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR -CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS -CONFIG_SYS_SST_SECT -CONFIG_SYS_SST_SECTSZ -CONFIG_SYS_STACK_SIZE -CONFIG_SYS_TBIPA_VALUE -CONFIG_SYS_TCLK -CONFIG_SYS_TIMERBASE -CONFIG_SYS_TIMER_BASE -CONFIG_SYS_TIMER_COUNTER -CONFIG_SYS_TIMER_COUNTS_DOWN -CONFIG_SYS_TIMER_RATE -CONFIG_SYS_TMPVIRT -CONFIG_SYS_TSEC1_OFFSET -CONFIG_SYS_TX_ETH_BUFFER -CONFIG_SYS_UART2_ALT3_GPIO -CONFIG_SYS_UART_PORT -CONFIG_SYS_UBOOT_BASE -CONFIG_SYS_UBOOT_START -CONFIG_SYS_UEC -CONFIG_SYS_UEC2_PHY_ADDR -CONFIG_SYS_USB_OHCI_REGS_BASE -CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR -CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN -CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT -CONFIG_SYS_VCXK_BASE -CONFIG_SYS_VCXK_DEFAULT_LINEALIGN -CONFIG_SYS_VCXK_DOUBLEBUFFERED -CONFIG_SYS_VCXK_ENABLE_DDR -CONFIG_SYS_VCXK_ENABLE_PIN -CONFIG_SYS_VCXK_ENABLE_PORT -CONFIG_SYS_VCXK_INVERT_DDR -CONFIG_SYS_VCXK_INVERT_PIN -CONFIG_SYS_VCXK_INVERT_PORT -CONFIG_SYS_VCXK_REQUEST_DDR -CONFIG_SYS_VCXK_REQUEST_PIN -CONFIG_SYS_VCXK_REQUEST_PORT -CONFIG_SYS_VSC7385_BASE -CONFIG_SYS_VSC7385_BASE_PHYS -CONFIG_SYS_VSC7385_BR_PRELIM -CONFIG_SYS_VSC7385_OR_PRELIM -CONFIG_SYS_WATCHDOG_VALUE -CONFIG_SYS_WDTC_WDMR_VAL -CONFIG_SYS_WRITE_SWAPPED_DATA -CONFIG_SYS_XHCI_USB1_ADDR -CONFIG_SYS_XHCI_USB2_ADDR -CONFIG_SYS_XHCI_USB3_ADDR -CONFIG_TCA642X CONFIG_TEGRA_BOARD_STRING -CONFIG_TEGRA_CLOCK_SCALING CONFIG_TEGRA_ENABLE_UARTA CONFIG_TEGRA_ENABLE_UARTD -CONFIG_TEGRA_LP0 -CONFIG_TEGRA_PMU CONFIG_TEGRA_SLINK_CTRLS CONFIG_TEGRA_SPI CONFIG_TEGRA_UARTA_GPU @@ -964,9 +243,7 @@ CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 CONFIG_TESTPIN_MASK CONFIG_TESTPIN_REG CONFIG_THOR_RESET_OFF -CONFIG_TMU_TIMER CONFIG_TPM_TIS_BASE_ADDRESS -CONFIG_TPS6586X_POWER CONFIG_TSEC CONFIG_TSEC1 CONFIG_TSEC1_NAME @@ -979,7 +256,6 @@ CONFIG_TSEC4_NAME CONFIG_TSECV2 CONFIG_TSECV2_1 CONFIG_TSEC_TBICR_SETTINGS -CONFIG_TWL6030_POWER CONFIG_UBIFS_VOLUME CONFIG_UBI_PART CONFIG_UBOOTPATH @@ -990,25 +266,15 @@ CONFIG_UEC_ETH2 CONFIG_USART_BASE CONFIG_USART_ID CONFIG_USBD_HS -CONFIG_USBD_MANUFACTURER -CONFIG_USBD_PRODUCTID_CDCACM -CONFIG_USBD_PRODUCTID_GSERIAL -CONFIG_USBD_PRODUCT_NAME -CONFIG_USBD_VENDORID CONFIG_USB_BOOTING -CONFIG_USB_DEVICE CONFIG_USB_EXT2_BOOT CONFIG_USB_FAT_BOOT -CONFIG_USB_GADGET_AT91 CONFIG_USB_ISP1301_I2C_ADDR -CONFIG_USB_TTY CONFIG_U_BOOT_HDR_SIZE CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM -CONFIG_VSC7385_ENET CONFIG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE -CONFIG_VSC9953 CONFIG_WATCHDOG_PRESC CONFIG_WATCHDOG_RC CONFIG_WATCHDOG_TIMEOUT From 17f13e7119cc628bc26edf12252794770247df63 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:42 -0500 Subject: [PATCH 062/424] scripts/config_whitelist.txt: Remove more referenced symbols Perform some deeper investigation on the remaining symbols listed in this file and remove more. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- include/configs/P1010RDB.h | 2 -- scripts/config_whitelist.txt | 21 --------------------- 2 files changed, 23 deletions(-) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c0805f979b..b1d6b15811 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -173,8 +173,6 @@ extern unsigned long get_sdram_size(void); #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE #endif -#define CONFIG_MTD_PARTITION - #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ccc3a73197..12c23a5dfd 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,5 +1,4 @@ CONFIG_ARM_GIC_BASE_ADDRESS -CONFIG_AUTO_ZRELADDR CONFIG_BOARDDIR CONFIG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC @@ -8,7 +7,6 @@ CONFIG_DFU_ALT_SYSTEM CONFIG_DFU_ENV_SETTINGS CONFIG_DM9000_BASE CONFIG_DM9000_BYTE_SWAPPED -CONFIG_DM9000_DEBUG CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT CONFIG_DW_WDT_CLOCK_KHZ @@ -49,8 +47,6 @@ CONFIG_FSL_PMIC_MODE CONFIG_FSL_SDHC_V2_3 CONFIG_FSL_SERDES1 CONFIG_FSL_SERDES2 -CONFIG_FTRTC010_EXTCLK -CONFIG_FTRTC010_PCLK CONFIG_GATEWAYIP CONFIG_GMII CONFIG_G_DNL_THOR_PRODUCT_NUM @@ -64,7 +60,6 @@ CONFIG_HW_ENV_SETTINGS CONFIG_I2C_ENV_EEPROM_BUS CONFIG_I2C_MULTI_BUS CONFIG_I2C_MVTWSI -CONFIG_I2C_MVTWSI_BASE CONFIG_I2C_MVTWSI_BASE0 CONFIG_I2C_MVTWSI_BASE1 CONFIG_I2C_RTC_ADDR @@ -136,12 +131,8 @@ CONFIG_MIU_2BIT_INTERLEAVED CONFIG_MMC_DEFAULT_DEV CONFIG_MMC_SUNXI_SLOT CONFIG_MONITOR_IS_IN_RAM -CONFIG_MPC85XX_FEC -CONFIG_MPC85XX_FEC_NAME CONFIG_MTD_NAND_VERIFY_WRITE -CONFIG_MTD_PARTITION CONFIG_MVGBE_PORTS -CONFIG_MVS CONFIG_MXC_GPT_HCLK CONFIG_MXC_NAND_HWECC CONFIG_MXC_NAND_IP_REGS_BASE @@ -150,15 +141,10 @@ CONFIG_MXC_UART_BASE CONFIG_MXC_USB_FLAGS CONFIG_MXC_USB_PORT CONFIG_MXC_USB_PORTSC -CONFIG_MXS CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC CONFIG_NAND_CS_INIT -CONFIG_NAND_OMAP_GPMC_WSCFG -CONFIG_NAND_SECBOOT -CONFIG_NAND_SPL CONFIG_NETDEV CONFIG_NETMASK -CONFIG_NEVER_ASSERT_ODT_TO_CPU CONFIG_NORBOOT CONFIG_NUM_DSP_CPUS CONFIG_ODROID_REV_AIN @@ -174,12 +160,10 @@ CONFIG_PHY_INTERFACE_MODE CONFIG_PHY_IRAM_BASE CONFIG_PL011_CLOCK CONFIG_PL01x_PORTS -CONFIG_PM CONFIG_PME_PLAT_CLK_DIV CONFIG_POST CONFIG_POSTBOOTMENU CONFIG_POST_EXTERNAL_WORD_FUNCS -CONFIG_POST_SKIP_ENV_FLAGS CONFIG_POWER_LTC3676_I2C_ADDR CONFIG_POWER_PFUZE100_I2C_ADDR CONFIG_POWER_PFUZE3000_I2C_ADDR @@ -204,7 +188,6 @@ CONFIG_SCIF_A CONFIG_SCSI_DEV_LIST CONFIG_SC_TIMER_CLK CONFIG_SERIAL_BOOT -CONFIG_SERIAL_SOFTWARE_FIFO CONFIG_SERVERIP CONFIG_SETUP_INITRD_TAG CONFIG_SET_DFU_ALT_BUF_LEN @@ -213,14 +196,12 @@ CONFIG_SH_ETHER_CACHE_INVALIDATE CONFIG_SH_ETHER_CACHE_WRITEBACK CONFIG_SH_ETHER_PHY_ADDR CONFIG_SH_ETHER_PHY_MODE -CONFIG_SH_ETHER_SH7734_MII CONFIG_SH_ETHER_USE_PORT CONFIG_SH_QSPI_BASE CONFIG_SLIC CONFIG_SMDK5420 CONFIG_SMP_PEN_ADDR CONFIG_SOCRATES -CONFIG_SOFT_I2C_READ_REPEATED_START CONFIG_SPI_ADDR CONFIG_SPI_BOOTING CONFIG_SPI_FLASH_QUAD @@ -244,7 +225,6 @@ CONFIG_TESTPIN_MASK CONFIG_TESTPIN_REG CONFIG_THOR_RESET_OFF CONFIG_TPM_TIS_BASE_ADDRESS -CONFIG_TSEC CONFIG_TSEC1 CONFIG_TSEC1_NAME CONFIG_TSEC2 @@ -262,7 +242,6 @@ CONFIG_UBOOTPATH CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_UEC_ETH -CONFIG_UEC_ETH2 CONFIG_USART_BASE CONFIG_USART_ID CONFIG_USBD_HS From d948c8988c212bc8fe94db556b7ef265d2e96452 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:43 -0500 Subject: [PATCH 063/424] sandbox: Rework how SDL is enabled / disabled Given that we can use Kconfig logic directly to see if we have a program available on the host or not, change from passing NO_SDL to instead controlling CONFIG_SANDBOX_SDL in Kconfig directly. Introduce CONFIG_HOST_HAS_SDL as the way to test for sdl2-config and default CONFIG_SANDBOX_SDL on if we have that, or not. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .azure-pipelines.yml | 4 ++-- arch/sandbox/Kconfig | 7 +++++++ arch/sandbox/config.mk | 4 +--- doc/arch/sandbox/sandbox.rst | 9 +++------ doc/build/tools.rst | 2 +- drivers/video/Kconfig | 2 +- include/configs/sandbox.h | 4 ---- 7 files changed, 15 insertions(+), 17 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d02c6636ff..add8847225 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -30,7 +30,7 @@ stages: %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel" displayName: 'Install Toolchain' - script: | - echo make tools-only_defconfig tools-only NO_SDL=1 > build-tools.sh + echo make tools-only_defconfig tools-only > build-tools.sh %CD:~0,2%\msys64\usr\bin\bash -lc "bash build-tools.sh" displayName: 'Build Host Tools' env: @@ -47,7 +47,7 @@ stages: - script: brew install make ossp-uuid displayName: Brew install dependencies - script: | - gmake tools-only_config tools-only NO_SDL=1 \ + gmake tools-only_config tools-only \ HOSTCFLAGS="-I/usr/local/opt/openssl@1.1/include" \ HOSTLDFLAGS="-L/usr/local/opt/openssl@1.1/lib" \ -j$(sysctl -n hw.logicalcpu) diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 96b3402b47..0ce77de2fc 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -47,6 +47,13 @@ config HOST_32BIT config HOST_64BIT def_bool $(cc-define,_LP64) +config HOST_HAS_SDL + def_bool $(success,sdl2-config --version) + +config SANDBOX_SDL + bool "Enable SDL2 support in sandbox" + default HOST_HAS_SDL + config SANDBOX_CRASH_RESET bool "Reset on crash" help diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 3e2c7f9ebe..1284ef390b 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -8,9 +8,7 @@ SDL_CONFIG ?= sdl2-config # Define this to avoid linking with SDL, which requires SDL libraries # This can solve 'sdl-config: Command not found' errors -ifneq ($(NO_SDL),) -PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL -else +ifeq ($(CONFIG_SANDBOX_SDL),y) PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs) PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags) endif diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 34c4e06d9b..e6d8403651 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -56,11 +56,8 @@ To run sandbox U-Boot use something like:: Note: If you get errors about 'sdl-config: Command not found' you may need to install libsdl2.0-dev or similar to get SDL support. Alternatively you can -build sandbox without SDL (i.e. no display/keyboard support) by removing -the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:: - - make sandbox_defconfig all NO_SDL=1 - ./u-boot +build sandbox without SDL (i.e. no display/keyboard support) by disabling +CONFIG_SANDBOX_SDL in the .config file. U-Boot will start on your computer, showing a sandbox emulation of the serial console:: @@ -84,7 +81,7 @@ To exit, type 'poweroff' or press Ctrl-C. Console / LCD support --------------------- -Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the +Assuming that CONFIG_SANDBOX_SDL is enabled when building, you can run the sandbox with LCD and keyboard emulation, using something like:: ./u-boot -d u-boot.dtb -l diff --git a/doc/build/tools.rst b/doc/build/tools.rst index c06f915274..ec01722925 100644 --- a/doc/build/tools.rst +++ b/doc/build/tools.rst @@ -44,4 +44,4 @@ applications using a linux toolchain (gcc, bash, etc), targeting respectively Launch the MSYS2 shell of the MSYS2 environment, and do the following:: $ make tools-only_defconfig - $ make tools-only NO_SDL=1 + $ make tools-only diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index c841b99bb3..f539977d9b 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -622,7 +622,7 @@ config VIDEO_ARM_MALIDP config VIDEO_SANDBOX_SDL bool "Enable sandbox video console using SDL" - depends on SANDBOX + depends on SANDBOX_SDL help When using sandbox you can enable an emulated LCD display which appears as an SDL (Simple DirectMedia Layer) window. This is a diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 1779f1894e..8d9af7f088 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -18,8 +18,4 @@ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -#ifndef SANDBOX_NO_SDL -#define CONFIG_SANDBOX_SDL -#endif - #endif From 9cebc4ad8ebe6832c6d0eca786a85533a3b54ce4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:44 -0500 Subject: [PATCH 064/424] post: Migrate to Kconfig We move the existing CONFIG_POST_* functionality over to CFG_POST and then introduce CONFIG_POST to Kconfig. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/pg_wcom_expu1_defconfig | 1 + configs/pg_wcom_expu1_update_defconfig | 1 + configs/pg_wcom_seli8_defconfig | 1 + configs/pg_wcom_seli8_update_defconfig | 1 + doc/README.POST | 6 +- doc/README.fsl-ddr | 2 +- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 4 +- include/configs/kmcent2.h | 2 +- include/configs/kmcoge5ne.h | 4 +- include/post.h | 4 +- include/serial.h | 4 +- post/cpu/mpc83xx/ecc.c | 2 +- post/drivers/flash.c | 2 +- post/drivers/i2c.c | 4 +- post/drivers/memory.c | 4 +- post/drivers/rtc.c | 4 +- post/lib_powerpc/andi.c | 2 +- post/lib_powerpc/asm.S | 2 +- post/lib_powerpc/b.c | 2 +- post/lib_powerpc/cmp.c | 2 +- post/lib_powerpc/cmpi.c | 2 +- post/lib_powerpc/complex.c | 2 +- post/lib_powerpc/cpu.c | 4 +- post/lib_powerpc/cr.c | 2 +- post/lib_powerpc/fpu/20001122-1.c | 4 +- post/lib_powerpc/fpu/20010114-2.c | 4 +- post/lib_powerpc/fpu/20010226-1.c | 4 +- post/lib_powerpc/fpu/980619-1.c | 4 +- post/lib_powerpc/fpu/acc1.c | 4 +- post/lib_powerpc/fpu/compare-fp-1.c | 4 +- post/lib_powerpc/fpu/fpu.c | 4 +- post/lib_powerpc/fpu/mul-subnormal-single-1.c | 4 +- post/lib_powerpc/load.c | 2 +- post/lib_powerpc/multi.c | 2 +- post/lib_powerpc/rlwimi.c | 2 +- post/lib_powerpc/rlwinm.c | 2 +- post/lib_powerpc/rlwnm.c | 2 +- post/lib_powerpc/srawi.c | 2 +- post/lib_powerpc/store.c | 2 +- post/lib_powerpc/string.c | 2 +- post/lib_powerpc/three.c | 2 +- post/lib_powerpc/threei.c | 2 +- post/lib_powerpc/threex.c | 2 +- post/lib_powerpc/two.c | 2 +- post/lib_powerpc/twox.c | 2 +- post/post.c | 4 +- post/tests.c | 68 +++++++++---------- test/Kconfig | 5 ++ 58 files changed, 114 insertions(+), 99 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 74ad7483dc..be85c54e48 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -486,7 +486,7 @@ int dram_init(void) #endif /* CONFIG_SYS_RAMBOOT */ #endif -#if CONFIG_POST & CFG_SYS_POST_MEMORY +#if CFG_POST & CFG_SYS_POST_MEMORY /* Board-specific functions defined in each board's ddr.c */ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 3d24b1a78c..f495205f5b 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -112,3 +112,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index cec55a1412..23a7b66fbc 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -107,3 +107,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 5fcf154642..7dfbde0469 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -109,3 +109,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index ce198e28cb..aea0b89f97 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -104,3 +104,4 @@ CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_POST=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 48ac85b699..41b26287d5 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -110,3 +110,4 @@ CONFIG_FS_CRAMFS=y CONFIG_BCH=y CONFIG_PANIC_HANG=y CONFIG_LZO=y +CONFIG_POST=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index c2a17c6212..013277c9bf 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -243,3 +243,4 @@ CONFIG_QE_UEC=y CONFIG_QE=y CONFIG_SYS_NS16550=y CONFIG_BCH=y +CONFIG_POST=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index ed55f7bfd0..d21e180d1f 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -100,3 +100,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 64ddaf8aa6..54773b0633 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -98,3 +98,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index ad08e3582e..8311b3a3a0 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -100,3 +100,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 01a6198d72..d6f4a05479 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -98,3 +98,4 @@ CONFIG_SCSI_AHCI_PLAT=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y +CONFIG_POST=y diff --git a/doc/README.POST b/doc/README.POST index 1d1c25bdf9..5d92f3fe6e 100644 --- a/doc/README.POST +++ b/doc/README.POST @@ -242,11 +242,11 @@ storage server and etc. All POST-related code will be #ifdef'ed with the CONFIG_POST macro. This macro will be defined in the config_.h file for those -boards that need POST. The CONFIG_POST macro will contain the list of +boards that need POST. The CFG_POST macro will contain the list of POST tests for the board. The macro will have the format of array composed of post_test structures: -#define CONFIG_POST \ +#define CFG_POST \ { "On-board peripherals test", "board", \ " This test performs full check-up of the " \ @@ -257,7 +257,7 @@ composed of post_test structures: A new file, post.h, will be created in the include/ directory. This file will contain common POST declarations and will define a set of -macros that will be reused for defining CONFIG_POST. As an example, +macros that will be reused for defining CFG_POST. As an example, the following macro may be defined: #define POST_CACHE \ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cec5d94df4..10e63f3be1 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -137,7 +137,7 @@ Memory testing options for mpc85xx 2. Memory test can be done with Power-On-Self-Test function, activated at compile time. - In order to enable the POST memory test, CONFIG_POST needs to be + In order to enable the POST memory test, CFG_POST needs to be defined in board configuraiton header file. By default, POST memory test performs a fast test. A slow test can be enabled by changing the flag at compiling time. To test memory bigger than 2GB, 36BIT support is needed. diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 8a489a2e3f..c02106747a 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -526,7 +526,7 @@ static int serial_post_probe(struct udevice *dev) ops->getconfig += gd->reloc_off; if (ops->setconfig) ops->setconfig += gd->reloc_off; -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART if (ops->loop) ops->loop += gd->reloc_off; #endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 4d54965094..369a8e38e3 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -458,7 +458,7 @@ void default_serial_puts(const char *s) dev->putc(*s++); } -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART static const int bauds[] = CFG_SYS_BAUDRATE_TABLE; /** diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index acbd43419f..8b901ca47a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -41,7 +41,7 @@ */ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ +#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */ /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index c1174b87ab..dfa81c037f 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -25,8 +25,8 @@ #define SPD_EEPROM_ADDRESS 0x54 /* POST memory regions test */ -#define CONFIG_POST (CFG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS +#define CFG_POST (CFG_SYS_POST_MEM_REGIONS) +#define CFG_POST_EXTERNAL_WORD_FUNCS /* * IFC Definitions diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 89c5a24ee9..527f0383bc 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -148,7 +148,7 @@ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E /* POST memory regions test */ -#define CONFIG_POST CFG_SYS_POST_MEM_REGIONS +#define CFG_POST CFG_SYS_POST_MEM_REGIONS /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index c24d6ad8bc..6b30fb4b61 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -33,8 +33,8 @@ CSCONFIG_COL_BIT_10) /* enable POST tests */ -#define CONFIG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ +#define CFG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) +#define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ diff --git a/include/post.h b/include/post.h index 867a66f300..e68d5c8902 100644 --- a/include/post.h +++ b/include/post.h @@ -16,7 +16,7 @@ #if defined(CONFIG_POST) -#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS +#ifndef CFG_POST_EXTERNAL_WORD_FUNCS #ifdef CONFIG_SYS_POST_WORD_ADDR #define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR #else @@ -51,7 +51,7 @@ static inline void post_word_store (ulong value) extern ulong post_word_load(void); extern void post_word_store(ulong value); -#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */ +#endif /* CFG_POST_EXTERNAL_WORD_FUNCS */ #endif /* defined (CONFIG_POST) */ #endif /* __ASSEMBLY__ */ diff --git a/include/serial.h b/include/serial.h index fe01bcfadb..f4d7dc58a9 100644 --- a/include/serial.h +++ b/include/serial.h @@ -14,7 +14,7 @@ struct serial_device { int (*tstc)(void); void (*putc)(const char c); void (*puts)(const char *s); -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART void (*loop)(int); #endif struct serial_device *next; @@ -242,7 +242,7 @@ struct dm_serial_ops { * @return 0 if OK, -ve on error */ int (*clear)(struct udevice *dev); -#if CONFIG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CONFIG_SYS_POST_UART /** * loop() - Control serial device loopback mode * diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index edd7411567..45263e6b44 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -17,7 +17,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CONFIG_SYS_POST_ECC /* * We use the RAW I/O accessors where possible in order to * achieve performance goal, since the test's execution time diff --git a/post/drivers/flash.c b/post/drivers/flash.c index 7d65f46d9f..e157d36911 100644 --- a/post/drivers/flash.c +++ b/post/drivers/flash.c @@ -6,7 +6,7 @@ * Licensed under the GPL-2 or later. */ -#if CONFIG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CONFIG_SYS_POST_FLASH #include #include #include diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c index 3b378921fa..057454ffd8 100644 --- a/post/drivers/i2c.c +++ b/post/drivers/i2c.c @@ -26,7 +26,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CONFIG_SYS_POST_I2C static int i2c_ignore_device(unsigned int chip) { @@ -94,4 +94,4 @@ int i2c_post_test (int flags) #endif } -#endif /* CONFIG_POST & CONFIG_SYS_POST_I2C */ +#endif /* CFG_POST & CONFIG_SYS_POST_I2C */ diff --git a/post/drivers/memory.c b/post/drivers/memory.c index 71dad7b8c0..1be2b41df4 100644 --- a/post/drivers/memory.c +++ b/post/drivers/memory.c @@ -138,7 +138,7 @@ #include #include -#if CONFIG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) +#if CFG_POST & (CFG_SYS_POST_MEMORY | CFG_SYS_POST_MEM_REGIONS) DECLARE_GLOBAL_DATA_PTR; @@ -535,4 +535,4 @@ int memory_post_test(int flags) return ret; } -#endif /* CONFIG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ +#endif /* CFG_POST&(CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) */ diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index c603f0e672..cfed56b680 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -26,7 +26,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CONFIG_SYS_POST_RTC static int rtc_post_skip (ulong * diff) { @@ -189,4 +189,4 @@ int rtc_post_test (int flags) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_RTC */ +#endif /* CFG_POST & CONFIG_SYS_POST_RTC */ diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index d4f60aa738..d69d61396b 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/asm.S b/post/lib_powerpc/asm.S index 91b599932f..13302d7968 100644 --- a/post/lib_powerpc/asm.S +++ b/post/lib_powerpc/asm.S @@ -10,7 +10,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ .global cpu_post_exec_02 diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c index 0b02e9169e..eb9371fa6b 100644 --- a/post/lib_powerpc/b.c +++ b/post/lib_powerpc/b.c @@ -24,7 +24,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index e70869774c..e4d0931fc9 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 85a9b0ad36..983892d006 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c index bb29e91701..d2ec21b0cb 100644 --- a/post/lib_powerpc/complex.c +++ b/post/lib_powerpc/complex.c @@ -18,7 +18,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); extern int cpu_post_complex_2_asm (int x, int n); diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index 1d47107342..77c2538172 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -20,7 +20,7 @@ #include #include -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern int cpu_post_test_cmp (void); extern int cpu_post_test_cmpi (void); @@ -118,4 +118,4 @@ int cpu_post_test (int flags) return ret; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_CPU */ diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index 56ed355dde..077fb0f2da 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -33,7 +33,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c index 4b452dc083..eddd3f915e 100644 --- a/post/lib_powerpc/fpu/20001122-1.c +++ b/post/lib_powerpc/fpu/20001122-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU int fpu_post_test_math1 (void) { @@ -40,4 +40,4 @@ int fpu_post_test_math1 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c index 4aadd1e048..9e3e54661f 100644 --- a/post/lib_powerpc/fpu/20010114-2.c +++ b/post/lib_powerpc/fpu/20010114-2.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU static float rintf (float x) { @@ -45,4 +45,4 @@ int fpu_post_test_math2 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c index b09a25c211..5bb3860900 100644 --- a/post/lib_powerpc/fpu/20010226-1.c +++ b/post/lib_powerpc/fpu/20010226-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU int fpu_post_test_math3 (void) { @@ -33,4 +33,4 @@ int fpu_post_test_math3 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c index 2fea708306..415cd50c85 100644 --- a/post/lib_powerpc/fpu/980619-1.c +++ b/post/lib_powerpc/fpu/980619-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU int fpu_post_test_math4 (void) { @@ -39,4 +39,4 @@ int fpu_post_test_math4 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c index 9e5783b257..4cf3b7cef7 100644 --- a/post/lib_powerpc/fpu/acc1.c +++ b/post/lib_powerpc/fpu/acc1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU static double func (const double *array) { @@ -36,4 +36,4 @@ int fpu_post_test_math5 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c index d46a13adcd..029600fd2b 100644 --- a/post/lib_powerpc/fpu/compare-fp-1.c +++ b/post/lib_powerpc/fpu/compare-fp-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU static int failed; @@ -204,4 +204,4 @@ int fpu_post_test_math6 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c index bd65f623d5..8993b36e80 100644 --- a/post/lib_powerpc/fpu/fpu.c +++ b/post/lib_powerpc/fpu/fpu.c @@ -21,7 +21,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU #include @@ -71,4 +71,4 @@ int fpu_post_test (int flags) return ret; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index cb61c9114d..87b882c6b2 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU union uf { @@ -82,4 +82,4 @@ int fpu_post_test_math7 (void) return 0; } -#endif /* CONFIG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index 5269563b1e..ece0b2756e 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index f082e4c546..0e9ee88eb5 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_02(ulong *code, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index 7b4dc79fb1..d24a3f665c 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 8a03e9b9bc..9f4a3edb3e 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index e2beb4e417..224e6bdd45 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index d4a8fabc42..713d4f2276 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 8e278fee88..2dbcccf098 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index 0d8d280b27..9b54847632 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -20,7 +20,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index fc6f1f5674..55f0ff8a88 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index f49c85e6b9..ec52d238e6 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 6bc5a54706..6f5f0b8eb7 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index fa376c76b1..b44dd4e208 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 5c36012a9b..320cc0a64e 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/post.c b/post/post.c index b81425d8cf..9964b41080 100644 --- a/post/post.c +++ b/post/post.c @@ -168,7 +168,7 @@ static void post_bootmode_test_off(void) post_word_store(word); } -#ifndef CONFIG_POST_SKIP_ENV_FLAGS +#ifndef CFG_POST_SKIP_ENV_FLAGS static void post_get_env_flags(int *test_flags) { int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST, @@ -227,7 +227,7 @@ static void post_get_flags(int *test_flags) for (j = 0; j < post_list_size; j++) test_flags[j] = post_list[j].flags; -#ifndef CONFIG_POST_SKIP_ENV_FLAGS +#ifndef CFG_POST_SKIP_ENV_FLAGS post_get_env_flags(test_flags); #endif diff --git a/post/tests.c b/post/tests.c index fc36e738f7..d61ea74d51 100644 --- a/post/tests.c +++ b/post/tests.c @@ -45,7 +45,7 @@ extern void sysmon_reloc (void); struct post_test post_list[] = { -#if CONFIG_POST & CONFIG_SYS_POST_OCM +#if CFG_POST & CONFIG_SYS_POST_OCM { "OCM test", "ocm", @@ -57,7 +57,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_OCM }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_CACHE +#if CFG_POST & CONFIG_SYS_POST_CACHE { "Cache test", "cache", @@ -69,9 +69,9 @@ struct post_test post_list[] = CONFIG_SYS_POST_CACHE }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG -#if defined(CONFIG_POST_WATCHDOG) - CONFIG_POST_WATCHDOG, +#if CFG_POST & CONFIG_SYS_POST_WATCHDOG +#if defined(CFG_POST_WATCHDOG) + CFG_POST_WATCHDOG, #else { "Watchdog timer test", @@ -85,7 +85,7 @@ struct post_test post_list[] = }, #endif #endif -#if CONFIG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CONFIG_SYS_POST_I2C { "I2C test", "i2c", @@ -97,7 +97,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_I2C }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CONFIG_SYS_POST_RTC { "RTC test", "rtc", @@ -109,7 +109,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_RTC }, #endif -#if CONFIG_POST & CFG_SYS_POST_MEMORY +#if CFG_POST & CFG_SYS_POST_MEMORY { "Memory test", "memory", @@ -121,7 +121,7 @@ struct post_test post_list[] = CFG_SYS_POST_MEMORY }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CONFIG_SYS_POST_CPU { "CPU test", "cpu", @@ -134,7 +134,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_CPU }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CONFIG_SYS_POST_FPU { "FPU test", "fpu", @@ -147,9 +147,9 @@ struct post_test post_list[] = CONFIG_SYS_POST_FPU }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_UART -#if defined(CONFIG_POST_UART) - CONFIG_POST_UART, +#if CFG_POST & CONFIG_SYS_POST_UART +#if defined(CFG_POST_UART) + CFG_POST_UART, #else { "UART test", @@ -161,9 +161,9 @@ struct post_test post_list[] = NULL, CONFIG_SYS_POST_UART }, -#endif /* CONFIG_POST_UART */ +#endif /* CFG_POST_UART */ #endif -#if CONFIG_POST & CONFIG_SYS_POST_ETHER +#if CFG_POST & CONFIG_SYS_POST_ETHER { "ETHERNET test", "ethernet", @@ -175,7 +175,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_ETHER }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_USB +#if CFG_POST & CONFIG_SYS_POST_USB { "USB test", "usb", @@ -187,7 +187,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_USB }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_SPR +#if CFG_POST & CONFIG_SYS_POST_SPR { "SPR test", "spr", @@ -199,7 +199,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_SPR }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_SYSMON +#if CFG_POST & CONFIG_SYS_POST_SYSMON { "SYSMON test", "sysmon", @@ -211,7 +211,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_SYSMON }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_DSP +#if CFG_POST & CONFIG_SYS_POST_DSP { "DSP test", "dsp", @@ -223,7 +223,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_DSP }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_CODEC +#if CFG_POST & CONFIG_SYS_POST_CODEC { "CODEC test", "codec", @@ -235,7 +235,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_CODEC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CONFIG_SYS_POST_ECC { "ECC test", "ecc", @@ -247,22 +247,22 @@ struct post_test post_list[] = CONFIG_SYS_POST_ECC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 - CONFIG_POST_BSPEC1, +#if CFG_POST & CONFIG_SYS_POST_BSPEC1 + CFG_POST_BSPEC1, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2 - CONFIG_POST_BSPEC2, +#if CFG_POST & CONFIG_SYS_POST_BSPEC2 + CFG_POST_BSPEC2, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3 - CONFIG_POST_BSPEC3, +#if CFG_POST & CONFIG_SYS_POST_BSPEC3 + CFG_POST_BSPEC3, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4 - CONFIG_POST_BSPEC4, +#if CFG_POST & CONFIG_SYS_POST_BSPEC4 + CFG_POST_BSPEC4, #endif -#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5 - CONFIG_POST_BSPEC5, +#if CFG_POST & CONFIG_SYS_POST_BSPEC5 + CFG_POST_BSPEC5, #endif -#if CONFIG_POST & CONFIG_SYS_POST_COPROC +#if CFG_POST & CONFIG_SYS_POST_COPROC { "Coprocessors communication test", "coproc_com", @@ -274,7 +274,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_COPROC }, #endif -#if CONFIG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CONFIG_SYS_POST_FLASH { "Parallel NOR flash test", "flash", @@ -286,7 +286,7 @@ struct post_test post_list[] = CONFIG_SYS_POST_FLASH }, #endif -#if CONFIG_POST & CFG_SYS_POST_MEM_REGIONS +#if CFG_POST & CFG_SYS_POST_MEM_REGIONS { "Memory regions test", "mem_regions", diff --git a/test/Kconfig b/test/Kconfig index a6b463e4d0..9f4641ae6b 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -1,3 +1,8 @@ +config POST + bool "Power On Self Test support" + help + See doc/README.POST for more details + menuconfig UNIT_TEST bool "Unit tests" help From 7102d324f6b41741ee74587d43d77b302b1bbd96 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sat, 19 Nov 2022 18:45:45 -0500 Subject: [PATCH 065/424] m68k: Rename CONFIG_WATCHDOG_TIMEOUT to CONFIG_WATCHDOG_TIMEOUT_MSECS In practice, it is clear that the usage in m68k of CONFIG_WATCHDOG_TIMEOUT is setting a value in milliseconds. Rename this to the existing symbol and move to Kconfig. Signed-off-by: Tom Rini --- arch/m68k/cpu/mcf523x/cpu.c | 2 +- arch/m68k/cpu/mcf52x2/cpu.c | 6 +++--- arch/m68k/cpu/mcf532x/cpu.c | 2 +- configs/M5208EVBE_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/astro_mcf5373l_defconfig | 1 + include/configs/M5208EVBE.h | 2 -- include/configs/M5235EVB.h | 2 -- include/configs/M5272C3.h | 2 -- include/configs/M53017EVB.h | 2 -- include/configs/M5329EVB.h | 2 -- include/configs/M5373EVB.h | 2 -- include/configs/astro_mcf5373l.h | 10 ---------- include/configs/cobra5272.h | 12 ------------ 20 files changed, 14 insertions(+), 39 deletions(-) diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c index 6d87908965..ba2c228911 100644 --- a/arch/m68k/cpu/mcf523x/cpu.c +++ b/arch/m68k/cpu/mcf523x/cpu.c @@ -92,7 +92,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT_MSECS); wdog_module |= (wdog_module / 8192); out_be16(&wdp->mr, wdog_module); diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c index d21d82fef7..d7cbf11e25 100644 --- a/arch/m68k/cpu/mcf52x2/cpu.c +++ b/arch/m68k/cpu/mcf52x2/cpu.c @@ -87,7 +87,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->mr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->sr, 0x5555); @@ -253,7 +253,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->wdog_wrrr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->wdog_wcr, 0); @@ -323,7 +323,7 @@ int watchdog_init(void) /* set timeout and enable watchdog */ out_be16(&wdt->wmr, - (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1); + (CONFIG_WATCHDOG_TIMEOUT_MSECS * CONFIG_SYS_HZ) / (32768 * 1000) - 1); /* reset watchdog counter */ out_be16(&wdt->wsr, 0x5555); diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c index 8a48d73475..548cbca36a 100644 --- a/arch/m68k/cpu/mcf532x/cpu.c +++ b/arch/m68k/cpu/mcf532x/cpu.c @@ -131,7 +131,7 @@ int watchdog_init(void) u32 wdog_module = 0; /* set timeout and enable watchdog */ - wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); + wdog_module = ((CFG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT_MSECS); #ifdef CONFIG_M5329 out_be16(&wdp->mr, wdog_module / 8192); #else diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index fd219cbaeb..680c2d4367 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -43,3 +43,4 @@ CONFIG_SYS_MAX_FLASH_SECT=254 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 1b7b156800..c0087aa67f 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -50,3 +50,4 @@ CONFIG_SYS_MAX_FLASH_SECT=137 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index fffcdddd49..b099e98606 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -50,3 +50,4 @@ CONFIG_SYS_MAX_FLASH_SECT=137 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 5e7d40144f..a321b1c5c2 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -62,3 +62,4 @@ CONFIG_SYS_MAX_FLASH_SECT=137 CONFIG_MCFFEC=y CONFIG_MII=y CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=10000 diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 6586f0468b..32d1958088 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -49,3 +49,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index bf1d70f832..9f0b419639 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -48,3 +48,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index b83b542f8f..05388796fb 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -50,3 +50,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=5000 diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 181f79b1e9..90d8321648 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -50,3 +50,4 @@ CONFIG_MII=y CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=3360 diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index afbcb86c03..9e5665a12b 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -50,3 +50,4 @@ CONFIG_MCFRTC=y CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 CONFIG_MCFUART=y CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=3355 diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 246437a51e..b360238b33 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -15,8 +15,6 @@ */ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 128ef50b47..ed45eccb62 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - /* I2C */ #define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 847b4c2593..a9339e5052 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -19,8 +19,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ - #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ /* Configuration for environment diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 0e9ba4c3ad..42b74aeb9b 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 - #ifdef CONFIG_MCFFEC # define CFG_SYS_TX_ETH_BUFFER 8 # define CFG_SYS_FEC_BUF_USE_SRAM diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 8f83810f16..72f0c63a1e 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 43c642edeb..4e8b54e01f 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -22,8 +22,6 @@ #define CFG_SYS_UART_PORT (0) -#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ - /* I2C */ #ifdef CONFIG_MCFFEC diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index f5922fc416..62aa99342a 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -69,16 +69,6 @@ #define CFG_SYS_UART_PORT (2) #define CFG_SYS_UART2_ALT3_GPIO -/* - * Watchdog configuration; Watchdog is disabled for running from RAM - * and set to highest possible value else. Beware there is no check - * in the watchdog code to validate the timeout value set here! - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ -#endif - /* * Configuration for environment * Environment is located in the last sector of the flash diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 01828ea201..6d6e2fc696 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -42,18 +42,6 @@ #define CFG_SYS_UART_PORT (0) -/* --- - * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change - * timeout acc. to your needs - * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 - * for 10 sec - * --- - */ - -#if 0 -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#endif - /* --- * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different * bootloader residing in flash ('chainloading'); if you want to use From f17fe71222e5fa0975089772e22b45979f202eff Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 12 Oct 2022 19:13:11 +0200 Subject: [PATCH 066/424] powerpc: fix fdt_fixup_liodn_tbl_fman() Builiding with GCC 12.2 fails: arch/powerpc/cpu/mpc85xx/liodn.c: In function 'fdt_fixup_liodn_tbl_fman': arch/powerpc/cpu/mpc85xx/liodn.c:340:35: error: the comparison will always evaluate as 'false' for the address of 'compat' will never be NULL [-Werror=address] 340 | if (tbl[i].compat == NULL) | Remove the superfluous check. Fixes: 97a8d010e029 ("net/fman: Support both new and legacy FMan Compatibles") Signed-off-by: Heinrich Schuchardt --- arch/powerpc/cpu/mpc85xx/liodn.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index d5df02d39d..18790921dd 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -337,9 +337,6 @@ static void fdt_fixup_liodn_tbl_fman(void *blob, for (i = 0; i < sz; i++) { int off; - if (tbl[i].compat == NULL) - continue; - /* Try the new compatible first. * If the node is missing, try the old. */ From 83e37a834525594e26067021f7df298662906f04 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 22 Nov 2022 12:31:53 -0500 Subject: [PATCH 067/424] buildman: Fetch 12.2.0 toolchains by default Update the toolchain list to be first 12.2.0 and second 11.1.0 and that's it. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- tools/buildman/toolchain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py index fea40ba215..38b0dea8c7 100644 --- a/tools/buildman/toolchain.py +++ b/tools/buildman/toolchain.py @@ -498,7 +498,7 @@ class Toolchains: if arch == 'aarch64': arch = 'arm64' base = 'https://www.kernel.org/pub/tools/crosstool/files/bin' - versions = ['11.1.0', '9.2.0', '7.3.0', '6.4.0', '4.9.4'] + versions = ['12.2.0', '11.1.0'] links = [] for version in versions: url = '%s/%s/%s/' % (base, arch, version) From 409e4b547872db78dbf50f63cf75d2422d5fbb3d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 22 Nov 2022 12:31:54 -0500 Subject: [PATCH 068/424] Makefile: Enforce DWARF4 output At this point in time, using DWARF-5 format isn't easy to do by default with all toolchains that we support. And relying on the implicit default can lead to mixing 4 and 5 and then the debug info not being useful to tools. For now, enforce using DWARF-4 only. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index d48f52f294..11efc41804 100644 --- a/Makefile +++ b/Makefile @@ -761,10 +761,10 @@ KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized) # change __FILE__ to the relative path from the srctree KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=) -KBUILD_CFLAGS += -g +KBUILD_CFLAGS += -gdwarf-4 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g # option to the assembler. -KBUILD_AFLAGS += -g +KBUILD_AFLAGS += -gdwarf-4 # Report stack usage if supported # ARC tools based on GCC 7.1 has an issue with stack usage From 583f124aac205b354b3b73ebb62c79e8cc41e6d5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 22 Nov 2022 12:31:55 -0500 Subject: [PATCH 069/424] event: Re-add file paths to the tests Now that we are enforcing dwarf-4 to be used we will have the full file paths present. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- test/py/tests/test_event_dump.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/test/py/tests/test_event_dump.py b/test/py/tests/test_event_dump.py index 1a46ca30f4..da196df4c3 100644 --- a/test/py/tests/test_event_dump.py +++ b/test/py/tests/test_event_dump.py @@ -16,7 +16,7 @@ def test_event_dump(u_boot_console): out = util.run_and_log(cons, ['scripts/event_dump.py', sandbox]) expect = '''.*Event type Id Source location -------------------- ------------------------------ ------------------------------ -EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*vbe_request.c:.* -EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*vbe_simple_os.c:.* -EVT_MISC_INIT_F sandbox_misc_init_f .*start.c:''' +EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.* +EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.* +EVT_MISC_INIT_F sandbox_misc_init_f .*arch/sandbox/cpu/start.c:''' assert re.match(expect, out, re.MULTILINE) is not None From fc2240046c82d652a75cf96782502eebd16b628b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 22 Nov 2022 12:31:56 -0500 Subject: [PATCH 070/424] arm: Use the WEAK assembly entry point consistently MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini Reviewed-by: Simon Glass Reviewed-by: Pali Rohár --- arch/arm/cpu/armv7/nonsec_virt.S | 3 +- arch/arm/cpu/armv7/psci.S | 75 +++++++++++--------------------- arch/arm/cpu/armv7/start.S | 6 +-- arch/arm/cpu/armv8/psci.S | 12 ++--- arch/arm/lib/relocate.S | 3 +- 5 files changed, 33 insertions(+), 66 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 39aeeb423f..5ee6577c2c 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -207,7 +207,7 @@ ENDPROC(_nonsec_init) #ifdef CONFIG_SMP_PEN_ADDR /* void __weak smp_waitloop(unsigned previous_address); */ -ENTRY(smp_waitloop) +WEAK(smp_waitloop) wfi ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address ldr r1, [r1] @@ -219,7 +219,6 @@ ENTRY(smp_waitloop) mov r0, r1 b _do_nonsec_entry ENDPROC(smp_waitloop) -.weak smp_waitloop #endif .popsection diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 983cd90442..6c066e50d9 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -36,34 +36,32 @@ _psci_vectors: b default_psci_vector @ irq b psci_fiq_enter @ fiq -ENTRY(psci_fiq_enter) +WEAK(psci_fiq_enter) movs pc, lr ENDPROC(psci_fiq_enter) -.weak psci_fiq_enter -ENTRY(default_psci_vector) +WEAK(default_psci_vector) movs pc, lr ENDPROC(default_psci_vector) -.weak default_psci_vector -ENTRY(psci_version) -ENTRY(psci_cpu_suspend) -ENTRY(psci_cpu_off) -ENTRY(psci_cpu_on) -ENTRY(psci_affinity_info) -ENTRY(psci_migrate) -ENTRY(psci_migrate_info_type) -ENTRY(psci_migrate_info_up_cpu) -ENTRY(psci_system_off) -ENTRY(psci_system_reset) -ENTRY(psci_features) -ENTRY(psci_cpu_freeze) -ENTRY(psci_cpu_default_suspend) -ENTRY(psci_node_hw_state) -ENTRY(psci_system_suspend) -ENTRY(psci_set_suspend_mode) -ENTRY(psi_stat_residency) -ENTRY(psci_stat_count) +WEAK(psci_version) +WEAK(psci_cpu_suspend) +WEAK(psci_cpu_off) +WEAK(psci_cpu_on) +WEAK(psci_affinity_info) +WEAK(psci_migrate) +WEAK(psci_migrate_info_type) +WEAK(psci_migrate_info_up_cpu) +WEAK(psci_system_off) +WEAK(psci_system_reset) +WEAK(psci_features) +WEAK(psci_cpu_freeze) +WEAK(psci_cpu_default_suspend) +WEAK(psci_node_hw_state) +WEAK(psci_system_suspend) +WEAK(psci_set_suspend_mode) +WEAK(psi_stat_residency) +WEAK(psci_stat_count) mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) mov pc, lr ENDPROC(psci_stat_count) @@ -84,24 +82,6 @@ ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) ENDPROC(psci_version) -.weak psci_version -.weak psci_cpu_suspend -.weak psci_cpu_off -.weak psci_cpu_on -.weak psci_affinity_info -.weak psci_migrate -.weak psci_migrate_info_type -.weak psci_migrate_info_up_cpu -.weak psci_system_off -.weak psci_system_reset -.weak psci_features -.weak psci_cpu_freeze -.weak psci_cpu_default_suspend -.weak psci_node_hw_state -.weak psci_system_suspend -.weak psci_set_suspend_mode -.weak psi_stat_residency -.weak psci_stat_count _psci_table: .word ARM_PSCI_FN_CPU_SUSPEND @@ -179,12 +159,11 @@ _smc_psci: movs pc, lr @ Return to the kernel @ Requires dense and single-cluster CPU ID space -ENTRY(psci_get_cpu_id) +WEAK(psci_get_cpu_id) mrc p15, 0, r0, c0, c0, 5 /* read MPIDR */ and r0, r0, #0xff /* return CPU ID in cluster */ bx lr ENDPROC(psci_get_cpu_id) -.weak psci_get_cpu_id /* Imported from Linux kernel */ ENTRY(psci_v7_flush_dcache_all) @@ -236,7 +215,7 @@ finished: bx lr ENDPROC(psci_v7_flush_dcache_all) -ENTRY(psci_disable_smp) +WEAK(psci_disable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR bic r0, r0, #(1 << 6) @ Clear SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR @@ -244,16 +223,14 @@ ENTRY(psci_disable_smp) dsb bx lr ENDPROC(psci_disable_smp) -.weak psci_disable_smp -ENTRY(psci_enable_smp) +WEAK(psci_enable_smp) mrc p15, 0, r0, c1, c0, 1 @ ACTLR orr r0, r0, #(1 << 6) @ Set SMP bit mcr p15, 0, r0, c1, c0, 1 @ ACTLR isb bx lr ENDPROC(psci_enable_smp) -.weak psci_enable_smp ENTRY(psci_cpu_off_common) push {lr} @@ -316,15 +293,13 @@ ENTRY(psci_stack_setup) bx r6 ENDPROC(psci_stack_setup) -ENTRY(psci_arch_init) +WEAK(psci_arch_init) mov pc, lr ENDPROC(psci_arch_init) -.weak psci_arch_init -ENTRY(psci_arch_cpu_entry) +WEAK(psci_arch_cpu_entry) mov pc, lr ENDPROC(psci_arch_cpu_entry) -.weak psci_arch_cpu_entry ENTRY(psci_cpu_entry) bl psci_enable_smp diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 4f6327fe3a..7d7aac021e 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -151,16 +151,14 @@ ENDPROC(c_runtime_cpu_setup) * Don't save anything to stack even if compiled with -O0 * *************************************************************************/ -ENTRY(save_boot_params) +WEAK(save_boot_params) b save_boot_params_ret @ back to my caller ENDPROC(save_boot_params) - .weak save_boot_params #ifdef CONFIG_ARMV7_LPAE -ENTRY(switch_to_hypervisor) +WEAK(switch_to_hypervisor) b switch_to_hypervisor_ret ENDPROC(switch_to_hypervisor) - .weak switch_to_hypervisor #endif /************************************************************************* diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S index 7ffc8dbadb..6aece11987 100644 --- a/arch/arm/cpu/armv8/psci.S +++ b/arch/arm/cpu/armv8/psci.S @@ -12,11 +12,10 @@ /* Default PSCI function, return -1, Not Implemented */ #define PSCI_DEFAULT(__fn) \ - ENTRY(__fn); \ + WEAK(__fn); \ mov w0, #ARM_PSCI_RET_NI; \ ret; \ ENDPROC(__fn); \ - .weak __fn /* PSCI function and ID table definition*/ #define PSCI_TABLE(__id, __fn) \ @@ -207,7 +206,7 @@ handle_smc64: * used for the return value, while in this PSCI environment, X0 usually holds * the SMC function identifier, so X0 should be saved by caller function. */ -ENTRY(psci_get_cpu_id) +WEAK(psci_get_cpu_id) #ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER mrs x9, MPIDR_EL1 ubfx x9, x9, #8, #8 @@ -221,7 +220,6 @@ ENTRY(psci_get_cpu_id) add x0, x10, x9 ret ENDPROC(psci_get_cpu_id) -.weak psci_get_cpu_id /* CPU ID input in x0, stack top output in x0*/ LENTRY(psci_get_cpu_stack_top) @@ -261,10 +259,9 @@ handle_sync: * Override this function if custom error handling is * needed for asynchronous aborts */ -ENTRY(plat_error_handler) +WEAK(plat_error_handler) ret ENDPROC(plat_error_handler) -.weak plat_error_handler handle_error: bl psci_get_cpu_id @@ -323,9 +320,8 @@ ENTRY(psci_setup_vectors) ret ENDPROC(psci_setup_vectors) -ENTRY(psci_arch_init) +WEAK(psci_arch_init) ret ENDPROC(psci_arch_init) -.weak psci_arch_init .popsection diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index dd6f2e3bd5..345e282e3e 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -23,9 +23,8 @@ */ .section .text.relocate_vectors,"ax",%progbits - .weak relocate_vectors -ENTRY(relocate_vectors) +WEAK(relocate_vectors) #ifdef CONFIG_CPU_V7M /* From 6caf6f5c83db773c068a5ad1042290c0a5f5bcc8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 22 Nov 2022 12:31:57 -0500 Subject: [PATCH 071/424] pogo_v4: Disable LTO With gcc-12.2 we now get: lib/zlib/inflate.c:360: undefined reference to `__gnu_thumb1_case_si' when building this platform. This seems like some odd problem with LTO and Thumb, but since the platform continues to link, I assume it's within size constraints, so lets just disable LTO for now. Cc: Tony Dinh Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/pogo_v4_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/pogo_v4_defconfig b/configs/pogo_v4_defconfig index 018c2f5033..57ec6f1fb6 100644 --- a/configs/pogo_v4_defconfig +++ b/configs/pogo_v4_defconfig @@ -17,7 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="kirkwood-pogoplug-series-4" CONFIG_SYS_PROMPT="Pogo_V4> " CONFIG_IDENT_STRING="\nPogoplug V4" CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 From 09ed7e62f3273bf5da658973f704254d3aa5a2e5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 22 Nov 2022 12:31:58 -0500 Subject: [PATCH 072/424] CI: Update to gcc-12.2 - Update to gcc-12.2, and cherry-pick a fix in grub for risc-v Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- .azure-pipelines.yml | 8 ++--- .gitlab-ci.yml | 6 ++-- tools/docker/Dockerfile | 65 +++++++++++++++++++++-------------------- 3 files changed, 41 insertions(+), 38 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index add8847225..d31b183ba6 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -2,7 +2,7 @@ variables: windows_vm: windows-2019 ubuntu_vm: ubuntu-22.04 macos_vm: macOS-12 - ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022 + ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20221101-22Nov2022 # Add '-u 0' options for Azure pipelines, otherwise we get "permission # denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer", # since our $(ci_runner_image) user is not root. @@ -204,7 +204,7 @@ stages: options: $(container_option) steps: - script: | - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH + export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH test/nokia_rx51_test.sh - job: pylint @@ -242,7 +242,7 @@ stages: TEST_PY_BD: "sandbox" sandbox_clang: TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-13" + OVERRIDE: "-O clang-14" sandbox_nolto: TEST_PY_BD: "sandbox" BUILD_ENV: "NO_LTO=1" @@ -486,7 +486,7 @@ stages: OVERRIDE: "-a ASAN" sandbox_clang_asan: BUILDMAN: "sandbox" - OVERRIDE: "-O clang-13 -a ASAN" + OVERRIDE: "-O clang-14 -a ASAN" samsung_socfpga: BUILDMAN: "samsung socfpga" sun4i: diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 91d5e0c4a8..e14b57a5e0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,7 +2,7 @@ # Grab our configured image. The source for this is found # in the u-boot tree at tools/docker/Dockerfile -image: trini/u-boot-gitlab-ci-runner:jammy-20221003-17Oct2022 +image: trini/u-boot-gitlab-ci-runner:jammy-20221101-22Nov2022 # We run some tests in different order, to catch some failures quicker. stages: @@ -225,7 +225,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: Run tests for Nokia RX-51 (aka N900): stage: testsuites script: - - export PATH=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin:$PATH; + - export PATH=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin:$PATH; test/nokia_rx51_test.sh # Check for any pylint regressions @@ -256,7 +256,7 @@ sandbox test.py: sandbox with clang test.py: variables: TEST_PY_BD: "sandbox" - OVERRIDE: "-O clang-13" + OVERRIDE: "-O clang-14" <<: *buildman_and_testpy_dfn sandbox without LTO test.py: diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 42ab81283d..2408788b2f 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -2,7 +2,7 @@ # This Dockerfile is used to build an image containing basic stuff to be used # to build U-Boot and run our test suites. -FROM ubuntu:jammy-20221003 +FROM ubuntu:jammy-20221101 MAINTAINER Tom Rini LABEL Description=" This image is for building U-Boot inside a container" @@ -12,20 +12,20 @@ ENV DEBIAN_FRONTEND=noninteractive # Add LLVM repository RUN apt-get update && apt-get install -y gnupg2 wget xz-utils && rm -rf /var/lib/apt/lists/* RUN wget -O - https://apt.llvm.org/llvm-snapshot.gpg.key | apt-key add - -RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-13 main | tee /etc/apt/sources.list.d/llvm.list +RUN echo deb http://apt.llvm.org/jammy/ llvm-toolchain-jammy-14 main | tee /etc/apt/sources.list.d/llvm.list -# Manually install the kernel.org "Crosstool" based toolchains for gcc-11.1.0 -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ -RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.1.0/x86_64-gcc-11.1.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ +# Manually install the kernel.org "Crosstool" based toolchains for gcc-12.2.0 +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-aarch64-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-arm-linux-gnueabi.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-i386-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-m68k-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-mips-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-microblaze-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-nios2-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-powerpc-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-riscv64-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-riscv32-linux.tar.xz | tar -C /opt -xJ +RUN wget -O - https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/12.2.0/x86_64-gcc-12.2.0-nolibc-sh2-linux.tar.xz | tar -C /opt -xJ # Manually install other toolchains RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz @@ -39,7 +39,7 @@ RUN apt-get update && apt-get install -y \ binutils-dev \ bison \ build-essential \ - clang-13 \ + clang-14 \ coreutils \ cpio \ cppcheck \ @@ -123,15 +123,18 @@ RUN chmod +r /boot/vmlinu* RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ cd /tmp/grub && \ git checkout grub-2.06 && \ + git config --global user.name "GitLab CI Runner" && \ + git config --global user.email trini@konsulko.com && \ + git cherry-pick 049efdd72eb7baa7b2bf8884391ee7fe650da5a0 && \ ./bootstrap && \ mkdir -p /opt/grub && \ ./configure --target=aarch64 --with-platform=efi \ CC=gcc \ - TARGET_CC=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \ - TARGET_OBJCOPY=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \ - TARGET_STRIP=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \ - TARGET_NM=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \ - TARGET_RANLIB=/opt/gcc-11.1.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \ + TARGET_CC=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-gcc \ + TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-objcopy \ + TARGET_STRIP=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-strip \ + TARGET_NM=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-nm \ + TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/aarch64-linux/bin/aarch64-linux-ranlib && \ make && \ ./grub-mkimage -O arm64-efi -o /opt/grub/grubaa64.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ @@ -141,11 +144,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ make clean && \ ./configure --target=arm --with-platform=efi \ CC=gcc \ - TARGET_CC=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \ - TARGET_OBJCOPY=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \ - TARGET_STRIP=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \ - TARGET_NM=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \ - TARGET_RANLIB=/opt/gcc-11.1.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \ + TARGET_CC=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-gcc \ + TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-objcopy \ + TARGET_STRIP=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-strip \ + TARGET_NM=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-nm \ + TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/arm-linux-gnueabi/bin/arm-linux-gnueabi-ranlib && \ make && \ ./grub-mkimage -O arm-efi -o /opt/grub/grubarm.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ @@ -155,11 +158,11 @@ RUN git clone git://git.savannah.gnu.org/grub.git /tmp/grub && \ make clean && \ ./configure --target=riscv64 --with-platform=efi \ CC=gcc \ - TARGET_CC=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \ - TARGET_OBJCOPY=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \ - TARGET_STRIP=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \ - TARGET_NM=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \ - TARGET_RANLIB=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \ + TARGET_CC=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-gcc \ + TARGET_OBJCOPY=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-objcopy \ + TARGET_STRIP=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-strip \ + TARGET_NM=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-nm \ + TARGET_RANLIB=/opt/gcc-12.2.0-nolibc/riscv64-linux/bin/riscv64-linux-ranlib && \ make && \ ./grub-mkimage -O riscv64-efi -o /opt/grub/grubriscv64.efi --prefix= -d \ grub-core cat chain configfile echo efinet ext2 fat halt help linux \ @@ -215,7 +218,7 @@ USER uboot:uboot # Create the buildman config file RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman -RUN /bin/echo -e "kernelorg = /opt/gcc-11.1.0-nolibc/*" >> ~/.buildman +RUN /bin/echo -e "kernelorg = /opt/gcc-12.2.0-nolibc/*" >> ~/.buildman RUN /bin/echo -e "arc = /opt/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman; RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman From ebef190e138ed52501c2f65b7f86302eb0c981a8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:24:56 -0500 Subject: [PATCH 073/424] xenguest_arm64: Disable networking support more fully This platform had largely disabled networking support before. More completely disable it by turning off CONFIG_NET. Cc: Anastasiia Lukianenko Cc: Oleksandr Andrushchenko Signed-off-by: Tom Rini --- configs/xenguest_arm64_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/xenguest_arm64_defconfig b/configs/xenguest_arm64_defconfig index 1632ca36b6..a696c2807b 100644 --- a/configs/xenguest_arm64_defconfig +++ b/configs/xenguest_arm64_defconfig @@ -35,10 +35,10 @@ CONFIG_CMD_PVBLOCK=y # CONFIG_CMD_ITEST is not set # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set # CONFIG_CMD_SLEEP is not set CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y +# CONFIG_NET is not set # CONFIG_MMC is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_DM_SERIAL=y From 66900cb7c4e32cb486614fbb4716f23dff59fb40 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:24:57 -0500 Subject: [PATCH 074/424] LicheePi_Zero: Disable networking support more fully This platform had largely disabled networking support before. More completely disable it by turning off CONFIG_NET. Cc: Icenowy Zheng Signed-off-by: Tom Rini --- configs/LicheePi_Zero_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 5e9732e62e..027edde6a5 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -6,4 +6,4 @@ CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SYS_MONITOR_LEN=786432 -# CONFIG_NETDEVICES is not set +# CONFIG_NET is not set From 3c6ee7bb72735e0122acb71ec9df9de7acf3c78b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:24:58 -0500 Subject: [PATCH 075/424] pinecube: Disable networking support more fully This platform had largely disabled networking support before. More completely disable it by turning off CONFIG_NET. Cc: Icenowy Zheng Signed-off-by: Tom Rini --- configs/pinecube_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 3386eda886..2ce7b2772a 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -10,12 +10,12 @@ CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y +# CONFIG_NET is not set CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 CONFIG_SPI_FLASH_WINBOND=y -# CONFIG_NETDEVICES is not set CONFIG_AXP209_POWER=y CONFIG_AXP_DCDC2_VOLT=1250 CONFIG_AXP_DCDC3_VOLT=3300 From da752ac3c423d872763d9748a5242d9e5d135999 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:24:59 -0500 Subject: [PATCH 076/424] topic_miami*: Disable networking support more fully This platform had largely disabled networking support before. More completely disable it by turning off CONFIG_NET. Cc: Mike Looijmans Signed-off-by: Tom Rini Acked-by: Mike Looijmans --- configs/topic_miami_defconfig | 2 +- configs/topic_miamilite_defconfig | 2 +- configs/topic_miamiplus_defconfig | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index 96aa62a7ec..ece625f629 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -46,11 +46,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 41ba8a7487..693a602ea3 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -46,11 +46,11 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 763bd8cccd..97624e69e7 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -50,6 +50,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DFU_RAM=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000 @@ -62,7 +63,6 @@ CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SF_DEFAULT_SPEED=108000000 CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set -# CONFIG_NETDEVICES is not set CONFIG_DEBUG_UART_ZYNQ=y CONFIG_ARM_DCC=y CONFIG_ZYNQ_SERIAL=y From 8459276445f23239c8f60b32b4af5791e9a40d00 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:00 -0500 Subject: [PATCH 077/424] chromebook_samus_tpl: Disable SPL networking We don't appear to actually use networking in SPL here, disable it. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- configs/chromebook_samus_tpl_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig index 77735739b8..337768b45f 100644 --- a/configs/chromebook_samus_tpl_defconfig +++ b/configs/chromebook_samus_tpl_defconfig @@ -39,7 +39,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_HANDOFF=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y -CONFIG_SPL_NET=y CONFIG_SPL_PCI=y CONFIG_SPL_PCH=y CONFIG_TPL_PCI=y From f6301702c1605184d2a72c0b453fd8846fc6c0d8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:02 -0500 Subject: [PATCH 078/424] net: Remove extraneous dependencies With DM_ETH being required now for all drivers, we don't need this listed on individual drivers as well. Signed-off-by: Tom Rini --- drivers/net/Kconfig | 4 ++-- drivers/net/bnxt/Kconfig | 1 - drivers/net/mscc_eswitch/Kconfig | 10 +++++----- drivers/net/phy/Kconfig | 3 --- drivers/net/qe/Kconfig | 1 - 5 files changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 13e434e591..db61c27e01 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1,7 +1,6 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" source "drivers/net/fsl-mc/Kconfig" -source "drivers/net/bnxt/Kconfig" config ETH def_bool y @@ -175,6 +174,8 @@ config BCMGENET help This driver supports the BCMGENET Ethernet MAC. +source "drivers/net/bnxt/Kconfig" + config CORTINA_NI_ENET bool "Cortina-Access Ethernet driver" depends on CORTINA_PLATFORM @@ -721,7 +722,6 @@ config RENESAS_RAVB config MPC8XX_FEC bool "Fast Ethernet Controller on MPC8XX" depends on MPC8xx - depends on DM_ETH select MII select SYS_DISCOVER_PHY help diff --git a/drivers/net/bnxt/Kconfig b/drivers/net/bnxt/Kconfig index 412ecd4303..6ff3ffa137 100644 --- a/drivers/net/bnxt/Kconfig +++ b/drivers/net/bnxt/Kconfig @@ -1,6 +1,5 @@ config BNXT_ETH bool "BNXT PCI support" - depends on DM_ETH select PCI_INIT_R help This driver implements support for bnxt pci controller diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig index 930d2ef113..f9780661c8 100644 --- a/drivers/net/mscc_eswitch/Kconfig +++ b/drivers/net/mscc_eswitch/Kconfig @@ -4,35 +4,35 @@ config MSCC_OCELOT_SWITCH bool "Ocelot switch driver" - depends on DM_ETH && ARCH_MSCC + depends on ARCH_MSCC select PHYLIB help This driver supports the Ocelot network switch device. config MSCC_LUTON_SWITCH bool "Luton switch driver" - depends on DM_ETH && ARCH_MSCC + depends on ARCH_MSCC select PHYLIB help This driver supports the Luton network switch device. config MSCC_JR2_SWITCH bool "Jaguar2 switch driver" - depends on DM_ETH && ARCH_MSCC + depends on ARCH_MSCC select PHYLIB help This driver supports the Jaguar2 network switch device. config MSCC_SERVALT_SWITCH bool "Servalt switch driver" - depends on DM_ETH && ARCH_MSCC + depends on ARCH_MSCC select PHYLIB help This driver supports the Servalt network switch device. config MSCC_SERVAL_SWITCH bool "Serval switch driver" - depends on DM_ETH && ARCH_MSCC + depends on ARCH_MSCC select PHYLIB help This driver supports the Serval network switch device. diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 86e698190f..580ac8e8fb 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -315,7 +315,6 @@ config PHY_XILINX config PHY_XILINX_GMII2RGMII bool "Xilinx GMII to RGMII Ethernet PHYs support" - depends on DM_ETH help This adds support for Xilinx GMII to RGMII IP core. This IP acts as bridge between MAC connected over GMII and external phy that @@ -336,7 +335,6 @@ config PHY_ETHERNET_ID config PHY_FIXED bool "Fixed-Link PHY" - depends on DM_ETH help Fixed PHY is used for having a 'fixed-link' to another MAC with a direct connection (MII, RGMII, ...). @@ -346,7 +344,6 @@ config PHY_FIXED config PHY_NCSI bool "NC-SI based PHY" - depends on DM_ETH endif #PHYLIB diff --git a/drivers/net/qe/Kconfig b/drivers/net/qe/Kconfig index dec88dea2a..e795e913d4 100644 --- a/drivers/net/qe/Kconfig +++ b/drivers/net/qe/Kconfig @@ -4,6 +4,5 @@ config QE_UEC bool "NXP QE UEC Ethernet controller" - depends on DM_ETH help This driver supports the NXP QE UEC ethernet controller From 8457d023b8907fea75c47887c0cfb144c4bc3472 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:03 -0500 Subject: [PATCH 079/424] global: Remove extraneous DM_ETH imply/select We only need to enable DM_ETH if we have a networking driver. All networking drivers depend on DM_ETH being enabled, and their selection ensures DM_ETH will be enabled. Signed-off-by: Tom Rini --- arch/Kconfig | 2 -- arch/arm/Kconfig | 13 ------------- arch/arm/mach-at91/Kconfig | 4 ---- arch/arm/mach-imx/mx5/Kconfig | 1 - arch/arm/mach-imx/mx6/Kconfig | 16 ---------------- arch/arm/mach-omap2/am33xx/Kconfig | 1 - arch/arm/mach-snapdragon/Kconfig | 2 -- arch/arm/mach-tegra/Kconfig | 1 - arch/mips/Kconfig | 4 ---- board/armltd/vexpress64/Kconfig | 1 - board/keymile/km83xx/Kconfig | 1 - board/tq/tqma6/Kconfig | 1 - 12 files changed, 47 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 51d46a45fe..b074cc6c51 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -113,7 +113,6 @@ config RISCV select DM select SPL_SEPARATE_BSS if SPL imply DM_SERIAL - imply DM_ETH imply DM_EVENT imply DM_MMC imply DM_SPI @@ -241,7 +240,6 @@ config X86 imply CMD_SF imply CMD_SF_TEST imply CMD_ZBOOT - imply DM_ETH imply DM_EVENT imply DM_GPIO imply DM_KEYBOARD diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fb696abac8..2d7e90a658 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -632,7 +632,6 @@ config ARCH_KIRKWOOD config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)" select DM - select DM_ETH select DM_SERIAL select DM_SPI select DM_SPI_FLASH @@ -736,7 +735,6 @@ config ARCH_EXYNOS select DM select DM_GPIO select DM_I2C - select DM_ETH select DM_KEYBOARD select DM_SERIAL select DM_SPI @@ -767,7 +765,6 @@ config ARCH_HIGHBANK select CLK select CLK_CCF select AHCI - select DM_ETH select PHYS_64BIT select TIMER select SP804_TIMER @@ -1041,7 +1038,6 @@ config ARCH_APPLE config ARCH_OWL bool "Actions Semi OWL SoCs" select DM - select DM_ETH select DM_SERIAL select GPIO_EXTRA_HEADER select OWL_SERIAL @@ -1141,7 +1137,6 @@ config ARCH_SUNXI select CMD_USB if DISTRO_DEFAULTS && USB_HOST select CLK select DM - select DM_ETH select DM_GPIO select DM_I2C if I2C select DM_SPI if SPI @@ -1220,7 +1215,6 @@ config ARCH_VERSAL select ARM64 select CLK select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select GICV3 @@ -1234,7 +1228,6 @@ config ARCH_VERSAL_NET select ARM64 select CLK select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select OF_CONTROL @@ -1259,7 +1252,6 @@ config ARCH_ZYNQ select CPU_V7A select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select DM_SPI @@ -1289,7 +1281,6 @@ config ARCH_ZYNQMP_R5 select CLK select CPU_V7R select DM - select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL select OF_CONTROL @@ -1302,7 +1293,6 @@ config ARCH_ZYNQMP select CLK select DM select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART - select DM_ETH if NET imply DM_MAILBOX select DM_MMC if MMC select DM_SERIAL @@ -1849,7 +1839,6 @@ config TARGET_SL28 select DM_I2C select DM_MMC select DM_SPI_FLASH - select DM_ETH select DM_MDIO select PCI select DM_RNG @@ -1886,7 +1875,6 @@ config ARCH_UNIPHIER bool "Socionext UniPhier SoCs" select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -2072,7 +2060,6 @@ config TARGET_POMELO select SCSI select DM_SCSI select DM_SERIAL - select DM_ETH if NET imply CMD_PCI help Support for pomelo platform. diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 094c9891f6..7c2e4ebbdb 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -85,7 +85,6 @@ config TARGET_GURNARD select AT91_WANTS_COMMON_PHY select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_SERIAL select DM_SPI @@ -253,7 +252,6 @@ config TARGET_CORVUS select AT91SAM9M10G45 select AT91_WANTS_COMMON_PHY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select SUPPORT_SPL @@ -271,7 +269,6 @@ config TARGET_TAURUS select AT91SAM9G20 select AT91_WANTS_COMMON_PHY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select DM_SPI @@ -284,7 +281,6 @@ config TARGET_SMARTWEB select AT91SAM9260 select AT91_WANTS_COMMON_PHY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select SUPPORT_SPL diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig index 494e2136dc..d282663dcf 100644 --- a/arch/arm/mach-imx/mx5/Kconfig +++ b/arch/arm/mach-imx/mx5/Kconfig @@ -22,7 +22,6 @@ config TARGET_KP_IMX53 bool "Support K+P imx53 board" select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_PMIC diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index e6b0ee7579..7529b311f8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -174,7 +174,6 @@ config TARGET_DART_6UL bool "Variscite imx6ULL dart(DART-SOM-6ULL)" depends on MX6ULL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -197,7 +196,6 @@ config TARGET_DISPLAY5 bool "LWN DISPLAY5 board" depends on MX6Q select DM - select DM_ETH select DM_I2C select DM_MMC select DM_SPI @@ -245,7 +243,6 @@ config TARGET_KONTRON_MX6UL config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" select BOARD_LATE_INIT - select DM_ETH select DM_GPIO select DM_MMC select PCI @@ -261,7 +258,6 @@ config TARGET_MCCMON6 select SUPPORT_SPL select DM select DM_GPIO - select DM_ETH select DM_SERIAL select DM_I2C select DM_SPI @@ -280,7 +276,6 @@ config TARGET_MX6LOGICPD select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -301,7 +296,6 @@ config TARGET_MX6DL_MAMOJ bool "Support BTicino Mamoj" depends on MX6QDL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -334,7 +328,6 @@ config TARGET_MX6Q_ENGICAM depends on MX6QDL select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -355,7 +348,6 @@ config TARGET_MX6Q_ACC select OF_CONTROL select SPL_OF_LIBFDT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -447,7 +439,6 @@ config TARGET_MX6UL_ENGICAM depends on MX6UL select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -484,7 +475,6 @@ config TARGET_MYS_6ULX bool "MYiR MYS-6ULX" depends on MX6ULL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -504,7 +494,6 @@ config TARGET_NPI_IMX6ULL bool "Seeed NPI-IMX6ULL" depends on MX6ULL select DM - select DM_ETH select DM_MMC select DM_GPIO select DM_SERIAL @@ -552,7 +541,6 @@ config TARGET_PCL063 bool "PHYTEC PCL063 (phyCORE-i.MX6UL)" depends on MX6UL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -564,7 +552,6 @@ config TARGET_PCL063_ULL bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)" depends on MX6ULL select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC @@ -577,7 +564,6 @@ config TARGET_SOMLABS_VISIONSOM_6ULL depends on MX6ULL select BOARD_LATE_INIT select DM - select DM_ETH select DM_GPIO select DM_MMC select DM_SERIAL @@ -597,7 +583,6 @@ config TARGET_KP_IMX6Q_TPC select SPL_DM if SPL select DM_THERMAL select DM_MMC - select DM_ETH select DM_REGULATOR select SPL_DM_REGULATOR if SPL select DM_SERIAL @@ -661,7 +646,6 @@ config TARGET_BRPPT2 select OF_CONTROL select SPL_OF_LIBFDT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_MMC diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 6c2d46abc4..b666e81110 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -230,7 +230,6 @@ config TARGET_AM43XX_EVM bool "Support am43xx_evm" select BOARD_LATE_INIT select TI_I2C_BOARD_DETECT - imply DM_ETH imply DM_I2C imply DM_SPI imply DM_SPI_FLASH diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0927333306..914f4d9605 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -55,7 +55,6 @@ config TARGET_DRAGONBOARD845C - 64GiB UFS drive select MISC_INIT_R select SDM845 - select DM_ETH if NET config TARGET_STARQLTECHN bool "Samsung S9 SM-G9600(starqltechn)" @@ -67,7 +66,6 @@ config TARGET_STARQLTECHN - 64GiB UFS drive select MISC_INIT_R select SDM845 - select DM_ETH if NET config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09ad2d6f5a..edcf967afd 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -44,7 +44,6 @@ config TEGRA_COMMON select BOARD_EARLY_INIT_F select CLK select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_KEYBOARD diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9af0133f10..23142bd270 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -19,7 +19,6 @@ config TARGET_MALTA select DM select DM_SERIAL select PCI - select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM select MIPS_INSERT_BOOT_CONFIG @@ -71,7 +70,6 @@ config ARCH_MTMIPS imply CMD_DM select DISPLAY_CPUINFO select DM - imply DM_ETH imply DM_GPIO select DM_RESET select DM_SERIAL @@ -104,7 +102,6 @@ config ARCH_OCTEON select DISPLAY_CPUINFO select DMA_ADDR_T_64BIT select DM - select DM_ETH select DM_GPIO select DM_I2C select DM_SERIAL @@ -153,7 +150,6 @@ config TARGET_XILFPGA bool "Support Imagination Xilfpga" select HAS_FIXED_TIMER_FREQUENCY select DM - select DM_ETH select DM_GPIO select DM_SERIAL select SYS_CACHE_SHIFT_4 diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index c7adae0ea7..5616e223a9 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -14,7 +14,6 @@ config VEXPRESS64_BASE_MODEL select SEMIHOSTING select VIRTIO_BLK if VIRTIO_MMIO select VIRTIO_NET if VIRTIO_MMIO - select DM_ETH if VIRTIO_NET select LINUX_KERNEL_IMAGE_HEADER select POSITION_INDEPENDENT diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index ef3c62b9de..f87a2e6416 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -6,7 +6,6 @@ config KM_ENABLE_FULL_DM_DTS_SUPPORT default y select CMD_DM select DM - select DM_ETH select DM_MDIO select DM_SERIAL select OF_CONTROL diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig index 1cd90718f4..e7f23367af 100644 --- a/board/tq/tqma6/Kconfig +++ b/board/tq/tqma6/Kconfig @@ -63,7 +63,6 @@ choice config MBA6 bool "TQMa6 on MBa6 Starterkit" - select DM_ETH select USB select CMD_USB select USB_STORAGE From 2f420f135ffdc7d30834d640efb504261426afa3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:04 -0500 Subject: [PATCH 080/424] net: tsec: Remove non-DM_ETH support code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Doing this removes some board support code which was also unused. Finally, this removes some CONFIG symbols that otherwise needed to be migrated to Kconfig, but were unused in code now. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-ls102xa/config.h | 5 - arch/powerpc/include/asm/config_mpc85xx.h | 17 -- arch/powerpc/include/asm/immap_83xx.h | 5 - arch/powerpc/include/asm/immap_85xx.h | 8 - board/freescale/common/pixis.c | 73 ------- board/freescale/mpc8548cds/mpc8548cds.c | 82 -------- board/freescale/p1010rdb/p1010rdb.c | 43 ----- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 50 ----- drivers/net/tsec.c | 199 +------------------- include/configs/MPC837XERDB.h | 27 --- include/configs/MPC8548CDS.h | 27 --- include/configs/P1010RDB.h | 31 --- include/configs/ls1021aiot.h | 21 --- include/configs/ls1021aqds.h | 26 --- include/configs/p1_p2_rdb_pc.h | 21 --- include/configs/socrates.h | 16 -- include/tsec.h | 60 ------ 17 files changed, 1 insertion(+), 710 deletions(-) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 6413a307d2..14f86df5ed 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -36,11 +36,6 @@ #define CFG_SYS_FSL_SEC_OFFSET 0x00700000 #define CFG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CFG_SYS_TSEC1_OFFSET 0x01d10000 -#define CFG_SYS_MDIO1_OFFSET 0x01d24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d9e5a7d621..1b5b4947f1 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -24,18 +24,9 @@ #elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -/* P1011 is single core version of P1020 */ -#elif defined(CONFIG_ARCH_P1011) -#define CONFIG_TSECV2 - -#elif defined(CONFIG_ARCH_P1020) -#define CONFIG_TSECV2 - #elif defined(CONFIG_ARCH_P1021) -#define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -47,13 +38,8 @@ #define CFG_SYS_BMAN_NUM_PORTALS 3 #define CFG_SYS_FM_MURAM_SIZE 0x10000 -/* P1024 is lower end variant of P1020 */ -#elif defined(CONFIG_ARCH_P1024) -#define CONFIG_TSECV2 - /* P1025 is lower end variant of P1021 */ #elif defined(CONFIG_ARCH_P1025) -#define CONFIG_TSECV2 #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -108,12 +94,10 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_T4240) @@ -221,7 +205,6 @@ #elif defined(CONFIG_ARCH_C29X) #define CONFIG_FSL_SDHC_V2_3 -#define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 19774f3053..24bd438c14 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -873,9 +873,4 @@ struct ccsr_gpio { #define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) -#define CFG_SYS_TSEC1_OFFSET 0x24000 -#define CFG_SYS_MDIO1_OFFSET 0x24000 - -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 283fdf3b45..7293720fb3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2541,13 +2541,6 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000 #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 -#ifdef CONFIG_TSECV2 -#define CFG_SYS_TSEC1_OFFSET 0xB0000 -#elif defined(CONFIG_TSECV2_1) -#define CFG_SYS_TSEC1_OFFSET 0x10000 -#else -#define CFG_SYS_TSEC1_OFFSET 0x24000 -#endif #define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) @@ -2673,7 +2666,6 @@ struct ccsr_pman { #define CFG_SYS_SEC_MON_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET) -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 6fdb11039e..cb9f454972 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -281,79 +281,6 @@ U_BOOT_CMD( "" ); -#ifdef CONFIG_PIXIS_SGMII_CMD - -/* Enable or disable SGMII mode for a TSEC - */ -static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - int which_tsec = -1; - unsigned char mask; - unsigned char switch_mask; - - if ((argc > 2) && (strcmp(argv[1], "all") != 0)) - which_tsec = simple_strtoul(argv[1], NULL, 0); - - switch (which_tsec) { -#ifdef CONFIG_TSEC1 - case 1: - mask = PIXIS_VSPEED2_TSEC1SER; - switch_mask = PIXIS_VCFGEN1_TSEC1SER; - break; -#endif -#ifdef CONFIG_TSEC2 - case 2: - mask = PIXIS_VSPEED2_TSEC2SER; - switch_mask = PIXIS_VCFGEN1_TSEC2SER; - break; -#endif -#ifdef CONFIG_TSEC3 - case 3: - mask = PIXIS_VSPEED2_TSEC3SER; - switch_mask = PIXIS_VCFGEN1_TSEC3SER; - break; -#endif -#ifdef CONFIG_TSEC4 - case 4: - mask = PIXIS_VSPEED2_TSEC4SER; - switch_mask = PIXIS_VCFGEN1_TSEC4SER; - break; -#endif - default: - mask = PIXIS_VSPEED2_MASK; - switch_mask = PIXIS_VCFGEN1_MASK; - break; - } - - /* Toggle whether the switches or FPGA control the settings */ - if (!strcmp(argv[argc - 1], "switch")) - clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); - else - setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); - - /* If it's not the switches, enable or disable SGMII, as specified */ - if (!strcmp(argv[argc - 1], "on")) - clrbits_8(pixis_base + PIXIS_VSPEED2, mask); - else if (!strcmp(argv[argc - 1], "off")) - setbits_8(pixis_base + PIXIS_VSPEED2, mask); - - return 0; -} - -U_BOOT_CMD( - pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii, - "pixis_set_sgmii" - " - Enable or disable SGMII mode for a given TSEC \n", - "\npixis_set_sgmii [TSEC num] \n" - " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n" - " on - enables SGMII\n" - " off - disables SGMII\n" - " switch - use switch settings" -); - -#endif - /* * This function takes the non-integral cpu:mpx pll ratio * and converts it to an integer that can be used to assign diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 73e024eaa0..ec6e3a2d0a 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -168,85 +168,3 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } - -#ifndef CONFIG_DM_ETH -static void configure_rgmii(void) -{ - unsigned short temp; - - /* Change the resistors for the PHY */ - /* This is needed to get the RGMII working for the 1.3+ - * CDS cards */ - if (get_board_version() == 0x13) { - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 29, 18); - - miiphy_read(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, &temp); - - temp = (temp & 0xf03f); - temp |= 2 << 9; /* 36 ohm */ - temp |= 2 << 6; /* 39 ohm */ - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, temp); - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 29, 3); - - miiphy_write(DEFAULT_MII_NAME, - TSEC1_PHY_ADDR, 30, 0x8000); - } - - return; -} - -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ - if (get_board_version() >= 0x13) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; - } -#endif -#ifdef CONFIG_TSEC4 - /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ - if (get_board_version() >= 0x13) { - SET_STD_TSEC_INFO(tsec_info[num], 4); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; - } -#endif - - if (!num) { - printf("No TSECs initialized\n"); - - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - configure_rgmii(); -#endif - - return pci_eth_init(bis); -} -#endif diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 0f014823c9..d32274b248 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -478,49 +478,6 @@ int checkboard(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - struct cpu_type *cpu; - int num = 0; - - cpu = gd->arch.cpu; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - /* P1014 and it's derivatives do not support eTSEC3 */ - if (cpu->soc_ver != SVR_P1014) { - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; - } -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} -#endif - #if defined(CONFIG_OF_BOARD_SETUP) void fdt_del_flexcan(void *blob) { diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index ab79724429..df9f6ae473 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -364,56 +364,6 @@ int board_early_init_r(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - ccsr_gur_t *gur __attribute__((unused)) = - (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - printf("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - -#if defined(CONFIG_UEC_ETH) - /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); - - uec_standard_init(bis); -#endif - - return pci_eth_init(bis); -} -#endif - #if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP) static void fix_max6370_watchdog(void *blob) { diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 8b6f034ea1..f465409d8c 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -22,34 +22,6 @@ #include #include -#ifndef CONFIG_DM_ETH -/* Default initializations for TSEC controllers. */ - -static struct tsec_info_struct tsec_info[] = { -#ifdef CONFIG_TSEC1 - STD_TSEC_INFO(1), /* TSEC1 */ -#endif -#ifdef CONFIG_TSEC2 - STD_TSEC_INFO(2), /* TSEC2 */ -#endif -#ifdef CONFIG_MPC85XX_FEC - { - .regs = TSEC_GET_REGS(2, 0x2000), - .devname = CONFIG_MPC85XX_FEC_NAME, - .phyaddr = FEC_PHY_ADDR, - .flags = FEC_FLAGS, - .mii_devname = DEFAULT_MII_NAME - }, /* FEC */ -#endif -#ifdef CONFIG_TSEC3 - STD_TSEC_INFO(3), /* TSEC3 */ -#endif -#ifdef CONFIG_TSEC4 - STD_TSEC_INFO(4), /* TSEC4 */ -#endif -}; -#endif /* CONFIG_DM_ETH */ - #define TBIANA_SETTINGS ( \ TBIANA_ASYMMETRIC_PAUSE \ | TBIANA_SYMMETRIC_PAUSE \ @@ -124,23 +96,14 @@ static u32 ether_crc(size_t len, unsigned char const *p) * for PowerPC (tm) is usually the case) in the register holds * the entry. */ -#ifndef CONFIG_DM_ETH -static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, - int join) -#else static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; u32 result, value; u8 whichbit, whichreg; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; result = ether_crc(MAC_ADDR_LEN, mcast_mac); whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ @@ -271,11 +234,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) * do the same. Presumably, this would be zero if there were no * errors */ -#ifndef CONFIG_DM_ETH -static int tsec_send(struct eth_device *dev, void *packet, int length) -#else static int tsec_send(struct udevice *dev, void *packet, int length) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; @@ -283,11 +242,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length) u16 status; int i; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; /* Find an empty buffer descriptor */ for (i = 0; @@ -324,42 +279,6 @@ static int tsec_send(struct udevice *dev, void *packet, int length) return result; } -#ifndef CONFIG_DM_ETH -static int tsec_recv(struct eth_device *dev) -{ - struct tsec_private *priv = (struct tsec_private *)dev->priv; - struct tsec __iomem *regs = priv->regs; - - while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) { - int length = in_be16(&priv->rxbd[priv->rx_idx].length); - u16 status = in_be16(&priv->rxbd[priv->rx_idx].status); - uchar *packet = net_rx_packets[priv->rx_idx]; - - /* Send the packet up if there were no errors */ - if (!(status & RXBD_STATS)) - net_process_received_packet(packet, length - 4); - else - printf("Got error %x\n", (status & RXBD_STATS)); - - out_be16(&priv->rxbd[priv->rx_idx].length, 0); - - status = RXBD_EMPTY; - /* Set the wrap bit if this is the last element in the list */ - if ((priv->rx_idx + 1) == PKTBUFSRX) - status |= RXBD_WRAP; - out_be16(&priv->rxbd[priv->rx_idx].status, status); - - priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX; - } - - if (in_be32(®s->ievent) & IEVENT_BSY) { - out_be32(®s->ievent, IEVENT_BSY); - out_be32(®s->rstat, RSTAT_CLEAR_RHALT); - } - - return -1; -} -#else static int tsec_recv(struct udevice *dev, int flags, uchar **packetp) { struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev); @@ -406,22 +325,12 @@ static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length) return 0; } -#endif -/* Stop the interface */ -#ifndef CONFIG_DM_ETH -static void tsec_halt(struct eth_device *dev) -#else static void tsec_halt(struct udevice *dev) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); @@ -583,27 +492,15 @@ static void startup_tsec(struct tsec_private *priv) * that it returns success if the link is up, failure otherwise. * This allows U-Boot to find the first active controller. */ -#ifndef CONFIG_DM_ETH -static int tsec_init(struct eth_device *dev, struct bd_info *bd) -#else static int tsec_init(struct udevice *dev) -#endif { struct tsec_private *priv; struct tsec __iomem *regs; -#ifdef CONFIG_DM_ETH struct eth_pdata *pdata = dev_get_plat(dev); -#else - struct eth_device *pdata = dev; -#endif u32 tempval; int ret; -#ifndef CONFIG_DM_ETH - priv = (struct tsec_private *)dev->priv; -#else priv = dev_get_priv(dev); -#endif regs = priv->regs; /* Make sure the controller is stopped */ tsec_halt(dev); @@ -715,7 +612,7 @@ static int init_phy(struct tsec_private *priv) if (priv->interface == PHY_INTERFACE_MODE_SGMII) tsec_configure_serdes(priv); -#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO) +#if defined(CONFIG_DM_MDIO) phydev = dm_eth_phy_connect(priv->dev); #else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, @@ -734,99 +631,6 @@ static int init_phy(struct tsec_private *priv) return 1; } -#ifndef CONFIG_DM_ETH -/* - * Initialize device structure. Returns success if PHY - * initialization succeeded (i.e. if it recognizes the PHY) - */ -static int tsec_initialize(struct bd_info *bis, - struct tsec_info_struct *tsec_info) -{ - struct tsec_private *priv; - struct eth_device *dev; - int i; - - dev = (struct eth_device *)malloc(sizeof(*dev)); - - if (!dev) - return 0; - - memset(dev, 0, sizeof(*dev)); - - priv = (struct tsec_private *)malloc(sizeof(*priv)); - - if (!priv) { - free(dev); - return 0; - } - - priv->regs = tsec_info->regs; - priv->phyregs_sgmii = tsec_info->miiregs_sgmii; - - priv->phyaddr = tsec_info->phyaddr; - priv->tbiaddr = CFG_SYS_TBIPA_VALUE; - priv->flags = tsec_info->flags; - - strcpy(dev->name, tsec_info->devname); - priv->interface = tsec_info->interface; - priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname); - priv->dev = dev; - dev->iobase = 0; - dev->priv = priv; - dev->init = tsec_init; - dev->halt = tsec_halt; - dev->send = tsec_send; - dev->recv = tsec_recv; - dev->mcast = tsec_mcast_addr; - - /* Tell U-Boot to get the addr from the env */ - for (i = 0; i < 6; i++) - dev->enetaddr[i] = 0; - - eth_register(dev); - - /* Reset the MAC */ - setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); - udelay(2); /* Soft Reset must be asserted for 3 TX clocks */ - clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET); - - /* Try to initialize PHY here, and return */ - return init_phy(priv); -} - -/* - * Initialize all the TSEC devices - * - * Returns the number of TSEC devices that were initialized - */ -int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs, - int num) -{ - int i; - int count = 0; - - for (i = 0; i < num; i++) { - int ret = tsec_initialize(bis, &tsecs[i]); - - if (ret > 0) - count += ret; - } - - return count; -} - -int tsec_standard_init(struct bd_info *bis) -{ - struct fsl_pq_mdio_info info; - - info.regs = TSEC_GET_MDIO_REGS_BASE(1); - info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &info); - - return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info)); -} -#else /* CONFIG_DM_ETH */ int tsec_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -966,4 +770,3 @@ U_BOOT_DRIVER(eth_tsec) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* CONFIG_DM_ETH */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 95a90199a4..f312ffb37e 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -41,8 +41,6 @@ #ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 @@ -178,31 +176,6 @@ #define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000 #define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 -/* - * TSEC - */ -#ifdef CONFIG_TSEC_ENET - -#define CONFIG_GMII /* MII PHY management */ - -#define CONFIG_TSEC1 - -#ifdef CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CFG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 2 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC2_PHY_ADDR 0x1c -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_PHYIDX 0 -#endif -#endif - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC_PIN_MUX #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 780ee5ae86..34b876f829 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -283,33 +283,6 @@ #endif #define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 -#define CONFIG_TSEC4_NAME "eTSEC3" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#endif /* CONFIG_TSEC_ENET */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b1d6b15811..4418d51695 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -349,37 +349,6 @@ extern unsigned long get_sdram_size(void); /* eSPI - Enhanced SPI */ #endif -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - #ifdef CONFIG_MMC #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 024a718527..179c5128e3 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -66,27 +66,6 @@ /* SPI */ -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#endif - #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #define CONFIG_PEN_ADDR_BIG_ENDIAN diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 5a91cc3efe..d6681e8598 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -247,32 +247,6 @@ * MMC */ -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 3 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 2 -#define TSEC3_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#endif - #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9738e9fa9c..49c5aef305 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -366,27 +366,6 @@ #endif #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#endif /* CONFIG_TSEC_ENET */ - /* * Environment */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 95393d3ab2..2a07671602 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -111,22 +111,6 @@ #define CFG_SYS_PCI1_MEM_PHYS 0x80000000 #define CFG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0,1] */ - /* * Miscellaneous configurable options */ diff --git a/include/tsec.h b/include/tsec.h index de279b2117..153337837a 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -19,56 +19,6 @@ #define TSEC_MDIO_REGS_OFFSET 0x520 -#ifndef CONFIG_DM_ETH - -#ifdef CONFIG_ARCH_LS1021A -#define TSEC_SIZE 0x40000 -#define TSEC_MDIO_OFFSET 0x40000 -#else -#define TSEC_SIZE 0x01000 -#define TSEC_MDIO_OFFSET 0x01000 -#endif - -#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET) - -#define TSEC_GET_REGS(num, offset) \ - (struct tsec __iomem *)\ - (TSEC_BASE_ADDR + (((num) - 1) * (offset))) - -#define TSEC_GET_REGS_BASE(num) \ - TSEC_GET_REGS((num), TSEC_SIZE) - -#define TSEC_GET_MDIO_REGS(num, offset) \ - (struct tsec_mii_mng __iomem *)\ - (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset)) - -#define TSEC_GET_MDIO_REGS_BASE(num) \ - TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET) - -#define DEFAULT_MII_NAME "FSL_MDIO" - -#define STD_TSEC_INFO(num) \ -{ \ - .regs = TSEC_GET_REGS_BASE(num), \ - .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \ - .devname = CONFIG_TSEC##num##_NAME, \ - .phyaddr = TSEC##num##_PHY_ADDR, \ - .flags = TSEC##num##_FLAGS, \ - .mii_devname = DEFAULT_MII_NAME \ -} - -#define SET_STD_TSEC_INFO(x, num) \ -{ \ - x.regs = TSEC_GET_REGS_BASE(num); \ - x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \ - x.devname = CONFIG_TSEC##num##_NAME; \ - x.phyaddr = TSEC##num##_PHY_ADDR; \ - x.flags = TSEC##num##_FLAGS;\ - x.mii_devname = DEFAULT_MII_NAME;\ -} - -#endif /* CONFIG_DM_ETH */ - #define MAC_ADDR_LEN 6 /* #define TSEC_TIMEOUT 1000000 */ @@ -414,11 +364,7 @@ struct tsec_private { u32 flags; uint rx_idx; /* index of the current RX buffer */ uint tx_idx; /* index of the current TX buffer */ -#ifndef CONFIG_DM_ETH - struct eth_device *dev; -#else struct udevice *dev; -#endif }; struct tsec_info_struct { @@ -431,10 +377,4 @@ struct tsec_info_struct { u32 flags; }; -#ifndef CONFIG_DM_ETH -int tsec_standard_init(struct bd_info *bis); -int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsec_info, - int num); -#endif - #endif /* __TSEC_H */ From cc2bf624eb7109f793b470660973e4167de8290f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:05 -0500 Subject: [PATCH 081/424] net: fm: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/fm/Makefile | 1 - drivers/net/fm/eth.c | 238 ----------------------- drivers/net/fm/fm.c | 4 - drivers/net/fm/fm.h | 8 - drivers/net/fm/init.c | 386 ------------------------------------- drivers/net/fm/memac_phy.c | 52 ----- 6 files changed, 689 deletions(-) delete mode 100644 drivers/net/fm/init.c diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 5a7d3037af..b34209d2b3 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -6,7 +6,6 @@ obj-y += dtsec.o obj-y += eth.o obj-y += fdt.o obj-y += fm.o -obj-y += init.o obj-y += tgec.o obj-y += tgec_phy.o diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index c8381cc713..9fd26de0d7 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -8,12 +8,10 @@ #include #include #include -#ifdef CONFIG_DM_ETH #include #include #include #include -#endif #include #include #include @@ -28,11 +26,6 @@ #include "fm.h" -#ifndef CONFIG_DM_ETH -static struct eth_device *devlist[NUM_FM_PORTS]; -static int num_controllers; -#endif - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \ @@ -53,14 +46,10 @@ static void dtsec_configure_serdes(struct fm_eth *priv) PHY_INTERFACE_MODE_2500BASEX) ? true : false; int i = 0, j; -#ifndef CONFIG_DM_ETH - bus.priv = priv->mac->phyregs; -#else bus.priv = priv->pcs_mdio; bus.read = memac_mdio_read; bus.write = memac_mdio_write; bus.reset = memac_mdio_reset; -#endif qsgmii_loop: /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ @@ -136,19 +125,6 @@ static void dtsec_init_phy(struct fm_eth *fm_eth) fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX) dtsec_configure_serdes(fm_eth); } - -#ifndef CONFIG_DM_ETH -#ifdef CONFIG_PHYLIB -static int tgec_is_fibre(struct fm_eth *fm) -{ - char phyopt[20]; - - sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1); - - return hwconfig_arg_cmp(phyopt, "xfi"); -} -#endif -#endif /* CONFIG_DM_ETH */ #endif static u16 muram_readw(u16 *addr) @@ -465,18 +441,10 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth) sync(); } -#ifndef CONFIG_DM_ETH -static int fm_eth_open(struct eth_device *dev, struct bd_info *bd) -#else static int fm_eth_open(struct udevice *dev) -#endif { -#ifndef CONFIG_DM_ETH - struct fm_eth *fm_eth = dev->priv; -#else struct eth_pdata *pdata = dev_get_plat(dev); struct fm_eth *fm_eth = dev_get_priv(dev); -#endif unsigned char *enetaddr; struct fsl_enet_mac *mac; #ifdef CONFIG_PHYLIB @@ -485,11 +453,7 @@ static int fm_eth_open(struct udevice *dev) mac = fm_eth->mac; -#ifndef CONFIG_DM_ETH - enetaddr = &dev->enetaddr[0]; -#else enetaddr = pdata->enetaddr; -#endif /* setup the MAC address */ if (enetaddr[0] & 0x01) { @@ -512,12 +476,7 @@ static int fm_eth_open(struct udevice *dev) if (fm_eth->phydev) { ret = phy_startup(fm_eth->phydev); if (ret) { -#ifndef CONFIG_DM_ETH - printf("%s: Could not initialize\n", - fm_eth->phydev->dev->name); -#else printf("%s: Could not initialize\n", dev->name); -#endif return ret; } } else { @@ -540,20 +499,12 @@ static int fm_eth_open(struct udevice *dev) return fm_eth->phydev->link ? 0 : -1; } -#ifndef CONFIG_DM_ETH -static void fm_eth_halt(struct eth_device *dev) -#else static void fm_eth_halt(struct udevice *dev) -#endif { struct fm_eth *fm_eth; struct fsl_enet_mac *mac; -#ifndef CONFIG_DM_ETH - fm_eth = (struct fm_eth *)dev->priv; -#else fm_eth = dev_get_priv(dev); -#endif mac = fm_eth->mac; /* graceful stop the transmission of frames */ @@ -571,11 +522,7 @@ static void fm_eth_halt(struct udevice *dev) #endif } -#ifndef CONFIG_DM_ETH -static int fm_eth_send(struct eth_device *dev, void *buf, int len) -#else static int fm_eth_send(struct udevice *dev, void *buf, int len) -#endif { struct fm_eth *fm_eth; struct fm_port_global_pram *pram; @@ -583,11 +530,7 @@ static int fm_eth_send(struct udevice *dev, void *buf, int len) u16 offset_in; int i; -#ifndef CONFIG_DM_ETH - fm_eth = (struct fm_eth *)dev->priv; -#else fm_eth = dev_get_priv(dev); -#endif pram = fm_eth->tx_pram; txbd = fm_eth->cur_txbd; @@ -668,11 +611,7 @@ static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth, return rxbd; } -#ifndef CONFIG_DM_ETH -static int fm_eth_recv(struct eth_device *dev) -#else static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp) -#endif { struct fm_eth *fm_eth; struct fm_port_bd *rxbd; @@ -681,11 +620,7 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp) int ret = -1; u8 *data; -#ifndef CONFIG_DM_ETH - fm_eth = (struct fm_eth *)dev->priv; -#else fm_eth = dev_get_priv(dev); -#endif rxbd = fm_eth->cur_rxbd; status = muram_readw(&rxbd->status); @@ -695,12 +630,8 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp) buf_lo = in_be32(&rxbd->buf_ptr_lo); data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo); len = muram_readw(&rxbd->len); -#ifndef CONFIG_DM_ETH - net_process_received_packet(data, len); -#else *packetp = data; return len; -#endif } else { printf("%s: Rx error\n", dev->name); ret = 0; @@ -717,7 +648,6 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp) return ret; } -#ifdef CONFIG_DM_ETH static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length) { struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev); @@ -726,65 +656,7 @@ static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length) return 0; } -#endif /* CONFIG_DM_ETH */ -#ifndef CONFIG_DM_ETH -static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) -{ - struct fsl_enet_mac *mac; - int num; - void *base, *phyregs = NULL; - - num = fm_eth->num; - -#ifdef CONFIG_SYS_FMAN_V3 -#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION - if (fm_eth->type == FM_ETH_10G_E) { - /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240. - * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080. - * 10GEC1 uses mEMAC1 on T1024. - * so it needs to change the num. - */ - if (fm_eth->num >= 2) - num -= 2; - else - num += 8; - } -#endif - base = ®->memac[num].fm_memac; - phyregs = ®->memac[num].fm_memac_mdio; -#else - /* Get the mac registers base address */ - if (fm_eth->type == FM_ETH_1G_E) { - base = ®->mac_1g[num].fm_dtesc; - phyregs = ®->mac_1g[num].fm_mdio.miimcfg; - } else { - base = ®->mac_10g[num].fm_10gec; - phyregs = ®->mac_10g[num].fm_10gec_mdio; - } -#endif - - /* alloc mac controller */ - mac = malloc(sizeof(struct fsl_enet_mac)); - if (!mac) - return -ENOMEM; - memset(mac, 0, sizeof(struct fsl_enet_mac)); - - /* save the mac to fm_eth struct */ - fm_eth->mac = mac; - -#ifdef CONFIG_SYS_FMAN_V3 - init_memac(mac, base, phyregs, MAX_RXBUF_LEN); -#else - if (fm_eth->type == FM_ETH_1G_E) - init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN); - else - init_tgec(mac, base, phyregs, MAX_RXBUF_LEN); -#endif - - return 0; -} -#else /* CONFIG_DM_ETH */ static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg) { #ifndef CONFIG_SYS_FMAN_V3 @@ -817,15 +689,11 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg) return 0; } -#endif /* CONFIG_DM_ETH */ static int init_phy(struct fm_eth *fm_eth) { #ifdef CONFIG_PHYLIB u32 supported = PHY_GBIT_FEATURES; -#ifndef CONFIG_DM_ETH - struct phy_device *phydev = NULL; -#endif if (fm_eth->type == FM_ETH_10G_E) supported = PHY_10G_FEATURES; @@ -836,7 +704,6 @@ static int init_phy(struct fm_eth *fm_eth) if (fm_eth->type == FM_ETH_1G_E) dtsec_init_phy(fm_eth); -#ifdef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB #ifdef CONFIG_DM_MDIO fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev); @@ -848,113 +715,9 @@ static int init_phy(struct fm_eth *fm_eth) phy_config(fm_eth->phydev); #endif -#else /* CONFIG_DM_ETH */ -#ifdef CONFIG_PHYLIB - if (fm_eth->bus) { - phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev, - fm_eth->enet_if); - if (!phydev) { - printf("Failed to connect\n"); - return -1; - } - } else { - return 0; - } - - if (fm_eth->type == FM_ETH_1G_E) { - supported = (SUPPORTED_10baseT_Half | - SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | - SUPPORTED_100baseT_Full | - SUPPORTED_1000baseT_Full); - } else { - supported = SUPPORTED_10000baseT_Full; - - if (tgec_is_fibre(fm_eth)) - phydev->port = PORT_FIBRE; - } - - phydev->supported &= supported; - phydev->advertising = phydev->supported; - - fm_eth->phydev = phydev; - - phy_config(phydev); -#endif -#endif /* CONFIG_DM_ETH */ return 0; } -#ifndef CONFIG_DM_ETH -int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info) -{ - struct eth_device *dev; - struct fm_eth *fm_eth; - int i, num = info->num; - int ret; - - /* alloc eth device */ - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); - if (!dev) - return -ENOMEM; - memset(dev, 0, sizeof(struct eth_device)); - - /* alloc the FMan ethernet private struct */ - fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth)); - if (!fm_eth) - return -ENOMEM; - memset(fm_eth, 0, sizeof(struct fm_eth)); - - /* save off some things we need from the info struct */ - fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */ - fm_eth->num = num; - fm_eth->type = info->type; - - fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi; - fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi; - - /* set the ethernet max receive length */ - fm_eth->max_rx_len = MAX_RXBUF_LEN; - - /* init global mac structure */ - ret = fm_eth_init_mac(fm_eth, reg); - if (ret) - return ret; - - /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */ - if (fm_eth->type == FM_ETH_1G_E) - sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1); - else - sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1); - - devlist[num_controllers++] = dev; - dev->iobase = 0; - dev->priv = (void *)fm_eth; - dev->init = fm_eth_open; - dev->halt = fm_eth_halt; - dev->send = fm_eth_send; - dev->recv = fm_eth_recv; - fm_eth->dev = dev; - fm_eth->bus = info->bus; - fm_eth->phyaddr = info->phy_addr; - fm_eth->enet_if = info->enet_if; - - /* startup the FM im */ - ret = fm_eth_startup(fm_eth); - if (ret) - return ret; - - init_phy(fm_eth); - - /* clear the ethernet address */ - for (i = 0; i < 6; i++) - dev->enetaddr[i] = 0; - eth_register(dev); - - return 0; -} -#else /* CONFIG_DM_ETH */ - static int fm_eth_bind(struct udevice *dev) { char mac_name[11]; @@ -1139,4 +902,3 @@ U_BOOT_DRIVER(eth_fman) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* CONFIG_DM_ETH */ diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index c476cb3120..055dd61fbe 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -10,9 +10,7 @@ #include #include #include -#ifdef CONFIG_DM_ETH #include -#endif #include "fm.h" #include /* For struct qe_firmware */ @@ -551,7 +549,6 @@ int fm_init_common(int index, struct ccsr_fman *reg) } #endif -#ifdef CONFIG_DM_ETH struct fman_priv { struct ccsr_fman *reg; unsigned int fman_id; @@ -626,4 +623,3 @@ U_BOOT_DRIVER(fman) = { .priv_auto = sizeof(struct fman_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* CONFIG_DM_ETH */ diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 3d9cc5ca06..ba858cc24b 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -57,7 +57,6 @@ struct fm_port_bd { #define TxBD_READY 0x8000 #define TxBD_LAST BD_LAST -#ifdef CONFIG_DM_ETH enum fm_mac_type { #ifdef CONFIG_SYS_FMAN_V3 FM_MEMAC, @@ -66,7 +65,6 @@ enum fm_mac_type { FM_TGEC, #endif }; -#endif /* Fman ethernet private struct */ /* Rx/Tx queue descriptor */ @@ -115,9 +113,7 @@ void fman_disable_port(enum fm_port port); void fman_enable_port(enum fm_port port); int fman_id(struct udevice *dev); void *fman_port(struct udevice *dev, int num); -#ifdef CONFIG_DM_ETH void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num); -#endif struct fsl_enet_mac { void *base; /* MAC controller registers base address */ @@ -143,13 +139,9 @@ struct fm_eth { struct mii_dev *bus; struct phy_device *phydev; int phyaddr; -#ifndef CONFIG_DM_ETH - struct eth_device *dev; -#else enum fm_mac_type mac_type; struct udevice *dev; struct udevice *pcs_mdio; -#endif int max_rx_len; struct fm_port_global_pram *rx_pram; /* Rx parameter table */ struct fm_port_global_pram *tx_pram; /* Tx parameter table */ diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c deleted file mode 100644 index 618c1bccbe..0000000000 --- a/drivers/net/fm/init.c +++ /dev/null @@ -1,386 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2015 Freescale Semiconductor, Inc. - */ -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_FSL_LAYERSCAPE -#include -#include -#else -#include -#endif - -#include "fm.h" - -#ifndef CONFIG_DM_ETH -struct fm_eth_info fm_info[] = { -#if (CFG_SYS_NUM_FM1_DTSEC >= 1) - FM_DTSEC_INFO_INITIALIZER(1, 1), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 2) - FM_DTSEC_INFO_INITIALIZER(1, 2), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 3) - FM_DTSEC_INFO_INITIALIZER(1, 3), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 4) - FM_DTSEC_INFO_INITIALIZER(1, 4), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 5) - FM_DTSEC_INFO_INITIALIZER(1, 5), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 6) - FM_DTSEC_INFO_INITIALIZER(1, 6), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 7) - FM_DTSEC_INFO_INITIALIZER(1, 9), -#endif -#if (CFG_SYS_NUM_FM1_DTSEC >= 8) - FM_DTSEC_INFO_INITIALIZER(1, 10), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 1) - FM_DTSEC_INFO_INITIALIZER(2, 1), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 2) - FM_DTSEC_INFO_INITIALIZER(2, 2), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 3) - FM_DTSEC_INFO_INITIALIZER(2, 3), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 4) - FM_DTSEC_INFO_INITIALIZER(2, 4), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 5) - FM_DTSEC_INFO_INITIALIZER(2, 5), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 6) - FM_DTSEC_INFO_INITIALIZER(2, 6), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 7) - FM_DTSEC_INFO_INITIALIZER(2, 9), -#endif -#if (CFG_SYS_NUM_FM2_DTSEC >= 8) - FM_DTSEC_INFO_INITIALIZER(2, 10), -#endif -#if (CFG_SYS_NUM_FM1_10GEC >= 1) - FM_TGEC_INFO_INITIALIZER(1, 1), -#endif -#if (CFG_SYS_NUM_FM1_10GEC >= 2) - FM_TGEC_INFO_INITIALIZER(1, 2), -#endif -#if (CFG_SYS_NUM_FM1_10GEC >= 3) - FM_TGEC_INFO_INITIALIZER2(1, 3), -#endif -#if (CFG_SYS_NUM_FM1_10GEC >= 4) - FM_TGEC_INFO_INITIALIZER2(1, 4), -#endif -#if (CFG_SYS_NUM_FM2_10GEC >= 1) - FM_TGEC_INFO_INITIALIZER(2, 1), -#endif -#if (CFG_SYS_NUM_FM2_10GEC >= 2) - FM_TGEC_INFO_INITIALIZER(2, 2), -#endif -}; - -int fm_standard_init(struct bd_info *bis) -{ - int i; - struct ccsr_fman *reg; - - reg = (void *)CFG_SYS_FSL_FM1_ADDR; - if (fm_init_common(0, reg)) - return 0; - - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - if ((fm_info[i].enabled) && (fm_info[i].index == 1)) - fm_eth_initialize(reg, &fm_info[i]); - } - -#if (CFG_SYS_NUM_FMAN == 2) - reg = (void *)CFG_SYS_FSL_FM2_ADDR; - if (fm_init_common(1, reg)) - return 0; - - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - if ((fm_info[i].enabled) && (fm_info[i].index == 2)) - fm_eth_initialize(reg, &fm_info[i]); - } -#endif - - return 1; -} - -/* simple linear search to map from port to array index */ -static int fm_port_to_index(enum fm_port port) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - if (fm_info[i].port == port) - return i; - } - - return -1; -} - -/* - * Determine if an interface is actually active based on HW config - * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NA if - * the interface is not active based on HW cfg of the SoC - */ -void fman_enet_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - phy_interface_t enet_if; - - enet_if = fman_port_enet_if(fm_info[i].port); - if (enet_if != PHY_INTERFACE_MODE_NA) { - fm_info[i].enabled = 1; - fm_info[i].enet_if = enet_if; - } else { - fm_info[i].enabled = 0; - } - } - - return; -} - -void fm_disable_port(enum fm_port port) -{ - int i = fm_port_to_index(port); - - if (i == -1) - return; - - fm_info[i].enabled = 0; -#ifndef CONFIG_SYS_FMAN_V3 - fman_disable_port(port); -#endif -} - -void fm_enable_port(enum fm_port port) -{ - int i = fm_port_to_index(port); - - if (i == -1) - return; - - fm_info[i].enabled = 1; - fman_enable_port(port); -} - -void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus) -{ - int i = fm_port_to_index(port); - - if (i == -1) - return; - - fm_info[i].bus = bus; -} - -void fm_info_set_phy_address(enum fm_port port, int address) -{ - int i = fm_port_to_index(port); - - if (i == -1) - return; - - fm_info[i].phy_addr = address; -} - -/* - * Returns the PHY address for a given Fman port - * - * The port must be set via a prior call to fm_info_set_phy_address(). - * A negative error code is returned if the port is invalid. - */ -int fm_info_get_phy_address(enum fm_port port) -{ - int i = fm_port_to_index(port); - - if (i == -1) - return -1; - - return fm_info[i].phy_addr; -} - -/* - * Returns the type of the data interface between the given MAC and its PHY. - * This is typically determined by the RCW. - */ -phy_interface_t fm_info_get_enet_if(enum fm_port port) -{ - int i = fm_port_to_index(port); - - if (i == -1) - return PHY_INTERFACE_MODE_NA; - - if (fm_info[i].enabled) - return fm_info[i].enet_if; - - return PHY_INTERFACE_MODE_NA; -} - -static void -__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - return; -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) - __attribute__((weak, alias("__def_board_ft_fman_fixup_port"))); - -int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) -{ - int off; - uint32_t ph; - phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset; -#ifndef CONFIG_SYS_FMAN_V3 - u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS + - CFG_SYS_FSL_FM1_DTSEC1_OFFSET; -#endif - - off = fdt_node_offset_by_compat_reg(blob, prop, paddr); - if (off == -FDT_ERR_NOTFOUND) - return -EINVAL; - - if (info->enabled) { - fdt_fixup_phy_connection(blob, off, info->enet_if); - board_ft_fman_fixup_port(blob, prop, paddr, info->port, off); - return 0; - } - -#ifdef CONFIG_SYS_FMAN_V3 -#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION - /* - * On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same - * dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9 - * is disabled, ensure that the dual-role MAC is not disabled, - * ditto for other dual-role MACs. - */ - if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || - ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || - ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || - ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || - ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || - ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || - ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || - ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) -#if (CFG_SYS_NUM_FMAN == 2) - || - ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || - ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) || - ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) || - ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10))) -#endif -#else - /* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */ - if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) || - ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) || - ((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) || - ((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) || - ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) || - ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) || - ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) || - ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4))) -#endif - ) - return 0; -#endif - /* board code might have caused offset to change */ - off = fdt_node_offset_by_compat_reg(blob, prop, paddr); - -#ifndef CONFIG_SYS_FMAN_V3 - /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */ - if (paddr != dtsec1_addr) -#endif - fdt_status_disabled(blob, off); /* disable the MAC node */ - - /* disable the fsl,dpa-ethernet node that points to the MAC */ - ph = fdt_get_phandle(blob, off); - do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), - "status", "disabled", strlen("disabled") + 1, 1); - - return 0; -} - -void fdt_fixup_fman_ethernet(void *blob) -{ - int i; - -#ifdef CONFIG_SYS_FMAN_V3 - for (i = 0; i < ARRAY_SIZE(fm_info); i++) - ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac"); -#else - for (i = 0; i < ARRAY_SIZE(fm_info); i++) { - /* Try the new compatible first. - * If the node is missing, try the old. - */ - if (fm_info[i].type == FM_ETH_1G_E) { - if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec")) - ft_fixup_port(blob, &fm_info[i], - "fsl,fman-1g-mac"); - } else { - if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") && - ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec")) - ft_fixup_port(blob, &fm_info[i], - "fsl,fman-10g-mac"); - } - } -#endif -} - -/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different. - *This function scans which Riser Card being used(QSGMII or SGMII Riser Card), - *then set the correct PHY address - */ -void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, - unsigned int port_num, int phy_base_addr) -{ - unsigned int regnum = 0; - int qsgmii; - int i; - int phy_real_addr; - - qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum); - - if (!qsgmii) - return; - - for (i = base_port; i < base_port + port_num; i++) { - if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) { - phy_real_addr = phy_base_addr + i - base_port; - fm_info_set_phy_address(i, phy_real_addr); - } - } -} - -/*to check whether qsgmii riser card is used*/ -int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, - unsigned int port_num, unsigned regnum) -{ - int i; - int val; - - if (!bus) - return 0; - - for (i = phy_base_addr; i < phy_base_addr + port_num; i++) { - val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum); - if (val != MIIM_TIMEOUT) - return 1; - } - - return 0; -} -#endif /* CONFIG_DM_ETH */ diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 3ddae97e09..e0b62b9449 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -22,11 +22,9 @@ #define memac_setbits_32(a, v) setbits_be32(a, v) #endif -#ifdef CONFIG_DM_ETH struct fm_mdio_priv { struct memac_mdio_controller *regs; }; -#endif #define MAX_NUM_RETRIES 1000 @@ -88,9 +86,6 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, u32 c45 = 1; /* Default to 10G interface */ int err; -#ifndef CONFIG_DM_ETH - regs = bus->priv; -#else struct fm_mdio_priv *priv; if (!bus->priv) @@ -99,7 +94,6 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, regs = priv->regs; debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n", regs, port_addr, dev_addr, regnum, value); -#endif if (dev_addr == MDIO_DEVAD_NONE) { c45 = 0; /* clause 22 */ @@ -147,22 +141,14 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, u32 c45 = 1; int err; -#ifndef CONFIG_DM_ETH - regs = bus->priv; -#else struct fm_mdio_priv *priv; if (!bus->priv) return -EINVAL; priv = dev_get_priv(bus->priv); regs = priv->regs; -#endif if (dev_addr == MDIO_DEVAD_NONE) { -#ifndef CONFIG_DM_ETH - if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME)) - return 0xffff; -#endif c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC); @@ -205,43 +191,6 @@ int memac_mdio_reset(struct mii_dev *bus) return 0; } -#ifndef CONFIG_DM_ETH -int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info) -{ - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate FM TGEC MDIO bus\n"); - return -1; - } - - bus->read = memac_mdio_read; - bus->write = memac_mdio_write; - bus->reset = memac_mdio_reset; - strcpy(bus->name, info->name); - - bus->priv = info->regs; - - /* - * On some platforms like B4860, default value of MDIO_CLK_DIV bits - * in mdio_stat(mdio_cfg) register generates MDIO clock too high - * (much higher than 2.5MHz), violating the IEEE specs. - * On other platforms like T1040, default value of MDIO_CLK_DIV bits - * is zero, so MDIO clock is disabled. - * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to - * be properly initialized. - * NEG bit default should be '1' as per FMAN-v3 RM, but on platform - * like T2080QDS, this bit default is '0', which leads to MDIO failure - * on XAUI PHY, so set this bit definitely. - */ - memac_setbits_32( - &((struct memac_mdio_controller *)info->regs)->mdio_stat, - MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); - - return mdio_register(bus); -} - -#else /* CONFIG_DM_ETH */ #if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO) static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg) { @@ -341,4 +290,3 @@ U_BOOT_DRIVER(fman_mdio) = { .plat_auto = sizeof(struct mdio_perdev_priv), }; #endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */ -#endif /* CONFIG_DM_ETH */ From d55a00390498cc53c14d8b575b5efb5bb9acaef7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:06 -0500 Subject: [PATCH 082/424] net: dc2114x: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/dc2114x.c | 156 ------------------------------------------ 1 file changed, 156 deletions(-) diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index deedfe76e4..4e7af95b41 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -73,13 +73,7 @@ #define POLL_DEMAND 1 -#if defined(CONFIG_DM_ETH) #define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a)) -#elif defined(CONFIG_E500) -#define phys_to_bus(dev, a) (a) -#else -#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a)) -#endif #define NUM_RX_DESC PKTBUFSRX #define NUM_TX_DESC 1 /* Number of TX descriptors */ @@ -103,12 +97,7 @@ struct dc2114x_priv { int tx_new; /* TX descriptor ring pointer */ char rx_ring_size; char tx_ring_size; -#ifdef CONFIG_DM_ETH struct udevice *devno; -#else - struct eth_device dev; - pci_dev_t devno; -#endif char *name; void __iomem *iobase; u8 *enetaddr; @@ -479,150 +468,6 @@ static struct pci_device_id supported[] = { { } }; -#ifndef CONFIG_DM_ETH -static int dc21x4x_init(struct eth_device *dev, struct bd_info *bis) -{ - struct dc2114x_priv *priv = - container_of(dev, struct dc2114x_priv, dev); - - /* Ensure we're not sleeping. */ - pci_write_config_byte(priv->devno, PCI_CFDA_PSM, WAKEUP); - - return dc21x4x_init_common(priv); -} - -static void dc21x4x_halt(struct eth_device *dev) -{ - struct dc2114x_priv *priv = - container_of(dev, struct dc2114x_priv, dev); - - dc21x4x_halt_common(priv); - - pci_write_config_byte(priv->devno, PCI_CFDA_PSM, SLEEP); -} - -static int dc21x4x_send(struct eth_device *dev, void *packet, int length) -{ - struct dc2114x_priv *priv = - container_of(dev, struct dc2114x_priv, dev); - - return dc21x4x_send_common(priv, packet, length); -} - -static int dc21x4x_recv(struct eth_device *dev) -{ - struct dc2114x_priv *priv = - container_of(dev, struct dc2114x_priv, dev); - int length = 0; - int ret; - - while (true) { - ret = dc21x4x_recv_check(priv); - if (!ret) - break; - - if (ret > 0) { - length = ret; - /* Pass the packet up to the protocol layers */ - net_process_received_packet - (net_rx_packets[priv->rx_new], length - 4); - } - - /* - * Change buffer ownership for this frame, - * back to the adapter. - */ - if (ret != -EAGAIN) - priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN); - - /* Update entry information. */ - priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size; - } - - return length; -} - -int dc21x4x_initialize(struct bd_info *bis) -{ - struct dc2114x_priv *priv; - struct eth_device *dev; - unsigned short status; - unsigned char timer; - unsigned int iobase; - int card_number = 0; - pci_dev_t devbusfn; - int idx = 0; - - while (1) { - devbusfn = pci_find_devices(supported, idx++); - if (devbusfn == -1) - break; - - pci_read_config_word(devbusfn, PCI_COMMAND, &status); - status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config_word(devbusfn, PCI_COMMAND, status); - - pci_read_config_word(devbusfn, PCI_COMMAND, &status); - if (!(status & PCI_COMMAND_MEMORY)) { - printf("Error: Can not enable MEMORY access.\n"); - continue; - } - - if (!(status & PCI_COMMAND_MASTER)) { - printf("Error: Can not enable Bus Mastering.\n"); - continue; - } - - /* Check the latency timer for values >= 0x60. */ - pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer); - - if (timer < 0x60) { - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, - 0x60); - } - - /* read BAR for memory space access */ - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; - debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase); - - priv = memalign(32, sizeof(*priv)); - if (!priv) { - printf("Can not allocalte memory of dc21x4x\n"); - break; - } - memset(priv, 0, sizeof(*priv)); - - dev = &priv->dev; - - sprintf(dev->name, "dc21x4x#%d", card_number); - priv->devno = devbusfn; - priv->name = dev->name; - priv->enetaddr = dev->enetaddr; - - dev->iobase = pci_mem_to_phys(devbusfn, iobase); - dev->priv = (void *)devbusfn; - dev->init = dc21x4x_init; - dev->halt = dc21x4x_halt; - dev->send = dc21x4x_send; - dev->recv = dc21x4x_recv; - - /* Ensure we're not sleeping. */ - pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP); - - udelay(10 * 1000); - - read_hw_addr(priv); - - eth_register(dev); - - card_number++; - } - - return card_number; -} - -#else /* DM_ETH */ static int dc2114x_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -756,4 +601,3 @@ U_BOOT_DRIVER(eth_dc2114x) = { }; U_BOOT_PCI_DEVICE(eth_dc2114x, supported); -#endif From acb30ccc7c4d43083689bb1f2266f836e306ee4f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:07 -0500 Subject: [PATCH 083/424] net: designware: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/designware.c | 112 ++------------------------------------- drivers/net/designware.h | 5 -- 2 files changed, 3 insertions(+), 114 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 0e63f70934..ddaf7ed1d3 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -34,12 +34,8 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { -#ifdef CONFIG_DM_ETH struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); struct eth_mac_regs *mac_p = priv->mac_regs_p; -#else - struct eth_mac_regs *mac_p = bus->priv; -#endif ulong start; u16 miiaddr; int timeout = CONFIG_MDIO_TIMEOUT; @@ -62,12 +58,8 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val) { -#ifdef CONFIG_DM_ETH struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); struct eth_mac_regs *mac_p = priv->mac_regs_p; -#else - struct eth_mac_regs *mac_p = bus->priv; -#endif ulong start; u16 miiaddr; int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; @@ -90,7 +82,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, return ret; } -#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) static int __dw_mdio_reset(struct udevice *dev) { struct dw_eth_dev *priv = dev_get_priv(dev); @@ -192,7 +184,7 @@ static int dw_mdio_init(const char *name, void *priv) bus->read = dw_mdio_read; bus->write = dw_mdio_write; snprintf(bus->name, sizeof(bus->name), "%s", name); -#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO) +#if CONFIG_IS_ENABLED(DM_GPIO) bus->reset = dw_mdio_reset; #endif @@ -575,7 +567,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) struct phy_device *phydev; int ret; -#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH) +#if IS_ENABLED(CONFIG_DM_MDIO) phydev = dm_eth_phy_connect(dev); if (!phydev) return -ENODEV; @@ -605,103 +597,6 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) return 0; } -#ifndef CONFIG_DM_ETH -static int dw_eth_init(struct eth_device *dev, struct bd_info *bis) -{ - int ret; - - ret = designware_eth_init(dev->priv, dev->enetaddr); - if (!ret) - ret = designware_eth_enable(dev->priv); - - return ret; -} - -static int dw_eth_send(struct eth_device *dev, void *packet, int length) -{ - return _dw_eth_send(dev->priv, packet, length); -} - -static int dw_eth_recv(struct eth_device *dev) -{ - uchar *packet; - int length; - - length = _dw_eth_recv(dev->priv, &packet); - if (length == -EAGAIN) - return 0; - net_process_received_packet(packet, length); - - _dw_free_pkt(dev->priv); - - return 0; -} - -static void dw_eth_halt(struct eth_device *dev) -{ - return _dw_eth_halt(dev->priv); -} - -static int dw_write_hwaddr(struct eth_device *dev) -{ - return _dw_write_hwaddr(dev->priv, dev->enetaddr); -} - -int designware_initialize(ulong base_addr, u32 interface) -{ - struct eth_device *dev; - struct dw_eth_dev *priv; - - dev = (struct eth_device *) malloc(sizeof(struct eth_device)); - if (!dev) - return -ENOMEM; - - /* - * Since the priv structure contains the descriptors which need a strict - * buswidth alignment, memalign is used to allocate memory - */ - priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, - sizeof(struct dw_eth_dev)); - if (!priv) { - free(dev); - return -ENOMEM; - } - - if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { - printf("designware: buffers are outside DMA memory\n"); - return -EINVAL; - } - - memset(dev, 0, sizeof(struct eth_device)); - memset(priv, 0, sizeof(struct dw_eth_dev)); - - sprintf(dev->name, "dwmac.%lx", base_addr); - dev->iobase = (int)base_addr; - dev->priv = priv; - - priv->dev = dev; - priv->mac_regs_p = (struct eth_mac_regs *)base_addr; - priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + - DW_DMA_BASE_OFFSET); - - dev->init = dw_eth_init; - dev->send = dw_eth_send; - dev->recv = dw_eth_recv; - dev->halt = dw_eth_halt; - dev->write_hwaddr = dw_write_hwaddr; - - eth_register(dev); - - priv->interface = interface; - - dw_mdio_init(dev->name, priv->mac_regs_p); - priv->bus = miiphy_get_dev_by_name(dev->name); - - return dw_phy_init(priv, dev); -} -#endif - -#ifdef CONFIG_DM_ETH static int designware_eth_start(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -971,4 +866,3 @@ static struct pci_device_id supported[] = { }; U_BOOT_PCI_DEVICE(eth_designware, supported); -#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 3793d55098..138c3c14bf 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -233,9 +233,6 @@ struct dw_eth_dev { struct eth_mac_regs *mac_regs_p; struct eth_dma_regs *dma_regs_p; -#ifndef CONFIG_DM_ETH - struct eth_device *dev; -#endif #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; #endif @@ -248,7 +245,6 @@ struct dw_eth_dev { struct mii_dev *bus; }; -#ifdef CONFIG_DM_ETH int designware_eth_of_to_plat(struct udevice *dev); int designware_eth_probe(struct udevice *dev); extern const struct eth_ops designware_eth_ops; @@ -266,6 +262,5 @@ int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length); void designware_eth_stop(struct udevice *dev); int designware_eth_write_hwaddr(struct udevice *dev); -#endif #endif From 9f2d365ed3c8eece717447c4dc73adaea66caeb4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:08 -0500 Subject: [PATCH 084/424] net: dm9000x: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/dm9000x.c | 66 ------------------------------------------- 1 file changed, 66 deletions(-) diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 07733df533..b46bdeb23b 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -75,9 +75,6 @@ struct dm9000_priv { void (*outblk)(struct dm9000_priv *db, void *data_ptr, int count); void (*inblk)(struct dm9000_priv *db, void *data_ptr, int count); void (*rx_status)(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen); -#ifndef CONFIG_DM_ETH - struct eth_device dev; -#endif void __iomem *base_io; void __iomem *base_data; }; @@ -572,68 +569,6 @@ static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) {} #endif -#ifndef CONFIG_DM_ETH -static int dm9000_init(struct eth_device *dev, struct bd_info *bd) -{ - struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev); - - return dm9000_init_common(db, dev->enetaddr); -} - -static void dm9000_halt(struct eth_device *dev) -{ - struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev); - - dm9000_halt_common(db); -} - -static int dm9000_send(struct eth_device *dev, void *packet, int length) -{ - struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev); - - return dm9000_send_common(db, packet, length); -} - -static int dm9000_recv(struct eth_device *dev) -{ - struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev); - int ret; - - ret = dm9000_recv_common(db, net_rx_packets[0]); - if (ret > 0) - net_process_received_packet(net_rx_packets[0], ret); - - return ret; -} - -int dm9000_initialize(struct bd_info *bis) -{ - struct dm9000_priv *priv; - struct eth_device *dev; - - priv = calloc(1, sizeof(*priv)); - if (!priv) - return -ENOMEM; - - dev = &priv->dev; - - priv->base_io = (void __iomem *)DM9000_IO; - priv->base_data = (void __iomem *)DM9000_DATA; - - /* Load MAC address from EEPROM */ - dm9000_get_enetaddr(priv, dev->enetaddr); - - dev->init = dm9000_init; - dev->halt = dm9000_halt; - dev->send = dm9000_send; - dev->recv = dm9000_recv; - strcpy(dev->name, "dm9000"); - - eth_register(&priv->dev); - - return 0; -} -#else /* ifdef CONFIG_DM_ETH */ static int dm9000_start(struct udevice *dev) { struct dm9000_priv *db = dev_get_priv(dev); @@ -746,4 +681,3 @@ U_BOOT_DRIVER(dm9000) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif From 53fa409f59236b84134cc1e215420f9adc1659ff Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:09 -0500 Subject: [PATCH 085/424] net: e1000: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/e1000.c | 216 +------------------------------------------- drivers/net/e1000.h | 11 --- 2 files changed, 1 insertion(+), 226 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 5fe016ebaf..41e6ba760e 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -65,9 +65,7 @@ DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); static int tx_tail; static int rx_tail, rx_last; -#ifdef CONFIG_DM_ETH static int num_cards; /* Number of E1000 devices seen so far */ -#endif static struct pci_device_id e1000_supported[] = { { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, @@ -1611,13 +1609,8 @@ e1000_reset_hw(struct e1000_hw *hw) /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); -#ifdef CONFIG_DM_ETH dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); -#else - pci_write_config_word(hw->pdev, PCI_COMMAND, - hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); -#endif } /* Clear interrupt mask to stop board from generating interrupts */ @@ -1695,11 +1688,7 @@ e1000_reset_hw(struct e1000_hw *hw) /* If MWI was previously enabled, reenable it. */ if (hw->mac_type == e1000_82542_rev2_0) { -#ifdef CONFIG_DM_ETH dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); -#else - pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); -#endif } if (hw->mac_type != e1000_igb) E1000_WRITE_REG(hw, PBA, pba); @@ -1884,15 +1873,9 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); -#ifdef CONFIG_DM_ETH dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw-> pci_cmd_word & ~PCI_COMMAND_INVALIDATE); -#else - pci_write_config_word(hw->pdev, PCI_COMMAND, - hw-> - pci_cmd_word & ~PCI_COMMAND_INVALIDATE); -#endif E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); E1000_WRITE_FLUSH(hw); mdelay(5); @@ -1908,11 +1891,7 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_FLUSH(hw); mdelay(1); -#ifdef CONFIG_DM_ETH dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); -#else - pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); -#endif } /* Zero out the Multicast HASH table */ @@ -1935,17 +1914,10 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ if (hw->bus_type == e1000_bus_type_pcix) { -#ifdef CONFIG_DM_ETH dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word); dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); -#else - pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, - &pcix_cmd_word); - pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, - &pcix_stat_hi_word); -#endif cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; @@ -1957,13 +1929,8 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) if (cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; -#ifdef CONFIG_DM_ETH dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word); -#else - pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, - pcix_cmd_word); -#endif } } break; @@ -5060,7 +5027,6 @@ e1000_sw_init(struct e1000_hw *hw) int result; /* PCI config space info */ -#ifdef CONFIG_DM_ETH dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, @@ -5069,16 +5035,6 @@ e1000_sw_init(struct e1000_hw *hw) dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); -#else - pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); - pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); - pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, - &hw->subsystem_vendor_id); - pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); - - pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); - pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); -#endif /* identify the MAC */ result = e1000_set_mac_type(hw); @@ -5485,51 +5441,25 @@ void e1000_get_bus_type(struct e1000_hw *hw) } } -#ifndef CONFIG_DM_ETH -/* A list of all registered e1000 devices */ -static LIST_HEAD(e1000_hw_list); -#endif - -#ifdef CONFIG_DM_ETH static int e1000_init_one(struct e1000_hw *hw, int cardnum, struct udevice *devno, unsigned char enetaddr[6]) -#else -static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, - unsigned char enetaddr[6]) -#endif { u32 val; /* Assign the passed-in values */ -#ifdef CONFIG_DM_ETH hw->pdev = devno; -#else - hw->pdev = devno; -#endif hw->cardnum = cardnum; /* Print a debug message with the IO base address */ -#ifdef CONFIG_DM_ETH dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); -#else - pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); -#endif E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); /* Try to enable I/O accesses and bus-mastering */ val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; -#ifdef CONFIG_DM_ETH dm_pci_write_config32(devno, PCI_COMMAND, val); -#else - pci_write_config_dword(devno, PCI_COMMAND, val); -#endif /* Make sure it worked */ -#ifdef CONFIG_DM_ETH dm_pci_read_config32(devno, PCI_COMMAND, &val); -#else - pci_read_config_dword(devno, PCI_COMMAND, &val); -#endif if (!(val & PCI_COMMAND_MEMORY)) { E1000_ERR(hw, "Can't enable I/O memory\n"); return -ENOSPC; @@ -5548,13 +5478,8 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, #ifndef CONFIG_E1000_NO_NVM hw->eeprom_semaphore_present = true; #endif -#ifdef CONFIG_DM_ETH hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, PCI_REGION_MEM); -#else - hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); -#endif hw->mac_type = e1000_undefined; /* MAC and Phy settings */ @@ -5599,71 +5524,13 @@ static void e1000_name(char *str, int cardnum) sprintf(str, "e1000#%u", cardnum); } -#ifndef CONFIG_DM_ETH -/************************************************************************** -TRANSMIT - Transmit a frame -***************************************************************************/ -static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) -{ - struct e1000_hw *hw = nic->priv; - - return _e1000_transmit(hw, txpacket, length); -} - -/************************************************************************** -DISABLE - Turn off ethernet interface -***************************************************************************/ -static void -e1000_disable(struct eth_device *nic) -{ - struct e1000_hw *hw = nic->priv; - - _e1000_disable(hw); -} - -/************************************************************************** -INIT - set up ethernet interface(s) -***************************************************************************/ -static int -e1000_init(struct eth_device *nic, struct bd_info *bis) -{ - struct e1000_hw *hw = nic->priv; - - return _e1000_init(hw, nic->enetaddr); -} - -static int -e1000_poll(struct eth_device *nic) -{ - struct e1000_hw *hw = nic->priv; - int len; - - len = _e1000_poll(hw); - if (len) { - net_process_received_packet((uchar *)packet, len); - fill_rx(hw); - } - - return len ? 1 : 0; -} -#endif /* !CONFIG_DM_ETH */ - -#ifdef CONFIG_DM_ETH static int e1000_write_hwaddr(struct udevice *dev) -#else -static int e1000_write_hwaddr(struct eth_device *dev) -#endif { #ifndef CONFIG_E1000_NO_NVM unsigned char current_mac[6]; -#ifdef CONFIG_DM_ETH struct eth_pdata *plat = dev_get_plat(dev); struct e1000_hw *hw = dev_get_priv(dev); u8 *mac = plat->enetaddr; -#else - struct e1000_hw *hw = dev->priv; - u8 *mac = dev->enetaddr; -#endif uint16_t data[3]; int ret_val, i; @@ -5701,87 +5568,16 @@ static int e1000_write_hwaddr(struct eth_device *dev) #endif } -#ifndef CONFIG_DM_ETH -/************************************************************************** -PROBE - Look for an adapter, this routine's visible to the outside -You should omit the last argument struct pci_device * for a non-PCI NIC -***************************************************************************/ -int -e1000_initialize(struct bd_info * bis) -{ - unsigned int i; - pci_dev_t devno; - int ret; - - DEBUGFUNC(); - - /* Find and probe all the matching PCI devices */ - for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { - /* - * These will never get freed due to errors, this allows us to - * perform SPI EEPROM programming from U-Boot, for example. - */ - struct eth_device *nic = malloc(sizeof(*nic)); - struct e1000_hw *hw = malloc(sizeof(*hw)); - if (!nic || !hw) { - printf("e1000#%u: Out of Memory!\n", i); - free(nic); - free(hw); - continue; - } - - /* Make sure all of the fields are initially zeroed */ - memset(nic, 0, sizeof(*nic)); - memset(hw, 0, sizeof(*hw)); - nic->priv = hw; - - /* Generate a card name */ - e1000_name(nic->name, i); - hw->name = nic->name; - - ret = e1000_init_one(hw, i, devno, nic->enetaddr); - if (ret) - continue; - list_add_tail(&hw->list_node, &e1000_hw_list); - - hw->nic = nic; - - /* Set up the function pointers and register the device */ - nic->init = e1000_init; - nic->recv = e1000_poll; - nic->send = e1000_transmit; - nic->halt = e1000_disable; - nic->write_hwaddr = e1000_write_hwaddr; - eth_register(nic); - } - - return i; -} - -struct e1000_hw *e1000_find_card(unsigned int cardnum) -{ - struct e1000_hw *hw; - - list_for_each_entry(hw, &e1000_hw_list, list_node) - if (hw->cardnum == cardnum) - return hw; - - return NULL; -} -#endif /* !CONFIG_DM_ETH */ - #ifdef CONFIG_CMD_E1000 static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { unsigned char *mac = NULL; -#ifdef CONFIG_DM_ETH struct eth_pdata *plat; struct udevice *dev; char name[30]; int ret; -#endif -#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI) +#if defined(CONFIG_E1000_SPI) struct e1000_hw *hw; #endif int cardnum; @@ -5793,18 +5589,12 @@ static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc, /* Make sure we can find the requested e1000 card */ cardnum = dectoul(argv[1], NULL); -#ifdef CONFIG_DM_ETH e1000_name(name, cardnum); ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); if (!ret) { plat = dev_get_plat(dev); mac = plat->enetaddr; } -#else - hw = e1000_find_card(cardnum); - if (hw) - mac = hw->nic->enetaddr; -#endif if (!mac) { printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); return 1; @@ -5817,9 +5607,7 @@ static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc, } #ifdef CONFIG_E1000_SPI -#ifdef CONFIG_DM_ETH hw = dev_get_priv(dev); -#endif /* Handle the "SPI" subcommand */ if (!strcmp(argv[2], "spi")) return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); @@ -5843,7 +5631,6 @@ U_BOOT_CMD( ); #endif /* not CONFIG_CMD_E1000 */ -#ifdef CONFIG_DM_ETH static int e1000_eth_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -5948,4 +5735,3 @@ U_BOOT_DRIVER(eth_e1000) = { }; U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); -#endif diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index f96f12c8f4..f788394da8 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -21,10 +21,6 @@ #include #include #include -/* Avoids a compile error since struct eth_device is not defined */ -#ifndef CONFIG_DM_ETH -#include -#endif #include #include @@ -1077,19 +1073,12 @@ typedef enum { struct e1000_hw { const char *name; struct list_head list_node; -#ifndef CONFIG_DM_ETH - struct eth_device *nic; -#endif #ifdef CONFIG_E1000_SPI struct spi_slave spi; #endif unsigned int cardnum; -#ifdef CONFIG_DM_ETH struct udevice *pdev; -#else - pci_dev_t pdev; -#endif uint8_t *hw_addr; e1000_mac_type mac_type; e1000_phy_type phy_type; From 4fb814f571e01a3702e9d58497c57e1892070c2e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:10 -0500 Subject: [PATCH 086/424] net: eepro100: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/eepro100.c | 134 ----------------------------------------- 1 file changed, 134 deletions(-) diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 935cd9c99c..a0424505bd 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -206,27 +206,14 @@ struct eepro100_priv { /* TX descriptor ring pointer */ int tx_next; int tx_threshold; -#ifdef CONFIG_DM_ETH struct udevice *devno; -#else - struct eth_device dev; - pci_dev_t devno; -#endif char *name; void __iomem *iobase; u8 *enetaddr; }; -#if defined(CONFIG_DM_ETH) #define bus_to_phys(dev, a) dm_pci_mem_to_phys((dev), (a)) #define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a)) -#elif defined(CONFIG_E500) -#define bus_to_phys(dev, a) (a) -#define phys_to_bus(dev, a) (a) -#else -#define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a)) -#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a)) -#endif static int INW(struct eepro100_priv *priv, u_long addr) { @@ -778,126 +765,6 @@ done: return; } -#ifndef CONFIG_DM_ETH -static int eepro100_init(struct eth_device *dev, struct bd_info *bis) -{ - struct eepro100_priv *priv = - container_of(dev, struct eepro100_priv, dev); - - return eepro100_init_common(priv); -} - -static void eepro100_halt(struct eth_device *dev) -{ - struct eepro100_priv *priv = - container_of(dev, struct eepro100_priv, dev); - - eepro100_halt_common(priv); -} - -static int eepro100_send(struct eth_device *dev, void *packet, int length) -{ - struct eepro100_priv *priv = - container_of(dev, struct eepro100_priv, dev); - - return eepro100_send_common(priv, packet, length); -} - -static int eepro100_recv(struct eth_device *dev) -{ - struct eepro100_priv *priv = - container_of(dev, struct eepro100_priv, dev); - uchar *packet; - int ret; - - ret = eepro100_recv_common(priv, &packet); - if (ret > 0) - net_process_received_packet(packet, ret); - if (ret) - eepro100_free_pkt_common(priv); - - return ret; -} - -int eepro100_initialize(struct bd_info *bis) -{ - struct eepro100_priv *priv; - struct eth_device *dev; - int card_number = 0; - u32 iobase, status; - pci_dev_t devno; - int idx = 0; - int ret; - - while (1) { - /* Find PCI device */ - devno = pci_find_devices(supported, idx++); - if (devno < 0) - break; - - pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase); - iobase &= ~0xf; - - debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", - iobase); - - pci_write_config_dword(devno, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Check if I/O accesses and Bus Mastering are enabled. */ - pci_read_config_dword(devno, PCI_COMMAND, &status); - if (!(status & PCI_COMMAND_MEMORY)) { - printf("Error: Can not enable MEM access.\n"); - continue; - } - - if (!(status & PCI_COMMAND_MASTER)) { - printf("Error: Can not enable Bus Mastering.\n"); - continue; - } - - priv = calloc(1, sizeof(*priv)); - if (!priv) { - printf("eepro100: Can not allocate memory\n"); - break; - } - dev = &priv->dev; - - sprintf(dev->name, "i82559#%d", card_number); - priv->name = dev->name; - /* this have to come before bus_to_phys() */ - priv->devno = devno; - priv->iobase = (void __iomem *)bus_to_phys(devno, iobase); - priv->enetaddr = dev->enetaddr; - - dev->init = eepro100_init; - dev->halt = eepro100_halt; - dev->send = eepro100_send; - dev->recv = eepro100_recv; - - eth_register(dev); - - ret = eepro100_initialize_mii(priv); - if (ret) { - eth_unregister(dev); - free(priv); - return ret; - } - - card_number++; - - /* Set the latency timer for value. */ - pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); - - udelay(10 * 1000); - - eepro100_get_hwaddr(priv); - } - - return card_number; -} - -#else /* DM_ETH */ static int eepro100_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -1014,4 +881,3 @@ U_BOOT_DRIVER(eth_eepro100) = { }; U_BOOT_PCI_DEVICE(eth_eepro100, supported); -#endif From ecca44805d9a00e8e9ac6c14d9e7293565900981 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:11 -0500 Subject: [PATCH 087/424] net: ethoc: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/ethoc.c | 85 ---------------------------- include/dm/platform_data/net_ethoc.h | 4 -- 2 files changed, 89 deletions(-) diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index a219affb58..29067e9e94 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -643,8 +643,6 @@ static inline int ethoc_phy_init(struct ethoc *priv, void *dev) #endif -#ifdef CONFIG_DM_ETH - static int ethoc_write_hwaddr(struct udevice *dev) { struct ethoc_eth_pdata *pdata = dev_get_plat(dev); @@ -753,86 +751,3 @@ U_BOOT_DRIVER(ethoc) = { .priv_auto = sizeof(struct ethoc), .plat_auto = sizeof(struct ethoc_eth_pdata), }; - -#else - -static int ethoc_init(struct eth_device *dev, struct bd_info *bd) -{ - struct ethoc *priv = (struct ethoc *)dev->priv; - - return ethoc_init_common(priv); -} - -static int ethoc_write_hwaddr(struct eth_device *dev) -{ - struct ethoc *priv = (struct ethoc *)dev->priv; - u8 *mac = dev->enetaddr; - - return ethoc_write_hwaddr_common(priv, mac); -} - -static int ethoc_send(struct eth_device *dev, void *packet, int length) -{ - return ethoc_send_common(dev->priv, packet, length); -} - -static void ethoc_halt(struct eth_device *dev) -{ - ethoc_disable_rx_and_tx(dev->priv); -} - -static int ethoc_recv(struct eth_device *dev) -{ - struct ethoc *priv = (struct ethoc *)dev->priv; - int count; - - if (!ethoc_is_new_packet_received(priv)) - return 0; - - for (count = 0; count < PKTBUFSRX; ++count) { - uchar *packetp; - int size = ethoc_rx_common(priv, &packetp); - - if (size < 0) - break; - if (size > 0) - net_process_received_packet(packetp, size); - ethoc_free_pkt_common(priv); - } - return 0; -} - -int ethoc_initialize(u8 dev_num, int base_addr) -{ - struct ethoc *priv; - struct eth_device *dev; - - priv = malloc(sizeof(*priv)); - if (!priv) - return 0; - dev = malloc(sizeof(*dev)); - if (!dev) { - free(priv); - return 0; - } - - memset(dev, 0, sizeof(*dev)); - dev->priv = priv; - dev->iobase = base_addr; - dev->init = ethoc_init; - dev->halt = ethoc_halt; - dev->send = ethoc_send; - dev->recv = ethoc_recv; - dev->write_hwaddr = ethoc_write_hwaddr; - sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); - priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE); - - eth_register(dev); - - ethoc_mdio_init(dev->name, priv); - ethoc_phy_init(priv, dev); - - return 1; -} - -#endif diff --git a/include/dm/platform_data/net_ethoc.h b/include/dm/platform_data/net_ethoc.h index 855e9999a0..44547d14f5 100644 --- a/include/dm/platform_data/net_ethoc.h +++ b/include/dm/platform_data/net_ethoc.h @@ -8,13 +8,9 @@ #include -#ifdef CONFIG_DM_ETH - struct ethoc_eth_pdata { struct eth_pdata eth_pdata; phys_addr_t packet_base; }; -#endif - #endif /* _ETHOC_H */ From b669c54bfdf06648b66679468cd36ecb3ed2cb43 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:12 -0500 Subject: [PATCH 088/424] net: fec_mxc: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/fec_mxc.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 48faa33d66..77bfc1cbf4 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -263,9 +263,7 @@ struct fec_priv { uint32_t reset_delay; uint32_t reset_post_delay; #endif -#ifdef CONFIG_DM_ETH u32 interface; -#endif struct clk ipg_clk; struct clk ahb_clk; struct clk clk_enet_out; From 3c7e652bbb0e2dd1f356ba5631281068adeb5b53 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:13 -0500 Subject: [PATCH 089/424] net: fsl-mc: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/fsl-mc/mc.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 69da465eaa..6b36860187 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -165,21 +165,12 @@ enum mc_fixup_type { }; static int mc_fixup_mac_addr(void *blob, int nodeoffset, -#ifdef CONFIG_DM_ETH const char *propname, struct udevice *eth_dev, -#else - const char *propname, struct eth_device *eth_dev, -#endif enum mc_fixup_type type) { -#ifdef CONFIG_DM_ETH struct eth_pdata *plat = dev_get_plat(eth_dev); unsigned char *enetaddr = plat->enetaddr; int eth_index = dev_seq(eth_dev); -#else - unsigned char *enetaddr = eth_dev->enetaddr; - int eth_index = eth_dev->index; -#endif int err = 0, len = 0, size, i; unsigned char env_enetaddr[ARP_HLEN]; unsigned int enetaddr_32[ARP_HLEN]; @@ -252,11 +243,7 @@ const char *dpl_get_connection_endpoint(void *blob, char *endpoint) } static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id, -#ifdef CONFIG_DM_ETH struct udevice *eth_dev) -#else - struct eth_device *eth_dev) -#endif { int objoff = fdt_path_offset(blob, "/objects"); int dpmacoff = -1, dpnioff = -1; @@ -355,11 +342,7 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob) } static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, -#ifdef CONFIG_DM_ETH struct udevice *eth_dev) -#else - struct eth_device *eth_dev) -#endif { int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff; int err = 0; @@ -402,12 +385,8 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type) { int i, err = 0, ret = 0; -#ifdef CONFIG_DM_ETH #define ETH_NAME_LEN 20 struct udevice *eth_dev; -#else - struct eth_device *eth_dev; -#endif char ethname[ETH_NAME_LEN]; for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { From cde5a844fbba61362085369ed2f5de904719eeea Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:14 -0500 Subject: [PATCH 090/424] net: ldpaa_eth: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/ldpaa_eth/ldpaa_eth.c | 198 +----------------------------- drivers/net/ldpaa_eth/ldpaa_eth.h | 4 - 2 files changed, 2 insertions(+), 200 deletions(-) diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index b6f589eb91..2485077794 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -24,7 +24,6 @@ #include "ldpaa_eth.h" #ifdef CONFIG_PHYLIB -#ifdef CONFIG_DM_ETH static void init_phy(struct udevice *dev) { struct ldpaa_eth_priv *priv = dev_get_priv(dev); @@ -36,51 +35,6 @@ static void init_phy(struct udevice *dev) phy_config(priv->phy); } -#else -static int init_phy(struct eth_device *dev) -{ - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv; - struct phy_device *phydev = NULL; - struct mii_dev *bus; - int phy_addr, phy_num; - int ret = 0; - - bus = wriop_get_mdio(priv->dpmac_id); - if (bus == NULL) - return 0; - - for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { - phy_addr = wriop_get_phy_address(priv->dpmac_id, phy_num); - if (phy_addr < 0) - continue; - - phydev = phy_connect(bus, phy_addr, dev, - wriop_get_enet_if(priv->dpmac_id)); - if (!phydev) { - printf("Failed to connect\n"); - ret = -ENODEV; - break; - } - wriop_set_phy_dev(priv->dpmac_id, phy_num, phydev); - ret = phy_config(phydev); - if (ret) - break; - } - - if (ret) { - for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { - phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num); - if (!phydev) - continue; - - free(phydev); - wriop_set_phy_dev(priv->dpmac_id, phy_num, NULL); - } - } - - return ret; -} -#endif #endif #ifdef DEBUG @@ -147,15 +101,9 @@ static void ldpaa_eth_get_dpni_counter(void) } } -#ifdef CONFIG_DM_ETH static void ldpaa_eth_get_dpmac_counter(struct udevice *dev) { struct ldpaa_eth_priv *priv = dev_get_priv(dev); -#else -static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev) -{ - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; -#endif int err = 0; u64 value; @@ -288,16 +236,10 @@ error: return; } -#ifdef CONFIG_DM_ETH static int ldpaa_eth_pull_dequeue_rx(struct udevice *dev, int flags, uchar **packetp) { struct ldpaa_eth_priv *priv = dev_get_priv(dev); -#else -static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev) -{ - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv; -#endif const struct ldpaa_dq *dq; const struct dpaa_fd *fd; int i = 5, err = 0, status; @@ -354,15 +296,9 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev) return err; } -#ifdef CONFIG_DM_ETH static int ldpaa_eth_tx(struct udevice *dev, void *buf, int len) { struct ldpaa_eth_priv *priv = dev_get_priv(dev); -#else -static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len) -{ - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; -#endif struct dpaa_fd fd; u64 buffer_start; int data_offset, err; @@ -438,27 +374,6 @@ error: return err; } -static struct phy_device *ldpaa_get_phydev(struct ldpaa_eth_priv *priv) -{ -#ifdef CONFIG_DM_ETH - return priv->phy; -#else -#ifdef CONFIG_PHYLIB - struct phy_device *phydev = NULL; - int phy_num; - - /* start the phy devices one by one and update the dpmac state */ - for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { - phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num); - if (phydev) - return phydev; - } - return NULL; -#endif - return NULL; -#endif -} - static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv, struct dpmac_link_state *state) { @@ -479,7 +394,7 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv, state->up = 1; state->options |= DPMAC_LINK_OPT_AUTONEG; - phydev = ldpaa_get_phydev(priv); + phydev = priv->phy; if (phydev) { err = phy_startup(phydev); @@ -509,16 +424,10 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv, return 0; } -#ifdef CONFIG_DM_ETH static int ldpaa_eth_open(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); struct ldpaa_eth_priv *priv = dev_get_priv(dev); -#else -static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd) -{ - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; -#endif struct dpmac_link_state dpmac_link_state = { 0 }; #ifdef DEBUG struct dpni_link_state link_state; @@ -526,13 +435,8 @@ static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd) int err = 0; struct dpni_queue d_queue; -#ifdef CONFIG_DM_ETH if (eth_is_active(dev)) return 0; -#else - if (net_dev->state == ETH_STATE_ACTIVE) - return 0; -#endif if (get_mc_boot_status() != 0) { printf("ERROR (MC is not booted)\n"); @@ -572,13 +476,8 @@ static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd) if (err) goto err_dpni_bind; -#ifdef CONFIG_DM_ETH err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, plat->enetaddr); -#else - err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpni->dpni_handle, net_dev->enetaddr); -#endif if (err) { printf("dpni_add_mac_addr() failed\n"); return err; @@ -651,34 +550,18 @@ err_dpmac_setup: return err; } -#ifdef CONFIG_DM_ETH static void ldpaa_eth_stop(struct udevice *dev) { struct ldpaa_eth_priv *priv = dev_get_priv(dev); -#else -static void ldpaa_eth_stop(struct eth_device *net_dev) -{ - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; -#endif struct phy_device *phydev = NULL; int err = 0; -#ifdef CONFIG_DM_ETH if (!eth_is_active(dev)) return; -#else - if ((net_dev->state == ETH_STATE_PASSIVE) || - (net_dev->state == ETH_STATE_INIT)) - return; -#endif #ifdef DEBUG ldpaa_eth_get_dpni_counter(); -#ifdef CONFIG_DM_ETH ldpaa_eth_get_dpmac_counter(dev); -#else - ldpaa_eth_get_dpmac_counter(net_dev); -#endif #endif err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, @@ -702,7 +585,7 @@ static void ldpaa_eth_stop(struct eth_device *net_dev) if (err < 0) printf("dpni_disable() failed\n"); - phydev = ldpaa_get_phydev(priv); + phydev = priv->phy; if (phydev) phy_shutdown(phydev); @@ -1097,7 +980,6 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) return 0; } -#ifdef CONFIG_DM_ETH static int ldpaa_eth_probe(struct udevice *dev) { struct ofnode_phandle_args phandle; @@ -1177,79 +1059,3 @@ U_BOOT_DRIVER(ldpaa_eth) = { .priv_auto = sizeof(struct ldpaa_eth_priv), .plat_auto = sizeof(struct eth_pdata), }; - -#else - -static int ldpaa_eth_netdev_init(struct eth_device *net_dev, - phy_interface_t enet_if) -{ - int err; - struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv; - - snprintf(net_dev->name, ETH_NAME_LEN, "DPMAC%d@%s", priv->dpmac_id, - phy_interface_strings[enet_if]); - - net_dev->iobase = 0; - net_dev->init = ldpaa_eth_open; - net_dev->halt = ldpaa_eth_stop; - net_dev->send = ldpaa_eth_tx; - net_dev->recv = ldpaa_eth_pull_dequeue_rx; - -#ifdef CONFIG_PHYLIB - err = init_phy(net_dev); - if (err < 0) - return err; -#endif - - err = eth_register(net_dev); - if (err < 0) { - printf("eth_register() = %d\n", err); - return err; - } - - return 0; -} - -int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if) -{ - struct eth_device *net_dev = NULL; - struct ldpaa_eth_priv *priv = NULL; - int err = 0; - - /* Net device */ - net_dev = (struct eth_device *)malloc(sizeof(struct eth_device)); - if (!net_dev) { - printf("eth_device malloc() failed\n"); - return -ENOMEM; - } - memset(net_dev, 0, sizeof(struct eth_device)); - - /* alloc the ldpaa ethernet private struct */ - priv = (struct ldpaa_eth_priv *)malloc(sizeof(struct ldpaa_eth_priv)); - if (!priv) { - printf("ldpaa_eth_priv malloc() failed\n"); - free(net_dev); - return -ENOMEM; - } - memset(priv, 0, sizeof(struct ldpaa_eth_priv)); - - net_dev->priv = (void *)priv; - priv->net_dev = (struct eth_device *)net_dev; - priv->dpmac_id = dpmac_id; - debug("%s dpmac_id=%d\n", __func__, dpmac_id); - - err = ldpaa_eth_netdev_init(net_dev, enet_if); - if (err) - goto err_netdev_init; - - debug("ldpaa ethernet: Probed interface %s\n", net_dev->name); - return 0; - -err_netdev_init: - free(priv); - net_dev->priv = NULL; - free(net_dev); - - return err; -} -#endif diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index e90513e56f..16d0106233 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -116,13 +116,9 @@ struct ldpaa_fas { LDPAA_ETH_FAS_TIDE) struct ldpaa_eth_priv { -#ifdef CONFIG_DM_ETH struct phy_device *phy; int phy_mode; bool started; -#else - struct eth_device *net_dev; -#endif uint32_t dpmac_id; uint16_t dpmac_handle; From 047a086fa3a4670f189eb80888f566d304a4e088 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:15 -0500 Subject: [PATCH 091/424] net: macb: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/macb.c | 194 +-------------------------------------------- 1 file changed, 2 insertions(+), 192 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 65ec1f24ad..bfc48dac07 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -33,9 +33,6 @@ */ #include -#ifndef CONFIG_DM_ETH -#include -#endif #include #include @@ -131,21 +128,16 @@ struct macb_device { unsigned long dummy_desc_dma; const struct device *dev; -#ifndef CONFIG_DM_ETH - struct eth_device netdev; -#endif unsigned short phy_addr; struct mii_dev *bus; #ifdef CONFIG_PHYLIB struct phy_device *phydev; #endif -#ifdef CONFIG_DM_ETH #ifdef CONFIG_CLK unsigned long pclk_rate; #endif phy_interface_t phy_interface; -#endif }; struct macb_usrio_cfg { @@ -164,10 +156,6 @@ struct macb_config { const struct macb_usrio_cfg *usrio; }; -#ifndef CONFIG_DM_ETH -#define to_macb(_nd) container_of(_nd, struct macb_device, netdev) -#endif - static int macb_is_gem(struct macb_device *macb) { return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2; @@ -258,13 +246,8 @@ void __weak arch_get_mdio_control(const char *name) int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) { u16 value = 0; -#ifdef CONFIG_DM_ETH struct udevice *dev = eth_get_dev_by_name(bus->name); struct macb_device *macb = dev_get_priv(dev); -#else - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct macb_device *macb = to_macb(dev); -#endif arch_get_mdio_control(bus->name); value = macb_mdio_read(macb, phy_adr, reg); @@ -275,13 +258,8 @@ int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, u16 value) { -#ifdef CONFIG_DM_ETH struct udevice *dev = eth_get_dev_by_name(bus->name); struct macb_device *macb = dev_get_priv(dev); -#else - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct macb_device *macb = to_macb(dev); -#endif arch_get_mdio_control(bus->name); macb_mdio_write(macb, phy_adr, reg, value); @@ -598,7 +576,6 @@ static int macb_phy_find(struct macb_device *macb, const char *name) * Returns 0 when operation success and negative errno number * when operation failed. */ -#ifdef CONFIG_DM_ETH static int macb_sifive_clk_init(struct udevice *dev, ulong rate) { void *gemgxl_regs; @@ -678,22 +655,10 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed) return 0; } -#else -int __weak macb_linkspd_cb(void *regs, unsigned int speed) -{ - return 0; -} -#endif -#ifdef CONFIG_DM_ETH static int macb_phy_init(struct udevice *dev, const char *name) -#else -static int macb_phy_init(struct macb_device *macb, const char *name) -#endif { -#ifdef CONFIG_DM_ETH struct macb_device *macb = dev_get_priv(dev); -#endif u32 ncfgr; u16 phy_id, status, adv, lpa; int media, speed, duplex; @@ -714,14 +679,8 @@ static int macb_phy_init(struct macb_device *macb, const char *name) } #ifdef CONFIG_PHYLIB -#ifdef CONFIG_DM_ETH macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev, macb->phy_interface); -#else - /* need to consider other phy interface mode */ - macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, - PHY_INTERFACE_MODE_RGMII); -#endif if (!macb->phydev) { printf("phy_connect failed\n"); return -ENODEV; @@ -778,11 +737,7 @@ static int macb_phy_init(struct macb_device *macb, const char *name) macb_writel(macb, NCFGR, ncfgr); -#ifdef CONFIG_DM_ETH ret = macb_linkspd_cb(dev, _1000BASET); -#else - ret = macb_linkspd_cb(macb->regs, _1000BASET); -#endif if (ret) return ret; @@ -807,17 +762,9 @@ static int macb_phy_init(struct macb_device *macb, const char *name) ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); if (speed) { ncfgr |= MACB_BIT(SPD); -#ifdef CONFIG_DM_ETH ret = macb_linkspd_cb(dev, _100BASET); -#else - ret = macb_linkspd_cb(macb->regs, _100BASET); -#endif } else { -#ifdef CONFIG_DM_ETH ret = macb_linkspd_cb(dev, _10BASET); -#else - ret = macb_linkspd_cb(macb->regs, _10BASET); -#endif } if (ret) @@ -891,16 +838,10 @@ static void gmac_configure_dma(struct macb_device *macb) gem_writel(macb, DMACFG, dmacfg); } -#ifdef CONFIG_DM_ETH static int _macb_init(struct udevice *dev, const char *name) -#else -static int _macb_init(struct macb_device *macb, const char *name) -#endif { -#ifdef CONFIG_DM_ETH struct macb_device *macb = dev_get_priv(dev); unsigned int val = 0; -#endif unsigned long paddr; int ret; int i; @@ -969,7 +910,6 @@ static int _macb_init(struct macb_device *macb, const char *name) * When the GMAC IP without GE feature, this bit is used * to select interface between RMII and MII. */ -#ifdef CONFIG_DM_ETH if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII || macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID || @@ -991,16 +931,8 @@ static int _macb_init(struct macb_device *macb, const char *name) ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); macb_writel(macb, NCFGR, ncfgr); } -#else -#if defined(CONFIG_RGMII) || defined(CONFIG_RMII) - gem_writel(macb, USRIO, macb->config->usrio->rgmii); -#else - gem_writel(macb, USRIO, 0); -#endif -#endif } else { /* choose RMII or MII mode. This depends on the board */ -#ifdef CONFIG_DM_ETH #ifdef CONFIG_AT91FAMILY if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { macb_writel(macb, USRIO, @@ -1014,30 +946,10 @@ static int _macb_init(struct macb_device *macb, const char *name) macb_writel(macb, USRIO, 0); else macb_writel(macb, USRIO, macb->config->usrio->mii); -#endif -#else -#ifdef CONFIG_RMII -#ifdef CONFIG_AT91FAMILY - macb_writel(macb, USRIO, macb->config->usrio->rmii | - macb->config->usrio->clken); -#else - macb_writel(macb, USRIO, 0); -#endif -#else -#ifdef CONFIG_AT91FAMILY - macb_writel(macb, USRIO, macb->config->usrio->clken); -#else - macb_writel(macb, USRIO, macb->config->usrio->mii); -#endif -#endif /* CONFIG_RMII */ #endif } -#ifdef CONFIG_DM_ETH ret = macb_phy_init(dev, name); -#else - ret = macb_phy_init(macb, name); -#endif if (ret) return ret; @@ -1081,7 +993,7 @@ static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) static u32 macb_mdc_clk_div(int id, struct macb_device *macb) { u32 config; -#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) +#if defined(CONFIG_CLK) unsigned long macb_hz = macb->pclk_rate; #else unsigned long macb_hz = get_macb_pclk_rate(id); @@ -1103,7 +1015,7 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb) { u32 config; -#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) +#if defined(CONFIG_CLK) unsigned long macb_hz = macb->pclk_rate; #else unsigned long macb_hz = get_macb_pclk_rate(id); @@ -1182,106 +1094,6 @@ static void _macb_eth_initialize(struct macb_device *macb) macb_writel(macb, NCFGR, ncfgr); } -#ifndef CONFIG_DM_ETH -static int macb_send(struct eth_device *netdev, void *packet, int length) -{ - struct macb_device *macb = to_macb(netdev); - - return _macb_send(macb, netdev->name, packet, length); -} - -static int macb_recv(struct eth_device *netdev) -{ - struct macb_device *macb = to_macb(netdev); - uchar *packet; - int length; - - macb->wrapped = false; - for (;;) { - macb->next_rx_tail = macb->rx_tail; - length = _macb_recv(macb, &packet); - if (length >= 0) { - net_process_received_packet(packet, length); - reclaim_rx_buffers(macb, macb->next_rx_tail); - } else { - return length; - } - } -} - -static int macb_init(struct eth_device *netdev, struct bd_info *bd) -{ - struct macb_device *macb = to_macb(netdev); - - return _macb_init(macb, netdev->name); -} - -static void macb_halt(struct eth_device *netdev) -{ - struct macb_device *macb = to_macb(netdev); - - return _macb_halt(macb); -} - -static int macb_write_hwaddr(struct eth_device *netdev) -{ - struct macb_device *macb = to_macb(netdev); - - return _macb_write_hwaddr(macb, netdev->enetaddr); -} - -int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) -{ - struct macb_device *macb; - struct eth_device *netdev; - - macb = malloc(sizeof(struct macb_device)); - if (!macb) { - printf("Error: Failed to allocate memory for MACB%d\n", id); - return -1; - } - memset(macb, 0, sizeof(struct macb_device)); - - netdev = &macb->netdev; - - macb->regs = regs; - macb->phy_addr = phy_addr; - - if (macb_is_gem(macb)) - sprintf(netdev->name, "gmac%d", id); - else - sprintf(netdev->name, "macb%d", id); - - netdev->init = macb_init; - netdev->halt = macb_halt; - netdev->send = macb_send; - netdev->recv = macb_recv; - netdev->write_hwaddr = macb_write_hwaddr; - - _macb_eth_initialize(macb); - - eth_register(netdev); - -#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); - mdiodev->read = macb_miiphy_read; - mdiodev->write = macb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - macb->bus = miiphy_get_dev_by_name(netdev->name); -#endif - return 0; -} -#endif /* !CONFIG_DM_ETH */ - -#ifdef CONFIG_DM_ETH - static int macb_start(struct udevice *dev) { return _macb_init(dev, dev->name); @@ -1536,5 +1348,3 @@ U_BOOT_DRIVER(eth_macb) = { .plat_auto = sizeof(struct eth_pdata), }; #endif - -#endif From c00e9467bc0f8c5213186219838b5451fbdc3002 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:16 -0500 Subject: [PATCH 092/424] net: mcfmii: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/mcfmii.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index e2c8f41876..48dd558405 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -85,11 +85,7 @@ void mii_reset(fec_info_t *info) /* send command to phy using mii, wait for result */ uint mii_send(uint mii_cmd) { -#ifdef CONFIG_DM_ETH struct udevice *dev; -#else - struct eth_device *dev; -#endif fec_info_t *info; volatile FEC_T *ep; uint mii_reply; @@ -97,11 +93,7 @@ uint mii_send(uint mii_cmd) /* retrieve from register structure */ dev = eth_get_dev(); -#ifdef CONFIG_DM_ETH info = dev_get_priv(dev); -#else - info = dev->priv; -#endif ep = (FEC_T *) info->miibase; @@ -202,11 +194,7 @@ int mii_discover_phy(fec_info_t *info) __weak void mii_init(void) { -#ifdef CONFIG_DM_ETH struct udevice *dev; -#else - struct eth_device *dev; -#endif fec_info_t *info; volatile FEC_T *fecp; int miispd = 0, i = 0; @@ -215,11 +203,7 @@ __weak void mii_init(void) /* retrieve from register structure */ dev = eth_get_dev(); -#ifdef CONFIG_DM_ETH info = dev_get_priv(dev); -#else - info = dev->priv; -#endif fecp = (FEC_T *) info->miibase; From c7f15a3ee846d529097d357d8410804f05b5cc7f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:17 -0500 Subject: [PATCH 093/424] net: mvgbe: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/mvgbe.c | 214 +------------------------------------------- drivers/net/mvgbe.h | 8 -- 2 files changed, 2 insertions(+), 220 deletions(-) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index a77c057432..58363fce05 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -132,12 +132,7 @@ static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr, static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, int reg_ofs) { -#ifdef CONFIG_DM_ETH struct mvgbe_device *dmvgbe = bus->priv; -#else - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct mvgbe_device *dmvgbe = to_mvgbe(dev); -#endif return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs); } @@ -189,12 +184,7 @@ static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr, static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, int reg_ofs, u16 data) { -#ifdef CONFIG_DM_ETH struct mvgbe_device *dmvgbe = bus->priv; -#else - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct mvgbe_device *dmvgbe = to_mvgbe(dev); -#endif return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data); } @@ -432,12 +422,6 @@ static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr, const char *name) { struct mvgbe_registers *regs = dmvgbe->regs; -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ - !defined(CONFIG_PHYLIB) && \ - !defined(CONFIG_DM_ETH) && \ - defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) - int i; -#endif /* setup RX rings */ mvgbe_init_rx_desc_ring(dmvgbe); @@ -486,37 +470,9 @@ static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr, /* Enable port Rx. */ MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ - !defined(CONFIG_PHYLIB) && \ - !defined(CONFIG_DM_ETH) && \ - defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) - /* Wait up to 5s for the link status */ - for (i = 0; i < 5; i++) { - u16 phyadr; - - miiphy_read(name, MV_PHY_ADR_REQUEST, - MV_PHY_ADR_REQUEST, &phyadr); - /* Return if we get link up */ - if (miiphy_link(name, phyadr)) - return 0; - udelay(1000000); - } - - printf("No link on %s\n", name); - return -1; -#endif return 0; } -#ifndef CONFIG_DM_ETH -static int mvgbe_init(struct eth_device *dev) -{ - struct mvgbe_device *dmvgbe = to_mvgbe(dev); - - return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name); -} -#endif - static void __mvgbe_halt(struct mvgbe_device *dmvgbe) { struct mvgbe_registers *regs = dmvgbe->regs; @@ -542,18 +498,6 @@ static void __mvgbe_halt(struct mvgbe_device *dmvgbe) MVGBE_REG_WR(regs->peim, 0); } -#ifndef CONFIG_DM_ETH -static int mvgbe_halt(struct eth_device *dev) -{ - struct mvgbe_device *dmvgbe = to_mvgbe(dev); - - __mvgbe_halt(dmvgbe); - - return 0; -} -#endif - -#ifdef CONFIG_DM_ETH static int mvgbe_write_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -562,16 +506,6 @@ static int mvgbe_write_hwaddr(struct udevice *dev) return 0; } -#else -static int mvgbe_write_hwaddr(struct eth_device *dev) -{ - struct mvgbe_device *dmvgbe = to_mvgbe(dev); - - /* Programs net device MAC address after initialization */ - port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr); - return 0; -} -#endif static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr, int datasize) @@ -628,15 +562,6 @@ static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr, return 0; } -#ifndef CONFIG_DM_ETH -static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize) -{ - struct mvgbe_device *dmvgbe = to_mvgbe(dev); - - return __mvgbe_send(dmvgbe, dataptr, datasize); -} -#endif - static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp) { struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; @@ -710,35 +635,11 @@ static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp) return rx_bytes; } -#ifndef CONFIG_DM_ETH -static int mvgbe_recv(struct eth_device *dev) -{ - struct mvgbe_device *dmvgbe = to_mvgbe(dev); - uchar *packet; - int ret; - - ret = __mvgbe_recv(dmvgbe, &packet); - if (ret < 0) - return ret; - - net_process_received_packet(packet, ret); - - return 0; -} -#endif - -#if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH) -#if defined(CONFIG_DM_ETH) +#if defined(CONFIG_PHYLIB) static struct phy_device *__mvgbe_phy_init(struct udevice *dev, struct mii_dev *bus, phy_interface_t phy_interface, int phyid) -#else -static struct phy_device *__mvgbe_phy_init(struct eth_device *dev, - struct mii_dev *bus, - phy_interface_t phy_interface, - int phyid) -#endif { struct phy_device *phydev; @@ -760,38 +661,7 @@ static struct phy_device *__mvgbe_phy_init(struct eth_device *dev, return phydev; } -#endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */ - -#if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH) -int mvgbe_phylib_init(struct eth_device *dev, int phyid) -{ - struct mii_dev *bus; - struct phy_device *phydev; - int ret; - - bus = mdio_alloc(); - if (!bus) { - printf("mdio_alloc failed\n"); - return -ENOMEM; - } - bus->read = smi_reg_read; - bus->write = smi_reg_write; - strcpy(bus->name, dev->name); - - ret = mdio_register(bus); - if (ret) { - printf("mdio_register failed\n"); - free(bus); - return -ENOMEM; - } - - phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid); - if (!phydev) - return -ENODEV; - - return 0; -} -#endif +#endif /* CONFIG_PHYLIB */ static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe) { @@ -825,85 +695,6 @@ error1: return -ENOMEM; } -#ifndef CONFIG_DM_ETH -int mvgbe_initialize(struct bd_info *bis) -{ - struct mvgbe_device *dmvgbe; - struct eth_device *dev; - int devnum; - int ret; - u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; - - for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { - /*skip if port is configured not to use */ - if (used_ports[devnum] == 0) - continue; - - dmvgbe = malloc(sizeof(struct mvgbe_device)); - if (!dmvgbe) - return -ENOMEM; - - memset(dmvgbe, 0, sizeof(struct mvgbe_device)); - ret = mvgbe_alloc_buffers(dmvgbe); - if (ret) { - printf("Err.. %s Failed to allocate memory\n", - __func__); - free(dmvgbe); - return ret; - } - - dev = &dmvgbe->dev; - - /* must be less than sizeof(dev->name) */ - sprintf(dev->name, "egiga%d", devnum); - - switch (devnum) { - case 0: - dmvgbe->regs = (void *)MVGBE0_BASE; - break; -#if defined(MVGBE1_BASE) - case 1: - dmvgbe->regs = (void *)MVGBE1_BASE; - break; -#endif - default: /* this should never happen */ - printf("Err..(%s) Invalid device number %d\n", - __func__, devnum); - return -1; - } - - dev->init = (void *)mvgbe_init; - dev->halt = (void *)mvgbe_halt; - dev->send = (void *)mvgbe_send; - dev->recv = (void *)mvgbe_recv; - dev->write_hwaddr = (void *)mvgbe_write_hwaddr; - - eth_register(dev); - -#if defined(CONFIG_PHYLIB) - mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); -#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = smi_reg_read; - mdiodev->write = smi_reg_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; - /* Set phy address of the port */ - miiphy_write(dev->name, MV_PHY_ADR_REQUEST, - MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); -#endif - } - return 0; -} -#endif - -#ifdef CONFIG_DM_ETH static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe) { return dmvgbe->phyaddr > PHY_MAX_ADDR; @@ -1046,4 +837,3 @@ U_BOOT_DRIVER(mvgbe) = { .priv_auto = sizeof(struct mvgbe_device), .plat_auto = sizeof(struct eth_pdata), }; -#endif /* CONFIG_DM_ETH */ diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h index 44541c0a85..e3f5ac0639 100644 --- a/drivers/net/mvgbe.h +++ b/drivers/net/mvgbe.h @@ -30,9 +30,6 @@ #define RXUQ 0 /* Used Rx queue */ #define TXUQ 0 /* Used Rx queue */ -#ifndef CONFIG_DM_ETH -#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) -#endif #define MVGBE_REG_WR(adr, val) writel(val, &adr) #define MVGBE_REG_RD(adr) readl(&adr) #define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) @@ -481,9 +478,6 @@ struct mvgbe_txdesc { /* port device data struct */ struct mvgbe_device { -#ifndef CONFIG_DM_ETH - struct eth_device dev; -#endif struct mvgbe_registers *regs; struct mvgbe_txdesc *p_txdesc; struct mvgbe_rxdesc *p_rxdesc; @@ -491,7 +485,6 @@ struct mvgbe_device { u8 *p_rxbuf; u8 *p_aligned_txbuf; -#ifdef CONFIG_DM_ETH phy_interface_t phy_interface; unsigned int link; unsigned int duplex; @@ -501,7 +494,6 @@ struct mvgbe_device { int phyaddr; struct phy_device *phydev; struct mii_dev *bus; -#endif }; #endif /* __MVGBE_H__ */ From fa9ea7607f09018fbe8c922609eacd43096e2f66 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:18 -0500 Subject: [PATCH 094/424] net: netconsole: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/netconsole.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index cec96c5715..1e52917ff2 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -172,11 +172,7 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port, static void nc_send_packet(const char *buf, int len) { -#ifdef CONFIG_DM_ETH struct udevice *eth; -#else - struct eth_device *eth; -#endif int inited = 0; uchar *pkt; uchar *ether; @@ -298,11 +294,7 @@ static int nc_stdio_getc(struct stdio_dev *dev) static int nc_stdio_tstc(struct stdio_dev *dev) { -#ifdef CONFIG_DM_ETH struct udevice *eth; -#else - struct eth_device *eth; -#endif if (input_recursion) return 0; From 32dc6772762dc7bb3f112822729d2369b98aa842 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:19 -0500 Subject: [PATCH 095/424] net: pcnet: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/pcnet.c | 136 -------------------------------------------- 1 file changed, 136 deletions(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 59ef104334..a1f3c2bd29 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -83,13 +83,8 @@ struct pcnet_priv { /* Receive Buffer space */ unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; struct pcnet_uncached_priv *uc; -#ifdef CONFIG_DM_ETH struct udevice *dev; const char *name; -#else - pci_dev_t dev; - char *name; -#endif void __iomem *iobase; u8 *enetaddr; u16 status; @@ -142,11 +137,7 @@ static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr) { void *virt_addr = addr; -#ifdef CONFIG_DM_ETH return dm_pci_virt_to_mem(lp->dev, virt_addr); -#else - return pci_virt_to_mem(lp->dev, virt_addr); -#endif } static struct pci_device_id supported[] = { @@ -457,132 +448,6 @@ static void pcnet_halt_common(struct pcnet_priv *lp) printf("%s: TIMEOUT: controller reset failed\n", lp->name); } -#ifndef CONFIG_DM_ETH -static int pcnet_init(struct eth_device *dev, struct bd_info *bis) -{ - struct pcnet_priv *lp = dev->priv; - - return pcnet_init_common(lp); -} - -static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) -{ - struct pcnet_priv *lp = dev->priv; - - return pcnet_send_common(lp, packet, pkt_len); -} - -static int pcnet_recv(struct eth_device *dev) -{ - struct pcnet_priv *lp = dev->priv; - uchar *packet; - int ret; - - ret = pcnet_recv_common(lp, &packet); - if (ret > 0) - net_process_received_packet(packet, ret); - if (ret) - pcnet_free_pkt_common(lp, ret); - - return ret; -} - -static void pcnet_halt(struct eth_device *dev) -{ - struct pcnet_priv *lp = dev->priv; - - pcnet_halt_common(lp); -} - -int pcnet_initialize(struct bd_info *bis) -{ - pci_dev_t devbusfn; - struct eth_device *dev; - struct pcnet_priv *lp; - u16 command, status; - int dev_nr = 0; - u32 bar; - - PCNET_DEBUG1("\n%s...\n", __func__); - - for (dev_nr = 0; ; dev_nr++) { - /* - * Find the PCnet PCI device(s). - */ - devbusfn = pci_find_devices(supported, dev_nr); - if (devbusfn < 0) - break; - - /* - * Allocate and pre-fill the device structure. - */ - dev = calloc(1, sizeof(*dev)); - if (!dev) { - printf("pcnet: Can not allocate memory\n"); - break; - } - - /* - * We only maintain one structure because the drivers will - * never be used concurrently. In 32bit mode the RX and TX - * ring entries must be aligned on 16-byte boundaries. - */ - lp = malloc_cache_aligned(sizeof(*lp)); - lp->uc = map_physmem((phys_addr_t)&lp->ucp, - sizeof(lp->ucp), MAP_NOCACHE); - lp->dev = devbusfn; - flush_dcache_range((unsigned long)lp, - (unsigned long)lp + sizeof(*lp)); - dev->priv = lp; - sprintf(dev->name, "pcnet#%d", dev_nr); - lp->name = dev->name; - lp->enetaddr = dev->enetaddr; - - /* - * Setup the PCI device. - */ - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar); - lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf); - - PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ", - lp->name, devbusfn, lp->iobase); - - command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config_word(devbusfn, PCI_COMMAND, command); - pci_read_config_word(devbusfn, PCI_COMMAND, &status); - if ((status & command) != command) { - printf("%s: Couldn't enable IO access or Bus Mastering\n", - lp->name); - free(dev); - continue; - } - - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); - - /* - * Probe the PCnet chip. - */ - if (pcnet_probe_common(lp) < 0) { - free(dev); - continue; - } - - /* - * Setup device structure and register the driver. - */ - dev->init = pcnet_init; - dev->halt = pcnet_halt; - dev->send = pcnet_send; - dev->recv = pcnet_recv; - - eth_register(dev); - } - - udelay(10 * 1000); - - return dev_nr; -} -#else /* DM_ETH */ static int pcnet_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -695,4 +560,3 @@ U_BOOT_DRIVER(eth_pcnet) = { }; U_BOOT_PCI_DEVICE(eth_pcnet, supported); -#endif From 36af92ba85ad45dfb07f1d17e8b7d6945c1ac0b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:20 -0500 Subject: [PATCH 096/424] net: phy: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/phy/aquantia.c | 2 -- drivers/net/phy/atheros.c | 2 -- drivers/net/phy/dp83867.c | 14 ----------- drivers/net/phy/dp83869.c | 14 ----------- drivers/net/phy/marvell.c | 7 ------ drivers/net/phy/micrel_ksz90x1.c | 18 -------------- drivers/net/phy/phy.c | 13 ---------- include/phy.h | 41 -------------------------------- 8 files changed, 111 deletions(-) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 79fbc11536..8eb6024829 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -338,7 +338,6 @@ static int aquantia_set_proto(struct phy_device *phydev, static int aquantia_dts_config(struct phy_device *phydev) { -#ifdef CONFIG_DM_ETH ofnode node = phydev->node; u32 prop; u16 reg; @@ -374,7 +373,6 @@ static int aquantia_dts_config(struct phy_device *phydev) (u16)(prop << 1)); } -#endif return 0; } diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index fa1fe08518..c6f9f91645 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -191,7 +191,6 @@ static int ar803x_regs_config(struct phy_device *phydev) static int ar803x_of_init(struct phy_device *phydev) { -#if defined(CONFIG_DM_ETH) struct ar803x_priv *priv; ofnode node, vddio_reg_node; u32 strength, freq, min_uV, max_uV; @@ -306,7 +305,6 @@ static int ar803x_of_init(struct phy_device *phydev) debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__, priv->flags, priv->clk_25m_reg, priv->clk_25m_mask); -#endif return 0; } diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 3d862636b6..a45152bddc 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -144,7 +144,6 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev) return 0; } -#if defined(CONFIG_DM_ETH) /** * dp83867_data_init - Convenience function for setting PHY specific data * @@ -249,19 +248,6 @@ static int dp83867_of_init(struct phy_device *phydev) return 0; } -#else -static int dp83867_of_init(struct phy_device *phydev) -{ - struct dp83867_private *dp83867 = phydev->priv; - - dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS; - dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS; - dp83867->fifo_depth = DEFAULT_FIFO_DEPTH; - dp83867->io_impedance = -EINVAL; - - return 0; -} -#endif static int dp83867_config(struct phy_device *phydev) { diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index c9461185cf..23dbf42b68 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -157,7 +157,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev) return 0; } -#ifdef CONFIG_DM_ETH static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250, 3500, 3750, 4000}; @@ -269,19 +268,6 @@ static int dp83869_of_init(struct phy_device *phydev) return 0; } -#else -static int dp83869_of_init(struct phy_device *phydev) -{ - struct dp83869_private *dp83869 = phydev->priv; - - dp83869->rx_int_delay = DP83869_RGMIIDCTL_2_25_NS; - dp83869->tx_int_delay = DP83869_RGMIIDCTL_2_75_NS; - dp83869->fifo_depth = DEFAULT_FIFO_DEPTH; - dp83869->io_impedance = -EINVAL; - - return 0; -} -#endif /* CONFIG_OF_MDIO */ static int dp83869_configure_rgmii(struct phy_device *phydev, struct dp83869_private *dp83869) diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 212a861596..1a25775eee 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -104,7 +104,6 @@ #define MIIM_88E151x_MODE_SGMII 1 #define MIIM_88E151x_RESET_OFFS 15 -#if IS_ENABLED(CONFIG_DM_ETH) static int marvell_read_page(struct phy_device *phydev) { return phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); @@ -179,12 +178,6 @@ static int marvell_of_reg_init(struct phy_device *phydev) err: return marvell_write_page(phydev, saved_page); } -#else -static int marvell_of_reg_init(struct phy_device *phydev) -{ - return 0; -} -#endif /* CONFIG_DM_ETH */ static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, int devaddr, int regnum) diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index e5f578201f..79ebdb5e82 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -68,7 +68,6 @@ static int ksz90xx_startup(struct phy_device *phydev) } /* Common OF config bits for KSZ9021 and KSZ9031 */ -#ifdef CONFIG_DM_ETH struct ksz90x1_reg_field { const char *name; const u8 size; /* Size of the bitfield, in bits */ @@ -211,23 +210,6 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev) return ret; } -#else /* !CONFIG_DM_ETH */ -static int ksz9021_of_config(struct phy_device *phydev) -{ - return 0; -} - -static int ksz9031_of_config(struct phy_device *phydev) -{ - return 0; -} - -static int ksz9031_center_flp_timing(struct phy_device *phydev) -{ - return 0; -} -#endif - /* * KSZ9021 */ diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 92143cf236..80230b907c 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -689,9 +689,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, dev->link = 0; dev->interface = PHY_INTERFACE_MODE_NA; -#ifdef CONFIG_DM_ETH dev->node = ofnode_null(); -#endif dev->autoneg = AUTONEG_ENABLE; @@ -922,13 +920,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask) return get_phy_device_by_mask(bus, phy_mask); } -#ifdef CONFIG_DM_ETH void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, phy_interface_t interface) -#else -void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev, - phy_interface_t interface) -#endif { /* Soft Reset the PHY */ phy_reset(phydev); @@ -1011,15 +1004,9 @@ static struct phy_device *phy_connect_fixed(struct mii_dev *bus, } #endif -#ifdef CONFIG_DM_ETH struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct udevice *dev, phy_interface_t interface) -#else -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface) -#endif { struct phy_device *phydev = NULL; uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff; diff --git a/include/phy.h b/include/phy.h index ff69536fca..87aa86c2e7 100644 --- a/include/phy.h +++ b/include/phy.h @@ -138,12 +138,8 @@ struct phy_device { struct phy_driver *drv; void *priv; -#ifdef CONFIG_DM_ETH struct udevice *dev; ofnode node; -#else - struct eth_device *dev; -#endif /* forced speed & duplex (no autoneg) * partner speed & duplex & pause (autoneg) @@ -233,8 +229,6 @@ static inline struct phy_device *fixed_phy_create(ofnode node) #endif -#ifdef CONFIG_DM_ETH - /** * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices * @phydev: PHY device @@ -293,41 +287,6 @@ static inline ofnode phy_get_ofnode(struct phy_device *phydev) else return dev_ofnode(phydev->dev); } -#else - -/** - * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices - * @phydev: PHY device - * @dev: Ethernet device - * @interface: type of MAC-PHY interface - */ -void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev, - phy_interface_t interface); - -/** - * phy_connect() - Creates a PHY device for the Ethernet interface - * Creates a PHY device for the PHY at the given address, if one doesn't exist - * already, and associates it with the Ethernet device. - * The function may be called with addr <= 0, in this case addr value is ignored - * and the bus is scanned to detect a PHY. Scanning should only be used if only - * one PHY is expected to be present on the MDIO bus, otherwise it is undefined - * which PHY is returned. - * - * @bus: MII/MDIO bus that hosts the PHY - * @addr: PHY address on MDIO bus - * @dev: Ethernet device to associate to the PHY - * @interface: type of MAC-PHY interface - * @return: pointer to phy_device if a PHY is found, or NULL otherwise - */ -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface); - -static inline ofnode phy_get_ofnode(struct phy_device *phydev) -{ - return ofnode_null(); -} -#endif int phy_read(struct phy_device *phydev, int devad, int regnum); int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val); From f6fa0715ce6e6afc70175037022cf3d1ccf9adc8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:21 -0500 Subject: [PATCH 097/424] net: rtl8139: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/rtl8139.c | 112 ------------------------------------------ 1 file changed, 112 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index feeea930fb..106bc1c7ae 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -97,13 +97,8 @@ #define DEBUG_TX 0 /* set to 1 to enable debug code */ #define DEBUG_RX 0 /* set to 1 to enable debug code */ -#ifdef CONFIG_DM_ETH #define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a)) #define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a)) -#else -#define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a)) -#define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a)) -#endif /* Symbolic offsets to registers. */ /* Ethernet hardware address. */ @@ -198,12 +193,7 @@ #define RTL_STS_RXSTATUSOK BIT(0) struct rtl8139_priv { -#ifndef CONFIG_DM_ETH - struct eth_device dev; - pci_dev_t devno; -#else struct udevice *devno; -#endif unsigned int rxstatus; unsigned int cur_rx; unsigned int cur_tx; @@ -557,107 +547,6 @@ static struct pci_device_id supported[] = { { } }; -#ifndef CONFIG_DM_ETH -static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, - int join) -{ - return 0; -} - -static int rtl8139_init(struct eth_device *dev, struct bd_info *bis) -{ - struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev); - - return rtl8139_init_common(priv); -} - -static void rtl8139_stop(struct eth_device *dev) -{ - struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev); - - return rtl8139_stop_common(priv); -} - -static int rtl8139_send(struct eth_device *dev, void *packet, int length) -{ - struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev); - - return rtl8139_send_common(priv, packet, length); -} - -static int rtl8139_recv(struct eth_device *dev) -{ - struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev); - unsigned char rxdata[RX_BUF_LEN]; - uchar *packet; - int ret; - - ret = rtl8139_recv_common(priv, rxdata, &packet); - if (ret) { - net_process_received_packet(packet, ret); - rtl8139_free_pkt_common(priv, ret); - } - - return ret; -} - -int rtl8139_initialize(struct bd_info *bis) -{ - struct rtl8139_priv *priv; - struct eth_device *dev; - int card_number = 0; - pci_dev_t devno; - int idx = 0; - u32 iobase; - - while (1) { - /* Find RTL8139 */ - devno = pci_find_devices(supported, idx++); - if (devno < 0) - break; - - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); - iobase &= ~0xf; - - debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); - - priv = calloc(1, sizeof(*priv)); - if (!priv) { - printf("Can not allocate memory of rtl8139\n"); - break; - } - - priv->devno = devno; - priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase); - - dev = &priv->dev; - - rtl8139_name(dev->name, card_number); - - dev->iobase = priv->ioaddr; /* Non-DM compatibility */ - dev->init = rtl8139_init; - dev->halt = rtl8139_stop; - dev->send = rtl8139_send; - dev->recv = rtl8139_recv; - dev->mcast = rtl8139_bcast_addr; - - rtl8139_get_hwaddr(priv); - - /* Non-DM compatibility */ - memcpy(priv->dev.enetaddr, priv->enetaddr, 6); - - eth_register(dev); - - card_number++; - - pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20); - - udelay(10 * 1000); - } - - return card_number; -} -#else /* DM_ETH */ static int rtl8139_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -776,4 +665,3 @@ U_BOOT_DRIVER(eth_rtl8139) = { }; U_BOOT_PCI_DEVICE(eth_rtl8139, supported); -#endif From f1ee1e1ef199fe4aaaf5423885d4fa7ef79c9147 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:22 -0500 Subject: [PATCH 098/424] net: rtl8169: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/rtl8169.c | 166 ------------------------------------------ 1 file changed, 166 deletions(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index da2cfb7f55..c9c07a5a8f 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -47,9 +47,6 @@ #include #include #include -#ifndef CONFIG_DM_ETH -#include -#endif #include #include #include @@ -514,13 +511,8 @@ static void rtl_flush_buffer(void *buf, size_t size) /************************************************************************** RECV - Receive a frame ***************************************************************************/ -#ifdef CONFIG_DM_ETH static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase, uchar **packetp) -#else -static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, - uchar **packetp) -#endif { /* return true if there's an ethernet packet ready to read */ /* nic->packet should contain data on return */ @@ -551,22 +543,12 @@ static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, else tpc->RxDescArray[cur_rx].status = cpu_to_le32(OWNbit + RX_BUF_SIZE); -#ifdef CONFIG_DM_ETH tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long) tpc->RxBufferRing[cur_rx])); -#else - tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( - pci_mem_to_phys(dev, (pci_addr_t)(unsigned long) - tpc->RxBufferRing[cur_rx])); -#endif rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); -#ifdef CONFIG_DM_ETH *packetp = rxdata; -#else - net_process_received_packet(rxdata, length); -#endif } else { puts("Error Rx"); length = -EIO; @@ -584,32 +566,19 @@ static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase, return (0); /* initially as this is called to flush the input */ } -#ifdef CONFIG_DM_ETH int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) { struct rtl8169_private *priv = dev_get_priv(dev); return rtl_recv_common(dev, priv->iobase, packetp); } -#else -static int rtl_recv(struct eth_device *dev) -{ - return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv, - dev->iobase, NULL); -} -#endif /* nCONFIG_DM_ETH */ #define HZ 1000 /************************************************************************** SEND - Transmit a frame ***************************************************************************/ -#ifdef CONFIG_DM_ETH static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase, void *packet, int length) -#else -static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, - void *packet, int length) -#endif { /* send the packet to destination */ @@ -637,13 +606,8 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN)); tpc->TxDescArray[entry].buf_Haddr = 0; -#ifdef CONFIG_DM_ETH tpc->TxDescArray[entry].buf_addr = cpu_to_le32( dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); -#else - tpc->TxDescArray[entry].buf_addr = cpu_to_le32( - pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb)); -#endif if (entry != (NUM_TX_DESC - 1)) { tpc->TxDescArray[entry].status = cpu_to_le32((OWNbit | FSbit | LSbit) | @@ -680,7 +644,6 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase, return ret; } -#ifdef CONFIG_DM_ETH int rtl8169_eth_send(struct udevice *dev, void *packet, int length) { struct rtl8169_private *priv = dev_get_priv(dev); @@ -688,14 +651,6 @@ int rtl8169_eth_send(struct udevice *dev, void *packet, int length) return rtl_send_common(dev, priv->iobase, packet, length); } -#else -static int rtl_send(struct eth_device *dev, void *packet, int length) -{ - return rtl_send_common((pci_dev_t)(unsigned long)dev->priv, - dev->iobase, packet, length); -} -#endif - static void rtl8169_set_rx_mode(void) { u32 mc_filter[2]; /* Multicast hash filter */ @@ -719,11 +674,7 @@ static void rtl8169_set_rx_mode(void) RTL_W32(MAR0 + 4, mc_filter[1]); } -#ifdef CONFIG_DM_ETH static void rtl8169_hw_start(struct udevice *dev) -#else -static void rtl8169_hw_start(pci_dev_t dev) -#endif { u32 i; @@ -768,21 +719,11 @@ static void rtl8169_hw_start(pci_dev_t dev) tpc->cur_rx = 0; -#ifdef CONFIG_DM_ETH RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)tpc->TxDescArray)); -#else - RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev, - (pci_addr_t)(unsigned long)tpc->TxDescArray)); -#endif RTL_W32(TxDescStartAddrHigh, (unsigned long)0); -#ifdef CONFIG_DM_ETH RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys( dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); -#else - RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( - dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); -#endif RTL_W32(RxDescStartAddrHigh, (unsigned long)0); /* RTL-8169sc/8110sc or later version */ @@ -804,11 +745,7 @@ static void rtl8169_hw_start(pci_dev_t dev) #endif } -#ifdef CONFIG_DM_ETH static void rtl8169_init_ring(struct udevice *dev) -#else -static void rtl8169_init_ring(pci_dev_t dev) -#endif { int i; @@ -836,13 +773,8 @@ static void rtl8169_init_ring(pci_dev_t dev) cpu_to_le32(OWNbit + RX_BUF_SIZE); tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; -#ifdef CONFIG_DM_ETH tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys( dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); -#else - tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( - dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); -#endif rtl_flush_rx_desc(&tpc->RxDescArray[i]); } @@ -851,13 +783,8 @@ static void rtl8169_init_ring(pci_dev_t dev) #endif } -#ifdef CONFIG_DM_ETH static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr, unsigned long dev_iobase) -#else -static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr, - unsigned long dev_iobase) -#endif { int i; @@ -887,7 +814,6 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr, #endif } -#ifdef CONFIG_DM_ETH static int rtl8169_eth_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -897,18 +823,6 @@ static int rtl8169_eth_start(struct udevice *dev) return 0; } -#else -/************************************************************************** -RESET - Finish setting up the ethernet interface -***************************************************************************/ -static int rtl_reset(struct eth_device *dev, struct bd_info *bis) -{ - rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv, - dev->enetaddr, dev->iobase); - - return 0; -} -#endif /* nCONFIG_DM_ETH */ static void rtl_halt_common(unsigned long dev_iobase) { @@ -933,24 +847,13 @@ static void rtl_halt_common(unsigned long dev_iobase) } } -#ifdef CONFIG_DM_ETH void rtl8169_eth_stop(struct udevice *dev) { struct rtl8169_private *priv = dev_get_priv(dev); rtl_halt_common(priv->iobase); } -#else -/************************************************************************** -HALT - Turn off ethernet interface -***************************************************************************/ -static void rtl_halt(struct eth_device *dev) -{ - rtl_halt_common(dev->iobase); -} -#endif -#ifdef CONFIG_DM_ETH static int rtl8169_write_hwaddr(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -965,7 +868,6 @@ static int rtl8169_write_hwaddr(struct udevice *dev) return 0; } -#endif /************************************************************************** INIT - Look for an adapter, this routine's visible to the outside @@ -1118,73 +1020,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name, return 0; } -#ifndef CONFIG_DM_ETH -int rtl8169_initialize(struct bd_info *bis) -{ - pci_dev_t devno; - int card_number = 0; - struct eth_device *dev; - u32 iobase; - int idx=0; - - while(1){ - unsigned int region; - u16 device; - int err; - - /* Find RTL8169 */ - if ((devno = pci_find_devices(supported, idx++)) < 0) - break; - - pci_read_config_word(devno, PCI_DEVICE_ID, &device); - switch (device) { - case 0x8168: - region = 2; - break; - - default: - region = 1; - break; - } - - pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); - iobase &= ~0xf; - - debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); - - dev = (struct eth_device *)malloc(sizeof *dev); - if (!dev) { - printf("Can not allocate memory of rtl8169\n"); - break; - } - - memset(dev, 0, sizeof(*dev)); - sprintf (dev->name, "RTL8169#%d", card_number); - - dev->priv = (void *)(unsigned long)devno; - dev->iobase = (int)pci_mem_to_phys(devno, iobase); - - dev->init = rtl_reset; - dev->halt = rtl_halt; - dev->send = rtl_send; - dev->recv = rtl_recv; - - err = rtl_init(dev->iobase, dev->name, dev->enetaddr); - if (err < 0) { - printf(pr_fmt("failed to initialize card: %d\n"), err); - free(dev); - continue; - } - - eth_register (dev); - - card_number++; - } - return card_number; -} -#endif - -#ifdef CONFIG_DM_ETH static int rtl8169_eth_probe(struct udevice *dev) { struct pci_child_plat *pplat = dev_get_parent_plat(dev); @@ -1253,4 +1088,3 @@ U_BOOT_DRIVER(eth_rtl8169) = { }; U_BOOT_PCI_DEVICE(eth_rtl8169, supported); -#endif From 85fdaea66cbe1f259f6931928efbb497f71c7c02 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:23 -0500 Subject: [PATCH 099/424] net: sh_eth: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/sh_eth.c | 160 ------------------------------------------- 1 file changed, 160 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 1de3ff8add..0c584a23b9 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -23,12 +23,10 @@ #include #include -#ifdef CONFIG_DM_ETH #include #include #include #include -#endif #include "sh_eth.h" @@ -526,163 +524,6 @@ static int sh_eth_start_common(struct sh_eth_dev *eth) return 0; } -#ifndef CONFIG_DM_ETH -static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth) -{ - int ret = 0; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - struct eth_device *dev = port_info->dev; - struct phy_device *phydev; - - phydev = phy_connect( - miiphy_get_dev_by_name(dev->name), - port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); - port_info->phydev = phydev; - phy_config(phydev); - - return ret; -} - -static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len) -{ - struct sh_eth_dev *eth = dev->priv; - - return sh_eth_send_common(eth, packet, len); -} - -static int sh_eth_recv_common(struct sh_eth_dev *eth) -{ - int len = 0; - struct sh_eth_info *port_info = ð->port_info[eth->port]; - uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); - - len = sh_eth_recv_start(eth); - if (len > 0) { - invalidate_cache(packet, len); - net_process_received_packet(packet, len); - sh_eth_recv_finish(eth); - } else - len = 0; - - /* Restart the receiver if disabled */ - if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) - sh_eth_write(port_info, EDRRR_R, EDRRR); - - return len; -} - -static int sh_eth_recv_legacy(struct eth_device *dev) -{ - struct sh_eth_dev *eth = dev->priv; - - return sh_eth_recv_common(eth); -} - -static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd) -{ - struct sh_eth_dev *eth = dev->priv; - int ret; - - ret = sh_eth_init_common(eth, dev->enetaddr); - if (ret) - return ret; - - ret = sh_eth_phy_config_legacy(eth); - if (ret) { - printf(SHETHER_NAME ": phy config timeout\n"); - goto err_start; - } - - ret = sh_eth_start_common(eth); - if (ret) - goto err_start; - - return 0; - -err_start: - sh_eth_tx_desc_free(eth); - sh_eth_rx_desc_free(eth); - return ret; -} - -void sh_eth_halt_legacy(struct eth_device *dev) -{ - struct sh_eth_dev *eth = dev->priv; - - sh_eth_stop(eth); -} - -int sh_eth_initialize(struct bd_info *bd) -{ - int ret = 0; - struct sh_eth_dev *eth = NULL; - struct eth_device *dev = NULL; - struct mii_dev *mdiodev; - - eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); - if (!eth) { - printf(SHETHER_NAME ": %s: malloc failed\n", __func__); - ret = -ENOMEM; - goto err; - } - - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); - if (!dev) { - printf(SHETHER_NAME ": %s: malloc failed\n", __func__); - ret = -ENOMEM; - goto err; - } - memset(dev, 0, sizeof(struct eth_device)); - memset(eth, 0, sizeof(struct sh_eth_dev)); - - eth->port = CONFIG_SH_ETHER_USE_PORT; - eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; - eth->port_info[eth->port].iobase = - (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); - - dev->priv = (void *)eth; - dev->iobase = 0; - dev->init = sh_eth_init_legacy; - dev->halt = sh_eth_halt_legacy; - dev->send = sh_eth_send_legacy; - dev->recv = sh_eth_recv_legacy; - eth->port_info[eth->port].dev = dev; - - strcpy(dev->name, SHETHER_NAME); - - /* Register Device to EtherNet subsystem */ - eth_register(dev); - - bb_miiphy_buses[0].priv = eth; - mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - ret = mdio_register(mdiodev); - if (ret < 0) - return ret; - - if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr)) - puts("Please set MAC address\n"); - - return ret; - -err: - if (dev) - free(dev); - - if (eth) - free(eth); - - printf(SHETHER_NAME ": Failed\n"); - return ret; -} - -#else /* CONFIG_DM_ETH */ - struct sh_ether_priv { struct sh_eth_dev shdev; @@ -955,7 +796,6 @@ U_BOOT_DRIVER(eth_sh_ether) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /******* for bb_miiphy *******/ static int sh_eth_bb_init(struct bb_miiphy_bus *bus) From 61af2af3f74767c6babd1ff54b21f9bdb678ea0e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:24 -0500 Subject: [PATCH 100/424] net: smc911x: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/smc911x.c | 147 ------------------------------------------ 1 file changed, 147 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 5d9a73f23d..5c5ad8b84a 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -22,9 +22,6 @@ struct chip_id { }; struct smc911x_priv { -#ifndef CONFIG_DM_ETH - struct eth_device dev; -#endif phys_addr_t iobase; const struct chip_id *chipid; unsigned char enetaddr[6]; @@ -382,149 +379,6 @@ static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data) return pktlen; } -#ifndef CONFIG_DM_ETH - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -/* wrapper for smc911x_eth_phy_read */ -static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad, - int reg) -{ - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - u16 val = 0; - int ret; - - if (!dev || !priv) - return -ENODEV; - - ret = smc911x_eth_phy_read(priv, phy, reg, &val); - if (ret < 0) - return ret; - - return val; -} - -/* wrapper for smc911x_eth_phy_write */ -static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad, - int reg, u16 val) -{ - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - - if (!dev || !priv) - return -ENODEV; - - return smc911x_eth_phy_write(priv, phy, reg, val); -} - -static int smc911x_initialize_mii(struct smc911x_priv *priv) -{ - struct mii_dev *mdiodev = mdio_alloc(); - int ret; - - if (!mdiodev) - return -ENOMEM; - - strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN); - mdiodev->read = smc911x_miiphy_read; - mdiodev->write = smc911x_miiphy_write; - - ret = mdio_register(mdiodev); - if (ret < 0) { - mdio_free(mdiodev); - return ret; - } - - return 0; -} -#else -static int smc911x_initialize_mii(struct smc911x_priv *priv) -{ - return 0; -} -#endif - -static int smc911x_init(struct eth_device *dev, struct bd_info *bd) -{ - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - - return smc911x_init_common(priv); -} - -static void smc911x_halt(struct eth_device *dev) -{ - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - - smc911x_halt_common(priv); -} - -static int smc911x_send(struct eth_device *dev, void *packet, int length) -{ - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - - return smc911x_send_common(priv, packet, length); -} - -static int smc911x_recv(struct eth_device *dev) -{ - struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev); - u32 *data = (u32 *)net_rx_packets[0]; - int ret; - - ret = smc911x_recv_common(priv, data); - if (ret) - net_process_received_packet(net_rx_packets[0], ret); - - return ret; -} - -int smc911x_initialize(u8 dev_num, phys_addr_t base_addr) -{ - struct smc911x_priv *priv; - int ret; - - priv = calloc(1, sizeof(*priv)); - if (!priv) - return -ENOMEM; - - priv->iobase = base_addr; - priv->dev.iobase = base_addr; - - priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT); - - /* Try to detect chip. Will fail if not present. */ - ret = smc911x_detect_chip(priv); - if (ret) { - ret = 0; /* Card not detected is not an error */ - goto err_detect; - } - - if (smc911x_read_mac_address(priv)) - memcpy(priv->dev.enetaddr, priv->enetaddr, 6); - - priv->dev.init = smc911x_init; - priv->dev.halt = smc911x_halt; - priv->dev.send = smc911x_send; - priv->dev.recv = smc911x_recv; - sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num); - - eth_register(&priv->dev); - - ret = smc911x_initialize_mii(priv); - if (ret) - goto err_mii; - - return 1; - -err_mii: - eth_unregister(&priv->dev); -err_detect: - free(priv); - return ret; -} - -#else /* ifdef CONFIG_DM_ETH */ - static int smc911x_start(struct udevice *dev) { struct eth_pdata *plat = dev_get_plat(dev); @@ -642,4 +496,3 @@ U_BOOT_DRIVER(smc911x) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif From 8f5c7cc96bf8a82ae498443a0ee2364cddb05696 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:25 -0500 Subject: [PATCH 101/424] net: sunxi_emac: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/sunxi_emac.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 8625e49dae..ad9e1abd16 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -164,9 +164,7 @@ struct emac_eth_dev { struct mii_dev *bus; struct phy_device *phydev; int link_printed; -#ifdef CONFIG_DM_ETH uchar rx_buf[EMAC_RX_BUFSIZE]; -#endif }; struct emac_rxhdr { From f8dc288c7f22a0b1d4e2b20ae163b956a9c89a00 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:26 -0500 Subject: [PATCH 102/424] net: cpsw: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/ti/cpsw.c | 96 ------------------------------------------- 1 file changed, 96 deletions(-) diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index 41cba7930d..a19dc38e52 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -200,11 +200,7 @@ struct cpdma_chan { ((priv)->data)->slaves; slave++) struct cpsw_priv { -#ifdef CONFIG_DM_ETH struct udevice *dev; -#else - struct eth_device *dev; -#endif struct cpsw_platform_data *data; int host_port; @@ -455,15 +451,10 @@ static inline void setbit_and_wait_for_clear32(void *addr) static void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv) { -#ifdef CONFIG_DM_ETH struct eth_pdata *pdata = dev_get_plat(priv->dev); writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); -#else - __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi); - __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo); -#endif } static int cpsw_slave_update_link(struct cpsw_slave *slave, @@ -856,21 +847,13 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) ret = phy_set_supported(phydev, slave->data->max_speed); if (ret) return ret; -#if CONFIG_IS_ENABLED(DM_ETH) dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n", slave->slave_num + 1, slave->data->max_speed); -#else - log_debug("%s: Port %u speed forced to %uMbit\n", - priv->dev->name, slave->slave_num + 1, - slave->data->max_speed); -#endif } phydev->advertising = phydev->supported; -#ifdef CONFIG_DM_ETH if (ofnode_valid(slave->data->phy_of_handle)) phydev->node = slave->data->phy_of_handle; -#endif priv->phydev = phydev; phy_config(phydev); @@ -935,84 +918,6 @@ int _cpsw_register(struct cpsw_priv *priv) return 0; } -#ifndef CONFIG_DM_ETH -static int cpsw_init(struct eth_device *dev, struct bd_info *bis) -{ - struct cpsw_priv *priv = dev->priv; - - return _cpsw_init(priv, dev->enetaddr); -} - -static void cpsw_halt(struct eth_device *dev) -{ - struct cpsw_priv *priv = dev->priv; - - return _cpsw_halt(priv); -} - -static int cpsw_send(struct eth_device *dev, void *packet, int length) -{ - struct cpsw_priv *priv = dev->priv; - - return _cpsw_send(priv, packet, length); -} - -static int cpsw_recv(struct eth_device *dev) -{ - struct cpsw_priv *priv = dev->priv; - uchar *pkt = NULL; - int len; - - len = _cpsw_recv(priv, &pkt); - - if (len > 0) { - net_process_received_packet(pkt, len); - cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE); - } - - return len; -} - -int cpsw_register(struct cpsw_platform_data *data) -{ - struct cpsw_priv *priv; - struct eth_device *dev; - int ret; - - dev = calloc(sizeof(*dev), 1); - if (!dev) - return -ENOMEM; - - priv = calloc(sizeof(*priv), 1); - if (!priv) { - free(dev); - return -ENOMEM; - } - - priv->dev = dev; - priv->data = data; - - strcpy(dev->name, "cpsw"); - dev->iobase = 0; - dev->init = cpsw_init; - dev->halt = cpsw_halt; - dev->send = cpsw_send; - dev->recv = cpsw_recv; - dev->priv = priv; - - eth_register(dev); - - ret = _cpsw_register(priv); - if (ret < 0) { - eth_unregister(dev); - free(dev); - free(priv); - return ret; - } - - return 1; -} -#else static int cpsw_eth_start(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -1380,4 +1285,3 @@ U_BOOT_DRIVER(eth_cpsw) = { .priv_auto = sizeof(struct cpsw_priv), .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC, }; -#endif /* CONFIG_DM_ETH */ From 8a9e3464e487a6837dba381b28f6532fd106ce6c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:27 -0500 Subject: [PATCH 103/424] net: keystone_net: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 1bdbd599d7..679a0450f1 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -592,10 +592,8 @@ static int ks2_eth_probe(struct udevice *dev) if (priv->has_mdio) { priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, priv->phy_if); -#ifdef CONFIG_DM_ETH - if (ofnode_valid(priv->phy_ofnode)) - priv->phydev->node = priv->phy_ofnode; -#endif + if (ofnode_valid(priv->phy_ofnode)) + priv->phydev->node = priv->phy_ofnode; phy_config(priv->phydev); } From 3aa2003b5187408da5b5f9761c90311063c4045b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:28 -0500 Subject: [PATCH 104/424] usb: eth: asix: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/usb/eth/asix.c | 255 ----------------------------------------- 1 file changed, 255 deletions(-) diff --git a/drivers/usb/eth/asix.c b/drivers/usb/eth/asix.c index 674f78e214..26dd312b7d 100644 --- a/drivers/usb/eth/asix.c +++ b/drivers/usb/eth/asix.c @@ -101,16 +101,9 @@ /* driver private */ struct asix_private { int flags; -#ifdef CONFIG_DM_ETH struct ueth_data ueth; -#endif }; -#ifndef CONFIG_DM_ETH -/* local vars */ -static int curr_eth_dev; /* index for name of next device detected */ -#endif - /* * Asix infrastructure commands */ @@ -494,253 +487,6 @@ static int asix_send_common(struct ueth_data *dev, void *packet, int length) return err; } -#ifndef CONFIG_DM_ETH -/* - * Asix callbacks - */ -static int asix_init(struct eth_device *eth, struct bd_info *bd) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - return asix_init_common(dev, eth->enetaddr); -} - -static int asix_send(struct eth_device *eth, void *packet, int length) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - return asix_send_common(dev, packet, length); -} - -static int asix_recv(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE); - unsigned char *buf_ptr; - int err; - int actual_len; - u32 packet_len; - - debug("** %s()\n", __func__); - - err = usb_bulk_msg(dev->pusb_dev, - usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), - (void *)recv_buf, - AX_RX_URB_SIZE, - &actual_len, - USB_BULK_RECV_TIMEOUT); - debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE, - actual_len, err); - if (err != 0) { - debug("Rx: failed to receive\n"); - return -1; - } - if (actual_len > AX_RX_URB_SIZE) { - debug("Rx: received too many bytes %d\n", actual_len); - return -1; - } - - buf_ptr = recv_buf; - while (actual_len > 0) { - /* - * 1st 4 bytes contain the length of the actual data as two - * complementary 16-bit words. Extract the length of the data. - */ - if (actual_len < sizeof(packet_len)) { - debug("Rx: incomplete packet length\n"); - return -1; - } - memcpy(&packet_len, buf_ptr, sizeof(packet_len)); - le32_to_cpus(&packet_len); - if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) { - debug("Rx: malformed packet length: %#x (%#x:%#x)\n", - packet_len, (~packet_len >> 16) & 0x7ff, - packet_len & 0x7ff); - return -1; - } - packet_len = packet_len & 0x7ff; - if (packet_len > actual_len - sizeof(packet_len)) { - debug("Rx: too large packet: %d\n", packet_len); - return -1; - } - - /* Notify net stack */ - net_process_received_packet(buf_ptr + sizeof(packet_len), - packet_len); - - /* Adjust for next iteration. Packets are padded to 16-bits */ - if (packet_len & 1) - packet_len++; - actual_len -= sizeof(packet_len) + packet_len; - buf_ptr += sizeof(packet_len) + packet_len; - } - - return err; -} - -static void asix_halt(struct eth_device *eth) -{ - debug("** %s()\n", __func__); -} - -static int asix_write_hwaddr(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - return asix_write_hwaddr_common(dev, eth->enetaddr); -} - -/* - * Asix probing functions - */ -void asix_eth_before_probe(void) -{ - curr_eth_dev = 0; -} - -struct asix_dongle { - unsigned short vendor; - unsigned short product; - int flags; -}; - -static const struct asix_dongle asix_dongles[] = { - { 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */ - { 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */ - { 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */ - /* Cables-to-Go USB Ethernet Adapter */ - { 0x0b95, 0x772a, FLAG_TYPE_AX88772 }, - { 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */ - { 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */ - { 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */ - { 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */ - { 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */ - /* DLink DUB-E100 H/W Ver B1 Alternate */ - { 0x2001, 0x3c05, FLAG_TYPE_AX88772 }, - /* ASIX 88772B */ - { 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC }, - { 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B }, - { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ -}; - -/* Probe to see if a new device is actually an asix device */ -int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss) -{ - struct usb_interface *iface; - struct usb_interface_descriptor *iface_desc; - int ep_in_found = 0, ep_out_found = 0; - int i; - - /* let's examine the device now */ - iface = &dev->config.if_desc[ifnum]; - iface_desc = &dev->config.if_desc[ifnum].desc; - - for (i = 0; asix_dongles[i].vendor != 0; i++) { - if (dev->descriptor.idVendor == asix_dongles[i].vendor && - dev->descriptor.idProduct == asix_dongles[i].product) - /* Found a supported dongle */ - break; - } - - if (asix_dongles[i].vendor == 0) - return 0; - - memset(ss, 0, sizeof(struct ueth_data)); - - /* At this point, we know we've got a live one */ - debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", - dev->descriptor.idVendor, dev->descriptor.idProduct); - - /* Initialize the ueth_data structure with some useful info */ - ss->ifnum = ifnum; - ss->pusb_dev = dev; - ss->subclass = iface_desc->bInterfaceSubClass; - ss->protocol = iface_desc->bInterfaceProtocol; - - /* alloc driver private */ - ss->dev_priv = calloc(1, sizeof(struct asix_private)); - if (!ss->dev_priv) - return 0; - - ((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags; - - /* - * We are expecting a minimum of 3 endpoints - in, out (bulk), and - * int. We will ignore any others. - */ - for (i = 0; i < iface_desc->bNumEndpoints; i++) { - /* is it an BULK endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { - u8 ep_addr = iface->ep_desc[i].bEndpointAddress; - if (ep_addr & USB_DIR_IN) { - if (!ep_in_found) { - ss->ep_in = ep_addr & - USB_ENDPOINT_NUMBER_MASK; - ep_in_found = 1; - } - } else { - if (!ep_out_found) { - ss->ep_out = ep_addr & - USB_ENDPOINT_NUMBER_MASK; - ep_out_found = 1; - } - } - } - - /* is it an interrupt endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { - ss->ep_int = iface->ep_desc[i].bEndpointAddress & - USB_ENDPOINT_NUMBER_MASK; - ss->irqinterval = iface->ep_desc[i].bInterval; - } - } - debug("Endpoints In %d Out %d Int %d\n", - ss->ep_in, ss->ep_out, ss->ep_int); - - /* Do some basic sanity checks, and bail if we find a problem */ - if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || - !ss->ep_in || !ss->ep_out || !ss->ep_int) { - debug("Problems with device\n"); - return 0; - } - dev->privptr = (void *)ss; - return 1; -} - -int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth) -{ - struct asix_private *priv = (struct asix_private *)ss->dev_priv; - - if (!eth) { - debug("%s: missing parameter.\n", __func__); - return 0; - } - sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); - eth->init = asix_init; - eth->send = asix_send; - eth->recv = asix_recv; - eth->halt = asix_halt; - if (!(priv->flags & FLAG_TYPE_AX88172)) - eth->write_hwaddr = asix_write_hwaddr; - eth->priv = ss; - - if (asix_basic_reset(ss)) - return 0; - - /* Get the MAC address */ - if (asix_read_mac_common(ss, priv, eth->enetaddr)) - return 0; - debug("MAC %pM\n", eth->enetaddr); - - return 1; -} -#endif - -#ifdef CONFIG_DM_ETH static int asix_eth_start(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); @@ -909,4 +655,3 @@ static const struct usb_device_id asix_eth_id_table[] = { }; U_BOOT_USB_DEVICE(asix_eth, asix_eth_id_table); -#endif From d9e81b0dd75cb6589df4746fa946f09fb531bd89 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:29 -0500 Subject: [PATCH 105/424] usb: eth: asix88179: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/usb/eth/asix88179.c | 250 ------------------------------------ 1 file changed, 250 deletions(-) diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 4742a95af9..2e737e6066 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -199,18 +199,12 @@ static const struct { {7, 0xcc, 0x4c, 0x04, 8}, }; -#ifndef CONFIG_DM_ETH -static int curr_eth_dev; /* index for name of next device detected */ -#endif - /* driver private */ struct asix_private { -#ifdef CONFIG_DM_ETH struct ueth_data ueth; unsigned pkt_cnt; uint8_t *pkt_data; uint32_t *pkt_hdr; -#endif int flags; int rx_urb_size; int maxpacketsize; @@ -505,249 +499,6 @@ static int asix_send_common(struct ueth_data *dev, return err; } -#ifndef CONFIG_DM_ETH -/* - * Asix callbacks - */ -static int asix_init(struct eth_device *eth, struct bd_info *bd) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; - - return asix_init_common(dev, dev_priv); -} - -static int asix_write_hwaddr(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - return asix_write_mac(dev, eth->enetaddr); -} - -static int asix_send(struct eth_device *eth, void *packet, int length) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; - - return asix_send_common(dev, dev_priv, packet, length); -} - -static int asix_recv(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; - - u16 frame_pos; - int err; - int actual_len; - - int pkt_cnt; - u32 rx_hdr; - u16 hdr_off; - u32 *pkt_hdr; - ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size); - - actual_len = -1; - - debug("** %s()\n", __func__); - - err = usb_bulk_msg(dev->pusb_dev, - usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), - (void *)recv_buf, - dev_priv->rx_urb_size, - &actual_len, - USB_BULK_RECV_TIMEOUT); - debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size, - actual_len, err); - - if (err != 0) { - debug("Rx: failed to receive\n"); - return -ECOMM; - } - if (actual_len > dev_priv->rx_urb_size) { - debug("Rx: received too many bytes %d\n", actual_len); - return -EMSGSIZE; - } - - - rx_hdr = *(u32 *)(recv_buf + actual_len - 4); - le32_to_cpus(&rx_hdr); - - pkt_cnt = (u16)rx_hdr; - hdr_off = (u16)(rx_hdr >> 16); - pkt_hdr = (u32 *)(recv_buf + hdr_off); - - - frame_pos = 0; - - while (pkt_cnt--) { - u16 pkt_len; - - le32_to_cpus(pkt_hdr); - pkt_len = (*pkt_hdr >> 16) & 0x1fff; - - frame_pos += 2; - - net_process_received_packet(recv_buf + frame_pos, pkt_len); - - pkt_hdr++; - frame_pos += ((pkt_len + 7) & 0xFFF8)-2; - - if (pkt_cnt == 0) - return 0; - } - return err; -} - -static void asix_halt(struct eth_device *eth) -{ - debug("** %s()\n", __func__); -} - -/* - * Asix probing functions - */ -void ax88179_eth_before_probe(void) -{ - curr_eth_dev = 0; -} - -struct asix_dongle { - unsigned short vendor; - unsigned short product; - int flags; -}; - -static const struct asix_dongle asix_dongles[] = { - { 0x0b95, 0x1790, FLAG_TYPE_AX88179 }, - { 0x0b95, 0x178a, FLAG_TYPE_AX88178a }, - { 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 }, - { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, - { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, - { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, - { 0x04b4, 0x3610, FLAG_TYPE_GX3 }, - { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ -}; - -/* Probe to see if a new device is actually an asix device */ -int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss) -{ - struct usb_interface *iface; - struct usb_interface_descriptor *iface_desc; - struct asix_private *dev_priv; - int ep_in_found = 0, ep_out_found = 0; - int i; - - /* let's examine the device now */ - iface = &dev->config.if_desc[ifnum]; - iface_desc = &dev->config.if_desc[ifnum].desc; - - for (i = 0; asix_dongles[i].vendor != 0; i++) { - if (dev->descriptor.idVendor == asix_dongles[i].vendor && - dev->descriptor.idProduct == asix_dongles[i].product) - /* Found a supported dongle */ - break; - } - - if (asix_dongles[i].vendor == 0) - return 0; - - memset(ss, 0, sizeof(struct ueth_data)); - - /* At this point, we know we've got a live one */ - debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", - dev->descriptor.idVendor, dev->descriptor.idProduct); - - /* Initialize the ueth_data structure with some useful info */ - ss->ifnum = ifnum; - ss->pusb_dev = dev; - ss->subclass = iface_desc->bInterfaceSubClass; - ss->protocol = iface_desc->bInterfaceProtocol; - - /* alloc driver private */ - ss->dev_priv = calloc(1, sizeof(struct asix_private)); - if (!ss->dev_priv) - return 0; - dev_priv = ss->dev_priv; - dev_priv->flags = asix_dongles[i].flags; - - /* - * We are expecting a minimum of 3 endpoints - in, out (bulk), and - * int. We will ignore any others. - */ - for (i = 0; i < iface_desc->bNumEndpoints; i++) { - /* is it an interrupt endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { - ss->ep_int = iface->ep_desc[i].bEndpointAddress & - USB_ENDPOINT_NUMBER_MASK; - ss->irqinterval = iface->ep_desc[i].bInterval; - continue; - } - - /* is it an BULK endpoint? */ - if (!((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)) - continue; - - u8 ep_addr = iface->ep_desc[i].bEndpointAddress; - if ((ep_addr & USB_DIR_IN) && !ep_in_found) { - ss->ep_in = ep_addr & - USB_ENDPOINT_NUMBER_MASK; - ep_in_found = 1; - } - if (!(ep_addr & USB_DIR_IN) && !ep_out_found) { - ss->ep_out = ep_addr & - USB_ENDPOINT_NUMBER_MASK; - dev_priv->maxpacketsize = - dev->epmaxpacketout[AX_ENDPOINT_OUT]; - ep_out_found = 1; - } - } - debug("Endpoints In %d Out %d Int %d\n", - ss->ep_in, ss->ep_out, ss->ep_int); - - /* Do some basic sanity checks, and bail if we find a problem */ - if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || - !ss->ep_in || !ss->ep_out || !ss->ep_int) { - debug("Problems with device\n"); - return 0; - } - dev->privptr = (void *)ss; - return 1; -} - -int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth) -{ - struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv; - - if (!eth) { - debug("%s: missing parameter.\n", __func__); - return 0; - } - sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++); - eth->init = asix_init; - eth->send = asix_send; - eth->recv = asix_recv; - eth->halt = asix_halt; - eth->write_hwaddr = asix_write_hwaddr; - eth->priv = ss; - - if (asix_basic_reset(ss, dev_priv)) - return 0; - - /* Get the MAC address */ - if (asix_read_mac(ss, eth->enetaddr)) - return 0; - debug("MAC %pM\n", eth->enetaddr); - - return 1; -} - -#else /* !CONFIG_DM_ETH */ - static int ax88179_eth_start(struct udevice *dev) { struct asix_private *priv = dev_get_priv(dev); @@ -918,4 +669,3 @@ static const struct usb_device_id ax88179_eth_id_table[] = { }; U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table); -#endif /* !CONFIG_DM_ETH */ From 05d654b564bf5210b150d0c8245cc7ebed64c905 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:30 -0500 Subject: [PATCH 106/424] usb: eth: msc7830: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/usb/eth/mcs7830.c | 276 -------------------------------------- 1 file changed, 276 deletions(-) diff --git a/drivers/usb/eth/mcs7830.c b/drivers/usb/eth/mcs7830.c index 783ab62f6b..8a256b3e34 100644 --- a/drivers/usb/eth/mcs7830.c +++ b/drivers/usb/eth/mcs7830.c @@ -86,10 +86,8 @@ struct mcs7830_regs { * @mchash: shadow for the network adapter's multicast hash registers */ struct mcs7830_private { -#ifdef CONFIG_DM_ETH uint8_t rx_buf[MCS7830_RX_URB_SIZE]; struct ueth_data ueth; -#endif uint8_t config; uint8_t mchash[8]; }; @@ -575,279 +573,6 @@ static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf) return -EIO; } -#ifndef CONFIG_DM_ETH -/* - * mcs7830_init() - network interface's init callback - * @udev: network device to initialize - * @bd: board information - * Return: zero upon success, negative upon error - * - * after initial setup during probe() and get_info(), this init() callback - * ensures that the link is up and subsequent send() and recv() calls can - * exchange ethernet frames - */ -static int mcs7830_init(struct eth_device *eth, struct bd_info *bd) -{ - struct ueth_data *dev = eth->priv; - - return mcs7830_init_common(dev->pusb_dev); -} - -/* - * mcs7830_send() - network interface's send callback - * @eth: network device to send the frame from - * @packet: ethernet frame content - * @length: ethernet frame length - * Return: zero upon success, negative upon error - * - * this routine send an ethernet frame out of the network interface - */ -static int mcs7830_send(struct eth_device *eth, void *packet, int length) -{ - struct ueth_data *dev = eth->priv; - - return mcs7830_send_common(dev, packet, length); -} - -/* - * mcs7830_recv() - network interface's recv callback - * @eth: network device to receive frames from - * Return: zero upon success, negative upon error - * - * this routine checks for available ethernet frames that the network - * interface might have received, and notifies the network stack - */ -static int mcs7830_recv(struct eth_device *eth) -{ - ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE); - struct ueth_data *ueth = eth->priv; - int len; - - len = mcs7830_recv_common(ueth, buf); - if (len >= 0) { - net_process_received_packet(buf, len); - return 0; - } - - return len; -} - -/* - * mcs7830_halt() - network interface's halt callback - * @eth: network device to cease operation of - * Return: none - * - * this routine is supposed to undo the effect of previous initialization and - * ethernet frames exchange; in this implementation it's a NOP - */ -static void mcs7830_halt(struct eth_device *eth) -{ - debug("%s()\n", __func__); -} - -/* - * mcs7830_write_mac() - write an ethernet adapter's MAC address - * @eth: network device to write to - * Return: zero upon success, negative upon error - * - * this routine takes the MAC address from the ethernet interface's data - * structure, and writes it into the ethernet adapter such that subsequent - * exchange of ethernet frames uses this address - */ -static int mcs7830_write_mac(struct eth_device *eth) -{ - struct ueth_data *ueth = eth->priv; - - return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr); -} - -/* - * mcs7830_iface_idx - index of detected network interfaces - * - * this counter keeps track of identified supported interfaces, - * to assign unique names as more interfaces are found - */ -static int mcs7830_iface_idx; - -/* - * mcs7830_eth_before_probe() - network driver's before_probe callback - * Return: none - * - * this routine initializes driver's internal data in preparation of - * subsequent probe callbacks - */ -void mcs7830_eth_before_probe(void) -{ - mcs7830_iface_idx = 0; -} - -/* - * struct mcs7830_dongle - description of a supported Moschip ethernet dongle - * @vendor: 16bit USB vendor identification - * @product: 16bit USB product identification - * - * this structure describes a supported USB ethernet dongle by means of the - * vendor and product codes found during USB enumeration; no flags are held - * here since all supported dongles have identical behaviour, and required - * fixups get determined at runtime, such that no manual configuration is - * needed - */ -struct mcs7830_dongle { - uint16_t vendor; - uint16_t product; -}; - -/* - * mcs7830_dongles - the list of supported Moschip based USB ethernet dongles - */ -static const struct mcs7830_dongle mcs7830_dongles[] = { - { 0x9710, 0x7832, }, /* Moschip 7832 */ - { 0x9710, 0x7830, }, /* Moschip 7830 */ - { 0x9710, 0x7730, }, /* Moschip 7730 */ - { 0x0df6, 0x0021, }, /* Sitecom LN 30 */ -}; - -/* - * mcs7830_eth_probe() - network driver's probe callback - * @dev: detected USB device to check - * @ifnum: detected USB interface to check - * @ss: USB ethernet data structure to fill in upon match - * Return: #1 upon match, #0 upon mismatch or error - * - * this routine checks whether the found USB device is supported by - * this ethernet driver, and upon match fills in the USB ethernet - * data structure which later is passed to the get_info callback - */ -int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss) -{ - struct usb_interface *iface; - struct usb_interface_descriptor *iface_desc; - int i; - struct mcs7830_private *priv; - int ep_in_found, ep_out_found, ep_intr_found; - - debug("%s()\n", __func__); - - /* iterate the list of supported dongles */ - iface = &dev->config.if_desc[ifnum]; - iface_desc = &iface->desc; - for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) { - if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor && - dev->descriptor.idProduct == mcs7830_dongles[i].product) - break; - } - if (i == ARRAY_SIZE(mcs7830_dongles)) - return 0; - debug("detected USB ethernet device: %04X:%04X\n", - dev->descriptor.idVendor, dev->descriptor.idProduct); - - /* fill in driver private data */ - priv = calloc(1, sizeof(*priv)); - if (!priv) - return 0; - - /* fill in the ueth_data structure, attach private data */ - memset(ss, 0, sizeof(*ss)); - ss->ifnum = ifnum; - ss->pusb_dev = dev; - ss->subclass = iface_desc->bInterfaceSubClass; - ss->protocol = iface_desc->bInterfaceProtocol; - ss->dev_priv = priv; - - /* - * a minimum of three endpoints is expected: in (bulk), - * out (bulk), and interrupt; ignore all others - */ - ep_in_found = ep_out_found = ep_intr_found = 0; - for (i = 0; i < iface_desc->bNumEndpoints; i++) { - uint8_t eptype, epaddr; - bool is_input; - - eptype = iface->ep_desc[i].bmAttributes; - eptype &= USB_ENDPOINT_XFERTYPE_MASK; - - epaddr = iface->ep_desc[i].bEndpointAddress; - is_input = epaddr & USB_DIR_IN; - epaddr &= USB_ENDPOINT_NUMBER_MASK; - - if (eptype == USB_ENDPOINT_XFER_BULK) { - if (is_input && !ep_in_found) { - ss->ep_in = epaddr; - ep_in_found++; - } - if (!is_input && !ep_out_found) { - ss->ep_out = epaddr; - ep_out_found++; - } - } - - if (eptype == USB_ENDPOINT_XFER_INT) { - if (is_input && !ep_intr_found) { - ss->ep_int = epaddr; - ss->irqinterval = iface->ep_desc[i].bInterval; - ep_intr_found++; - } - } - } - debug("endpoints: in %d, out %d, intr %d\n", - ss->ep_in, ss->ep_out, ss->ep_int); - - /* apply basic sanity checks */ - if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || - !ss->ep_in || !ss->ep_out || !ss->ep_int) { - debug("device probe incomplete\n"); - return 0; - } - - dev->privptr = ss; - return 1; -} - -/* - * mcs7830_eth_get_info() - network driver's get_info callback - * @dev: detected USB device - * @ss: USB ethernet data structure filled in at probe() - * @eth: ethernet interface data structure to fill in - * Return: #1 upon success, #0 upon error - * - * this routine registers the mandatory init(), send(), recv(), and - * halt() callbacks with the ethernet interface, can register the - * optional write_hwaddr() callback with the ethernet interface, - * and initiates configuration of the interface such that subsequent - * calls to those callbacks results in network communication - */ -int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth) -{ - debug("%s()\n", __func__); - if (!eth) { - debug("%s: missing parameter.\n", __func__); - return 0; - } - - snprintf(eth->name, sizeof(eth->name), "%s%d", - MCS7830_BASE_NAME, mcs7830_iface_idx++); - eth->init = mcs7830_init; - eth->send = mcs7830_send; - eth->recv = mcs7830_recv; - eth->halt = mcs7830_halt; - eth->write_hwaddr = mcs7830_write_mac; - eth->priv = ss; - - if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv)) - return 0; - - if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr)) - return 0; - debug("MAC %pM\n", eth->enetaddr); - - return 1; -} -#endif - - -#ifdef CONFIG_DM_ETH static int mcs7830_eth_start(struct udevice *dev) { struct usb_device *udev = dev_get_parent_priv(dev); @@ -942,4 +667,3 @@ static const struct usb_device_id mcs7830_eth_id_table[] = { }; U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table); -#endif From 82cdcd5792f33ece8da4d1931ea8e2be2d85deff Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:31 -0500 Subject: [PATCH 107/424] usb: eth: r8152: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/usb/eth/r8152.c | 275 ---------------------------------------- drivers/usb/eth/r8152.h | 2 - 2 files changed, 277 deletions(-) diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 1aaa5a79b3..3c866f4f1e 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -18,43 +18,6 @@ #include "usb_ether.h" #include "r8152.h" -#ifndef CONFIG_DM_ETH -/* local vars */ -static int curr_eth_dev; /* index for name of next device detected */ - -struct r8152_dongle { - unsigned short vendor; - unsigned short product; -}; - -static const struct r8152_dongle r8152_dongles[] = { - /* Realtek */ - { 0x0bda, 0x8050 }, - { 0x0bda, 0x8152 }, - { 0x0bda, 0x8153 }, - - /* Samsung */ - { 0x04e8, 0xa101 }, - - /* Lenovo */ - { 0x17ef, 0x304f }, - { 0x17ef, 0x3052 }, - { 0x17ef, 0x3054 }, - { 0x17ef, 0x3057 }, - { 0x17ef, 0x7205 }, - { 0x17ef, 0x720a }, - { 0x17ef, 0x720b }, - { 0x17ef, 0x720c }, - - /* TP-LINK */ - { 0x2357, 0x0601 }, - { 0x2357, 0x0602 }, - - /* Nvidia */ - { 0x0955, 0x09ff }, -}; -#endif - struct r8152_version { unsigned short tcr; unsigned short version; @@ -1479,243 +1442,6 @@ static int r8152_send_common(struct ueth_data *ueth, void *packet, int length) return err; } -#ifndef CONFIG_DM_ETH -static int r8152_init(struct eth_device *eth, struct bd_info *bd) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct r8152 *tp = (struct r8152 *)dev->dev_priv; - - return r8152_init_common(tp); -} - -static int r8152_send(struct eth_device *eth, void *packet, int length) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - return r8152_send_common(dev, packet, length); -} - -static int r8152_recv(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ); - unsigned char *pkt_ptr; - int err; - int actual_len; - u16 packet_len; - - u32 bytes_process = 0; - struct rx_desc *rx_desc; - - debug("** %s()\n", __func__); - - err = usb_bulk_msg(dev->pusb_dev, - usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), - (void *)recv_buf, - RTL8152_AGG_BUF_SZ, - &actual_len, - USB_BULK_RECV_TIMEOUT); - debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ, - actual_len, err); - if (err != 0) { - debug("Rx: failed to receive\n"); - return -1; - } - if (actual_len > RTL8152_AGG_BUF_SZ) { - debug("Rx: received too many bytes %d\n", actual_len); - return -1; - } - - while (bytes_process < actual_len) { - rx_desc = (struct rx_desc *)(recv_buf + bytes_process); - pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process; - - packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; - packet_len -= CRC_SIZE; - - net_process_received_packet(pkt_ptr, packet_len); - - bytes_process += - (packet_len + sizeof(struct rx_desc) + CRC_SIZE); - - if (bytes_process % 8) - bytes_process = bytes_process + 8 - (bytes_process % 8); - } - - return 0; -} - -static void r8152_halt(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct r8152 *tp = (struct r8152 *)dev->dev_priv; - - debug("** %s()\n", __func__); - - tp->rtl_ops.disable(tp); -} - -static int r8152_write_hwaddr(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct r8152 *tp = (struct r8152 *)dev->dev_priv; - - unsigned char enetaddr[8] = {0}; - - memcpy(enetaddr, eth->enetaddr, ETH_ALEN); - - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); - pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); - - debug("MAC %pM\n", eth->enetaddr); - return 0; -} - -void r8152_eth_before_probe(void) -{ - curr_eth_dev = 0; -} - -/* Probe to see if a new device is actually an realtek device */ -int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss) -{ - struct usb_interface *iface; - struct usb_interface_descriptor *iface_desc; - int ep_in_found = 0, ep_out_found = 0; - struct r8152 *tp; - int i; - - /* let's examine the device now */ - iface = &dev->config.if_desc[ifnum]; - iface_desc = &dev->config.if_desc[ifnum].desc; - - for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) { - if (dev->descriptor.idVendor == r8152_dongles[i].vendor && - dev->descriptor.idProduct == r8152_dongles[i].product) - /* Found a supported dongle */ - break; - } - - if (i == ARRAY_SIZE(r8152_dongles)) - return 0; - - memset(ss, 0, sizeof(struct ueth_data)); - - /* At this point, we know we've got a live one */ - debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n", - dev->descriptor.idVendor, dev->descriptor.idProduct); - - /* Initialize the ueth_data structure with some useful info */ - ss->ifnum = ifnum; - ss->pusb_dev = dev; - ss->subclass = iface_desc->bInterfaceSubClass; - ss->protocol = iface_desc->bInterfaceProtocol; - - /* alloc driver private */ - ss->dev_priv = calloc(1, sizeof(struct r8152)); - - if (!ss->dev_priv) - return 0; - - /* - * We are expecting a minimum of 3 endpoints - in, out (bulk), and - * int. We will ignore any others. - */ - for (i = 0; i < iface_desc->bNumEndpoints; i++) { - /* is it an BULK endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { - u8 ep_addr = iface->ep_desc[i].bEndpointAddress; - - if (ep_addr & USB_DIR_IN) { - if (!ep_in_found) { - ss->ep_in = ep_addr & - USB_ENDPOINT_NUMBER_MASK; - ep_in_found = 1; - } - } else { - if (!ep_out_found) { - ss->ep_out = ep_addr & - USB_ENDPOINT_NUMBER_MASK; - ep_out_found = 1; - } - } - } - - /* is it an interrupt endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { - ss->ep_int = iface->ep_desc[i].bEndpointAddress & - USB_ENDPOINT_NUMBER_MASK; - ss->irqinterval = iface->ep_desc[i].bInterval; - } - } - - debug("Endpoints In %d Out %d Int %d\n", - ss->ep_in, ss->ep_out, ss->ep_int); - - /* Do some basic sanity checks, and bail if we find a problem */ - if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || - !ss->ep_in || !ss->ep_out || !ss->ep_int) { - debug("Problems with device\n"); - goto error; - } - - dev->privptr = (void *)ss; - - tp = ss->dev_priv; - tp->udev = dev; - tp->intf = iface; - - r8152b_get_version(tp); - - if (rtl_ops_init(tp)) - goto error; - - tp->rtl_ops.init(tp); - tp->rtl_ops.up(tp); - - rtl8152_set_speed(tp, AUTONEG_ENABLE, - tp->supports_gmii ? SPEED_1000 : SPEED_100, - DUPLEX_FULL); - - return 1; - -error: - cfree(ss->dev_priv); - ss->dev_priv = 0; - return 0; -} - -int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth) -{ - if (!eth) { - debug("%s: missing parameter.\n", __func__); - return 0; - } - - sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++); - eth->init = r8152_init; - eth->send = r8152_send; - eth->recv = r8152_recv; - eth->halt = r8152_halt; - eth->write_hwaddr = r8152_write_hwaddr; - eth->priv = ss; - - /* Get the MAC address */ - if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0) - return 0; - - debug("MAC %pM\n", eth->enetaddr); - return 1; -} -#endif /* !CONFIG_DM_ETH */ - -#ifdef CONFIG_DM_ETH static int r8152_eth_start(struct udevice *dev) { struct r8152 *tp = dev_get_priv(dev); @@ -1895,4 +1621,3 @@ static const struct usb_device_id r8152_eth_id_table[] = { }; U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); -#endif /* CONFIG_DM_ETH */ diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h index 45172c055f..7b128b1934 100644 --- a/drivers/usb/eth/r8152.h +++ b/drivers/usb/eth/r8152.h @@ -642,9 +642,7 @@ struct r8152 { u8 version; -#ifdef CONFIG_DM_ETH struct ueth_data ueth; -#endif }; int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, From 0a9cbd4f3c90b8ea7230b8dd0885797c48053a5f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:32 -0500 Subject: [PATCH 108/424] usb: eth: smsc95xx: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/usb/eth/smsc95xx.c | 234 ------------------------------------- 1 file changed, 234 deletions(-) diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 283c52c16a..de6586e626 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -143,16 +143,9 @@ #define TURBO_MODE -#ifndef CONFIG_DM_ETH -/* local vars */ -static int curr_eth_dev; /* index for name of next device detected */ -#endif - /* driver private */ struct smsc95xx_private { -#ifdef CONFIG_DM_ETH struct ueth_data ueth; -#endif size_t rx_urb_size; /* maximum USB URB size */ u32 mac_cr; /* MAC control register value */ int have_hwaddr; /* 1 if we have a hardware MAC address */ @@ -521,11 +514,6 @@ static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev, debug("timeout waiting for PHY Reset\n"); return -ETIMEDOUT; } -#ifndef CONFIG_DM_ETH - if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) == - 0) - priv->have_hwaddr = 1; -#endif if (!priv->have_hwaddr) { puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); return -EADDRNOTAVAIL; @@ -712,227 +700,6 @@ static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length) return err; } -#ifndef CONFIG_DM_ETH -/* - * Smsc95xx callbacks - */ -static int smsc95xx_init(struct eth_device *eth, struct bd_info *bd) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct usb_device *udev = dev->pusb_dev; - struct smsc95xx_private *priv = - (struct smsc95xx_private *)dev->dev_priv; - - return smsc95xx_init_common(udev, dev, priv, eth->enetaddr); -} - -static int smsc95xx_send(struct eth_device *eth, void *packet, int length) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - - return smsc95xx_send_common(dev, packet, length); -} - -static int smsc95xx_recv(struct eth_device *eth) -{ - struct ueth_data *dev = (struct ueth_data *)eth->priv; - DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE); - unsigned char *buf_ptr; - int err; - int actual_len; - u32 packet_len; - int cur_buf_align; - - debug("** %s()\n", __func__); - err = usb_bulk_msg(dev->pusb_dev, - usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in), - (void *)recv_buf, RX_URB_SIZE, &actual_len, - USB_BULK_RECV_TIMEOUT); - debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE, - actual_len, err); - if (err != 0) { - debug("Rx: failed to receive\n"); - return -err; - } - if (actual_len > RX_URB_SIZE) { - debug("Rx: received too many bytes %d\n", actual_len); - return -ENOSPC; - } - - buf_ptr = recv_buf; - while (actual_len > 0) { - /* - * 1st 4 bytes contain the length of the actual data plus error - * info. Extract data length. - */ - if (actual_len < sizeof(packet_len)) { - debug("Rx: incomplete packet length\n"); - return -EIO; - } - memcpy(&packet_len, buf_ptr, sizeof(packet_len)); - le32_to_cpus(&packet_len); - if (packet_len & RX_STS_ES_) { - debug("Rx: Error header=%#x", packet_len); - return -EIO; - } - packet_len = ((packet_len & RX_STS_FL_) >> 16); - - if (packet_len > actual_len - sizeof(packet_len)) { - debug("Rx: too large packet: %d\n", packet_len); - return -EIO; - } - - /* Notify net stack */ - net_process_received_packet(buf_ptr + sizeof(packet_len), - packet_len - 4); - - /* Adjust for next iteration */ - actual_len -= sizeof(packet_len) + packet_len; - buf_ptr += sizeof(packet_len) + packet_len; - cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf; - - if (cur_buf_align & 0x03) { - int align = 4 - (cur_buf_align & 0x03); - - actual_len -= align; - buf_ptr += align; - } - } - return err; -} - -static void smsc95xx_halt(struct eth_device *eth) -{ - debug("** %s()\n", __func__); -} - -static int smsc95xx_write_hwaddr(struct eth_device *eth) -{ - struct ueth_data *dev = eth->priv; - struct usb_device *udev = dev->pusb_dev; - struct smsc95xx_private *priv = dev->dev_priv; - - return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr); -} - -/* - * SMSC probing functions - */ -void smsc95xx_eth_before_probe(void) -{ - curr_eth_dev = 0; -} - -struct smsc95xx_dongle { - unsigned short vendor; - unsigned short product; -}; - -static const struct smsc95xx_dongle smsc95xx_dongles[] = { - { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */ - { 0x0424, 0x9500 }, /* LAN9500 Ethernet */ - { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */ - { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */ - { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */ - { 0x0000, 0x0000 } /* END - Do not remove */ -}; - -/* Probe to see if a new device is actually an SMSC device */ -int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss) -{ - struct usb_interface *iface; - struct usb_interface_descriptor *iface_desc; - int i; - - /* let's examine the device now */ - iface = &dev->config.if_desc[ifnum]; - iface_desc = &dev->config.if_desc[ifnum].desc; - - for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) { - if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor && - dev->descriptor.idProduct == smsc95xx_dongles[i].product) - /* Found a supported dongle */ - break; - } - if (smsc95xx_dongles[i].vendor == 0) - return 0; - - /* At this point, we know we've got a live one */ - debug("\n\nUSB Ethernet device detected\n"); - memset(ss, '\0', sizeof(struct ueth_data)); - - /* Initialize the ueth_data structure with some useful info */ - ss->ifnum = ifnum; - ss->pusb_dev = dev; - ss->subclass = iface_desc->bInterfaceSubClass; - ss->protocol = iface_desc->bInterfaceProtocol; - - /* - * We are expecting a minimum of 3 endpoints - in, out (bulk), and int. - * We will ignore any others. - */ - for (i = 0; i < iface_desc->bNumEndpoints; i++) { - /* is it an BULK endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { - if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) - ss->ep_in = - iface->ep_desc[i].bEndpointAddress & - USB_ENDPOINT_NUMBER_MASK; - else - ss->ep_out = - iface->ep_desc[i].bEndpointAddress & - USB_ENDPOINT_NUMBER_MASK; - } - - /* is it an interrupt endpoint? */ - if ((iface->ep_desc[i].bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { - ss->ep_int = iface->ep_desc[i].bEndpointAddress & - USB_ENDPOINT_NUMBER_MASK; - ss->irqinterval = iface->ep_desc[i].bInterval; - } - } - debug("Endpoints In %d Out %d Int %d\n", - ss->ep_in, ss->ep_out, ss->ep_int); - - /* Do some basic sanity checks, and bail if we find a problem */ - if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) || - !ss->ep_in || !ss->ep_out || !ss->ep_int) { - debug("Problems with device\n"); - return 0; - } - dev->privptr = (void *)ss; - - /* alloc driver private */ - ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private)); - if (!ss->dev_priv) - return 0; - - return 1; -} - -int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth) -{ - debug("** %s()\n", __func__); - if (!eth) { - debug("%s: missing parameter.\n", __func__); - return 0; - } - sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++); - eth->init = smsc95xx_init; - eth->send = smsc95xx_send; - eth->recv = smsc95xx_recv; - eth->halt = smsc95xx_halt; - eth->write_hwaddr = smsc95xx_write_hwaddr; - eth->priv = ss; - return 1; -} -#endif /* !CONFIG_DM_ETH */ - -#ifdef CONFIG_DM_ETH static int smsc95xx_eth_start(struct udevice *dev) { struct usb_device *udev = dev_get_parent_priv(dev); @@ -1077,4 +844,3 @@ static const struct usb_device_id smsc95xx_eth_id_table[] = { }; U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table); -#endif From b8daa6e9ee079fea7f9772e40b56147274c5726b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:33 -0500 Subject: [PATCH 109/424] usb: eth: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code fro usb_ether itself. Signed-off-by: Tom Rini --- drivers/usb/eth/usb_ether.c | 199 ---------------------------------- drivers/usb/host/usb-uclass.c | 43 -------- include/usb.h | 15 --- include/usb_ether.h | 44 +------- 4 files changed, 1 insertion(+), 300 deletions(-) diff --git a/drivers/usb/eth/usb_ether.c b/drivers/usb/eth/usb_ether.c index e368ecda0d..2e9af54fd6 100644 --- a/drivers/usb/eth/usb_ether.c +++ b/drivers/usb/eth/usb_ether.c @@ -15,8 +15,6 @@ #include "usb_ether.h" -#ifdef CONFIG_DM_ETH - #define USB_BULK_RECV_TIMEOUT 500 int usb_ether_register(struct udevice *dev, struct ueth_data *ueth, int rxsize) @@ -137,200 +135,3 @@ int usb_ether_get_rx_bytes(struct ueth_data *ueth, uint8_t **ptrp) return ueth->rxlen - ueth->rxptr; } - -#else - -typedef void (*usb_eth_before_probe)(void); -typedef int (*usb_eth_probe)(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -typedef int (*usb_eth_get_info)(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *dev_desc); - -struct usb_eth_prob_dev { - usb_eth_before_probe before_probe; /* optional */ - usb_eth_probe probe; - usb_eth_get_info get_info; -}; - -/* driver functions go here, each bracketed by #ifdef CONFIG_USB_ETHER_xxx */ -static const struct usb_eth_prob_dev prob_dev[] = { -#ifdef CONFIG_USB_ETHER_ASIX - { - .before_probe = asix_eth_before_probe, - .probe = asix_eth_probe, - .get_info = asix_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_ASIX88179 - { - .before_probe = ax88179_eth_before_probe, - .probe = ax88179_eth_probe, - .get_info = ax88179_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_MCS7830 - { - .before_probe = mcs7830_eth_before_probe, - .probe = mcs7830_eth_probe, - .get_info = mcs7830_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_SMSC95XX - { - .before_probe = smsc95xx_eth_before_probe, - .probe = smsc95xx_eth_probe, - .get_info = smsc95xx_eth_get_info, - }, -#endif -#ifdef CONFIG_USB_ETHER_RTL8152 - { - .before_probe = r8152_eth_before_probe, - .probe = r8152_eth_probe, - .get_info = r8152_eth_get_info, - }, -#endif - { }, /* END */ -}; - -static int usb_max_eth_dev; /* number of highest available usb eth device */ -static struct ueth_data usb_eth[USB_MAX_ETH_DEV]; - -/******************************************************************************* - * tell if current ethernet device is a usb dongle - */ -int is_eth_dev_on_usb_host(void) -{ - int i; - struct eth_device *dev = eth_get_dev(); - - if (dev) { - for (i = 0; i < usb_max_eth_dev; i++) - if (&usb_eth[i].eth_dev == dev) - return 1; - } - return 0; -} - -/* - * Given a USB device, ask each driver if it can support it, and attach it - * to the first driver that says 'yes' - */ -static void probe_valid_drivers(struct usb_device *dev) -{ - struct eth_device *eth; - int j; - - for (j = 0; prob_dev[j].probe && prob_dev[j].get_info; j++) { - if (!prob_dev[j].probe(dev, 0, &usb_eth[usb_max_eth_dev])) - continue; - /* - * ok, it is a supported eth device. Get info and fill it in - */ - eth = &usb_eth[usb_max_eth_dev].eth_dev; - if (prob_dev[j].get_info(dev, - &usb_eth[usb_max_eth_dev], - eth)) { - /* found proper driver */ - /* register with networking stack */ - usb_max_eth_dev++; - - /* - * usb_max_eth_dev must be incremented prior to this - * call since eth_current_changed (internally called) - * relies on it - */ - eth_register(eth); - if (eth_write_hwaddr(eth, "usbeth", - usb_max_eth_dev - 1)) - puts("Warning: failed to set MAC address\n"); - break; - } - } - } - -/******************************************************************************* - * scan the usb and reports device info - * to the user if mode = 1 - * returns current device or -1 if no - */ -int usb_host_eth_scan(int mode) -{ - int i, old_async; - - if (mode == 1) - printf(" scanning usb for ethernet devices... "); - - old_async = usb_disable_asynch(1); /* asynch transfer not allowed */ - - /* unregister a previously detected device */ - for (i = 0; i < usb_max_eth_dev; i++) - eth_unregister(&usb_eth[i].eth_dev); - - memset(usb_eth, 0, sizeof(usb_eth)); - - for (i = 0; prob_dev[i].probe; i++) { - if (prob_dev[i].before_probe) - prob_dev[i].before_probe(); - } - - usb_max_eth_dev = 0; -#if CONFIG_IS_ENABLED(DM_USB) - /* - * TODO: We should add U_BOOT_USB_DEVICE() declarations to each USB - * Ethernet driver and then most of this file can be removed. - */ - struct udevice *bus; - struct uclass *uc; - int ret; - - ret = uclass_get(UCLASS_USB, &uc); - if (ret) - return ret; - uclass_foreach_dev(bus, uc) { - for (i = 0; i < USB_MAX_DEVICE; i++) { - struct usb_device *dev; - - dev = usb_get_dev_index(bus, i); /* get device */ - debug("i=%d, %s\n", i, dev ? dev->dev->name : "(done)"); - if (!dev) - break; /* no more devices available */ - - /* - * find valid usb_ether driver for this device, - * if any - */ - probe_valid_drivers(dev); - - /* check limit */ - if (usb_max_eth_dev == USB_MAX_ETH_DEV) - break; - } /* for */ - } -#else - for (i = 0; i < USB_MAX_DEVICE; i++) { - struct usb_device *dev; - - dev = usb_get_dev_index(i); /* get device */ - debug("i=%d\n", i); - if (!dev) - break; /* no more devices available */ - - /* find valid usb_ether driver for this device, if any */ - probe_valid_drivers(dev); - - /* check limit */ - if (usb_max_eth_dev == USB_MAX_ETH_DEV) - break; - } /* for */ -#endif - if (usb_max_eth_dev == USB_MAX_ETH_DEV) { - printf("max USB Ethernet Device reached: %d stopping\n", - usb_max_eth_dev); - } - usb_disable_asynch(old_async); /* restore asynch value */ - printf("%d Ethernet Device(s) found\n", usb_max_eth_dev); - if (usb_max_eth_dev > 0) - return 0; - return -1; -} -#endif diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 060f3441df..956e2a4e8e 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -346,49 +346,6 @@ int usb_init(void) return usb_started ? 0 : -1; } -/* - * TODO(sjg@chromium.org): Remove this legacy function. At present it is needed - * to support boards which use driver model for USB but not Ethernet, and want - * to use USB Ethernet. - * - * The #if clause is here to ensure that remains the only case. - */ -#if !defined(CONFIG_DM_ETH) && defined(CONFIG_USB_HOST_ETHER) -static struct usb_device *find_child_devnum(struct udevice *parent, int devnum) -{ - struct usb_device *udev; - struct udevice *dev; - - if (!device_active(parent)) - return NULL; - udev = dev_get_parent_priv(parent); - if (udev->devnum == devnum) - return udev; - - for (device_find_first_child(parent, &dev); - dev; - device_find_next_child(&dev)) { - udev = find_child_devnum(dev, devnum); - if (udev) - return udev; - } - - return NULL; -} - -struct usb_device *usb_get_dev_index(struct udevice *bus, int index) -{ - struct udevice *dev; - int devnum = index + 1; /* Addresses are allocated from 1 on USB */ - - device_find_first_child(bus, &dev); - if (!dev) - return NULL; - - return find_child_devnum(dev, devnum); -} -#endif - int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp) { struct usb_plat *plat; diff --git a/include/usb.h b/include/usb.h index 7e3796bd5b..80cb846720 100644 --- a/include/usb.h +++ b/include/usb.h @@ -808,21 +808,6 @@ struct dm_usb_ops { #define usb_get_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) #define usb_get_emul_ops(dev) ((struct dm_usb_ops *)(dev)->driver->ops) -/** - * usb_get_dev_index() - look up a device index number - * - * Look up devices using their index number (starting at 0). This works since - * in U-Boot device addresses are allocated starting at 1 with no gaps. - * - * TODO(sjg@chromium.org): Remove this function when usb_ether.c is modified - * to work better with driver model. - * - * @bus: USB bus to check - * @index: Index number of device to find (0=first). This is just the - * device address less 1. - */ -struct usb_device *usb_get_dev_index(struct udevice *bus, int index); - /** * usb_setup_device() - set up a device ready for use * diff --git a/include/usb_ether.h b/include/usb_ether.h index 8c7bd06906..18d7184711 100644 --- a/include/usb_ether.h +++ b/include/usb_ether.h @@ -8,19 +8,13 @@ #include -/* TODO(sjg@chromium.org): Remove @pusb_dev when all boards use CONFIG_DM_ETH */ +/* TODO(sjg@chromium.org): Remove @pusb_dev now that all boards use CONFIG_DM_ETH */ struct ueth_data { /* eth info */ -#ifdef CONFIG_DM_ETH uint8_t *rxbuf; int rxsize; int rxlen; /* Total bytes available in rxbuf */ int rxptr; /* Current position in rxbuf */ -#else - struct eth_device eth_dev; /* used with eth_register */ - /* driver private */ - void *dev_priv; -#endif int phy_id; /* mii phy id */ /* usb info */ @@ -34,7 +28,6 @@ struct ueth_data { unsigned char irqinterval; /* Intervall for IRQ Pipe */ }; -#ifdef CONFIG_DM_ETH /** * usb_ether_register() - register a new USB ethernet device * @@ -92,40 +85,5 @@ int usb_ether_get_rx_bytes(struct ueth_data *ueth, uint8_t **ptrp); * @num_bytes: Number of bytes to skip, or -1 to skip all bytes */ void usb_ether_advance_rxbuf(struct ueth_data *ueth, int num_bytes); -#else -/* - * Function definitions for each USB ethernet driver go here - * (declaration is unconditional, compilation is conditional) - */ -void asix_eth_before_probe(void); -int asix_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void ax88179_eth_before_probe(void); -int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void mcs7830_eth_before_probe(void); -int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void smsc95xx_eth_before_probe(void); -int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); - -void r8152_eth_before_probe(void); -int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum, - struct ueth_data *ss); -int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, - struct eth_device *eth); -#endif #endif /* __USB_ETHER_H__ */ From 2098a3b8fe1d228c445d64d9408ea14fafdc4091 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:34 -0500 Subject: [PATCH 110/424] usb: gadget: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/usb/gadget/ether.c | 97 -------------------------------------- drivers/usb/gadget/rndis.c | 9 ---- drivers/usb/gadget/rndis.h | 11 ----- 3 files changed, 117 deletions(-) diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 43aec7ffa7..85c971e4c4 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -109,11 +109,7 @@ struct eth_dev { struct usb_request *tx_req, *rx_req; -#ifndef CONFIG_DM_ETH - struct eth_device *net; -#else struct udevice *net; -#endif struct net_device_stats stats; unsigned int tx_qlen; @@ -140,11 +136,7 @@ struct eth_dev { /*-------------------------------------------------------------------------*/ struct ether_priv { struct eth_dev ethdev; -#ifndef CONFIG_DM_ETH - struct eth_device netdev; -#else struct udevice *netdev; -#endif struct usb_gadget_driver eth_driver; }; @@ -1827,22 +1819,14 @@ static void rndis_control_ack_complete(struct usb_ep *ep, static char rndis_resp_buf[8] __attribute__((aligned(sizeof(__le32)))); -#ifndef CONFIG_DM_ETH -static int rndis_control_ack(struct eth_device *net) -#else static int rndis_control_ack(struct udevice *net) -#endif { struct ether_priv *priv; struct eth_dev *dev; int length; struct usb_request *resp; -#ifndef CONFIG_DM_ETH - priv = (struct ether_priv *)net->priv; -#else priv = dev_get_priv(net); -#endif dev = &priv->ethdev; resp = dev->stat_req; @@ -1989,9 +1973,7 @@ static int eth_bind(struct usb_gadget *gadget) int status = -ENOMEM; int gcnum; u8 tmp[7]; -#ifdef CONFIG_DM_ETH struct eth_pdata *pdata = dev_get_plat(l_priv->netdev); -#endif /* these flags are only ever cleared; compiler take note */ #ifndef CONFIG_USB_ETH_CDC @@ -2168,11 +2150,7 @@ autoconf_fail: /* network device setup */ -#ifndef CONFIG_DM_ETH - dev->net = &l_priv->netdev; -#else dev->net = l_priv->netdev; -#endif dev->cdc = cdc; dev->zlp = zlp; @@ -2189,13 +2167,8 @@ autoconf_fail: * host side code for the SAFE thing cares -- its original BLAN * thing didn't, Sharp never assigned those addresses on Zaurii. */ -#ifndef CONFIG_DM_ETH - get_ether_addr(dev_addr, dev->net->enetaddr); - memcpy(tmp, dev->net->enetaddr, sizeof(dev->net->enetaddr)); -#else get_ether_addr(dev_addr, pdata->enetaddr); memcpy(tmp, pdata->enetaddr, sizeof(pdata->enetaddr)); -#endif get_ether_addr(host_addr, dev->host_mac); @@ -2256,11 +2229,7 @@ autoconf_fail: status_ep ? " STATUS " : "", status_ep ? status_ep->name : "" ); -#ifndef CONFIG_DM_ETH - printf("MAC %pM\n", dev->net->enetaddr); -#else printf("MAC %pM\n", pdata->enetaddr); -#endif if (cdc || rndis) printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n", @@ -2490,71 +2459,6 @@ static void _usb_eth_halt(struct ether_priv *priv) usb_gadget_release(0); } -#ifndef CONFIG_DM_ETH -static int usb_eth_init(struct eth_device *netdev, struct bd_info *bd) -{ - struct ether_priv *priv = (struct ether_priv *)netdev->priv; - - return _usb_eth_init(priv); -} - -static int usb_eth_send(struct eth_device *netdev, void *packet, int length) -{ - struct ether_priv *priv = (struct ether_priv *)netdev->priv; - - return _usb_eth_send(priv, packet, length); -} - -static int usb_eth_recv(struct eth_device *netdev) -{ - struct ether_priv *priv = (struct ether_priv *)netdev->priv; - struct eth_dev *dev = &priv->ethdev; - int ret; - - ret = _usb_eth_recv(priv); - if (ret) { - pr_err("error packet receive\n"); - return ret; - } - - if (!packet_received) - return 0; - - if (dev->rx_req) { - net_process_received_packet(net_rx_packets[0], - dev->rx_req->length); - } else { - pr_err("dev->rx_req invalid"); - } - packet_received = 0; - rx_submit(dev, dev->rx_req, 0); - - return 0; -} - -void usb_eth_halt(struct eth_device *netdev) -{ - struct ether_priv *priv = (struct ether_priv *)netdev->priv; - - _usb_eth_halt(priv); -} - -int usb_eth_initialize(struct bd_info *bi) -{ - struct eth_device *netdev = &l_priv->netdev; - - strlcpy(netdev->name, USB_NET_NAME, sizeof(netdev->name)); - - netdev->init = usb_eth_init; - netdev->send = usb_eth_send; - netdev->recv = usb_eth_recv; - netdev->halt = usb_eth_halt; - netdev->priv = l_priv; - - eth_register(netdev); - return 0; -} -#else static int usb_eth_start(struct udevice *dev) { struct ether_priv *priv = dev_get_priv(dev); @@ -2663,4 +2567,3 @@ U_BOOT_DRIVER(eth_usb) = { .plat_auto = sizeof(struct eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, }; -#endif /* CONFIG_DM_ETH */ diff --git a/drivers/usb/gadget/rndis.c b/drivers/usb/gadget/rndis.c index 13c327ea38..d2a51829f9 100644 --- a/drivers/usb/gadget/rndis.c +++ b/drivers/usb/gadget/rndis.c @@ -1115,11 +1115,7 @@ int rndis_msg_parser(u8 configNr, u8 *buf) return -ENOTSUPP; } -#ifndef CONFIG_DM_ETH -int rndis_register(int (*rndis_control_ack)(struct eth_device *)) -#else int rndis_register(int (*rndis_control_ack)(struct udevice *)) -#endif { u8 i; @@ -1147,13 +1143,8 @@ void rndis_deregister(int configNr) return; } -#ifndef CONFIG_DM_ETH -int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu, - struct net_device_stats *stats, u16 *cdc_filter) -#else int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu, struct net_device_stats *stats, u16 *cdc_filter) -#endif { debug("%s: configNr = %d\n", __func__, configNr); if (!dev || !stats) diff --git a/drivers/usb/gadget/rndis.h b/drivers/usb/gadget/rndis.h index e827af0be4..77db55a563 100644 --- a/drivers/usb/gadget/rndis.h +++ b/drivers/usb/gadget/rndis.h @@ -226,13 +226,8 @@ typedef struct rndis_params { u32 vendorID; const char *vendorDescr; -#ifndef CONFIG_DM_ETH - struct eth_device *dev; - int (*ack)(struct eth_device *); -#else struct udevice *dev; int (*ack)(struct udevice *); -#endif struct list_head resp_queue; } rndis_params; @@ -240,15 +235,9 @@ typedef struct rndis_params { int rndis_msg_parser(u8 configNr, u8 *buf); enum rndis_state rndis_get_state(int configNr); void rndis_deregister(int configNr); -#ifndef CONFIG_DM_ETH -int rndis_register(int (*rndis_control_ack)(struct eth_device *)); -int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu, - struct net_device_stats *stats, u16 *cdc_filter); -#else int rndis_register(int (*rndis_control_ack)(struct udevice *)); int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu, struct net_device_stats *stats, u16 *cdc_filter); -#endif int rndis_set_param_vendor(u8 configNr, u32 vendorID, const char *vendorDescr); int rndis_set_param_medium(u8 configNr, u32 medium, u32 speed); From 9e0bcf8043084515fd7d0102b5f3192ae2be1124 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:35 -0500 Subject: [PATCH 111/424] qe: Remove non-DM_ETH code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini --- drivers/qe/Makefile | 2 +- drivers/qe/uccf.c | 509 --------------- drivers/qe/uccf.h | 119 ---- drivers/qe/uec.c | 1436 ------------------------------------------ drivers/qe/uec.h | 692 -------------------- drivers/qe/uec_phy.c | 930 --------------------------- drivers/qe/uec_phy.h | 214 ------- 7 files changed, 1 insertion(+), 3901 deletions(-) delete mode 100644 drivers/qe/uccf.c delete mode 100644 drivers/qe/uccf.h delete mode 100644 drivers/qe/uec.c delete mode 100644 drivers/qe/uec.h delete mode 100644 drivers/qe/uec_phy.c delete mode 100644 drivers/qe/uec_phy.h diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index 0d31ed1a42..12d0b459fb 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -2,6 +2,6 @@ # # Copyright (C) 2006 Freescale Semiconductor, Inc. -obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_QE) += qe.o obj-$(CONFIG_U_QE) += qe.o obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/drivers/qe/uccf.c b/drivers/qe/uccf.c deleted file mode 100644 index d5d734439c..0000000000 --- a/drivers/qe/uccf.c +++ /dev/null @@ -1,509 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * Dave Liu - * based on source code of Shlomi Gridish - */ - -#include -#include -#include -#include -#include -#include "uccf.h" -#include - -#if !defined(CONFIG_DM_ETH) -void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf) -{ - out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD); -} - -u32 ucc_fast_get_qe_cr_subblock(int ucc_num) -{ - switch (ucc_num) { - case 0: - return QE_CR_SUBBLOCK_UCCFAST1; - case 1: - return QE_CR_SUBBLOCK_UCCFAST2; - case 2: - return QE_CR_SUBBLOCK_UCCFAST3; - case 3: - return QE_CR_SUBBLOCK_UCCFAST4; - case 4: - return QE_CR_SUBBLOCK_UCCFAST5; - case 5: - return QE_CR_SUBBLOCK_UCCFAST6; - case 6: - return QE_CR_SUBBLOCK_UCCFAST7; - case 7: - return QE_CR_SUBBLOCK_UCCFAST8; - default: - return QE_CR_SUBBLOCK_INVALID; - } -} - -static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr, - u8 *reg_num, u8 *shift) -{ - switch (ucc_num) { - case 0: /* UCC1 */ - *p_cmxucr = &qe_immr->qmx.cmxucr1; - *reg_num = 1; - *shift = 16; - break; - case 2: /* UCC3 */ - *p_cmxucr = &qe_immr->qmx.cmxucr1; - *reg_num = 1; - *shift = 0; - break; - case 4: /* UCC5 */ - *p_cmxucr = &qe_immr->qmx.cmxucr2; - *reg_num = 2; - *shift = 16; - break; - case 6: /* UCC7 */ - *p_cmxucr = &qe_immr->qmx.cmxucr2; - *reg_num = 2; - *shift = 0; - break; - case 1: /* UCC2 */ - *p_cmxucr = &qe_immr->qmx.cmxucr3; - *reg_num = 3; - *shift = 16; - break; - case 3: /* UCC4 */ - *p_cmxucr = &qe_immr->qmx.cmxucr3; - *reg_num = 3; - *shift = 0; - break; - case 5: /* UCC6 */ - *p_cmxucr = &qe_immr->qmx.cmxucr4; - *reg_num = 4; - *shift = 16; - break; - case 7: /* UCC8 */ - *p_cmxucr = &qe_immr->qmx.cmxucr4; - *reg_num = 4; - *shift = 0; - break; - default: - break; - } -} - -static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode) -{ - u32 *p_cmxucr = NULL; - u8 reg_num = 0; - u8 shift = 0; - u32 clk_bits; - u32 clk_mask; - int source = -1; - - /* check if the UCC number is in range. */ - if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) - return -EINVAL; - - if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) { - printf("%s: bad comm mode type passed\n", __func__); - return -EINVAL; - } - - ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); - - switch (reg_num) { - case 1: - switch (clock) { - case QE_BRG1: - source = 1; - break; - case QE_BRG2: - source = 2; - break; - case QE_BRG7: - source = 3; - break; - case QE_BRG8: - source = 4; - break; - case QE_CLK9: - source = 5; - break; - case QE_CLK10: - source = 6; - break; - case QE_CLK11: - source = 7; - break; - case QE_CLK12: - source = 8; - break; - case QE_CLK15: - source = 9; - break; - case QE_CLK16: - source = 10; - break; - default: - source = -1; - break; - } - break; - case 2: - switch (clock) { - case QE_BRG5: - source = 1; - break; - case QE_BRG6: - source = 2; - break; - case QE_BRG7: - source = 3; - break; - case QE_BRG8: - source = 4; - break; - case QE_CLK13: - source = 5; - break; - case QE_CLK14: - source = 6; - break; - case QE_CLK19: - source = 7; - break; - case QE_CLK20: - source = 8; - break; - case QE_CLK15: - source = 9; - break; - case QE_CLK16: - source = 10; - break; - default: - source = -1; - break; - } - break; - case 3: - switch (clock) { - case QE_BRG9: - source = 1; - break; - case QE_BRG10: - source = 2; - break; - case QE_BRG15: - source = 3; - break; - case QE_BRG16: - source = 4; - break; - case QE_CLK3: - source = 5; - break; - case QE_CLK4: - source = 6; - break; - case QE_CLK17: - source = 7; - break; - case QE_CLK18: - source = 8; - break; - case QE_CLK7: - source = 9; - break; - case QE_CLK8: - source = 10; - break; - case QE_CLK16: - source = 11; - break; - default: - source = -1; - break; - } - break; - case 4: - switch (clock) { - case QE_BRG13: - source = 1; - break; - case QE_BRG14: - source = 2; - break; - case QE_BRG15: - source = 3; - break; - case QE_BRG16: - source = 4; - break; - case QE_CLK5: - source = 5; - break; - case QE_CLK6: - source = 6; - break; - case QE_CLK21: - source = 7; - break; - case QE_CLK22: - source = 8; - break; - case QE_CLK7: - source = 9; - break; - case QE_CLK8: - source = 10; - break; - case QE_CLK16: - source = 11; - break; - default: - source = -1; - break; - } - break; - default: - source = -1; - break; - } - - if (source == -1) { - printf("%s: Bad combination of clock and UCC\n", __func__); - return -ENOENT; - } - - clk_bits = (u32)source; - clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK; - if (mode == COMM_DIR_RX) { - clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */ - clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */ - } - clk_bits <<= shift; - clk_mask <<= shift; - - out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits); - - return 0; -} - -static uint ucc_get_reg_baseaddr(int ucc_num) -{ - uint base = 0; - - /* check if the UCC number is in range */ - if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) { - printf("%s: the UCC num not in ranges\n", __func__); - return 0; - } - - switch (ucc_num) { - case 0: - base = 0x00002000; - break; - case 1: - base = 0x00003000; - break; - case 2: - base = 0x00002200; - break; - case 3: - base = 0x00003200; - break; - case 4: - base = 0x00002400; - break; - case 5: - base = 0x00003400; - break; - case 6: - base = 0x00002600; - break; - case 7: - base = 0x00003600; - break; - default: - break; - } - - base = (uint)qe_immr + base; - return base; -} - -void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode) -{ - ucc_fast_t *uf_regs; - u32 gumr; - - uf_regs = uccf->uf_regs; - - /* Enable reception and/or transmission on this UCC. */ - gumr = in_be32(&uf_regs->gumr); - if (mode & COMM_DIR_TX) { - gumr |= UCC_FAST_GUMR_ENT; - uccf->enabled_tx = 1; - } - if (mode & COMM_DIR_RX) { - gumr |= UCC_FAST_GUMR_ENR; - uccf->enabled_rx = 1; - } - out_be32(&uf_regs->gumr, gumr); -} - -void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode) -{ - ucc_fast_t *uf_regs; - u32 gumr; - - uf_regs = uccf->uf_regs; - - /* Disable reception and/or transmission on this UCC. */ - gumr = in_be32(&uf_regs->gumr); - if (mode & COMM_DIR_TX) { - gumr &= ~UCC_FAST_GUMR_ENT; - uccf->enabled_tx = 0; - } - if (mode & COMM_DIR_RX) { - gumr &= ~UCC_FAST_GUMR_ENR; - uccf->enabled_rx = 0; - } - out_be32(&uf_regs->gumr, gumr); -} - -int ucc_fast_init(struct ucc_fast_inf *uf_info, - struct ucc_fast_priv **uccf_ret) -{ - struct ucc_fast_priv *uccf; - ucc_fast_t *uf_regs; - - if (!uf_info) - return -EINVAL; - - if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { - printf("%s: Illagal UCC number!\n", __func__); - return -EINVAL; - } - - uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv)); - if (!uccf) { - printf("%s: No memory for UCC fast data structure!\n", - __func__); - return -ENOMEM; - } - memset(uccf, 0, sizeof(struct ucc_fast_priv)); - - /* Save fast UCC structure */ - uccf->uf_info = uf_info; - uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num); - - if (!uccf->uf_regs) { - printf("%s: No memory map for UCC fast controller!\n", - __func__); - return -ENOMEM; - } - - uccf->enabled_tx = 0; - uccf->enabled_rx = 0; - - uf_regs = uccf->uf_regs; - uccf->p_ucce = (u32 *)&uf_regs->ucce; - uccf->p_uccm = (u32 *)&uf_regs->uccm; - - /* Init GUEMR register, UCC both Rx and Tx is Fast protocol */ - out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX - | UCC_GUEMR_MODE_FAST_TX); - - /* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */ - out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH); - - /* Set the Giga ethernet VFIFO stuff */ - if (uf_info->eth_type == GIGA_ETH) { - /* Allocate memory for Tx Virtual Fifo */ - uccf->ucc_fast_tx_virtual_fifo_base_offset = - qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT, - UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); - - /* Allocate memory for Rx Virtual Fifo */ - uccf->ucc_fast_rx_virtual_fifo_base_offset = - qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT + - UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, - UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); - - /* utfb, urfb are offsets from MURAM base */ - out_be32(&uf_regs->utfb, - uccf->ucc_fast_tx_virtual_fifo_base_offset); - out_be32(&uf_regs->urfb, - uccf->ucc_fast_rx_virtual_fifo_base_offset); - - /* Set Virtual Fifo registers */ - out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT); - out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT); - out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT); - out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT); - out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT); - out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT); - } - - /* Set the Fast ethernet VFIFO stuff */ - if (uf_info->eth_type == FAST_ETH) { - /* Allocate memory for Tx Virtual Fifo */ - uccf->ucc_fast_tx_virtual_fifo_base_offset = - qe_muram_alloc(UCC_GETH_UTFS_INIT, - UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); - - /* Allocate memory for Rx Virtual Fifo */ - uccf->ucc_fast_rx_virtual_fifo_base_offset = - qe_muram_alloc(UCC_GETH_URFS_INIT + - UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD, - UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); - - /* utfb, urfb are offsets from MURAM base */ - out_be32(&uf_regs->utfb, - uccf->ucc_fast_tx_virtual_fifo_base_offset); - out_be32(&uf_regs->urfb, - uccf->ucc_fast_rx_virtual_fifo_base_offset); - - /* Set Virtual Fifo registers */ - out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT); - out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT); - out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT); - out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT); - out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT); - out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT); - } - - /* Rx clock routing */ - if (uf_info->rx_clock != QE_CLK_NONE) { - if (ucc_set_clk_src(uf_info->ucc_num, - uf_info->rx_clock, COMM_DIR_RX)) { - printf("%s: Illegal value for parameter 'RxClock'.\n", - __func__); - return -EINVAL; - } - } - - /* Tx clock routing */ - if (uf_info->tx_clock != QE_CLK_NONE) { - if (ucc_set_clk_src(uf_info->ucc_num, - uf_info->tx_clock, COMM_DIR_TX)) { - printf("%s: Illegal value for parameter 'TxClock'.\n", - __func__); - return -EINVAL; - } - } - - /* Clear interrupt mask register to disable all of interrupts */ - out_be32(&uf_regs->uccm, 0x0); - - /* Writing '1' to clear all of envents */ - out_be32(&uf_regs->ucce, 0xffffffff); - - *uccf_ret = uccf; - return 0; -} -#endif diff --git a/drivers/qe/uccf.h b/drivers/qe/uccf.h deleted file mode 100644 index 99f8458edf..0000000000 --- a/drivers/qe/uccf.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * - * Dave Liu - * based on source code of Shlomi Gridish - */ - -#ifndef __UCCF_H__ -#define __UCCF_H__ - -#include "common.h" -#include "linux/immap_qe.h" -#include - -/* Fast or Giga ethernet */ -enum enet_type { - FAST_ETH, - GIGA_ETH, -}; - -/* General UCC Extended Mode Register */ -#define UCC_GUEMR_MODE_MASK_RX 0x02 -#define UCC_GUEMR_MODE_MASK_TX 0x01 -#define UCC_GUEMR_MODE_FAST_RX 0x02 -#define UCC_GUEMR_MODE_FAST_TX 0x01 -#define UCC_GUEMR_MODE_SLOW_RX 0x00 -#define UCC_GUEMR_MODE_SLOW_TX 0x00 -/* Bit 3 must be set 1 */ -#define UCC_GUEMR_SET_RESERVED3 0x10 - -/* General UCC FAST Mode Register */ -#define UCC_FAST_GUMR_TCI 0x20000000 -#define UCC_FAST_GUMR_TRX 0x10000000 -#define UCC_FAST_GUMR_TTX 0x08000000 -#define UCC_FAST_GUMR_CDP 0x04000000 -#define UCC_FAST_GUMR_CTSP 0x02000000 -#define UCC_FAST_GUMR_CDS 0x01000000 -#define UCC_FAST_GUMR_CTSS 0x00800000 -#define UCC_FAST_GUMR_TXSY 0x00020000 -#define UCC_FAST_GUMR_RSYN 0x00010000 -#define UCC_FAST_GUMR_RTSM 0x00002000 -#define UCC_FAST_GUMR_REVD 0x00000400 -#define UCC_FAST_GUMR_ENR 0x00000020 -#define UCC_FAST_GUMR_ENT 0x00000010 - -/* GUMR [MODE] bit maps */ -#define UCC_FAST_GUMR_HDLC 0x00000000 -#define UCC_FAST_GUMR_QMC 0x00000002 -#define UCC_FAST_GUMR_UART 0x00000004 -#define UCC_FAST_GUMR_BISYNC 0x00000008 -#define UCC_FAST_GUMR_ATM 0x0000000a -#define UCC_FAST_GUMR_ETH 0x0000000c - -/* Transmit On Demand (UTORD) */ -#define UCC_SLOW_TOD 0x8000 -#define UCC_FAST_TOD 0x8000 - -/* Fast Ethernet (10/100 Mbps) */ -/* Rx virtual FIFO size */ -#define UCC_GETH_URFS_INIT 512 -/* 1/2 urfs */ -#define UCC_GETH_URFET_INIT 256 -/* 3/4 urfs */ -#define UCC_GETH_URFSET_INIT 384 -/* Tx virtual FIFO size */ -#define UCC_GETH_UTFS_INIT 512 -/* 1/2 utfs */ -#define UCC_GETH_UTFET_INIT 256 -#define UCC_GETH_UTFTT_INIT 128 - -/* Gigabit Ethernet (1000 Mbps) */ -/* Rx virtual FIFO size */ -#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ -/* 1/2 urfs */ -#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ -/* 3/4 urfs */ -#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ -/* Tx virtual FIFO size */ -#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ -/* 1/2 utfs */ -#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ -#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ - -/* UCC fast alignment */ -#define UCC_FAST_RX_ALIGN 4 -#define UCC_FAST_MRBLR_ALIGNMENT 4 -#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 - -/* Sizes */ -#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8 - -/* UCC fast structure. */ -struct ucc_fast_inf { - int ucc_num; - qe_clock_e rx_clock; - qe_clock_e tx_clock; - enum enet_type eth_type; -}; - -struct ucc_fast_priv { - struct ucc_fast_inf *uf_info; - ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */ - u32 *p_ucce; /* a pointer to the event register */ - u32 *p_uccm; /* a pointer to the mask register */ - int enabled_tx; /* whether UCC is enabled for Tx (ENT) */ - int enabled_rx; /* whether UCC is enabled for Rx (ENR) */ - u32 ucc_fast_tx_virtual_fifo_base_offset; - u32 ucc_fast_rx_virtual_fifo_base_offset; -}; - -void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf); -u32 ucc_fast_get_qe_cr_subblock(int ucc_num); -void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode); -void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode); -int ucc_fast_init(struct ucc_fast_inf *uf_info, - struct ucc_fast_priv **uccf_ret); - -#endif /* __UCCF_H__ */ diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c deleted file mode 100644 index 3108879643..0000000000 --- a/drivers/qe/uec.c +++ /dev/null @@ -1,1436 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2011 Freescale Semiconductor, Inc. - * - * Dave Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "uccf.h" -#include "uec.h" -#include "uec_phy.h" -#include "miiphy.h" -#include -#include - -#if !defined(CONFIG_DM_ETH) -/* Default UTBIPAR SMI address */ -#ifndef CONFIG_UTBIPAR_INIT_TBIPA -#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F -#endif - -static struct uec_inf uec_info[] = { -#ifdef CONFIG_UEC_ETH1 - STD_UEC_INFO(1), /* UEC1 */ -#endif -#ifdef CONFIG_UEC_ETH2 - STD_UEC_INFO(2), /* UEC2 */ -#endif -#ifdef CONFIG_UEC_ETH3 - STD_UEC_INFO(3), /* UEC3 */ -#endif -#ifdef CONFIG_UEC_ETH4 - STD_UEC_INFO(4), /* UEC4 */ -#endif -#ifdef CONFIG_UEC_ETH5 - STD_UEC_INFO(5), /* UEC5 */ -#endif -#ifdef CONFIG_UEC_ETH6 - STD_UEC_INFO(6), /* UEC6 */ -#endif -#ifdef CONFIG_UEC_ETH7 - STD_UEC_INFO(7), /* UEC7 */ -#endif -#ifdef CONFIG_UEC_ETH8 - STD_UEC_INFO(8), /* UEC8 */ -#endif -}; - -#define MAXCONTROLLERS (8) - -static struct eth_device *devlist[MAXCONTROLLERS]; - -static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode) -{ - uec_t *uec_regs; - u32 maccfg1; - - if (!uec) { - printf("%s: uec not initial\n", __func__); - return -EINVAL; - } - uec_regs = uec->uec_regs; - - maccfg1 = in_be32(&uec_regs->maccfg1); - - if (mode & COMM_DIR_TX) { - maccfg1 |= MACCFG1_ENABLE_TX; - out_be32(&uec_regs->maccfg1, maccfg1); - uec->mac_tx_enabled = 1; - } - - if (mode & COMM_DIR_RX) { - maccfg1 |= MACCFG1_ENABLE_RX; - out_be32(&uec_regs->maccfg1, maccfg1); - uec->mac_rx_enabled = 1; - } - - return 0; -} - -static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode) -{ - uec_t *uec_regs; - u32 maccfg1; - - if (!uec) { - printf("%s: uec not initial\n", __func__); - return -EINVAL; - } - uec_regs = uec->uec_regs; - - maccfg1 = in_be32(&uec_regs->maccfg1); - - if (mode & COMM_DIR_TX) { - maccfg1 &= ~MACCFG1_ENABLE_TX; - out_be32(&uec_regs->maccfg1, maccfg1); - uec->mac_tx_enabled = 0; - } - - if (mode & COMM_DIR_RX) { - maccfg1 &= ~MACCFG1_ENABLE_RX; - out_be32(&uec_regs->maccfg1, maccfg1); - uec->mac_rx_enabled = 0; - } - - return 0; -} - -static int uec_graceful_stop_tx(struct uec_priv *uec) -{ - ucc_fast_t *uf_regs; - u32 cecr_subblock; - u32 ucce; - - if (!uec || !uec->uccf) { - printf("%s: No handle passed.\n", __func__); - return -EINVAL; - } - - uf_regs = uec->uccf->uf_regs; - - /* Clear the grace stop event */ - out_be32(&uf_regs->ucce, UCCE_GRA); - - /* Issue host command */ - cecr_subblock = - ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); - qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, - (u8)QE_CR_PROTOCOL_ETHERNET, 0); - - /* Wait for command to complete */ - do { - ucce = in_be32(&uf_regs->ucce); - } while (!(ucce & UCCE_GRA)); - - uec->grace_stopped_tx = 1; - - return 0; -} - -static int uec_graceful_stop_rx(struct uec_priv *uec) -{ - u32 cecr_subblock; - u8 ack; - - if (!uec) { - printf("%s: No handle passed.\n", __func__); - return -EINVAL; - } - - if (!uec->p_rx_glbl_pram) { - printf("%s: No init rx global parameter\n", __func__); - return -EINVAL; - } - - /* Clear acknowledge bit */ - ack = uec->p_rx_glbl_pram->rxgstpack; - ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX; - uec->p_rx_glbl_pram->rxgstpack = ack; - - /* Keep issuing cmd and checking ack bit until it is asserted */ - do { - /* Issue host command */ - cecr_subblock = - ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); - qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock, - (u8)QE_CR_PROTOCOL_ETHERNET, 0); - ack = uec->p_rx_glbl_pram->rxgstpack; - } while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX)); - - uec->grace_stopped_rx = 1; - - return 0; -} - -static int uec_restart_tx(struct uec_priv *uec) -{ - u32 cecr_subblock; - - if (!uec || !uec->uec_info) { - printf("%s: No handle passed.\n", __func__); - return -EINVAL; - } - - cecr_subblock = - ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); - qe_issue_cmd(QE_RESTART_TX, cecr_subblock, - (u8)QE_CR_PROTOCOL_ETHERNET, 0); - - uec->grace_stopped_tx = 0; - - return 0; -} - -static int uec_restart_rx(struct uec_priv *uec) -{ - u32 cecr_subblock; - - if (!uec || !uec->uec_info) { - printf("%s: No handle passed.\n", __func__); - return -EINVAL; - } - - cecr_subblock = - ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num); - qe_issue_cmd(QE_RESTART_RX, cecr_subblock, - (u8)QE_CR_PROTOCOL_ETHERNET, 0); - - uec->grace_stopped_rx = 0; - - return 0; -} - -static int uec_open(struct uec_priv *uec, comm_dir_e mode) -{ - struct ucc_fast_priv *uccf; - - if (!uec || !uec->uccf) { - printf("%s: No handle passed.\n", __func__); - return -EINVAL; - } - uccf = uec->uccf; - - /* check if the UCC number is in range. */ - if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { - printf("%s: ucc_num out of range.\n", __func__); - return -EINVAL; - } - - /* Enable MAC */ - uec_mac_enable(uec, mode); - - /* Enable UCC fast */ - ucc_fast_enable(uccf, mode); - - /* RISC microcode start */ - if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) - uec_restart_tx(uec); - if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) - uec_restart_rx(uec); - - return 0; -} - -static int uec_stop(struct uec_priv *uec, comm_dir_e mode) -{ - if (!uec || !uec->uccf) { - printf("%s: No handle passed.\n", __func__); - return -EINVAL; - } - - /* check if the UCC number is in range. */ - if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) { - printf("%s: ucc_num out of range.\n", __func__); - return -EINVAL; - } - /* Stop any transmissions */ - if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) - uec_graceful_stop_tx(uec); - - /* Stop any receptions */ - if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) - uec_graceful_stop_rx(uec); - - /* Disable the UCC fast */ - ucc_fast_disable(uec->uccf, mode); - - /* Disable the MAC */ - uec_mac_disable(uec, mode); - - return 0; -} - -static int uec_set_mac_duplex(struct uec_priv *uec, int duplex) -{ - uec_t *uec_regs; - u32 maccfg2; - - if (!uec) { - printf("%s: uec not initial\n", __func__); - return -EINVAL; - } - uec_regs = uec->uec_regs; - - if (duplex == DUPLEX_HALF) { - maccfg2 = in_be32(&uec_regs->maccfg2); - maccfg2 &= ~MACCFG2_FDX; - out_be32(&uec_regs->maccfg2, maccfg2); - } - - if (duplex == DUPLEX_FULL) { - maccfg2 = in_be32(&uec_regs->maccfg2); - maccfg2 |= MACCFG2_FDX; - out_be32(&uec_regs->maccfg2, maccfg2); - } - - return 0; -} - -static int uec_set_mac_if_mode(struct uec_priv *uec, - phy_interface_t if_mode, int speed) -{ - phy_interface_t enet_if_mode; - uec_t *uec_regs; - u32 upsmr; - u32 maccfg2; - - if (!uec) { - printf("%s: uec not initial\n", __func__); - return -EINVAL; - } - - uec_regs = uec->uec_regs; - enet_if_mode = if_mode; - - maccfg2 = in_be32(&uec_regs->maccfg2); - maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK; - - upsmr = in_be32(&uec->uccf->uf_regs->upsmr); - upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM); - - switch (speed) { - case SPEED_10: - maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; - switch (enet_if_mode) { - case PHY_INTERFACE_MODE_MII: - break; - case PHY_INTERFACE_MODE_RGMII: - upsmr |= (UPSMR_RPM | UPSMR_R10M); - break; - case PHY_INTERFACE_MODE_RMII: - upsmr |= (UPSMR_R10M | UPSMR_RMM); - break; - default: - return -EINVAL; - } - break; - case SPEED_100: - maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE; - switch (enet_if_mode) { - case PHY_INTERFACE_MODE_MII: - break; - case PHY_INTERFACE_MODE_RGMII: - upsmr |= UPSMR_RPM; - break; - case PHY_INTERFACE_MODE_RMII: - upsmr |= UPSMR_RMM; - break; - default: - return -EINVAL; - } - break; - case SPEED_1000: - maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE; - switch (enet_if_mode) { - case PHY_INTERFACE_MODE_GMII: - break; - case PHY_INTERFACE_MODE_TBI: - upsmr |= UPSMR_TBIM; - break; - case PHY_INTERFACE_MODE_RTBI: - upsmr |= (UPSMR_RPM | UPSMR_TBIM); - break; - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII: - upsmr |= UPSMR_RPM; - break; - case PHY_INTERFACE_MODE_SGMII: - upsmr |= UPSMR_SGMM; - break; - default: - return -EINVAL; - } - break; - default: - return -EINVAL; - } - - out_be32(&uec_regs->maccfg2, maccfg2); - out_be32(&uec->uccf->uf_regs->upsmr, upsmr); - - return 0; -} - -static int init_mii_management_configuration(uec_mii_t *uec_mii_regs) -{ - uint timeout = 0x1000; - u32 miimcfg = 0; - - miimcfg = in_be32(&uec_mii_regs->miimcfg); - miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE; - out_be32(&uec_mii_regs->miimcfg, miimcfg); - - /* Wait until the bus is free */ - while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--) - ; - if (timeout <= 0) { - printf("%s: The MII Bus is stuck!", __func__); - return -ETIMEDOUT; - } - - return 0; -} - -static int init_phy(struct eth_device *dev) -{ - struct uec_priv *uec; - uec_mii_t *umii_regs; - struct uec_mii_info *mii_info; - struct phy_info *curphy; - int err; - - uec = (struct uec_priv *)dev->priv; - umii_regs = uec->uec_mii_regs; - - uec->oldlink = 0; - uec->oldspeed = 0; - uec->oldduplex = -1; - - mii_info = malloc(sizeof(*mii_info)); - if (!mii_info) { - printf("%s: Could not allocate mii_info", dev->name); - return -ENOMEM; - } - memset(mii_info, 0, sizeof(*mii_info)); - - if (uec->uec_info->uf_info.eth_type == GIGA_ETH) - mii_info->speed = SPEED_1000; - else - mii_info->speed = SPEED_100; - - mii_info->duplex = DUPLEX_FULL; - mii_info->pause = 0; - mii_info->link = 1; - - mii_info->advertising = (ADVERTISED_10baseT_Half | - ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | - ADVERTISED_100baseT_Full | - ADVERTISED_1000baseT_Full); - mii_info->autoneg = 1; - mii_info->mii_id = uec->uec_info->phy_address; - mii_info->dev = dev; - - mii_info->mdio_read = &uec_read_phy_reg; - mii_info->mdio_write = &uec_write_phy_reg; - - uec->mii_info = mii_info; - - qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num); - - if (init_mii_management_configuration(umii_regs)) { - printf("%s: The MII Bus is stuck!", dev->name); - err = -1; - goto bus_fail; - } - - /* get info for this PHY */ - curphy = uec_get_phy_info(uec->mii_info); - if (!curphy) { - printf("%s: No PHY found", dev->name); - err = -1; - goto no_phy; - } - - mii_info->phyinfo = curphy; - - /* Run the commands which initialize the PHY */ - if (curphy->init) { - err = curphy->init(uec->mii_info); - if (err) - goto phy_init_fail; - } - - return 0; - -phy_init_fail: -no_phy: -bus_fail: - free(mii_info); - return err; -} - -static void adjust_link(struct eth_device *dev) -{ - struct uec_priv *uec = (struct uec_priv *)dev->priv; - struct uec_mii_info *mii_info = uec->mii_info; - - if (mii_info->link) { - /* - * Now we make sure that we can be in full duplex mode. - * If not, we operate in half-duplex mode. - */ - if (mii_info->duplex != uec->oldduplex) { - if (!(mii_info->duplex)) { - uec_set_mac_duplex(uec, DUPLEX_HALF); - printf("%s: Half Duplex\n", dev->name); - } else { - uec_set_mac_duplex(uec, DUPLEX_FULL); - printf("%s: Full Duplex\n", dev->name); - } - uec->oldduplex = mii_info->duplex; - } - - if (mii_info->speed != uec->oldspeed) { - phy_interface_t mode = - uec->uec_info->enet_interface_type; - if (uec->uec_info->uf_info.eth_type == GIGA_ETH) { - switch (mii_info->speed) { - case SPEED_1000: - break; - case SPEED_100: - printf("switching to rgmii 100\n"); - mode = PHY_INTERFACE_MODE_RGMII; - break; - case SPEED_10: - printf("switching to rgmii 10\n"); - mode = PHY_INTERFACE_MODE_RGMII; - break; - default: - printf("%s: Ack,Speed(%d)is illegal\n", - dev->name, mii_info->speed); - break; - } - } - - /* change phy */ - change_phy_interface_mode(dev, mode, mii_info->speed); - /* change the MAC interface mode */ - uec_set_mac_if_mode(uec, mode, mii_info->speed); - - printf("%s: Speed %dBT\n", dev->name, mii_info->speed); - uec->oldspeed = mii_info->speed; - } - - if (!uec->oldlink) { - printf("%s: Link is up\n", dev->name); - uec->oldlink = 1; - } - - } else { /* if (mii_info->link) */ - if (uec->oldlink) { - printf("%s: Link is down\n", dev->name); - uec->oldlink = 0; - uec->oldspeed = 0; - uec->oldduplex = -1; - } - } -} - -static void phy_change(struct eth_device *dev) -{ - struct uec_priv *uec = (struct uec_priv *)dev->priv; - -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - - /* QE9 and QE12 need to be set for enabling QE MII management signals */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); -#endif - - /* Update the link, speed, duplex */ - uec->mii_info->phyinfo->read_status(uec->mii_info); - -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - /* - * QE12 is muxed with LBCTL, it needs to be released for enabling - * LBCTL signal for LBC usage. - */ - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); -#endif - - /* Adjust the interface according to speed */ - adjust_link(dev); -} - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - -/* - * Find a device index from the devlist by name - * - * Returns: - * The index where the device is located, -1 on error - */ -static int uec_miiphy_find_dev_by_name(const char *devname) -{ - int i; - - for (i = 0; i < MAXCONTROLLERS; i++) { - if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) - break; - } - - /* If device cannot be found, returns -1 */ - if (i == MAXCONTROLLERS) { - debug("%s: device %s not found in devlist\n", __func__, - devname); - i = -1; - } - - return i; -} - -/* - * Read a MII PHY register. - * - * Returns: - * 0 on success - */ -static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - unsigned short value = 0; - int devindex = 0; - - if (!bus->name) { - debug("%s: NULL pointer given\n", __func__); - } else { - devindex = uec_miiphy_find_dev_by_name(bus->name); - if (devindex >= 0) - value = uec_read_phy_reg(devlist[devindex], addr, reg); - } - return value; -} - -/* - * Write a MII PHY register. - * - * Returns: - * 0 on success - */ -static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value) -{ - int devindex = 0; - - if (!bus->name) { - debug("%s: NULL pointer given\n", __func__); - } else { - devindex = uec_miiphy_find_dev_by_name(bus->name); - if (devindex >= 0) - uec_write_phy_reg(devlist[devindex], addr, reg, value); - } - return 0; -} -#endif - -static int uec_set_mac_address(struct uec_priv *uec, u8 *mac_addr) -{ - uec_t *uec_regs; - u32 mac_addr1; - u32 mac_addr2; - - if (!uec) { - printf("%s: uec not initial\n", __func__); - return -EINVAL; - } - - uec_regs = uec->uec_regs; - - /* - * if a station address of 0x12345678ABCD, perform a write to - * MACSTNADDR1 of 0xCDAB7856, - * MACSTNADDR2 of 0x34120000 - */ - - mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | - (mac_addr[3] << 8) | (mac_addr[2]); - out_be32(&uec_regs->macstnaddr1, mac_addr1); - - mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000; - out_be32(&uec_regs->macstnaddr2, mac_addr2); - - return 0; -} - -static int uec_convert_threads_num(enum uec_num_of_threads threads_num, - int *threads_num_ret) -{ - int num_threads_numerica; - - switch (threads_num) { - case UEC_NUM_OF_THREADS_1: - num_threads_numerica = 1; - break; - case UEC_NUM_OF_THREADS_2: - num_threads_numerica = 2; - break; - case UEC_NUM_OF_THREADS_4: - num_threads_numerica = 4; - break; - case UEC_NUM_OF_THREADS_6: - num_threads_numerica = 6; - break; - case UEC_NUM_OF_THREADS_8: - num_threads_numerica = 8; - break; - default: - printf("%s: Bad number of threads value.", - __func__); - return -EINVAL; - } - - *threads_num_ret = num_threads_numerica; - - return 0; -} - -static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx) -{ - struct uec_inf *uec_info; - u32 end_bd; - u8 bmrx = 0; - int i; - - uec_info = uec->uec_info; - - /* Alloc global Tx parameter RAM page */ - uec->tx_glbl_pram_offset = - qe_muram_alloc(sizeof(struct uec_tx_global_pram), - UEC_TX_GLOBAL_PRAM_ALIGNMENT); - uec->p_tx_glbl_pram = (struct uec_tx_global_pram *) - qe_muram_addr(uec->tx_glbl_pram_offset); - - /* Zero the global Tx prameter RAM */ - memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram)); - - /* Init global Tx parameter RAM */ - - /* TEMODER, RMON statistics disable, one Tx queue */ - out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE); - - /* SQPTR */ - uec->send_q_mem_reg_offset = - qe_muram_alloc(sizeof(struct uec_send_queue_qd), - UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT); - uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *) - qe_muram_addr(uec->send_q_mem_reg_offset); - out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset); - - /* Setup the table with TxBDs ring */ - end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1) - * SIZEOFBD; - out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base, - (u32)(uec->p_tx_bd_ring)); - out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address, - end_bd); - - /* Scheduler Base Pointer, we have only one Tx queue, no need it */ - out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0); - - /* TxRMON Base Pointer, TxRMON disable, we don't need it */ - out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0); - - /* TSTATE, global snooping, big endian, the CSB bus selected */ - bmrx = BMR_INIT_VALUE; - out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT)); - - /* IPH_Offset */ - for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) - out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0); - - /* VTAG table */ - for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) - out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0); - - /* TQPTR */ - uec->thread_dat_tx_offset = - qe_muram_alloc(num_threads_tx * - sizeof(struct uec_thread_data_tx) + - 32 * (num_threads_tx == 1), - UEC_THREAD_DATA_ALIGNMENT); - - uec->p_thread_data_tx = (struct uec_thread_data_tx *) - qe_muram_addr(uec->thread_dat_tx_offset); - out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset); -} - -static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx) -{ - u8 bmrx = 0; - int i; - struct uec_82xx_add_filtering_pram *p_af_pram; - - /* Allocate global Rx parameter RAM page */ - uec->rx_glbl_pram_offset = - qe_muram_alloc(sizeof(struct uec_rx_global_pram), - UEC_RX_GLOBAL_PRAM_ALIGNMENT); - uec->p_rx_glbl_pram = (struct uec_rx_global_pram *) - qe_muram_addr(uec->rx_glbl_pram_offset); - - /* Zero Global Rx parameter RAM */ - memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram)); - - /* Init global Rx parameter RAM */ - /* - * REMODER, Extended feature mode disable, VLAN disable, - * LossLess flow control disable, Receive firmware statisic disable, - * Extended address parsing mode disable, One Rx queues, - * Dynamic maximum/minimum frame length disable, IP checksum check - * disable, IP address alignment disable - */ - out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE); - - /* RQPTR */ - uec->thread_dat_rx_offset = - qe_muram_alloc(num_threads_rx * - sizeof(struct uec_thread_data_rx), - UEC_THREAD_DATA_ALIGNMENT); - uec->p_thread_data_rx = (struct uec_thread_data_rx *) - qe_muram_addr(uec->thread_dat_rx_offset); - out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset); - - /* Type_or_Len */ - out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072); - - /* RxRMON base pointer, we don't need it */ - out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0); - - /* IntCoalescingPTR, we don't need it, no interrupt */ - out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0); - - /* RSTATE, global snooping, big endian, the CSB bus selected */ - bmrx = BMR_INIT_VALUE; - out_8(&uec->p_rx_glbl_pram->rstate, bmrx); - - /* MRBLR */ - out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN); - - /* RBDQPTR */ - uec->rx_bd_qs_tbl_offset = - qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) + - sizeof(struct uec_rx_pref_bds), - UEC_RX_BD_QUEUES_ALIGNMENT); - uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *) - qe_muram_addr(uec->rx_bd_qs_tbl_offset); - - /* Zero it */ - memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) + - sizeof(struct uec_rx_pref_bds)); - out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset); - out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr, - (u32)uec->p_rx_bd_ring); - - /* MFLR */ - out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN); - /* MINFLR */ - out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN); - /* MAXD1 */ - out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN); - /* MAXD2 */ - out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN); - /* ECAM_PTR */ - out_be32(&uec->p_rx_glbl_pram->ecamptr, 0); - /* L2QT */ - out_be32(&uec->p_rx_glbl_pram->l2qt, 0); - /* L3QT */ - for (i = 0; i < 8; i++) - out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0); - - /* VLAN_TYPE */ - out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100); - /* TCI */ - out_be16(&uec->p_rx_glbl_pram->vlantci, 0); - - /* Clear PQ2 style address filtering hash table */ - p_af_pram = (struct uec_82xx_add_filtering_pram *) - uec->p_rx_glbl_pram->addressfiltering; - - p_af_pram->iaddr_h = 0; - p_af_pram->iaddr_l = 0; - p_af_pram->gaddr_h = 0; - p_af_pram->gaddr_l = 0; -} - -static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec, - int thread_tx, int thread_rx) -{ - struct uec_init_cmd_pram *p_init_enet_param; - u32 init_enet_param_offset; - struct uec_inf *uec_info; - struct ucc_fast_inf *uf_info; - int i; - int snum; - u32 off; - u32 entry_val; - u32 command; - u32 cecr_subblock; - - uec_info = uec->uec_info; - uf_info = &uec_info->uf_info; - - /* Allocate init enet command parameter */ - uec->init_enet_param_offset = - qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4); - init_enet_param_offset = uec->init_enet_param_offset; - uec->p_init_enet_param = (struct uec_init_cmd_pram *) - qe_muram_addr(uec->init_enet_param_offset); - - /* Zero init enet command struct */ - memset((void *)uec->p_init_enet_param, 0, - sizeof(struct uec_init_cmd_pram)); - - /* Init the command struct */ - p_init_enet_param = uec->p_init_enet_param; - p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0; - p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1; - p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2; - p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3; - p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4; - p_init_enet_param->largestexternallookupkeysize = 0; - - p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx) - << ENET_INIT_PARAM_RGF_SHIFT; - p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx) - << ENET_INIT_PARAM_TGF_SHIFT; - - /* Init Rx global parameter pointer */ - p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset | - (u32)uec_info->risc_rx; - - /* Init Rx threads */ - for (i = 0; i < (thread_rx + 1); i++) { - snum = qe_get_snum(); - if (snum < 0) { - printf("%s can not get snum\n", __func__); - return -ENOMEM; - } - - if (i == 0) { - off = 0; - } else { - off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram), - UEC_THREAD_RX_PRAM_ALIGNMENT); - } - - entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | - off | (u32)uec_info->risc_rx; - p_init_enet_param->rxthread[i] = entry_val; - } - - /* Init Tx global parameter pointer */ - p_init_enet_param->txglobal = uec->tx_glbl_pram_offset | - (u32)uec_info->risc_tx; - - /* Init Tx threads */ - for (i = 0; i < thread_tx; i++) { - snum = qe_get_snum(); - if (snum < 0) { - printf("%s can not get snum\n", __func__); - return -ENOMEM; - } - - off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram), - UEC_THREAD_TX_PRAM_ALIGNMENT); - - entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) | - off | (u32)uec_info->risc_tx; - p_init_enet_param->txthread[i] = entry_val; - } - - __asm__ __volatile__("sync"); - - /* Issue QE command */ - command = QE_INIT_TX_RX; - cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); - qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET, - init_enet_param_offset); - - return 0; -} - -static int uec_startup(struct uec_priv *uec) -{ - struct uec_inf *uec_info; - struct ucc_fast_inf *uf_info; - struct ucc_fast_priv *uccf; - ucc_fast_t *uf_regs; - uec_t *uec_regs; - int num_threads_tx; - int num_threads_rx; - u32 utbipar; - u32 length; - u32 align; - struct buffer_descriptor *bd; - u8 *buf; - int i; - - if (!uec || !uec->uec_info) { - printf("%s: uec or uec_info not initial\n", __func__); - return -EINVAL; - } - - uec_info = uec->uec_info; - uf_info = &uec_info->uf_info; - - /* Check if Rx BD ring len is illegal */ - if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN || - (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) { - printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n", - __func__); - return -EINVAL; - } - - /* Check if Tx BD ring len is illegal */ - if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) { - printf("%s: Tx BD ring length must not be smaller than 2.\n", - __func__); - return -EINVAL; - } - - /* Check if MRBLR is illegal */ - if (MAX_RXBUF_LEN == 0 || MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT) { - printf("%s: max rx buffer length must be mutliple of 128.\n", - __func__); - return -EINVAL; - } - - /* Both Rx and Tx are stopped */ - uec->grace_stopped_rx = 1; - uec->grace_stopped_tx = 1; - - /* Init UCC fast */ - if (ucc_fast_init(uf_info, &uccf)) { - printf("%s: failed to init ucc fast\n", __func__); - return -ENOMEM; - } - - /* Save uccf */ - uec->uccf = uccf; - - /* Convert the Tx threads number */ - if (uec_convert_threads_num(uec_info->num_threads_tx, - &num_threads_tx)) { - return -EINVAL; - } - - /* Convert the Rx threads number */ - if (uec_convert_threads_num(uec_info->num_threads_rx, - &num_threads_rx)) { - return -EINVAL; - } - - uf_regs = uccf->uf_regs; - - /* UEC register is following UCC fast registers */ - uec_regs = (uec_t *)(&uf_regs->ucc_eth); - - /* Save the UEC register pointer to UEC private struct */ - uec->uec_regs = uec_regs; - - /* Init UPSMR, enable hardware statistics (UCC) */ - out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE); - - /* Init MACCFG1, flow control disable, disable Tx and Rx */ - out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE); - - /* Init MACCFG2, length check, MAC PAD and CRC enable */ - out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE); - - /* Setup MAC interface mode */ - uec_set_mac_if_mode(uec, uec_info->enet_interface_type, - uec_info->speed); - - /* Setup MII management base */ -#ifndef CONFIG_eTSEC_MDIO_BUS - uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg); -#else - uec->uec_mii_regs = (uec_mii_t *)CONFIG_MIIM_ADDRESS; -#endif - - /* Setup MII master clock source */ - qe_set_mii_clk_src(uec_info->uf_info.ucc_num); - - /* Setup UTBIPAR */ - utbipar = in_be32(&uec_regs->utbipar); - utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK; - - /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC. - * This frees up the remaining SMI addresses for use. - */ - utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT; - out_be32(&uec_regs->utbipar, utbipar); - - /* Configure the TBI for SGMII operation */ - if (uec->uec_info->enet_interface_type == PHY_INTERFACE_MODE_SGMII && - uec->uec_info->speed == SPEED_1000) { - uec_write_phy_reg(uec->dev, uec_regs->utbipar, - ENET_TBI_MII_ANA, TBIANA_SETTINGS); - - uec_write_phy_reg(uec->dev, uec_regs->utbipar, - ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); - - uec_write_phy_reg(uec->dev, uec_regs->utbipar, - ENET_TBI_MII_CR, TBICR_SETTINGS); - } - - /* Allocate Tx BDs */ - length = ((uec_info->tx_bd_ring_len * SIZEOFBD) / - UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) * - UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; - if ((uec_info->tx_bd_ring_len * SIZEOFBD) % - UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) { - length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT; - } - - align = UEC_TX_BD_RING_ALIGNMENT; - uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align)); - if (uec->tx_bd_ring_offset != 0) { - uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align) - & ~(align - 1)); - } - - /* Zero all of Tx BDs */ - memset((void *)(uec->tx_bd_ring_offset), 0, length + align); - - /* Allocate Rx BDs */ - length = uec_info->rx_bd_ring_len * SIZEOFBD; - align = UEC_RX_BD_RING_ALIGNMENT; - uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align))); - if (uec->rx_bd_ring_offset != 0) { - uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align) - & ~(align - 1)); - } - - /* Zero all of Rx BDs */ - memset((void *)(uec->rx_bd_ring_offset), 0, length + align); - - /* Allocate Rx buffer */ - length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN; - align = UEC_RX_DATA_BUF_ALIGNMENT; - uec->rx_buf_offset = (u32)malloc(length + align); - if (uec->rx_buf_offset != 0) { - uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align) - & ~(align - 1)); - } - - /* Zero all of the Rx buffer */ - memset((void *)(uec->rx_buf_offset), 0, length + align); - - /* Init TxBD ring */ - bd = (struct buffer_descriptor *)uec->p_tx_bd_ring; - uec->tx_bd = bd; - - for (i = 0; i < uec_info->tx_bd_ring_len; i++) { - BD_DATA_CLEAR(bd); - BD_STATUS_SET(bd, 0); - BD_LENGTH_SET(bd, 0); - bd++; - } - BD_STATUS_SET((--bd), TX_BD_WRAP); - - /* Init RxBD ring */ - bd = (struct buffer_descriptor *)uec->p_rx_bd_ring; - uec->rx_bd = bd; - buf = uec->p_rx_buf; - for (i = 0; i < uec_info->rx_bd_ring_len; i++) { - BD_DATA_SET(bd, buf); - BD_LENGTH_SET(bd, 0); - BD_STATUS_SET(bd, RX_BD_EMPTY); - buf += MAX_RXBUF_LEN; - bd++; - } - BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY); - - /* Init global Tx parameter RAM */ - uec_init_tx_parameter(uec, num_threads_tx); - - /* Init global Rx parameter RAM */ - uec_init_rx_parameter(uec, num_threads_rx); - - /* Init ethernet Tx and Rx parameter command */ - if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx, - num_threads_rx)) { - printf("%s issue init enet cmd failed\n", __func__); - return -ENOMEM; - } - - return 0; -} - -static int uec_init(struct eth_device *dev, struct bd_info *bd) -{ - struct uec_priv *uec; - int err, i; - struct phy_info *curphy; -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); -#endif - - uec = (struct uec_priv *)dev->priv; - - if (!uec->the_first_run) { -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - /* - * QE9 and QE12 need to be set for enabling QE MII - * management signals - */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); -#endif - - err = init_phy(dev); - if (err) { - printf("%s: Cannot initialize PHY, aborting.\n", - dev->name); - return err; - } - - curphy = uec->mii_info->phyinfo; - - if (curphy->config_aneg) { - err = curphy->config_aneg(uec->mii_info); - if (err) { - printf("%s: Can't negotiate PHY\n", dev->name); - return err; - } - } - - /* Give PHYs up to 5 sec to report a link */ - i = 50; - do { - err = curphy->read_status(uec->mii_info); - if (!(((i-- > 0) && !uec->mii_info->link) || err)) - break; - mdelay(100); - } while (1); - -#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - /* QE12 needs to be released for enabling LBCTL signal*/ - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); -#endif - - if (err || i <= 0) - printf("warning: %s: timeout on PHY link\n", dev->name); - - adjust_link(dev); - uec->the_first_run = 1; - } - - /* Set up the MAC address */ - if (dev->enetaddr[0] & 0x01) { - printf("%s: MacAddress is multcast address\n", - __func__); - return -1; - } - uec_set_mac_address(uec, dev->enetaddr); - - err = uec_open(uec, COMM_DIR_RX_AND_TX); - if (err) { - printf("%s: cannot enable UEC device\n", dev->name); - return -1; - } - - phy_change(dev); - - return uec->mii_info->link ? 0 : -1; -} - -static void uec_halt(struct eth_device *dev) -{ - struct uec_priv *uec = (struct uec_priv *)dev->priv; - - uec_stop(uec, COMM_DIR_RX_AND_TX); -} - -static int uec_send(struct eth_device *dev, void *buf, int len) -{ - struct uec_priv *uec; - struct ucc_fast_priv *uccf; - struct buffer_descriptor *bd; - u16 status; - int i; - int result = 0; - - uec = (struct uec_priv *)dev->priv; - uccf = uec->uccf; - bd = uec->tx_bd; - - /* Find an empty TxBD */ - for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) { - if (i > 0x100000) { - printf("%s: tx buffer not ready\n", dev->name); - return result; - } - } - - /* Init TxBD */ - BD_DATA_SET(bd, buf); - BD_LENGTH_SET(bd, len); - status = BD_STATUS(bd); - status &= BD_WRAP; - status |= (TX_BD_READY | TX_BD_LAST); - BD_STATUS_SET(bd, status); - - /* Tell UCC to transmit the buffer */ - ucc_fast_transmit_on_demand(uccf); - - /* Wait for buffer to be transmitted */ - for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) { - if (i > 0x100000) { - printf("%s: tx error\n", dev->name); - return result; - } - } - - /* Ok, the buffer be transimitted */ - BD_ADVANCE(bd, status, uec->p_tx_bd_ring); - uec->tx_bd = bd; - result = 1; - - return result; -} - -static int uec_recv(struct eth_device *dev) -{ - struct uec_priv *uec = dev->priv; - struct buffer_descriptor *bd; - u16 status; - u16 len; - u8 *data; - - bd = uec->rx_bd; - status = BD_STATUS(bd); - - while (!(status & RX_BD_EMPTY)) { - if (!(status & RX_BD_ERROR)) { - data = BD_DATA(bd); - len = BD_LENGTH(bd); - net_process_received_packet(data, len); - } else { - printf("%s: Rx error\n", dev->name); - } - status &= BD_CLEAN; - BD_LENGTH_SET(bd, 0); - BD_STATUS_SET(bd, status | RX_BD_EMPTY); - BD_ADVANCE(bd, status, uec->p_rx_bd_ring); - status = BD_STATUS(bd); - } - uec->rx_bd = bd; - - return 1; -} - -int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info) -{ - struct eth_device *dev; - int i; - struct uec_priv *uec; - int err; - - dev = (struct eth_device *)malloc(sizeof(struct eth_device)); - if (!dev) - return 0; - memset(dev, 0, sizeof(struct eth_device)); - - /* Allocate the UEC private struct */ - uec = (struct uec_priv *)malloc(sizeof(struct uec_priv)); - if (!uec) - return -ENOMEM; - - memset(uec, 0, sizeof(struct uec_priv)); - - /* Adjust uec_info */ -#if (MAX_QE_RISC == 4) - uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS; - uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS; -#endif - - devlist[uec_info->uf_info.ucc_num] = dev; - - uec->uec_info = uec_info; - uec->dev = dev; - - sprintf(dev->name, "UEC%d", uec_info->uf_info.ucc_num); - dev->iobase = 0; - dev->priv = (void *)uec; - dev->init = uec_init; - dev->halt = uec_halt; - dev->send = uec_send; - dev->recv = uec_recv; - - /* Clear the ethnet address */ - for (i = 0; i < 6; i++) - dev->enetaddr[i] = 0; - - eth_register(dev); - - err = uec_startup(uec); - if (err) { - printf("%s: Cannot configure net device, aborting.", dev->name); - return err; - } - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = uec_miiphy_read; - mdiodev->write = uec_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - - return 1; -} - -int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num) -{ - int i; - - for (i = 0; i < num; i++) - uec_initialize(bis, &uecs[i]); - - return 0; -} - -int uec_standard_init(struct bd_info *bis) -{ - return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info)); -} -#endif diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h deleted file mode 100644 index 63371e71bf..0000000000 --- a/drivers/qe/uec.h +++ /dev/null @@ -1,692 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. - * - * Dave Liu - * based on source code of Shlomi Gridish - */ - -#ifndef __UEC_H__ -#define __UEC_H__ - -#include "uccf.h" -#include -#include - -#define MAX_TX_THREADS 8 -#define MAX_RX_THREADS 8 -#define MAX_TX_QUEUES 8 -#define MAX_RX_QUEUES 8 -#define MAX_PREFETCHED_BDS 4 -#define MAX_IPH_OFFSET_ENTRY 8 -#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 -#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 - -/* UEC UPSMR (Protocol Specific Mode Register) - */ -#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ -#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ -#define UPSMR_PRO 0x00400000 /* Promiscuous */ -#define UPSMR_CAP 0x00200000 /* CAM polarity */ -#define UPSMR_RSH 0x00100000 /* Receive Short Frames */ -#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ -#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ -#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ -#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ -#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ -#define UPSMR_CAM 0x00000400 /* CAM Address Matching */ -#define UPSMR_BRO 0x00000200 /* Broadcast Address */ -#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ -#define UPSMR_SGMM 0x00000020 /* SGMII mode */ - -#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) - -/* UEC MACCFG1 (MAC Configuration 1 Register) - */ -#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ -#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ -#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ -#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ -#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ -#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ - -#define MACCFG1_INIT_VALUE (0) - -/* UEC MACCFG2 (MAC Configuration 2 Register) - */ -#define MACCFG2_PREL 0x00007000 -#define MACCFG2_PREL_SHIFT (31 - 19) -#define MACCFG2_PREL_MASK 0x0000f000 -#define MACCFG2_SRP 0x00000080 -#define MACCFG2_STP 0x00000040 -#define MACCFG2_RESERVED_1 0x00000020 /* must be set */ -#define MACCFG2_LC 0x00000010 /* Length Check */ -#define MACCFG2_MPE 0x00000008 -#define MACCFG2_FDX 0x00000001 /* Full Duplex */ -#define MACCFG2_FDX_MASK 0x00000001 -#define MACCFG2_PAD_CRC 0x00000004 -#define MACCFG2_CRC_EN 0x00000002 -#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 -#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 -#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 -#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 -#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 -#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 - -#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ - MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) - -/* UEC Event Register */ -#define UCCE_MPD 0x80000000 -#define UCCE_SCAR 0x40000000 -#define UCCE_GRA 0x20000000 -#define UCCE_CBPR 0x10000000 -#define UCCE_BSY 0x08000000 -#define UCCE_RXC 0x04000000 -#define UCCE_TXC 0x02000000 -#define UCCE_TXE 0x01000000 -#define UCCE_TXB7 0x00800000 -#define UCCE_TXB6 0x00400000 -#define UCCE_TXB5 0x00200000 -#define UCCE_TXB4 0x00100000 -#define UCCE_TXB3 0x00080000 -#define UCCE_TXB2 0x00040000 -#define UCCE_TXB1 0x00020000 -#define UCCE_TXB0 0x00010000 -#define UCCE_RXB7 0x00008000 -#define UCCE_RXB6 0x00004000 -#define UCCE_RXB5 0x00002000 -#define UCCE_RXB4 0x00001000 -#define UCCE_RXB3 0x00000800 -#define UCCE_RXB2 0x00000400 -#define UCCE_RXB1 0x00000200 -#define UCCE_RXB0 0x00000100 -#define UCCE_RXF7 0x00000080 -#define UCCE_RXF6 0x00000040 -#define UCCE_RXF5 0x00000020 -#define UCCE_RXF4 0x00000010 -#define UCCE_RXF3 0x00000008 -#define UCCE_RXF2 0x00000004 -#define UCCE_RXF1 0x00000002 -#define UCCE_RXF0 0x00000001 - -#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ - UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) -#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ - UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) -#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ - UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) -#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ - UCCE_RXC | UCCE_TXC | UCCE_TXE) - -/* UEC TEMODR Register */ -#define TEMODER_SCHEDULER_ENABLE 0x2000 -#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 -#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 -#define TEMODER_RMON_STATISTICS 0x0100 -#define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15) - -#define TEMODER_INIT_VALUE 0xc000 - -/* UEC REMODR Register */ -#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 -#define REMODER_RX_EXTENDED_FEATURES 0x80000000 -#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9) -#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10) -#define REMODER_RX_QOS_MODE_SHIFT (31 - 15) -#define REMODER_RMON_STATISTICS 0x00001000 -#define REMODER_RX_EXTENDED_FILTERING 0x00000800 -#define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23) -#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 -#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 -#define REMODER_IP_CHECKSUM_CHECK 0x00000002 -#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 - -#define REMODER_INIT_VALUE 0 - -/* BMRx - Bus Mode Register */ -#define BMR_GLB 0x20 -#define BMR_BO_BE 0x10 -#define BMR_DTB_SECONDARY_BUS 0x02 -#define BMR_BDB_SECONDARY_BUS 0x01 - -#define BMR_SHIFT 24 -#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) - -/* UEC UCCS (Ethernet Status Register) - */ -#define UCCS_BPR 0x02 -#define UCCS_PAU 0x02 -#define UCCS_MPD 0x01 - -/* UEC MIIMCFG (MII Management Configuration Register) - */ -#define MIIMCFG_RESET_MANAGEMENT 0x80000000 -#define MIIMCFG_NO_PREAMBLE 0x00000010 -#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) -#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 -#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 - -#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ - MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 - -/* UEC MIIMCOM (MII Management Command Register) - */ -#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ -#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ - -/* UEC MIIMADD (MII Management Address Register) - */ -#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) -#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) - -/* UEC MIIMCON (MII Management Control Register) - */ -#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) -#define MIIMCON_PHY_STATUS_SHIFT (31 - 31) - -/* UEC MIIMIND (MII Management Indicator Register) - */ -#define MIIMIND_NOT_VALID 0x00000004 -#define MIIMIND_SCAN 0x00000002 -#define MIIMIND_BUSY 0x00000001 - -/* UEC UTBIPAR (Ten Bit Interface Physical Address Register) - */ -#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) -#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f - -/* UEC UESCR (Ethernet Statistics Control Register) - */ -#define UESCR_AUTOZ 0x8000 -#define UESCR_CLRCNT 0x4000 -#define UESCR_MAXCOV_SHIFT (15 - 7) -#define UESCR_SCOV_SHIFT (15 - 15) - -/****** Tx data struct collection ******/ -/* Tx thread data, each Tx thread has one this struct. */ -struct uec_thread_data_tx { - u8 res0[136]; -} __packed; - -/* Tx thread parameter, each Tx thread has one this struct. */ -struct uec_thread_tx_pram { - u8 res0[64]; -} __packed; - -/* Send queue queue-descriptor, each Tx queue has one this QD */ -struct uec_send_queue_qd { - u32 bd_ring_base; /* pointer to BD ring base address */ - u8 res0[0x8]; - u32 last_bd_completed_address; /* last entry in BD ring */ - u8 res1[0x30]; -} __packed; - -/* Send queue memory region */ -struct uec_send_queue_mem_region { - struct uec_send_queue_qd sqqd[MAX_TX_QUEUES]; -} __packed; - -/* Scheduler struct */ -struct uec_scheduler { - u16 cpucount0; /* CPU packet counter */ - u16 cpucount1; /* CPU packet counter */ - u16 cecount0; /* QE packet counter */ - u16 cecount1; /* QE packet counter */ - u16 cpucount2; /* CPU packet counter */ - u16 cpucount3; /* CPU packet counter */ - u16 cecount2; /* QE packet counter */ - u16 cecount3; /* QE packet counter */ - u16 cpucount4; /* CPU packet counter */ - u16 cpucount5; /* CPU packet counter */ - u16 cecount4; /* QE packet counter */ - u16 cecount5; /* QE packet counter */ - u16 cpucount6; /* CPU packet counter */ - u16 cpucount7; /* CPU packet counter */ - u16 cecount6; /* QE packet counter */ - u16 cecount7; /* QE packet counter */ - u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ - u32 rtsrshadow; /* temporary variable handled by QE */ - u32 time; /* temporary variable handled by QE */ - u32 ttl; /* temporary variable handled by QE */ - u32 mblinterval; /* max burst length interval */ - u16 nortsrbytetime; /* normalized value of byte time in tsr units */ - u8 fracsiz; - u8 res0[1]; - u8 strictpriorityq; /* Strict Priority Mask register */ - u8 txasap; /* Transmit ASAP register */ - u8 extrabw; /* Extra BandWidth register */ - u8 oldwfqmask; /* temporary variable handled by QE */ - u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ - u32 minw; /* temporary variable handled by QE */ - u8 res1[0x70 - 0x64]; -} __packed; - -/* Tx firmware counters */ -struct uec_tx_firmware_statistics_pram { - u32 sicoltx; /* single collision */ - u32 mulcoltx; /* multiple collision */ - u32 latecoltxfr; /* late collision */ - u32 frabortduecol; /* frames aborted due to tx collision */ - u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ - u32 carriersenseertx; /* carrier sense error */ - u32 frtxok; /* frames transmitted OK */ - u32 txfrexcessivedefer; - u32 txpkts256; /* total packets(including bad) 256~511 B */ - u32 txpkts512; /* total packets(including bad) 512~1023B */ - u32 txpkts1024; /* total packets(including bad) 1024~1518B */ - u32 txpktsjumbo; /* total packets(including bad) >1024 */ -} __packed; - -/* Tx global parameter table */ -struct uec_tx_global_pram { - u16 temoder; - u8 res0[0x38 - 0x02]; - u32 sqptr; - u32 schedulerbasepointer; - u32 txrmonbaseptr; - u32 tstate; - u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; - u32 vtagtable[0x8]; - u32 tqptr; - u8 res2[0x80 - 0x74]; -} __packed; - -/****** Rx data struct collection ******/ -/* Rx thread data, each Rx thread has one this struct. */ -struct uec_thread_data_rx { - u8 res0[40]; -} __packed; - -/* Rx thread parameter, each Rx thread has one this struct. */ -struct uec_thread_rx_pram { - u8 res0[128]; -} __packed; - -/* Rx firmware counters */ -struct uec_rx_firmware_statistics_pram { - u32 frrxfcser; /* frames with crc error */ - u32 fraligner; /* frames with alignment error */ - u32 inrangelenrxer; /* in range length error */ - u32 outrangelenrxer; /* out of range length error */ - u32 frtoolong; /* frame too long */ - u32 runt; /* runt */ - u32 verylongevent; /* very long event */ - u32 symbolerror; /* symbol error */ - u32 dropbsy; /* drop because of BD not ready */ - u8 res0[0x8]; - u32 mismatchdrop; /* drop because of MAC filtering */ - u32 underpkts; /* total frames less than 64 octets */ - u32 pkts256; /* total frames(including bad)256~511 B */ - u32 pkts512; /* total frames(including bad)512~1023 B */ - u32 pkts1024; /* total frames(including bad)1024~1518 B */ - u32 pktsjumbo; /* total frames(including bad) >1024 B */ - u32 frlossinmacer; - u32 pausefr; /* pause frames */ - u8 res1[0x4]; - u32 removevlan; - u32 replacevlan; - u32 insertvlan; -} __packed; - -/* Rx interrupt coalescing entry, each Rx queue has one this entry. */ -struct uec_rx_interrupt_coalescing_entry { - u32 maxvalue; - u32 counter; -} __packed; - -struct uec_rx_interrupt_coalescing_table { - struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES]; -} __packed; - -/* RxBD queue entry, each Rx queue has one this entry. */ -struct uec_rx_bd_queues_entry { - u32 bdbaseptr; /* BD base pointer */ - u32 bdptr; /* BD pointer */ - u32 externalbdbaseptr; /* external BD base pointer */ - u32 externalbdptr; /* external BD pointer */ -} __packed; - -/* Rx global parameter table */ -struct uec_rx_global_pram { - u32 remoder; /* ethernet mode reg. */ - u32 rqptr; /* base pointer to the Rx Queues */ - u32 res0[0x1]; - u8 res1[0x20 - 0xc]; - u16 typeorlen; - u8 res2[0x1]; - u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ - u32 rxrmonbaseptr; /* Rx RMON statistics base */ - u8 res3[0x30 - 0x28]; - u32 intcoalescingptr; /* Interrupt coalescing table pointer */ - u8 res4[0x36 - 0x34]; - u8 rstate; - u8 res5[0x46 - 0x37]; - u16 mrblr; /* max receive buffer length reg. */ - u32 rbdqptr; /* RxBD parameter table description */ - u16 mflr; /* max frame length reg. */ - u16 minflr; /* min frame length reg. */ - u16 maxd1; /* max dma1 length reg. */ - u16 maxd2; /* max dma2 length reg. */ - u32 ecamptr; /* external CAM address */ - u32 l2qt; /* VLAN priority mapping table. */ - u32 l3qt[0x8]; /* IP priority mapping table. */ - u16 vlantype; /* vlan type */ - u16 vlantci; /* default vlan tci */ - u8 addressfiltering[64];/* address filtering data structure */ - u32 exf_global_param; /* extended filtering global parameters */ - u8 res6[0x100 - 0xc4]; /* Initialize to zero */ -} __packed; - -#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 - -/****** UEC common ******/ -/* UCC statistics - hardware counters */ -struct uec_hardware_statistics { - u32 tx64; - u32 tx127; - u32 tx255; - u32 rx64; - u32 rx127; - u32 rx255; - u32 txok; - u16 txcf; - u32 tmca; - u32 tbca; - u32 rxfok; - u32 rxbok; - u32 rbyt; - u32 rmca; - u32 rbca; -} __packed; - -/* InitEnet command parameter */ -struct uec_init_cmd_pram { - u8 resinit0; - u8 resinit1; - u8 resinit2; - u8 resinit3; - u16 resinit4; - u8 res1[0x1]; - u8 largestexternallookupkeysize; - u32 rgftgfrxglobal; - u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ - u8 res2[0x38 - 0x30]; - u32 txglobal; /* tx global */ - u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ - u8 res3[0x1]; -} __packed; - -#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) -#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) - -#define ENET_INIT_PARAM_RISC_MASK 0x0000003f -#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 -#define ENET_INIT_PARAM_SNUM_MASK 0xff000000 -#define ENET_INIT_PARAM_SNUM_SHIFT 24 - -#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 -#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 -#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff -#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 -#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 - -/* structure representing 82xx Address Filtering Enet Address in PRAM */ -struct uec_82xx_enet_addr { - u8 res1[0x2]; - u16 h; /* address (MSB) */ - u16 m; /* address */ - u16 l; /* address (LSB) */ -} __packed; - -/* structure representing 82xx Address Filtering PRAM */ -struct uec_82xx_add_filtering_pram { - u32 iaddr_h; /* individual address filter, high */ - u32 iaddr_l; /* individual address filter, low */ - u32 gaddr_h; /* group address filter, high */ - u32 gaddr_l; /* group address filter, low */ - struct uec_82xx_enet_addr taddr; - struct uec_82xx_enet_addr paddr[4]; - u8 res0[0x40 - 0x38]; -} __packed; - -/* Buffer Descriptor */ -struct buffer_descriptor { - u16 status; - u16 len; - u32 data; -} __packed; - -#define SIZEOFBD sizeof(struct buffer_descriptor) - -/* Common BD flags */ -#define BD_WRAP 0x2000 -#define BD_INT 0x1000 -#define BD_LAST 0x0800 -#define BD_CLEAN 0x3000 - -/* TxBD status flags */ -#define TX_BD_READY 0x8000 -#define TX_BD_PADCRC 0x4000 -#define TX_BD_WRAP BD_WRAP -#define TX_BD_INT BD_INT -#define TX_BD_LAST BD_LAST -#define TX_BD_TXCRC 0x0400 -#define TX_BD_DEF 0x0200 -#define TX_BD_PP 0x0100 -#define TX_BD_LC 0x0080 -#define TX_BD_RL 0x0040 -#define TX_BD_RC 0x003C -#define TX_BD_UNDERRUN 0x0002 -#define TX_BD_TRUNC 0x0001 - -#define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC) - -/* RxBD status flags */ -#define RX_BD_EMPTY 0x8000 -#define RX_BD_OWNER 0x4000 -#define RX_BD_WRAP BD_WRAP -#define RX_BD_INT BD_INT -#define RX_BD_LAST BD_LAST -#define RX_BD_FIRST 0x0400 -#define RX_BD_CMR 0x0200 -#define RX_BD_MISS 0x0100 -#define RX_BD_BCAST 0x0080 -#define RX_BD_MCAST 0x0040 -#define RX_BD_LG 0x0020 -#define RX_BD_NO 0x0010 -#define RX_BD_SHORT 0x0008 -#define RX_BD_CRCERR 0x0004 -#define RX_BD_OVERRUN 0x0002 -#define RX_BD_IPCH 0x0001 - -#define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \ - RX_BD_CRCERR | RX_BD_OVERRUN) - -/* BD access macros */ -#define BD_STATUS(_bd) (in_be16(&((_bd)->status))) -#define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v)) -#define BD_LENGTH(_bd) (in_be16(&((_bd)->len))) -#define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v)) -#define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0)) -#define BD_DATA(_bd) ((u8 *)(((_bd)->data))) -#define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data)) -#define BD_ADVANCE(_bd, _status, _base) \ - (((_status) & BD_WRAP) ? (_bd) = \ - ((struct buffer_descriptor *)(_base)) : ++(_bd)) - -/* Rx Prefetched BDs */ -struct uec_rx_pref_bds { - struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ -} __packed; - -/* Alignments */ -#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 -#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 -#define UEC_THREAD_RX_PRAM_ALIGNMENT 128 -#define UEC_THREAD_TX_PRAM_ALIGNMENT 64 -#define UEC_THREAD_DATA_ALIGNMENT 256 -#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 -#define UEC_SCHEDULER_ALIGNMENT 4 -#define UEC_TX_STATISTICS_ALIGNMENT 4 -#define UEC_RX_STATISTICS_ALIGNMENT 4 -#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 -#define UEC_RX_BD_QUEUES_ALIGNMENT 8 -#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 -#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 -#define UEC_RX_BD_RING_ALIGNMENT 32 -#define UEC_TX_BD_RING_ALIGNMENT 32 -#define UEC_MRBLR_ALIGNMENT 128 -#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 -#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 -#define UEC_RX_DATA_BUF_ALIGNMENT 64 - -#define UEC_VLAN_PRIORITY_MAX 8 -#define UEC_IP_PRIORITY_MAX 64 -#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 -#define UEC_RX_BD_RING_SIZE_MIN 8 -#define UEC_TX_BD_RING_SIZE_MIN 2 - -/* TBI / MII Set Register */ -enum enet_tbi_mii_reg { - ENET_TBI_MII_CR = 0x00, - ENET_TBI_MII_SR = 0x01, - ENET_TBI_MII_ANA = 0x04, - ENET_TBI_MII_ANLPBPA = 0x05, - ENET_TBI_MII_ANEX = 0x06, - ENET_TBI_MII_ANNPT = 0x07, - ENET_TBI_MII_ANLPANP = 0x08, - ENET_TBI_MII_EXST = 0x0F, - ENET_TBI_MII_JD = 0x10, - ENET_TBI_MII_TBICON = 0x11 -}; - -/* TBI MDIO register bit fields*/ -#define TBICON_CLK_SELECT 0x0020 -#define TBIANA_ASYMMETRIC_PAUSE 0x0100 -#define TBIANA_SYMMETRIC_PAUSE 0x0080 -#define TBIANA_HALF_DUPLEX 0x0040 -#define TBIANA_FULL_DUPLEX 0x0020 -#define TBICR_PHY_RESET 0x8000 -#define TBICR_ANEG_ENABLE 0x1000 -#define TBICR_RESTART_ANEG 0x0200 -#define TBICR_FULL_DUPLEX 0x0100 -#define TBICR_SPEED1_SET 0x0040 - -#define TBIANA_SETTINGS ( \ - TBIANA_ASYMMETRIC_PAUSE \ - | TBIANA_SYMMETRIC_PAUSE \ - | TBIANA_FULL_DUPLEX \ - ) - -#define TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -/* UEC number of threads */ -enum uec_num_of_threads { - UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ - UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ - UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ - UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ - UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ -}; - -/* UEC initialization info struct */ -#define STD_UEC_INFO(num) \ -{ \ - .uf_info = { \ - .ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\ - .rx_clock = CFG_SYS_UEC##num##_RX_CLK, \ - .tx_clock = CFG_SYS_UEC##num##_TX_CLK, \ - .eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\ - }, \ - .num_threads_tx = UEC_NUM_OF_THREADS_1, \ - .num_threads_rx = UEC_NUM_OF_THREADS_1, \ - .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ - .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ - .tx_bd_ring_len = 16, \ - .rx_bd_ring_len = 16, \ - .phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \ - .enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \ - .speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \ -} - -struct uec_inf { - struct ucc_fast_inf uf_info; - enum uec_num_of_threads num_threads_tx; - enum uec_num_of_threads num_threads_rx; - unsigned int risc_tx; - unsigned int risc_rx; - u16 rx_bd_ring_len; - u16 tx_bd_ring_len; - u8 phy_address; - phy_interface_t enet_interface_type; - int speed; -}; - -/* UEC driver initialized info */ -#define MAX_RXBUF_LEN 1536 -#define MAX_FRAME_LEN 1518 -#define MIN_FRAME_LEN 64 -#define MAX_DMA1_LEN 1520 -#define MAX_DMA2_LEN 1520 - -/* UEC driver private struct */ -struct uec_priv { - struct uec_inf *uec_info; - struct ucc_fast_priv *uccf; - struct eth_device *dev; - uec_t *uec_regs; - uec_mii_t *uec_mii_regs; - /* enet init command parameter */ - struct uec_init_cmd_pram *p_init_enet_param; - u32 init_enet_param_offset; - /* Rx and Tx parameter */ - struct uec_rx_global_pram *p_rx_glbl_pram; - u32 rx_glbl_pram_offset; - struct uec_tx_global_pram *p_tx_glbl_pram; - u32 tx_glbl_pram_offset; - struct uec_send_queue_mem_region *p_send_q_mem_reg; - u32 send_q_mem_reg_offset; - struct uec_thread_data_tx *p_thread_data_tx; - u32 thread_dat_tx_offset; - struct uec_thread_data_rx *p_thread_data_rx; - u32 thread_dat_rx_offset; - struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl; - u32 rx_bd_qs_tbl_offset; - /* BDs specific */ - u8 *p_tx_bd_ring; - u32 tx_bd_ring_offset; - u8 *p_rx_bd_ring; - u32 rx_bd_ring_offset; - u8 *p_rx_buf; - u32 rx_buf_offset; - struct buffer_descriptor *tx_bd; - struct buffer_descriptor *rx_bd; - /* Status */ - int mac_tx_enabled; - int mac_rx_enabled; - int grace_stopped_tx; - int grace_stopped_rx; - int the_first_run; - /* PHY specific */ - struct uec_mii_info *mii_info; - int oldspeed; - int oldduplex; - int oldlink; -}; - -int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info); -int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num); -int uec_standard_init(struct bd_info *bis); -#endif /* __UEC_H__ */ diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c deleted file mode 100644 index fcf06d1032..0000000000 --- a/drivers/qe/uec_phy.c +++ /dev/null @@ -1,930 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc. - * - * Author: Shlomi Gridish - * - * Description: UCC GETH Driver -- PHY handling - * Driver for UEC on QE - * Based on 8260_io/fcc_enet.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include "uccf.h" -#include "uec.h" -#include "uec_phy.h" -#include "miiphy.h" -#include -#include - -#if !defined(CONFIG_DM_ETH) - -#define ugphy_printk(format, arg...) \ - printf(format "\n", ## arg) - -#define ugphy_dbg(format, arg...) \ - ugphy_printk(format, ## arg) -#define ugphy_err(format, arg...) \ - ugphy_printk(format, ## arg) -#define ugphy_info(format, arg...) \ - ugphy_printk(format, ## arg) -#define ugphy_warn(format, arg...) \ - ugphy_printk(format, ## arg) - -#ifdef UEC_VERBOSE_DEBUG -#define ugphy_vdbg ugphy_dbg -#else -#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) -#endif /* UEC_VERBOSE_DEBUG */ - -/* - * -------------------------------------------------------------------- - * Fixed PHY (PHY-less) support for Ethernet Ports. - * - * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c - *-------------------------------------------------------------------- - * - * Some boards do not have a PHY for each ethernet port. These ports are known - * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate - * CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address) - * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned - * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network - * speed and duplex should be for the port. - * - * Example board header configuration file: - * #define CONFIG_FIXED_PHY 0xFFFFFFFF - * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address) - * - * #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CFG_SYS_UEC2_PHY_ADDR 0x02 - * #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR - * #define CFG_SYS_UEC4_PHY_ADDR 0x04 - * - * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \ - * {name, speed, duplex}, - * - * #define CONFIG_SYS_FIXED_PHY_PORTS \ - * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \ - * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF) - */ - -#ifndef CONFIG_FIXED_PHY -#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ -#endif - -#ifndef CONFIG_SYS_FIXED_PHY_PORTS -#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ -#endif - -struct fixed_phy_port { - char name[16]; /* ethernet port name */ - unsigned int speed; /* specified speed 10,100 or 1000 */ - unsigned int duplex; /* specified duplex FULL or HALF */ -}; - -static const struct fixed_phy_port fixed_phy_port[] = { - CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ -}; - -/* - * ------------------------------------------------------------------- - * BitBang MII support for ethernet ports - * - * Based from MPC8560ADS implementation - *-------------------------------------------------------------------- - * - * Example board header file to define bitbang ethernet ports: - * - * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name, - * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0") - */ -#ifndef CONFIG_SYS_BITBANG_PHY_PORTS -#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */ -#endif - -#if defined(CONFIG_BITBANGMII) -static const char * const bitbang_phy_port[] = { - CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */ -}; -#endif /* CONFIG_BITBANGMII */ - -static void config_genmii_advert(struct uec_mii_info *mii_info); -static void genmii_setup_forced(struct uec_mii_info *mii_info); -static void genmii_restart_aneg(struct uec_mii_info *mii_info); -static int gbit_config_aneg(struct uec_mii_info *mii_info); -static int genmii_config_aneg(struct uec_mii_info *mii_info); -static int genmii_update_link(struct uec_mii_info *mii_info); -static int genmii_read_status(struct uec_mii_info *mii_info); -static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum); -static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, - u16 val); - -/* - * Write value to the PHY for this device to the register at regnum, - * waiting until the write is done before it returns. All PHY - * configuration has to be done through the TSEC1 MIIM regs - */ -void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum, - int value) -{ - struct uec_priv *ugeth = (struct uec_priv *)dev->priv; - uec_mii_t *ug_regs; - enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum; - u32 tmp_reg; - -#if defined(CONFIG_BITBANGMII) - u32 i = 0; - - for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { - if (strncmp(dev->name, bitbang_phy_port[i], - sizeof(dev->name)) == 0) { - (void)bb_miiphy_write(NULL, mii_id, regnum, value); - return; - } - } -#endif /* CONFIG_BITBANGMII */ - - ug_regs = ugeth->uec_mii_regs; - - /* Stop the MII management read cycle */ - out_be32 (&ug_regs->miimcom, 0); - /* Setting up the MII Management Address Register */ - tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; - out_be32 (&ug_regs->miimadd, tmp_reg); - - /* Setting up the MII Management Control Register with the value */ - out_be32 (&ug_regs->miimcon, (u32)value); - sync(); - - /* Wait till MII management write is complete */ - while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY) - ; -} - -/* - * Reads from register regnum in the PHY for device dev, - * returning the value. Clears miimcom first. All PHY - * configuration has to be done through the TSEC1 MIIM regs - */ -int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum) -{ - struct uec_priv *ugeth = (struct uec_priv *)dev->priv; - uec_mii_t *ug_regs; - enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum; - u32 tmp_reg; - u16 value; - -#if defined(CONFIG_BITBANGMII) - u32 i = 0; - - for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { - if (strncmp(dev->name, bitbang_phy_port[i], - sizeof(dev->name)) == 0) { - (void)bb_miiphy_read(NULL, mii_id, regnum, &value); - return value; - } - } -#endif /* CONFIG_BITBANGMII */ - - ug_regs = ugeth->uec_mii_regs; - - /* Setting up the MII Management Address Register */ - tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg; - out_be32 (&ug_regs->miimadd, tmp_reg); - - /* clear MII management command cycle */ - out_be32 (&ug_regs->miimcom, 0); - sync(); - - /* Perform an MII management read cycle */ - out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE); - - /* Wait till MII management write is complete */ - while ((in_be32 (&ug_regs->miimind)) & - (MIIMIND_NOT_VALID | MIIMIND_BUSY)) - ; - - /* Read MII management status */ - value = (u16)in_be32 (&ug_regs->miimstat); - if (value == 0xffff) - ugphy_vdbg - ("read wrong value : mii_id %d,mii_reg %d, base %08x", - mii_id, mii_reg, (u32)&ug_regs->miimcfg); - - return value; -} - -void mii_clear_phy_interrupt(struct uec_mii_info *mii_info) -{ - if (mii_info->phyinfo->ack_interrupt) - mii_info->phyinfo->ack_interrupt(mii_info); -} - -void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, - u32 interrupts) -{ - mii_info->interrupts = interrupts; - if (mii_info->phyinfo->config_intr) - mii_info->phyinfo->config_intr(mii_info); -} - -/* Writes MII_ADVERTISE with the appropriate values, after - * sanitizing advertise to make sure only supported features - * are advertised - */ -static void config_genmii_advert(struct uec_mii_info *mii_info) -{ - u32 advertise; - u16 adv; - - /* Only allow advertising what this PHY supports */ - mii_info->advertising &= mii_info->phyinfo->features; - advertise = mii_info->advertising; - - /* Setup standard advertisement */ - adv = uec_phy_read(mii_info, MII_ADVERTISE); - adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); - if (advertise & ADVERTISED_10baseT_Half) - adv |= ADVERTISE_10HALF; - if (advertise & ADVERTISED_10baseT_Full) - adv |= ADVERTISE_10FULL; - if (advertise & ADVERTISED_100baseT_Half) - adv |= ADVERTISE_100HALF; - if (advertise & ADVERTISED_100baseT_Full) - adv |= ADVERTISE_100FULL; - uec_phy_write(mii_info, MII_ADVERTISE, adv); -} - -static void genmii_setup_forced(struct uec_mii_info *mii_info) -{ - u16 ctrl; - u32 features = mii_info->phyinfo->features; - - ctrl = uec_phy_read(mii_info, MII_BMCR); - - ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | - BMCR_SPEED1000 | BMCR_ANENABLE); - ctrl |= BMCR_RESET; - - switch (mii_info->speed) { - case SPEED_1000: - if (features & (SUPPORTED_1000baseT_Half - | SUPPORTED_1000baseT_Full)) { - ctrl |= BMCR_SPEED1000; - break; - } - mii_info->speed = SPEED_100; - case SPEED_100: - if (features & (SUPPORTED_100baseT_Half - | SUPPORTED_100baseT_Full)) { - ctrl |= BMCR_SPEED100; - break; - } - mii_info->speed = SPEED_10; - case SPEED_10: - if (features & (SUPPORTED_10baseT_Half - | SUPPORTED_10baseT_Full)) - break; - default: /* Unsupported speed! */ - ugphy_err("%s: Bad speed!", mii_info->dev->name); - break; - } - - uec_phy_write(mii_info, MII_BMCR, ctrl); -} - -/* Enable and Restart Autonegotiation */ -static void genmii_restart_aneg(struct uec_mii_info *mii_info) -{ - u16 ctl; - - ctl = uec_phy_read(mii_info, MII_BMCR); - ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); - uec_phy_write(mii_info, MII_BMCR, ctl); -} - -static int gbit_config_aneg(struct uec_mii_info *mii_info) -{ - u16 adv; - u32 advertise; - - if (mii_info->autoneg) { - /* Configure the ADVERTISE register */ - config_genmii_advert(mii_info); - advertise = mii_info->advertising; - - adv = uec_phy_read(mii_info, MII_CTRL1000); - adv &= ~(ADVERTISE_1000FULL | - ADVERTISE_1000HALF); - if (advertise & SUPPORTED_1000baseT_Half) - adv |= ADVERTISE_1000HALF; - if (advertise & SUPPORTED_1000baseT_Full) - adv |= ADVERTISE_1000FULL; - uec_phy_write(mii_info, MII_CTRL1000, adv); - - /* Start/Restart aneg */ - genmii_restart_aneg(mii_info); - } else { - genmii_setup_forced(mii_info); - } - - return 0; -} - -static int marvell_config_aneg(struct uec_mii_info *mii_info) -{ - /* - * The Marvell PHY has an errata which requires - * that certain registers get written in order - * to restart autonegotiation - */ - uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); - - uec_phy_write(mii_info, 0x1d, 0x1f); - uec_phy_write(mii_info, 0x1e, 0x200c); - uec_phy_write(mii_info, 0x1d, 0x5); - uec_phy_write(mii_info, 0x1e, 0); - uec_phy_write(mii_info, 0x1e, 0x100); - - gbit_config_aneg(mii_info); - - return 0; -} - -static int genmii_config_aneg(struct uec_mii_info *mii_info) -{ - if (mii_info->autoneg) { - /* - * Speed up the common case, if link is already up, speed and - * duplex match, skip auto neg as it already matches - */ - if (!genmii_read_status(mii_info) && mii_info->link) - if (mii_info->duplex == DUPLEX_FULL && - mii_info->speed == SPEED_100) - if (mii_info->advertising & - ADVERTISED_100baseT_Full) - return 0; - - config_genmii_advert(mii_info); - genmii_restart_aneg(mii_info); - } else { - genmii_setup_forced(mii_info); - } - - return 0; -} - -static int genmii_update_link(struct uec_mii_info *mii_info) -{ - u16 status; - - /* Status is read once to clear old link state */ - uec_phy_read(mii_info, MII_BMSR); - - /* - * Wait if the link is up, and autonegotiation is in progress - * (ie - we're capable and it's not done) - */ - status = uec_phy_read(mii_info, MII_BMSR); - if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) && - !(status & BMSR_ANEGCOMPLETE)) { - int i = 0; - - while (!(status & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > UGETH_AN_TIMEOUT) { - mii_info->link = 0; - return 0; - } - - i++; - udelay(1000); /* 1 ms */ - status = uec_phy_read(mii_info, MII_BMSR); - } - mii_info->link = 1; - } else { - if (status & BMSR_LSTATUS) - mii_info->link = 1; - else - mii_info->link = 0; - } - - return 0; -} - -static int genmii_read_status(struct uec_mii_info *mii_info) -{ - u16 status; - int err; - - /* Update the link, but return if there was an error */ - err = genmii_update_link(mii_info); - if (err) - return err; - - if (mii_info->autoneg) { - status = uec_phy_read(mii_info, MII_STAT1000); - - if (status & (LPA_1000FULL | LPA_1000HALF)) { - mii_info->speed = SPEED_1000; - if (status & LPA_1000FULL) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - } else { - status = uec_phy_read(mii_info, MII_LPA); - - if (status & (LPA_10FULL | LPA_100FULL)) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - if (status & (LPA_100FULL | LPA_100HALF)) - mii_info->speed = SPEED_100; - else - mii_info->speed = SPEED_10; - } - mii_info->pause = 0; - } - /* On non-aneg, we assume what we put in BMCR is the speed, - * though magic-aneg shouldn't prevent this case from occurring - */ - - return 0; -} - -static int bcm_init(struct uec_mii_info *mii_info) -{ - struct eth_device *edev = mii_info->dev; - struct uec_priv *uec = edev->priv; - - gbit_config_aneg(mii_info); - - if (uec->uec_info->enet_interface_type == - PHY_INTERFACE_MODE_RGMII_RXID && - uec->uec_info->speed == SPEED_1000) { - u16 val; - int cnt = 50; - - /* Wait for aneg to complete. */ - do - val = uec_phy_read(mii_info, MII_BMSR); - while (--cnt && !(val & BMSR_ANEGCOMPLETE)); - - /* Set RDX clk delay. */ - uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12)); - - val = uec_phy_read(mii_info, 0x18); - /* Set RDX-RXC skew. */ - val |= (1 << 8); - val |= (7 | (7 << 12)); - /* Write bits 14:0. */ - val |= (1 << 15); - uec_phy_write(mii_info, 0x18, val); - } - - return 0; -} - -static int uec_marvell_init(struct uec_mii_info *mii_info) -{ - struct eth_device *edev = mii_info->dev; - struct uec_priv *uec = edev->priv; - phy_interface_t iface = uec->uec_info->enet_interface_type; - int speed = uec->uec_info->speed; - - if (speed == SPEED_1000 && - (iface == PHY_INTERFACE_MODE_RGMII_ID || - iface == PHY_INTERFACE_MODE_RGMII_RXID || - iface == PHY_INTERFACE_MODE_RGMII_TXID)) { - int temp; - - temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR); - if (iface == PHY_INTERFACE_MODE_RGMII_ID) { - temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY; - } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) { - temp &= ~MII_M1111_TX_DELAY; - temp |= MII_M1111_RX_DELAY; - } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) { - temp &= ~MII_M1111_RX_DELAY; - temp |= MII_M1111_TX_DELAY; - } - uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp); - - temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR); - temp &= ~MII_M1111_HWCFG_MODE_MASK; - temp |= MII_M1111_HWCFG_MODE_RGMII; - uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp); - - uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); - } - - return 0; -} - -static int marvell_read_status(struct uec_mii_info *mii_info) -{ - u16 status; - int err; - - /* Update the link, but return if there was an error */ - err = genmii_update_link(mii_info); - if (err) - return err; - - /* - * If the link is up, read the speed and duplex - * If we aren't autonegotiating, assume speeds - * are as set - */ - if (mii_info->autoneg && mii_info->link) { - int speed; - - status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); - - /* Get the duplexity */ - if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - - /* Get the speed */ - speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK; - switch (speed) { - case MII_M1011_PHY_SPEC_STATUS_1000: - mii_info->speed = SPEED_1000; - break; - case MII_M1011_PHY_SPEC_STATUS_100: - mii_info->speed = SPEED_100; - break; - default: - mii_info->speed = SPEED_10; - break; - } - mii_info->pause = 0; - } - - return 0; -} - -static int marvell_ack_interrupt(struct uec_mii_info *mii_info) -{ - /* Clear the interrupts by reading the reg */ - uec_phy_read(mii_info, MII_M1011_IEVENT); - - return 0; -} - -static int marvell_config_intr(struct uec_mii_info *mii_info) -{ - if (mii_info->interrupts == MII_INTERRUPT_ENABLED) - uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); - else - uec_phy_write(mii_info, MII_M1011_IMASK, - MII_M1011_IMASK_CLEAR); - - return 0; -} - -static int dm9161_init(struct uec_mii_info *mii_info) -{ - /* Reset the PHY */ - uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) | - BMCR_RESET); - /* PHY and MAC connect */ - uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) & - ~BMCR_ISOLATE); - - uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT); - - config_genmii_advert(mii_info); - /* Start/restart aneg */ - genmii_config_aneg(mii_info); - - return 0; -} - -static int dm9161_config_aneg(struct uec_mii_info *mii_info) -{ - return 0; -} - -static int dm9161_read_status(struct uec_mii_info *mii_info) -{ - u16 status; - int err; - - /* Update the link, but return if there was an error */ - err = genmii_update_link(mii_info); - if (err) - return err; - /* - * If the link is up, read the speed and duplex - * If we aren't autonegotiating assume speeds are as set - */ - if (mii_info->autoneg && mii_info->link) { - status = uec_phy_read(mii_info, MII_DM9161_SCSR); - if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) - mii_info->speed = SPEED_100; - else - mii_info->speed = SPEED_10; - - if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F)) - mii_info->duplex = DUPLEX_FULL; - else - mii_info->duplex = DUPLEX_HALF; - } - - return 0; -} - -static int dm9161_ack_interrupt(struct uec_mii_info *mii_info) -{ - /* Clear the interrupt by reading the reg */ - uec_phy_read(mii_info, MII_DM9161_INTR); - - return 0; -} - -static int dm9161_config_intr(struct uec_mii_info *mii_info) -{ - if (mii_info->interrupts == MII_INTERRUPT_ENABLED) - uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); - else - uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); - - return 0; -} - -static void dm9161_close(struct uec_mii_info *mii_info) -{ -} - -static int fixed_phy_aneg(struct uec_mii_info *mii_info) -{ - mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */ - return 0; -} - -static int fixed_phy_read_status(struct uec_mii_info *mii_info) -{ - int i = 0; - - for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { - if (strncmp(mii_info->dev->name, fixed_phy_port[i].name, - strlen(mii_info->dev->name)) == 0) { - mii_info->speed = fixed_phy_port[i].speed; - mii_info->duplex = fixed_phy_port[i].duplex; - mii_info->link = 1; /* Link is always UP */ - mii_info->pause = 0; - break; - } - } - return 0; -} - -static int smsc_config_aneg(struct uec_mii_info *mii_info) -{ - return 0; -} - -static int smsc_read_status(struct uec_mii_info *mii_info) -{ - u16 status; - int err; - - /* Update the link, but return if there was an error */ - err = genmii_update_link(mii_info); - if (err) - return err; - - /* - * If the link is up, read the speed and duplex - * If we aren't autonegotiating, assume speeds - * are as set - */ - if (mii_info->autoneg && mii_info->link) { - int val; - - status = uec_phy_read(mii_info, 0x1f); - val = (status & 0x1c) >> 2; - - switch (val) { - case 1: - mii_info->duplex = DUPLEX_HALF; - mii_info->speed = SPEED_10; - break; - case 5: - mii_info->duplex = DUPLEX_FULL; - mii_info->speed = SPEED_10; - break; - case 2: - mii_info->duplex = DUPLEX_HALF; - mii_info->speed = SPEED_100; - break; - case 6: - mii_info->duplex = DUPLEX_FULL; - mii_info->speed = SPEED_100; - break; - } - mii_info->pause = 0; - } - - return 0; -} - -static struct phy_info phy_info_dm9161 = { - .phy_id = 0x0181b880, - .phy_id_mask = 0x0ffffff0, - .name = "Davicom DM9161E", - .init = dm9161_init, - .config_aneg = dm9161_config_aneg, - .read_status = dm9161_read_status, - .close = dm9161_close, -}; - -static struct phy_info phy_info_dm9161a = { - .phy_id = 0x0181b8a0, - .phy_id_mask = 0x0ffffff0, - .name = "Davicom DM9161A", - .features = MII_BASIC_FEATURES, - .init = dm9161_init, - .config_aneg = dm9161_config_aneg, - .read_status = dm9161_read_status, - .ack_interrupt = dm9161_ack_interrupt, - .config_intr = dm9161_config_intr, - .close = dm9161_close, -}; - -static struct phy_info phy_info_marvell = { - .phy_id = 0x01410c00, - .phy_id_mask = 0xffffff00, - .name = "Marvell 88E11x1", - .features = MII_GBIT_FEATURES, - .init = &uec_marvell_init, - .config_aneg = &marvell_config_aneg, - .read_status = &marvell_read_status, - .ack_interrupt = &marvell_ack_interrupt, - .config_intr = &marvell_config_intr, -}; - -static struct phy_info phy_info_bcm5481 = { - .phy_id = 0x0143bca0, - .phy_id_mask = 0xffffff0, - .name = "Broadcom 5481", - .features = MII_GBIT_FEATURES, - .read_status = genmii_read_status, - .init = bcm_init, -}; - -static struct phy_info phy_info_fixedphy = { - .phy_id = CONFIG_FIXED_PHY, - .phy_id_mask = CONFIG_FIXED_PHY, - .name = "Fixed PHY", - .config_aneg = fixed_phy_aneg, - .read_status = fixed_phy_read_status, -}; - -static struct phy_info phy_info_smsclan8700 = { - .phy_id = 0x0007c0c0, - .phy_id_mask = 0xfffffff0, - .name = "SMSC LAN8700", - .features = MII_BASIC_FEATURES, - .config_aneg = smsc_config_aneg, - .read_status = smsc_read_status, -}; - -static struct phy_info phy_info_genmii = { - .phy_id = 0x00000000, - .phy_id_mask = 0x00000000, - .name = "Generic MII", - .features = MII_BASIC_FEATURES, - .config_aneg = genmii_config_aneg, - .read_status = genmii_read_status, -}; - -static struct phy_info *phy_info[] = { - &phy_info_dm9161, - &phy_info_dm9161a, - &phy_info_marvell, - &phy_info_bcm5481, - &phy_info_smsclan8700, - &phy_info_fixedphy, - &phy_info_genmii, - NULL -}; - -static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum) -{ - return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); -} - -static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val) -{ - mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val); -} - -/* Use the PHY ID registers to determine what type of PHY is attached - * to device dev. return a struct phy_info structure describing that PHY - */ -struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info) -{ - u16 phy_reg; - u32 phy_ID; - int i; - struct phy_info *info = NULL; - - /* Grab the bits from PHYIR1, and put them in the upper half */ - phy_reg = uec_phy_read(mii_info, MII_PHYSID1); - phy_ID = (phy_reg & 0xffff) << 16; - - /* Grab the bits from PHYIR2, and put them in the lower half */ - phy_reg = uec_phy_read(mii_info, MII_PHYSID2); - phy_ID |= (phy_reg & 0xffff); - - /* loop through all the known PHY types, and find one that */ - /* matches the ID we read from the PHY. */ - for (i = 0; phy_info[i]; i++) - if (phy_info[i]->phy_id == - (phy_ID & phy_info[i]->phy_id_mask)) { - info = phy_info[i]; - break; - } - - /* This shouldn't happen, as we have generic PHY support */ - if (!info) { - ugphy_info("UEC: PHY id %x is not supported!", phy_ID); - return NULL; - } - ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID); - - return info; -} - -void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type, - int speed) -{ - struct uec_priv *uec = (struct uec_priv *)dev->priv; - struct uec_mii_info *mii_info; - u16 status; - - if (!uec->mii_info) { - printf("%s: the PHY not initialized\n", __func__); - return; - } - mii_info = uec->mii_info; - - if (type == PHY_INTERFACE_MODE_RGMII) { - if (speed == SPEED_100) { - uec_phy_write(mii_info, 0x00, 0x9140); - uec_phy_write(mii_info, 0x1d, 0x001f); - uec_phy_write(mii_info, 0x1e, 0x200c); - uec_phy_write(mii_info, 0x1d, 0x0005); - uec_phy_write(mii_info, 0x1e, 0x0000); - uec_phy_write(mii_info, 0x1e, 0x0100); - uec_phy_write(mii_info, 0x09, 0x0e00); - uec_phy_write(mii_info, 0x04, 0x01e1); - uec_phy_write(mii_info, 0x00, 0x9140); - uec_phy_write(mii_info, 0x00, 0x1000); - mdelay(100); - uec_phy_write(mii_info, 0x00, 0x2900); - uec_phy_write(mii_info, 0x14, 0x0cd2); - uec_phy_write(mii_info, 0x00, 0xa100); - uec_phy_write(mii_info, 0x09, 0x0000); - uec_phy_write(mii_info, 0x1b, 0x800b); - uec_phy_write(mii_info, 0x04, 0x05e1); - uec_phy_write(mii_info, 0x00, 0xa100); - uec_phy_write(mii_info, 0x00, 0x2100); - mdelay(1000); - } else if (speed == SPEED_10) { - uec_phy_write(mii_info, 0x14, 0x8e40); - uec_phy_write(mii_info, 0x1b, 0x800b); - uec_phy_write(mii_info, 0x14, 0x0c82); - uec_phy_write(mii_info, 0x00, 0x8100); - mdelay(1000); - } - } - - /* handle 88e1111 rev.B2 erratum 5.6 */ - if (mii_info->autoneg) { - status = uec_phy_read(mii_info, MII_BMCR); - uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE); - } - /* now the B2 will correctly report autoneg completion status */ -} - -void change_phy_interface_mode(struct eth_device *dev, - phy_interface_t type, int speed) -{ -#ifdef CONFIG_PHY_MODE_NEED_CHANGE - marvell_phy_interface_mode(dev, type, speed); -#endif -} -#endif diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h deleted file mode 100644 index 7fd0e2c544..0000000000 --- a/drivers/qe/uec_phy.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2005, 2011 Freescale Semiconductor, Inc. - * - * Author: Shlomi Gridish - * - * Description: UCC ethernet driver -- PHY handling - * Driver for UEC on QE - * Based on 8260_io/fcc_enet.c - */ -#ifndef __UEC_PHY_H__ -#define __UEC_PHY_H__ - -#include - -#define MII_end ((u32)-2) -#define MII_read ((u32)-1) - -#define MIIMIND_BUSY 0x00000001 -#define MIIMIND_NOTVALID 0x00000004 - -#define UGETH_AN_TIMEOUT 2000 - -/* Cicada Extended Control Register 1 */ -#define MII_CIS8201_EXT_CON1 0x17 -#define MII_CIS8201_EXTCON1_INIT 0x0000 - -/* Cicada Interrupt Mask Register */ -#define MII_CIS8201_IMASK 0x19 -#define MII_CIS8201_IMASK_IEN 0x8000 -#define MII_CIS8201_IMASK_SPEED 0x4000 -#define MII_CIS8201_IMASK_LINK 0x2000 -#define MII_CIS8201_IMASK_DUPLEX 0x1000 -#define MII_CIS8201_IMASK_MASK 0xf000 - -/* Cicada Interrupt Status Register */ -#define MII_CIS8201_ISTAT 0x1a -#define MII_CIS8201_ISTAT_STATUS 0x8000 -#define MII_CIS8201_ISTAT_SPEED 0x4000 -#define MII_CIS8201_ISTAT_LINK 0x2000 -#define MII_CIS8201_ISTAT_DUPLEX 0x1000 - -/* Cicada Auxiliary Control/Status Register */ -#define MII_CIS8201_AUX_CONSTAT 0x1c -#define MII_CIS8201_AUXCONSTAT_INIT 0x0004 -#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020 -#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018 -#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010 -#define MII_CIS8201_AUXCONSTAT_100 0x0008 - -/* 88E1011 PHY Status Register */ -#define MII_M1011_PHY_SPEC_STATUS 0x11 -#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 -#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 -#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 -#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 -#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 -#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400 - -#define MII_M1011_IEVENT 0x13 -#define MII_M1011_IEVENT_CLEAR 0x0000 - -#define MII_M1011_IMASK 0x12 -#define MII_M1011_IMASK_INIT 0x6400 -#define MII_M1011_IMASK_CLEAR 0x0000 - -/* 88E1111 PHY Register */ -#define MII_M1111_PHY_EXT_CR 0x14 -#define MII_M1111_RX_DELAY 0x80 -#define MII_M1111_TX_DELAY 0x2 -#define MII_M1111_PHY_EXT_SR 0x1b -#define MII_M1111_HWCFG_MODE_MASK 0xf -#define MII_M1111_HWCFG_MODE_RGMII 0xb - -#define MII_DM9161_SCR 0x10 -#define MII_DM9161_SCR_INIT 0x0610 -#define MII_DM9161_SCR_RMII_INIT 0x0710 - -/* DM9161 Specified Configuration and Status Register */ -#define MII_DM9161_SCSR 0x11 -#define MII_DM9161_SCSR_100F 0x8000 -#define MII_DM9161_SCSR_100H 0x4000 -#define MII_DM9161_SCSR_10F 0x2000 -#define MII_DM9161_SCSR_10H 0x1000 - -/* DM9161 Interrupt Register */ -#define MII_DM9161_INTR 0x15 -#define MII_DM9161_INTR_PEND 0x8000 -#define MII_DM9161_INTR_DPLX_MASK 0x0800 -#define MII_DM9161_INTR_SPD_MASK 0x0400 -#define MII_DM9161_INTR_LINK_MASK 0x0200 -#define MII_DM9161_INTR_MASK 0x0100 -#define MII_DM9161_INTR_DPLX_CHANGE 0x0010 -#define MII_DM9161_INTR_SPD_CHANGE 0x0008 -#define MII_DM9161_INTR_LINK_CHANGE 0x0004 -#define MII_DM9161_INTR_INIT 0x0000 -#define MII_DM9161_INTR_STOP \ - (MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \ - MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK) - -/* DM9161 10BT Configuration/Status */ -#define MII_DM9161_10BTCSR 0x12 -#define MII_DM9161_10BTCSR_INIT 0x7800 - -#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ - SUPPORTED_10baseT_Full | \ - SUPPORTED_100baseT_Half | \ - SUPPORTED_100baseT_Full | \ - SUPPORTED_Autoneg | \ - SUPPORTED_TP | \ - SUPPORTED_MII) - -#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \ - SUPPORTED_1000baseT_Half | \ - SUPPORTED_1000baseT_Full) - -#define MII_READ_COMMAND 0x00000001 - -#define MII_INTERRUPT_DISABLED 0x0 -#define MII_INTERRUPT_ENABLED 0x1 - -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 - -/* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 - -/* Taken from mii_if_info and sungem_phy.h */ -struct uec_mii_info { - /* Information about the PHY type */ - /* And management functions */ - struct phy_info *phyinfo; - - struct eth_device *dev; - - /* forced speed & duplex (no autoneg) - * partner speed & duplex & pause (autoneg) - */ - int speed; - int duplex; - int pause; - - /* The most recently read link state */ - int link; - - /* Enabled Interrupts */ - u32 interrupts; - - u32 advertising; - int autoneg; - int mii_id; - - /* private data pointer */ - /* For use by PHYs to maintain extra state */ - void *priv; - - /* Provided by ethernet driver */ - int (*mdio_read)(struct eth_device *dev, int mii_id, int reg); - void (*mdio_write)(struct eth_device *dev, int mii_id, int reg, - int val); -}; - -/* struct phy_info: a structure which defines attributes for a PHY - * - * id will contain a number which represents the PHY. During - * startup, the driver will poll the PHY to find out what its - * UID--as defined by registers 2 and 3--is. The 32-bit result - * gotten from the PHY will be ANDed with phy_id_mask to - * discard any bits which may change based on revision numbers - * unimportant to functionality - * - * There are 6 commands which take a ugeth_mii_info structure. - * Each PHY must declare config_aneg, and read_status. - */ -struct phy_info { - u32 phy_id; - char *name; - unsigned int phy_id_mask; - u32 features; - - /* Called to initialize the PHY */ - int (*init)(struct uec_mii_info *mii_info); - - /* Called to suspend the PHY for power */ - int (*suspend)(struct uec_mii_info *mii_info); - - /* Reconfigures autonegotiation (or disables it) */ - int (*config_aneg)(struct uec_mii_info *mii_info); - - /* Determines the negotiated speed and duplex */ - int (*read_status)(struct uec_mii_info *mii_info); - - /* Clears any pending interrupts */ - int (*ack_interrupt)(struct uec_mii_info *mii_info); - - /* Enables or disables interrupts */ - int (*config_intr)(struct uec_mii_info *mii_info); - - /* Clears up any memory if needed */ - void (*close)(struct uec_mii_info *mii_info); -}; - -struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info); -void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum, - int value); -int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum); -void mii_clear_phy_interrupt(struct uec_mii_info *mii_info); -void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, - u32 interrupts); -void change_phy_interface_mode(struct eth_device *dev, - phy_interface_t type, int speed); -#endif /* __UEC_PHY_H__ */ From e524f3a449f58e2ef967fb9b64b01db3d099a27a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 27 Nov 2022 10:25:36 -0500 Subject: [PATCH 112/424] net: Remove eth_legacy.c As there are no more non-DM_ETH cases for networking, remove this legacy file and update the Makefile to match current usage. Signed-off-by: Tom Rini --- boot/bootm.c | 3 - cmd/net.c | 2 - cmd/usb.c | 10 -- drivers/net/Kconfig | 4 + include/net.h | 71 -------- net/Makefile | 10 +- net/eth_internal.h | 4 - net/eth_legacy.c | 426 -------------------------------------------- 8 files changed, 7 insertions(+), 523 deletions(-) delete mode 100644 net/eth_legacy.c diff --git a/boot/bootm.c b/boot/bootm.c index a4c0870c0f..15fce8ad95 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -475,9 +475,6 @@ ulong bootm_disable_interrupts(void) #ifdef CONFIG_NETCONSOLE /* Stop the ethernet stack if NetConsole could have left it up */ eth_halt(); -# ifndef CONFIG_DM_ETH - eth_unregister(eth_get_dev()); -# endif #endif #if defined(CONFIG_CMD_USB) diff --git a/cmd/net.c b/cmd/net.c index 0e9f200ca9..dd50930a36 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -597,7 +597,6 @@ U_BOOT_CMD( #endif /* CONFIG_CMD_LINK_LOCAL */ -#ifdef CONFIG_DM_ETH static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { const struct udevice *current = eth_get_dev(); @@ -640,7 +639,6 @@ U_BOOT_CMD( "NET sub-system", "list - list available devices\n" ); -#endif // CONFIG_DM_ETH #if defined(CONFIG_CMD_NCSI) static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) diff --git a/cmd/usb.c b/cmd/usb.c index 2ba056982c..73addb04c4 100644 --- a/cmd/usb.c +++ b/cmd/usb.c @@ -591,16 +591,6 @@ static void do_usb_start(void) drv_usb_kbd_init(); # endif #endif /* !CONFIG_DM_USB */ -#ifdef CONFIG_USB_HOST_ETHER -# ifdef CONFIG_DM_ETH -# ifndef CONFIG_DM_USB -# error "You must use CONFIG_DM_USB if you want to use CONFIG_USB_HOST_ETHER with CONFIG_DM_ETH" -# endif -# else - /* try to recognize ethernet devices immediately */ - usb_ether_curr_dev = usb_host_eth_scan(1); -# endif -#endif } #ifdef CONFIG_DM_USB diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index db61c27e01..4e5da5ab72 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -15,6 +15,10 @@ config DM_ETH This is currently implemented in net/eth-uclass.c Look in include/net.h for details. +config SPL_DM_ETH + depends on SPL_NET + def_bool y + config DM_MDIO bool "Enable Driver Model for MDIO devices" depends on PHYLIB diff --git a/include/net.h b/include/net.h index 1a99009959..ee08f3307e 100644 --- a/include/net.h +++ b/include/net.h @@ -101,7 +101,6 @@ enum eth_state_t { ETH_STATE_ACTIVE }; -#ifdef CONFIG_DM_ETH /** * struct eth_pdata - Platform data for Ethernet MAC controllers * @@ -180,76 +179,6 @@ unsigned char *eth_get_ethaddr(void); /* get the current device MAC */ int eth_is_active(struct udevice *dev); /* Test device for active state */ int eth_init_state_only(void); /* Set active state */ void eth_halt_state_only(void); /* Set passive state */ -#endif - -#ifndef CONFIG_DM_ETH -struct eth_device { -#define ETH_NAME_LEN 20 - char name[ETH_NAME_LEN]; - unsigned char enetaddr[ARP_HLEN]; - phys_addr_t iobase; - int state; - - int (*init)(struct eth_device *eth, struct bd_info *bd); - int (*send)(struct eth_device *, void *packet, int length); - int (*recv)(struct eth_device *); - void (*halt)(struct eth_device *); - int (*mcast)(struct eth_device *, const u8 *enetaddr, int join); - int (*write_hwaddr)(struct eth_device *eth); - struct eth_device *next; - int index; - void *priv; -}; - -int eth_register(struct eth_device *dev);/* Register network device */ -int eth_unregister(struct eth_device *dev);/* Remove network device */ - -extern struct eth_device *eth_current; - -static __always_inline struct eth_device *eth_get_dev(void) -{ - return eth_current; -} -struct eth_device *eth_get_dev_by_name(const char *devname); -struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */ - -/* get the current device MAC */ -static inline unsigned char *eth_get_ethaddr(void) -{ - if (eth_current) - return eth_current->enetaddr; - return NULL; -} - -/* Used only when NetConsole is enabled */ -int eth_is_active(struct eth_device *dev); /* Test device for active state */ -/* Set active state */ -static __always_inline int eth_init_state_only(void) -{ - eth_get_dev()->state = ETH_STATE_ACTIVE; - - return 0; -} -/* Set passive state */ -static __always_inline void eth_halt_state_only(void) -{ - eth_get_dev()->state = ETH_STATE_PASSIVE; -} - -/* - * Set the hardware address for an ethernet interface based on 'eth%daddr' - * environment variable (or just 'ethaddr' if eth_number is 0). - * Args: - * base_name - base name for device (normally "eth") - * eth_number - value of %d (0 for first device of this type) - * Returns: - * 0 is success, non-zero is error status from driver. - */ -int eth_write_hwaddr(struct eth_device *dev, const char *base_name, - int eth_number); - -int usb_eth_initialize(struct bd_info *bi); -#endif int eth_initialize(void); /* Initialize network subsystem */ void eth_try_another(int first_restart); /* Change the device */ diff --git a/net/Makefile b/net/Makefile index 13eef04029..bea000b206 100644 --- a/net/Makefile +++ b/net/Makefile @@ -10,18 +10,14 @@ obj-$(CONFIG_CMD_BOOTP) += bootp.o obj-$(CONFIG_CMD_CDP) += cdp.o obj-$(CONFIG_CMD_DNS) += dns.o obj-$(CONFIG_DM_DSA) += dsa-uclass.o -ifdef CONFIG_DM_ETH -obj-$(CONFIG_NET) += eth-uclass.o +obj-$(CONFIG_$(SPL_)DM_ETH) += eth-uclass.o obj-$(CONFIG_$(SPL_TPL_)BOOTDEV_ETH) += eth_bootdev.o -else -obj-$(CONFIG_NET) += eth_legacy.o -endif obj-$(CONFIG_DM_MDIO) += mdio-uclass.o obj-$(CONFIG_DM_MDIO_MUX) += mdio-mux-uclass.o -obj-$(CONFIG_NET) += eth_common.o +obj-$(CONFIG_$(SPL_)DM_ETH) += eth_common.o obj-$(CONFIG_CMD_LINK_LOCAL) += link_local.o obj-$(CONFIG_IPV6) += ndisc.o -obj-$(CONFIG_NET) += net.o +obj-$(CONFIG_$(SPL_)DM_ETH) += net.o obj-$(CONFIG_IPV6) += net6.o obj-$(CONFIG_CMD_NFS) += nfs.o obj-$(CONFIG_CMD_PING) += ping.o diff --git a/net/eth_internal.h b/net/eth_internal.h index 042e58a99a..0b829a8d38 100644 --- a/net/eth_internal.h +++ b/net/eth_internal.h @@ -29,11 +29,7 @@ int eth_env_set_enetaddr_by_index(const char *base_name, int index, int eth_mac_skip(int index); void eth_current_changed(void); -#ifdef CONFIG_DM_ETH void eth_set_dev(struct udevice *dev); -#else -void eth_set_dev(struct eth_device *dev); -#endif void eth_set_current_to_next(void); #endif diff --git a/net/eth_legacy.c b/net/eth_legacy.c deleted file mode 100644 index 0b282d918b..0000000000 --- a/net/eth_legacy.c +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001-2015 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Joe Hershberger, National Instruments - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "eth_internal.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * CPU and board-specific Ethernet initializations. Aliased function - * signals caller to move on - */ -static int __def_eth_init(struct bd_info *bis) -{ - return -1; -} -int cpu_eth_init(struct bd_info *bis) __attribute__((weak, alias("__def_eth_init"))); -int board_eth_init(struct bd_info *bis) __attribute__((weak, alias("__def_eth_init"))); - -#ifdef CONFIG_API -static struct { - uchar data[PKTSIZE]; - int length; -} eth_rcv_bufs[PKTBUFSRX]; - -static unsigned int eth_rcv_current, eth_rcv_last; -#endif - -static struct eth_device *eth_devices; -struct eth_device *eth_current; - -void eth_set_current_to_next(void) -{ - eth_current = eth_current->next; -} - -void eth_set_dev(struct eth_device *dev) -{ - eth_current = dev; -} - -struct eth_device *eth_get_dev_by_name(const char *devname) -{ - struct eth_device *dev, *target_dev; - - BUG_ON(devname == NULL); - - if (!eth_devices) - return NULL; - - dev = eth_devices; - target_dev = NULL; - do { - if (strcmp(devname, dev->name) == 0) { - target_dev = dev; - break; - } - dev = dev->next; - } while (dev != eth_devices); - - return target_dev; -} - -struct eth_device *eth_get_dev_by_index(int index) -{ - struct eth_device *dev, *target_dev; - - if (!eth_devices) - return NULL; - - dev = eth_devices; - target_dev = NULL; - do { - if (dev->index == index) { - target_dev = dev; - break; - } - dev = dev->next; - } while (dev != eth_devices); - - return target_dev; -} - -int eth_get_dev_index(void) -{ - if (!eth_current) - return -1; - - return eth_current->index; -} - -static int on_ethaddr(const char *name, const char *value, enum env_op op, - int flags) -{ - int index; - struct eth_device *dev; - - if (!eth_devices) - return 0; - - /* look for an index after "eth" */ - index = dectoul(name + 3, NULL); - - dev = eth_devices; - do { - if (dev->index == index) { - switch (op) { - case env_op_create: - case env_op_overwrite: - string_to_enetaddr(value, dev->enetaddr); - eth_write_hwaddr(dev, "eth", dev->index); - break; - case env_op_delete: - memset(dev->enetaddr, 0, ARP_HLEN); - } - } - dev = dev->next; - } while (dev != eth_devices); - - return 0; -} -U_BOOT_ENV_CALLBACK(ethaddr, on_ethaddr); - -int eth_write_hwaddr(struct eth_device *dev, const char *base_name, - int eth_number) -{ - unsigned char env_enetaddr[ARP_HLEN]; - int ret = 0; - - eth_env_get_enetaddr_by_index(base_name, eth_number, env_enetaddr); - - if (!is_zero_ethaddr(env_enetaddr)) { - if (!is_zero_ethaddr(dev->enetaddr) && - memcmp(dev->enetaddr, env_enetaddr, ARP_HLEN)) { - printf("\nWarning: %s MAC addresses don't match:\n", - dev->name); - printf("Address in SROM is %pM\n", - dev->enetaddr); - printf("Address in environment is %pM\n", - env_enetaddr); - } - - memcpy(dev->enetaddr, env_enetaddr, ARP_HLEN); - } else if (is_valid_ethaddr(dev->enetaddr)) { - eth_env_set_enetaddr_by_index(base_name, eth_number, - dev->enetaddr); - } else if (is_zero_ethaddr(dev->enetaddr)) { -#ifdef CONFIG_NET_RANDOM_ETHADDR - net_random_ethaddr(dev->enetaddr); - printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", - dev->name, eth_number, dev->enetaddr); - eth_env_set_enetaddr_by_index("eth", eth_number, - dev->enetaddr); -#else - printf("\nError: %s address not set.\n", - dev->name); - return -EINVAL; -#endif - } - - if (dev->write_hwaddr && !eth_mac_skip(eth_number)) { - if (!is_valid_ethaddr(dev->enetaddr)) { - printf("\nError: %s address %pM illegal value\n", - dev->name, dev->enetaddr); - return -EINVAL; - } - - ret = dev->write_hwaddr(dev); - if (ret) - printf("\nWarning: %s failed to set MAC address\n", - dev->name); - } - - return ret; -} - -int eth_register(struct eth_device *dev) -{ - struct eth_device *d; - static int index; - - assert(strlen(dev->name) < sizeof(dev->name)); - - if (!eth_devices) { - eth_devices = dev; - eth_current = dev; - eth_current_changed(); - } else { - for (d = eth_devices; d->next != eth_devices; d = d->next) - ; - d->next = dev; - } - - dev->state = ETH_STATE_INIT; - dev->next = eth_devices; - dev->index = index++; - - return 0; -} - -int eth_unregister(struct eth_device *dev) -{ - struct eth_device *cur; - - /* No device */ - if (!eth_devices) - return -ENODEV; - - for (cur = eth_devices; cur->next != eth_devices && cur->next != dev; - cur = cur->next) - ; - - /* Device not found */ - if (cur->next != dev) - return -ENODEV; - - cur->next = dev->next; - - if (eth_devices == dev) - eth_devices = dev->next == eth_devices ? NULL : dev->next; - - if (eth_current == dev) { - eth_current = eth_devices; - eth_current_changed(); - } - - return 0; -} - -int eth_initialize(void) -{ - int num_devices = 0; - - eth_devices = NULL; - eth_current = NULL; - eth_common_init(); - /* - * If board-specific initialization exists, call it. - * If not, call a CPU-specific one - */ - if (board_eth_init != __def_eth_init) { - if (board_eth_init(gd->bd) < 0) - printf("Board Net Initialization Failed\n"); - } else if (cpu_eth_init != __def_eth_init) { - if (cpu_eth_init(gd->bd) < 0) - printf("CPU Net Initialization Failed\n"); - } else { - printf("Net Initialization Skipped\n"); - } - - if (!eth_devices) { - log_err("No ethernet found.\n"); - bootstage_error(BOOTSTAGE_ID_NET_ETH_START); - } else { - struct eth_device *dev = eth_devices; - char *ethprime = env_get("ethprime"); - - bootstage_mark(BOOTSTAGE_ID_NET_ETH_INIT); - do { - if (dev->index) - puts(", "); - - printf("%s", dev->name); - - if (ethprime && strcmp(dev->name, ethprime) == 0) { - eth_current = dev; - puts(" [PRIME]"); - } - - if (strchr(dev->name, ' ')) - puts("\nWarning: eth device name has a space!" - "\n"); - - eth_write_hwaddr(dev, "eth", dev->index); - - dev = dev->next; - num_devices++; - } while (dev != eth_devices); - - eth_current_changed(); - putc('\n'); - } - - return num_devices; -} - -/* Multicast. - * mcast_addr: multicast ipaddr from which multicast Mac is made - * join: 1=join, 0=leave. - */ -int eth_mcast_join(struct in_addr mcast_ip, int join) -{ - u8 mcast_mac[ARP_HLEN]; - if (!eth_current || !eth_current->mcast) - return -1; - mcast_mac[5] = htonl(mcast_ip.s_addr) & 0xff; - mcast_mac[4] = (htonl(mcast_ip.s_addr)>>8) & 0xff; - mcast_mac[3] = (htonl(mcast_ip.s_addr)>>16) & 0x7f; - mcast_mac[2] = 0x5e; - mcast_mac[1] = 0x0; - mcast_mac[0] = 0x1; - return eth_current->mcast(eth_current, mcast_mac, join); -} - -int eth_init(void) -{ - struct eth_device *old_current; - - if (!eth_current) { - log_err("No ethernet found.\n"); - return -ENODEV; - } - - old_current = eth_current; - do { - debug("Trying %s\n", eth_current->name); - - if (eth_current->init(eth_current, gd->bd) >= 0) { - eth_current->state = ETH_STATE_ACTIVE; - - return 0; - } - debug("FAIL\n"); - - eth_try_another(0); - } while (old_current != eth_current); - - return -ETIMEDOUT; -} - -void eth_halt(void) -{ - if (!eth_current) - return; - - eth_current->halt(eth_current); - - eth_current->state = ETH_STATE_PASSIVE; -} - -int eth_is_active(struct eth_device *dev) -{ - return dev && dev->state == ETH_STATE_ACTIVE; -} - -int eth_send(void *packet, int length) -{ - int ret; - - if (!eth_current) - return -ENODEV; - - ret = eth_current->send(eth_current, packet, length); -#if defined(CONFIG_CMD_PCAP) - if (ret >= 0) - pcap_post(packet, length, true); -#endif - return ret; -} - -int eth_rx(void) -{ - if (!eth_current) - return -ENODEV; - - return eth_current->recv(eth_current); -} - -#ifdef CONFIG_API -static void eth_save_packet(void *packet, int length) -{ - char *p = packet; - int i; - - if ((eth_rcv_last+1) % PKTBUFSRX == eth_rcv_current) - return; - - if (PKTSIZE < length) - return; - - for (i = 0; i < length; i++) - eth_rcv_bufs[eth_rcv_last].data[i] = p[i]; - - eth_rcv_bufs[eth_rcv_last].length = length; - eth_rcv_last = (eth_rcv_last + 1) % PKTBUFSRX; -} - -int eth_receive(void *packet, int length) -{ - char *p = packet; - void *pp = push_packet; - int i; - - if (eth_rcv_current == eth_rcv_last) { - push_packet = eth_save_packet; - eth_rx(); - push_packet = pp; - - if (eth_rcv_current == eth_rcv_last) - return -1; - } - - length = min(eth_rcv_bufs[eth_rcv_current].length, length); - - for (i = 0; i < length; i++) - p[i] = eth_rcv_bufs[eth_rcv_current].data[i]; - - eth_rcv_current = (eth_rcv_current + 1) % PKTBUFSRX; - return length; -} -#endif /* CONFIG_API */ From c059a22b7776dc4306acb73cbeb78e841cf60b84 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 13 Oct 2022 17:41:21 +0900 Subject: [PATCH 113/424] tools: env: fw_env: Fix unused-result warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix unused-result warning about fread. tools/env/fw_env.c: In function ‘find_nvmem_device’: tools/env/fw_env.c:1751:3: warning: ignoring return value of ‘fread’, declared with attribute warn_unused_result [-Wunused-result] 1751 | fread(buf, sizeof(buf), 1, fp); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Jaehoon Chung --- tools/env/fw_env.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index c251e2e6ba..c9a8774ace 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1733,6 +1733,7 @@ static int find_nvmem_device(void) while (!nvmem && (dent = readdir(dir))) { FILE *fp; + size_t size; if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) { continue; @@ -1748,7 +1749,14 @@ static int find_nvmem_device(void) continue; } - fread(buf, sizeof(buf), 1, fp); + size = fread(buf, sizeof(buf), 1, fp); + if (size != 1) { + fprintf(stderr, + "read failed about %s\n", comp); + fclose(fp); + return -EIO; + } + if (!strcmp(buf, "u-boot,env")) { bytes = asprintf(&nvmem, "%s/%s/nvmem", path, dent->d_name); From 164232943c77409921f0d1add63d1e41f0460715 Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Fri, 18 Nov 2022 11:50:02 +0300 Subject: [PATCH 114/424] tool: ifwitool: The function localtime() can return NULL. This will cause the local_time pointer is passed as the 4th argument to function strftime() to also point to NULL. This result in a segmentation fault. Thus, it's necessary to add a check of the local_time pointer to NULL. Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Mikhail Ilin Reviewed-by: Simon Glass --- tools/ifwitool.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/ifwitool.c b/tools/ifwitool.c index b2b06cc921..a06eb7f33d 100644 --- a/tools/ifwitool.c +++ b/tools/ifwitool.c @@ -1628,6 +1628,8 @@ static void init_manifest_header(struct manifest_header *hdr, size_t size) curr_time = time(NULL); local_time = localtime(&curr_time); + assert(local_time != NULL); + strftime(buffer, sizeof(buffer), "0x%Y%m%d", local_time); hdr->date = strtoul(buffer, NULL, 16); From 2d1b2ac13fe5be6aa149e7a8ab5b059f0ad05476 Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Fri, 18 Nov 2022 14:50:24 +0300 Subject: [PATCH 115/424] tool: ifwitool: Fix buffer overflow An incorrect 1st parameter is passed to the fix_member() function. Should use a pointer to the beginning of the parent structure (bpdt or subpart_dir, because are boxed), not to their fields. Otherwise, this leads to an overrun of the structure boundary, since in the fix_member() function, an 'offset' is made, relative to the 1st argument, which itself is an 'offset' from the beginning of the structure. Signed-off-by: Mikhail Ilin Reviewed-by: Simon Glass --- tools/ifwitool.c | 44 +++++++++++++++++++------------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/tools/ifwitool.c b/tools/ifwitool.c index a06eb7f33d..31591863b2 100644 --- a/tools/ifwitool.c +++ b/tools/ifwitool.c @@ -1441,23 +1441,20 @@ static void bpdt_fixup_write_buffer(struct buffer *buf) size_t offset = 0; - offset = fix_member(&h->signature, offset, sizeof(h->signature)); - offset = fix_member(&h->descriptor_count, offset, - sizeof(h->descriptor_count)); - offset = fix_member(&h->bpdt_version, offset, sizeof(h->bpdt_version)); - offset = fix_member(&h->xor_redundant_block, offset, - sizeof(h->xor_redundant_block)); - offset = fix_member(&h->ifwi_version, offset, sizeof(h->ifwi_version)); - offset = fix_member(&h->fit_tool_version, offset, - sizeof(h->fit_tool_version)); + offset = fix_member(&s, offset, sizeof(h->signature)); + offset = fix_member(&s, offset, sizeof(h->descriptor_count)); + offset = fix_member(&s, offset, sizeof(h->bpdt_version)); + offset = fix_member(&s, offset, sizeof(h->xor_redundant_block)); + offset = fix_member(&s, offset, sizeof(h->ifwi_version)); + offset = fix_member(&s, offset, sizeof(h->fit_tool_version)); uint32_t i; for (i = 0; i < count; i++) { - offset = fix_member(&e[i].type, offset, sizeof(e[i].type)); - offset = fix_member(&e[i].flags, offset, sizeof(e[i].flags)); - offset = fix_member(&e[i].offset, offset, sizeof(e[i].offset)); - offset = fix_member(&e[i].size, offset, sizeof(e[i].size)); + offset = fix_member(&s, offset, sizeof(e[i].type)); + offset = fix_member(&s, offset, sizeof(e[i].flags)); + offset = fix_member(&s, offset, sizeof(e[i].offset)); + offset = fix_member(&s, offset, sizeof(e[i].size)); } } @@ -1657,24 +1654,21 @@ static void subpart_dir_fixup_write_buffer(struct buffer *buf) size_t count = h->num_entries; size_t offset = 0; - offset = fix_member(&h->marker, offset, sizeof(h->marker)); - offset = fix_member(&h->num_entries, offset, sizeof(h->num_entries)); - offset = fix_member(&h->header_version, offset, - sizeof(h->header_version)); - offset = fix_member(&h->entry_version, offset, - sizeof(h->entry_version)); - offset = fix_member(&h->header_length, offset, - sizeof(h->header_length)); - offset = fix_member(&h->checksum, offset, sizeof(h->checksum)); + offset = fix_member(&s, offset, sizeof(h->marker)); + offset = fix_member(&s, offset, sizeof(h->num_entries)); + offset = fix_member(&s, offset, sizeof(h->header_version)); + offset = fix_member(&s, offset, sizeof(h->entry_version)); + offset = fix_member(&s, offset, sizeof(h->header_length)); + offset = fix_member(&s, offset, sizeof(h->checksum)); offset += sizeof(h->name); uint32_t i; for (i = 0; i < count; i++) { offset += sizeof(e[i].name); - offset = fix_member(&e[i].offset, offset, sizeof(e[i].offset)); - offset = fix_member(&e[i].length, offset, sizeof(e[i].length)); - offset = fix_member(&e[i].rsvd, offset, sizeof(e[i].rsvd)); + offset = fix_member(&s, offset, sizeof(e[i].offset)); + offset = fix_member(&s, offset, sizeof(e[i].length)); + offset = fix_member(&s, offset, sizeof(e[i].rsvd)); } } From 04e6332ec0b139a0b7452551455ae96428c7d1ef Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Tue, 22 Nov 2022 11:00:55 +0300 Subject: [PATCH 116/424] fs: ext4: Fix free(NULL) The 'depth_dirname', 'ptr', 'parent_inode' and 'first_inode' pointers may be null. Thus, it is necessary to check them before using free() to avoid free(NULL) cases. Fixes: 934b14f2bb30 ("ext4: free allocations by parse_path()") Signed-off-by: Mikhail Ilin --- fs/ext4/ext4_common.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 1185cb2c04..f50de7c089 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -850,15 +850,20 @@ end: fail: free(depth_dirname); - free(parse_dirname); - for (i = 0; i < depth; i++) { - if (!ptr[i]) - break; - free(ptr[i]); + if (parse_dirname) + free(parse_dirname); + if (ptr) { + for (i = 0; i < depth; i++) { + if (!ptr[i]) + break; + free(ptr[i]); + } + free(ptr); } - free(ptr); - free(parent_inode); - free(first_inode); + if (parent_inode) + free(parent_inode); + if (first_inode) + free(first_inode); return result_inode_no; } From 17f8a7487689ad727aadc00c14cd3315cd880e4a Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Wed, 23 Nov 2022 12:39:36 +0300 Subject: [PATCH 117/424] tools: mkimage: Fix nullptr at strchr() The copy_datafile(ifd, params.datafile) function has been implemented to copy data by reducing the number of lines in the main function. Signed-off-by: Mikhail Ilin --- tools/mkimage.c | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 30c6df7708..0b5ee5da1e 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -430,6 +430,25 @@ static void verify_image(const struct image_type_params *tparams) (void)close(ifd); } +void copy_datafile(int ifd, char *file) +{ + if (!file) + return; + for (;;) { + char *sep = strchr(file, ':'); + + if (sep) { + *sep = '\0'; + copy_file(ifd, file, 1); + *sep++ = ':'; + file = sep; + } else { + copy_file(ifd, file, 0); + break; + } + } +} + int main(int argc, char **argv) { int ifd = -1; @@ -647,21 +666,7 @@ int main(int argc, char **argv) file = NULL; } } - - file = params.datafile; - - for (;;) { - char *sep = strchr(file, ':'); - if (sep) { - *sep = '\0'; - copy_file (ifd, file, 1); - *sep++ = ':'; - file = sep; - } else { - copy_file (ifd, file, 0); - break; - } - } + copy_datafile(ifd, params.datafile); } else if (params.type == IH_TYPE_PBLIMAGE) { /* PBL has special Image format, implements its' own */ pbl_load_uboot(ifd, ¶ms); From 4b95e8407eba6e6fd73341695de15dec19e723a8 Mon Sep 17 00:00:00 2001 From: Mikhail Ilin Date: Wed, 23 Nov 2022 14:31:03 +0300 Subject: [PATCH 118/424] tools: fdtgrep: Fix handle leak The handle "fd" was created in fdtgrep.c:708 by calling the "open" function and is lost in fdtgrep.c:716 and fdtgrep.c:723. Close file descriptor 'fd' before exiting with an error from function utilfdt_read_err_len(const char *filename, char **buffp, off_t *len). Fixes: 1043d0a0296a ("fdt: Add fdtgrep tool") Signed-off-by: Mikhail Ilin Reviewed-by: Simon Glass --- tools/fdtgrep.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 641d6a2e3e..7eabcab439 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -712,15 +712,19 @@ int utilfdt_read_err_len(const char *filename, char **buffp, off_t *len) /* Loop until we have read everything */ buf = malloc(bufsize); - if (!buf) + if (!buf) { + close(fd); return -ENOMEM; + } do { /* Expand the buffer to hold the next chunk */ if (offset == bufsize) { bufsize *= 2; buf = realloc(buf, bufsize); - if (!buf) + if (!buf) { + close(fd); return -ENOMEM; + } } ret = read(fd, &buf[offset], bufsize - offset); From 72c3f5dbd9545259a7eb04a7d21dff9b318de77e Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 23 Nov 2022 12:55:32 +0100 Subject: [PATCH 119/424] tools: mkimage: don't print error message "Success" in case of failure In case there's no struct image_type_params::set_header callback, no "errno" will be set. Don't fail with an error message, followed by "Success". Remove the printing of the human readable "errno" value. Signed-off-by: Marc Kleine-Budde Reviewed-by: Simon Glass --- tools/mkimage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/mkimage.c b/tools/mkimage.c index 0b5ee5da1e..8306861ce5 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -765,8 +765,8 @@ int main(int argc, char **argv) if (tparams->set_header) tparams->set_header (ptr, &sbuf, ifd, ¶ms); else { - fprintf (stderr, "%s: Can't set header for %s: %s\n", - params.cmdname, tparams->name, strerror(errno)); + fprintf (stderr, "%s: Can't set header for %s\n", + params.cmdname, tparams->name); exit (EXIT_FAILURE); } From 28f924f2650ed2229fd712620c36a41dc0610fcb Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 23 Nov 2022 12:55:33 +0100 Subject: [PATCH 120/424] tools: mkimage: add new image type "fdt_legacy" If the user select the image type "flat_dt" a FIT image will be build. This breaks the legacy use case of putting a Flat Device Tree into a legacy u-boot image. Add a new image type "fdt_legacy" to build a legacy u-boot image with a "flat_dt" type. Link: https://lore.kernel.org/all/20221028155205.ojw6tcso2fofgnhm@pengutronix.de Signed-off-by: Marc Kleine-Budde Reviewed-by: Sean Anderson --- boot/image.c | 1 + include/image.h | 1 + tools/default_image.c | 11 +++++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/boot/image.c b/boot/image.c index b33d1dfc6b..958dbf8534 100644 --- a/boot/image.c +++ b/boot/image.c @@ -180,6 +180,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_COPRO, "copro", "Coprocessor Image"}, { IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" }, { IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image" }, + { IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat Device Tree ", }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 6f21dafba8..b6a809834a 100644 --- a/include/image.h +++ b/include/image.h @@ -229,6 +229,7 @@ enum image_type_t { IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/ IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */ IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */ + IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a Legacy Image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/tools/default_image.c b/tools/default_image.c index 4a067e6586..0ac3382003 100644 --- a/tools/default_image.c +++ b/tools/default_image.c @@ -27,7 +27,8 @@ static struct legacy_img_hdr header; static int image_check_image_types(uint8_t type) { if (((type > IH_TYPE_INVALID) && (type < IH_TYPE_FLATDT)) || - (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT)) + (type == IH_TYPE_KERNEL_NOLOAD) || (type == IH_TYPE_FIRMWARE_IVT) || + (type == IH_TYPE_FDT_LEGACY)) return EXIT_SUCCESS; else return EXIT_FAILURE; @@ -94,6 +95,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, uint32_t imagesize; uint32_t ep; uint32_t addr; + int type; struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)ptr; checksum = crc32(0, @@ -113,6 +115,11 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, else imagesize = sbuf->st_size - sizeof(struct legacy_img_hdr); + if (params->type == IH_TYPE_FDT_LEGACY) + type = IH_TYPE_FLATDT; + else + type = params->type; + if (params->os == IH_OS_TEE) { addr = optee_image_get_load_addr(hdr); ep = optee_image_get_entry_point(hdr); @@ -127,7 +134,7 @@ static void image_set_header(void *ptr, struct stat *sbuf, int ifd, image_set_dcrc(hdr, checksum); image_set_os(hdr, params->os); image_set_arch(hdr, params->arch); - image_set_type(hdr, params->type); + image_set_type(hdr, type); image_set_comp(hdr, params->comp); image_set_name(hdr, params->imagename); From 55b0affd26e5b31868893faf3e69c41157ce56a6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 25 Nov 2022 12:56:29 +0100 Subject: [PATCH 121/424] firmware: scmi: use protocol node name to bind the scmi regulator driver In scmi firmware driver, it is better to bind the scmi protocol driver "scmi_voltage_domain" with the node name of the protocol 17 and not the sub-node named "regulator", because is a fixed string which doesn't provide information and because it is not aligned with the other scmi protocol nodes. For example on stm32mp135f-dk board with device tree in stm32mp131.dtsi scmi: scmi { compatible = "linaro,scmi-optee"; #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; shmem = <&scmi_shm>; scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; }; scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; }; scmi_voltd: protocol@17 { reg = <0x17>; scmi_regu: regulators { #address-cells = <1>; #size-cells = <0>; scmi_reg11: voltd-reg11 { reg = ; regulator-name = "reg11"; }; scmi_reg18: voltd-reg18 { reg = ; regulator-name = "reg18"; }; scmi_usb33: voltd-usb33 { reg = ; regulator-name = "usb33"; }; }; }; }; Before the patch: > dm tree scmi_agent 0 [ + ] scmi-over-optee |-- scmi clk 1 [ + ] scmi_clk | |-- protocol@14 ... reset 1 [ ] scmi_reset_domain | |-- protocol@16 nop 2 [ + ] scmi_voltage_domain | `-- regulators regulator 0 [ + ] scmi_regulator | |-- voltd-reg11 regulator 1 [ + ] scmi_regulator | |-- voltd-reg18 regulator 2 [ + ] scmi_regulator | |-- voltd-usb33 ... after the patch: > dm tree scmi_agent 0 [ + ] scmi-over-optee |-- scmi clk 1 [ + ] scmi_clk | |-- protocol@14 ... reset 1 [ ] scmi_reset_domain | |-- protocol@16 nop 2 [ + ] scmi_voltage_domain | `-- protocol@17 regulator 0 [ + ] scmi_regulator | |-- voltd-reg11 regulator 1 [ + ] scmi_regulator | |-- voltd-reg18 regulator 2 [ + ] scmi_regulator | |-- voltd-usb33 ... Signed-off-by: Patrick Delaunay --- drivers/firmware/scmi/scmi_agent-uclass.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 8f48de30c8..9a32678617 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -60,6 +60,7 @@ static int scmi_bind_protocols(struct udevice *dev) { int ret = 0; ofnode node; + const char *name; dev_for_each_subnode(node, dev) { struct driver *drv = NULL; @@ -71,6 +72,7 @@ static int scmi_bind_protocols(struct udevice *dev) if (ofnode_read_u32(node, "reg", &protocol_id)) continue; + name = ofnode_get_name(node); switch (protocol_id) { case SCMI_PROTOCOL_ID_CLOCK: if (IS_ENABLED(CONFIG_CLK_SCMI)) @@ -100,8 +102,7 @@ static int scmi_bind_protocols(struct udevice *dev) continue; } - ret = device_bind(dev, drv, ofnode_get_name(node), NULL, node, - NULL); + ret = device_bind(dev, drv, name, NULL, node, NULL); if (ret) break; } From 486aef08de091ca35386f32fe961a201c3cfa9d4 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 28 Nov 2022 09:41:22 +0100 Subject: [PATCH 122/424] u-boot-initial-env: rework make target MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With LTO enabled the U-Boot initial environment is no longer stored in an easy accessible section in env/common.o. I.e. the section name changes from build to build, its content maybe compressed and it is annotated with additional data. Drop trying to read the initial env with elf tools from the compiler specific object file in favour of adding and using a host tool with the only functionality of printing the initial env to stdout. See also: https://lore.kernel.org/all/927b122e-1f62-e790-f5ca-30bae4332c77@foss.st.com/ Signed-off-by: Max Krummenacher Acked-by: Pali Rohár Reviewed-by: Simon Glass --- Makefile | 10 ++++++---- tools/.gitignore | 1 + tools/Makefile | 4 ++++ tools/printinitialenv.c | 44 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 55 insertions(+), 4 deletions(-) create mode 100644 tools/printinitialenv.c diff --git a/Makefile b/Makefile index 11efc41804..9ec2e12a06 100644 --- a/Makefile +++ b/Makefile @@ -2439,11 +2439,13 @@ endif $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost quiet_cmd_genenv = GENENV $@ -cmd_genenv = $(OBJCOPY) --dump-section .rodata.default_environment=$@ env/common.o; \ - sed --in-place -e 's/\x00/\x0A/g' $@; sed --in-place -e '/^\s*$$/d' $@; \ - sort --field-separator== -k1,1 --stable $@ -o $@ +cmd_genenv = \ + $(objtree)/tools/printinitialenv | \ + sed -e '/^\s*$$/d' | \ + sort --field-separator== -k1,1 --stable -o $@ -u-boot-initial-env: u-boot.bin +u-boot-initial-env: $(env_h) FORCE + $(Q)$(MAKE) $(build)=tools $(objtree)/tools/printinitialenv $(call if_changed,genenv) # Consistency checks diff --git a/tools/.gitignore b/tools/.gitignore index d3a93ff294..28e8ce2a07 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -28,6 +28,7 @@ /mxsboot /ncb /prelink-riscv +/printinitialenv /proftool /relocate-rela /spl_size_limit diff --git a/tools/Makefile b/tools/Makefile index 26be0a7ba2..80bc62befc 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -275,6 +275,10 @@ clean-dirs := lib common always := $(hostprogs-y) +# Host tool to dump the currently configured default environment, +# build it on demand, i.e. not add it to 'always'. +hostprogs-y += printinitialenv + # Generated LCD/video logo LOGO_H = $(objtree)/include/bmp_logo.h LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h diff --git a/tools/printinitialenv.c b/tools/printinitialenv.c new file mode 100644 index 0000000000..c58b234d67 --- /dev/null +++ b/tools/printinitialenv.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 + * Max Krummenacher, Toradex + * + * Snippets taken from tools/env/fw_env.c + * + * This prints the list of default environment variables as currently + * configured. + * + */ + +#include + +/* Pull in the current config to define the default environment */ +#include + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* get only #defines from config.h */ +#include +#undef __ASSEMBLY__ +#else +#include +#endif + +#define DEFAULT_ENV_INSTANCE_STATIC +#include +#include + +int main(void) +{ + char *env, *nxt; + + for (env = default_environment; *env; env = nxt + 1) { + for (nxt = env; *nxt; ++nxt) { + if (nxt >= &default_environment[sizeof(default_environment)]) { + fprintf(stderr, "## Error: environment not terminated\n"); + return -1; + } + } + printf("%s\n", env); + } + return 0; +} From aeea67f9a033ab6f3adca7b30bbd02579f72512f Mon Sep 17 00:00:00 2001 From: Kasper Revsbech Date: Thu, 1 Dec 2022 16:30:32 +0100 Subject: [PATCH 123/424] fs/squashfs: use lldiv function for math When compling for x86: u-boot/fs/squashfs/sqfs.c:90: undefined reference to `__udivmoddi4' Signed-off-by: Kasper Revsbech Tested-by: Sean Nyekjaer --- fs/squashfs/sqfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 74ca70c3ff..4226621923 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -87,7 +87,7 @@ static int sqfs_calc_n_blks(__le64 start, __le64 end, u64 *offset) u64 start_, table_size; table_size = le64_to_cpu(end) - le64_to_cpu(start); - start_ = le64_to_cpu(start) / ctxt.cur_dev->blksz; + start_ = lldiv(le64_to_cpu(start), ctxt.cur_dev->blksz); *offset = le64_to_cpu(start) - (start_ * ctxt.cur_dev->blksz); return DIV_ROUND_UP(table_size + *offset, ctxt.cur_dev->blksz); From bd0ed9a2d251d68e6327656f3d8ef2f145396ee4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 4 Dec 2022 13:31:08 +0100 Subject: [PATCH 124/424] ata: ahci-pci: Replace magic constant by macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace 0x1b21 by macro PCI_VENDOR_ID_ASMEDIA with the same value. Signed-off-by: Pali Rohár Reviewed-by: Simon Glass --- drivers/ata/ahci-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c index 797e0d570e..5356b9d83d 100644 --- a/drivers/ata/ahci-pci.c +++ b/drivers/ata/ahci-pci.c @@ -37,7 +37,7 @@ U_BOOT_DRIVER(ahci_pci) = { static struct pci_device_id ahci_pci_supported[] = { { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) }, - { PCI_DEVICE(0x1b21, 0x0611) }, + { PCI_DEVICE(PCI_VENDOR_ID_ASMEDIA, 0x0611) }, { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6121) }, { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6145) }, {}, From 6a8dfd57220d4b7c2182f1b9a7a5fe3e4da8b63d Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:01 +0530 Subject: [PATCH 125/424] nand: atmel: Add DM based NAND driver This implementation is ported from the rework done by Boris Brezillon in Linux. This porting is done based on linux-5.4-at91. The driver is tested in sam9x60ek, sama5d3_xplained, sam9x75eb and sama7g54-ddr3-eb. Changes done includes - Adapt GPIO descriptor apis for U-Boot. Use gpio_request_by_name_nodev, dm_gpio_get_value etc. - Use U_BOOT_DRIVER instead of platform_driver. - Replace struct platform_device with struct udevice - Check the status of nfc exec operation by polling the status register instead of interrupt based handling - DMA operations not supported. Remove it - Adapt DT parsing to U-Boot APIs Signed-off-by: Balamanikandan Gunasundar --- drivers/mtd/nand/raw/Kconfig | 8 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/atmel/Makefile | 4 + drivers/mtd/nand/raw/atmel/nand-controller.c | 2286 ++++++++++++++++++ 4 files changed, 2299 insertions(+) create mode 100644 drivers/mtd/nand/raw/atmel/Makefile create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 338a3562a4..0f2eaebfdb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -45,6 +45,14 @@ config SYS_NAND_NO_SUBPAGE_WRITE bool "Disable subpage write support" depends on NAND_ARASAN || NAND_DAVINCI || NAND_KIRKWOOD +config DM_NAND_ATMEL + bool "Support Atmel NAND controller with DM support" + select SYS_NAND_SELF_INIT + imply SYS_NAND_USE_FLASH_BBT + help + Enable this driver for NAND flash platforms using an Atmel NAND + controller. + config NAND_ATMEL bool "Support Atmel NAND controller" select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a398aa9d88..42c1fb25b4 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -48,6 +48,7 @@ ifdef NORMAL_DRIVERS obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o +obj-$(CONFIG_DM_NAND_ATMEL) += atmel/ obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o diff --git a/drivers/mtd/nand/raw/atmel/Makefile b/drivers/mtd/nand/raw/atmel/Makefile new file mode 100644 index 0000000000..6708416983 --- /dev/null +++ b/drivers/mtd/nand/raw/atmel/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_DM_NAND_ATMEL) += atmel-nand-controller.o + +atmel-nand-controller-objs := nand-controller.o diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c new file mode 100644 index 0000000000..9873d11254 --- /dev/null +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -0,0 +1,2286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 ATMEL + * Copyright 2017 Free Electrons + * + * Author: Boris Brezillon + * + * Derived from the atmel_nand.c driver which contained the following + * copyrights: + * + * Copyright 2003 Rick Bronson + * + * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8) + * Copyright 2001 Thomas Gleixner (gleixner@autronix.de) + * + * Derived from drivers/mtd/spia.c (removed in v3.8) + * Copyright 2000 Steven J. Hill (sjhill@cotw.com) + * + * + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007 + * + * Derived from Das U-Boot source code + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) + * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * Add Programmable Multibit ECC support for various AT91 SoC + * Copyright 2012 ATMEL, Hong Xu + * + * Add Nand Flash Controller support for SAMA5 SoC + * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) + * + * Port from Linux + * Balamanikandan Gunasundar(balamanikandan.gunasundar@microchip.com) + * Copyright (C) 2022 Microchip Technology Inc. + * + * A few words about the naming convention in this file. This convention + * applies to structure and function names. + * + * Prefixes: + * + * - atmel_nand_: all generic structures/functions + * - atmel_smc_nand_: all structures/functions specific to the SMC interface + * (at91sam9 and avr32 SoCs) + * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface + * (sama5 SoCs and later) + * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block + * that is available in the HSMC block + * - _nand_: all SoC specific structures/functions + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmecc.h" + +#define NSEC_PER_SEC 1000000000L + +#define ATMEL_HSMC_NFC_CFG 0x0 +#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24) +#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24) +#define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20)) +#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16) +#define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13) +#define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12) +#define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9) +#define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8) +#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0) +#define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1) + +#define ATMEL_HSMC_NFC_CTRL 0x4 +#define ATMEL_HSMC_NFC_CTRL_EN BIT(0) +#define ATMEL_HSMC_NFC_CTRL_DIS BIT(1) + +#define ATMEL_HSMC_NFC_SR 0x8 +#define ATMEL_HSMC_NFC_IER 0xc +#define ATMEL_HSMC_NFC_IDR 0x10 +#define ATMEL_HSMC_NFC_IMR 0x14 +#define ATMEL_HSMC_NFC_SR_ENABLED BIT(1) +#define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4) +#define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5) +#define ATMEL_HSMC_NFC_SR_BUSY BIT(8) +#define ATMEL_HSMC_NFC_SR_WR BIT(11) +#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12) +#define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16) +#define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17) +#define ATMEL_HSMC_NFC_SR_DTOE BIT(20) +#define ATMEL_HSMC_NFC_SR_UNDEF BIT(21) +#define ATMEL_HSMC_NFC_SR_AWB BIT(22) +#define ATMEL_HSMC_NFC_SR_NFCASE BIT(23) +#define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \ + ATMEL_HSMC_NFC_SR_UNDEF | \ + ATMEL_HSMC_NFC_SR_AWB | \ + ATMEL_HSMC_NFC_SR_NFCASE) +#define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24) + +#define ATMEL_HSMC_NFC_ADDR 0x18 +#define ATMEL_HSMC_NFC_BANK 0x1c + +#define ATMEL_NFC_MAX_RB_ID 7 + +#define ATMEL_NFC_SRAM_SIZE 0x2400 + +#define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2)) +#define ATMEL_NFC_VCMD2 BIT(18) +#define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19) +#define ATMEL_NFC_CSID(cs) ((cs) << 22) +#define ATMEL_NFC_DATAEN BIT(25) +#define ATMEL_NFC_NFCWR BIT(26) + +#define ATMEL_NFC_MAX_ADDR_CYCLES 5 + +#define ATMEL_NAND_ALE_OFFSET BIT(21) +#define ATMEL_NAND_CLE_OFFSET BIT(22) + +#define DEFAULT_TIMEOUT_MS 1000 +#define MIN_DMA_LEN 128 + +static struct nand_ecclayout atmel_pmecc_oobinfo; + +struct nand_controller_ops { + int (*attach_chip)(struct nand_chip *chip); + int (*setup_data_interface)(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf); +}; + +struct nand_controller { + const struct nand_controller_ops *ops; +}; + +enum atmel_nand_rb_type { + ATMEL_NAND_NO_RB, + ATMEL_NAND_NATIVE_RB, + ATMEL_NAND_GPIO_RB, +}; + +struct atmel_nand_rb { + enum atmel_nand_rb_type type; + union { + struct gpio_desc gpio; + int id; + }; +}; + +struct atmel_nand_cs { + int id; + struct atmel_nand_rb rb; + struct gpio_desc csgpio; + struct { + void __iomem *virt; + dma_addr_t dma; + } io; + + struct atmel_smc_cs_conf smcconf; +}; + +struct atmel_nand { + struct list_head node; + struct udevice *dev; + struct nand_chip base; + struct atmel_nand_cs *activecs; + struct atmel_pmecc_user *pmecc; + struct gpio_desc cdgpio; + int numcs; + struct nand_controller *controller; + struct atmel_nand_cs cs[]; +}; + +static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip) +{ + return container_of(chip, struct atmel_nand, base); +} + +enum atmel_nfc_data_xfer { + ATMEL_NFC_NO_DATA, + ATMEL_NFC_READ_DATA, + ATMEL_NFC_WRITE_DATA, +}; + +struct atmel_nfc_op { + u8 cs; + u8 ncmds; + u8 cmds[2]; + u8 naddrs; + u8 addrs[5]; + enum atmel_nfc_data_xfer data; + u32 wait; + u32 errors; +}; + +struct atmel_nand_controller; +struct atmel_nand_controller_caps; + +struct atmel_nand_controller_ops { + int (*probe)(struct udevice *udev, + const struct atmel_nand_controller_caps *caps); + int (*remove)(struct atmel_nand_controller *nc); + void (*nand_init)(struct atmel_nand_controller *nc, + struct atmel_nand *nand); + int (*ecc_init)(struct nand_chip *chip); + int (*setup_data_interface)(struct atmel_nand *nand, int csline, + const struct nand_data_interface *conf); +}; + +struct atmel_nand_controller_caps { + bool has_dma; + bool legacy_of_bindings; + u32 ale_offs; + u32 cle_offs; + const char *ebi_csa_regmap_name; + const struct atmel_nand_controller_ops *ops; +}; + +struct atmel_nand_controller { + struct nand_controller base; + const struct atmel_nand_controller_caps *caps; + struct udevice *dev; + struct regmap *smc; + struct dma_chan *dmac; + struct atmel_pmecc *pmecc; + struct list_head chips; + struct clk *mck; +}; + +static inline struct atmel_nand_controller * +to_nand_controller(struct nand_controller *ctl) +{ + return container_of(ctl, struct atmel_nand_controller, base); +} + +struct atmel_smc_nand_ebi_csa_cfg { + u32 offs; + u32 nfd0_on_d16; +}; + +struct atmel_smc_nand_controller { + struct atmel_nand_controller base; + struct regmap *ebi_csa_regmap; + struct atmel_smc_nand_ebi_csa_cfg *ebi_csa; +}; + +static inline struct atmel_smc_nand_controller * +to_smc_nand_controller(struct nand_controller *ctl) +{ + return container_of(to_nand_controller(ctl), + struct atmel_smc_nand_controller, base); +} + +struct atmel_hsmc_nand_controller { + struct atmel_nand_controller base; + struct { + struct gen_pool *pool; + void __iomem *virt; + dma_addr_t dma; + } sram; + const struct atmel_hsmc_reg_layout *hsmc_layout; + struct regmap *io; + struct atmel_nfc_op op; + struct completion complete; + int irq; + + /* Only used when instantiating from legacy DT bindings. */ + struct clk *clk; +}; + +static inline struct atmel_hsmc_nand_controller * +to_hsmc_nand_controller(struct nand_controller *ctl) +{ + return container_of(to_nand_controller(ctl), + struct atmel_hsmc_nand_controller, base); +} + +static void pmecc_config_ecc_layout(struct nand_ecclayout *layout, + int oobsize, int ecc_len) +{ + int i; + + layout->eccbytes = ecc_len; + + /* ECC will occupy the last ecc_len bytes continuously */ + for (i = 0; i < ecc_len; i++) + layout->eccpos[i] = oobsize - ecc_len + i; + + layout->oobfree[0].offset = 2; + layout->oobfree[0].length = + oobsize - ecc_len - layout->oobfree[0].offset; +} + +static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status) +{ + op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS; + op->wait ^= status & op->wait; + + return !op->wait || op->errors; +} + +static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll, + unsigned int timeout_ms) +{ + int ret; + u32 status; + + if (!timeout_ms) + timeout_ms = DEFAULT_TIMEOUT_MS; + + if (poll) + ret = regmap_read_poll_timeout(nc->base.smc, + ATMEL_HSMC_NFC_SR, status, + atmel_nfc_op_done(&nc->op, + status), + 0, timeout_ms); + else + return -EOPNOTSUPP; + + if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) { + dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); + ret = -ETIMEDOUT; + } + + if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) { + dev_err(nc->base.dev, "Access to an undefined area\n"); + ret = -EIO; + } + + if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) { + dev_err(nc->base.dev, "Access while busy\n"); + ret = -EIO; + } + + if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) { + dev_err(nc->base.dev, "Wrong access size\n"); + ret = -EIO; + } + + return ret; +} + +static void iowrite8_rep(void *addr, const uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + writeb(buf[i], addr); +} + +static void ioread8_rep(void *addr, uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + buf[i] = readb(addr); +} + +static void ioread16_rep(void *addr, void *buf, int len) +{ + int i; + u16 *p = (u16 *)buf; + + for (i = 0; i < len; i++) + p[i] = readw(addr); +} + +static void iowrite16_rep(void *addr, const void *buf, int len) +{ + int i; + u16 *p = (u16 *)buf; + + for (i = 0; i < len; i++) + writew(p[i], addr); +} + +static u8 atmel_nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + + return ioread8(nand->activecs->io.virt); +} + +static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + + if (chip->options & NAND_BUSWIDTH_16) + iowrite16(byte | (byte << 8), nand->activecs->io.virt); + else + iowrite8(byte, nand->activecs->io.virt); +} + +static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + + if (chip->options & NAND_BUSWIDTH_16) + ioread16_rep(nand->activecs->io.virt, buf, len / 2); + else + ioread8_rep(nand->activecs->io.virt, buf, len); +} + +static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + + if (chip->options & NAND_BUSWIDTH_16) + iowrite16_rep(nand->activecs->io.virt, buf, len / 2); + else + iowrite8_rep(nand->activecs->io.virt, buf, len); +} + +static int atmel_nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + + return dm_gpio_get_value(&nand->activecs->rb.gpio); +} + +static void atmel_nand_select_chip(struct mtd_info *mtd, int cs) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + + if (cs < 0 || cs >= nand->numcs) { + nand->activecs = NULL; + chip->dev_ready = NULL; + return; + } + + nand->activecs = &nand->cs[cs]; + + if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB) + chip->dev_ready = atmel_nand_dev_ready; +} + +static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + u32 status; + + nc = to_hsmc_nand_controller(nand->controller); + + regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status); + + return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); +} + +static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + + nc = to_hsmc_nand_controller(nand->controller); + + atmel_nand_select_chip(mtd, cs); + + if (!nand->activecs) { + regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, + ATMEL_HSMC_NFC_CTRL_DIS); + return; + } + + if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB) + chip->dev_ready = atmel_hsmc_nand_dev_ready; + + regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, + ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK | + ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK | + ATMEL_HSMC_NFC_CFG_RSPARE | + ATMEL_HSMC_NFC_CFG_WSPARE, + ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | + ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | + ATMEL_HSMC_NFC_CFG_RSPARE); + regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, + ATMEL_HSMC_NFC_CTRL_EN); +} + +static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll) +{ + u8 *addrs = nc->op.addrs; + unsigned int op = 0; + u32 addr, val; + int i, ret; + + nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE; + + for (i = 0; i < nc->op.ncmds; i++) + op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]); + + if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) + regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++); + + op |= ATMEL_NFC_CSID(nc->op.cs) | + ATMEL_NFC_ACYCLE(nc->op.naddrs); + + if (nc->op.ncmds > 1) + op |= ATMEL_NFC_VCMD2; + + addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) | + (addrs[3] << 24); + + if (nc->op.data != ATMEL_NFC_NO_DATA) { + op |= ATMEL_NFC_DATAEN; + nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE; + + if (nc->op.data == ATMEL_NFC_WRITE_DATA) + op |= ATMEL_NFC_NFCWR; + } + + /* Clear all flags. */ + regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val); + + /* Send the command. */ + regmap_write(nc->io, op, addr); + + ret = atmel_nfc_wait(nc, poll, 0); + if (ret) + dev_err(nc->base.dev, + "Failed to send NAND command (err = %d)!", + ret); + + /* Reset the op state. */ + memset(&nc->op, 0, sizeof(nc->op)); + + return ret; +} + +static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat, + unsigned int ctrl) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + + nc = to_hsmc_nand_controller(nand->controller); + + if (ctrl & NAND_ALE) { + if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) + return; + + nc->op.addrs[nc->op.naddrs++] = dat; + } else if (ctrl & NAND_CLE) { + if (nc->op.ncmds > 1) + return; + + nc->op.cmds[nc->op.ncmds++] = dat; + } + + if (dat == NAND_CMD_NONE) { + nc->op.cs = nand->activecs->id; + atmel_nfc_exec_op(nc, true); + } +} + +static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_nand_controller *nc; + + nc = to_nand_controller(nand->controller); + + if ((ctrl & NAND_CTRL_CHANGE) && + dm_gpio_is_valid(&nand->activecs->csgpio)) { + if (ctrl & NAND_NCE) + dm_gpio_set_value(&nand->activecs->csgpio, 0); + else + dm_gpio_set_value(&nand->activecs->csgpio, 1); + } + + if (ctrl & NAND_ALE) + writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs); + else if (ctrl & NAND_CLE) + writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs); +} + +static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf, + bool oob_required) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + int ret = -EIO; + + nc = to_hsmc_nand_controller(nand->controller); + + if (ret) + memcpy_toio(nc->sram.virt, buf, mtd->writesize); + + if (oob_required) + memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi, + mtd->oobsize); +} + +static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf, + bool oob_required) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + int ret = -EIO; + + nc = to_hsmc_nand_controller(nand->controller); + + if (ret) + memcpy_fromio(buf, nc->sram.virt, mtd->writesize); + + if (oob_required) + memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize, + mtd->oobsize); +} + +static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + + nc = to_hsmc_nand_controller(nand->controller); + + if (column >= 0) { + nc->op.addrs[nc->op.naddrs++] = column; + + /* + * 2 address cycles for the column offset on large page NANDs. + */ + if (mtd->writesize > 512) + nc->op.addrs[nc->op.naddrs++] = column >> 8; + } + + if (page >= 0) { + nc->op.addrs[nc->op.naddrs++] = page; + nc->op.addrs[nc->op.naddrs++] = page >> 8; + + if (chip->options & NAND_ROW_ADDR_3) + nc->op.addrs[nc->op.naddrs++] = page >> 16; + } +} + +static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw) +{ + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_nand_controller *nc; + int ret; + + nc = to_nand_controller(nand->controller); + + if (raw) + return 0; + + ret = atmel_pmecc_enable(nand->pmecc, op); + if (ret) + dev_err(nc->dev, + "Failed to enable ECC engine (err = %d)\n", ret); + + return ret; +} + +static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw) +{ + struct atmel_nand *nand = to_atmel_nand(chip); + + if (!raw) + atmel_pmecc_disable(nand->pmecc); +} + +static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw) +{ + struct atmel_nand *nand = to_atmel_nand(chip); + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand_controller *nc; + struct mtd_oob_region oobregion; + void *eccbuf; + int ret, i; + + nc = to_nand_controller(nand->controller); + + if (raw) + return 0; + + ret = atmel_pmecc_wait_rdy(nand->pmecc); + if (ret) { + dev_err(nc->dev, + "Failed to transfer NAND page data (err = %d)\n", + ret); + return ret; + } + + mtd_ooblayout_ecc(mtd, 0, &oobregion); + eccbuf = chip->oob_poi + oobregion.offset; + + for (i = 0; i < chip->ecc.steps; i++) { + atmel_pmecc_get_generated_eccbytes(nand->pmecc, i, + eccbuf); + eccbuf += chip->ecc.bytes; + } + + return 0; +} + +static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf, + bool raw) +{ + struct atmel_nand *nand = to_atmel_nand(chip); + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand_controller *nc; + struct mtd_oob_region oobregion; + int ret, i, max_bitflips = 0; + void *databuf, *eccbuf; + + nc = to_nand_controller(nand->controller); + + if (raw) + return 0; + + ret = atmel_pmecc_wait_rdy(nand->pmecc); + if (ret) { + dev_err(nc->dev, + "Failed to read NAND page data (err = %d)\n", ret); + return ret; + } + + mtd_ooblayout_ecc(mtd, 0, &oobregion); + eccbuf = chip->oob_poi + oobregion.offset; + databuf = buf; + + for (i = 0; i < chip->ecc.steps; i++) { + ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf, + eccbuf); + if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc)) + ret = nand_check_erased_ecc_chunk(databuf, + chip->ecc.size, + eccbuf, + chip->ecc.bytes, + NULL, 0, + chip->ecc.strength); + + if (ret >= 0) + max_bitflips = max(ret, max_bitflips); + else + mtd->ecc_stats.failed++; + + databuf += chip->ecc.size; + eccbuf += chip->ecc.bytes; + } + + return max_bitflips; +} + +static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf, + bool oob_required, int page, bool raw) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + int ret; + + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + + ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw); + if (ret) + return ret; + + atmel_nand_write_buf(mtd, buf, mtd->writesize); + + ret = atmel_nand_pmecc_generate_eccbytes(chip, raw); + if (ret) { + atmel_pmecc_disable(nand->pmecc); + return ret; + } + + atmel_nand_pmecc_disable(chip, raw); + + atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + return nand_prog_page_end_op(chip); +} + +static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, const u8 *buf, + int oob_required, int page) +{ + return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false); +} + +static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, + const u8 *buf, int oob_required, + int page) +{ + return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true); +} + +static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf, + bool oob_required, int page, bool raw) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + nand_read_page_op(chip, page, 0, NULL, 0); + + ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw); + if (ret) + return ret; + + atmel_nand_read_buf(mtd, buf, mtd->writesize); + atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + ret = atmel_nand_pmecc_correct_data(chip, buf, raw); + + atmel_nand_pmecc_disable(chip, raw); + + return ret; +} + +static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false); +} + +static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true); +} + +static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip, + const u8 *buf, bool oob_required, + int page, bool raw) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + int ret, status; + + nc = to_hsmc_nand_controller(nand->controller); + + atmel_nfc_copy_to_sram(chip, buf, false); + + nc->op.cmds[0] = NAND_CMD_SEQIN; + nc->op.ncmds = 1; + atmel_nfc_set_op_addr(chip, page, 0x0); + nc->op.cs = nand->activecs->id; + nc->op.data = ATMEL_NFC_WRITE_DATA; + + ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw); + if (ret) + return ret; + + ret = atmel_nfc_exec_op(nc, true); + if (ret) { + atmel_nand_pmecc_disable(chip, raw); + dev_err(nc->base.dev, + "Failed to transfer NAND page data (err = %d)\n", + ret); + return ret; + } + + ret = atmel_nand_pmecc_generate_eccbytes(chip, raw); + + atmel_nand_pmecc_disable(chip, raw); + + if (ret) + return ret; + + atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + nc->op.cmds[0] = NAND_CMD_PAGEPROG; + nc->op.ncmds = 1; + nc->op.cs = nand->activecs->id; + ret = atmel_nfc_exec_op(nc, true); + if (ret) + dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n", + ret); + + status = chip->waitfunc(mtd, chip); + if (status & NAND_STATUS_FAIL) + return -EIO; + + return ret; +} + +static int +atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, int oob_required, + int page) +{ + return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page, + false); +} + +static int +atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, + const u8 *buf, + int oob_required, int page) +{ + return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page, + true); +} + +static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf, + bool oob_required, int page, + bool raw) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_hsmc_nand_controller *nc; + int ret; + + nc = to_hsmc_nand_controller(nand->controller); + + /* + * Optimized read page accessors only work when the NAND R/B pin is + * connected to a native SoC R/B pin. If that's not the case, fallback + * to the non-optimized one. + */ + if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) { + nand_read_page_op(chip, page, 0, NULL, 0); + + return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, + raw); + } + + nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; + + if (mtd->writesize > 512) + nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART; + + atmel_nfc_set_op_addr(chip, page, 0x0); + nc->op.cs = nand->activecs->id; + nc->op.data = ATMEL_NFC_READ_DATA; + + ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw); + if (ret) + return ret; + + ret = atmel_nfc_exec_op(nc, true); + if (ret) { + atmel_nand_pmecc_disable(chip, raw); + dev_err(nc->base.dev, + "Failed to load NAND page data (err = %d)\n", + ret); + return ret; + } + + atmel_nfc_copy_from_sram(chip, buf, true); + + ret = atmel_nand_pmecc_correct_data(chip, buf, raw); + + atmel_nand_pmecc_disable(chip, raw); + + return ret; +} + +static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page, + false); +} + +static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, + u8 *buf, int oob_required, + int page) +{ + return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page, + true); +} + +static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_ecc_ctrl *ecc = &chip->ecc; + + if (section || !ecc->total) + return -ERANGE; + + oobregion->length = ecc->total; + oobregion->offset = mtd->oobsize - oobregion->length; + + return 0; +} + +static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, + struct mtd_oob_region *oobregion) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_ecc_ctrl *ecc = &chip->ecc; + + if (section) + return -ERANGE; + + oobregion->length = mtd->oobsize - ecc->total - 2; + oobregion->offset = 2; + + return 0; +} + +static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { + .ecc = nand_ooblayout_ecc_lp, + .rfree = nand_ooblayout_free_lp, +}; + +const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void) +{ + return &nand_ooblayout_lp_ops; +} + +static int atmel_nand_pmecc_init(struct nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(chip); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_nand_controller *nc; + struct atmel_pmecc_user_req req; + + nc = to_nand_controller(nand->controller); + + if (!nc->pmecc) { + dev_err(nc->dev, "HW ECC not supported\n"); + return -EOPNOTSUPP; + } + + if (nc->caps->legacy_of_bindings) { + u32 val; + + if (!ofnode_read_u32(nc->dev->node_, "atmel,pmecc-cap", &val)) + chip->ecc.strength = val; + + if (!ofnode_read_u32(nc->dev->node_, + "atmel,pmecc-sector-size", + &val)) + chip->ecc.size = val; + } + + if (chip->ecc.options & NAND_ECC_MAXIMIZE) + req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; + else if (chip->ecc.strength) + req.ecc.strength = chip->ecc.strength; + else + req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; + + if (chip->ecc.size) + req.ecc.sectorsize = chip->ecc.size; + else + req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; + + req.pagesize = mtd->writesize; + req.oobsize = mtd->oobsize; + + if (mtd->writesize <= 512) { + req.ecc.bytes = 4; + req.ecc.ooboffset = 0; + } else { + req.ecc.bytes = mtd->oobsize - 2; + req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO; + } + + nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req); + if (IS_ERR(nand->pmecc)) + return PTR_ERR(nand->pmecc); + + chip->ecc.algo = NAND_ECC_BCH; + chip->ecc.size = req.ecc.sectorsize; + chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; + chip->ecc.strength = req.ecc.strength; + + chip->options |= NAND_NO_SUBPAGE_WRITE; + + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); + pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, + mtd->oobsize, + chip->ecc.bytes); + chip->ecc.layout = &atmel_pmecc_oobinfo; + + return 0; +} + +static int atmel_nand_ecc_init(struct nand_chip *chip) +{ + struct atmel_nand_controller *nc; + struct atmel_nand *nand = to_atmel_nand(chip); + int ret; + + nc = to_nand_controller(nand->controller); + + switch (chip->ecc.mode) { + case NAND_ECC_NONE: + case NAND_ECC_SOFT: + /* + * Nothing to do, the core will initialize everything for us. + */ + break; + + case NAND_ECC_HW: + ret = atmel_nand_pmecc_init(chip); + if (ret) + return ret; + + chip->ecc.read_page = atmel_nand_pmecc_read_page; + chip->ecc.write_page = atmel_nand_pmecc_write_page; + chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw; + chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw; + break; + + default: + /* Other modes are not supported. */ + dev_err(nc->dev, "Unsupported ECC mode: %d\n", + chip->ecc.mode); + return -EOPNOTSUPP; + } + + return 0; +} + +static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip) +{ + int ret; + + ret = atmel_nand_ecc_init(chip); + if (ret) + return ret; + + if (chip->ecc.mode != NAND_ECC_HW) + return 0; + + /* Adjust the ECC operations for the HSMC IP. */ + chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page; + chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page; + chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw; + chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw; + + return 0; +} + +static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand, + const struct nand_data_interface *conf, + struct atmel_smc_cs_conf *smcconf) +{ + u32 ncycles, totalcycles, timeps, mckperiodps; + struct atmel_nand_controller *nc; + int ret; + + nc = to_nand_controller(nand->controller); + + /* DDR interface not supported. */ + if (conf->type != NAND_SDR_IFACE) + return -EOPNOTSUPP; + + /* + * tRC < 30ns implies EDO mode. This controller does not support this + * mode. + */ + if (conf->timings.sdr.tRC_min < 30000) + return -EOPNOTSUPP; + + atmel_smc_cs_conf_init(smcconf); + + mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck); + mckperiodps *= 1000; + + /* + * Set write pulse timing. This one is easy to extract: + * + * NWE_PULSE = tWP + */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); + totalcycles = ncycles; + ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT, + ncycles); + if (ret) + return ret; + + /* + * The write setup timing depends on the operation done on the NAND. + * All operations goes through the same data bus, but the operation + * type depends on the address we are writing to (ALE/CLE address + * lines). + * Since we have no way to differentiate the different operations at + * the SMC level, we must consider the worst case (the biggest setup + * time among all operation types): + * + * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE + */ + timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, + conf->timings.sdr.tALS_min); + timeps = max(timeps, conf->timings.sdr.tDS_min); + ncycles = DIV_ROUND_UP(timeps, mckperiodps); + ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0; + totalcycles += ncycles; + ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT, + ncycles); + if (ret) + return ret; + + /* + * As for the write setup timing, the write hold timing depends on the + * operation done on the NAND: + * + * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH) + */ + timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, + conf->timings.sdr.tALH_min); + timeps = max3(timeps, conf->timings.sdr.tDH_min, + conf->timings.sdr.tWH_min); + ncycles = DIV_ROUND_UP(timeps, mckperiodps); + totalcycles += ncycles; + + /* + * The write cycle timing is directly matching tWC, but is also + * dependent on the other timings on the setup and hold timings we + * calculated earlier, which gives: + * + * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD) + */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); + ncycles = max(totalcycles, ncycles); + ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT, + ncycles); + if (ret) + return ret; + + /* + * We don't want the CS line to be toggled between each byte/word + * transfer to the NAND. The only way to guarantee that is to have the + * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means: + * + * NCS_WR_PULSE = NWE_CYCLE + */ + ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT, + ncycles); + if (ret) + return ret; + + /* + * As for the write setup timing, the read hold timing depends on the + * operation done on the NAND: + * + * NRD_HOLD = max(tREH, tRHOH) + */ + timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min); + ncycles = DIV_ROUND_UP(timeps, mckperiodps); + totalcycles = ncycles; + + /* + * TDF = tRHZ - NRD_HOLD + */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps); + ncycles -= totalcycles; + + /* + * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and + * we might end up with a config that does not fit in the TDF field. + * Just take the max value in this case and hope that the NAND is more + * tolerant than advertised. + */ + if (ncycles > ATMEL_SMC_MODE_TDF_MAX) + ncycles = ATMEL_SMC_MODE_TDF_MAX; + else if (ncycles < ATMEL_SMC_MODE_TDF_MIN) + ncycles = ATMEL_SMC_MODE_TDF_MIN; + + smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) | + ATMEL_SMC_MODE_TDFMODE_OPTIMIZED; + + /* + * Read pulse timing directly matches tRP: + * + * NRD_PULSE = tRP + */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps); + totalcycles += ncycles; + ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT, + ncycles); + if (ret) + return ret; + + /* + * The write cycle timing is directly matching tWC, but is also + * dependent on the setup and hold timings we calculated earlier, + * which gives: + * + * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD) + * + * NRD_SETUP is always 0. + */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); + ncycles = max(totalcycles, ncycles); + ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT, + ncycles); + if (ret) + return ret; + + /* + * We don't want the CS line to be toggled between each byte/word + * transfer from the NAND. The only way to guarantee that is to have + * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means: + * + * NCS_RD_PULSE = NRD_CYCLE + */ + ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT, + ncycles); + if (ret) + return ret; + + /* Txxx timings are directly matching tXXX ones. */ + ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps); + ret = atmel_smc_cs_conf_set_timing(smcconf, + ATMEL_HSMC_TIMINGS_TCLR_SHIFT, + ncycles); + if (ret) + return ret; + + ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps); + ret = atmel_smc_cs_conf_set_timing(smcconf, + ATMEL_HSMC_TIMINGS_TADL_SHIFT, + ncycles); + /* + * Version 4 of the ONFI spec mandates that tADL be at least 400 + * nanoseconds, but, depending on the master clock rate, 400 ns may not + * fit in the tADL field of the SMC reg. We need to relax the check and + * accept the -ERANGE return code. + * + * Note that previous versions of the ONFI spec had a lower tADL_min + * (100 or 200 ns). It's not clear why this timing constraint got + * increased but it seems most NANDs are fine with values lower than + * 400ns, so we should be safe. + */ + if (ret && ret != -ERANGE) + return ret; + + ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps); + ret = atmel_smc_cs_conf_set_timing(smcconf, + ATMEL_HSMC_TIMINGS_TAR_SHIFT, + ncycles); + if (ret) + return ret; + + ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps); + ret = atmel_smc_cs_conf_set_timing(smcconf, + ATMEL_HSMC_TIMINGS_TRR_SHIFT, + ncycles); + if (ret) + return ret; + + ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps); + ret = atmel_smc_cs_conf_set_timing(smcconf, + ATMEL_HSMC_TIMINGS_TWB_SHIFT, + ncycles); + if (ret) + return ret; + + /* Attach the CS line to the NFC logic. */ + smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL; + + /* Set the appropriate data bus width. */ + if (nand->base.options & NAND_BUSWIDTH_16) + smcconf->mode |= ATMEL_SMC_MODE_DBW_16; + + /* Operate in NRD/NWE READ/WRITEMODE. */ + smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD | + ATMEL_SMC_MODE_WRITEMODE_NWE; + + return 0; +} + +static int +atmel_smc_nand_setup_data_interface(struct atmel_nand *nand, + int csline, + const struct nand_data_interface *conf) +{ + struct atmel_nand_controller *nc; + struct atmel_smc_cs_conf smcconf; + struct atmel_nand_cs *cs; + int ret; + + nc = to_nand_controller(nand->controller); + + ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); + if (ret) + return ret; + + if (csline == NAND_DATA_IFACE_CHECK_ONLY) + return 0; + + cs = &nand->cs[csline]; + cs->smcconf = smcconf; + + atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf); + + return 0; +} + +static int +atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand, + int csline, + const struct nand_data_interface *conf) +{ + struct atmel_hsmc_nand_controller *nc; + struct atmel_smc_cs_conf smcconf; + struct atmel_nand_cs *cs; + int ret; + + nc = to_hsmc_nand_controller(nand->controller); + + ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf); + if (ret) + return ret; + + if (csline == NAND_DATA_IFACE_CHECK_ONLY) + return 0; + + cs = &nand->cs[csline]; + cs->smcconf = smcconf; + + if (cs->rb.type == ATMEL_NAND_NATIVE_RB) + cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id); + + atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id, + &cs->smcconf); + + return 0; +} + +static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline, + const struct nand_data_interface *conf) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_nand_controller *nc; + + nc = to_nand_controller(nand->controller); + + if (csline >= nand->numcs || + (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY)) + return -EINVAL; + + return nc->caps->ops->setup_data_interface(nand, csline, conf); +} + +#define NAND_KEEP_TIMINGS 0x00800000 + +static void atmel_nand_init(struct atmel_nand_controller *nc, + struct atmel_nand *nand) +{ + struct nand_chip *chip = &nand->base; + struct mtd_info *mtd = nand_to_mtd(chip); + + mtd->dev->parent = nc->dev; + nand->controller = &nc->base; + nand->controller = &nc->base; + + chip->cmd_ctrl = atmel_nand_cmd_ctrl; + chip->read_byte = atmel_nand_read_byte; + chip->write_byte = atmel_nand_write_byte; + chip->read_buf = atmel_nand_read_buf; + chip->write_buf = atmel_nand_write_buf; + chip->select_chip = atmel_nand_select_chip; + chip->setup_data_interface = atmel_nand_setup_data_interface; + + if (!nc->mck || !nc->caps->ops->setup_data_interface) + chip->options |= NAND_KEEP_TIMINGS; + + /* Some NANDs require a longer delay than the default one (20us). */ + chip->chip_delay = 40; + + /* Default to HW ECC if pmecc is available. */ + if (nc->pmecc) + chip->ecc.mode = NAND_ECC_HW; +} + +static void atmel_smc_nand_init(struct atmel_nand_controller *nc, + struct atmel_nand *nand) +{ + struct atmel_smc_nand_controller *smc_nc; + int i; + + atmel_nand_init(nc, nand); + + smc_nc = to_smc_nand_controller(nand->controller); + if (!smc_nc->ebi_csa_regmap) + return; + + /* Attach the CS to the NAND Flash logic. */ + for (i = 0; i < nand->numcs; i++) + regmap_update_bits(smc_nc->ebi_csa_regmap, + smc_nc->ebi_csa->offs, + BIT(nand->cs[i].id), BIT(nand->cs[i].id)); + + if (smc_nc->ebi_csa->nfd0_on_d16) + regmap_update_bits(smc_nc->ebi_csa_regmap, + smc_nc->ebi_csa->offs, + smc_nc->ebi_csa->nfd0_on_d16, + smc_nc->ebi_csa->nfd0_on_d16); +} + +static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc, + struct atmel_nand *nand) +{ + struct nand_chip *chip = &nand->base; + + atmel_nand_init(nc, nand); + + /* Overload some methods for the HSMC controller. */ + chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl; + chip->select_chip = atmel_hsmc_nand_select_chip; +} + +static int atmel_nand_controller_remove_nand(struct atmel_nand *nand) +{ + list_del(&nand->node); + + return 0; +} + +static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc, + ofnode np, + int reg_cells) +{ + struct atmel_nand *nand; + ofnode n; + int numcs = 0; + int ret, i; + u32 val; + fdt32_t faddr; + phys_addr_t base; + + /* Count num of nand nodes */ + ofnode_for_each_subnode(n, ofnode_get_parent(np)) + numcs++; + if (numcs < 1) { + dev_err(nc->dev, "Missing or invalid reg property\n"); + return ERR_PTR(-EINVAL); + } + + nand = devm_kzalloc(nc->dev, + sizeof(struct atmel_nand) + + (numcs * sizeof(struct atmel_nand_cs)), + GFP_KERNEL); + if (!nand) { + dev_err(nc->dev, "Failed to allocate NAND object\n"); + return ERR_PTR(-ENOMEM); + } + + nand->numcs = numcs; + + gpio_request_by_name_nodev(np, "det-gpios", 0, &nand->cdgpio, + GPIOD_IS_IN); + + for (i = 0; i < numcs; i++) { + ret = ofnode_read_u32(np, "reg", &val); + if (ret) { + dev_err(nc->dev, "Invalid reg property (err = %d)\n", + ret); + return ERR_PTR(ret); + } + nand->cs[i].id = val; + + /* Read base address */ + struct resource res; + + if (ofnode_read_resource(np, 0, &res)) { + dev_err(nc->dev, "Unable to read resource\n"); + return ERR_PTR(-ENOMEM); + } + + faddr = cpu_to_fdt32(val); + base = ofnode_translate_address(np, &faddr); + nand->cs[i].io.virt = (void *)base; + + if (!ofnode_read_u32(np, "atmel,rb", &val)) { + if (val > ATMEL_NFC_MAX_RB_ID) + return ERR_PTR(-EINVAL); + + nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB; + nand->cs[i].rb.id = val; + } else { + gpio_request_by_name_nodev(np, "rb-gpios", 0, + &nand->cs[i].rb.gpio, + GPIOD_IS_IN); + nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB; + } + + gpio_request_by_name_nodev(np, "cs-gpios", 0, + &nand->cs[i].csgpio, + GPIOD_IS_OUT); + } + + nand_set_flash_node(&nand->base, np); + + return nand; +} + +static int nand_attach(struct nand_chip *chip) +{ + struct atmel_nand *nand = to_atmel_nand(chip); + + if (nand->controller->ops && nand->controller->ops->attach_chip) + return nand->controller->ops->attach_chip(chip); + + return 0; +} + +int atmel_nand_scan(struct mtd_info *mtd, int maxchips) +{ + int ret; + + ret = nand_scan_ident(mtd, maxchips, NULL); + if (ret) + return ret; + + ret = nand_attach(mtd_to_nand(mtd)); + if (ret) + return ret; + + ret = nand_scan_tail(mtd); + return ret; +} + +static int +atmel_nand_controller_add_nand(struct atmel_nand_controller *nc, + struct atmel_nand *nand) +{ + struct nand_chip *chip = &nand->base; + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + /* No card inserted, skip this NAND. */ + if (dm_gpio_is_valid(&nand->cdgpio) && + dm_gpio_get_value(&nand->cdgpio)) { + dev_info(nc->dev, "No SmartMedia card inserted.\n"); + return 0; + } + + nc->caps->ops->nand_init(nc, nand); + + ret = atmel_nand_scan(mtd, nand->numcs); + if (ret) { + dev_err(nc->dev, "NAND scan failed: %d\n", ret); + return ret; + } + + ret = nand_register(0, mtd); + if (ret) { + dev_err(nc->dev, "nand register failed: %d\n", ret); + return ret; + } + + list_add_tail(&nand->node, &nc->chips); + + return 0; +} + +static int +atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc) +{ + struct atmel_nand *nand, *tmp; + int ret; + + list_for_each_entry_safe(nand, tmp, &nc->chips, node) { + ret = atmel_nand_controller_remove_nand(nand); + if (ret) + return ret; + } + + return 0; +} + +static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc) +{ + ofnode np; + ofnode nand_np; + int ret, reg_cells; + u32 val; + + /* TODO: + * Add support for legacy nands + */ + + np = nc->dev->node_; + + ret = ofnode_read_u32(np, "#address-cells", &val); + if (ret) { + dev_err(nc->dev, "missing #address-cells property\n"); + return ret; + } + + reg_cells = val; + + ret = ofnode_read_u32(np, "#size-cells", &val); + if (ret) { + dev_err(nc->dev, "missing #size-cells property\n"); + return ret; + } + + reg_cells += val; + + ofnode_for_each_subnode(nand_np, np) { + struct atmel_nand *nand; + + nand = atmel_nand_create(nc, nand_np, reg_cells); + if (IS_ERR(nand)) { + ret = PTR_ERR(nand); + goto err; + } + + ret = atmel_nand_controller_add_nand(nc, nand); + if (ret) + goto err; + } + + return 0; + +err: + atmel_nand_controller_remove_nands(nc); + + return ret; +} + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = { + .offs = AT91SAM9260_MATRIX_EBICSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = { + .offs = AT91SAM9261_MATRIX_EBICSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = { + .offs = AT91SAM9263_MATRIX_EBI0CSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = { + .offs = AT91SAM9RL_MATRIX_EBICSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = { + .offs = AT91SAM9G45_MATRIX_EBICSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = { + .offs = AT91SAM9N12_MATRIX_EBICSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = { + .offs = AT91SAM9X5_MATRIX_EBICSA, +}; + +static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = { + .offs = AT91_SFR_CCFG_EBICSA, + .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16, +}; + +static const struct udevice_id atmel_ebi_csa_regmap_of_ids[] = { + { + .compatible = "atmel,at91sam9260-matrix", + .data = (ulong)&at91sam9260_ebi_csa, + }, + { + .compatible = "atmel,at91sam9261-matrix", + .data = (ulong)&at91sam9261_ebi_csa, + }, + { + .compatible = "atmel,at91sam9263-matrix", + .data = (ulong)&at91sam9263_ebi_csa, + }, + { + .compatible = "atmel,at91sam9rl-matrix", + .data = (ulong)&at91sam9rl_ebi_csa, + }, + { + .compatible = "atmel,at91sam9g45-matrix", + .data = (ulong)&at91sam9g45_ebi_csa, + }, + { + .compatible = "atmel,at91sam9n12-matrix", + .data = (ulong)&at91sam9n12_ebi_csa, + }, + { + .compatible = "atmel,at91sam9x5-matrix", + .data = (ulong)&at91sam9x5_ebi_csa, + }, + { + .compatible = "microchip,sam9x60-sfr", + .data = (ulong)&sam9x60_ebi_csa, + }, + { /* sentinel */ }, +}; + +static int atmel_nand_attach_chip(struct nand_chip *chip) +{ + struct atmel_nand *nand = to_atmel_nand(chip); + struct atmel_nand_controller *nc = to_nand_controller(nand->controller); + struct mtd_info *mtd = nand_to_mtd(chip); + int ret; + + ret = nc->caps->ops->ecc_init(chip); + if (ret) + return ret; + + if (nc->caps->legacy_of_bindings || !ofnode_valid(nc->dev->node_)) { + /* + * We keep the MTD name unchanged to avoid breaking platforms + * where the MTD cmdline parser is used and the bootloader + * has not been updated to use the new naming scheme. + */ + mtd->name = "atmel_nand"; + } else if (!mtd->name) { + /* + * If the new bindings are used and the bootloader has not been + * updated to pass a new mtdparts parameter on the cmdline, you + * should define the following property in your nand node: + * + * label = "atmel_nand"; + * + * This way, mtd->name will be set by the core when + * nand_set_flash_node() is called. + */ + sprintf(mtd->name, "%s:nand.%d", nc->dev->name, nand->cs[0].id); + } + + return 0; +} + +static const struct nand_controller_ops atmel_nand_controller_ops = { + .attach_chip = atmel_nand_attach_chip, +}; + +static int +atmel_nand_controller_init(struct atmel_nand_controller *nc, + struct udevice *dev, + const struct atmel_nand_controller_caps *caps) +{ + struct ofnode_phandle_args args; + int ret; + + nc->base.ops = &atmel_nand_controller_ops; + INIT_LIST_HEAD(&nc->chips); + nc->dev = dev; + nc->caps = caps; + + nc->pmecc = devm_atmel_pmecc_get(dev); + if (IS_ERR(nc->pmecc)) { + ret = PTR_ERR(nc->pmecc); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Could not get PMECC object (err = %d)\n", + ret); + return ret; + } + + /* We do not retrieve the SMC syscon when parsing old DTs. */ + if (nc->caps->legacy_of_bindings) + return 0; + + nc->mck = devm_kzalloc(dev, sizeof(nc->mck), GFP_KERNEL); + if (!nc->mck) + return -ENOMEM; + + clk_get_by_index(dev->parent, 0, nc->mck); + if (IS_ERR(nc->mck)) { + dev_err(dev, "Failed to retrieve MCK clk\n"); + return PTR_ERR(nc->mck); + } + + ret = ofnode_parse_phandle_with_args(dev->parent->node_, + "atmel,smc", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Missing or invalid atmel,smc property\n"); + return -EINVAL; + } + + nc->smc = syscon_node_to_regmap(args.node); + if (IS_ERR(nc->smc)) { + ret = PTR_ERR(nc->smc); + dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret); + return 0; + } + + return 0; +} + +static int +atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc) +{ + struct udevice *dev = nc->base.dev; + struct ofnode_phandle_args args; + const struct udevice_id *match = NULL; + const char *name; + int ret; + int len; + int i; + + /* We do not retrieve the EBICSA regmap when parsing old DTs. */ + if (nc->base.caps->legacy_of_bindings) + return 0; + + ret = ofnode_parse_phandle_with_args(dev->parent->node_, + nc->base.caps->ebi_csa_regmap_name, + NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Unable to read ebi csa regmap\n"); + return -EINVAL; + } + + name = ofnode_get_property(args.node, "compatible", &len); + + for (i = 0; i < ARRAY_SIZE(atmel_ebi_csa_regmap_of_ids); i++) { + if (!strcmp(name, atmel_ebi_csa_regmap_of_ids[i].compatible)) { + match = &atmel_ebi_csa_regmap_of_ids[i]; + break; + } + } + + if (!match) { + dev_err(dev, "Unable to find ebi csa conf"); + return -EINVAL; + } + nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data; + + nc->ebi_csa_regmap = syscon_node_to_regmap(args.node); + if (IS_ERR(nc->ebi_csa_regmap)) { + ret = PTR_ERR(nc->ebi_csa_regmap); + dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret); + return ret; + } + + /* TODO: + * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1 + * add 4 to ->ebi_csa->offs. + */ + + return 0; +} + +static int atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc) +{ + struct udevice *dev = nc->base.dev; + struct ofnode_phandle_args args; + struct clk smc_clk; + int ret; + u32 addr; + + ret = ofnode_parse_phandle_with_args(dev->parent->node_, + "atmel,smc", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Missing or invalid atmel,smc property\n"); + return -EINVAL; + } + + nc->hsmc_layout = atmel_hsmc_get_reg_layout(args.node); + if (IS_ERR(nc->hsmc_layout)) { + dev_err(dev, "Could not get hsmc layout\n"); + return -EINVAL; + } + + /* Enable smc clock */ + ret = clk_get_by_index_nodev(args.node, 0, &smc_clk); + if (ret) { + dev_err(dev, "Unable to get smc clock (err = %d)", ret); + return ret; + } + + ret = clk_prepare_enable(&smc_clk); + if (ret) + return ret; + + ret = ofnode_parse_phandle_with_args(dev->node_, + "atmel,nfc-io", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Missing or invalid atmel,nfc-io property\n"); + return -EINVAL; + } + + nc->io = syscon_node_to_regmap(args.node); + if (IS_ERR(nc->io)) { + ret = PTR_ERR(nc->io); + dev_err(dev, "Could not get NFC IO regmap\n"); + return ret; + } + + ret = ofnode_parse_phandle_with_args(dev->node_, + "atmel,nfc-sram", NULL, 0, 0, &args); + if (ret) { + dev_err(dev, "Missing or invalid atmel,nfc-sram property\n"); + return ret; + } + + ret = ofnode_read_u32(args.node, "reg", &addr); + if (ret) { + dev_err(dev, "Could not read reg addr of nfc sram"); + return ret; + } + nc->sram.virt = (void *)addr; + + return 0; +} + +static int +atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc) +{ + struct atmel_hsmc_nand_controller *hsmc_nc; + int ret; + + ret = atmel_nand_controller_remove_nands(nc); + if (ret) + return ret; + + hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base); + + if (hsmc_nc->clk) { + clk_disable_unprepare(hsmc_nc->clk); + devm_clk_put(nc->dev, hsmc_nc->clk); + } + + return 0; +} + +static int +atmel_hsmc_nand_controller_probe(struct udevice *dev, + const struct atmel_nand_controller_caps *caps) +{ + struct atmel_hsmc_nand_controller *nc; + int ret; + + nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL); + if (!nc) + return -ENOMEM; + + ret = atmel_nand_controller_init(&nc->base, dev, caps); + if (ret) + return ret; + + ret = atmel_hsmc_nand_controller_init(nc); + if (ret) + return ret; + + /* Make sure all irqs are masked before registering our IRQ handler. */ + regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff); + + /* Initial NFC configuration. */ + regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, + ATMEL_HSMC_NFC_CFG_DTO_MAX); + + ret = atmel_nand_controller_add_nands(&nc->base); + if (ret) + goto err; + + return 0; + +err: + atmel_hsmc_nand_controller_remove(&nc->base); + + return ret; +} + +static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = { + .probe = atmel_hsmc_nand_controller_probe, + .remove = atmel_hsmc_nand_controller_remove, + .ecc_init = atmel_hsmc_nand_ecc_init, + .nand_init = atmel_hsmc_nand_init, + .setup_data_interface = atmel_hsmc_nand_setup_data_interface, +}; + +static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = { + .has_dma = true, + .ale_offs = BIT(21), + .cle_offs = BIT(22), + .ops = &atmel_hsmc_nc_ops, +}; + +static int +atmel_smc_nand_controller_probe(struct udevice *dev, + const struct atmel_nand_controller_caps *caps) +{ + struct atmel_smc_nand_controller *nc; + int ret; + + nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL); + if (!nc) + return -ENOMEM; + + ret = atmel_nand_controller_init(&nc->base, dev, caps); + if (ret) + return ret; + + ret = atmel_smc_nand_controller_init(nc); + if (ret) + return ret; + + return atmel_nand_controller_add_nands(&nc->base); +} + +static int +atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc) +{ + int ret; + + ret = atmel_nand_controller_remove_nands(nc); + if (ret) + return ret; + + return 0; +} + +/* + * The SMC reg layout of at91rm9200 is completely different which prevents us + * from re-using atmel_smc_nand_setup_data_interface() for the + * ->setup_data_interface() hook. + * At this point, there's no support for the at91rm9200 SMC IP, so we leave + * ->setup_data_interface() unassigned. + */ +static const struct atmel_nand_controller_ops at91rm9200_nc_ops = { + .probe = atmel_smc_nand_controller_probe, + .remove = atmel_smc_nand_controller_remove, + .ecc_init = atmel_nand_ecc_init, + .nand_init = atmel_smc_nand_init, +}; + +static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = { + .ale_offs = BIT(21), + .cle_offs = BIT(22), + .ebi_csa_regmap_name = "atmel,matrix", + .ops = &at91rm9200_nc_ops, +}; + +static const struct atmel_nand_controller_ops atmel_smc_nc_ops = { + .probe = atmel_smc_nand_controller_probe, + .remove = atmel_smc_nand_controller_remove, + .ecc_init = atmel_nand_ecc_init, + .nand_init = atmel_smc_nand_init, + .setup_data_interface = atmel_smc_nand_setup_data_interface, +}; + +static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = { + .ale_offs = BIT(21), + .cle_offs = BIT(22), + .ebi_csa_regmap_name = "atmel,matrix", + .ops = &atmel_smc_nc_ops, +}; + +static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = { + .ale_offs = BIT(22), + .cle_offs = BIT(21), + .ebi_csa_regmap_name = "atmel,matrix", + .ops = &atmel_smc_nc_ops, +}; + +static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = { + .has_dma = true, + .ale_offs = BIT(21), + .cle_offs = BIT(22), + .ebi_csa_regmap_name = "atmel,matrix", + .ops = &atmel_smc_nc_ops, +}; + +static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = { + .has_dma = true, + .ale_offs = BIT(21), + .cle_offs = BIT(22), + .ebi_csa_regmap_name = "microchip,sfr", + .ops = &atmel_smc_nc_ops, +}; + +/* Only used to parse old bindings. */ +static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = { + .ale_offs = BIT(21), + .cle_offs = BIT(22), + .ops = &atmel_smc_nc_ops, + .legacy_of_bindings = true, +}; + +static const struct udevice_id atmel_nand_controller_of_ids[] = { + { + .compatible = "atmel,at91rm9200-nand-controller", + .data = (ulong)&atmel_rm9200_nc_caps, + }, + { + .compatible = "atmel,at91sam9260-nand-controller", + .data = (ulong)&atmel_sam9260_nc_caps, + }, + { + .compatible = "atmel,at91sam9261-nand-controller", + .data = (ulong)&atmel_sam9261_nc_caps, + }, + { + .compatible = "atmel,at91sam9g45-nand-controller", + .data = (ulong)&atmel_sam9g45_nc_caps, + }, + { + .compatible = "atmel,sama5d3-nand-controller", + .data = (ulong)&atmel_sama5_nc_caps, + }, + { + .compatible = "microchip,sam9x60-nand-controller", + .data = (ulong)µchip_sam9x60_nc_caps, + }, + /* Support for old/deprecated bindings: */ + { + .compatible = "atmel,at91rm9200-nand", + .data = (ulong)&atmel_rm9200_nand_caps, + }, + { + .compatible = "atmel,sama5d4-nand", + .data = (ulong)&atmel_rm9200_nand_caps, + }, + { + .compatible = "atmel,sama5d2-nand", + .data = (ulong)&atmel_rm9200_nand_caps, + }, + { /* sentinel */ }, +}; + +static int atmel_nand_controller_probe(struct udevice *dev) +{ + const struct atmel_nand_controller_caps *caps; + struct udevice *pmecc_dev; + + caps = (struct atmel_nand_controller_caps *)dev_get_driver_data(dev); + if (!caps) { + printf("Could not retrieve NFC caps\n"); + return -EINVAL; + } + + /* Probe pmecc driver */ + if (uclass_get_device(UCLASS_MTD, 1, &pmecc_dev)) { + printf("%s: get device fail\n", __func__); + return -EINVAL; + } + + return caps->ops->probe(dev, caps); +} + +static int atmel_nand_controller_remove(struct udevice *dev) +{ + struct atmel_nand_controller *nc; + + nc = (struct atmel_nand_controller *)dev_get_driver_data(dev); + + return nc->caps->ops->remove(nc); +} + +U_BOOT_DRIVER(atmel_nand_controller) = { + .name = "atmel-nand-controller", + .id = UCLASS_MTD, + .of_match = atmel_nand_controller_of_ids, + .probe = atmel_nand_controller_probe, + .remove = atmel_nand_controller_remove, +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(atmel_nand_controller), + &dev); + if (ret && ret != -ENODEV) + printf("Failed to initialize NAND controller. (error %d)\n", + ret); +} From a490e1b7c017c7eb5aa8ae3ad939ba26da64f3f9 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:02 +0530 Subject: [PATCH 126/424] nand: atmel: Add pmecc driver Add driver for atmel pmecc. This implementation is ported from Linux. The reference taken is linux-5.4-at91. Signed-off-by: Balamanikandan Gunasundar --- drivers/mtd/nand/raw/atmel/Makefile | 3 +- drivers/mtd/nand/raw/atmel/pmecc.c | 965 ++++++++++++++++++++++++++++ drivers/mtd/nand/raw/atmel/pmecc.h | 94 +++ 3 files changed, 1061 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.c create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.h diff --git a/drivers/mtd/nand/raw/atmel/Makefile b/drivers/mtd/nand/raw/atmel/Makefile index 6708416983..e044ff55ba 100644 --- a/drivers/mtd/nand/raw/atmel/Makefile +++ b/drivers/mtd/nand/raw/atmel/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_DM_NAND_ATMEL) += atmel-nand-controller.o +obj-$(CONFIG_DM_NAND_ATMEL) += atmel-nand-controller.o atmel-pmecc.o atmel-nand-controller-objs := nand-controller.o +atmel-pmecc-objs := pmecc.o diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c new file mode 100644 index 0000000000..e2e3f1ee6b --- /dev/null +++ b/drivers/mtd/nand/raw/atmel/pmecc.c @@ -0,0 +1,965 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2017 ATMEL + * Copyright 2017 Free Electrons + * + * Author: Boris Brezillon + * + * Derived from the atmel_nand.c driver which contained the following + * copyrights: + * + * Copyright 2003 Rick Bronson + * + * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8) + * Copyright 2001 Thomas Gleixner (gleixner@autronix.de) + * + * Derived from drivers/mtd/spia.c (removed in v3.8) + * Copyright 2000 Steven J. Hill (sjhill@cotw.com) + * + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007 + * + * Derived from Das U-Boot source code + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) + * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * Add Programmable Multibit ECC support for various AT91 SoC + * Copyright 2012 ATMEL, Hong Xu + * + * Add Nand Flash Controller support for SAMA5 SoC + * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) + * + * The PMECC is an hardware assisted BCH engine, which means part of the + * ECC algorithm is left to the software. The hardware/software repartition + * is explained in the "PMECC Controller Functional Description" chapter in + * Atmel datasheets, and some of the functions in this file are directly + * implementing the algorithms described in the "Software Implementation" + * sub-section. + * + * TODO: it seems that the software BCH implementation in lib/bch.c is already + * providing some of the logic we are implementing here. It would be smart + * to expose the needed lib/bch.c helpers/functions and re-use them here. + */ +#include +#include +#include +#include +#include +#include "pmecc.h" +#include +#include +#include +#include + +/* Galois field dimension */ +#define PMECC_GF_DIMENSION_13 13 +#define PMECC_GF_DIMENSION_14 14 + +/* Primitive Polynomial used by PMECC */ +#define PMECC_GF_13_PRIMITIVE_POLY 0x201b +#define PMECC_GF_14_PRIMITIVE_POLY 0x4443 + +#define PMECC_LOOKUP_TABLE_SIZE_512 0x2000 +#define PMECC_LOOKUP_TABLE_SIZE_1024 0x4000 + +/* Time out value for reading PMECC status register */ +#define PMECC_MAX_TIMEOUT_MS 100 + +/* PMECC Register Definitions */ +#define ATMEL_PMECC_CFG 0x0 +#define PMECC_CFG_BCH_STRENGTH(x) (x) +#define PMECC_CFG_BCH_STRENGTH_MASK GENMASK(2, 0) +#define PMECC_CFG_SECTOR512 (0 << 4) +#define PMECC_CFG_SECTOR1024 BIT(4) +#define PMECC_CFG_NSECTORS(x) ((fls(x) - 1) << 8) +#define PMECC_CFG_READ_OP (0 << 12) +#define PMECC_CFG_WRITE_OP BIT(12) +#define PMECC_CFG_SPARE_ENABLE BIT(16) +#define PMECC_CFG_AUTO_ENABLE BIT(20) + +#define ATMEL_PMECC_SAREA 0x4 +#define ATMEL_PMECC_SADDR 0x8 +#define ATMEL_PMECC_EADDR 0xc + +#define ATMEL_PMECC_CLK 0x10 +#define PMECC_CLK_133MHZ (2 << 0) + +#define ATMEL_PMECC_CTRL 0x14 +#define PMECC_CTRL_RST BIT(0) +#define PMECC_CTRL_DATA BIT(1) +#define PMECC_CTRL_USER BIT(2) +#define PMECC_CTRL_ENABLE BIT(4) +#define PMECC_CTRL_DISABLE BIT(5) + +#define ATMEL_PMECC_SR 0x18 +#define PMECC_SR_BUSY BIT(0) +#define PMECC_SR_ENABLE BIT(4) + +#define ATMEL_PMECC_IER 0x1c +#define ATMEL_PMECC_IDR 0x20 +#define ATMEL_PMECC_IMR 0x24 +#define ATMEL_PMECC_ISR 0x28 +#define PMECC_ERROR_INT BIT(0) + +#define ATMEL_PMECC_ECC(sector, n) \ + ((((sector) + 1) * 0x40) + (n)) + +#define ATMEL_PMECC_REM(sector, n) \ + ((((sector) + 1) * 0x40) + ((n) * 4) + 0x200) + +/* PMERRLOC Register Definitions */ +#define ATMEL_PMERRLOC_ELCFG 0x0 +#define PMERRLOC_ELCFG_SECTOR_512 (0 << 0) +#define PMERRLOC_ELCFG_SECTOR_1024 BIT(0) +#define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16) + +#define ATMEL_PMERRLOC_ELPRIM 0x4 +#define ATMEL_PMERRLOC_ELEN 0x8 +#define ATMEL_PMERRLOC_ELDIS 0xc +#define PMERRLOC_DISABLE BIT(0) + +#define ATMEL_PMERRLOC_ELSR 0x10 +#define PMERRLOC_ELSR_BUSY BIT(0) + +#define ATMEL_PMERRLOC_ELIER 0x14 +#define ATMEL_PMERRLOC_ELIDR 0x18 +#define ATMEL_PMERRLOC_ELIMR 0x1c +#define ATMEL_PMERRLOC_ELISR 0x20 +#define PMERRLOC_ERR_NUM_MASK GENMASK(12, 8) +#define PMERRLOC_CALC_DONE BIT(0) + +#define ATMEL_PMERRLOC_SIGMA(x) (((x) * 0x4) + 0x28) + +#define ATMEL_PMERRLOC_EL(offs, x) (((x) * 0x4) + (offs)) + +struct atmel_pmecc_gf_tables { + u16 *alpha_to; + u16 *index_of; +}; + +struct atmel_pmecc_caps { + const int *strengths; + int nstrengths; + int el_offset; + bool correct_erased_chunks; +}; + +struct atmel_pmecc_user_conf_cache { + u32 cfg; + u32 sarea; + u32 saddr; + u32 eaddr; +}; + +struct atmel_pmecc_user { + struct atmel_pmecc_user_conf_cache cache; + struct atmel_pmecc *pmecc; + const struct atmel_pmecc_gf_tables *gf_tables; + int eccbytes; + s16 *partial_syn; + s16 *si; + s16 *lmu; + s16 *smu; + s32 *mu; + s32 *dmu; + s32 *delta; + u32 isr; +}; + +/* Serialize table access */ +DEFINE_MUTEX(pmecc_gf_tables_lock); +static const struct atmel_pmecc_gf_tables *pmecc_gf_tables_512; +static const struct atmel_pmecc_gf_tables *pmecc_gf_tables_1024; + +static inline int deg(unsigned int poly) +{ + /* polynomial degree is the most-significant bit index */ + return fls(poly) - 1; +} + +static int atmel_pmecc_build_gf_tables(int mm, unsigned int poly, + struct atmel_pmecc_gf_tables *gf_tables) +{ + unsigned int i, x = 1; + const unsigned int k = BIT(deg(poly)); + unsigned int nn = BIT(mm) - 1; + + /* primitive polynomial must be of degree m */ + if (k != (1u << mm)) + return -EINVAL; + + for (i = 0; i < nn; i++) { + gf_tables->alpha_to[i] = x; + gf_tables->index_of[x] = i; + if (i && (x == 1)) + /* polynomial is not primitive (a^i=1 with 0alpha_to[nn] = 1; + gf_tables->index_of[0] = 0; + + return 0; +} + +static const struct atmel_pmecc_gf_tables * +atmel_pmecc_create_gf_tables(const struct atmel_pmecc_user_req *req) +{ + struct atmel_pmecc_gf_tables *gf_tables; + unsigned int poly, degree, table_size; + int ret; + + if (req->ecc.sectorsize == 512) { + degree = PMECC_GF_DIMENSION_13; + poly = PMECC_GF_13_PRIMITIVE_POLY; + table_size = PMECC_LOOKUP_TABLE_SIZE_512; + } else { + degree = PMECC_GF_DIMENSION_14; + poly = PMECC_GF_14_PRIMITIVE_POLY; + table_size = PMECC_LOOKUP_TABLE_SIZE_1024; + } + + gf_tables = kzalloc(sizeof(*gf_tables) + + (2 * table_size * sizeof(u16)), + GFP_KERNEL); + if (!gf_tables) + return ERR_PTR(-ENOMEM); + + gf_tables->alpha_to = (void *)(gf_tables + 1); + gf_tables->index_of = gf_tables->alpha_to + table_size; + + ret = atmel_pmecc_build_gf_tables(degree, poly, gf_tables); + if (ret) { + kfree(gf_tables); + return ERR_PTR(ret); + } + + return gf_tables; +} + +static const struct atmel_pmecc_gf_tables * +atmel_pmecc_get_gf_tables(const struct atmel_pmecc_user_req *req) +{ + const struct atmel_pmecc_gf_tables **gf_tables, *ret; + + mutex_lock(&pmecc_gf_tables_lock); + if (req->ecc.sectorsize == 512) + gf_tables = &pmecc_gf_tables_512; + else + gf_tables = &pmecc_gf_tables_1024; + + ret = *gf_tables; + + if (!ret) { + ret = atmel_pmecc_create_gf_tables(req); + if (!IS_ERR(ret)) + *gf_tables = ret; + } + mutex_unlock(&pmecc_gf_tables_lock); + + return ret; +} + +static int atmel_pmecc_prepare_user_req(struct atmel_pmecc *pmecc, + struct atmel_pmecc_user_req *req) +{ + int i, max_eccbytes, eccbytes = 0, eccstrength = 0; + + if (req->pagesize <= 0 || req->oobsize <= 0 || req->ecc.bytes <= 0) + return -EINVAL; + + if (req->ecc.ooboffset >= 0 && + req->ecc.ooboffset + req->ecc.bytes > req->oobsize) + return -EINVAL; + + if (req->ecc.sectorsize == ATMEL_PMECC_SECTOR_SIZE_AUTO) { + if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH) + return -EINVAL; + + if (req->pagesize > 512) + req->ecc.sectorsize = 1024; + else + req->ecc.sectorsize = 512; + } + + if (req->ecc.sectorsize != 512 && req->ecc.sectorsize != 1024) + return -EINVAL; + + if (req->pagesize % req->ecc.sectorsize) + return -EINVAL; + + req->ecc.nsectors = req->pagesize / req->ecc.sectorsize; + + max_eccbytes = req->ecc.bytes; + + for (i = 0; i < pmecc->caps->nstrengths; i++) { + int nbytes, strength = pmecc->caps->strengths[i]; + + if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH && + strength < req->ecc.strength) + continue; + + nbytes = DIV_ROUND_UP(strength * fls(8 * req->ecc.sectorsize), + 8); + nbytes *= req->ecc.nsectors; + + if (nbytes > max_eccbytes) + break; + + eccstrength = strength; + eccbytes = nbytes; + + if (req->ecc.strength != ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH) + break; + } + + if (!eccstrength) + return -EINVAL; + + req->ecc.bytes = eccbytes; + req->ecc.strength = eccstrength; + + if (req->ecc.ooboffset < 0) + req->ecc.ooboffset = req->oobsize - eccbytes; + + return 0; +} + +struct atmel_pmecc_user * +atmel_pmecc_create_user(struct atmel_pmecc *pmecc, + struct atmel_pmecc_user_req *req) +{ + struct atmel_pmecc_user *user; + const struct atmel_pmecc_gf_tables *gf_tables; + int strength, size, ret; + + ret = atmel_pmecc_prepare_user_req(pmecc, req); + if (ret) + return ERR_PTR(ret); + + size = sizeof(*user); + size = ALIGN(size, sizeof(u16)); + /* Reserve space for partial_syn, si and smu */ + size += ((2 * req->ecc.strength) + 1) * sizeof(u16) * + (2 + req->ecc.strength + 2); + /* Reserve space for lmu. */ + size += (req->ecc.strength + 1) * sizeof(u16); + /* Reserve space for mu, dmu and delta. */ + size = ALIGN(size, sizeof(s32)); + size += (req->ecc.strength + 1) * sizeof(s32) * 3; + + user = kzalloc(size, GFP_KERNEL); + if (!user) + return ERR_PTR(-ENOMEM); + + user->pmecc = pmecc; + + user->partial_syn = (s16 *)PTR_ALIGN(user + 1, sizeof(u16)); + user->si = user->partial_syn + ((2 * req->ecc.strength) + 1); + user->lmu = user->si + ((2 * req->ecc.strength) + 1); + user->smu = user->lmu + (req->ecc.strength + 1); + user->mu = (s32 *)PTR_ALIGN(user->smu + + (((2 * req->ecc.strength) + 1) * + (req->ecc.strength + 2)), + sizeof(s32)); + user->dmu = user->mu + req->ecc.strength + 1; + user->delta = user->dmu + req->ecc.strength + 1; + + gf_tables = atmel_pmecc_get_gf_tables(req); + if (IS_ERR(gf_tables)) { + kfree(user); + return ERR_CAST(gf_tables); + } + + user->gf_tables = gf_tables; + + user->eccbytes = req->ecc.bytes / req->ecc.nsectors; + + for (strength = 0; strength < pmecc->caps->nstrengths; strength++) { + if (pmecc->caps->strengths[strength] == req->ecc.strength) + break; + } + + user->cache.cfg = PMECC_CFG_BCH_STRENGTH(strength) | + PMECC_CFG_NSECTORS(req->ecc.nsectors); + + if (req->ecc.sectorsize == 1024) + user->cache.cfg |= PMECC_CFG_SECTOR1024; + + user->cache.sarea = req->oobsize - 1; + user->cache.saddr = req->ecc.ooboffset; + user->cache.eaddr = req->ecc.ooboffset + req->ecc.bytes - 1; + + return user; +} +EXPORT_SYMBOL_GPL(atmel_pmecc_create_user); + +void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user) +{ + kfree(user); +} +EXPORT_SYMBOL_GPL(atmel_pmecc_destroy_user); + +static int get_strength(struct atmel_pmecc_user *user) +{ + const int *strengths = user->pmecc->caps->strengths; + + return strengths[user->cache.cfg & PMECC_CFG_BCH_STRENGTH_MASK]; +} + +static int get_sectorsize(struct atmel_pmecc_user *user) +{ + return user->cache.cfg & PMECC_CFG_SECTOR1024 ? 1024 : 512; +} + +static void atmel_pmecc_gen_syndrome(struct atmel_pmecc_user *user, int sector) +{ + int strength = get_strength(user); + u32 value; + int i; + + /* Fill odd syndromes */ + for (i = 0; i < strength; i++) { + value = readl_relaxed(user->pmecc->regs.base + + ATMEL_PMECC_REM(sector, i / 2)); + if (i & 1) + value >>= 16; + + user->partial_syn[(2 * i) + 1] = value; + } +} + +static void atmel_pmecc_substitute(struct atmel_pmecc_user *user) +{ + int degree = get_sectorsize(user) == 512 ? 13 : 14; + int cw_len = BIT(degree) - 1; + int strength = get_strength(user); + s16 *alpha_to = (s16 *)user->gf_tables->alpha_to; + s16 *index_of = (s16 *)user->gf_tables->index_of; + s16 *partial_syn = user->partial_syn; + s16 *si; + int i, j; + + /* + * si[] is a table that holds the current syndrome value, + * an element of that table belongs to the field + */ + si = user->si; + + memset(&si[1], 0, sizeof(s16) * ((2 * strength) - 1)); + + /* Computation 2t syndromes based on S(x) */ + /* Odd syndromes */ + for (i = 1; i < 2 * strength; i += 2) { + for (j = 0; j < degree; j++) { + if (partial_syn[i] & BIT(j)) + si[i] = alpha_to[i * j] ^ si[i]; + } + } + /* Even syndrome = (Odd syndrome) ** 2 */ + for (i = 2, j = 1; j <= strength; i = ++j << 1) { + if (si[j] == 0) { + si[i] = 0; + } else { + s16 tmp; + + tmp = index_of[si[j]]; + tmp = (tmp * 2) % cw_len; + si[i] = alpha_to[tmp]; + } + } +} + +static void atmel_pmecc_get_sigma(struct atmel_pmecc_user *user) +{ + s16 *lmu = user->lmu; + s16 *si = user->si; + s32 *mu = user->mu; + s32 *dmu = user->dmu; + s32 *delta = user->delta; + int degree = get_sectorsize(user) == 512 ? 13 : 14; + int cw_len = BIT(degree) - 1; + int strength = get_strength(user); + int num = 2 * strength + 1; + s16 *index_of = (s16 *)user->gf_tables->index_of; + s16 *alpha_to = (s16 *)user->gf_tables->alpha_to; + int i, j, k; + u32 dmu_0_count, tmp; + s16 *smu = user->smu; + + /* index of largest delta */ + int ro; + int largest; + int diff; + + dmu_0_count = 0; + + /* First Row */ + + /* Mu */ + mu[0] = -1; + + memset(smu, 0, sizeof(s16) * num); + smu[0] = 1; + + /* discrepancy set to 1 */ + dmu[0] = 1; + /* polynom order set to 0 */ + lmu[0] = 0; + delta[0] = (mu[0] * 2 - lmu[0]) >> 1; + + /* Second Row */ + + /* Mu */ + mu[1] = 0; + /* Sigma(x) set to 1 */ + memset(&smu[num], 0, sizeof(s16) * num); + smu[num] = 1; + + /* discrepancy set to S1 */ + dmu[1] = si[1]; + + /* polynom order set to 0 */ + lmu[1] = 0; + + delta[1] = (mu[1] * 2 - lmu[1]) >> 1; + + /* Init the Sigma(x) last row */ + memset(&smu[(strength + 1) * num], 0, sizeof(s16) * num); + + for (i = 1; i <= strength; i++) { + mu[i + 1] = i << 1; + /* Begin Computing Sigma (Mu+1) and L(mu) */ + /* check if discrepancy is set to 0 */ + if (dmu[i] == 0) { + dmu_0_count++; + + tmp = ((strength - (lmu[i] >> 1) - 1) / 2); + if ((strength - (lmu[i] >> 1) - 1) & 0x1) + tmp += 2; + else + tmp += 1; + + if (dmu_0_count == tmp) { + for (j = 0; j <= (lmu[i] >> 1) + 1; j++) + smu[(strength + 1) * num + j] = + smu[i * num + j]; + + lmu[strength + 1] = lmu[i]; + return; + } + + /* copy polynom */ + for (j = 0; j <= lmu[i] >> 1; j++) + smu[(i + 1) * num + j] = smu[i * num + j]; + + /* copy previous polynom order to the next */ + lmu[i + 1] = lmu[i]; + } else { + ro = 0; + largest = -1; + /* find largest delta with dmu != 0 */ + for (j = 0; j < i; j++) { + if ((dmu[j]) && (delta[j] > largest)) { + largest = delta[j]; + ro = j; + } + } + + /* compute difference */ + diff = (mu[i] - mu[ro]); + + /* Compute degree of the new smu polynomial */ + if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff)) + lmu[i + 1] = lmu[i]; + else + lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2; + + /* Init smu[i+1] with 0 */ + for (k = 0; k < num; k++) + smu[(i + 1) * num + k] = 0; + + /* Compute smu[i+1] */ + for (k = 0; k <= lmu[ro] >> 1; k++) { + s16 a, b, c; + + if (!(smu[ro * num + k] && dmu[i])) + continue; + + a = index_of[dmu[i]]; + b = index_of[dmu[ro]]; + c = index_of[smu[ro * num + k]]; + tmp = a + (cw_len - b) + c; + a = alpha_to[tmp % cw_len]; + smu[(i + 1) * num + (k + diff)] = a; + } + + for (k = 0; k <= lmu[i] >> 1; k++) + smu[(i + 1) * num + k] ^= smu[i * num + k]; + } + + /* End Computing Sigma (Mu+1) and L(mu) */ + /* In either case compute delta */ + delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1; + + /* Do not compute discrepancy for the last iteration */ + if (i >= strength) + continue; + + for (k = 0; k <= (lmu[i + 1] >> 1); k++) { + tmp = 2 * (i - 1); + if (k == 0) { + dmu[i + 1] = si[tmp + 3]; + } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) { + s16 a, b, c; + + a = index_of[smu[(i + 1) * num + k]]; + b = si[2 * (i - 1) + 3 - k]; + c = index_of[b]; + tmp = a + c; + tmp %= cw_len; + dmu[i + 1] = alpha_to[tmp] ^ dmu[i + 1]; + } + } + } +} + +static int atmel_pmecc_err_location(struct atmel_pmecc_user *user) +{ + int sector_size = get_sectorsize(user); + int degree = sector_size == 512 ? 13 : 14; + struct atmel_pmecc *pmecc = user->pmecc; + int strength = get_strength(user); + int ret, roots_nbr, i, err_nbr = 0; + int num = (2 * strength) + 1; + s16 *smu = user->smu; + u32 val; + + writel(PMERRLOC_DISABLE, pmecc->regs.errloc + ATMEL_PMERRLOC_ELDIS); + + for (i = 0; i <= user->lmu[strength + 1] >> 1; i++) { + writel_relaxed(smu[(strength + 1) * num + i], + pmecc->regs.errloc + ATMEL_PMERRLOC_SIGMA(i)); + err_nbr++; + } + + val = (err_nbr - 1) << 16; + if (sector_size == 1024) + val |= 1; + + writel(val, pmecc->regs.errloc + ATMEL_PMERRLOC_ELCFG); + writel((sector_size * 8) + (degree * strength), + pmecc->regs.errloc + ATMEL_PMERRLOC_ELEN); + + ret = readl_relaxed_poll_timeout(pmecc->regs.errloc + + ATMEL_PMERRLOC_ELISR, + val, val & PMERRLOC_CALC_DONE, + PMECC_MAX_TIMEOUT_MS * 1000); + if (ret) { + dev_err(pmecc->dev, + "PMECC: Timeout to calculate error location.\n"); + return ret; + } + + roots_nbr = (val & PMERRLOC_ERR_NUM_MASK) >> 8; + /* Number of roots == degree of smu hence <= cap */ + if (roots_nbr == user->lmu[strength + 1] >> 1) + return err_nbr - 1; + + /* + * Number of roots does not match the degree of smu + * unable to correct error. + */ + return -EBADMSG; +} + +int atmel_pmecc_correct_sector(struct atmel_pmecc_user *user, int sector, + void *data, void *ecc) +{ + struct atmel_pmecc *pmecc = user->pmecc; + int sectorsize = get_sectorsize(user); + int eccbytes = user->eccbytes; + int i, nerrors; + + if (!(user->isr & BIT(sector))) + return 0; + + atmel_pmecc_gen_syndrome(user, sector); + atmel_pmecc_substitute(user); + atmel_pmecc_get_sigma(user); + + nerrors = atmel_pmecc_err_location(user); + if (nerrors < 0) + return nerrors; + + for (i = 0; i < nerrors; i++) { + const char *area; + int byte, bit; + u32 errpos; + u8 *ptr; + + errpos = readl_relaxed(pmecc->regs.errloc + + ATMEL_PMERRLOC_EL(pmecc->caps->el_offset, i)); + errpos--; + + byte = errpos / 8; + bit = errpos % 8; + + if (byte < sectorsize) { + ptr = data + byte; + area = "data"; + } else if (byte < sectorsize + eccbytes) { + ptr = ecc + byte - sectorsize; + area = "ECC"; + } else { + dev_dbg(pmecc->dev, + "Invalid errpos value (%d, max is %d)\n", + errpos, (sectorsize + eccbytes) * 8); + return -EINVAL; + } + + dev_dbg(pmecc->dev, + "Bit flip in %s area, byte %d: 0x%02x -> 0x%02x\n", + area, byte, *ptr, (unsigned int)(*ptr ^ BIT(bit))); + + *ptr ^= BIT(bit); + } + + return nerrors; +} +EXPORT_SYMBOL_GPL(atmel_pmecc_correct_sector); + +bool atmel_pmecc_correct_erased_chunks(struct atmel_pmecc_user *user) +{ + return user->pmecc->caps->correct_erased_chunks; +} +EXPORT_SYMBOL_GPL(atmel_pmecc_correct_erased_chunks); + +void atmel_pmecc_get_generated_eccbytes(struct atmel_pmecc_user *user, + int sector, void *ecc) +{ + struct atmel_pmecc *pmecc = user->pmecc; + u8 *ptr = ecc; + int i; + + for (i = 0; i < user->eccbytes; i++) + ptr[i] = readb_relaxed(pmecc->regs.base + + ATMEL_PMECC_ECC(sector, i)); +} +EXPORT_SYMBOL_GPL(atmel_pmecc_get_generated_eccbytes); + +void atmel_pmecc_reset(struct atmel_pmecc *pmecc) +{ + writel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL); + writel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); +} +EXPORT_SYMBOL_GPL(atmel_pmecc_reset); + +int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op) +{ + struct atmel_pmecc *pmecc = user->pmecc; + u32 cfg; + + if (op != NAND_ECC_READ && op != NAND_ECC_WRITE) { + dev_err(pmecc->dev, "Bad ECC operation!"); + return -EINVAL; + } + + mutex_lock(&user->pmecc->lock); + + cfg = user->cache.cfg; + if (op == NAND_ECC_WRITE) + cfg |= PMECC_CFG_WRITE_OP; + else + cfg |= PMECC_CFG_AUTO_ENABLE; + + writel(cfg, pmecc->regs.base + ATMEL_PMECC_CFG); + writel(user->cache.sarea, pmecc->regs.base + ATMEL_PMECC_SAREA); + writel(user->cache.saddr, pmecc->regs.base + ATMEL_PMECC_SADDR); + writel(user->cache.eaddr, pmecc->regs.base + ATMEL_PMECC_EADDR); + + writel(PMECC_CTRL_ENABLE, pmecc->regs.base + ATMEL_PMECC_CTRL); + writel(PMECC_CTRL_DATA, pmecc->regs.base + ATMEL_PMECC_CTRL); + + return 0; +} +EXPORT_SYMBOL_GPL(atmel_pmecc_enable); + +void atmel_pmecc_disable(struct atmel_pmecc_user *user) +{ + atmel_pmecc_reset(user->pmecc); + mutex_unlock(&user->pmecc->lock); +} +EXPORT_SYMBOL_GPL(atmel_pmecc_disable); + +int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user) +{ + struct atmel_pmecc *pmecc = user->pmecc; + u32 status; + int ret; + + ret = readl_relaxed_poll_timeout(pmecc->regs.base + + ATMEL_PMECC_SR, + status, !(status & PMECC_SR_BUSY), + PMECC_MAX_TIMEOUT_MS * 1000); + if (ret) { + dev_err(pmecc->dev, + "Timeout while waiting for PMECC ready.\n"); + return ret; + } + + user->isr = readl_relaxed(pmecc->regs.base + ATMEL_PMECC_ISR); + + return 0; +} +EXPORT_SYMBOL_GPL(atmel_pmecc_wait_rdy); + +#define ATMEL_BASE_PMECC 0xffffe000 +#define ATMEL_BASE_PMERRLOC 0xffffe600 + +static struct atmel_pmecc * +atmel_pmecc_create(struct udevice *dev, + const struct atmel_pmecc_caps *caps, + int pmecc_res_idx, int errloc_res_idx, + int timing_res_idx) +{ + struct atmel_pmecc *pmecc; + struct resource res; + + pmecc = devm_kzalloc(dev, sizeof(*pmecc), GFP_KERNEL); + if (!pmecc) + return ERR_PTR(-ENOMEM); + + pmecc->caps = caps; + pmecc->dev = dev; + mutex_init(&pmecc->lock); + + ofnode_read_resource(dev->node_, 0, &res); + pmecc->regs.base = (void *)res.start; + ofnode_read_resource(dev->node_, 1, &res); + pmecc->regs.errloc = (void *)res.start; + + pmecc->regs.timing = 0; + + /* Disable all interrupts before registering the PMECC handler. */ + writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR); + atmel_pmecc_reset(pmecc); + + return pmecc; +} + +static void devm_atmel_pmecc_put(struct udevice *dev, void *res) +{ +} + +static struct atmel_pmecc *atmel_pmecc_get_by_node(struct udevice *dev) +{ + struct atmel_pmecc *pmecc, **ptr; + int ret; + + pmecc = dev_get_plat(dev); + if (!pmecc) { + ret = -EPROBE_DEFER; + goto err_put_device; + } + + ptr = devres_alloc(devm_atmel_pmecc_put, sizeof(*ptr), GFP_KERNEL); + if (!ptr) { + ret = -ENOMEM; + goto err_put_device; + } + + *ptr = pmecc; + + devres_add(dev, ptr); + + return pmecc; + +err_put_device: + return ERR_PTR(ret); +} + +static const int atmel_pmecc_strengths[] = { 2, 4, 8, 12, 24, 32 }; + +static struct atmel_pmecc_caps at91sam9g45_caps = { + .strengths = atmel_pmecc_strengths, + .nstrengths = 5, + .el_offset = 0x8c, +}; + +static struct atmel_pmecc_caps sama5d4_caps = { + .strengths = atmel_pmecc_strengths, + .nstrengths = 5, + .el_offset = 0x8c, + .correct_erased_chunks = true, +}; + +static struct atmel_pmecc_caps sama5d2_caps = { + .strengths = atmel_pmecc_strengths, + .nstrengths = 6, + .el_offset = 0xac, + .correct_erased_chunks = true, +}; + +struct atmel_pmecc *devm_atmel_pmecc_get(struct udevice *userdev) +{ + struct atmel_pmecc *pmecc; + struct ofnode_phandle_args args; + struct udevice *pdev; + int ret; + + if (!userdev) + return ERR_PTR(-EINVAL); + + ret = ofnode_parse_phandle_with_args(userdev->node_, + "ecc-engine", + NULL, 0, 0, &args); + ret = uclass_get_device_by_ofnode(UCLASS_MTD, args.node, &pdev); + if (ret) + return NULL; + + pmecc = atmel_pmecc_get_by_node(pdev); + + /* TODO: + * Support old DT bindings + */ + + return pmecc; +} +EXPORT_SYMBOL(devm_atmel_pmecc_get); + +static const struct udevice_id atmel_pmecc_match[] = { + { .compatible = "atmel,at91sam9g45-pmecc", (ulong)&at91sam9g45_caps }, + { .compatible = "atmel,sama5d4-pmecc", (ulong)&sama5d4_caps }, + { .compatible = "atmel,sama5d2-pmecc", (ulong)&sama5d2_caps }, + { /* sentinel */ } +}; + +static int atmel_pmecc_probe(struct udevice *dev) +{ + const struct atmel_pmecc_caps *caps; + struct atmel_pmecc *pmecc; + + caps = (struct atmel_pmecc_caps *)dev_get_driver_data(dev); + if (!caps) { + dev_err(dev, "Invalid caps\n"); + return -EINVAL; + } + + pmecc = atmel_pmecc_create(dev, caps, 0, 1, 2); + if (IS_ERR(pmecc)) + return PTR_ERR(pmecc); + + dev->plat_ = pmecc; + + return 0; +} + +U_BOOT_DRIVER(atmel_pmecc) = { + .name = "atmel-pmecc", + .id = UCLASS_MTD, + .of_match = atmel_pmecc_match, + .probe = atmel_pmecc_probe, +}; diff --git a/drivers/mtd/nand/raw/atmel/pmecc.h b/drivers/mtd/nand/raw/atmel/pmecc.h new file mode 100644 index 0000000000..43f96b2f16 --- /dev/null +++ b/drivers/mtd/nand/raw/atmel/pmecc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * © Copyright 2016 ATMEL + * © Copyright 2016 Free Electrons + * + * Author: Boris Brezillon + * + * Derived from the atmel_nand.c driver which contained the following + * copyrights: + * + * Copyright © 2003 Rick Bronson + * + * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8) + * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de) + * + * Derived from drivers/mtd/spia.c (removed in v3.8) + * Copyright © 2000 Steven J. Hill (sjhill@cotw.com) + * + * + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 + * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007 + * + * Derived from Das U-Boot source code + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) + * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * Add Programmable Multibit ECC support for various AT91 SoC + * © Copyright 2012 ATMEL, Hong Xu + * + * Add Nand Flash Controller support for SAMA5 SoC + * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) + */ + +#ifndef ATMEL_PMECC_H +#define ATMEL_PMECC_H + +#define ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH 0 +#define ATMEL_PMECC_SECTOR_SIZE_AUTO 0 +#define ATMEL_PMECC_OOBOFFSET_AUTO -1 + +struct atmel_pmecc_user_req { + int pagesize; + int oobsize; + struct { + int strength; + int bytes; + int sectorsize; + int nsectors; + int ooboffset; + } ecc; +}; + +struct atmel_pmecc_suspend_ctx { + u32 setup; + u32 pulse; + u32 cycle; + u32 timings; + u32 mode; +}; + +struct atmel_pmecc { + struct udevice *dev; + const struct atmel_pmecc_caps *caps; + + struct { + void __iomem *base; + void __iomem *errloc; + void __iomem *timing; + } regs; + + /* Mutex used for pmecc enable/disable */ + struct mutex lock; + + struct atmel_pmecc_suspend_ctx suspend; +}; + +struct atmel_pmecc *devm_atmel_pmecc_get(struct udevice *dev); + +struct atmel_pmecc_user * +atmel_pmecc_create_user(struct atmel_pmecc *pmecc, + struct atmel_pmecc_user_req *req); +void atmel_pmecc_destroy_user(struct atmel_pmecc_user *user); + +void atmel_pmecc_reset(struct atmel_pmecc *pmecc); +int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op); +void atmel_pmecc_disable(struct atmel_pmecc_user *user); +int atmel_pmecc_wait_rdy(struct atmel_pmecc_user *user); +int atmel_pmecc_correct_sector(struct atmel_pmecc_user *user, int sector, + void *data, void *ecc); +bool atmel_pmecc_correct_erased_chunks(struct atmel_pmecc_user *user); +void atmel_pmecc_get_generated_eccbytes(struct atmel_pmecc_user *user, + int sector, void *ecc); + +#endif /* ATMEL_PMECC_H */ From de32a2a32aec6ba82fc60c15bef4750ee6729826 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:03 +0530 Subject: [PATCH 127/424] mfd: syscon: Add atmel-matrix registers definition This file is copied from Linux. AT91 SoCs have a memory range reserved for internal bus configuration. Expose those registers so that drivers can make use of the matrix syscon declared in at91 DTs. Signed-off-by: Balamanikandan Gunasundar --- include/linux/mfd/syscon/atmel-matrix.h | 112 ++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 include/linux/mfd/syscon/atmel-matrix.h diff --git a/include/linux/mfd/syscon/atmel-matrix.h b/include/linux/mfd/syscon/atmel-matrix.h new file mode 100644 index 0000000000..dd228cab67 --- /dev/null +++ b/include/linux/mfd/syscon/atmel-matrix.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + */ + +#ifndef _LINUX_MFD_SYSCON_ATMEL_MATRIX_H +#define _LINUX_MFD_SYSCON_ATMEL_MATRIX_H + +#define AT91SAM9260_MATRIX_MCFG 0x00 +#define AT91SAM9260_MATRIX_SCFG 0x40 +#define AT91SAM9260_MATRIX_PRS 0x80 +#define AT91SAM9260_MATRIX_MRCR 0x100 +#define AT91SAM9260_MATRIX_EBICSA 0x11c + +#define AT91SAM9261_MATRIX_MRCR 0x0 +#define AT91SAM9261_MATRIX_SCFG 0x4 +#define AT91SAM9261_MATRIX_TCR 0x24 +#define AT91SAM9261_MATRIX_EBICSA 0x30 +#define AT91SAM9261_MATRIX_USBPUCR 0x34 + +#define AT91SAM9263_MATRIX_MCFG 0x00 +#define AT91SAM9263_MATRIX_SCFG 0x40 +#define AT91SAM9263_MATRIX_PRS 0x80 +#define AT91SAM9263_MATRIX_MRCR 0x100 +#define AT91SAM9263_MATRIX_TCR 0x114 +#define AT91SAM9263_MATRIX_EBI0CSA 0x120 +#define AT91SAM9263_MATRIX_EBI1CSA 0x124 + +#define AT91SAM9RL_MATRIX_MCFG 0x00 +#define AT91SAM9RL_MATRIX_SCFG 0x40 +#define AT91SAM9RL_MATRIX_PRS 0x80 +#define AT91SAM9RL_MATRIX_MRCR 0x100 +#define AT91SAM9RL_MATRIX_TCR 0x114 +#define AT91SAM9RL_MATRIX_EBICSA 0x120 + +#define AT91SAM9G45_MATRIX_MCFG 0x00 +#define AT91SAM9G45_MATRIX_SCFG 0x40 +#define AT91SAM9G45_MATRIX_PRS 0x80 +#define AT91SAM9G45_MATRIX_MRCR 0x100 +#define AT91SAM9G45_MATRIX_TCR 0x110 +#define AT91SAM9G45_MATRIX_DDRMPR 0x118 +#define AT91SAM9G45_MATRIX_EBICSA 0x128 + +#define AT91SAM9N12_MATRIX_MCFG 0x00 +#define AT91SAM9N12_MATRIX_SCFG 0x40 +#define AT91SAM9N12_MATRIX_PRS 0x80 +#define AT91SAM9N12_MATRIX_MRCR 0x100 +#define AT91SAM9N12_MATRIX_EBICSA 0x118 + +#define AT91SAM9X5_MATRIX_MCFG 0x00 +#define AT91SAM9X5_MATRIX_SCFG 0x40 +#define AT91SAM9X5_MATRIX_PRS 0x80 +#define AT91SAM9X5_MATRIX_MRCR 0x100 +#define AT91SAM9X5_MATRIX_EBICSA 0x120 + +#define SAMA5D3_MATRIX_MCFG 0x00 +#define SAMA5D3_MATRIX_SCFG 0x40 +#define SAMA5D3_MATRIX_PRS 0x80 +#define SAMA5D3_MATRIX_MRCR 0x100 + +#define AT91_MATRIX_MCFG(o, x) ((o) + ((x) * 0x4)) +#define AT91_MATRIX_ULBT GENMASK(2, 0) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG(o, x) ((o) + ((x) * 0x4)) +#define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0) +#define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18) +#define AT91_MATRIX_ARBT GENMASK(25, 24) +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0) +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_ITCM_64 (7 << 0) +#define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4) +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) + +#define AT91_MATRIX_PRAS(o, x) ((o) + ((x) * 0x8)) +#define AT91_MATRIX_PRBS(o, x) ((o) + ((x) * 0x8) + 0x4) +#define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4)) + +#define AT91_MATRIX_RCB(x) BIT(x) + +#define AT91_MATRIX_CSA(cs, val) ((val) << (cs)) +#define AT91_MATRIX_DBPUC BIT(8) +#define AT91_MATRIX_DBPDC BIT(9) +#define AT91_MATRIX_VDDIOMSEL BIT(16) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_IOSR BIT(17) +#define AT91_MATRIX_DDR_IOSR BIT(18) +#define AT91_MATRIX_NFD0_SELECT BIT(24) +#define AT91_MATRIX_DDR_MP_EN BIT(25) + +#define AT91_MATRIX_USBPUCR_PUON BIT(30) + +#endif /* _LINUX_MFD_SYSCON_ATMEL_MATRIX_H */ From 68ddf18dc3bd6b9c229bae0f9cf383f7255c0437 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:04 +0530 Subject: [PATCH 128/424] memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver The EBI is used to access peripherals like NAND, SRAM, NOR etc. Add this driver to probe the nand flash controller. This is a dummy driver and not yet a complete device driver for EBI. Signed-off-by: Balamanikandan Gunasundar --- MAINTAINERS | 1 + drivers/memory/Kconfig | 7 +++++++ drivers/memory/Makefile | 1 + drivers/memory/atmel_ebi.c | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 46 insertions(+) create mode 100644 drivers/memory/atmel_ebi.c diff --git a/MAINTAINERS b/MAINTAINERS index 75b27bc1cc..3a0aab499f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -409,6 +409,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-atmel.git F: arch/arm/mach-at91/ F: board/atmel/ F: drivers/cpu/at91_cpu.c +F: drivers/memory/atmel-ebi.c F: drivers/misc/microchip_flexcom.c F: drivers/timer/atmel_tcb_timer.c F: include/dt-bindings/mfd/atmel-flexcom.h diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 56b89f17be..22cb9d637c 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -13,6 +13,13 @@ config MEMORY SRAM, Ethernet adapters, FPGAs, etc. For now this uclass has no methods yet. +config ATMEL_EBI + bool "Support for Atmel EBI" + help + Driver for Atmel EBI controller. This is a dummy + driver. Doesn't provide an access to EBI controller. Select + this option to enable the NAND flash controller driver + config SANDBOX_MEMORY bool "Enable Sandbox Memory Controller driver" depends on SANDBOX && MEMORY diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 2b196d78c0..1cabf8ac9c 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_MEMORY) += memory-uclass.o obj-$(CONFIG_SANDBOX_MEMORY) += memory-sandbox.o obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o +obj-$(CONFIG_ATMEL_EBI) += atmel_ebi.o obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_GPMC) += ti-gpmc.o diff --git a/drivers/memory/atmel_ebi.c b/drivers/memory/atmel_ebi.c new file mode 100644 index 0000000000..4739eef1b7 --- /dev/null +++ b/drivers/memory/atmel_ebi.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + */ + +#include +#include +#include +#include + +static int atmel_ebi_probe(struct udevice *dev) +{ + int ret; + struct udevice *ndev; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(atmel_nand_controller), + &ndev); + if (ret) + printf("Failed to probe nand driver (err = %d)\n", ret); + + return ret; +} + +static const struct udevice_id atmel_ebi_match[] = { + {.compatible = "microchip,sam9x60-ebi"}, + {.compatible = "atmel,sama5d3-ebi"}, + { /* Sentinel */ } +}; + +U_BOOT_DRIVER(atmel_ebi) = { + .name = "atmel_ebi", + .id = UCLASS_NOP, + .of_match = atmel_ebi_match, + .probe = atmel_ebi_probe, + .bind = dm_scan_fdt_dev, +}; From 2dc1b8fe17b283db4e4485f01ba10dff6b37d693 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:05 +0530 Subject: [PATCH 129/424] mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation Add helper functions for atmel Static Memory Controller. The functions are required to configure SMC. This file is inherited from the work done by Boris Brezillon for Linux Signed-off-by: Balamanikandan Gunasundar --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/mfd/Kconfig | 4 + drivers/mfd/Makefile | 1 + drivers/mfd/atmel-smc.c | 364 +++++++++++++++++++++++++++ include/linux/mfd/syscon/atmel-smc.h | 119 +++++++++ 6 files changed, 491 insertions(+) create mode 100644 drivers/mfd/Kconfig create mode 100644 drivers/mfd/Makefile create mode 100644 drivers/mfd/atmel-smc.c create mode 100644 include/linux/mfd/syscon/atmel-smc.h diff --git a/drivers/Kconfig b/drivers/Kconfig index 75ac149d31..9101e538b0 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -62,6 +62,8 @@ source "drivers/mailbox/Kconfig" source "drivers/memory/Kconfig" +source "drivers/mfd/Kconfig" + source "drivers/misc/Kconfig" source "drivers/mmc/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 6f1de58e00..83b14ef1fd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_QE) += qe/ obj-$(CONFIG_U_QE) += qe/ obj-y += mailbox/ obj-y += memory/ +obj-y += mfd/ obj-y += mtd/ obj-y += pwm/ obj-y += reset/ diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig new file mode 100644 index 0000000000..ae53b02f27 --- /dev/null +++ b/drivers/mfd/Kconfig @@ -0,0 +1,4 @@ +config MFD_ATMEL_SMC + bool "Atmel Static Memory Controller driver" + help + Say yes here to support Atmel Static Memory Controller driver. diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile new file mode 100644 index 0000000000..4454815a98 --- /dev/null +++ b/drivers/mfd/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c new file mode 100644 index 0000000000..15296f71a1 --- /dev/null +++ b/drivers/mfd/atmel-smc.c @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Atmel SMC (Static Memory Controller) helper functions. + * + * Copyright (C) 2022 Microchip Technology Inc. + * Copyright (C) 2017 Free Electrons + * + * Author: Boris Brezillon + */ + +#include +#include +#include +#include +#include +#include + +/** + * atmel_smc_cs_conf_init - initialize a SMC CS conf + * @conf: the SMC CS conf to initialize + * + * Set all fields to 0 so that one can start defining a new config. + */ +void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf) +{ + memset(conf, 0, sizeof(*conf)); +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init); + +/** + * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the + * format expected by the SMC engine + * @ncycles: number of MCK clk cycles + * @msbpos: position of the MSB part of the timing field + * @msbwidth: width of the MSB part of the timing field + * @msbfactor: factor applied to the MSB + * @encodedval: param used to store the encoding result + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic + * helper which called with different parameter depending on the encoding + * scheme. + * + * If the @ncycles value is too big to be encoded, -ERANGE is returned and + * the encodedval is contains the maximum val. Otherwise, 0 is returned. + */ +static int atmel_smc_cs_encode_ncycles(unsigned int ncycles, + unsigned int msbpos, + unsigned int msbwidth, + unsigned int msbfactor, + unsigned int *encodedval) +{ + unsigned int lsbmask = GENMASK(msbpos - 1, 0); + unsigned int msbmask = GENMASK(msbwidth - 1, 0); + unsigned int msb, lsb; + int ret = 0; + + msb = ncycles / msbfactor; + lsb = ncycles % msbfactor; + + if (lsb > lsbmask) { + lsb = 0; + msb++; + } + + /* + * Let's just put the maximum we can if the requested setting does + * not fit in the register field. + * We still return -ERANGE in case the caller cares. + */ + if (msb > msbmask) { + msb = msbmask; + lsb = lsbmask; + ret = -ERANGE; + } + + *encodedval = (msb << msbpos) | lsb; + + return ret; +} + +/** + * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the Txx field in the TIMINGS register + * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Timings Register"), and then stores the result in the + * @conf->timings field at @shift position. + * + * Returns -EINVAL if shift is invalid, -ERANGE if ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_HSMC_TIMINGS_TCLR_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TADL_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TAR_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TRR_SHIFT && + shift != ATMEL_HSMC_TIMINGS_TWB_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "HSMC Timings + * Register"): + * + * ncycles = (Txx[3] * 64) + Txx[2:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 3, 1, 64, &val); + conf->timings &= ~GENMASK(shift + 3, shift); + conf->timings |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_timing); + +/** + * atmel_smc_cs_conf_set_setup - set the SMC CS conf xx_SETUP parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the xx_SETUP field in the SETUP register + * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_SETUP + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Setup Register"), and then stores the result in the + * @conf->setup field at @shift position. + * + * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT && + shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "SMC Setup + * Register"): + * + * ncycles = (128 * xx_SETUP[5]) + xx_SETUP[4:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 5, 1, 128, &val); + conf->setup &= ~GENMASK(shift + 7, shift); + conf->setup |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_setup); + +/** + * atmel_smc_cs_conf_set_pulse - set the SMC CS conf xx_PULSE parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the xx_PULSE field in the PULSE register + * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_PULSE + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Pulse Register"), and then stores the result in the + * @conf->setup field at @shift position. + * + * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NCS_WR_SHIFT && + shift != ATMEL_SMC_NRD_SHIFT && shift != ATMEL_SMC_NCS_RD_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "SMC Pulse + * Register"): + * + * ncycles = (256 * xx_PULSE[6]) + xx_PULSE[5:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 6, 1, 256, &val); + conf->pulse &= ~GENMASK(shift + 7, shift); + conf->pulse |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_pulse); + +/** + * atmel_smc_cs_conf_set_cycle - set the SMC CS conf xx_CYCLE parameter to a + * specific value + * @conf: SMC CS conf descriptor + * @shift: the position of the xx_CYCLE field in the CYCLE register + * @ncycles: value (expressed in MCK clk cycles) to assign to this xx_CYCLE + * parameter + * + * This function encodes the @ncycles value as described in the datasheet + * (section "SMC Cycle Register"), and then stores the result in the + * @conf->setup field at @shift position. + * + * Returns -EINVAL if @shift is invalid, -ERANGE if @ncycles does not fit in + * the field, and 0 otherwise. + */ +int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles) +{ + unsigned int val; + int ret; + + if (shift != ATMEL_SMC_NWE_SHIFT && shift != ATMEL_SMC_NRD_SHIFT) + return -EINVAL; + + /* + * The formula described in atmel datasheets (section "SMC Cycle + * Register"): + * + * ncycles = (xx_CYCLE[8:7] * 256) + xx_CYCLE[6:0] + */ + ret = atmel_smc_cs_encode_ncycles(ncycles, 7, 2, 256, &val); + conf->cycle &= ~GENMASK(shift + 15, shift); + conf->cycle |= val << shift; + + return ret; +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_set_cycle); + +/** + * atmel_smc_cs_conf_apply - apply an SMC CS conf + * @regmap: the SMC regmap + * @cs: the CS id + * @conf: the SMC CS conf to apply + * + * Applies an SMC CS configuration. + * Only valid on at91sam9/avr32 SoCs. + */ +void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, + const struct atmel_smc_cs_conf *conf) +{ + regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup); + regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse); + regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); + regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_apply); + +/** + * atmel_hsmc_cs_conf_apply - apply an SMC CS conf + * @regmap: the HSMC regmap + * @cs: the CS id + * @layout: the layout of registers + * @conf: the SMC CS conf to apply + * + * Applies an SMC CS configuration. + * Only valid on post-sama5 SoCs. + */ +void atmel_hsmc_cs_conf_apply(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *layout, + int cs, const struct atmel_smc_cs_conf *conf) +{ + regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup); + regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), conf->pulse); + regmap_write(regmap, ATMEL_HSMC_CYCLE(layout, cs), conf->cycle); + regmap_write(regmap, ATMEL_HSMC_TIMINGS(layout, cs), conf->timings); + regmap_write(regmap, ATMEL_HSMC_MODE(layout, cs), conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_apply); + +/** + * atmel_smc_cs_conf_get - retrieve the current SMC CS conf + * @regmap: the SMC regmap + * @cs: the CS id + * @conf: the SMC CS conf object to store the current conf + * + * Retrieve the SMC CS configuration. + * Only valid on at91sam9/avr32 SoCs. + */ +void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, + struct atmel_smc_cs_conf *conf) +{ + regmap_read(regmap, ATMEL_SMC_SETUP(cs), &conf->setup); + regmap_read(regmap, ATMEL_SMC_PULSE(cs), &conf->pulse); + regmap_read(regmap, ATMEL_SMC_CYCLE(cs), &conf->cycle); + regmap_read(regmap, ATMEL_SMC_MODE(cs), &conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_get); + +/** + * atmel_hsmc_cs_conf_get - retrieve the current SMC CS conf + * @regmap: the HSMC regmap + * @cs: the CS id + * @layout: the layout of registers + * @conf: the SMC CS conf object to store the current conf + * + * Retrieve the SMC CS configuration. + * Only valid on post-sama5 SoCs. + */ +void atmel_hsmc_cs_conf_get(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *layout, + int cs, struct atmel_smc_cs_conf *conf) +{ + regmap_read(regmap, ATMEL_HSMC_SETUP(layout, cs), &conf->setup); + regmap_read(regmap, ATMEL_HSMC_PULSE(layout, cs), &conf->pulse); + regmap_read(regmap, ATMEL_HSMC_CYCLE(layout, cs), &conf->cycle); + regmap_read(regmap, ATMEL_HSMC_TIMINGS(layout, cs), &conf->timings); + regmap_read(regmap, ATMEL_HSMC_MODE(layout, cs), &conf->mode); +} +EXPORT_SYMBOL_GPL(atmel_hsmc_cs_conf_get); + +static const struct atmel_hsmc_reg_layout sama5d3_reg_layout = { + .timing_regs_offset = 0x600, +}; + +static const struct atmel_hsmc_reg_layout sama5d2_reg_layout = { + .timing_regs_offset = 0x700, +}; + +static const struct udevice_id atmel_smc_ids[] = { + { .compatible = "atmel,at91sam9260-smc", .data = (ulong)0 }, + { .compatible = "atmel,sama5d3-smc", .data = (ulong)&sama5d3_reg_layout }, + { .compatible = "atmel,sama5d2-smc", .data = (ulong)&sama5d2_reg_layout }, + { /* sentinel */ }, +}; + +/** + * atmel_hsmc_get_reg_layout - retrieve the layout of HSMC registers + * @np: the HSMC regmap + * + * Retrieve the layout of HSMC registers. + * + * Returns NULL in case of SMC, a struct atmel_hsmc_reg_layout pointer + * in HSMC case, otherwise ERR_PTR(-EINVAL). + */ +const struct atmel_hsmc_reg_layout * +atmel_hsmc_get_reg_layout(ofnode np) +{ + int i; + const struct udevice_id *match; + const char *name; + int len; + + name = ofnode_get_property(np, "compatible", &len); + + for (i = 0; i < ARRAY_SIZE(atmel_smc_ids); i++) { + if (!strcmp(name, atmel_smc_ids[i].compatible)) { + match = &atmel_smc_ids[i]; + break; + } + } + + return match ? (struct atmel_hsmc_reg_layout *)match->data : ERR_PTR(-EINVAL); +} diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h new file mode 100644 index 0000000000..74be5a199f --- /dev/null +++ b/include/linux/mfd/syscon/atmel-smc.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Atmel SMC (Static Memory Controller) register offsets and bit definitions. + * + * Copyright (C) 2014 Atmel + * Copyright (C) 2014 Free Electrons + * + * Author: Boris Brezillon + */ + +#ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_ +#define _LINUX_MFD_SYSCON_ATMEL_SMC_H_ + +#include +#include +#include + +#define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) +#define ATMEL_HSMC_SETUP(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14)) +#define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) +#define ATMEL_HSMC_PULSE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4) +#define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) +#define ATMEL_HSMC_CYCLE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8) +#define ATMEL_SMC_NWE_SHIFT 0 +#define ATMEL_SMC_NCS_WR_SHIFT 8 +#define ATMEL_SMC_NRD_SHIFT 16 +#define ATMEL_SMC_NCS_RD_SHIFT 24 + +#define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc) +#define ATMEL_HSMC_MODE(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10) +#define ATMEL_SMC_MODE_READMODE_MASK BIT(0) +#define ATMEL_SMC_MODE_READMODE_NCS (0 << 0) +#define ATMEL_SMC_MODE_READMODE_NRD (1 << 0) +#define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1) +#define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1) +#define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1) +#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4) +#define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4) +#define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4) +#define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4) +#define ATMEL_SMC_MODE_BAT_MASK BIT(8) +#define ATMEL_SMC_MODE_BAT_SELECT (0 << 8) +#define ATMEL_SMC_MODE_BAT_WRITE (1 << 8) +#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12) +#define ATMEL_SMC_MODE_DBW_8 (0 << 12) +#define ATMEL_SMC_MODE_DBW_16 (1 << 12) +#define ATMEL_SMC_MODE_DBW_32 (2 << 12) +#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16) +#define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16) +#define ATMEL_SMC_MODE_TDF_MAX 16 +#define ATMEL_SMC_MODE_TDF_MIN 1 +#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20) +#define ATMEL_SMC_MODE_PMEN BIT(24) +#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28) +#define ATMEL_SMC_MODE_PS_4 (0 << 28) +#define ATMEL_SMC_MODE_PS_8 (1 << 28) +#define ATMEL_SMC_MODE_PS_16 (2 << 28) +#define ATMEL_SMC_MODE_PS_32 (3 << 28) + +#define ATMEL_HSMC_TIMINGS(layout, cs) \ + ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc) +#define ATMEL_HSMC_TIMINGS_OCMS BIT(12) +#define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28) +#define ATMEL_HSMC_TIMINGS_NFSEL BIT(31) +#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0 +#define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4 +#define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8 +#define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16 +#define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24 + +struct atmel_hsmc_reg_layout { + unsigned int timing_regs_offset; +}; + +/** + * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet. + * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200) + * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200) + * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200) + * @timings: advanced NAND related timings (only applicable to HSMC) + * @mode: all kind of config parameters (see the fields definition above). + * The mode fields are different on at91rm9200 + */ +struct atmel_smc_cs_conf { + u32 setup; + u32 pulse; + u32 cycle; + u32 timings; + u32 mode; +}; + +void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf); +int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf, + unsigned int shift, + unsigned int ncycles); +int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles); +int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles); +int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf, + unsigned int shift, unsigned int ncycles); +void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, + const struct atmel_smc_cs_conf *conf); +void atmel_hsmc_cs_conf_apply(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *reglayout, + int cs, const struct atmel_smc_cs_conf *conf); +void atmel_smc_cs_conf_get(struct regmap *regmap, int cs, + struct atmel_smc_cs_conf *conf); +void atmel_hsmc_cs_conf_get(struct regmap *regmap, + const struct atmel_hsmc_reg_layout *reglayout, + int cs, struct atmel_smc_cs_conf *conf); +const struct atmel_hsmc_reg_layout * +atmel_hsmc_get_reg_layout(ofnode np); + +#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */ From 2cf5d0aa8e92aff6f5f18ada9dc1b6c7021ff026 Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:06 +0530 Subject: [PATCH 130/424] configs: at91: sam9x60ek: Enable DM based nand driver Enable Device model supported NAND driver and remove legacy Atmel NAND driver. Signed-off-by: Balamanikandan Gunasundar --- configs/sam9x60ek_mmc_defconfig | 9 ++++++--- configs/sam9x60ek_nandflash_defconfig | 9 ++++++--- configs/sam9x60ek_qspiflash_defconfig | 8 +++++--- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig index f83cbf6f15..268a485456 100644 --- a/configs/sam9x60ek_mmc_defconfig +++ b/configs/sam9x60ek_mmc_defconfig @@ -52,6 +52,8 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y @@ -61,15 +63,16 @@ CONFIG_CPU=y CONFIG_AT91_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_AT91=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y CONFIG_I2C_EEPROM=y CONFIG_MICROCHIP_FLEXCOM=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y CONFIG_MTD=y +CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_ATMEL=y -CONFIG_ATMEL_NAND_HW_PMECC=y -CONFIG_PMECC_CAP=8 +CONFIG_DM_NAND_ATMEL=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index b04a153640..a9cbb6e953 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -54,6 +54,8 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y @@ -63,14 +65,15 @@ CONFIG_CPU=y CONFIG_AT91_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_AT91=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y CONFIG_I2C_EEPROM=y CONFIG_MICROCHIP_FLEXCOM=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y +CONFIG_DM_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_ATMEL_NAND_HW_PMECC=y -CONFIG_PMECC_CAP=8 +CONFIG_DM_NAND_ATMEL=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig index fd95a6fbbb..72f08f1375 100644 --- a/configs/sam9x60ek_qspiflash_defconfig +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -54,6 +54,8 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_CLK_AT91=y @@ -63,6 +65,8 @@ CONFIG_CPU=y CONFIG_AT91_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_AT91=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y CONFIG_I2C_EEPROM=y CONFIG_MICROCHIP_FLEXCOM=y CONFIG_GENERIC_ATMEL_MCI=y @@ -70,9 +74,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set -CONFIG_NAND_ATMEL=y -CONFIG_ATMEL_NAND_HW_PMECC=y -CONFIG_PMECC_CAP=8 +CONFIG_DM_NAND_ATMEL=y CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y From 2d35bf242072b97af10d3a168e4d56c9cdd8a21c Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:07 +0530 Subject: [PATCH 131/424] ARM: dts: at91: sam9x60: Add nodes for EBI and NAND Add new bindings for EBI and NAND controller Signed-off-by: Balamanikandan Gunasundar --- arch/arm/dts/sam9x60.dtsi | 42 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index a5c429eb3a..17224ef771 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -69,6 +69,32 @@ #size-cells = <1>; ranges; + ebi: ebi@10000000 { + compatible = "microchip,sam9x60-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&smc>; + microchip,sfr = <&sfr>; + reg = <0x10000000 0x60000000>; + ranges = <0x0 0x0 0x10000000 0x10000000 + 0x1 0x0 0x20000000 0x10000000 + 0x2 0x0 0x30000000 0x10000000 + 0x3 0x0 0x40000000 0x10000000 + 0x4 0x0 0x50000000 0x10000000 + 0x5 0x0 0x60000000 0x10000000>; + clocks = <&pmc PMC_TYPE_CORE 11>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "microchip,sam9x60-nand-controller"; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + sdhci0: sdhci-host@80000000 { compatible = "microchip,sam9x60-sdhci"; reg = <0x80000000 0x300>; @@ -119,6 +145,11 @@ status = "disabled"; }; + sfr: sfr@f8050000 { + compatible = "microchip,sam9x60-sfr", "syscon"; + reg = <0xf8050000 0x100>; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; @@ -182,6 +213,17 @@ }; }; + pmecc: ecc-engine@ffffe000 { + compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; + reg = <0xffffe000 0x300>, + <0xffffe600 0x100>; + }; + + smc: smc@ffffea00 { + compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; + reg = <0xffffea00 0x100>; + }; + pioA: gpio@fffff400 { compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; reg = <0xfffff400 0x200>; From 70cbf2f09784319d2773a09e26bba077f6af927b Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:08 +0530 Subject: [PATCH 132/424] ARM: dts: at91: sam9x60ek: Enable NAND support Enable the EBI and NAND flash controller. Define the pinctrl and partition table Signed-off-by: Balamanikandan Gunasundar --- arch/arm/dts/sam9x60ek.dts | 103 +++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index eb44868a3e..1a02e2cb79 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -80,6 +80,44 @@ }; pinctrl { + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + ebi { + pinctrl_ebi_data_0_7: ebi-data-lsb-0 { + atmel,pins = + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-0 { + atmel,pins = + ; + }; + }; + pinctrl_qspi: qspi { atmel,pins = ; + status = "okay"; + + nand_controller: nand-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label = "U-Boot Env Redundant"; + reg = <0x100000 0x40000>; + }; + + ubootenv@140000 { + label = "U-Boot Env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + &macb0 { phy-mode = "rmii"; status = "okay"; From c41e05bab0b025691741d819ff372c08e285b99a Mon Sep 17 00:00:00 2001 From: Balamanikandan Gunasundar Date: Tue, 25 Oct 2022 16:21:09 +0530 Subject: [PATCH 133/424] board: sam9x60ek: remove nand init from board file Move this out of board file as this is done by the DM based NAND flash driver. The EBI chip select configuration, iomux and timings are handled by the driver Signed-off-by: Balamanikandan Gunasundar --- board/atmel/sam9x60ek/sam9x60ek.c | 59 ------------------------------- include/configs/sam9x60ek.h | 9 ----- 2 files changed, 68 deletions(-) diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index a3e35f3066..04bf2bb5c9 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -24,62 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; void at91_prepare_cpu_var(void); -#ifdef CONFIG_CMD_NAND -static void sam9x60ek_nand_hw_init(void) -{ - struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; - unsigned int csa; - - at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ - at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ - /* Enable NandFlash */ - at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1); - /* Configure RDY/BSY */ - at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); - at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); - - at91_periph_clk_enable(ATMEL_ID_PIOD); - - /* Enable CS3 */ - csa = readl(&sfr->ebicsa); - csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16; - - /* Configure IO drive */ - csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60; - - writel(csa, &sfr->ebicsa); - - /* Configure SMC CS3 for NAND/SmartMedia */ - writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup); - - writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) | - AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20), - &smc->cs[3].pulse); - - writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), - &smc->cs[3].cycle); - - writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_MODE_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_MODE_DBW_8 | -#endif - AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15), - &smc->cs[3].mode); -} -#endif - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -122,9 +66,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_CMD_NAND - sam9x60ek_nand_hw_init(); -#endif return 0; } diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 27b39ebf41..cb7f35c7ca 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -26,13 +26,4 @@ #define CFG_SYS_SDRAM_BASE 0x20000000 #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CFG_SYS_NAND_BASE 0x40000000 -#define CFG_SYS_NAND_MASK_ALE BIT(21) -#define CFG_SYS_NAND_MASK_CLE BIT(22) -#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5 -#endif - #endif From 544071ac4a1c301ed38d7f9ce41cc7cd0910083d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 24 Nov 2022 00:45:00 +0100 Subject: [PATCH 134/424] Nokia RX-51: Use ENTRY/ENDPROC for save_boot_params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ENTRY/ENDPROC macros from linux/linkage.h will make code more readable and also will properly mark assembly symbol in ELF binary as function symbol. Signed-off-by: Pali Rohár --- board/nokia/rx51/lowlevel_init.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index 930052ea60..44f32f114e 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -5,6 +5,7 @@ */ #include +#include kernoffs: /* offset of kernel image from this address */ .word . - CONFIG_TEXT_BASE - KERNEL_OFFSET @@ -29,8 +30,7 @@ z_magic: /* LINUX_ARM_ZIMAGE_MAGIC */ * Description: Copy attached kernel to address KERNEL_ADDRESS */ -.global save_boot_params -save_boot_params: +ENTRY(save_boot_params) /* * Copy valid attached kernel to absolute address KERNEL_ADDRESS @@ -93,3 +93,5 @@ skip_copy: /* Returns */ b save_boot_params_ret + +ENDPROC(save_boot_params) From 0db588caf99821b616169a7888d8a9515604940c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Nov 2022 12:54:51 -0500 Subject: [PATCH 135/424] x86: fsp: Only compile fsp_save_s3_stack if (SPL_)DM_RTC is enabled This function calls rtc_write32, which has a different signature depending on if (SPL_)DM_RTC is enabled or not. This could result in a mismatch in SPL if DM_RTC was enabled but SPL_DM_RTC, as the non-DM declaration would still be used in SPL even though the implementation would be for non-DM_RTC. We are switching to the correct definitions in the next commit, so this will become a compilation error. Since fsp_save_s3_stack is not called from SPL, avoid compiling it if (SPL_)DM_RTC is disabled. Signed-off-by: Sean Anderson --- arch/x86/lib/fsp/fsp_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 82f7d3ab5f..8f2977a807 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -61,6 +61,7 @@ void board_final_init(void) debug("OK\n"); } +#if CONFIG_IS_ENABLED(DM_RTC) int fsp_save_s3_stack(void) { struct udevice *dev; @@ -84,3 +85,4 @@ int fsp_save_s3_stack(void) return 0; } +#endif From 640aecb416cff52cf8a89d786d41e6eee54c94ff Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Nov 2022 12:54:52 -0500 Subject: [PATCH 136/424] rtc: Add fallbacks for dm functions This adds fallbacks for the various dm_rtc_* functions. This allows common code to use these functions without ifdefs. Fixes: c8ce7ba87d1 ("misc: Add support for nvmem cells") Reviewed-by: Simon Glass Signed-off-by: Sean Anderson --- include/rtc.h | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/include/rtc.h b/include/rtc.h index 10104e3bf5..b6fdbb60dc 100644 --- a/include/rtc.h +++ b/include/rtc.h @@ -15,13 +15,12 @@ #include #include +#include typedef int64_t time64_t; - -#ifdef CONFIG_DM_RTC - struct udevice; +#if CONFIG_IS_ENABLED(DM_RTC) struct rtc_ops { /** * get() - get the current time @@ -222,6 +221,33 @@ int rtc_enable_32khz_output(int busnum, int chip_addr); #endif #else +static inline int dm_rtc_get(struct udevice *dev, struct rtc_time *time) +{ + return -ENOSYS; +} + +static inline int dm_rtc_set(struct udevice *dev, struct rtc_time *time) +{ + return -ENOSYS; +} + +static inline int dm_rtc_reset(struct udevice *dev) +{ + return -ENOSYS; +} + +static inline int dm_rtc_read(struct udevice *dev, unsigned int reg, u8 *buf, + unsigned int len) +{ + return -ENOSYS; +} + +static inline int dm_rtc_write(struct udevice *dev, unsigned int reg, + const u8 *buf, unsigned int len) +{ + return -ENOSYS; +} + int rtc_get (struct rtc_time *); int rtc_set (struct rtc_time *); void rtc_reset (void); From ee31be429ba4be734fcb7bcb037d38afc82cc052 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Mon, 24 Oct 2022 16:53:28 -0500 Subject: [PATCH 137/424] ram: k3-ddrss: add auto-generated macros for am62a support The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof --- drivers/ram/Kconfig | 10 + .../ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h | 14 - .../k3-ddrss/16bit/lpddr4_16bit_structs_if.h | 15 - .../ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h | 14 - .../k3-ddrss/32bit/lpddr4_32bit_structs_if.h | 15 - drivers/ram/k3-ddrss/Makefile | 18 +- .../am62a/lpddr4_address_slice_0_macros.h | 778 ++ .../am62a/lpddr4_address_slice_1_macros.h | 778 ++ .../am62a/lpddr4_address_slice_2_macros.h | 778 ++ .../am62a/lpddr4_am62a_ctl_regs_rw_masks.h | 25 + drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h | 108 + .../ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h | 14 + .../k3-ddrss/am62a/lpddr4_am62a_structs_if.h | 15 + drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h | 1721 ++++ .../am62a/lpddr4_data_slice_0_macros.h | 2292 ++++++ .../am62a/lpddr4_data_slice_1_macros.h | 2292 ++++++ .../am62a/lpddr4_data_slice_2_macros.h | 2292 ++++++ .../am62a/lpddr4_data_slice_3_macros.h | 2292 ++++++ .../am62a/lpddr4_ddr_controller_macros.h | 6560 ++++++++++++++++ .../k3-ddrss/am62a/lpddr4_phy_core_macros.h | 1986 +++++ drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h | 6892 +++++++++++++++++ .../lpddr4_address_slice_0_macros.h | 4 +- .../lpddr4_address_slice_1_macros.h | 4 +- .../lpddr4_address_slice_2_macros.h | 4 +- .../lpddr4_am64_ctl_regs_rw_masks.h} | 4 +- .../lpddr4_am64_if.h} | 10 +- .../ram/k3-ddrss/am64/lpddr4_am64_obj_if.h | 14 + .../k3-ddrss/am64/lpddr4_am64_structs_if.h | 15 + .../{16bit => am64}/lpddr4_ctl_regs.h | 4 +- .../lpddr4_data_slice_0_macros.h | 4 +- .../lpddr4_data_slice_1_macros.h | 4 +- .../lpddr4_ddr_controller_macros.h | 4 +- .../{16bit => am64}/lpddr4_phy_core_macros.h | 4 +- .../{16bit => am64}/lpddr4_pi_macros.h | 4 +- drivers/ram/k3-ddrss/cps_drv_lpddr4.h | 4 +- .../lpddr4_address_slice_0_macros.h | 4 +- .../{32bit => j721e}/lpddr4_ctl_regs.h | 4 +- .../lpddr4_data_slice_0_macros.h | 4 +- .../lpddr4_data_slice_1_macros.h | 4 +- .../lpddr4_data_slice_2_macros.h | 4 +- .../lpddr4_data_slice_3_macros.h | 4 +- .../lpddr4_ddr_controller_macros.h | 4 +- .../lpddr4_j721e_ctl_regs_rw_masks.h} | 4 +- .../lpddr4_j721e_if.h} | 10 +- .../ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h | 14 + .../k3-ddrss/j721e/lpddr4_j721e_structs_if.h | 15 + .../{32bit => j721e}/lpddr4_phy_core_macros.h | 4 +- .../{32bit => j721e}/lpddr4_pi_macros.h | 4 +- drivers/ram/k3-ddrss/lpddr4.c | 67 +- drivers/ram/k3-ddrss/lpddr4.h | 33 +- drivers/ram/k3-ddrss/lpddr4_16bit.h | 33 - .../k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c | 1726 +++++ ...asks.c => lpddr4_am64_ctl_regs_rw_masks.c} | 6 +- .../{lpddr4_16bit.c => lpddr4_am6x.c} | 16 +- drivers/ram/k3-ddrss/lpddr4_am6x.h | 45 + ...r4_16bit_sanity.h => lpddr4_am6x_sanity.h} | 20 +- drivers/ram/k3-ddrss/lpddr4_if.h | 12 +- .../{lpddr4_32bit.c => lpddr4_j721e.c} | 7 +- .../{lpddr4_32bit.h => lpddr4_j721e.h} | 20 +- ...sks.c => lpddr4_j721e_ctl_regs_rw_masks.c} | 6 +- ...4_32bit_sanity.h => lpddr4_j721e_sanity.h} | 17 +- drivers/ram/k3-ddrss/lpddr4_obj_if.c | 5 +- drivers/ram/k3-ddrss/lpddr4_obj_if.h | 6 +- drivers/ram/k3-ddrss/lpddr4_private.h | 60 - drivers/ram/k3-ddrss/lpddr4_sanity.h | 20 +- drivers/ram/k3-ddrss/lpddr4_structs_if.h | 4 +- 66 files changed, 30830 insertions(+), 344 deletions(-) delete mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h delete mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h delete mode 100644 drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h delete mode 100644 drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h create mode 100644 drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_address_slice_0_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_address_slice_1_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_address_slice_2_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit/lpddr4_ctl_regs_rw_masks.h => am64/lpddr4_am64_ctl_regs_rw_masks.h} (82%) rename drivers/ram/k3-ddrss/{16bit/lpddr4_16bit_if.h => am64/lpddr4_am64_if.h} (94%) create mode 100644 drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h create mode 100644 drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_ctl_regs.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_data_slice_0_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_data_slice_1_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_ddr_controller_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_phy_core_macros.h (99%) rename drivers/ram/k3-ddrss/{16bit => am64}/lpddr4_pi_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_address_slice_0_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_ctl_regs.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_data_slice_0_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_data_slice_1_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_data_slice_2_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_data_slice_3_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_ddr_controller_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit/lpddr4_ctl_regs_rw_masks.h => j721e/lpddr4_j721e_ctl_regs_rw_masks.h} (82%) rename drivers/ram/k3-ddrss/{32bit/lpddr4_32bit_if.h => j721e/lpddr4_j721e_if.h} (93%) create mode 100644 drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h create mode 100644 drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_phy_core_macros.h (99%) rename drivers/ram/k3-ddrss/{32bit => j721e}/lpddr4_pi_macros.h (99%) delete mode 100644 drivers/ram/k3-ddrss/lpddr4_16bit.h create mode 100644 drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c rename drivers/ram/k3-ddrss/{lpddr4_16bit_ctl_regs_rw_masks.c => lpddr4_am64_ctl_regs_rw_masks.c} (99%) rename drivers/ram/k3-ddrss/{lpddr4_16bit.c => lpddr4_am6x.c} (97%) create mode 100644 drivers/ram/k3-ddrss/lpddr4_am6x.h rename drivers/ram/k3-ddrss/{lpddr4_16bit_sanity.h => lpddr4_am6x_sanity.h} (97%) rename drivers/ram/k3-ddrss/{lpddr4_32bit.c => lpddr4_j721e.c} (98%) rename drivers/ram/k3-ddrss/{lpddr4_32bit.h => lpddr4_j721e.h} (56%) rename drivers/ram/k3-ddrss/{lpddr4_32bit_ctl_regs_rw_masks.c => lpddr4_j721e_ctl_regs_rw_masks.c} (99%) rename drivers/ram/k3-ddrss/{lpddr4_32bit_sanity.h => lpddr4_j721e_sanity.h} (96%) delete mode 100644 drivers/ram/k3-ddrss/lpddr4_private.h diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 86857c0627..bf279b79f6 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -86,6 +86,16 @@ config K3_AM64_DDRSS Enabling this config adds support for the DDR memory controller on AM642 family of SoCs. +config K3_AM62A_DDRSS + bool "Enable AM62A DDRSS support" + help + The AM62A DDR subsystem comprises of a DDR controller, DDR PHY and + wrapper logic to integrate these blocks into once device. The DDR + subsystem is used to provide an interface to external SDRAM devices + which can be utilized for storing programs or any other data. + Enabling this option adds support for the DDR memory controller for + the AM62A family of SoCs. + endchoice config IMXRT_SDRAM diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h deleted file mode 100644 index 6c57dd9d00..0000000000 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Cadence DDR Driver - * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef LPDDR4_16BIT_OBJ_IF_H -#define LPDDR4_16BIT_OBJ_IF_H - -#include "lpddr4_16bit_if.h" - -#endif /* LPDDR4_16BIT_OBJ_IF_H */ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h deleted file mode 100644 index 52973484ec..0000000000 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Cadence DDR Driver - * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef LPDDR4_16BIT_STRUCTS_IF_H -#define LPDDR4_16BIT_STRUCTS_IF_H - -#include -#include "lpddr4_16bit_if.h" - -#endif /* LPDDR4_16BIT_STRUCTS_IF_H */ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h deleted file mode 100644 index 7fee54f00d..0000000000 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Cadence DDR Driver - * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef LPDDR4_32BIT_OBJ_IF_H -#define LPDDR4_32BIT_OBJ_IF_H - -#include "lpddr4_32bit_if.h" - -#endif /* LPDDR4_32BIT_OBJ_IF_H */ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h deleted file mode 100644 index 69b2a47ab3..0000000000 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Cadence DDR Driver - * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef LPDDR4_32BIT_STRUCTS_IF_H -#define LPDDR4_32BIT_STRUCTS_IF_H - -#include -#include "lpddr4_32bit_if.h" - -#endif /* LPDDR4_32BIT_STRUCTS_IF_H */ diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile index 8be00118f5..ba5d9a2f4d 100644 --- a/drivers/ram/k3-ddrss/Makefile +++ b/drivers/ram/k3-ddrss/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/ +# Copyright (C) 2019-2022 Texas Instruments Incorporated - http://www.ti.com/ # obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o @@ -8,10 +8,14 @@ obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o obj-$(CONFIG_K3_DDRSS) += lpddr4.o ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/ -obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o -obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o -ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/ +obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am6x.o +obj-$(CONFIG_K3_AM62A_DDRSS) += lpddr4_am62a_ctl_regs_rw_masks.o +ccflags-$(CONFIG_K3_AM62A_DDRSS) += -Idrivers/ram/k3-ddrss/am62a/ -obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o -obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o -ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/ +obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am6x.o +obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_am64_ctl_regs_rw_masks.o +ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/am64/ + +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e.o +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_j721e_ctl_regs_rw_masks.o +ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/j721e/ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h new file mode 100644 index 0000000000..1cd40c8332 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_0_macros.h @@ -0,0 +1,778 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_1024 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_1028 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030 +#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031 +#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032 +#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0 + +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0 + +#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036 +#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0 + +#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0 + +#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_1040 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_0 + +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041 +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0 + +#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042 +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0 + +#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043 +#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0 + +#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044 +#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0 + +#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045 +#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0 + +#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046 +#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0 + +#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047 +#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0 + +#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048 +#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0 + +#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049 +#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0 + +#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050 +#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0 + +#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051 +#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0 + +#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052 +#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0 + +#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 30U +#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053 +#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0 + +#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0 + +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054 +#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0 + +#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_CSLVL_TRAIN_MASK_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR0_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR1_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056 +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR4_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR5_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057 +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0 + +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0_WIDTH 6U +#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058 +#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0 + +#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_DIRECT_0 + +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059 +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0 + +#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x00003F01U +#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x00003F01U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR_DC_CAL_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1061 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1061__PHY_PAD_ADR_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x07FF1F07U +#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x07FF1F07U +#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1062__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1062 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR0_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1063_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1063 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR1_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1063 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR2_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR2_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1064 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR3_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR3_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR4_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR4_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR5_SW_WRADDR_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_1067 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR5_CLK_WR_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1067 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_1068_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1068 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1069 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR_SW_CALVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1070 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_CALVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_1071_READ_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_CALVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1071 +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_DC_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_CALVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__REG DENALI_PHY_1072 +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_DC_DM_CLK_THRSHLD_0 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h new file mode 100644 index 0000000000..69521c75c1 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_1_macros.h @@ -0,0 +1,778 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_1280 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_1280 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_1280__PHY_ADR_CLK_BYPASS_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_1280 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_1280__SC_PHY_ADR_MANUAL_CLEAR_1 + +#define LPDDR4__DENALI_PHY_1281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_1281 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_1281__PHY_ADR_LPBK_RESULT_OBS_1 + +#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_1282 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_LPBK_ERROR_COUNT_OBS_1 + +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_1282 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MEAS_DLY_STEP_VALUE_1 + +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_1282 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_1283_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_MASTER_DLY_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_1283 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_1283__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_1284 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1 + +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_1284 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_1284 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_1284__SC_PHY_ADR_SNAP_OBS_REGS_1 + +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_1284 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1284__PHY_ADR_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_1285 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_LPBK_CONTROL_1 + +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_1285 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_START_1 + +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_1285 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PRBS_PATTERN_MASK_1 + +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_1285 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_1285__PHY_ADR_PWR_RDC_DISABLE_1 + +#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1286 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_1286 +#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_TYPE_1 + +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_1286 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_WRADDR_SHIFT_OBS_1 + +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_1286 +#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_1286__PHY_ADR_IE_MODE_1 + +#define LPDDR4__DENALI_PHY_1287_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1287_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_1287 +#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_1287__PHY_ADR_DDL_MODE_1 + +#define LPDDR4__DENALI_PHY_1288_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_1288 +#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_1288__PHY_ADR_DDL_MASK_1 + +#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_1289 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_1289__PHY_ADR_DDL_TEST_OBS_1 + +#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_1290 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_1290__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_1291 +#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_START_1 + +#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_1291 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_1291__PHY_ADR_CALVL_COARSE_DLY_1 + +#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_1292 +#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_1292__PHY_ADR_CALVL_QTR_1 + +#define LPDDR4__DENALI_PHY_1293_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_1293 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_1293__PHY_ADR_CALVL_SWIZZLE0_1 + +#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_SWIZZLE1_1 + +#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_1294 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_1294__PHY_ADR_CALVL_RANK_CTRL_1 + +#define LPDDR4__DENALI_PHY_1295_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_1295 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_NUM_PATTERNS_1 + +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_1295 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_1295 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_1295__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_1296_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_1296 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_DEBUG_MODE_1 + +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_1296 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_DEBUG_CONT_1 + +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_1296 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_1296__SC_PHY_ADR_CALVL_ERROR_CLR_1 + +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_1296 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_1296__PHY_ADR_CALVL_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_1297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__REG DENALI_PHY_1297 +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_1__FLD LPDDR4__DENALI_PHY_1297__PHY_ADR_CALVL_CH0_OBS0_1 + +#define LPDDR4__DENALI_PHY_1298_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__REG DENALI_PHY_1298 +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_1__FLD LPDDR4__DENALI_PHY_1298__PHY_ADR_CALVL_CH1_OBS0_1 + +#define LPDDR4__DENALI_PHY_1299_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_1299 +#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADR_CALVL_OBS1_1 + +#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_1300 +#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_1300__PHY_ADR_CALVL_OBS2_1 + +#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_1301 +#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_1301__PHY_ADR_CALVL_FG_0_1 + +#define LPDDR4__DENALI_PHY_1302_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_1302 +#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_1302__PHY_ADR_CALVL_BG_0_1 + +#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_1303 +#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_1303__PHY_ADR_CALVL_FG_1_1 + +#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_1304 +#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_1304__PHY_ADR_CALVL_BG_1_1 + +#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_1305 +#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_1305__PHY_ADR_CALVL_FG_2_1 + +#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_1306 +#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_1306__PHY_ADR_CALVL_BG_2_1 + +#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_1307 +#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_ADR_CALVL_FG_3_1 + +#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_1308 +#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_ADR_CALVL_BG_3_1 + +#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1_WIDTH 30U +#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_1309 +#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_1309__PHY_ADR_ADDR_SEL_1 + +#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_1310 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_LP4_BOOT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_1310 +#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_BIT_MASK_1 + +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_1310 +#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_1310__PHY_ADR_SEG_MASK_1 + +#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_1311 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CALVL_TRAIN_MASK_1 + +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_1311 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_CSLVL_TRAIN_MASK_1 + +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_1311 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_STATIC_TOG_DISABLE_1 + +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_1311 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1311__PHY_ADR_SW_TXIO_CTRL_1 + +#define LPDDR4__DENALI_PHY_1312_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__REG DENALI_PHY_1312 +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_INIT_DISABLE_1 + +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__REG DENALI_PHY_1312 +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR0_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__REG DENALI_PHY_1312 +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR1_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__REG DENALI_PHY_1312 +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1312__PHY_ADR_DC_ADR2_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__REG DENALI_PHY_1313 +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR3_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__REG DENALI_PHY_1313 +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR4_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__REG DENALI_PHY_1313 +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DC_ADR5_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_1313 +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_1313__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_1314 +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_SAMPLE_WAIT_1 + +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__REG DENALI_PHY_1314 +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_CAL_TIMEOUT_1 + +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_WEIGHT_1__REG DENALI_PHY_1314 +#define LPDDR4__PHY_ADR_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_WEIGHT_1 + +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1_WIDTH 6U +#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__REG DENALI_PHY_1314 +#define LPDDR4__PHY_ADR_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_1314__PHY_ADR_DC_ADJUST_START_1 + +#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_1315 +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_SAMPLE_CNT_1 + +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_1315 +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1_WOSET 0U +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__REG DENALI_PHY_1315 +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_ADJUST_DIRECT_1 + +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__REG DENALI_PHY_1315 +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_1315__PHY_ADR_DC_CAL_POLARITY_1 + +#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x00003F01U +#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x00003F01U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_START_1__REG DENALI_PHY_1316 +#define LPDDR4__PHY_ADR_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_DC_CAL_START_1 + +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_1316 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1316__PHY_ADR_SW_TXPWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_1317 +#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__REG DENALI_PHY_1317 +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1317__PHY_ADR_DC_CAL_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_1317 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PAD_ADR_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x07FF1F07U +#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x07FF1F07U +#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_1318 +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1318 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1318 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1318__PHY_ADR0_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1319 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR1_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1319 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1319__PHY_ADR2_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1320 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR2_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1320 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1320__PHY_ADR3_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1321 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR3_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1321 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1321__PHY_ADR4_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1322 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR4_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_1322 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_1322__PHY_ADR5_SW_WRADDR_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_1323 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR5_CLK_WR_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_1323 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_1323__PHY_ADR_SW_MASTER_MODE_1 + +#define LPDDR4__DENALI_PHY_1324_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_1324 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_START_1 + +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_1324 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_STEP_1 + +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_1324 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_1324__PHY_ADR_MASTER_DELAY_WAIT_1 + +#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_1325 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1 + +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_1325 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_1325 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_1325__PHY_ADR_SW_CALVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_1326 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_1326__PHY_ADR_CALVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_1327 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_CALVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_1327 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_MEAS_DLY_STEP_ENABLE_1 + +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__REG DENALI_PHY_1327 +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_1327__PHY_ADR_DC_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__REG DENALI_PHY_1328 +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_CALVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__REG DENALI_PHY_1328 +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_1__FLD LPDDR4__DENALI_PHY_1328__PHY_ADR_DC_DM_CLK_THRSHLD_1 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h new file mode 100644 index 0000000000..abb7640de9 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_address_slice_2_macros.h @@ -0,0 +1,778 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ +#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1536_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1536_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1536 +#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1536 +#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1536__PHY_ADR_CLK_BYPASS_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1536 +#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1536__SC_PHY_ADR_MANUAL_CLEAR_2 + +#define LPDDR4__DENALI_PHY_1537_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1537_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1537 +#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1537__PHY_ADR_LPBK_RESULT_OBS_2 + +#define LPDDR4__DENALI_PHY_1538_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1538_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1538 +#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_LPBK_ERROR_COUNT_OBS_2 + +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1538 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MEAS_DLY_STEP_VALUE_2 + +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1538 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1538__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_1539_READ_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1539_WRITE_MASK 0xFF7F07FFU +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1539 +#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_MASTER_DLY_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539 +#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1539 +#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1539__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_1540_READ_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1540_WRITE_MASK 0x01000707U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1540 +#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2 + +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1540 +#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1540 +#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1540__SC_PHY_ADR_SNAP_OBS_REGS_2 + +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1540 +#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1540__PHY_ADR_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_1541_READ_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1541_WRITE_MASK 0x011F7F7FU +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U +#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1541 +#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_LPBK_CONTROL_2 + +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1541 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_START_2 + +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1541 +#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PRBS_PATTERN_MASK_2 + +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1541 +#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1541__PHY_ADR_PWR_RDC_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1542_READ_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1542_WRITE_MASK 0x01070301U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1542 +#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2_WIDTH 2U +#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1542 +#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_TYPE_2 + +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1542 +#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_WRADDR_SHIFT_OBS_2 + +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2_WOSET 0U +#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1542 +#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1542__PHY_ADR_IE_MODE_2 + +#define LPDDR4__DENALI_PHY_1543_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1543_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2_WIDTH 27U +#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1543 +#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1543__PHY_ADR_DDL_MODE_2 + +#define LPDDR4__DENALI_PHY_1544_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1544_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1544 +#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1544__PHY_ADR_DDL_MASK_2 + +#define LPDDR4__DENALI_PHY_1545_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1545_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1545 +#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1545__PHY_ADR_DDL_TEST_OBS_2 + +#define LPDDR4__DENALI_PHY_1546_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1546_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1546 +#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1546__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_1547_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1547_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1547 +#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_START_2 + +#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1547 +#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1547__PHY_ADR_CALVL_COARSE_DLY_2 + +#define LPDDR4__DENALI_PHY_1548_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1548_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2_WIDTH 11U +#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1548 +#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1548__PHY_ADR_CALVL_QTR_2 + +#define LPDDR4__DENALI_PHY_1549_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1549_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1549 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1549__PHY_ADR_CALVL_SWIZZLE0_2 + +#define LPDDR4__DENALI_PHY_1550_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1550_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1550 +#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_SWIZZLE1_2 + +#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1550 +#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1550__PHY_ADR_CALVL_RANK_CTRL_2 + +#define LPDDR4__DENALI_PHY_1551_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1551_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1551 +#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_NUM_PATTERNS_2 + +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1551 +#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1551 +#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1551__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_1552_READ_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1552_WRITE_MASK 0x07000001U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1552 +#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_DEBUG_MODE_2 + +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1552 +#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_DEBUG_CONT_2 + +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1552 +#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1552__SC_PHY_ADR_CALVL_ERROR_CLR_2 + +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1552 +#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1552__PHY_ADR_CALVL_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_1553_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1553_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__REG DENALI_PHY_1553 +#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_2__FLD LPDDR4__DENALI_PHY_1553__PHY_ADR_CALVL_CH0_OBS0_2 + +#define LPDDR4__DENALI_PHY_1554_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1554_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__REG DENALI_PHY_1554 +#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_2__FLD LPDDR4__DENALI_PHY_1554__PHY_ADR_CALVL_CH1_OBS0_2 + +#define LPDDR4__DENALI_PHY_1555_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1555_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1555 +#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1555__PHY_ADR_CALVL_OBS1_2 + +#define LPDDR4__DENALI_PHY_1556_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1556_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2_WIDTH 32U +#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1556 +#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1556__PHY_ADR_CALVL_OBS2_2 + +#define LPDDR4__DENALI_PHY_1557_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1557_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1557 +#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1557__PHY_ADR_CALVL_FG_0_2 + +#define LPDDR4__DENALI_PHY_1558_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1558_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1558 +#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1558__PHY_ADR_CALVL_BG_0_2 + +#define LPDDR4__DENALI_PHY_1559_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1559_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1559 +#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1559__PHY_ADR_CALVL_FG_1_2 + +#define LPDDR4__DENALI_PHY_1560_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1560_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1560 +#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1560__PHY_ADR_CALVL_BG_1_2 + +#define LPDDR4__DENALI_PHY_1561_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1561_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1561 +#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1561__PHY_ADR_CALVL_FG_2_2 + +#define LPDDR4__DENALI_PHY_1562_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1562_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1562 +#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1562__PHY_ADR_CALVL_BG_2_2 + +#define LPDDR4__DENALI_PHY_1563_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1563_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1563 +#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1563__PHY_ADR_CALVL_FG_3_2 + +#define LPDDR4__DENALI_PHY_1564_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1564_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2_WIDTH 20U +#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1564 +#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1564__PHY_ADR_CALVL_BG_3_2 + +#define LPDDR4__DENALI_PHY_1565_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1565_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2_WIDTH 30U +#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1565 +#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1565__PHY_ADR_ADDR_SEL_2 + +#define LPDDR4__DENALI_PHY_1566_READ_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1566_WRITE_MASK 0x3F3F03FFU +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1566 +#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_LP4_BOOT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1566 +#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_BIT_MASK_2 + +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1566 +#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1566__PHY_ADR_SEG_MASK_2 + +#define LPDDR4__DENALI_PHY_1567_READ_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1567_WRITE_MASK 0x3F0F3F3FU +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1567 +#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CALVL_TRAIN_MASK_2 + +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1567 +#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_CSLVL_TRAIN_MASK_2 + +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1567 +#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_STATIC_TOG_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1567 +#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1567__PHY_ADR_SW_TXIO_CTRL_2 + +#define LPDDR4__DENALI_PHY_1568_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1568_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__REG DENALI_PHY_1568 +#define LPDDR4__PHY_ADR_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_INIT_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__REG DENALI_PHY_1568 +#define LPDDR4__PHY_ADR_DC_ADR0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR0_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__REG DENALI_PHY_1568 +#define LPDDR4__PHY_ADR_DC_ADR1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR1_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__REG DENALI_PHY_1568 +#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1568__PHY_ADR_DC_ADR2_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_1569_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1569_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__REG DENALI_PHY_1569 +#define LPDDR4__PHY_ADR_DC_ADR3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR3_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__REG DENALI_PHY_1569 +#define LPDDR4__PHY_ADR_DC_ADR4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR4_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__REG DENALI_PHY_1569 +#define LPDDR4__PHY_ADR_DC_ADR5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DC_ADR5_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1569 +#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1569__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_1570_READ_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1570_WRITE_MASK 0x3F03FFFFU +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_1570 +#define LPDDR4__PHY_ADR_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_SAMPLE_WAIT_2 + +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__REG DENALI_PHY_1570 +#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_CAL_TIMEOUT_2 + +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2_WIDTH 2U +#define LPDDR4__PHY_ADR_DC_WEIGHT_2__REG DENALI_PHY_1570 +#define LPDDR4__PHY_ADR_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_WEIGHT_2 + +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2_WIDTH 6U +#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__REG DENALI_PHY_1570 +#define LPDDR4__PHY_ADR_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_1570__PHY_ADR_DC_ADJUST_START_2 + +#define LPDDR4__DENALI_PHY_1571_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1571_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_1571 +#define LPDDR4__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_SAMPLE_CNT_2 + +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_1571 +#define LPDDR4__PHY_ADR_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2_WOSET 0U +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__REG DENALI_PHY_1571 +#define LPDDR4__PHY_ADR_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_ADJUST_DIRECT_2 + +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__REG DENALI_PHY_1571 +#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_1571__PHY_ADR_DC_CAL_POLARITY_2 + +#define LPDDR4__DENALI_PHY_1572_READ_MASK 0x00003F01U +#define LPDDR4__DENALI_PHY_1572_WRITE_MASK 0x00003F01U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CAL_START_2__REG DENALI_PHY_1572 +#define LPDDR4__PHY_ADR_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_DC_CAL_START_2 + +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1572 +#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1572__PHY_ADR_SW_TXPWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_1573_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1573_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1573 +#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__REG DENALI_PHY_1573 +#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1573__PHY_ADR_DC_CAL_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U +#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1573 +#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1573__PHY_PAD_ADR_IO_CFG_2 + +#define LPDDR4__DENALI_PHY_1574_READ_MASK 0x07FF1F07U +#define LPDDR4__DENALI_PHY_1574_WRITE_MASK 0x07FF1F07U +#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1574 +#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1574__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1574 +#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1574 +#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1574__PHY_ADR0_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1575_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1575_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575 +#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1575 +#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR1_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1575 +#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1575__PHY_ADR2_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1576_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1576_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1576 +#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR2_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1576 +#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1576__PHY_ADR3_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1577_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1577_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1577 +#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR3_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1577 +#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1577__PHY_ADR4_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1578_READ_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1578_WRITE_MASK 0x001F07FFU +#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1578 +#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR4_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1578 +#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1578__PHY_ADR5_SW_WRADDR_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1579_READ_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1579_WRITE_MASK 0x000F07FFU +#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1579 +#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR5_CLK_WR_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1579 +#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1579__PHY_ADR_SW_MASTER_MODE_2 + +#define LPDDR4__DENALI_PHY_1580_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1580_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1580 +#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_START_2 + +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1580 +#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_STEP_2 + +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1580 +#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1580__PHY_ADR_MASTER_DELAY_WAIT_2 + +#define LPDDR4__DENALI_PHY_1581_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1581_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1581 +#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2 + +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1581 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1581 +#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1581__PHY_ADR_SW_CALVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_1582_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1582_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1582 +#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1582__PHY_ADR_CALVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_1583_READ_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1583_WRITE_MASK 0x03FF010FU +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1583 +#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_CALVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1583 +#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_MEAS_DLY_STEP_ENABLE_2 + +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__REG DENALI_PHY_1583 +#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1583__PHY_ADR_DC_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_1584_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1584_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__REG DENALI_PHY_1584 +#define LPDDR4__PHY_ADR_DC_CALVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_CALVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__REG DENALI_PHY_1584 +#define LPDDR4__PHY_ADR_DC_DM_CLK_THRSHLD_2__FLD LPDDR4__DENALI_PHY_1584__PHY_ADR_DC_DM_CLK_THRSHLD_2 + +#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h new file mode 100644 index 0000000000..22384a1b74 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_ctl_regs_rw_masks.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_RW_MASKS_H_ +#define LPDDR4_RW_MASKS_H_ + +#include + +extern u32 g_lpddr4_ddr_controller_rw_mask[435]; +extern u32 g_lpddr4_pi_rw_mask[424]; +extern u32 g_lpddr4_data_slice_0_rw_mask[137]; +extern u32 g_lpddr4_data_slice_1_rw_mask[137]; +extern u32 g_lpddr4_data_slice_2_rw_mask[137]; +extern u32 g_lpddr4_data_slice_3_rw_mask[137]; +extern u32 g_lpddr4_address_slice_0_rw_mask[49]; +extern u32 g_lpddr4_address_slice_1_rw_mask[49]; +extern u32 g_lpddr4_address_slice_2_rw_mask[49]; +extern u32 g_lpddr4_phy_core_rw_mask[132]; + +#endif /* LPDDR4_RW_MASKS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h new file mode 100644 index 0000000000..102184a502 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_if.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_AM62A_IF_H +#define LPDDR4_AM62A_IF_H + +#include + +#define LPDDR4_INTR_MAX_CS (2U) + +#define LPDDR4_INTR_CTL_REG_COUNT (435U) + +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (424U) + +#define LPDDR4_INTR_PHY_REG_COUNT (1924U) + +typedef enum { + LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U, + LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U, + LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U, + LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U, + LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U, + LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U, + LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U, + LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U, + LPDDR4_INTR_ECC_ERROR = 8U, + LPDDR4_INTR_LP_DONE = 9U, + LPDDR4_INTR_LP_TIMEOUT = 10U, + LPDDR4_INTR_PORT_TIMEOUT = 11U, + LPDDR4_INTR_RFIFO_TIMEOUT = 12U, + LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U, + LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U, + LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U, + LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U, + LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U, + LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U, + LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U, + LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U, + LPDDR4_INTR_USERIF_WRAP = 21U, + LPDDR4_INTR_USERIF_INVAL_SETTING = 22U, + LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U, + LPDDR4_INTR_MISC_SW_REQ_MODE = 24U, + LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U, + LPDDR4_INTR_MISC_TEMP_ALERT = 26U, + LPDDR4_INTR_MISC_REFRESH_STATUS = 27U, + LPDDR4_INTR_BIST_DONE = 28U, + LPDDR4_INTR_CRC = 29U, + LPDDR4_INTR_DFI_UPDATE_ERROR = 30U, + LPDDR4_INTR_DFI_PHY_ERROR = 31U, + LPDDR4_INTR_DFI_BUS_ERROR = 32U, + LPDDR4_INTR_DFI_STATE_CHANGE = 33U, + LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U, + LPDDR4_INTR_DFI_TIMEOUT = 35U, + LPDDR4_INTR_DIMM = 36U, + LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U, + LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U, + LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U, + LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U, + LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U, + LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U, + LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U, + LPDDR4_INTR_MC_INIT_DONE = 44U, + LPDDR4_INTR_INIT_POWER_ON_STATE = 45U, + LPDDR4_INTR_MRR_ERROR = 46U, + LPDDR4_INTR_MR_READ_DONE = 47U, + LPDDR4_INTR_MR_WRITE_DONE = 48U, + LPDDR4_INTR_PARITY_ERROR = 49U, + LPDDR4_INTR_LOR_BITS = 50U +} lpddr4_intr_ctlinterrupt; + +typedef enum { + LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U, + LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U, + LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U, + LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U, + LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U, + LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U, + LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U, + LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U, + LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U, + LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U, + LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U, + LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U, + LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U, + LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U, + LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U, + LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U, + LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U, + LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U, + LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U, + LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U, + LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U, + LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U, + LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U, + LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U, + LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U, + LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U, + LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U +} lpddr4_intr_phyindepinterrupt; + +#endif /* LPDDR4_AM62A_IF_H */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h new file mode 100644 index 0000000000..4c41863c5b --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_obj_if.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_AM62A_OBJ_IF_H +#define LPDDR4_AM62A_OBJ_IF_H + +#include "lpddr4_am62a_if.h" + +#endif /* LPDDR4_AM62A_OBJ_IF_H */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h new file mode 100644 index 0000000000..ab2b1f1a0f --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_am62a_structs_if.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_AM62A_STRUCTS_IF_H +#define LPDDR4_AM62A_STRUCTS_IF_H + +#include +#include "lpddr4_am62a_if.h" + +#endif /* LPDDR4_AM62A_STRUCTS_IF_H */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h new file mode 100644 index 0000000000..7a9ec00c8a --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_ctl_regs.h @@ -0,0 +1,1721 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_CTL_REGS_H_ +#define REG_LPDDR4_CTL_REGS_H_ + +#include "lpddr4_ddr_controller_macros.h" +#include "lpddr4_pi_macros.h" +#include "lpddr4_data_slice_0_macros.h" +#include "lpddr4_data_slice_1_macros.h" +#include "lpddr4_data_slice_2_macros.h" +#include "lpddr4_data_slice_3_macros.h" +#include "lpddr4_address_slice_0_macros.h" +#include "lpddr4_address_slice_1_macros.h" +#include "lpddr4_address_slice_2_macros.h" +#include "lpddr4_phy_core_macros.h" + +typedef struct __attribute__((packed)) lpddr4_ctlregs_s { + volatile u32 DENALI_CTL_0; + volatile u32 DENALI_CTL_1; + volatile u32 DENALI_CTL_2; + volatile u32 DENALI_CTL_3; + volatile u32 DENALI_CTL_4; + volatile u32 DENALI_CTL_5; + volatile u32 DENALI_CTL_6; + volatile u32 DENALI_CTL_7; + volatile u32 DENALI_CTL_8; + volatile u32 DENALI_CTL_9; + volatile u32 DENALI_CTL_10; + volatile u32 DENALI_CTL_11; + volatile u32 DENALI_CTL_12; + volatile u32 DENALI_CTL_13; + volatile u32 DENALI_CTL_14; + volatile u32 DENALI_CTL_15; + volatile u32 DENALI_CTL_16; + volatile u32 DENALI_CTL_17; + volatile u32 DENALI_CTL_18; + volatile u32 DENALI_CTL_19; + volatile u32 DENALI_CTL_20; + volatile u32 DENALI_CTL_21; + volatile u32 DENALI_CTL_22; + volatile u32 DENALI_CTL_23; + volatile u32 DENALI_CTL_24; + volatile u32 DENALI_CTL_25; + volatile u32 DENALI_CTL_26; + volatile u32 DENALI_CTL_27; + volatile u32 DENALI_CTL_28; + volatile u32 DENALI_CTL_29; + volatile u32 DENALI_CTL_30; + volatile u32 DENALI_CTL_31; + volatile u32 DENALI_CTL_32; + volatile u32 DENALI_CTL_33; + volatile u32 DENALI_CTL_34; + volatile u32 DENALI_CTL_35; + volatile u32 DENALI_CTL_36; + volatile u32 DENALI_CTL_37; + volatile u32 DENALI_CTL_38; + volatile u32 DENALI_CTL_39; + volatile u32 DENALI_CTL_40; + volatile u32 DENALI_CTL_41; + volatile u32 DENALI_CTL_42; + volatile u32 DENALI_CTL_43; + volatile u32 DENALI_CTL_44; + volatile u32 DENALI_CTL_45; + volatile u32 DENALI_CTL_46; + volatile u32 DENALI_CTL_47; + volatile u32 DENALI_CTL_48; + volatile u32 DENALI_CTL_49; + volatile u32 DENALI_CTL_50; + volatile u32 DENALI_CTL_51; + volatile u32 DENALI_CTL_52; + volatile u32 DENALI_CTL_53; + volatile u32 DENALI_CTL_54; + volatile u32 DENALI_CTL_55; + volatile u32 DENALI_CTL_56; + volatile u32 DENALI_CTL_57; + volatile u32 DENALI_CTL_58; + volatile u32 DENALI_CTL_59; + volatile u32 DENALI_CTL_60; + volatile u32 DENALI_CTL_61; + volatile u32 DENALI_CTL_62; + volatile u32 DENALI_CTL_63; + volatile u32 DENALI_CTL_64; + volatile u32 DENALI_CTL_65; + volatile u32 DENALI_CTL_66; + volatile u32 DENALI_CTL_67; + volatile u32 DENALI_CTL_68; + volatile u32 DENALI_CTL_69; + volatile u32 DENALI_CTL_70; + volatile u32 DENALI_CTL_71; + volatile u32 DENALI_CTL_72; + volatile u32 DENALI_CTL_73; + volatile u32 DENALI_CTL_74; + volatile u32 DENALI_CTL_75; + volatile u32 DENALI_CTL_76; + volatile u32 DENALI_CTL_77; + volatile u32 DENALI_CTL_78; + volatile u32 DENALI_CTL_79; + volatile u32 DENALI_CTL_80; + volatile u32 DENALI_CTL_81; + volatile u32 DENALI_CTL_82; + volatile u32 DENALI_CTL_83; + volatile u32 DENALI_CTL_84; + volatile u32 DENALI_CTL_85; + volatile u32 DENALI_CTL_86; + volatile u32 DENALI_CTL_87; + volatile u32 DENALI_CTL_88; + volatile u32 DENALI_CTL_89; + volatile u32 DENALI_CTL_90; + volatile u32 DENALI_CTL_91; + volatile u32 DENALI_CTL_92; + volatile u32 DENALI_CTL_93; + volatile u32 DENALI_CTL_94; + volatile u32 DENALI_CTL_95; + volatile u32 DENALI_CTL_96; + volatile u32 DENALI_CTL_97; + volatile u32 DENALI_CTL_98; + volatile u32 DENALI_CTL_99; + volatile u32 DENALI_CTL_100; + volatile u32 DENALI_CTL_101; + volatile u32 DENALI_CTL_102; + volatile u32 DENALI_CTL_103; + volatile u32 DENALI_CTL_104; + volatile u32 DENALI_CTL_105; + volatile u32 DENALI_CTL_106; + volatile u32 DENALI_CTL_107; + volatile u32 DENALI_CTL_108; + volatile u32 DENALI_CTL_109; + volatile u32 DENALI_CTL_110; + volatile u32 DENALI_CTL_111; + volatile u32 DENALI_CTL_112; + volatile u32 DENALI_CTL_113; + volatile u32 DENALI_CTL_114; + volatile u32 DENALI_CTL_115; + volatile u32 DENALI_CTL_116; + volatile u32 DENALI_CTL_117; + volatile u32 DENALI_CTL_118; + volatile u32 DENALI_CTL_119; + volatile u32 DENALI_CTL_120; + volatile u32 DENALI_CTL_121; + volatile u32 DENALI_CTL_122; + volatile u32 DENALI_CTL_123; + volatile u32 DENALI_CTL_124; + volatile u32 DENALI_CTL_125; + volatile u32 DENALI_CTL_126; + volatile u32 DENALI_CTL_127; + volatile u32 DENALI_CTL_128; + volatile u32 DENALI_CTL_129; + volatile u32 DENALI_CTL_130; + volatile u32 DENALI_CTL_131; + volatile u32 DENALI_CTL_132; + volatile u32 DENALI_CTL_133; + volatile u32 DENALI_CTL_134; + volatile u32 DENALI_CTL_135; + volatile u32 DENALI_CTL_136; + volatile u32 DENALI_CTL_137; + volatile u32 DENALI_CTL_138; + volatile u32 DENALI_CTL_139; + volatile u32 DENALI_CTL_140; + volatile u32 DENALI_CTL_141; + volatile u32 DENALI_CTL_142; + volatile u32 DENALI_CTL_143; + volatile u32 DENALI_CTL_144; + volatile u32 DENALI_CTL_145; + volatile u32 DENALI_CTL_146; + volatile u32 DENALI_CTL_147; + volatile u32 DENALI_CTL_148; + volatile u32 DENALI_CTL_149; + volatile u32 DENALI_CTL_150; + volatile u32 DENALI_CTL_151; + volatile u32 DENALI_CTL_152; + volatile u32 DENALI_CTL_153; + volatile u32 DENALI_CTL_154; + volatile u32 DENALI_CTL_155; + volatile u32 DENALI_CTL_156; + volatile u32 DENALI_CTL_157; + volatile u32 DENALI_CTL_158; + volatile u32 DENALI_CTL_159; + volatile u32 DENALI_CTL_160; + volatile u32 DENALI_CTL_161; + volatile u32 DENALI_CTL_162; + volatile u32 DENALI_CTL_163; + volatile u32 DENALI_CTL_164; + volatile u32 DENALI_CTL_165; + volatile u32 DENALI_CTL_166; + volatile u32 DENALI_CTL_167; + volatile u32 DENALI_CTL_168; + volatile u32 DENALI_CTL_169; + volatile u32 DENALI_CTL_170; + volatile u32 DENALI_CTL_171; + volatile u32 DENALI_CTL_172; + volatile u32 DENALI_CTL_173; + volatile u32 DENALI_CTL_174; + volatile u32 DENALI_CTL_175; + volatile u32 DENALI_CTL_176; + volatile u32 DENALI_CTL_177; + volatile u32 DENALI_CTL_178; + volatile u32 DENALI_CTL_179; + volatile u32 DENALI_CTL_180; + volatile u32 DENALI_CTL_181; + volatile u32 DENALI_CTL_182; + volatile u32 DENALI_CTL_183; + volatile u32 DENALI_CTL_184; + volatile u32 DENALI_CTL_185; + volatile u32 DENALI_CTL_186; + volatile u32 DENALI_CTL_187; + volatile u32 DENALI_CTL_188; + volatile u32 DENALI_CTL_189; + volatile u32 DENALI_CTL_190; + volatile u32 DENALI_CTL_191; + volatile u32 DENALI_CTL_192; + volatile u32 DENALI_CTL_193; + volatile u32 DENALI_CTL_194; + volatile u32 DENALI_CTL_195; + volatile u32 DENALI_CTL_196; + volatile u32 DENALI_CTL_197; + volatile u32 DENALI_CTL_198; + volatile u32 DENALI_CTL_199; + volatile u32 DENALI_CTL_200; + volatile u32 DENALI_CTL_201; + volatile u32 DENALI_CTL_202; + volatile u32 DENALI_CTL_203; + volatile u32 DENALI_CTL_204; + volatile u32 DENALI_CTL_205; + volatile u32 DENALI_CTL_206; + volatile u32 DENALI_CTL_207; + volatile u32 DENALI_CTL_208; + volatile u32 DENALI_CTL_209; + volatile u32 DENALI_CTL_210; + volatile u32 DENALI_CTL_211; + volatile u32 DENALI_CTL_212; + volatile u32 DENALI_CTL_213; + volatile u32 DENALI_CTL_214; + volatile u32 DENALI_CTL_215; + volatile u32 DENALI_CTL_216; + volatile u32 DENALI_CTL_217; + volatile u32 DENALI_CTL_218; + volatile u32 DENALI_CTL_219; + volatile u32 DENALI_CTL_220; + volatile u32 DENALI_CTL_221; + volatile u32 DENALI_CTL_222; + volatile u32 DENALI_CTL_223; + volatile u32 DENALI_CTL_224; + volatile u32 DENALI_CTL_225; + volatile u32 DENALI_CTL_226; + volatile u32 DENALI_CTL_227; + volatile u32 DENALI_CTL_228; + volatile u32 DENALI_CTL_229; + volatile u32 DENALI_CTL_230; + volatile u32 DENALI_CTL_231; + volatile u32 DENALI_CTL_232; + volatile u32 DENALI_CTL_233; + volatile u32 DENALI_CTL_234; + volatile u32 DENALI_CTL_235; + volatile u32 DENALI_CTL_236; + volatile u32 DENALI_CTL_237; + volatile u32 DENALI_CTL_238; + volatile u32 DENALI_CTL_239; + volatile u32 DENALI_CTL_240; + volatile u32 DENALI_CTL_241; + volatile u32 DENALI_CTL_242; + volatile u32 DENALI_CTL_243; + volatile u32 DENALI_CTL_244; + volatile u32 DENALI_CTL_245; + volatile u32 DENALI_CTL_246; + volatile u32 DENALI_CTL_247; + volatile u32 DENALI_CTL_248; + volatile u32 DENALI_CTL_249; + volatile u32 DENALI_CTL_250; + volatile u32 DENALI_CTL_251; + volatile u32 DENALI_CTL_252; + volatile u32 DENALI_CTL_253; + volatile u32 DENALI_CTL_254; + volatile u32 DENALI_CTL_255; + volatile u32 DENALI_CTL_256; + volatile u32 DENALI_CTL_257; + volatile u32 DENALI_CTL_258; + volatile u32 DENALI_CTL_259; + volatile u32 DENALI_CTL_260; + volatile u32 DENALI_CTL_261; + volatile u32 DENALI_CTL_262; + volatile u32 DENALI_CTL_263; + volatile u32 DENALI_CTL_264; + volatile u32 DENALI_CTL_265; + volatile u32 DENALI_CTL_266; + volatile u32 DENALI_CTL_267; + volatile u32 DENALI_CTL_268; + volatile u32 DENALI_CTL_269; + volatile u32 DENALI_CTL_270; + volatile u32 DENALI_CTL_271; + volatile u32 DENALI_CTL_272; + volatile u32 DENALI_CTL_273; + volatile u32 DENALI_CTL_274; + volatile u32 DENALI_CTL_275; + volatile u32 DENALI_CTL_276; + volatile u32 DENALI_CTL_277; + volatile u32 DENALI_CTL_278; + volatile u32 DENALI_CTL_279; + volatile u32 DENALI_CTL_280; + volatile u32 DENALI_CTL_281; + volatile u32 DENALI_CTL_282; + volatile u32 DENALI_CTL_283; + volatile u32 DENALI_CTL_284; + volatile u32 DENALI_CTL_285; + volatile u32 DENALI_CTL_286; + volatile u32 DENALI_CTL_287; + volatile u32 DENALI_CTL_288; + volatile u32 DENALI_CTL_289; + volatile u32 DENALI_CTL_290; + volatile u32 DENALI_CTL_291; + volatile u32 DENALI_CTL_292; + volatile u32 DENALI_CTL_293; + volatile u32 DENALI_CTL_294; + volatile u32 DENALI_CTL_295; + volatile u32 DENALI_CTL_296; + volatile u32 DENALI_CTL_297; + volatile u32 DENALI_CTL_298; + volatile u32 DENALI_CTL_299; + volatile u32 DENALI_CTL_300; + volatile u32 DENALI_CTL_301; + volatile u32 DENALI_CTL_302; + volatile u32 DENALI_CTL_303; + volatile u32 DENALI_CTL_304; + volatile u32 DENALI_CTL_305; + volatile u32 DENALI_CTL_306; + volatile u32 DENALI_CTL_307; + volatile u32 DENALI_CTL_308; + volatile u32 DENALI_CTL_309; + volatile u32 DENALI_CTL_310; + volatile u32 DENALI_CTL_311; + volatile u32 DENALI_CTL_312; + volatile u32 DENALI_CTL_313; + volatile u32 DENALI_CTL_314; + volatile u32 DENALI_CTL_315; + volatile u32 DENALI_CTL_316; + volatile u32 DENALI_CTL_317; + volatile u32 DENALI_CTL_318; + volatile u32 DENALI_CTL_319; + volatile u32 DENALI_CTL_320; + volatile u32 DENALI_CTL_321; + volatile u32 DENALI_CTL_322; + volatile u32 DENALI_CTL_323; + volatile u32 DENALI_CTL_324; + volatile u32 DENALI_CTL_325; + volatile u32 DENALI_CTL_326; + volatile u32 DENALI_CTL_327; + volatile u32 DENALI_CTL_328; + volatile u32 DENALI_CTL_329; + volatile u32 DENALI_CTL_330; + volatile u32 DENALI_CTL_331; + volatile u32 DENALI_CTL_332; + volatile u32 DENALI_CTL_333; + volatile u32 DENALI_CTL_334; + volatile u32 DENALI_CTL_335; + volatile u32 DENALI_CTL_336; + volatile u32 DENALI_CTL_337; + volatile u32 DENALI_CTL_338; + volatile u32 DENALI_CTL_339; + volatile u32 DENALI_CTL_340; + volatile u32 DENALI_CTL_341; + volatile u32 DENALI_CTL_342; + volatile u32 DENALI_CTL_343; + volatile u32 DENALI_CTL_344; + volatile u32 DENALI_CTL_345; + volatile u32 DENALI_CTL_346; + volatile u32 DENALI_CTL_347; + volatile u32 DENALI_CTL_348; + volatile u32 DENALI_CTL_349; + volatile u32 DENALI_CTL_350; + volatile u32 DENALI_CTL_351; + volatile u32 DENALI_CTL_352; + volatile u32 DENALI_CTL_353; + volatile u32 DENALI_CTL_354; + volatile u32 DENALI_CTL_355; + volatile u32 DENALI_CTL_356; + volatile u32 DENALI_CTL_357; + volatile u32 DENALI_CTL_358; + volatile u32 DENALI_CTL_359; + volatile u32 DENALI_CTL_360; + volatile u32 DENALI_CTL_361; + volatile u32 DENALI_CTL_362; + volatile u32 DENALI_CTL_363; + volatile u32 DENALI_CTL_364; + volatile u32 DENALI_CTL_365; + volatile u32 DENALI_CTL_366; + volatile u32 DENALI_CTL_367; + volatile u32 DENALI_CTL_368; + volatile u32 DENALI_CTL_369; + volatile u32 DENALI_CTL_370; + volatile u32 DENALI_CTL_371; + volatile u32 DENALI_CTL_372; + volatile u32 DENALI_CTL_373; + volatile u32 DENALI_CTL_374; + volatile u32 DENALI_CTL_375; + volatile u32 DENALI_CTL_376; + volatile u32 DENALI_CTL_377; + volatile u32 DENALI_CTL_378; + volatile u32 DENALI_CTL_379; + volatile u32 DENALI_CTL_380; + volatile u32 DENALI_CTL_381; + volatile u32 DENALI_CTL_382; + volatile u32 DENALI_CTL_383; + volatile u32 DENALI_CTL_384; + volatile u32 DENALI_CTL_385; + volatile u32 DENALI_CTL_386; + volatile u32 DENALI_CTL_387; + volatile u32 DENALI_CTL_388; + volatile u32 DENALI_CTL_389; + volatile u32 DENALI_CTL_390; + volatile u32 DENALI_CTL_391; + volatile u32 DENALI_CTL_392; + volatile u32 DENALI_CTL_393; + volatile u32 DENALI_CTL_394; + volatile u32 DENALI_CTL_395; + volatile u32 DENALI_CTL_396; + volatile u32 DENALI_CTL_397; + volatile u32 DENALI_CTL_398; + volatile u32 DENALI_CTL_399; + volatile u32 DENALI_CTL_400; + volatile u32 DENALI_CTL_401; + volatile u32 DENALI_CTL_402; + volatile u32 DENALI_CTL_403; + volatile u32 DENALI_CTL_404; + volatile u32 DENALI_CTL_405; + volatile u32 DENALI_CTL_406; + volatile u32 DENALI_CTL_407; + volatile u32 DENALI_CTL_408; + volatile u32 DENALI_CTL_409; + volatile u32 DENALI_CTL_410; + volatile u32 DENALI_CTL_411; + volatile u32 DENALI_CTL_412; + volatile u32 DENALI_CTL_413; + volatile u32 DENALI_CTL_414; + volatile u32 DENALI_CTL_415; + volatile u32 DENALI_CTL_416; + volatile u32 DENALI_CTL_417; + volatile u32 DENALI_CTL_418; + volatile u32 DENALI_CTL_419; + volatile u32 DENALI_CTL_420; + volatile u32 DENALI_CTL_421; + volatile u32 DENALI_CTL_422; + volatile u32 DENALI_CTL_423; + volatile u32 DENALI_CTL_424; + volatile u32 DENALI_CTL_425; + volatile u32 DENALI_CTL_426; + volatile u32 DENALI_CTL_427; + volatile u32 DENALI_CTL_428; + volatile u32 DENALI_CTL_429; + volatile u32 DENALI_CTL_430; + volatile u32 DENALI_CTL_431; + volatile u32 DENALI_CTL_432; + volatile u32 DENALI_CTL_433; + volatile u32 DENALI_CTL_434; + volatile char pad__0[0x1934U]; + volatile u32 DENALI_PI_0; + volatile u32 DENALI_PI_1; + volatile u32 DENALI_PI_2; + volatile u32 DENALI_PI_3; + volatile u32 DENALI_PI_4; + volatile u32 DENALI_PI_5; + volatile u32 DENALI_PI_6; + volatile u32 DENALI_PI_7; + volatile u32 DENALI_PI_8; + volatile u32 DENALI_PI_9; + volatile u32 DENALI_PI_10; + volatile u32 DENALI_PI_11; + volatile u32 DENALI_PI_12; + volatile u32 DENALI_PI_13; + volatile u32 DENALI_PI_14; + volatile u32 DENALI_PI_15; + volatile u32 DENALI_PI_16; + volatile u32 DENALI_PI_17; + volatile u32 DENALI_PI_18; + volatile u32 DENALI_PI_19; + volatile u32 DENALI_PI_20; + volatile u32 DENALI_PI_21; + volatile u32 DENALI_PI_22; + volatile u32 DENALI_PI_23; + volatile u32 DENALI_PI_24; + volatile u32 DENALI_PI_25; + volatile u32 DENALI_PI_26; + volatile u32 DENALI_PI_27; + volatile u32 DENALI_PI_28; + volatile u32 DENALI_PI_29; + volatile u32 DENALI_PI_30; + volatile u32 DENALI_PI_31; + volatile u32 DENALI_PI_32; + volatile u32 DENALI_PI_33; + volatile u32 DENALI_PI_34; + volatile u32 DENALI_PI_35; + volatile u32 DENALI_PI_36; + volatile u32 DENALI_PI_37; + volatile u32 DENALI_PI_38; + volatile u32 DENALI_PI_39; + volatile u32 DENALI_PI_40; + volatile u32 DENALI_PI_41; + volatile u32 DENALI_PI_42; + volatile u32 DENALI_PI_43; + volatile u32 DENALI_PI_44; + volatile u32 DENALI_PI_45; + volatile u32 DENALI_PI_46; + volatile u32 DENALI_PI_47; + volatile u32 DENALI_PI_48; + volatile u32 DENALI_PI_49; + volatile u32 DENALI_PI_50; + volatile u32 DENALI_PI_51; + volatile u32 DENALI_PI_52; + volatile u32 DENALI_PI_53; + volatile u32 DENALI_PI_54; + volatile u32 DENALI_PI_55; + volatile u32 DENALI_PI_56; + volatile u32 DENALI_PI_57; + volatile u32 DENALI_PI_58; + volatile u32 DENALI_PI_59; + volatile u32 DENALI_PI_60; + volatile u32 DENALI_PI_61; + volatile u32 DENALI_PI_62; + volatile u32 DENALI_PI_63; + volatile u32 DENALI_PI_64; + volatile u32 DENALI_PI_65; + volatile u32 DENALI_PI_66; + volatile u32 DENALI_PI_67; + volatile u32 DENALI_PI_68; + volatile u32 DENALI_PI_69; + volatile u32 DENALI_PI_70; + volatile u32 DENALI_PI_71; + volatile u32 DENALI_PI_72; + volatile u32 DENALI_PI_73; + volatile u32 DENALI_PI_74; + volatile u32 DENALI_PI_75; + volatile u32 DENALI_PI_76; + volatile u32 DENALI_PI_77; + volatile u32 DENALI_PI_78; + volatile u32 DENALI_PI_79; + volatile u32 DENALI_PI_80; + volatile u32 DENALI_PI_81; + volatile u32 DENALI_PI_82; + volatile u32 DENALI_PI_83; + volatile u32 DENALI_PI_84; + volatile u32 DENALI_PI_85; + volatile u32 DENALI_PI_86; + volatile u32 DENALI_PI_87; + volatile u32 DENALI_PI_88; + volatile u32 DENALI_PI_89; + volatile u32 DENALI_PI_90; + volatile u32 DENALI_PI_91; + volatile u32 DENALI_PI_92; + volatile u32 DENALI_PI_93; + volatile u32 DENALI_PI_94; + volatile u32 DENALI_PI_95; + volatile u32 DENALI_PI_96; + volatile u32 DENALI_PI_97; + volatile u32 DENALI_PI_98; + volatile u32 DENALI_PI_99; + volatile u32 DENALI_PI_100; + volatile u32 DENALI_PI_101; + volatile u32 DENALI_PI_102; + volatile u32 DENALI_PI_103; + volatile u32 DENALI_PI_104; + volatile u32 DENALI_PI_105; + volatile u32 DENALI_PI_106; + volatile u32 DENALI_PI_107; + volatile u32 DENALI_PI_108; + volatile u32 DENALI_PI_109; + volatile u32 DENALI_PI_110; + volatile u32 DENALI_PI_111; + volatile u32 DENALI_PI_112; + volatile u32 DENALI_PI_113; + volatile u32 DENALI_PI_114; + volatile u32 DENALI_PI_115; + volatile u32 DENALI_PI_116; + volatile u32 DENALI_PI_117; + volatile u32 DENALI_PI_118; + volatile u32 DENALI_PI_119; + volatile u32 DENALI_PI_120; + volatile u32 DENALI_PI_121; + volatile u32 DENALI_PI_122; + volatile u32 DENALI_PI_123; + volatile u32 DENALI_PI_124; + volatile u32 DENALI_PI_125; + volatile u32 DENALI_PI_126; + volatile u32 DENALI_PI_127; + volatile u32 DENALI_PI_128; + volatile u32 DENALI_PI_129; + volatile u32 DENALI_PI_130; + volatile u32 DENALI_PI_131; + volatile u32 DENALI_PI_132; + volatile u32 DENALI_PI_133; + volatile u32 DENALI_PI_134; + volatile u32 DENALI_PI_135; + volatile u32 DENALI_PI_136; + volatile u32 DENALI_PI_137; + volatile u32 DENALI_PI_138; + volatile u32 DENALI_PI_139; + volatile u32 DENALI_PI_140; + volatile u32 DENALI_PI_141; + volatile u32 DENALI_PI_142; + volatile u32 DENALI_PI_143; + volatile u32 DENALI_PI_144; + volatile u32 DENALI_PI_145; + volatile u32 DENALI_PI_146; + volatile u32 DENALI_PI_147; + volatile u32 DENALI_PI_148; + volatile u32 DENALI_PI_149; + volatile u32 DENALI_PI_150; + volatile u32 DENALI_PI_151; + volatile u32 DENALI_PI_152; + volatile u32 DENALI_PI_153; + volatile u32 DENALI_PI_154; + volatile u32 DENALI_PI_155; + volatile u32 DENALI_PI_156; + volatile u32 DENALI_PI_157; + volatile u32 DENALI_PI_158; + volatile u32 DENALI_PI_159; + volatile u32 DENALI_PI_160; + volatile u32 DENALI_PI_161; + volatile u32 DENALI_PI_162; + volatile u32 DENALI_PI_163; + volatile u32 DENALI_PI_164; + volatile u32 DENALI_PI_165; + volatile u32 DENALI_PI_166; + volatile u32 DENALI_PI_167; + volatile u32 DENALI_PI_168; + volatile u32 DENALI_PI_169; + volatile u32 DENALI_PI_170; + volatile u32 DENALI_PI_171; + volatile u32 DENALI_PI_172; + volatile u32 DENALI_PI_173; + volatile u32 DENALI_PI_174; + volatile u32 DENALI_PI_175; + volatile u32 DENALI_PI_176; + volatile u32 DENALI_PI_177; + volatile u32 DENALI_PI_178; + volatile u32 DENALI_PI_179; + volatile u32 DENALI_PI_180; + volatile u32 DENALI_PI_181; + volatile u32 DENALI_PI_182; + volatile u32 DENALI_PI_183; + volatile u32 DENALI_PI_184; + volatile u32 DENALI_PI_185; + volatile u32 DENALI_PI_186; + volatile u32 DENALI_PI_187; + volatile u32 DENALI_PI_188; + volatile u32 DENALI_PI_189; + volatile u32 DENALI_PI_190; + volatile u32 DENALI_PI_191; + volatile u32 DENALI_PI_192; + volatile u32 DENALI_PI_193; + volatile u32 DENALI_PI_194; + volatile u32 DENALI_PI_195; + volatile u32 DENALI_PI_196; + volatile u32 DENALI_PI_197; + volatile u32 DENALI_PI_198; + volatile u32 DENALI_PI_199; + volatile u32 DENALI_PI_200; + volatile u32 DENALI_PI_201; + volatile u32 DENALI_PI_202; + volatile u32 DENALI_PI_203; + volatile u32 DENALI_PI_204; + volatile u32 DENALI_PI_205; + volatile u32 DENALI_PI_206; + volatile u32 DENALI_PI_207; + volatile u32 DENALI_PI_208; + volatile u32 DENALI_PI_209; + volatile u32 DENALI_PI_210; + volatile u32 DENALI_PI_211; + volatile u32 DENALI_PI_212; + volatile u32 DENALI_PI_213; + volatile u32 DENALI_PI_214; + volatile u32 DENALI_PI_215; + volatile u32 DENALI_PI_216; + volatile u32 DENALI_PI_217; + volatile u32 DENALI_PI_218; + volatile u32 DENALI_PI_219; + volatile u32 DENALI_PI_220; + volatile u32 DENALI_PI_221; + volatile u32 DENALI_PI_222; + volatile u32 DENALI_PI_223; + volatile u32 DENALI_PI_224; + volatile u32 DENALI_PI_225; + volatile u32 DENALI_PI_226; + volatile u32 DENALI_PI_227; + volatile u32 DENALI_PI_228; + volatile u32 DENALI_PI_229; + volatile u32 DENALI_PI_230; + volatile u32 DENALI_PI_231; + volatile u32 DENALI_PI_232; + volatile u32 DENALI_PI_233; + volatile u32 DENALI_PI_234; + volatile u32 DENALI_PI_235; + volatile u32 DENALI_PI_236; + volatile u32 DENALI_PI_237; + volatile u32 DENALI_PI_238; + volatile u32 DENALI_PI_239; + volatile u32 DENALI_PI_240; + volatile u32 DENALI_PI_241; + volatile u32 DENALI_PI_242; + volatile u32 DENALI_PI_243; + volatile u32 DENALI_PI_244; + volatile u32 DENALI_PI_245; + volatile u32 DENALI_PI_246; + volatile u32 DENALI_PI_247; + volatile u32 DENALI_PI_248; + volatile u32 DENALI_PI_249; + volatile u32 DENALI_PI_250; + volatile u32 DENALI_PI_251; + volatile u32 DENALI_PI_252; + volatile u32 DENALI_PI_253; + volatile u32 DENALI_PI_254; + volatile u32 DENALI_PI_255; + volatile u32 DENALI_PI_256; + volatile u32 DENALI_PI_257; + volatile u32 DENALI_PI_258; + volatile u32 DENALI_PI_259; + volatile u32 DENALI_PI_260; + volatile u32 DENALI_PI_261; + volatile u32 DENALI_PI_262; + volatile u32 DENALI_PI_263; + volatile u32 DENALI_PI_264; + volatile u32 DENALI_PI_265; + volatile u32 DENALI_PI_266; + volatile u32 DENALI_PI_267; + volatile u32 DENALI_PI_268; + volatile u32 DENALI_PI_269; + volatile u32 DENALI_PI_270; + volatile u32 DENALI_PI_271; + volatile u32 DENALI_PI_272; + volatile u32 DENALI_PI_273; + volatile u32 DENALI_PI_274; + volatile u32 DENALI_PI_275; + volatile u32 DENALI_PI_276; + volatile u32 DENALI_PI_277; + volatile u32 DENALI_PI_278; + volatile u32 DENALI_PI_279; + volatile u32 DENALI_PI_280; + volatile u32 DENALI_PI_281; + volatile u32 DENALI_PI_282; + volatile u32 DENALI_PI_283; + volatile u32 DENALI_PI_284; + volatile u32 DENALI_PI_285; + volatile u32 DENALI_PI_286; + volatile u32 DENALI_PI_287; + volatile u32 DENALI_PI_288; + volatile u32 DENALI_PI_289; + volatile u32 DENALI_PI_290; + volatile u32 DENALI_PI_291; + volatile u32 DENALI_PI_292; + volatile u32 DENALI_PI_293; + volatile u32 DENALI_PI_294; + volatile u32 DENALI_PI_295; + volatile u32 DENALI_PI_296; + volatile u32 DENALI_PI_297; + volatile u32 DENALI_PI_298; + volatile u32 DENALI_PI_299; + volatile u32 DENALI_PI_300; + volatile u32 DENALI_PI_301; + volatile u32 DENALI_PI_302; + volatile u32 DENALI_PI_303; + volatile u32 DENALI_PI_304; + volatile u32 DENALI_PI_305; + volatile u32 DENALI_PI_306; + volatile u32 DENALI_PI_307; + volatile u32 DENALI_PI_308; + volatile u32 DENALI_PI_309; + volatile u32 DENALI_PI_310; + volatile u32 DENALI_PI_311; + volatile u32 DENALI_PI_312; + volatile u32 DENALI_PI_313; + volatile u32 DENALI_PI_314; + volatile u32 DENALI_PI_315; + volatile u32 DENALI_PI_316; + volatile u32 DENALI_PI_317; + volatile u32 DENALI_PI_318; + volatile u32 DENALI_PI_319; + volatile u32 DENALI_PI_320; + volatile u32 DENALI_PI_321; + volatile u32 DENALI_PI_322; + volatile u32 DENALI_PI_323; + volatile u32 DENALI_PI_324; + volatile u32 DENALI_PI_325; + volatile u32 DENALI_PI_326; + volatile u32 DENALI_PI_327; + volatile u32 DENALI_PI_328; + volatile u32 DENALI_PI_329; + volatile u32 DENALI_PI_330; + volatile u32 DENALI_PI_331; + volatile u32 DENALI_PI_332; + volatile u32 DENALI_PI_333; + volatile u32 DENALI_PI_334; + volatile u32 DENALI_PI_335; + volatile u32 DENALI_PI_336; + volatile u32 DENALI_PI_337; + volatile u32 DENALI_PI_338; + volatile u32 DENALI_PI_339; + volatile u32 DENALI_PI_340; + volatile u32 DENALI_PI_341; + volatile u32 DENALI_PI_342; + volatile u32 DENALI_PI_343; + volatile u32 DENALI_PI_344; + volatile u32 DENALI_PI_345; + volatile u32 DENALI_PI_346; + volatile u32 DENALI_PI_347; + volatile u32 DENALI_PI_348; + volatile u32 DENALI_PI_349; + volatile u32 DENALI_PI_350; + volatile u32 DENALI_PI_351; + volatile u32 DENALI_PI_352; + volatile u32 DENALI_PI_353; + volatile u32 DENALI_PI_354; + volatile u32 DENALI_PI_355; + volatile u32 DENALI_PI_356; + volatile u32 DENALI_PI_357; + volatile u32 DENALI_PI_358; + volatile u32 DENALI_PI_359; + volatile u32 DENALI_PI_360; + volatile u32 DENALI_PI_361; + volatile u32 DENALI_PI_362; + volatile u32 DENALI_PI_363; + volatile u32 DENALI_PI_364; + volatile u32 DENALI_PI_365; + volatile u32 DENALI_PI_366; + volatile u32 DENALI_PI_367; + volatile u32 DENALI_PI_368; + volatile u32 DENALI_PI_369; + volatile u32 DENALI_PI_370; + volatile u32 DENALI_PI_371; + volatile u32 DENALI_PI_372; + volatile u32 DENALI_PI_373; + volatile u32 DENALI_PI_374; + volatile u32 DENALI_PI_375; + volatile u32 DENALI_PI_376; + volatile u32 DENALI_PI_377; + volatile u32 DENALI_PI_378; + volatile u32 DENALI_PI_379; + volatile u32 DENALI_PI_380; + volatile u32 DENALI_PI_381; + volatile u32 DENALI_PI_382; + volatile u32 DENALI_PI_383; + volatile u32 DENALI_PI_384; + volatile u32 DENALI_PI_385; + volatile u32 DENALI_PI_386; + volatile u32 DENALI_PI_387; + volatile u32 DENALI_PI_388; + volatile u32 DENALI_PI_389; + volatile u32 DENALI_PI_390; + volatile u32 DENALI_PI_391; + volatile u32 DENALI_PI_392; + volatile u32 DENALI_PI_393; + volatile u32 DENALI_PI_394; + volatile u32 DENALI_PI_395; + volatile u32 DENALI_PI_396; + volatile u32 DENALI_PI_397; + volatile u32 DENALI_PI_398; + volatile u32 DENALI_PI_399; + volatile u32 DENALI_PI_400; + volatile u32 DENALI_PI_401; + volatile u32 DENALI_PI_402; + volatile u32 DENALI_PI_403; + volatile u32 DENALI_PI_404; + volatile u32 DENALI_PI_405; + volatile u32 DENALI_PI_406; + volatile u32 DENALI_PI_407; + volatile u32 DENALI_PI_408; + volatile u32 DENALI_PI_409; + volatile u32 DENALI_PI_410; + volatile u32 DENALI_PI_411; + volatile u32 DENALI_PI_412; + volatile u32 DENALI_PI_413; + volatile u32 DENALI_PI_414; + volatile u32 DENALI_PI_415; + volatile u32 DENALI_PI_416; + volatile u32 DENALI_PI_417; + volatile u32 DENALI_PI_418; + volatile u32 DENALI_PI_419; + volatile u32 DENALI_PI_420; + volatile u32 DENALI_PI_421; + volatile u32 DENALI_PI_422; + volatile u32 DENALI_PI_423; + volatile char pad__1[0x1960U]; + volatile u32 DENALI_PHY_0; + volatile u32 DENALI_PHY_1; + volatile u32 DENALI_PHY_2; + volatile u32 DENALI_PHY_3; + volatile u32 DENALI_PHY_4; + volatile u32 DENALI_PHY_5; + volatile u32 DENALI_PHY_6; + volatile u32 DENALI_PHY_7; + volatile u32 DENALI_PHY_8; + volatile u32 DENALI_PHY_9; + volatile u32 DENALI_PHY_10; + volatile u32 DENALI_PHY_11; + volatile u32 DENALI_PHY_12; + volatile u32 DENALI_PHY_13; + volatile u32 DENALI_PHY_14; + volatile u32 DENALI_PHY_15; + volatile u32 DENALI_PHY_16; + volatile u32 DENALI_PHY_17; + volatile u32 DENALI_PHY_18; + volatile u32 DENALI_PHY_19; + volatile u32 DENALI_PHY_20; + volatile u32 DENALI_PHY_21; + volatile u32 DENALI_PHY_22; + volatile u32 DENALI_PHY_23; + volatile u32 DENALI_PHY_24; + volatile u32 DENALI_PHY_25; + volatile u32 DENALI_PHY_26; + volatile u32 DENALI_PHY_27; + volatile u32 DENALI_PHY_28; + volatile u32 DENALI_PHY_29; + volatile u32 DENALI_PHY_30; + volatile u32 DENALI_PHY_31; + volatile u32 DENALI_PHY_32; + volatile u32 DENALI_PHY_33; + volatile u32 DENALI_PHY_34; + volatile u32 DENALI_PHY_35; + volatile u32 DENALI_PHY_36; + volatile u32 DENALI_PHY_37; + volatile u32 DENALI_PHY_38; + volatile u32 DENALI_PHY_39; + volatile u32 DENALI_PHY_40; + volatile u32 DENALI_PHY_41; + volatile u32 DENALI_PHY_42; + volatile u32 DENALI_PHY_43; + volatile u32 DENALI_PHY_44; + volatile u32 DENALI_PHY_45; + volatile u32 DENALI_PHY_46; + volatile u32 DENALI_PHY_47; + volatile u32 DENALI_PHY_48; + volatile u32 DENALI_PHY_49; + volatile u32 DENALI_PHY_50; + volatile u32 DENALI_PHY_51; + volatile u32 DENALI_PHY_52; + volatile u32 DENALI_PHY_53; + volatile u32 DENALI_PHY_54; + volatile u32 DENALI_PHY_55; + volatile u32 DENALI_PHY_56; + volatile u32 DENALI_PHY_57; + volatile u32 DENALI_PHY_58; + volatile u32 DENALI_PHY_59; + volatile u32 DENALI_PHY_60; + volatile u32 DENALI_PHY_61; + volatile u32 DENALI_PHY_62; + volatile u32 DENALI_PHY_63; + volatile u32 DENALI_PHY_64; + volatile u32 DENALI_PHY_65; + volatile u32 DENALI_PHY_66; + volatile u32 DENALI_PHY_67; + volatile u32 DENALI_PHY_68; + volatile u32 DENALI_PHY_69; + volatile u32 DENALI_PHY_70; + volatile u32 DENALI_PHY_71; + volatile u32 DENALI_PHY_72; + volatile u32 DENALI_PHY_73; + volatile u32 DENALI_PHY_74; + volatile u32 DENALI_PHY_75; + volatile u32 DENALI_PHY_76; + volatile u32 DENALI_PHY_77; + volatile u32 DENALI_PHY_78; + volatile u32 DENALI_PHY_79; + volatile u32 DENALI_PHY_80; + volatile u32 DENALI_PHY_81; + volatile u32 DENALI_PHY_82; + volatile u32 DENALI_PHY_83; + volatile u32 DENALI_PHY_84; + volatile u32 DENALI_PHY_85; + volatile u32 DENALI_PHY_86; + volatile u32 DENALI_PHY_87; + volatile u32 DENALI_PHY_88; + volatile u32 DENALI_PHY_89; + volatile u32 DENALI_PHY_90; + volatile u32 DENALI_PHY_91; + volatile u32 DENALI_PHY_92; + volatile u32 DENALI_PHY_93; + volatile u32 DENALI_PHY_94; + volatile u32 DENALI_PHY_95; + volatile u32 DENALI_PHY_96; + volatile u32 DENALI_PHY_97; + volatile u32 DENALI_PHY_98; + volatile u32 DENALI_PHY_99; + volatile u32 DENALI_PHY_100; + volatile u32 DENALI_PHY_101; + volatile u32 DENALI_PHY_102; + volatile u32 DENALI_PHY_103; + volatile u32 DENALI_PHY_104; + volatile u32 DENALI_PHY_105; + volatile u32 DENALI_PHY_106; + volatile u32 DENALI_PHY_107; + volatile u32 DENALI_PHY_108; + volatile u32 DENALI_PHY_109; + volatile u32 DENALI_PHY_110; + volatile u32 DENALI_PHY_111; + volatile u32 DENALI_PHY_112; + volatile u32 DENALI_PHY_113; + volatile u32 DENALI_PHY_114; + volatile u32 DENALI_PHY_115; + volatile u32 DENALI_PHY_116; + volatile u32 DENALI_PHY_117; + volatile u32 DENALI_PHY_118; + volatile u32 DENALI_PHY_119; + volatile u32 DENALI_PHY_120; + volatile u32 DENALI_PHY_121; + volatile u32 DENALI_PHY_122; + volatile u32 DENALI_PHY_123; + volatile u32 DENALI_PHY_124; + volatile u32 DENALI_PHY_125; + volatile u32 DENALI_PHY_126; + volatile u32 DENALI_PHY_127; + volatile u32 DENALI_PHY_128; + volatile u32 DENALI_PHY_129; + volatile u32 DENALI_PHY_130; + volatile u32 DENALI_PHY_131; + volatile u32 DENALI_PHY_132; + volatile u32 DENALI_PHY_133; + volatile u32 DENALI_PHY_134; + volatile u32 DENALI_PHY_135; + volatile u32 DENALI_PHY_136; + volatile char pad__2[0x1DCU]; + volatile u32 DENALI_PHY_256; + volatile u32 DENALI_PHY_257; + volatile u32 DENALI_PHY_258; + volatile u32 DENALI_PHY_259; + volatile u32 DENALI_PHY_260; + volatile u32 DENALI_PHY_261; + volatile u32 DENALI_PHY_262; + volatile u32 DENALI_PHY_263; + volatile u32 DENALI_PHY_264; + volatile u32 DENALI_PHY_265; + volatile u32 DENALI_PHY_266; + volatile u32 DENALI_PHY_267; + volatile u32 DENALI_PHY_268; + volatile u32 DENALI_PHY_269; + volatile u32 DENALI_PHY_270; + volatile u32 DENALI_PHY_271; + volatile u32 DENALI_PHY_272; + volatile u32 DENALI_PHY_273; + volatile u32 DENALI_PHY_274; + volatile u32 DENALI_PHY_275; + volatile u32 DENALI_PHY_276; + volatile u32 DENALI_PHY_277; + volatile u32 DENALI_PHY_278; + volatile u32 DENALI_PHY_279; + volatile u32 DENALI_PHY_280; + volatile u32 DENALI_PHY_281; + volatile u32 DENALI_PHY_282; + volatile u32 DENALI_PHY_283; + volatile u32 DENALI_PHY_284; + volatile u32 DENALI_PHY_285; + volatile u32 DENALI_PHY_286; + volatile u32 DENALI_PHY_287; + volatile u32 DENALI_PHY_288; + volatile u32 DENALI_PHY_289; + volatile u32 DENALI_PHY_290; + volatile u32 DENALI_PHY_291; + volatile u32 DENALI_PHY_292; + volatile u32 DENALI_PHY_293; + volatile u32 DENALI_PHY_294; + volatile u32 DENALI_PHY_295; + volatile u32 DENALI_PHY_296; + volatile u32 DENALI_PHY_297; + volatile u32 DENALI_PHY_298; + volatile u32 DENALI_PHY_299; + volatile u32 DENALI_PHY_300; + volatile u32 DENALI_PHY_301; + volatile u32 DENALI_PHY_302; + volatile u32 DENALI_PHY_303; + volatile u32 DENALI_PHY_304; + volatile u32 DENALI_PHY_305; + volatile u32 DENALI_PHY_306; + volatile u32 DENALI_PHY_307; + volatile u32 DENALI_PHY_308; + volatile u32 DENALI_PHY_309; + volatile u32 DENALI_PHY_310; + volatile u32 DENALI_PHY_311; + volatile u32 DENALI_PHY_312; + volatile u32 DENALI_PHY_313; + volatile u32 DENALI_PHY_314; + volatile u32 DENALI_PHY_315; + volatile u32 DENALI_PHY_316; + volatile u32 DENALI_PHY_317; + volatile u32 DENALI_PHY_318; + volatile u32 DENALI_PHY_319; + volatile u32 DENALI_PHY_320; + volatile u32 DENALI_PHY_321; + volatile u32 DENALI_PHY_322; + volatile u32 DENALI_PHY_323; + volatile u32 DENALI_PHY_324; + volatile u32 DENALI_PHY_325; + volatile u32 DENALI_PHY_326; + volatile u32 DENALI_PHY_327; + volatile u32 DENALI_PHY_328; + volatile u32 DENALI_PHY_329; + volatile u32 DENALI_PHY_330; + volatile u32 DENALI_PHY_331; + volatile u32 DENALI_PHY_332; + volatile u32 DENALI_PHY_333; + volatile u32 DENALI_PHY_334; + volatile u32 DENALI_PHY_335; + volatile u32 DENALI_PHY_336; + volatile u32 DENALI_PHY_337; + volatile u32 DENALI_PHY_338; + volatile u32 DENALI_PHY_339; + volatile u32 DENALI_PHY_340; + volatile u32 DENALI_PHY_341; + volatile u32 DENALI_PHY_342; + volatile u32 DENALI_PHY_343; + volatile u32 DENALI_PHY_344; + volatile u32 DENALI_PHY_345; + volatile u32 DENALI_PHY_346; + volatile u32 DENALI_PHY_347; + volatile u32 DENALI_PHY_348; + volatile u32 DENALI_PHY_349; + volatile u32 DENALI_PHY_350; + volatile u32 DENALI_PHY_351; + volatile u32 DENALI_PHY_352; + volatile u32 DENALI_PHY_353; + volatile u32 DENALI_PHY_354; + volatile u32 DENALI_PHY_355; + volatile u32 DENALI_PHY_356; + volatile u32 DENALI_PHY_357; + volatile u32 DENALI_PHY_358; + volatile u32 DENALI_PHY_359; + volatile u32 DENALI_PHY_360; + volatile u32 DENALI_PHY_361; + volatile u32 DENALI_PHY_362; + volatile u32 DENALI_PHY_363; + volatile u32 DENALI_PHY_364; + volatile u32 DENALI_PHY_365; + volatile u32 DENALI_PHY_366; + volatile u32 DENALI_PHY_367; + volatile u32 DENALI_PHY_368; + volatile u32 DENALI_PHY_369; + volatile u32 DENALI_PHY_370; + volatile u32 DENALI_PHY_371; + volatile u32 DENALI_PHY_372; + volatile u32 DENALI_PHY_373; + volatile u32 DENALI_PHY_374; + volatile u32 DENALI_PHY_375; + volatile u32 DENALI_PHY_376; + volatile u32 DENALI_PHY_377; + volatile u32 DENALI_PHY_378; + volatile u32 DENALI_PHY_379; + volatile u32 DENALI_PHY_380; + volatile u32 DENALI_PHY_381; + volatile u32 DENALI_PHY_382; + volatile u32 DENALI_PHY_383; + volatile u32 DENALI_PHY_384; + volatile u32 DENALI_PHY_385; + volatile u32 DENALI_PHY_386; + volatile u32 DENALI_PHY_387; + volatile u32 DENALI_PHY_388; + volatile u32 DENALI_PHY_389; + volatile u32 DENALI_PHY_390; + volatile u32 DENALI_PHY_391; + volatile u32 DENALI_PHY_392; + volatile char pad__3[0x1DCU]; + volatile u32 DENALI_PHY_512; + volatile u32 DENALI_PHY_513; + volatile u32 DENALI_PHY_514; + volatile u32 DENALI_PHY_515; + volatile u32 DENALI_PHY_516; + volatile u32 DENALI_PHY_517; + volatile u32 DENALI_PHY_518; + volatile u32 DENALI_PHY_519; + volatile u32 DENALI_PHY_520; + volatile u32 DENALI_PHY_521; + volatile u32 DENALI_PHY_522; + volatile u32 DENALI_PHY_523; + volatile u32 DENALI_PHY_524; + volatile u32 DENALI_PHY_525; + volatile u32 DENALI_PHY_526; + volatile u32 DENALI_PHY_527; + volatile u32 DENALI_PHY_528; + volatile u32 DENALI_PHY_529; + volatile u32 DENALI_PHY_530; + volatile u32 DENALI_PHY_531; + volatile u32 DENALI_PHY_532; + volatile u32 DENALI_PHY_533; + volatile u32 DENALI_PHY_534; + volatile u32 DENALI_PHY_535; + volatile u32 DENALI_PHY_536; + volatile u32 DENALI_PHY_537; + volatile u32 DENALI_PHY_538; + volatile u32 DENALI_PHY_539; + volatile u32 DENALI_PHY_540; + volatile u32 DENALI_PHY_541; + volatile u32 DENALI_PHY_542; + volatile u32 DENALI_PHY_543; + volatile u32 DENALI_PHY_544; + volatile u32 DENALI_PHY_545; + volatile u32 DENALI_PHY_546; + volatile u32 DENALI_PHY_547; + volatile u32 DENALI_PHY_548; + volatile u32 DENALI_PHY_549; + volatile u32 DENALI_PHY_550; + volatile u32 DENALI_PHY_551; + volatile u32 DENALI_PHY_552; + volatile u32 DENALI_PHY_553; + volatile u32 DENALI_PHY_554; + volatile u32 DENALI_PHY_555; + volatile u32 DENALI_PHY_556; + volatile u32 DENALI_PHY_557; + volatile u32 DENALI_PHY_558; + volatile u32 DENALI_PHY_559; + volatile u32 DENALI_PHY_560; + volatile u32 DENALI_PHY_561; + volatile u32 DENALI_PHY_562; + volatile u32 DENALI_PHY_563; + volatile u32 DENALI_PHY_564; + volatile u32 DENALI_PHY_565; + volatile u32 DENALI_PHY_566; + volatile u32 DENALI_PHY_567; + volatile u32 DENALI_PHY_568; + volatile u32 DENALI_PHY_569; + volatile u32 DENALI_PHY_570; + volatile u32 DENALI_PHY_571; + volatile u32 DENALI_PHY_572; + volatile u32 DENALI_PHY_573; + volatile u32 DENALI_PHY_574; + volatile u32 DENALI_PHY_575; + volatile u32 DENALI_PHY_576; + volatile u32 DENALI_PHY_577; + volatile u32 DENALI_PHY_578; + volatile u32 DENALI_PHY_579; + volatile u32 DENALI_PHY_580; + volatile u32 DENALI_PHY_581; + volatile u32 DENALI_PHY_582; + volatile u32 DENALI_PHY_583; + volatile u32 DENALI_PHY_584; + volatile u32 DENALI_PHY_585; + volatile u32 DENALI_PHY_586; + volatile u32 DENALI_PHY_587; + volatile u32 DENALI_PHY_588; + volatile u32 DENALI_PHY_589; + volatile u32 DENALI_PHY_590; + volatile u32 DENALI_PHY_591; + volatile u32 DENALI_PHY_592; + volatile u32 DENALI_PHY_593; + volatile u32 DENALI_PHY_594; + volatile u32 DENALI_PHY_595; + volatile u32 DENALI_PHY_596; + volatile u32 DENALI_PHY_597; + volatile u32 DENALI_PHY_598; + volatile u32 DENALI_PHY_599; + volatile u32 DENALI_PHY_600; + volatile u32 DENALI_PHY_601; + volatile u32 DENALI_PHY_602; + volatile u32 DENALI_PHY_603; + volatile u32 DENALI_PHY_604; + volatile u32 DENALI_PHY_605; + volatile u32 DENALI_PHY_606; + volatile u32 DENALI_PHY_607; + volatile u32 DENALI_PHY_608; + volatile u32 DENALI_PHY_609; + volatile u32 DENALI_PHY_610; + volatile u32 DENALI_PHY_611; + volatile u32 DENALI_PHY_612; + volatile u32 DENALI_PHY_613; + volatile u32 DENALI_PHY_614; + volatile u32 DENALI_PHY_615; + volatile u32 DENALI_PHY_616; + volatile u32 DENALI_PHY_617; + volatile u32 DENALI_PHY_618; + volatile u32 DENALI_PHY_619; + volatile u32 DENALI_PHY_620; + volatile u32 DENALI_PHY_621; + volatile u32 DENALI_PHY_622; + volatile u32 DENALI_PHY_623; + volatile u32 DENALI_PHY_624; + volatile u32 DENALI_PHY_625; + volatile u32 DENALI_PHY_626; + volatile u32 DENALI_PHY_627; + volatile u32 DENALI_PHY_628; + volatile u32 DENALI_PHY_629; + volatile u32 DENALI_PHY_630; + volatile u32 DENALI_PHY_631; + volatile u32 DENALI_PHY_632; + volatile u32 DENALI_PHY_633; + volatile u32 DENALI_PHY_634; + volatile u32 DENALI_PHY_635; + volatile u32 DENALI_PHY_636; + volatile u32 DENALI_PHY_637; + volatile u32 DENALI_PHY_638; + volatile u32 DENALI_PHY_639; + volatile u32 DENALI_PHY_640; + volatile u32 DENALI_PHY_641; + volatile u32 DENALI_PHY_642; + volatile u32 DENALI_PHY_643; + volatile u32 DENALI_PHY_644; + volatile u32 DENALI_PHY_645; + volatile u32 DENALI_PHY_646; + volatile u32 DENALI_PHY_647; + volatile u32 DENALI_PHY_648; + volatile char pad__4[0x1DCU]; + volatile u32 DENALI_PHY_768; + volatile u32 DENALI_PHY_769; + volatile u32 DENALI_PHY_770; + volatile u32 DENALI_PHY_771; + volatile u32 DENALI_PHY_772; + volatile u32 DENALI_PHY_773; + volatile u32 DENALI_PHY_774; + volatile u32 DENALI_PHY_775; + volatile u32 DENALI_PHY_776; + volatile u32 DENALI_PHY_777; + volatile u32 DENALI_PHY_778; + volatile u32 DENALI_PHY_779; + volatile u32 DENALI_PHY_780; + volatile u32 DENALI_PHY_781; + volatile u32 DENALI_PHY_782; + volatile u32 DENALI_PHY_783; + volatile u32 DENALI_PHY_784; + volatile u32 DENALI_PHY_785; + volatile u32 DENALI_PHY_786; + volatile u32 DENALI_PHY_787; + volatile u32 DENALI_PHY_788; + volatile u32 DENALI_PHY_789; + volatile u32 DENALI_PHY_790; + volatile u32 DENALI_PHY_791; + volatile u32 DENALI_PHY_792; + volatile u32 DENALI_PHY_793; + volatile u32 DENALI_PHY_794; + volatile u32 DENALI_PHY_795; + volatile u32 DENALI_PHY_796; + volatile u32 DENALI_PHY_797; + volatile u32 DENALI_PHY_798; + volatile u32 DENALI_PHY_799; + volatile u32 DENALI_PHY_800; + volatile u32 DENALI_PHY_801; + volatile u32 DENALI_PHY_802; + volatile u32 DENALI_PHY_803; + volatile u32 DENALI_PHY_804; + volatile u32 DENALI_PHY_805; + volatile u32 DENALI_PHY_806; + volatile u32 DENALI_PHY_807; + volatile u32 DENALI_PHY_808; + volatile u32 DENALI_PHY_809; + volatile u32 DENALI_PHY_810; + volatile u32 DENALI_PHY_811; + volatile u32 DENALI_PHY_812; + volatile u32 DENALI_PHY_813; + volatile u32 DENALI_PHY_814; + volatile u32 DENALI_PHY_815; + volatile u32 DENALI_PHY_816; + volatile u32 DENALI_PHY_817; + volatile u32 DENALI_PHY_818; + volatile u32 DENALI_PHY_819; + volatile u32 DENALI_PHY_820; + volatile u32 DENALI_PHY_821; + volatile u32 DENALI_PHY_822; + volatile u32 DENALI_PHY_823; + volatile u32 DENALI_PHY_824; + volatile u32 DENALI_PHY_825; + volatile u32 DENALI_PHY_826; + volatile u32 DENALI_PHY_827; + volatile u32 DENALI_PHY_828; + volatile u32 DENALI_PHY_829; + volatile u32 DENALI_PHY_830; + volatile u32 DENALI_PHY_831; + volatile u32 DENALI_PHY_832; + volatile u32 DENALI_PHY_833; + volatile u32 DENALI_PHY_834; + volatile u32 DENALI_PHY_835; + volatile u32 DENALI_PHY_836; + volatile u32 DENALI_PHY_837; + volatile u32 DENALI_PHY_838; + volatile u32 DENALI_PHY_839; + volatile u32 DENALI_PHY_840; + volatile u32 DENALI_PHY_841; + volatile u32 DENALI_PHY_842; + volatile u32 DENALI_PHY_843; + volatile u32 DENALI_PHY_844; + volatile u32 DENALI_PHY_845; + volatile u32 DENALI_PHY_846; + volatile u32 DENALI_PHY_847; + volatile u32 DENALI_PHY_848; + volatile u32 DENALI_PHY_849; + volatile u32 DENALI_PHY_850; + volatile u32 DENALI_PHY_851; + volatile u32 DENALI_PHY_852; + volatile u32 DENALI_PHY_853; + volatile u32 DENALI_PHY_854; + volatile u32 DENALI_PHY_855; + volatile u32 DENALI_PHY_856; + volatile u32 DENALI_PHY_857; + volatile u32 DENALI_PHY_858; + volatile u32 DENALI_PHY_859; + volatile u32 DENALI_PHY_860; + volatile u32 DENALI_PHY_861; + volatile u32 DENALI_PHY_862; + volatile u32 DENALI_PHY_863; + volatile u32 DENALI_PHY_864; + volatile u32 DENALI_PHY_865; + volatile u32 DENALI_PHY_866; + volatile u32 DENALI_PHY_867; + volatile u32 DENALI_PHY_868; + volatile u32 DENALI_PHY_869; + volatile u32 DENALI_PHY_870; + volatile u32 DENALI_PHY_871; + volatile u32 DENALI_PHY_872; + volatile u32 DENALI_PHY_873; + volatile u32 DENALI_PHY_874; + volatile u32 DENALI_PHY_875; + volatile u32 DENALI_PHY_876; + volatile u32 DENALI_PHY_877; + volatile u32 DENALI_PHY_878; + volatile u32 DENALI_PHY_879; + volatile u32 DENALI_PHY_880; + volatile u32 DENALI_PHY_881; + volatile u32 DENALI_PHY_882; + volatile u32 DENALI_PHY_883; + volatile u32 DENALI_PHY_884; + volatile u32 DENALI_PHY_885; + volatile u32 DENALI_PHY_886; + volatile u32 DENALI_PHY_887; + volatile u32 DENALI_PHY_888; + volatile u32 DENALI_PHY_889; + volatile u32 DENALI_PHY_890; + volatile u32 DENALI_PHY_891; + volatile u32 DENALI_PHY_892; + volatile u32 DENALI_PHY_893; + volatile u32 DENALI_PHY_894; + volatile u32 DENALI_PHY_895; + volatile u32 DENALI_PHY_896; + volatile u32 DENALI_PHY_897; + volatile u32 DENALI_PHY_898; + volatile u32 DENALI_PHY_899; + volatile u32 DENALI_PHY_900; + volatile u32 DENALI_PHY_901; + volatile u32 DENALI_PHY_902; + volatile u32 DENALI_PHY_903; + volatile u32 DENALI_PHY_904; + volatile char pad__5[0x1DCU]; + volatile u32 DENALI_PHY_1024; + volatile u32 DENALI_PHY_1025; + volatile u32 DENALI_PHY_1026; + volatile u32 DENALI_PHY_1027; + volatile u32 DENALI_PHY_1028; + volatile u32 DENALI_PHY_1029; + volatile u32 DENALI_PHY_1030; + volatile u32 DENALI_PHY_1031; + volatile u32 DENALI_PHY_1032; + volatile u32 DENALI_PHY_1033; + volatile u32 DENALI_PHY_1034; + volatile u32 DENALI_PHY_1035; + volatile u32 DENALI_PHY_1036; + volatile u32 DENALI_PHY_1037; + volatile u32 DENALI_PHY_1038; + volatile u32 DENALI_PHY_1039; + volatile u32 DENALI_PHY_1040; + volatile u32 DENALI_PHY_1041; + volatile u32 DENALI_PHY_1042; + volatile u32 DENALI_PHY_1043; + volatile u32 DENALI_PHY_1044; + volatile u32 DENALI_PHY_1045; + volatile u32 DENALI_PHY_1046; + volatile u32 DENALI_PHY_1047; + volatile u32 DENALI_PHY_1048; + volatile u32 DENALI_PHY_1049; + volatile u32 DENALI_PHY_1050; + volatile u32 DENALI_PHY_1051; + volatile u32 DENALI_PHY_1052; + volatile u32 DENALI_PHY_1053; + volatile u32 DENALI_PHY_1054; + volatile u32 DENALI_PHY_1055; + volatile u32 DENALI_PHY_1056; + volatile u32 DENALI_PHY_1057; + volatile u32 DENALI_PHY_1058; + volatile u32 DENALI_PHY_1059; + volatile u32 DENALI_PHY_1060; + volatile u32 DENALI_PHY_1061; + volatile u32 DENALI_PHY_1062; + volatile u32 DENALI_PHY_1063; + volatile u32 DENALI_PHY_1064; + volatile u32 DENALI_PHY_1065; + volatile u32 DENALI_PHY_1066; + volatile u32 DENALI_PHY_1067; + volatile u32 DENALI_PHY_1068; + volatile u32 DENALI_PHY_1069; + volatile u32 DENALI_PHY_1070; + volatile u32 DENALI_PHY_1071; + volatile u32 DENALI_PHY_1072; + volatile char pad__6[0x33CU]; + volatile u32 DENALI_PHY_1280; + volatile u32 DENALI_PHY_1281; + volatile u32 DENALI_PHY_1282; + volatile u32 DENALI_PHY_1283; + volatile u32 DENALI_PHY_1284; + volatile u32 DENALI_PHY_1285; + volatile u32 DENALI_PHY_1286; + volatile u32 DENALI_PHY_1287; + volatile u32 DENALI_PHY_1288; + volatile u32 DENALI_PHY_1289; + volatile u32 DENALI_PHY_1290; + volatile u32 DENALI_PHY_1291; + volatile u32 DENALI_PHY_1292; + volatile u32 DENALI_PHY_1293; + volatile u32 DENALI_PHY_1294; + volatile u32 DENALI_PHY_1295; + volatile u32 DENALI_PHY_1296; + volatile u32 DENALI_PHY_1297; + volatile u32 DENALI_PHY_1298; + volatile u32 DENALI_PHY_1299; + volatile u32 DENALI_PHY_1300; + volatile u32 DENALI_PHY_1301; + volatile u32 DENALI_PHY_1302; + volatile u32 DENALI_PHY_1303; + volatile u32 DENALI_PHY_1304; + volatile u32 DENALI_PHY_1305; + volatile u32 DENALI_PHY_1306; + volatile u32 DENALI_PHY_1307; + volatile u32 DENALI_PHY_1308; + volatile u32 DENALI_PHY_1309; + volatile u32 DENALI_PHY_1310; + volatile u32 DENALI_PHY_1311; + volatile u32 DENALI_PHY_1312; + volatile u32 DENALI_PHY_1313; + volatile u32 DENALI_PHY_1314; + volatile u32 DENALI_PHY_1315; + volatile u32 DENALI_PHY_1316; + volatile u32 DENALI_PHY_1317; + volatile u32 DENALI_PHY_1318; + volatile u32 DENALI_PHY_1319; + volatile u32 DENALI_PHY_1320; + volatile u32 DENALI_PHY_1321; + volatile u32 DENALI_PHY_1322; + volatile u32 DENALI_PHY_1323; + volatile u32 DENALI_PHY_1324; + volatile u32 DENALI_PHY_1325; + volatile u32 DENALI_PHY_1326; + volatile u32 DENALI_PHY_1327; + volatile u32 DENALI_PHY_1328; + volatile char pad__7[0x33CU]; + volatile u32 DENALI_PHY_1536; + volatile u32 DENALI_PHY_1537; + volatile u32 DENALI_PHY_1538; + volatile u32 DENALI_PHY_1539; + volatile u32 DENALI_PHY_1540; + volatile u32 DENALI_PHY_1541; + volatile u32 DENALI_PHY_1542; + volatile u32 DENALI_PHY_1543; + volatile u32 DENALI_PHY_1544; + volatile u32 DENALI_PHY_1545; + volatile u32 DENALI_PHY_1546; + volatile u32 DENALI_PHY_1547; + volatile u32 DENALI_PHY_1548; + volatile u32 DENALI_PHY_1549; + volatile u32 DENALI_PHY_1550; + volatile u32 DENALI_PHY_1551; + volatile u32 DENALI_PHY_1552; + volatile u32 DENALI_PHY_1553; + volatile u32 DENALI_PHY_1554; + volatile u32 DENALI_PHY_1555; + volatile u32 DENALI_PHY_1556; + volatile u32 DENALI_PHY_1557; + volatile u32 DENALI_PHY_1558; + volatile u32 DENALI_PHY_1559; + volatile u32 DENALI_PHY_1560; + volatile u32 DENALI_PHY_1561; + volatile u32 DENALI_PHY_1562; + volatile u32 DENALI_PHY_1563; + volatile u32 DENALI_PHY_1564; + volatile u32 DENALI_PHY_1565; + volatile u32 DENALI_PHY_1566; + volatile u32 DENALI_PHY_1567; + volatile u32 DENALI_PHY_1568; + volatile u32 DENALI_PHY_1569; + volatile u32 DENALI_PHY_1570; + volatile u32 DENALI_PHY_1571; + volatile u32 DENALI_PHY_1572; + volatile u32 DENALI_PHY_1573; + volatile u32 DENALI_PHY_1574; + volatile u32 DENALI_PHY_1575; + volatile u32 DENALI_PHY_1576; + volatile u32 DENALI_PHY_1577; + volatile u32 DENALI_PHY_1578; + volatile u32 DENALI_PHY_1579; + volatile u32 DENALI_PHY_1580; + volatile u32 DENALI_PHY_1581; + volatile u32 DENALI_PHY_1582; + volatile u32 DENALI_PHY_1583; + volatile u32 DENALI_PHY_1584; + volatile char pad__8[0x33CU]; + volatile u32 DENALI_PHY_1792; + volatile u32 DENALI_PHY_1793; + volatile u32 DENALI_PHY_1794; + volatile u32 DENALI_PHY_1795; + volatile u32 DENALI_PHY_1796; + volatile u32 DENALI_PHY_1797; + volatile u32 DENALI_PHY_1798; + volatile u32 DENALI_PHY_1799; + volatile u32 DENALI_PHY_1800; + volatile u32 DENALI_PHY_1801; + volatile u32 DENALI_PHY_1802; + volatile u32 DENALI_PHY_1803; + volatile u32 DENALI_PHY_1804; + volatile u32 DENALI_PHY_1805; + volatile u32 DENALI_PHY_1806; + volatile u32 DENALI_PHY_1807; + volatile u32 DENALI_PHY_1808; + volatile u32 DENALI_PHY_1809; + volatile u32 DENALI_PHY_1810; + volatile u32 DENALI_PHY_1811; + volatile u32 DENALI_PHY_1812; + volatile u32 DENALI_PHY_1813; + volatile u32 DENALI_PHY_1814; + volatile u32 DENALI_PHY_1815; + volatile u32 DENALI_PHY_1816; + volatile u32 DENALI_PHY_1817; + volatile u32 DENALI_PHY_1818; + volatile u32 DENALI_PHY_1819; + volatile u32 DENALI_PHY_1820; + volatile u32 DENALI_PHY_1821; + volatile u32 DENALI_PHY_1822; + volatile u32 DENALI_PHY_1823; + volatile u32 DENALI_PHY_1824; + volatile u32 DENALI_PHY_1825; + volatile u32 DENALI_PHY_1826; + volatile u32 DENALI_PHY_1827; + volatile u32 DENALI_PHY_1828; + volatile u32 DENALI_PHY_1829; + volatile u32 DENALI_PHY_1830; + volatile u32 DENALI_PHY_1831; + volatile u32 DENALI_PHY_1832; + volatile u32 DENALI_PHY_1833; + volatile u32 DENALI_PHY_1834; + volatile u32 DENALI_PHY_1835; + volatile u32 DENALI_PHY_1836; + volatile u32 DENALI_PHY_1837; + volatile u32 DENALI_PHY_1838; + volatile u32 DENALI_PHY_1839; + volatile u32 DENALI_PHY_1840; + volatile u32 DENALI_PHY_1841; + volatile u32 DENALI_PHY_1842; + volatile u32 DENALI_PHY_1843; + volatile u32 DENALI_PHY_1844; + volatile u32 DENALI_PHY_1845; + volatile u32 DENALI_PHY_1846; + volatile u32 DENALI_PHY_1847; + volatile u32 DENALI_PHY_1848; + volatile u32 DENALI_PHY_1849; + volatile u32 DENALI_PHY_1850; + volatile u32 DENALI_PHY_1851; + volatile u32 DENALI_PHY_1852; + volatile u32 DENALI_PHY_1853; + volatile u32 DENALI_PHY_1854; + volatile u32 DENALI_PHY_1855; + volatile u32 DENALI_PHY_1856; + volatile u32 DENALI_PHY_1857; + volatile u32 DENALI_PHY_1858; + volatile u32 DENALI_PHY_1859; + volatile u32 DENALI_PHY_1860; + volatile u32 DENALI_PHY_1861; + volatile u32 DENALI_PHY_1862; + volatile u32 DENALI_PHY_1863; + volatile u32 DENALI_PHY_1864; + volatile u32 DENALI_PHY_1865; + volatile u32 DENALI_PHY_1866; + volatile u32 DENALI_PHY_1867; + volatile u32 DENALI_PHY_1868; + volatile u32 DENALI_PHY_1869; + volatile u32 DENALI_PHY_1870; + volatile u32 DENALI_PHY_1871; + volatile u32 DENALI_PHY_1872; + volatile u32 DENALI_PHY_1873; + volatile u32 DENALI_PHY_1874; + volatile u32 DENALI_PHY_1875; + volatile u32 DENALI_PHY_1876; + volatile u32 DENALI_PHY_1877; + volatile u32 DENALI_PHY_1878; + volatile u32 DENALI_PHY_1879; + volatile u32 DENALI_PHY_1880; + volatile u32 DENALI_PHY_1881; + volatile u32 DENALI_PHY_1882; + volatile u32 DENALI_PHY_1883; + volatile u32 DENALI_PHY_1884; + volatile u32 DENALI_PHY_1885; + volatile u32 DENALI_PHY_1886; + volatile u32 DENALI_PHY_1887; + volatile u32 DENALI_PHY_1888; + volatile u32 DENALI_PHY_1889; + volatile u32 DENALI_PHY_1890; + volatile u32 DENALI_PHY_1891; + volatile u32 DENALI_PHY_1892; + volatile u32 DENALI_PHY_1893; + volatile u32 DENALI_PHY_1894; + volatile u32 DENALI_PHY_1895; + volatile u32 DENALI_PHY_1896; + volatile u32 DENALI_PHY_1897; + volatile u32 DENALI_PHY_1898; + volatile u32 DENALI_PHY_1899; + volatile u32 DENALI_PHY_1900; + volatile u32 DENALI_PHY_1901; + volatile u32 DENALI_PHY_1902; + volatile u32 DENALI_PHY_1903; + volatile u32 DENALI_PHY_1904; + volatile u32 DENALI_PHY_1905; + volatile u32 DENALI_PHY_1906; + volatile u32 DENALI_PHY_1907; + volatile u32 DENALI_PHY_1908; + volatile u32 DENALI_PHY_1909; + volatile u32 DENALI_PHY_1910; + volatile u32 DENALI_PHY_1911; + volatile u32 DENALI_PHY_1912; + volatile u32 DENALI_PHY_1913; + volatile u32 DENALI_PHY_1914; + volatile u32 DENALI_PHY_1915; + volatile u32 DENALI_PHY_1916; + volatile u32 DENALI_PHY_1917; + volatile u32 DENALI_PHY_1918; + volatile u32 DENALI_PHY_1919; + volatile u32 DENALI_PHY_1920; + volatile u32 DENALI_PHY_1921; + volatile u32 DENALI_PHY_1922; + volatile u32 DENALI_PHY_1923; +} lpddr4_ctlregs; + +#endif /* REG_LPDDR4_CTL_REGS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h new file mode 100644 index 0000000000..013f1f0343 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_0_macros.h @@ -0,0 +1,2292 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_ + +#define LPDDR4__DENALI_PHY_0_READ_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH 7U +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1_READ_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 + +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0 + +#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0 + +#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0 + +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0 + +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0 + +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0 + +#define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_0__FLD LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0 + +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0 + +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0 + +#define LPDDR4__DENALI_PHY_9_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_9 +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_9__PHY_GATE_DELAY_COMP_DISABLE_0 + +#define LPDDR4__DENALI_PHY_10_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_10 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_CONTROL_0 + +#define LPDDR4__DENALI_PHY_11_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_11 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_11__PHY_AUTO_TIMING_MARGIN_OBS_0 + +#define LPDDR4__DENALI_PHY_12_READ_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0_WIDTH 9U +#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_DQ_IDLE_0 + +#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0_WOSET 0U +#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_12__PHY_PDA_MODE_EN_0 + +#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_12 +#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_START_0 + +#define LPDDR4__DENALI_PHY_13_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_13__PHY_PRBS_PATTERN_MASK_0 + +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_ENABLE_0 + +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_13 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_14_READ_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_14__PHY_VREF_INITIAL_STEPSIZE_0 + +#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_14__PHY_VREF_TRAIN_OBS_0 + +#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_14 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_15_READ_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_ERROR_DELAY_SELECT_0 + +#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_15 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_15__SC_PHY_SNAP_OBS_REGS_0 + +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_15 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_16_READ_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_16__PHY_LPDDR_0_WOSET 0U +#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_16 +#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_16__PHY_LPDDR_0 + +#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_16 +#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_16__PHY_MEM_CLASS_0 + +#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_16 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_SMPL2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_17 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_17__ON_FLY_GATE_ADJUST_EN_0 + +#define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_18 +#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_18__PHY_GATE_TRACKING_OBS_0 + +#define LPDDR4__DENALI_PHY_19_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_19 +#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_19__PHY_DFI40_POLARITY_0 + +#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_19 +#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_19__PHY_LP4_PST_AMBLE_0 + +#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_20 +#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT8_0 + +#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_21 +#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT9_0 + +#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_22 +#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT10_0 + +#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_23 +#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT11_0 + +#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_24 +#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT12_0 + +#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_25 +#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT13_0 + +#define LPDDR4__DENALI_PHY_26_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_26 +#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT14_0 + +#define LPDDR4__DENALI_PHY_27_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_27 +#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDLVL_PATT15_0 + +#define LPDDR4__DENALI_PHY_28_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_28__PHY_SLAVE_LOOP_CNT_UPDATE_0 + +#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_28__PHY_SW_FIFO_PTR_RST_DISABLE_0 + +#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_MASTER_DLY_LOCK_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_29_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_RDDQS_DQ_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WR_ENC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WR_SHIFT_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_29 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_29__PHY_FIFO_PTR_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_30_READ_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_30__PHY_LVL_DEBUG_MODE_0 + +#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_30 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_30__SC_PHY_LVL_DEBUG_CONT_0 + +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_ALGO_0 + +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_30 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_31_READ_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_WRLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_31__PHY_DQ_MASK_0 + +#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_GTLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_GTLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_32_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_CAPTURE_CNT_0 + +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_OP_MODE_0 + +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_32 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_33_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_MASK_0 + +#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_MASK 0x03FFFF00U +#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH 18U +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_33 +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_33__PHY_RDLVL_DATA_SWIZZLE_0 + +#define LPDDR4__DENALI_PHY_34_READ_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 + +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_BURST_CNT_0 + +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_34 +#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_PATT_0 + +#define LPDDR4__DENALI_PHY_35_READ_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 + +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_UPDT_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_35 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQDM_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_36_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_36 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_PERIODIC_OBS_SELECT_0 + +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_36 +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DQ_SLV_DELTA_0 + +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_36 +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DM_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_36 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_36__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 + +#define LPDDR4__DENALI_PHY_37_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_37 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_37__PHY_WDQLVL_DATADM_MASK_0 + +#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_38 +#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT0_0 + +#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_39 +#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT1_0 + +#define LPDDR4__DENALI_PHY_40_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_40 +#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT2_0 + +#define LPDDR4__DENALI_PHY_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_41 +#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT3_0 + +#define LPDDR4__DENALI_PHY_42_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_42__PHY_USER_PATT4_0 + +#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_42 +#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_MULT_TRAIN_0 + +#define LPDDR4__DENALI_PHY_43_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_43 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_44_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_44 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MIN_0 + +#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_44 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_44__PHY_NTP_PERIOD_THRESHOLD_MAX_0 + +#define LPDDR4__DENALI_PHY_45_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_45__PHY_CALVL_VREF_DRIVING_SLICE_0 + +#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_45 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_45__SC_PHY_MANUAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_45 +#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_FIFO_PTR_OBS_0 + +#define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_46 +#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_47_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_LPBK_ERROR_COUNT_OBS_0 + +#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_47 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_MASTER_DLY_LOCK_OBS_0 + +#define LPDDR4__DENALI_PHY_48_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQ_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_48__PHY_MEAS_DLY_STEP_VALUE_0 + +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_49_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_50_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_50 +#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WR_SHIFT_OBS_0 + +#define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_51 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_52_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0_WIDTH 21U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_52 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_53_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_53 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_53 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 + +#define LPDDR4__DENALI_PHY_54_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_54 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_WRLVL_ERROR_OBS_0 + +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_54 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_HARD0_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_55_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_55 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_GTLVL_HARD1_DELAY_OBS_0 + +#define LPDDR4__DENALI_PHY_56_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_56 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_GTLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_57_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_57 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_57 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_58_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_58 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0 + +#define LPDDR4__DENALI_PHY_59_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_59 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_RDLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_60_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_60 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_LE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_60 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_DQDM_TE_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_61 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_STATUS_OBS_0 + +#define LPDDR4__DENALI_PHY_62_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_62 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_62__PHY_WDQLVL_PERIODIC_OBS_0 + +#define LPDDR4__DENALI_PHY_63_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_63 +#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MODE_0 + +#define LPDDR4__DENALI_PHY_64_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_64 +#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_MASK_0 + +#define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_65 +#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_OBS_0 + +#define LPDDR4__DENALI_PHY_66_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_66 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TEST_MSTR_DLY_OBS_0 + +#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_67__PHY_DDL_TRACK_UPD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_67__PHY_LP4_WDQS_OE_EXTEND_0 + +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67 +#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0 + +#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0 + +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68 +#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0 + +#define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0 + +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69 +#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0 + +#define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0 + +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70 +#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0 + +#define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71 +#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0 + +#define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72 +#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0 + +#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0 + +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73 +#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0 + +#define LPDDR4__DENALI_PHY_74_READ_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_74__PHY_PAD_RX_BIAS_EN_0 + +#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_STATIC_TOG_DISABLE_0 + +#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_74 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DATA_DC_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_75_READ_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_CAL_TIMEOUT_0 + +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_WEIGHT_0 + +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_START_0 + +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__REG DENALI_PHY_75 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DATA_DC_ADJUST_SAMPLE_CNT_0 + +#define LPDDR4__DENALI_PHY_76_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_ADJUST_DIRECT_0 + +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_POLARITY_0 + +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_76 +#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_76__PHY_DATA_DC_CAL_START_0 + +#define LPDDR4__DENALI_PHY_77_READ_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_SW_RANK_0 + +#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_77__PHY_FDBK_PWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_SLV_DLY_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_77 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_RDPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_78_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_78__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_78 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_78__PHY_SLICE_PWR_RDC_DISABLE_0 + +#define LPDDR4__DENALI_PHY_79_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQ_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_79 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_79__PHY_DQS_TSEL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_80_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_80__PHY_DQS_TSEL_SELECT_0 + +#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_TWO_CYC_PREAMBLE_0 + +#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_80 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_80__PHY_VREF_INITIAL_START_POINT_0 + +#define LPDDR4__DENALI_PHY_81_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_81__PHY_VREF_INITIAL_STOP_POINT_0 + +#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_81__PHY_VREF_TRAINING_CTRL_0 + +#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_81__PHY_NTP_TRAIN_EN_0 + +#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_81 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_81__PHY_NTP_WDQ_STEP_SIZE_0 + +#define LPDDR4__DENALI_PHY_82_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_START_0 + +#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_82 +#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_82__PHY_NTP_WDQ_STOP_0 + +#define LPDDR4__DENALI_PHY_83_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_83__PHY_NTP_WDQ_BIT_EN_0 + +#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_83__PHY_WDQLVL_DVW_MIN_0 + +#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_83 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_83__PHY_SW_WDQLVL_DVW_MIN_EN_0 + +#define LPDDR4__DENALI_PHY_84_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_84__PHY_WDQLVL_PER_START_OFFSET_0 + +#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_84__PHY_FAST_LVL_EN_0 + +#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_84__PHY_PAD_TX_DCD_0 + +#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_84 +#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_84__PHY_PAD_RX_DCD_0_0 + +#define LPDDR4__DENALI_PHY_85_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_1_0 + +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_2_0 + +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_3_0 + +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_85 +#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_85__PHY_PAD_RX_DCD_4_0 + +#define LPDDR4__DENALI_PHY_86_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_5_0 + +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_6_0 + +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_RX_DCD_7_0 + +#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_86 +#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_86__PHY_PAD_DM_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_87_READ_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_DQS_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_FDBK_RX_DCD_0 + +#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 7U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_87 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_87__PHY_PAD_DSLICE_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_88_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_88__PHY_RDDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_88 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_88__PHY_RDDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_89_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_89__PHY_RDDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_89 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_89__PHY_RDDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_90_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_90__PHY_RDDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_90 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_90__PHY_RDDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_91_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_91 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_92_READ_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_92__PHY_RDDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_92__PHY_RX_PCLK_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_92 +#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_RX_CAL_ALL_DLY_0 + +#define LPDDR4__DENALI_PHY_93_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_93 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_93__PHY_DATA_DC_CAL_CLK_SEL_0 + +#define LPDDR4__DENALI_PHY_94_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQ_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_94 +#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_94__PHY_DQS_OE_TIMING_0 + +#define LPDDR4__DENALI_PHY_95_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_IO_PAD_DELAY_TIMING_0 + +#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_OE_RD_TIMING_0 + +#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_95 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_95__PHY_DQS_TSEL_WR_TIMING_0 + +#define LPDDR4__DENALI_PHY_96_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_96__PHY_VREF_SETTING_TIME_0 + +#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_96 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_96__PHY_PAD_VREF_CTRL_DQ_0 + +#define LPDDR4__DENALI_PHY_97_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_97__PHY_PER_CS_TRAINING_EN_0 + +#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_97__PHY_DQ_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_97__PHY_DQS_IE_TIMING_0 + +#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_97 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDATA_EN_IE_DLY_0 + +#define LPDDR4__DENALI_PHY_98_READ_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_98__PHY_IE_MODE_0 + +#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0_WIDTH 2U +#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_98__PHY_DBI_MODE_0 + +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0_WOSET 0U +#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_IE_ON_0 + +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_98 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_99_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_TSEL_DLY_0 + +#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDDATA_EN_OE_DLY_0 + +#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_99 +#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_99__PHY_SW_MASTER_MODE_0 + +#define LPDDR4__DENALI_PHY_100_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_START_0 + +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_STEP_0 + +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_100 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_100__PHY_MASTER_DELAY_WAIT_0 + +#define LPDDR4__DENALI_PHY_101_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MASTER_DELAY_HALF_MEASURE_0 + +#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_101__PHY_RPTR_UPDATE_0 + +#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_101 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRLVL_DLY_FINE_STEP_0 + +#define LPDDR4__DENALI_PHY_102_READ_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_102__PHY_WRLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_102__PHY_GTLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_102 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_102__PHY_GTLVL_RESP_WAIT_CNT_0 + +#define LPDDR4__DENALI_PHY_103_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_GTLVL_BACK_STEP_0 + +#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_103 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_GTLVL_FINAL_STEP_0 + +#define LPDDR4__DENALI_PHY_104_READ_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_QTR_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_104 +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_104__PHY_WDQLVL_DM_SEARCH_RANGE_0 + +#define LPDDR4__DENALI_PHY_105_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_105__PHY_TOGGLE_PRE_SUPPORT_0 + +#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_105 +#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_RDLVL_DLY_STEP_0 + +#define LPDDR4__DENALI_PHY_106_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_106 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_106__PHY_RDLVL_MAX_EDGE_0 + +#define LPDDR4__DENALI_PHY_107_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_DISABLE_0 + +#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_107__PHY_WRPATH_GATE_TIMING_0 + +#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_107 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_107__PHY_DATA_DC_INIT_DISABLE_0 + +#define LPDDR4__DENALI_PHY_108_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__REG DENALI_PHY_108 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_108 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 + +#define LPDDR4__DENALI_PHY_109_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WRLVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_WDQLVL_ENABLE_0 + +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_109 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_109__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 + +#define LPDDR4__DENALI_PHY_110_READ_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_110__PHY_WDQ_OSC_DELTA_0 + +#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 7U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_MEAS_DLY_STEP_ENABLE_0 + +#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_110 +#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDATA_EN_DLY_0 + +#define LPDDR4__DENALI_PHY_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_111 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_111__PHY_DQ_DM_SWIZZLE0_0 + +#define LPDDR4__DENALI_PHY_112_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_112 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_112__PHY_DQ_DM_SWIZZLE1_0 + +#define LPDDR4__DENALI_PHY_113_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_113 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_CLK_WRDQ1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_114_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_114 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_114 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_CLK_WRDQ3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_115_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_115 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ4_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_115 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_CLK_WRDQ5_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ6_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_116 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ7_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDM_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_117 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQS_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_118_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_118__PHY_WRLVL_THRESHOLD_ADJUST_0 + +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_119 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_120 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_121_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_126 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_127 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_127 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_GATE_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_LATENCY_ADJUST_0 + +#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_128__PHY_WRITE_PATH_LAT_ADD_0 + +#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_128 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_128__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_129_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_129 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_129__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 + +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_129 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_129__PHY_WRLVL_EARLY_FORCE_ZERO_0 + +#define LPDDR4__DENALI_PHY_130_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_130 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_130__PHY_GTLVL_RDDQS_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_130 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_130__PHY_GTLVL_LAT_ADJ_START_0 + +#define LPDDR4__DENALI_PHY_131_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_131__PHY_WDQLVL_DQDM_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_131__PHY_NTP_WRLAT_START_0 + +#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_131 +#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_131__PHY_NTP_PASS_0 + +#define LPDDR4__DENALI_PHY_132_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_132 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_132__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 + +#define LPDDR4__DENALI_PHY_133_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_133_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQS_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ0_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ1_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_133 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_133__PHY_DATA_DC_DQ2_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_134_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_134_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ3_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ4_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ5_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_134 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_134__PHY_DATA_DC_DQ6_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_135_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_135_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__REG DENALI_PHY_135 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DQ7_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__REG DENALI_PHY_135 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_135__PHY_DATA_DC_DM_CLK_ADJUST_0 + +#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_135 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_135__PHY_DSLICE_PAD_BOOSTPN_SETTING_0 + +#define LPDDR4__DENALI_PHY_136_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_136_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_136__PHY_DSLICE_PAD_RX_CTLE_SETTING_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_136__PHY_DQ_FFE_0 + +#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_136 +#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_136__PHY_DQS_FFE_0 + +#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h new file mode 100644 index 0000000000..c1071120f1 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_1_macros.h @@ -0,0 +1,2292 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_ + +#define LPDDR4__DENALI_PHY_256_READ_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH 7U +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_257_READ_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 + +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1 + +#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1 + +#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1 + +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1 + +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1 + +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1 + +#define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_1__FLD LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1 + +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1 + +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1 + +#define LPDDR4__DENALI_PHY_265_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_265 +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_265__PHY_GATE_DELAY_COMP_DISABLE_1 + +#define LPDDR4__DENALI_PHY_266_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_266 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_CONTROL_1 + +#define LPDDR4__DENALI_PHY_267_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_267 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_267__PHY_AUTO_TIMING_MARGIN_OBS_1 + +#define LPDDR4__DENALI_PHY_268_READ_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1_WIDTH 9U +#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_DQ_IDLE_1 + +#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1_WOSET 0U +#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_268__PHY_PDA_MODE_EN_1 + +#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_268 +#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_START_1 + +#define LPDDR4__DENALI_PHY_269_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_269__PHY_PRBS_PATTERN_MASK_1 + +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_ENABLE_1 + +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_269 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_270_READ_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_270__PHY_VREF_INITIAL_STEPSIZE_1 + +#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_270__PHY_VREF_TRAIN_OBS_1 + +#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_270 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_271_READ_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_ERROR_DELAY_SELECT_1 + +#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_271 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_271__SC_PHY_SNAP_OBS_REGS_1 + +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_271 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_272_READ_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_272__PHY_LPDDR_1_WOSET 0U +#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_272 +#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_272__PHY_LPDDR_1 + +#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_272 +#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_272__PHY_MEM_CLASS_1 + +#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_272 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_SMPL2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_273 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_273__ON_FLY_GATE_ADJUST_EN_1 + +#define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_274 +#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_274__PHY_GATE_TRACKING_OBS_1 + +#define LPDDR4__DENALI_PHY_275_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_275 +#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_275__PHY_DFI40_POLARITY_1 + +#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_275 +#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_275__PHY_LP4_PST_AMBLE_1 + +#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_276 +#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT8_1 + +#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_277 +#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT9_1 + +#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_278 +#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT10_1 + +#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_279 +#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT11_1 + +#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_280 +#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT12_1 + +#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_281 +#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT13_1 + +#define LPDDR4__DENALI_PHY_282_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_282 +#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT14_1 + +#define LPDDR4__DENALI_PHY_283_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_283 +#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDLVL_PATT15_1 + +#define LPDDR4__DENALI_PHY_284_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_284__PHY_SLAVE_LOOP_CNT_UPDATE_1 + +#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_284__PHY_SW_FIFO_PTR_RST_DISABLE_1 + +#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_MASTER_DLY_LOCK_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_285_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_RDDQS_DQ_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WR_ENC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WR_SHIFT_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_285 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_285__PHY_FIFO_PTR_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_286_READ_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_286__PHY_LVL_DEBUG_MODE_1 + +#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_286 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_286__SC_PHY_LVL_DEBUG_CONT_1 + +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_ALGO_1 + +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_286 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_287_READ_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_WRLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_287__PHY_DQ_MASK_1 + +#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_GTLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_GTLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_288_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_CAPTURE_CNT_1 + +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_OP_MODE_1 + +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_288 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_289_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_MASK_1 + +#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_MASK 0x03FFFF00U +#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH 18U +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_289 +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_289__PHY_RDLVL_DATA_SWIZZLE_1 + +#define LPDDR4__DENALI_PHY_290_READ_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1 + +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_BURST_CNT_1 + +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_290 +#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_PATT_1 + +#define LPDDR4__DENALI_PHY_291_READ_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 + +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_UPDT_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_291 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQDM_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_292_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_292 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_PERIODIC_OBS_SELECT_1 + +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_292 +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DQ_SLV_DELTA_1 + +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_292 +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DM_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_292 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_292__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1 + +#define LPDDR4__DENALI_PHY_293_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_293 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_293__PHY_WDQLVL_DATADM_MASK_1 + +#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_294 +#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT0_1 + +#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_295 +#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT1_1 + +#define LPDDR4__DENALI_PHY_296_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_296 +#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT2_1 + +#define LPDDR4__DENALI_PHY_297_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_297 +#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT3_1 + +#define LPDDR4__DENALI_PHY_298_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_298__PHY_USER_PATT4_1 + +#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_298 +#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_MULT_TRAIN_1 + +#define LPDDR4__DENALI_PHY_299_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_299 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_300_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_300 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MIN_1 + +#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_300 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_300__PHY_NTP_PERIOD_THRESHOLD_MAX_1 + +#define LPDDR4__DENALI_PHY_301_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_301__PHY_CALVL_VREF_DRIVING_SLICE_1 + +#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_301 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_301__SC_PHY_MANUAL_CLEAR_1 + +#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_301 +#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_FIFO_PTR_OBS_1 + +#define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_302 +#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_RESULT_OBS_1 + +#define LPDDR4__DENALI_PHY_303_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_LPBK_ERROR_COUNT_OBS_1 + +#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_303 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_MASTER_DLY_LOCK_OBS_1 + +#define LPDDR4__DENALI_PHY_304_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQ_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_304__PHY_MEAS_DLY_STEP_VALUE_1 + +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_305_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_306_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_306 +#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WR_SHIFT_OBS_1 + +#define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_307 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_308_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1_WIDTH 21U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_308 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_309_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_309 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_309 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 + +#define LPDDR4__DENALI_PHY_310_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_310 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_WRLVL_ERROR_OBS_1 + +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_310 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_HARD0_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_311_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_311 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_GTLVL_HARD1_DELAY_OBS_1 + +#define LPDDR4__DENALI_PHY_312_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_312 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_GTLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_313_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_313 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_313 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_314_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_314 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1 + +#define LPDDR4__DENALI_PHY_315_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_315 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_RDLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_316_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_316 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_LE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_316 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_DQDM_TE_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_317 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_STATUS_OBS_1 + +#define LPDDR4__DENALI_PHY_318_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_318 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_318__PHY_WDQLVL_PERIODIC_OBS_1 + +#define LPDDR4__DENALI_PHY_319_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_319 +#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MODE_1 + +#define LPDDR4__DENALI_PHY_320_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_320 +#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_MASK_1 + +#define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_321 +#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_OBS_1 + +#define LPDDR4__DENALI_PHY_322_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_322 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TEST_MSTR_DLY_OBS_1 + +#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_323__PHY_DDL_TRACK_UPD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_323__PHY_LP4_WDQS_OE_EXTEND_1 + +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323 +#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1 + +#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1 + +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324 +#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1 + +#define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1 + +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325 +#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1 + +#define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1 + +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326 +#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1 + +#define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327 +#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1 + +#define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328 +#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1 + +#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1 + +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329 +#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1 + +#define LPDDR4__DENALI_PHY_330_READ_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_330__PHY_PAD_RX_BIAS_EN_1 + +#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_STATIC_TOG_DISABLE_1 + +#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_330 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DATA_DC_CAL_SAMPLE_WAIT_1 + +#define LPDDR4__DENALI_PHY_331_READ_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_CAL_TIMEOUT_1 + +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_WEIGHT_1 + +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_START_1 + +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__REG DENALI_PHY_331 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DATA_DC_ADJUST_SAMPLE_CNT_1 + +#define LPDDR4__DENALI_PHY_332_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_ADJUST_DIRECT_1 + +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_POLARITY_1 + +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_332 +#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_332__PHY_DATA_DC_CAL_START_1 + +#define LPDDR4__DENALI_PHY_333_READ_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_SW_RANK_1 + +#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_333__PHY_FDBK_PWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_SLV_DLY_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_333 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_RDPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_334_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_334__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_334 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_334__PHY_SLICE_PWR_RDC_DISABLE_1 + +#define LPDDR4__DENALI_PHY_335_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQ_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_335 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_335__PHY_DQS_TSEL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_336_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_336__PHY_DQS_TSEL_SELECT_1 + +#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_TWO_CYC_PREAMBLE_1 + +#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_336 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_336__PHY_VREF_INITIAL_START_POINT_1 + +#define LPDDR4__DENALI_PHY_337_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_337__PHY_VREF_INITIAL_STOP_POINT_1 + +#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_337__PHY_VREF_TRAINING_CTRL_1 + +#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_337__PHY_NTP_TRAIN_EN_1 + +#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_337 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_337__PHY_NTP_WDQ_STEP_SIZE_1 + +#define LPDDR4__DENALI_PHY_338_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_START_1 + +#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_338 +#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_338__PHY_NTP_WDQ_STOP_1 + +#define LPDDR4__DENALI_PHY_339_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_339__PHY_NTP_WDQ_BIT_EN_1 + +#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_339__PHY_WDQLVL_DVW_MIN_1 + +#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_339 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_339__PHY_SW_WDQLVL_DVW_MIN_EN_1 + +#define LPDDR4__DENALI_PHY_340_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_340__PHY_WDQLVL_PER_START_OFFSET_1 + +#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_340__PHY_FAST_LVL_EN_1 + +#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_340__PHY_PAD_TX_DCD_1 + +#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_340 +#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_340__PHY_PAD_RX_DCD_0_1 + +#define LPDDR4__DENALI_PHY_341_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_1_1 + +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_2_1 + +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_3_1 + +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_341 +#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_341__PHY_PAD_RX_DCD_4_1 + +#define LPDDR4__DENALI_PHY_342_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_5_1 + +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_6_1 + +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_RX_DCD_7_1 + +#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_342 +#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_342__PHY_PAD_DM_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_343_READ_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_DQS_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_FDBK_RX_DCD_1 + +#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 7U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_343 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_343__PHY_PAD_DSLICE_IO_CFG_1 + +#define LPDDR4__DENALI_PHY_344_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_344__PHY_RDDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_344 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_344__PHY_RDDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_345_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_345__PHY_RDDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_345 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_345__PHY_RDDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_346_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_346__PHY_RDDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_346 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_346__PHY_RDDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_347_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_347 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_348_READ_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_348__PHY_RDDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_348__PHY_RX_PCLK_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_348 +#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_RX_CAL_ALL_DLY_1 + +#define LPDDR4__DENALI_PHY_349_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_349 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_349__PHY_DATA_DC_CAL_CLK_SEL_1 + +#define LPDDR4__DENALI_PHY_350_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQ_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_350 +#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_350__PHY_DQS_OE_TIMING_1 + +#define LPDDR4__DENALI_PHY_351_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_IO_PAD_DELAY_TIMING_1 + +#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_OE_RD_TIMING_1 + +#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_351 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_351__PHY_DQS_TSEL_WR_TIMING_1 + +#define LPDDR4__DENALI_PHY_352_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_352__PHY_VREF_SETTING_TIME_1 + +#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_352 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_352__PHY_PAD_VREF_CTRL_DQ_1 + +#define LPDDR4__DENALI_PHY_353_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_353__PHY_PER_CS_TRAINING_EN_1 + +#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_353__PHY_DQ_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_353__PHY_DQS_IE_TIMING_1 + +#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_353 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDATA_EN_IE_DLY_1 + +#define LPDDR4__DENALI_PHY_354_READ_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_354__PHY_IE_MODE_1 + +#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1_WIDTH 2U +#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_354__PHY_DBI_MODE_1 + +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1_WOSET 0U +#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_IE_ON_1 + +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_354 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_355_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_TSEL_DLY_1 + +#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDDATA_EN_OE_DLY_1 + +#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_355 +#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_355__PHY_SW_MASTER_MODE_1 + +#define LPDDR4__DENALI_PHY_356_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_START_1 + +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_STEP_1 + +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_356 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_356__PHY_MASTER_DELAY_WAIT_1 + +#define LPDDR4__DENALI_PHY_357_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MASTER_DELAY_HALF_MEASURE_1 + +#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_357__PHY_RPTR_UPDATE_1 + +#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_357 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRLVL_DLY_FINE_STEP_1 + +#define LPDDR4__DENALI_PHY_358_READ_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_358__PHY_WRLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_358__PHY_GTLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_358 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_358__PHY_GTLVL_RESP_WAIT_CNT_1 + +#define LPDDR4__DENALI_PHY_359_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_GTLVL_BACK_STEP_1 + +#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_359 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_GTLVL_FINAL_STEP_1 + +#define LPDDR4__DENALI_PHY_360_READ_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_QTR_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_360 +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_360__PHY_WDQLVL_DM_SEARCH_RANGE_1 + +#define LPDDR4__DENALI_PHY_361_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_361__PHY_TOGGLE_PRE_SUPPORT_1 + +#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_361 +#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_RDLVL_DLY_STEP_1 + +#define LPDDR4__DENALI_PHY_362_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_362 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_362__PHY_RDLVL_MAX_EDGE_1 + +#define LPDDR4__DENALI_PHY_363_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_DISABLE_1 + +#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_363__PHY_WRPATH_GATE_TIMING_1 + +#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_363 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_363__PHY_DATA_DC_INIT_DISABLE_1 + +#define LPDDR4__DENALI_PHY_364_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__REG DENALI_PHY_364 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_364 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 + +#define LPDDR4__DENALI_PHY_365_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WRLVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_WDQLVL_ENABLE_1 + +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_SE_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_365 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_365__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1 + +#define LPDDR4__DENALI_PHY_366_READ_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_366__PHY_WDQ_OSC_DELTA_1 + +#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 7U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_MEAS_DLY_STEP_ENABLE_1 + +#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_366 +#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDATA_EN_DLY_1 + +#define LPDDR4__DENALI_PHY_367_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_367 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_367__PHY_DQ_DM_SWIZZLE0_1 + +#define LPDDR4__DENALI_PHY_368_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_368 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_368__PHY_DQ_DM_SWIZZLE1_1 + +#define LPDDR4__DENALI_PHY_369_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_369 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_CLK_WRDQ1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_370_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_370 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_370 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_CLK_WRDQ3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_371_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_371 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ4_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_371 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_CLK_WRDQ5_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ6_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_372 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ7_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDM_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_373 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQS_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_374_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_374__PHY_WRLVL_THRESHOLD_ADJUST_1 + +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_375 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_376 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_377_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_382 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_383 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_383 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_GATE_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_LATENCY_ADJUST_1 + +#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_384__PHY_WRITE_PATH_LAT_ADD_1 + +#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_384 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_384__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_385_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_385 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_385__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 + +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_385 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_385__PHY_WRLVL_EARLY_FORCE_ZERO_1 + +#define LPDDR4__DENALI_PHY_386_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_386 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_386__PHY_GTLVL_RDDQS_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_386 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_386__PHY_GTLVL_LAT_ADJ_START_1 + +#define LPDDR4__DENALI_PHY_387_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_387__PHY_WDQLVL_DQDM_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_387__PHY_NTP_WRLAT_START_1 + +#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WIDTH 1U +#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WOCLR 0U +#define LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_387 +#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_387__PHY_NTP_PASS_1 + +#define LPDDR4__DENALI_PHY_388_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_388 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_388__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 + +#define LPDDR4__DENALI_PHY_389_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_389_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQS_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ0_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ1_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_389 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_389__PHY_DATA_DC_DQ2_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_390_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_390_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ3_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ4_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ5_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_390 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_390__PHY_DATA_DC_DQ6_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_391_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_391_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__REG DENALI_PHY_391 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DQ7_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__REG DENALI_PHY_391 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_391__PHY_DATA_DC_DM_CLK_ADJUST_1 + +#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_391 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_391__PHY_DSLICE_PAD_BOOSTPN_SETTING_1 + +#define LPDDR4__DENALI_PHY_392_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_392_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_392__PHY_DSLICE_PAD_RX_CTLE_SETTING_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_392__PHY_DQ_FFE_1 + +#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_392 +#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_392__PHY_DQS_FFE_1 + +#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h new file mode 100644 index 0000000000..b8fb80e08e --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_2_macros.h @@ -0,0 +1,2292 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_ + +#define LPDDR4__DENALI_PHY_512_READ_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2_WIDTH 7U +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_512__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_2 + +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_512 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_513_READ_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_IO_PAD_DELAY_TIMING_BYPASS_2 + +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2 + +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2 + +#define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_514__PHY_BYPASS_TWO_CYC_PREAMBLE_2 + +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2 + +#define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2 + +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2 + +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2 + +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2 + +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2 + +#define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_2__FLD LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2 + +#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2 + +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2 + +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2 + +#define LPDDR4__DENALI_PHY_521_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_2__REG DENALI_PHY_521 +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_2__FLD LPDDR4__DENALI_PHY_521__PHY_GATE_DELAY_COMP_DISABLE_2 + +#define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_522 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_CONTROL_2 + +#define LPDDR4__DENALI_PHY_523_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_523 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_523__PHY_AUTO_TIMING_MARGIN_OBS_2 + +#define LPDDR4__DENALI_PHY_524_READ_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2_WIDTH 9U +#define LPDDR4__PHY_DQ_IDLE_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_DQ_IDLE_2__FLD LPDDR4__DENALI_PHY_524__PHY_DQ_IDLE_2 + +#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2_WOSET 0U +#define LPDDR4__PHY_PDA_MODE_EN_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_PDA_MODE_EN_2__FLD LPDDR4__DENALI_PHY_524__PHY_PDA_MODE_EN_2 + +#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_524 +#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_524__PHY_PRBS_PATTERN_START_2 + +#define LPDDR4__DENALI_PHY_525_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_525__PHY_PRBS_PATTERN_MASK_2 + +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_ENABLE_2 + +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__REG DENALI_PHY_525 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_525__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2 + +#define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_526__PHY_VREF_INITIAL_STEPSIZE_2 + +#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_526__PHY_VREF_TRAIN_OBS_2 + +#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_526 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__REG DENALI_PHY_527 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_ERROR_DELAY_SELECT_2 + +#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_527 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_527__SC_PHY_SNAP_OBS_REGS_2 + +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_527 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_528_READ_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_528__PHY_LPDDR_2_WOSET 0U +#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_528 +#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_528__PHY_LPDDR_2 + +#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_528 +#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_528__PHY_MEM_CLASS_2 + +#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__REG DENALI_PHY_528 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_SMPL2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_529 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_529__ON_FLY_GATE_ADJUST_EN_2 + +#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_530 +#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_530__PHY_GATE_TRACKING_OBS_2 + +#define LPDDR4__DENALI_PHY_531_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_531 +#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_531__PHY_DFI40_POLARITY_2 + +#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_531 +#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_531__PHY_LP4_PST_AMBLE_2 + +#define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_532 +#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT8_2 + +#define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_533 +#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT9_2 + +#define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_534 +#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT10_2 + +#define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_535 +#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT11_2 + +#define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_536 +#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT12_2 + +#define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_537 +#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT13_2 + +#define LPDDR4__DENALI_PHY_538_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_538 +#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDLVL_PATT14_2 + +#define LPDDR4__DENALI_PHY_539_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_539 +#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDLVL_PATT15_2 + +#define LPDDR4__DENALI_PHY_540_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_540__PHY_SLAVE_LOOP_CNT_UPDATE_2 + +#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_2__FLD LPDDR4__DENALI_PHY_540__PHY_SW_FIFO_PTR_RST_DISABLE_2 + +#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_540__PHY_MASTER_DLY_LOCK_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_540 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_540__PHY_RDDQ_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_541_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_RDDQS_DQ_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WR_ENC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WR_SHIFT_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_541 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_541__PHY_FIFO_PTR_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_542__PHY_LVL_DEBUG_MODE_2 + +#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_542 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_542__SC_PHY_LVL_DEBUG_CONT_2 + +#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_542__PHY_WRLVL_ALGO_2 + +#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_542 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_WRLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_543_READ_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_WRLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_543__PHY_DQ_MASK_2 + +#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_GTLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_543 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_GTLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_544_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_CAPTURE_CNT_2 + +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_OP_MODE_2 + +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_544 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_545_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_MASK_2 + +#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_MASK 0x03FFFF00U +#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2_WIDTH 18U +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_2__REG DENALI_PHY_545 +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_2__FLD LPDDR4__DENALI_PHY_545__PHY_RDLVL_DATA_SWIZZLE_2 + +#define LPDDR4__DENALI_PHY_546_READ_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2 + +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_BURST_CNT_2 + +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_546 +#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_546__PHY_WDQLVL_PATT_2 + +#define LPDDR4__DENALI_PHY_547_READ_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__REG DENALI_PHY_547 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2 + +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_547 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_UPDT_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__REG DENALI_PHY_547 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DQDM_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_548_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__REG DENALI_PHY_548 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_PERIODIC_OBS_SELECT_2 + +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_2__REG DENALI_PHY_548 +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DQ_SLV_DELTA_2 + +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_2__REG DENALI_PHY_548 +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_548__PHY_WDQLVL_DM_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_548 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_548__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2 + +#define LPDDR4__DENALI_PHY_549_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_549 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_549__PHY_WDQLVL_DATADM_MASK_2 + +#define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_550 +#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT0_2 + +#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_551 +#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT1_2 + +#define LPDDR4__DENALI_PHY_552_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_552 +#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT2_2 + +#define LPDDR4__DENALI_PHY_553_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_553 +#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_553__PHY_USER_PATT3_2 + +#define LPDDR4__DENALI_PHY_554_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_554 +#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_554__PHY_USER_PATT4_2 + +#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_554 +#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_MULT_TRAIN_2 + +#define LPDDR4__DENALI_PHY_555_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__REG DENALI_PHY_555 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_555__PHY_NTP_EARLY_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_555 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_555__PHY_NTP_PERIOD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_556_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_556_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__REG DENALI_PHY_556 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_2__FLD LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MIN_2 + +#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_556 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_556__PHY_NTP_PERIOD_THRESHOLD_MAX_2 + +#define LPDDR4__DENALI_PHY_557_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__REG DENALI_PHY_557 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_557__PHY_CALVL_VREF_DRIVING_SLICE_2 + +#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_557 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_557__SC_PHY_MANUAL_CLEAR_2 + +#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_557 +#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_FIFO_PTR_OBS_2 + +#define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_558 +#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_LPBK_RESULT_OBS_2 + +#define LPDDR4__DENALI_PHY_559_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_LPBK_ERROR_COUNT_OBS_2 + +#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_559 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_MASTER_DLY_LOCK_OBS_2 + +#define LPDDR4__DENALI_PHY_560_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_560_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQ_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_560__PHY_MEAS_DLY_STEP_VALUE_2 + +#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_560 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_561_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_561 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_562_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_562 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_562 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_562 +#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WR_SHIFT_OBS_2 + +#define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_563 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD0_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_563 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_WRLVL_HARD1_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_564_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2_WIDTH 21U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_564 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_565_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_565 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_565 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2 + +#define LPDDR4__DENALI_PHY_566_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_566 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_WRLVL_ERROR_OBS_2 + +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_566 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_HARD0_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_567_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_567 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_GTLVL_HARD1_DELAY_OBS_2 + +#define LPDDR4__DENALI_PHY_568_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_568 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_GTLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_569_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_569_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__REG DENALI_PHY_569 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_569 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_570_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_570_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_570 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2 + +#define LPDDR4__DENALI_PHY_571_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_571_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_571 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_RDLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_572_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_572_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__REG DENALI_PHY_572 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_LE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_572 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_DQDM_TE_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_573 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_STATUS_OBS_2 + +#define LPDDR4__DENALI_PHY_574_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_574_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_574 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_574__PHY_WDQLVL_PERIODIC_OBS_2 + +#define LPDDR4__DENALI_PHY_575_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_575 +#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MODE_2 + +#define LPDDR4__DENALI_PHY_576_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_576_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_576 +#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_MASK_2 + +#define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_577 +#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_OBS_2 + +#define LPDDR4__DENALI_PHY_578_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_578_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_578 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TEST_MSTR_DLY_OBS_2 + +#define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_579__PHY_DDL_TRACK_UPD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_579__PHY_LP4_WDQS_OE_EXTEND_2 + +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579 +#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2 + +#define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580 +#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2 + +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580 +#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2 + +#define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581 +#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2 + +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581 +#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2 + +#define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582 +#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2 + +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582 +#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2 + +#define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583 +#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2 + +#define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584 +#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2 + +#define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585 +#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2 + +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585 +#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2 + +#define LPDDR4__DENALI_PHY_586_READ_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_586_WRITE_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_586__PHY_PAD_RX_BIAS_EN_2 + +#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_586__PHY_STATIC_TOG_DISABLE_2 + +#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_586 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_586__PHY_DATA_DC_CAL_SAMPLE_WAIT_2 + +#define LPDDR4__DENALI_PHY_587_READ_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_587_WRITE_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_CAL_TIMEOUT_2 + +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_WEIGHT_2 + +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_START_2 + +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__REG DENALI_PHY_587 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2__FLD LPDDR4__DENALI_PHY_587__PHY_DATA_DC_ADJUST_SAMPLE_CNT_2 + +#define LPDDR4__DENALI_PHY_588_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_ADJUST_DIRECT_2 + +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_POLARITY_2 + +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_588 +#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_588__PHY_DATA_DC_CAL_START_2 + +#define LPDDR4__DENALI_PHY_589_READ_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_SW_RANK_2 + +#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_589__PHY_FDBK_PWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_SLV_DLY_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__REG DENALI_PHY_589 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_RDPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_590_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_590__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_590 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_590__PHY_SLICE_PWR_RDC_DISABLE_2 + +#define LPDDR4__DENALI_PHY_591_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQ_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_591 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_591__PHY_DQS_TSEL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_592_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_592__PHY_DQS_TSEL_SELECT_2 + +#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_TWO_CYC_PREAMBLE_2 + +#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_592 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_592__PHY_VREF_INITIAL_START_POINT_2 + +#define LPDDR4__DENALI_PHY_593_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_593_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_593__PHY_VREF_INITIAL_STOP_POINT_2 + +#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_593__PHY_VREF_TRAINING_CTRL_2 + +#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_593__PHY_NTP_TRAIN_EN_2 + +#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_593 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_593__PHY_NTP_WDQ_STEP_SIZE_2 + +#define LPDDR4__DENALI_PHY_594_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_594 +#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_START_2 + +#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_594 +#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_594__PHY_NTP_WDQ_STOP_2 + +#define LPDDR4__DENALI_PHY_595_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_595__PHY_NTP_WDQ_BIT_EN_2 + +#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_595__PHY_WDQLVL_DVW_MIN_2 + +#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_595 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_595__PHY_SW_WDQLVL_DVW_MIN_EN_2 + +#define LPDDR4__DENALI_PHY_596_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_596__PHY_WDQLVL_PER_START_OFFSET_2 + +#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_596__PHY_FAST_LVL_EN_2 + +#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_596__PHY_PAD_TX_DCD_2 + +#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_596 +#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_596__PHY_PAD_RX_DCD_0_2 + +#define LPDDR4__DENALI_PHY_597_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_1_2 + +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_2_2 + +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_3_2 + +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_597 +#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_597__PHY_PAD_RX_DCD_4_2 + +#define LPDDR4__DENALI_PHY_598_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_598_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_5_2 + +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_6_2 + +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_RX_DCD_7_2 + +#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_598 +#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_598__PHY_PAD_DM_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_599_READ_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_DQS_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_FDBK_RX_DCD_2 + +#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 7U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_599 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_599__PHY_PAD_DSLICE_IO_CFG_2 + +#define LPDDR4__DENALI_PHY_600_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_600__PHY_RDDQ0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_600 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_600__PHY_RDDQ1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_601_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_601__PHY_RDDQ2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_601 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_601__PHY_RDDQ3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_602_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_602__PHY_RDDQ4_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_602 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_602__PHY_RDDQ5_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_603_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_603__PHY_RDDQ6_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_603 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_603__PHY_RDDQ7_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_604_READ_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_604__PHY_RDDM_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_604__PHY_RX_PCLK_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RX_CAL_ALL_DLY_2__REG DENALI_PHY_604 +#define LPDDR4__PHY_RX_CAL_ALL_DLY_2__FLD LPDDR4__DENALI_PHY_604__PHY_RX_CAL_ALL_DLY_2 + +#define LPDDR4__DENALI_PHY_605_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_605 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_605__PHY_DATA_DC_CAL_CLK_SEL_2 + +#define LPDDR4__DENALI_PHY_606_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_606_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_OE_TIMING_2 + +#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQ_TSEL_WR_TIMING_2 + +#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_606 +#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_606__PHY_DQS_OE_TIMING_2 + +#define LPDDR4__DENALI_PHY_607_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_607_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_IO_PAD_DELAY_TIMING_2 + +#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_OE_RD_TIMING_2 + +#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_607 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_607__PHY_DQS_TSEL_WR_TIMING_2 + +#define LPDDR4__DENALI_PHY_608_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_608 +#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_608__PHY_VREF_SETTING_TIME_2 + +#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_608 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_608__PHY_PAD_VREF_CTRL_DQ_2 + +#define LPDDR4__DENALI_PHY_609_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_609__PHY_PER_CS_TRAINING_EN_2 + +#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_609__PHY_DQ_IE_TIMING_2 + +#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_609__PHY_DQS_IE_TIMING_2 + +#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_609 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDATA_EN_IE_DLY_2 + +#define LPDDR4__DENALI_PHY_610_READ_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_610_WRITE_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_610__PHY_IE_MODE_2 + +#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2_WIDTH 2U +#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_610__PHY_DBI_MODE_2 + +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2_WOSET 0U +#define LPDDR4__PHY_WDQLVL_IE_ON_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_WDQLVL_IE_ON_2__FLD LPDDR4__DENALI_PHY_610__PHY_WDQLVL_IE_ON_2 + +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_2__REG DENALI_PHY_610 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_610__PHY_WDQLVL_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_611_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_611_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_TSEL_DLY_2 + +#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_611__PHY_RDDATA_EN_OE_DLY_2 + +#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_611 +#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_611__PHY_SW_MASTER_MODE_2 + +#define LPDDR4__DENALI_PHY_612_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_612_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_START_2 + +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_STEP_2 + +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_612 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_612__PHY_MASTER_DELAY_WAIT_2 + +#define LPDDR4__DENALI_PHY_613_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_613__PHY_MASTER_DELAY_HALF_MEASURE_2 + +#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_613__PHY_RPTR_UPDATE_2 + +#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__REG DENALI_PHY_613 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_2__FLD LPDDR4__DENALI_PHY_613__PHY_WRLVL_DLY_FINE_STEP_2 + +#define LPDDR4__DENALI_PHY_614_READ_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_614__PHY_WRLVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_614__PHY_GTLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_614 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_614__PHY_GTLVL_RESP_WAIT_CNT_2 + +#define LPDDR4__DENALI_PHY_615_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_GTLVL_BACK_STEP_2 + +#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_615 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_GTLVL_FINAL_STEP_2 + +#define LPDDR4__DENALI_PHY_616_READ_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_616_WRITE_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_QTR_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_2__REG DENALI_PHY_616 +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_2__FLD LPDDR4__DENALI_PHY_616__PHY_WDQLVL_DM_SEARCH_RANGE_2 + +#define LPDDR4__DENALI_PHY_617_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_617__PHY_TOGGLE_PRE_SUPPORT_2 + +#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_617 +#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_RDLVL_DLY_STEP_2 + +#define LPDDR4__DENALI_PHY_618_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_618 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_618__PHY_RDLVL_MAX_EDGE_2 + +#define LPDDR4__DENALI_PHY_619_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_DISABLE_2 + +#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_619__PHY_WRPATH_GATE_TIMING_2 + +#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_619 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_619__PHY_DATA_DC_INIT_DISABLE_2 + +#define LPDDR4__DENALI_PHY_620_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__REG DENALI_PHY_620 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_620 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_620__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 + +#define LPDDR4__DENALI_PHY_621_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_621_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WRLVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_WDQLVL_ENABLE_2 + +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_SE_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_621 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_621__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2 + +#define LPDDR4__DENALI_PHY_622_READ_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_622__PHY_WDQ_OSC_DELTA_2 + +#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2_WIDTH 7U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_MEAS_DLY_STEP_ENABLE_2 + +#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_622 +#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_622__PHY_RDDATA_EN_DLY_2 + +#define LPDDR4__DENALI_PHY_623_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_623_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_623 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_623__PHY_DQ_DM_SWIZZLE0_2 + +#define LPDDR4__DENALI_PHY_624_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_624_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_624 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_624__PHY_DQ_DM_SWIZZLE1_2 + +#define LPDDR4__DENALI_PHY_625_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_625 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_625__PHY_CLK_WRDQ1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_626_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_626_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__REG DENALI_PHY_626 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_626 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_626__PHY_CLK_WRDQ3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_627_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__REG DENALI_PHY_627 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ4_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_627 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_627__PHY_CLK_WRDQ5_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__REG DENALI_PHY_628 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ6_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_628 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ7_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_629_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__REG DENALI_PHY_629 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDM_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_629 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQS_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_630_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__REG DENALI_PHY_630 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_2__FLD LPDDR4__DENALI_PHY_630__PHY_WRLVL_THRESHOLD_ADJUST_2 + +#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_630 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_631_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__REG DENALI_PHY_631 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_631 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__REG DENALI_PHY_632 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_632 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_633_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__REG DENALI_PHY_633 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__REG DENALI_PHY_634 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__REG DENALI_PHY_635 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__REG DENALI_PHY_636 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__REG DENALI_PHY_637 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__REG DENALI_PHY_638 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__REG DENALI_PHY_639 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_639 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_GATE_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_LATENCY_ADJUST_2 + +#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_640__PHY_WRITE_PATH_LAT_ADD_2 + +#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_640 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_640__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_641_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__REG DENALI_PHY_641 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_641__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 + +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_641 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_641__PHY_WRLVL_EARLY_FORCE_ZERO_2 + +#define LPDDR4__DENALI_PHY_642_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__REG DENALI_PHY_642 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_642__PHY_GTLVL_RDDQS_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_642 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_642__PHY_GTLVL_LAT_ADJ_START_2 + +#define LPDDR4__DENALI_PHY_643_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_643__PHY_WDQLVL_DQDM_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_643__PHY_NTP_WRLAT_START_2 + +#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WIDTH 1U +#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WOCLR 0U +#define LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_643 +#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_643__PHY_NTP_PASS_2 + +#define LPDDR4__DENALI_PHY_644_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_644 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_644__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 + +#define LPDDR4__DENALI_PHY_645_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_645_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQS_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ0_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ1_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_645 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_645__PHY_DATA_DC_DQ2_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_646_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_646_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ3_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ4_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ5_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_646 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_646__PHY_DATA_DC_DQ6_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_647_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_647_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__REG DENALI_PHY_647 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DQ7_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__REG DENALI_PHY_647 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_647__PHY_DATA_DC_DM_CLK_ADJUST_2 + +#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_647 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_647__PHY_DSLICE_PAD_BOOSTPN_SETTING_2 + +#define LPDDR4__DENALI_PHY_648_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_648_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_648__PHY_DSLICE_PAD_RX_CTLE_SETTING_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_648__PHY_DQ_FFE_2 + +#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_648 +#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_648__PHY_DQS_FFE_2 + +#endif /* REG_LPDDR4_DATA_SLICE_2_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h new file mode 100644 index 0000000000..29bdc46e94 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_data_slice_3_macros.h @@ -0,0 +1,2292 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_ +#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_ + +#define LPDDR4__DENALI_PHY_768_READ_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x07FF7F07U +#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_3 + +#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3_WIDTH 7U +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_768__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_3 + +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_768 +#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_769_READ_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x0703FF0FU +#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_IO_PAD_DELAY_TIMING_BYPASS_3 + +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3 + +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3 + +#define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3_WIDTH 2U +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_770__PHY_BYPASS_TWO_CYC_PREAMBLE_3 + +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3_WOSET 0U +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770 +#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3 + +#define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3 + +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771 +#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3 + +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772 +#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U +#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U +#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3 + +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U +#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3 + +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773 +#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3 + +#define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_PER_CS_TRAINING_INDEX_3__FLD LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_WIDTH 4U +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3_WIDTH 5U +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775 +#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3 + +#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U +#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3 + +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U +#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3 + +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3_WOSET 0U +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776 +#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3 + +#define LPDDR4__DENALI_PHY_777_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_3__REG DENALI_PHY_777 +#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_3__FLD LPDDR4__DENALI_PHY_777__PHY_GATE_DELAY_COMP_DISABLE_3 + +#define LPDDR4__DENALI_PHY_778_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH 32U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_778 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_CONTROL_3 + +#define LPDDR4__DENALI_PHY_779_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH 28U +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_779 +#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_779__PHY_AUTO_TIMING_MARGIN_OBS_3 + +#define LPDDR4__DENALI_PHY_780_READ_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x7F0101FFU +#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3_WIDTH 9U +#define LPDDR4__PHY_DQ_IDLE_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_DQ_IDLE_3__FLD LPDDR4__DENALI_PHY_780__PHY_DQ_IDLE_3 + +#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3_WOSET 0U +#define LPDDR4__PHY_PDA_MODE_EN_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_PDA_MODE_EN_3__FLD LPDDR4__DENALI_PHY_780__PHY_PDA_MODE_EN_3 + +#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3_WIDTH 7U +#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_780 +#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_780__PHY_PRBS_PATTERN_START_3 + +#define LPDDR4__DENALI_PHY_781_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U +#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_781__PHY_PRBS_PATTERN_MASK_3 + +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_ENABLE_3 + +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__REG DENALI_PHY_781 +#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_781__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3 + +#define LPDDR4__DENALI_PHY_782_READ_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x03FF7F3FU +#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3_WIDTH 6U +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_782__PHY_VREF_INITIAL_STEPSIZE_3 + +#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3_WIDTH 7U +#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_782__PHY_VREF_TRAIN_OBS_3 + +#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__REG DENALI_PHY_782 +#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_783_READ_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x01FF000FU +#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__REG DENALI_PHY_783 +#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_ERROR_DELAY_SELECT_3 + +#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_783 +#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_783__SC_PHY_SNAP_OBS_REGS_3 + +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_783 +#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_784_READ_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0x01FF0701U +#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_784__PHY_LPDDR_3_WOSET 0U +#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_784 +#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_784__PHY_LPDDR_3 + +#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3_WIDTH 3U +#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_784 +#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_784__PHY_MEM_CLASS_3 + +#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH 9U +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__REG DENALI_PHY_784 +#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_SMPL2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_785 +#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_785__ON_FLY_GATE_ADJUST_EN_3 + +#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3_WIDTH 32U +#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_786 +#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_786__PHY_GATE_TRACKING_OBS_3 + +#define LPDDR4__DENALI_PHY_787_READ_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0x00000301U +#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3_WOSET 0U +#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_787 +#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_787__PHY_DFI40_POLARITY_3 + +#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3_WIDTH 2U +#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_787 +#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_787__PHY_LP4_PST_AMBLE_3 + +#define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_788 +#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT8_3 + +#define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_789 +#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT9_3 + +#define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_790 +#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT10_3 + +#define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_791 +#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT11_3 + +#define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_792 +#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT12_3 + +#define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_793 +#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT13_3 + +#define LPDDR4__DENALI_PHY_794_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_794 +#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDLVL_PATT14_3 + +#define LPDDR4__DENALI_PHY_795_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_795 +#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDLVL_PATT15_3 + +#define LPDDR4__DENALI_PHY_796_READ_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0x070F0107U +#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH 3U +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_3__FLD LPDDR4__DENALI_PHY_796__PHY_SLAVE_LOOP_CNT_UPDATE_3 + +#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_3__FLD LPDDR4__DENALI_PHY_796__PHY_SW_FIFO_PTR_RST_DISABLE_3 + +#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_796__PHY_MASTER_DLY_LOCK_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3_WIDTH 3U +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_796 +#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_796__PHY_RDDQ_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_797_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_RDDQS_DQ_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WR_ENC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WR_SHIFT_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_797 +#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_797__PHY_FIFO_PTR_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_798_READ_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x3F030001U +#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3_WOSET 0U +#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_798__PHY_LVL_DEBUG_MODE_3 + +#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_798 +#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_798__SC_PHY_LVL_DEBUG_CONT_3 + +#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3_WIDTH 2U +#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_798__PHY_WRLVL_ALGO_3 + +#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_798 +#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_WRLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_799_READ_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x0F3FFF0FU +#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_WRLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3_WIDTH 8U +#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_799__PHY_DQ_MASK_3 + +#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_GTLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_799 +#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_GTLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_800_READ_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x1F030F3FU +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_CAPTURE_CNT_3 + +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3_WIDTH 2U +#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_OP_MODE_3 + +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_WIDTH 5U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_800 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_801_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3_WIDTH 8U +#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_MASK_3 + +#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_MASK 0x03FFFF00U +#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3_WIDTH 18U +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_3__REG DENALI_PHY_801 +#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_3__FLD LPDDR4__DENALI_PHY_801__PHY_RDLVL_DATA_SWIZZLE_3 + +#define LPDDR4__DENALI_PHY_802_READ_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x00073FFFU +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3 + +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_BURST_CNT_3 + +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3_WIDTH 3U +#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_802 +#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_802__PHY_WDQLVL_PATT_3 + +#define LPDDR4__DENALI_PHY_803_READ_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x0F0F07FFU +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__REG DENALI_PHY_803 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3 + +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_803 +#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_UPDT_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__REG DENALI_PHY_803 +#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DQDM_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_804_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__REG DENALI_PHY_804 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_PERIODIC_OBS_SELECT_3 + +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_3__REG DENALI_PHY_804 +#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DQ_SLV_DELTA_3 + +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_3__REG DENALI_PHY_804 +#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_804__PHY_WDQLVL_DM_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_WOSET 0U +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_804 +#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_804__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3 + +#define LPDDR4__DENALI_PHY_805_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_805 +#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_805__PHY_WDQLVL_DATADM_MASK_3 + +#define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_806 +#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT0_3 + +#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_807 +#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT1_3 + +#define LPDDR4__DENALI_PHY_808_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_808 +#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT2_3 + +#define LPDDR4__DENALI_PHY_809_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3_WIDTH 32U +#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_809 +#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_809__PHY_USER_PATT3_3 + +#define LPDDR4__DENALI_PHY_810_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3_WIDTH 16U +#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_810 +#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_810__PHY_USER_PATT4_3 + +#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3_WOSET 0U +#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_810 +#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_MULT_TRAIN_3 + +#define LPDDR4__DENALI_PHY_811_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__REG DENALI_PHY_811 +#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_811__PHY_NTP_EARLY_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_811 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_811__PHY_NTP_PERIOD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_812_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_812_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__REG DENALI_PHY_812 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_3__FLD LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MIN_3 + +#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3_WIDTH 10U +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_812 +#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_812__PHY_NTP_PERIOD_THRESHOLD_MAX_3 + +#define LPDDR4__DENALI_PHY_813_READ_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x00FF0001U +#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3_WOSET 0U +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__REG DENALI_PHY_813 +#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_813__PHY_CALVL_VREF_DRIVING_SLICE_3 + +#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U +#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_813 +#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_813__SC_PHY_MANUAL_CLEAR_3 + +#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3_WIDTH 8U +#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_813 +#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_FIFO_PTR_OBS_3 + +#define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3_WIDTH 32U +#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_814 +#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_LPBK_RESULT_OBS_3 + +#define LPDDR4__DENALI_PHY_815_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH 16U +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_LPBK_ERROR_COUNT_OBS_3 + +#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3_WIDTH 11U +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_815 +#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_MASTER_DLY_LOCK_OBS_3 + +#define LPDDR4__DENALI_PHY_816_READ_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_816_WRITE_MASK 0xFFFF7F7FU +#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQ_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3_WIDTH 8U +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_3__FLD LPDDR4__DENALI_PHY_816__PHY_MEAS_DLY_STEP_VALUE_3 + +#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_816 +#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_817_READ_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x7F07FFFFU +#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_WIDTH 11U +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_WIDTH 7U +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_817 +#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_818_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_818 +#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_818 +#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3_WIDTH 3U +#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_818 +#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WR_SHIFT_OBS_3 + +#define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_819 +#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD0_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_819 +#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_WRLVL_HARD1_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_820_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3_WIDTH 21U +#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_820 +#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_821_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_821 +#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_WIDTH 10U +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_821 +#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3 + +#define LPDDR4__DENALI_PHY_822_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U +#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_822 +#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_WRLVL_ERROR_OBS_3 + +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_MASK 0x3FFF0000U +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_822 +#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_HARD0_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_823_READ_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK 0x00003FFFU +#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH 14U +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_823 +#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_GTLVL_HARD1_DELAY_OBS_3 + +#define LPDDR4__DENALI_PHY_824_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U +#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_824 +#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_GTLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_825_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_825_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__REG DENALI_PHY_825 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_825 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_826_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_826_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH 2U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_826 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3 + +#define LPDDR4__DENALI_PHY_827_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_827_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U +#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_827 +#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_RDLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_828_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_828_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__REG DENALI_PHY_828 +#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_LE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_828 +#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_DQDM_TE_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_829 +#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_STATUS_OBS_3 + +#define LPDDR4__DENALI_PHY_830_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_830_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH 32U +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_830 +#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_830__PHY_WDQLVL_PERIODIC_OBS_3 + +#define LPDDR4__DENALI_PHY_831_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3_WIDTH 31U +#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_831 +#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MODE_3 + +#define LPDDR4__DENALI_PHY_832_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_832_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3_WIDTH 6U +#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_832 +#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_MASK_3 + +#define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_833 +#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_OBS_3 + +#define LPDDR4__DENALI_PHY_834_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_834_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH 32U +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_834 +#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TEST_MSTR_DLY_OBS_3 + +#define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_835__PHY_DDL_TRACK_UPD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_835__PHY_LP4_WDQS_OE_EXTEND_3 + +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835 +#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3 + +#define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836 +#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3 + +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836 +#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3 + +#define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837 +#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3 + +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837 +#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3 + +#define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838 +#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3 + +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838 +#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3 + +#define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839 +#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3 + +#define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U +#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840 +#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3 + +#define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841 +#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3 + +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U +#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841 +#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3 + +#define LPDDR4__DENALI_PHY_842_READ_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_842_WRITE_MASK 0xFF1F07FFU +#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U +#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_842__PHY_PAD_RX_BIAS_EN_3 + +#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U +#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_842__PHY_STATIC_TOG_DISABLE_3 + +#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_842 +#define LPDDR4__PHY_DATA_DC_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_842__PHY_DATA_DC_CAL_SAMPLE_WAIT_3 + +#define LPDDR4__DENALI_PHY_843_READ_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_843_WRITE_MASK 0xFF3F03FFU +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_CAL_TIMEOUT_3 + +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_WEIGHT_3 + +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3_WIDTH 6U +#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_DATA_DC_ADJUST_START_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_START_3 + +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__REG DENALI_PHY_843 +#define LPDDR4__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3__FLD LPDDR4__DENALI_PHY_843__PHY_DATA_DC_ADJUST_SAMPLE_CNT_3 + +#define LPDDR4__DENALI_PHY_844_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_DATA_DC_ADJUST_THRSHLD_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_ADJUST_DIRECT_3 + +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_POLARITY_3 + +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_844 +#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_844__PHY_DATA_DC_CAL_START_3 + +#define LPDDR4__DENALI_PHY_845_READ_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x01010703U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_SW_RANK_3 + +#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3_WIDTH 3U +#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_845__PHY_FDBK_PWR_CTRL_3 + +#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_SLV_DLY_CTRL_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__REG DENALI_PHY_845 +#define LPDDR4__PHY_RDPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_RDPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_846_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_846__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3_WOSET 0U +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_846 +#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_846__PHY_SLICE_PWR_RDC_DISABLE_3 + +#define LPDDR4__DENALI_PHY_847_READ_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07FFFF07U +#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U +#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3_WIDTH 16U +#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQ_TSEL_SELECT_3 + +#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U +#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_847 +#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_847__PHY_DQS_TSEL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_848_READ_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x7F03FFFFU +#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3_WIDTH 16U +#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_848__PHY_DQS_TSEL_SELECT_3 + +#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_TWO_CYC_PREAMBLE_3 + +#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_848 +#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_848__PHY_VREF_INITIAL_START_POINT_3 + +#define LPDDR4__DENALI_PHY_849_READ_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_849_WRITE_MASK 0xFF01037FU +#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH 7U +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_849__PHY_VREF_INITIAL_STOP_POINT_3 + +#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U +#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_849__PHY_VREF_TRAINING_CTRL_3 + +#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3_WOSET 0U +#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_849__PHY_NTP_TRAIN_EN_3 + +#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_849 +#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_849__PHY_NTP_WDQ_STEP_SIZE_3 + +#define LPDDR4__DENALI_PHY_850_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_850 +#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_START_3 + +#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3_WIDTH 11U +#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_850 +#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_850__PHY_NTP_WDQ_STOP_3 + +#define LPDDR4__DENALI_PHY_851_READ_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x0103FFFFU +#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_851__PHY_NTP_WDQ_BIT_EN_3 + +#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U +#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_851__PHY_WDQLVL_DVW_MIN_3 + +#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3_WOSET 0U +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_851 +#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_851__PHY_SW_WDQLVL_DVW_MIN_EN_3 + +#define LPDDR4__DENALI_PHY_852_READ_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x1F1F0F3FU +#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH 6U +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_852__PHY_WDQLVL_PER_START_OFFSET_3 + +#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3_WIDTH 4U +#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_852__PHY_FAST_LVL_EN_3 + +#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_852__PHY_PAD_TX_DCD_3 + +#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_852 +#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_852__PHY_PAD_RX_DCD_0_3 + +#define LPDDR4__DENALI_PHY_853_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_1_3 + +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_2_3 + +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_3_3 + +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_853 +#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_853__PHY_PAD_RX_DCD_4_3 + +#define LPDDR4__DENALI_PHY_854_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_854_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_5_3 + +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_6_3 + +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3_WIDTH 5U +#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_RX_DCD_7_3 + +#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_854 +#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_854__PHY_PAD_DM_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_855_READ_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x007F1F1FU +#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_DQS_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_FDBK_RX_DCD_3 + +#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_MASK 0x007F0000U +#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 7U +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_855 +#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_855__PHY_PAD_DSLICE_IO_CFG_3 + +#define LPDDR4__DENALI_PHY_856_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_856__PHY_RDDQ0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_856 +#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_856__PHY_RDDQ1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_857_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_857__PHY_RDDQ2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_857 +#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_857__PHY_RDDQ3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_858_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_858__PHY_RDDQ4_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_858 +#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_858__PHY_RDDQ5_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_859_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_859__PHY_RDDQ6_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_859 +#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_859__PHY_RDDQ7_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_860_READ_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x1F0703FFU +#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_860__PHY_RDDM_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3_WIDTH 3U +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_RX_PCLK_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_860__PHY_RX_PCLK_CLK_SEL_3 + +#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RX_CAL_ALL_DLY_3__REG DENALI_PHY_860 +#define LPDDR4__PHY_RX_CAL_ALL_DLY_3__FLD LPDDR4__DENALI_PHY_860__PHY_RX_CAL_ALL_DLY_3 + +#define LPDDR4__DENALI_PHY_861_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3_WIDTH 3U +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_861 +#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_861__PHY_DATA_DC_CAL_CLK_SEL_3 + +#define LPDDR4__DENALI_PHY_862_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_862_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_OE_TIMING_3 + +#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQ_TSEL_WR_TIMING_3 + +#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_862 +#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_862__PHY_DQS_OE_TIMING_3 + +#define LPDDR4__DENALI_PHY_863_READ_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_863_WRITE_MASK 0xFFFFFF0FU +#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3_WIDTH 4U +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_IO_PAD_DELAY_TIMING_3 + +#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_OE_RD_TIMING_3 + +#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_863 +#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_863__PHY_DQS_TSEL_WR_TIMING_3 + +#define LPDDR4__DENALI_PHY_864_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3_WIDTH 16U +#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_864 +#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_864__PHY_VREF_SETTING_TIME_3 + +#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_864 +#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_864__PHY_PAD_VREF_CTRL_DQ_3 + +#define LPDDR4__DENALI_PHY_865_READ_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x03FFFF01U +#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3_WOSET 0U +#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_865__PHY_PER_CS_TRAINING_EN_3 + +#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_865__PHY_DQ_IE_TIMING_3 + +#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3_WIDTH 8U +#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_865__PHY_DQS_IE_TIMING_3 + +#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_865 +#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDATA_EN_IE_DLY_3 + +#define LPDDR4__DENALI_PHY_866_READ_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_866_WRITE_MASK 0x1F010303U +#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3_WIDTH 2U +#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_866__PHY_IE_MODE_3 + +#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3_WIDTH 2U +#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_866__PHY_DBI_MODE_3 + +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3_WOSET 0U +#define LPDDR4__PHY_WDQLVL_IE_ON_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_WDQLVL_IE_ON_3__FLD LPDDR4__DENALI_PHY_866__PHY_WDQLVL_IE_ON_3 + +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_3__REG DENALI_PHY_866 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_866__PHY_WDQLVL_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_867_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_867_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_TSEL_DLY_3 + +#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_867__PHY_RDDATA_EN_OE_DLY_3 + +#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3_WIDTH 4U +#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_867 +#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_867__PHY_SW_MASTER_MODE_3 + +#define LPDDR4__DENALI_PHY_868_READ_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_868_WRITE_MASK 0xFF3F07FFU +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3_WIDTH 11U +#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_START_3 + +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3_WIDTH 6U +#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_STEP_3 + +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_868 +#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_868__PHY_MASTER_DELAY_WAIT_3 + +#define LPDDR4__DENALI_PHY_869_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3_WIDTH 8U +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_869__PHY_MASTER_DELAY_HALF_MEASURE_3 + +#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3_WIDTH 4U +#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_869__PHY_RPTR_UPDATE_3 + +#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3_WIDTH 8U +#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__REG DENALI_PHY_869 +#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_3__FLD LPDDR4__DENALI_PHY_869__PHY_WRLVL_DLY_FINE_STEP_3 + +#define LPDDR4__DENALI_PHY_870_READ_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x001F0F3FU +#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3_WIDTH 6U +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_870__PHY_WRLVL_RESP_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_870__PHY_GTLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3_WIDTH 5U +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_870 +#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_870__PHY_GTLVL_RESP_WAIT_CNT_3 + +#define LPDDR4__DENALI_PHY_871_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_GTLVL_BACK_STEP_3 + +#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_871 +#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_GTLVL_FINAL_STEP_3 + +#define LPDDR4__DENALI_PHY_872_READ_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_872_WRITE_MASK 0x01FF0FFFU +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U +#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_QTR_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3_WIDTH 9U +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_3__REG DENALI_PHY_872 +#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_3__FLD LPDDR4__DENALI_PHY_872__PHY_WDQLVL_DM_SEARCH_RANGE_3 + +#define LPDDR4__DENALI_PHY_873_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_873__PHY_TOGGLE_PRE_SUPPORT_3 + +#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3_WIDTH 4U +#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_873 +#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_RDLVL_DLY_STEP_3 + +#define LPDDR4__DENALI_PHY_874_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_874 +#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_874__PHY_RDLVL_MAX_EDGE_3 + +#define LPDDR4__DENALI_PHY_875_READ_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x00030703U +#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_DISABLE_3 + +#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U +#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_875__PHY_WRPATH_GATE_TIMING_3 + +#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3_WIDTH 2U +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_875 +#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_875__PHY_DATA_DC_INIT_DISABLE_3 + +#define LPDDR4__DENALI_PHY_876_READ_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x07FF03FFU +#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__REG DENALI_PHY_876 +#define LPDDR4__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 + +#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_876 +#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_876__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 + +#define LPDDR4__DENALI_PHY_877_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_877_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_DATA_DC_WRLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WRLVL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3_WOSET 0U +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_DATA_DC_WDQLVL_ENABLE_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_WDQLVL_ENABLE_3 + +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_SE_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_877 +#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_877__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3 + +#define LPDDR4__DENALI_PHY_878_READ_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x001F7F7FU +#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3_WIDTH 7U +#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_878__PHY_WDQ_OSC_DELTA_3 + +#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3_WIDTH 7U +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_MEAS_DLY_STEP_ENABLE_3 + +#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3_WIDTH 5U +#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_878 +#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_878__PHY_RDDATA_EN_DLY_3 + +#define LPDDR4__DENALI_PHY_879_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_879_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_879 +#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_879__PHY_DQ_DM_SWIZZLE0_3 + +#define LPDDR4__DENALI_PHY_880_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_880_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_880 +#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_880__PHY_DQ_DM_SWIZZLE1_3 + +#define LPDDR4__DENALI_PHY_881_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_881 +#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_881__PHY_CLK_WRDQ1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_882_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_882_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__REG DENALI_PHY_882 +#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_882 +#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_882__PHY_CLK_WRDQ3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_883_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__REG DENALI_PHY_883 +#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ4_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_883 +#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_883__PHY_CLK_WRDQ5_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__REG DENALI_PHY_884 +#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ6_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_884 +#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ7_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_885_READ_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x03FF07FFU +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__REG DENALI_PHY_885 +#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDM_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_885 +#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQS_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_886_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH 2U +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__REG DENALI_PHY_886 +#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_3__FLD LPDDR4__DENALI_PHY_886__PHY_WRLVL_THRESHOLD_ADJUST_3 + +#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_MASK 0x0003FF00U +#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_886 +#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_887_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__REG DENALI_PHY_887 +#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_887 +#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__REG DENALI_PHY_888 +#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_888 +#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_889_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__REG DENALI_PHY_889 +#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889 +#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__REG DENALI_PHY_890 +#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890 +#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__REG DENALI_PHY_891 +#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891 +#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__REG DENALI_PHY_892 +#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892 +#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__REG DENALI_PHY_893 +#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893 +#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__REG DENALI_PHY_894 +#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894 +#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__REG DENALI_PHY_895 +#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3_WIDTH 10U +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_895 +#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_GATE_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF070FU +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH 4U +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_LATENCY_ADJUST_3 + +#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_896__PHY_WRITE_PATH_LAT_ADD_3 + +#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_896 +#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_896__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_897_READ_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x000103FFU +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH 10U +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__REG DENALI_PHY_897 +#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_897__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 + +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3_WOSET 0U +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_897 +#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_897__PHY_WRLVL_EARLY_FORCE_ZERO_3 + +#define LPDDR4__DENALI_PHY_898_READ_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x000F03FFU +#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH 10U +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__REG DENALI_PHY_898 +#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_898__PHY_GTLVL_RDDQS_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3_WIDTH 4U +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_898 +#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_898__PHY_GTLVL_LAT_ADJ_START_3 + +#define LPDDR4__DENALI_PHY_899_READ_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x010F07FFU +#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH 11U +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_899__PHY_WDQLVL_DQDM_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3_WIDTH 4U +#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_899__PHY_NTP_WRLAT_START_3 + +#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WIDTH 1U +#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WOCLR 0U +#define LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3_WOSET 0U +#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_899 +#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_899__PHY_NTP_PASS_3 + +#define LPDDR4__DENALI_PHY_900_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH 10U +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_900 +#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_900__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 + +#define LPDDR4__DENALI_PHY_901_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_901_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_DATA_DC_DQS_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQS_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_DATA_DC_DQ0_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ0_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_DATA_DC_DQ1_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ1_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_901 +#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_901__PHY_DATA_DC_DQ2_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_902_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_902_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_DATA_DC_DQ3_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ3_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_DATA_DC_DQ4_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ4_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_DATA_DC_DQ5_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ5_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_902 +#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_902__PHY_DATA_DC_DQ6_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_903_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_903_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__REG DENALI_PHY_903 +#define LPDDR4__PHY_DATA_DC_DQ7_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DQ7_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3_WIDTH 8U +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__REG DENALI_PHY_903 +#define LPDDR4__PHY_DATA_DC_DM_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_903__PHY_DATA_DC_DM_CLK_ADJUST_3 + +#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3_WIDTH 16U +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_903 +#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_903__PHY_DSLICE_PAD_BOOSTPN_SETTING_3 + +#define LPDDR4__DENALI_PHY_904_READ_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_904_WRITE_MASK 0x0003033FU +#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH 6U +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_904__PHY_DSLICE_PAD_RX_CTLE_SETTING_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3_WIDTH 2U +#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_904__PHY_DQ_FFE_3 + +#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3_WIDTH 2U +#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_904 +#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_904__PHY_DQS_FFE_3 + +#endif /* REG_LPDDR4_DATA_SLICE_3_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h new file mode 100644 index 0000000000..61ae622a79 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_ddr_controller_macros.h @@ -0,0 +1,6560 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ +#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ + +#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U +#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U +#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U +#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U +#define LPDDR4__DENALI_CTL_0__START_WOSET 0U +#define LPDDR4__START__REG DENALI_CTL_0 +#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START + +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U +#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0 +#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS + +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U +#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U +#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0 +#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID + +#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1 +#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0 + +#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U +#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2 +#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1 + +#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U +#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U +#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG + +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U +#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U +#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG + +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U +#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U +#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3 +#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG + +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3 +#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4 +#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH + +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5 +#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH + +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U +#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U +#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5 +#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES + +#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U +#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U +#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U +#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6 +#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH + +#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U +#define LPDDR4__TINIT_F0__REG DENALI_CTL_7 +#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0 + +#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U +#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8 +#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0 + +#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U +#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9 +#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0 + +#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U +#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10 +#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0 + +#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U +#define LPDDR4__TINIT_F1__REG DENALI_CTL_11 +#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1 + +#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U +#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12 +#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1 + +#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U +#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13 +#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1 + +#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U +#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14 +#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1 + +#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U +#define LPDDR4__TINIT_F2__REG DENALI_CTL_15 +#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2 + +#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U +#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16 +#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2 + +#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U +#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17 +#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2 + +#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U +#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18 +#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2 + +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18 +#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_CTL_19_READ_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x03030301U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U +#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19 +#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH 2U +#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19 +#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0 + +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH 2U +#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19 +#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1 + +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH 2U +#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19 +#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2 + +#define LPDDR4__DENALI_CTL_20_READ_MASK 0x01030101U +#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x01030101U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT 0U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET 0U +#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20 +#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO + +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET 0U +#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20 +#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT + +#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT 16U +#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH 2U +#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20 +#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE + +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 24U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20 +#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE + +#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F013FU +#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F013FU +#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT 0U +#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH 6U +#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21 +#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR + +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT 8U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH 1U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR 0U +#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET 0U +#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21 +#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0 + +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21 +#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1 + +#define LPDDR4__DENALI_CTL_22_READ_MASK 0x0303031FU +#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x0303031FU +#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH 5U +#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22 +#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1 + +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U +#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22 +#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2 + +#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U +#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23 +#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON + +#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U +#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24 +#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE + +#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH 16U +#define LPDDR4__TDLL_F0__REG DENALI_CTL_25 +#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0 + +#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH 16U +#define LPDDR4__TDLL_F1__REG DENALI_CTL_25 +#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1 + +#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH 16U +#define LPDDR4__TDLL_F2__REG DENALI_CTL_26 +#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2 + +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U +#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26 +#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS + +#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH 2U +#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26 +#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS + +#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFFFFFF01U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT 0U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH 1U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR 0U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET 0U +#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27 +#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST + +#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT 8U +#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH 24U +#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27 +#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD + +#define LPDDR4__DENALI_CTL_28_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT 0U +#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH 8U +#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28 +#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG + +#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT 8U +#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH 8U +#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28 +#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG + +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET 0U +#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28 +#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE + +#define LPDDR4__DENALI_CTL_29_READ_MASK 0x000F7FFFU +#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0x000F7FFFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK 0x00007FFFU +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT 0U +#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH 15U +#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29 +#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD + +#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT 16U +#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH 4U +#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29 +#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES + +#define LPDDR4__DENALI_CTL_30_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH 32U +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30 +#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH 32U +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31 +#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH 32U +#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32 +#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT + +#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 32U +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33 +#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD + +#define LPDDR4__DENALI_CTL_34_READ_MASK 0xFF00FFFFU +#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0xFF00FFFFU +#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH 16U +#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34 +#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT + +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT 16U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH 1U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR 0U +#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET 0U +#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34 +#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST + +#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH 8U +#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34 +#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0 + +#define LPDDR4__DENALI_CTL_35_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH 8U +#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35 +#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1 + +#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH 8U +#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35 +#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2 + +#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35 +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0 + +#define LPDDR4__DENALI_CTL_36_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36 +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0 + +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_36 +#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_2_CS0 + +#define LPDDR4__DENALI_CTL_37_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_37 +#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_3_CS0 + +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_37 +#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_0_CS1 + +#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_38 +#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_1_CS1 + +#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_38 +#define LPDDR4__DQS_OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_38__DQS_OSC_BASE_VALUE_2_CS1 + +#define LPDDR4__DENALI_CTL_39_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1_WIDTH 16U +#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_39 +#define LPDDR4__DQS_OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_BASE_VALUE_3_CS1 + +#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS_WIDTH 4U +#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_39 +#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_STATUS + +#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS_WOSET 0U +#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_39 +#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_39__DQS_OSC_IN_PROGRESS_STATUS + +#define LPDDR4__DENALI_CTL_40_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_40 +#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F0 + +#define LPDDR4__DENALI_CTL_40__WRLAT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_40__WRLAT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_40__WRLAT_F0_WIDTH 7U +#define LPDDR4__WRLAT_F0__REG DENALI_CTL_40 +#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_40__WRLAT_F0 + +#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0_WIDTH 6U +#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_40 +#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F0 + +#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0_WIDTH 4U +#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_40 +#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F0 + +#define LPDDR4__DENALI_CTL_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F0_WIDTH 8U +#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_41 +#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F0 + +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F0_WIDTH 8U +#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_41 +#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F0 + +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0_WIDTH 8U +#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_41 +#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F0 + +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0_WIDTH 8U +#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_41 +#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F0 + +#define LPDDR4__DENALI_CTL_42_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_42 +#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F1 + +#define LPDDR4__DENALI_CTL_42__WRLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_42__WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_42__WRLAT_F1_WIDTH 7U +#define LPDDR4__WRLAT_F1__REG DENALI_CTL_42 +#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_42__WRLAT_F1 + +#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1_WIDTH 6U +#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_42 +#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F1 + +#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1_WIDTH 4U +#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_42 +#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F1 + +#define LPDDR4__DENALI_CTL_43_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F1_WIDTH 8U +#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_43 +#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F1 + +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F1_WIDTH 8U +#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_43 +#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F1 + +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1_WIDTH 8U +#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_43 +#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F1 + +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1_WIDTH 8U +#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_43 +#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F1 + +#define LPDDR4__DENALI_CTL_44_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_44 +#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_44__CASLAT_LIN_F2 + +#define LPDDR4__DENALI_CTL_44__WRLAT_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_44__WRLAT_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_44__WRLAT_F2_WIDTH 7U +#define LPDDR4__WRLAT_F2__REG DENALI_CTL_44 +#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_44__WRLAT_F2 + +#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2_WIDTH 6U +#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_44 +#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_44__ADDITIVE_LAT_F2 + +#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2_WIDTH 4U +#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_44 +#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_44__CA_PARITY_LAT_F2 + +#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_45__TMOD_PAR_F2_WIDTH 8U +#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_45 +#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_45__TMOD_PAR_F2 + +#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_45__TMRD_PAR_F2_WIDTH 8U +#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_45 +#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_45__TMRD_PAR_F2 + +#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2_WIDTH 8U +#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_45 +#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_45__TMOD_PAR_MAX_PL_F2 + +#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2_WIDTH 8U +#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_45 +#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_45__TMRD_PAR_MAX_PL_F2 + +#define LPDDR4__DENALI_CTL_46_READ_MASK 0xFF1F1F07U +#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0xFF1F1F07U +#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL_WIDTH 3U +#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_46 +#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_46__TBST_INT_INTERVAL + +#define LPDDR4__DENALI_CTL_46__TCCD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_46__TCCD_SHIFT 8U +#define LPDDR4__DENALI_CTL_46__TCCD_WIDTH 5U +#define LPDDR4__TCCD__REG DENALI_CTL_46 +#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_46__TCCD + +#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_46__TCCD_L_F0_WIDTH 5U +#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_46 +#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_46__TCCD_L_F0 + +#define LPDDR4__DENALI_CTL_46__TRRD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_46__TRRD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_46__TRRD_F0_WIDTH 8U +#define LPDDR4__TRRD_F0__REG DENALI_CTL_46 +#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_46__TRRD_F0 + +#define LPDDR4__DENALI_CTL_47_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_47__TRRD_L_F0_WIDTH 8U +#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_47 +#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_47__TRRD_L_F0 + +#define LPDDR4__DENALI_CTL_47__TRC_F0_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_47__TRC_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_47__TRC_F0_WIDTH 9U +#define LPDDR4__TRC_F0__REG DENALI_CTL_47 +#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_47__TRC_F0 + +#define LPDDR4__DENALI_CTL_48_READ_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_48__TRAS_MIN_F0_WIDTH 9U +#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_48 +#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_48__TRAS_MIN_F0 + +#define LPDDR4__DENALI_CTL_48__TWTR_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_48__TWTR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_48__TWTR_F0_WIDTH 6U +#define LPDDR4__TWTR_F0__REG DENALI_CTL_48 +#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_48__TWTR_F0 + +#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_48__TWTR_L_F0_WIDTH 6U +#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_48 +#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_48__TWTR_L_F0 + +#define LPDDR4__DENALI_CTL_49_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_49__TRP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_49__TRP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_49__TRP_F0_WIDTH 8U +#define LPDDR4__TRP_F0__REG DENALI_CTL_49 +#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_49__TRP_F0 + +#define LPDDR4__DENALI_CTL_49__TFAW_F0_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_49__TFAW_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_49__TFAW_F0_WIDTH 9U +#define LPDDR4__TFAW_F0__REG DENALI_CTL_49 +#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_49__TFAW_F0 + +#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_49__TCCD_L_F1_WIDTH 5U +#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_49 +#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_49__TCCD_L_F1 + +#define LPDDR4__DENALI_CTL_50_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_50__TRRD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_50__TRRD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_50__TRRD_F1_WIDTH 8U +#define LPDDR4__TRRD_F1__REG DENALI_CTL_50 +#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_50__TRRD_F1 + +#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_50__TRRD_L_F1_WIDTH 8U +#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_50 +#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_50__TRRD_L_F1 + +#define LPDDR4__DENALI_CTL_50__TRC_F1_MASK 0x01FF0000U +#define LPDDR4__DENALI_CTL_50__TRC_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_50__TRC_F1_WIDTH 9U +#define LPDDR4__TRC_F1__REG DENALI_CTL_50 +#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_50__TRC_F1 + +#define LPDDR4__DENALI_CTL_51_READ_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_51__TRAS_MIN_F1_WIDTH 9U +#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_51 +#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_51__TRAS_MIN_F1 + +#define LPDDR4__DENALI_CTL_51__TWTR_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_51__TWTR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_51__TWTR_F1_WIDTH 6U +#define LPDDR4__TWTR_F1__REG DENALI_CTL_51 +#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_51__TWTR_F1 + +#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_51__TWTR_L_F1_WIDTH 6U +#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_51 +#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_51__TWTR_L_F1 + +#define LPDDR4__DENALI_CTL_52_READ_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x1F01FFFFU +#define LPDDR4__DENALI_CTL_52__TRP_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_52__TRP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_52__TRP_F1_WIDTH 8U +#define LPDDR4__TRP_F1__REG DENALI_CTL_52 +#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_52__TRP_F1 + +#define LPDDR4__DENALI_CTL_52__TFAW_F1_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_52__TFAW_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_52__TFAW_F1_WIDTH 9U +#define LPDDR4__TFAW_F1__REG DENALI_CTL_52 +#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_52__TFAW_F1 + +#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_52__TCCD_L_F2_WIDTH 5U +#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_52 +#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_52__TCCD_L_F2 + +#define LPDDR4__DENALI_CTL_53_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_53__TRRD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_53__TRRD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_53__TRRD_F2_WIDTH 8U +#define LPDDR4__TRRD_F2__REG DENALI_CTL_53 +#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_53__TRRD_F2 + +#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_53__TRRD_L_F2_WIDTH 8U +#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_53 +#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_53__TRRD_L_F2 + +#define LPDDR4__DENALI_CTL_53__TRC_F2_MASK 0x01FF0000U +#define LPDDR4__DENALI_CTL_53__TRC_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_53__TRC_F2_WIDTH 9U +#define LPDDR4__TRC_F2__REG DENALI_CTL_53 +#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_53__TRC_F2 + +#define LPDDR4__DENALI_CTL_54_READ_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x3F3F01FFU +#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_MASK 0x000001FFU +#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_54__TRAS_MIN_F2_WIDTH 9U +#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_54 +#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_54__TRAS_MIN_F2 + +#define LPDDR4__DENALI_CTL_54__TWTR_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_54__TWTR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_54__TWTR_F2_WIDTH 6U +#define LPDDR4__TWTR_F2__REG DENALI_CTL_54 +#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_54__TWTR_F2 + +#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_54__TWTR_L_F2_WIDTH 6U +#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_54 +#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_54__TWTR_L_F2 + +#define LPDDR4__DENALI_CTL_55_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_55__TRP_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_55__TRP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_55__TRP_F2_WIDTH 8U +#define LPDDR4__TRP_F2__REG DENALI_CTL_55 +#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_55__TRP_F2 + +#define LPDDR4__DENALI_CTL_55__TFAW_F2_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_55__TFAW_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_55__TFAW_F2_WIDTH 9U +#define LPDDR4__TFAW_F2__REG DENALI_CTL_55 +#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_55__TFAW_F2 + +#define LPDDR4__DENALI_CTL_55__TRTP_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_55__TRTP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_55__TRTP_F0_WIDTH 8U +#define LPDDR4__TRTP_F0__REG DENALI_CTL_55 +#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_55__TRTP_F0 + +#define LPDDR4__DENALI_CTL_56_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_56__TRTP_AP_F0_WIDTH 8U +#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_56 +#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F0 + +#define LPDDR4__DENALI_CTL_56__TMRD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_56__TMRD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_56__TMRD_F0_WIDTH 8U +#define LPDDR4__TMRD_F0__REG DENALI_CTL_56 +#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_56__TMRD_F0 + +#define LPDDR4__DENALI_CTL_56__TMOD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_56__TMOD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_56__TMOD_F0_WIDTH 8U +#define LPDDR4__TMOD_F0__REG DENALI_CTL_56 +#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_56__TMOD_F0 + +#define LPDDR4__DENALI_CTL_57_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_57__TRAS_MAX_F0_WIDTH 20U +#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_57 +#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_57__TRAS_MAX_F0 + +#define LPDDR4__DENALI_CTL_57__TCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_57__TCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_57__TCKE_F0_WIDTH 5U +#define LPDDR4__TCKE_F0__REG DENALI_CTL_57 +#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_57__TCKE_F0 + +#define LPDDR4__DENALI_CTL_58_READ_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_58__TCKESR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_58__TCKESR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_58__TCKESR_F0_WIDTH 8U +#define LPDDR4__TCKESR_F0__REG DENALI_CTL_58 +#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_58__TCKESR_F0 + +#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_58__TCCDMW_F0_WIDTH 6U +#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_58 +#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_58__TCCDMW_F0 + +#define LPDDR4__DENALI_CTL_58__TRTP_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_58__TRTP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_58__TRTP_F1_WIDTH 8U +#define LPDDR4__TRTP_F1__REG DENALI_CTL_58 +#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_58__TRTP_F1 + +#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_58__TRTP_AP_F1_WIDTH 8U +#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_58 +#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_58__TRTP_AP_F1 + +#define LPDDR4__DENALI_CTL_59_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_59__TMRD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_59__TMRD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_59__TMRD_F1_WIDTH 8U +#define LPDDR4__TMRD_F1__REG DENALI_CTL_59 +#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_59__TMRD_F1 + +#define LPDDR4__DENALI_CTL_59__TMOD_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_59__TMOD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_59__TMOD_F1_WIDTH 8U +#define LPDDR4__TMOD_F1__REG DENALI_CTL_59 +#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_59__TMOD_F1 + +#define LPDDR4__DENALI_CTL_60_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_60__TRAS_MAX_F1_WIDTH 20U +#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_60 +#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_60__TRAS_MAX_F1 + +#define LPDDR4__DENALI_CTL_60__TCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_60__TCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_60__TCKE_F1_WIDTH 5U +#define LPDDR4__TCKE_F1__REG DENALI_CTL_60 +#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_60__TCKE_F1 + +#define LPDDR4__DENALI_CTL_61_READ_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0xFFFF3FFFU +#define LPDDR4__DENALI_CTL_61__TCKESR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_61__TCKESR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_61__TCKESR_F1_WIDTH 8U +#define LPDDR4__TCKESR_F1__REG DENALI_CTL_61 +#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_61__TCKESR_F1 + +#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_61__TCCDMW_F1_WIDTH 6U +#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_61 +#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_61__TCCDMW_F1 + +#define LPDDR4__DENALI_CTL_61__TRTP_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_61__TRTP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_61__TRTP_F2_WIDTH 8U +#define LPDDR4__TRTP_F2__REG DENALI_CTL_61 +#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_61__TRTP_F2 + +#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_61__TRTP_AP_F2_WIDTH 8U +#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_61 +#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_61__TRTP_AP_F2 + +#define LPDDR4__DENALI_CTL_62_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_62__TMRD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_62__TMRD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_62__TMRD_F2_WIDTH 8U +#define LPDDR4__TMRD_F2__REG DENALI_CTL_62 +#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_62__TMRD_F2 + +#define LPDDR4__DENALI_CTL_62__TMOD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_62__TMOD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_62__TMOD_F2_WIDTH 8U +#define LPDDR4__TMOD_F2__REG DENALI_CTL_62 +#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_62__TMOD_F2 + +#define LPDDR4__DENALI_CTL_63_READ_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x1F0FFFFFU +#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_63__TRAS_MAX_F2_WIDTH 20U +#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_63 +#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_63__TRAS_MAX_F2 + +#define LPDDR4__DENALI_CTL_63__TCKE_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_63__TCKE_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_63__TCKE_F2_WIDTH 5U +#define LPDDR4__TCKE_F2__REG DENALI_CTL_63 +#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_63__TCKE_F2 + +#define LPDDR4__DENALI_CTL_64_READ_MASK 0x07073FFFU +#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x07073FFFU +#define LPDDR4__DENALI_CTL_64__TCKESR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_64__TCKESR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_64__TCKESR_F2_WIDTH 8U +#define LPDDR4__TCKESR_F2__REG DENALI_CTL_64 +#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_64__TCKESR_F2 + +#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_64__TCCDMW_F2_WIDTH 6U +#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_64 +#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_64__TCCDMW_F2 + +#define LPDDR4__DENALI_CTL_64__TPPD_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_64__TPPD_SHIFT 16U +#define LPDDR4__DENALI_CTL_64__TPPD_WIDTH 3U +#define LPDDR4__TPPD__REG DENALI_CTL_64 +#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_64__TPPD + +#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_SHIFT 24U +#define LPDDR4__DENALI_CTL_64__MC_RESERVED0_WIDTH 3U +#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_64 +#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_64__MC_RESERVED0 + +#define LPDDR4__DENALI_CTL_65_READ_MASK 0xFFFF0107U +#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0xFFFF0107U +#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_SHIFT 0U +#define LPDDR4__DENALI_CTL_65__MC_RESERVED1_WIDTH 3U +#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_65 +#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_65__MC_RESERVED1 + +#define LPDDR4__DENALI_CTL_65__WRITEINTERP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_65__WRITEINTERP_SHIFT 8U +#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WIDTH 1U +#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WOCLR 0U +#define LPDDR4__DENALI_CTL_65__WRITEINTERP_WOSET 0U +#define LPDDR4__WRITEINTERP__REG DENALI_CTL_65 +#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_65__WRITEINTERP + +#define LPDDR4__DENALI_CTL_65__TRCD_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_65__TRCD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_65__TRCD_F0_WIDTH 8U +#define LPDDR4__TRCD_F0__REG DENALI_CTL_65 +#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_65__TRCD_F0 + +#define LPDDR4__DENALI_CTL_65__TWR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_65__TWR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_65__TWR_F0_WIDTH 8U +#define LPDDR4__TWR_F0__REG DENALI_CTL_65 +#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_65__TWR_F0 + +#define LPDDR4__DENALI_CTL_66_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_66__TRCD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_66__TRCD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_66__TRCD_F1_WIDTH 8U +#define LPDDR4__TRCD_F1__REG DENALI_CTL_66 +#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_66__TRCD_F1 + +#define LPDDR4__DENALI_CTL_66__TWR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_66__TWR_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_66__TWR_F1_WIDTH 8U +#define LPDDR4__TWR_F1__REG DENALI_CTL_66 +#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_66__TWR_F1 + +#define LPDDR4__DENALI_CTL_66__TRCD_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_66__TRCD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_66__TRCD_F2_WIDTH 8U +#define LPDDR4__TRCD_F2__REG DENALI_CTL_66 +#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_66__TRCD_F2 + +#define LPDDR4__DENALI_CTL_66__TWR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_66__TWR_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_66__TWR_F2_WIDTH 8U +#define LPDDR4__TWR_F2__REG DENALI_CTL_66 +#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_66__TWR_F2 + +#define LPDDR4__DENALI_CTL_67_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_CTL_67__TMRR_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_67__TMRR_SHIFT 0U +#define LPDDR4__DENALI_CTL_67__TMRR_WIDTH 4U +#define LPDDR4__TMRR__REG DENALI_CTL_67 +#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_67__TMRR + +#define LPDDR4__DENALI_CTL_67__AP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_67__AP_SHIFT 8U +#define LPDDR4__DENALI_CTL_67__AP_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__AP_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__AP_WOSET 0U +#define LPDDR4__AP__REG DENALI_CTL_67 +#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_67__AP + +#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_SHIFT 16U +#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__CONCURRENTAP_WOSET 0U +#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_67 +#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_67__CONCURRENTAP + +#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_SHIFT 24U +#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WIDTH 1U +#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WOCLR 0U +#define LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT_WOSET 0U +#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_67 +#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_67__TRAS_LOCKOUT + +#define LPDDR4__DENALI_CTL_68_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_CTL_68__TDAL_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_68__TDAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_68__TDAL_F0_WIDTH 8U +#define LPDDR4__TDAL_F0__REG DENALI_CTL_68 +#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_68__TDAL_F0 + +#define LPDDR4__DENALI_CTL_68__TDAL_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_68__TDAL_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_68__TDAL_F1_WIDTH 8U +#define LPDDR4__TDAL_F1__REG DENALI_CTL_68 +#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_68__TDAL_F1 + +#define LPDDR4__DENALI_CTL_68__TDAL_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_68__TDAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_68__TDAL_F2_WIDTH 8U +#define LPDDR4__TDAL_F2__REG DENALI_CTL_68 +#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_68__TDAL_F2 + +#define LPDDR4__DENALI_CTL_68__BSTLEN_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_68__BSTLEN_SHIFT 24U +#define LPDDR4__DENALI_CTL_68__BSTLEN_WIDTH 6U +#define LPDDR4__BSTLEN__REG DENALI_CTL_68 +#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_68__BSTLEN + +#define LPDDR4__DENALI_CTL_69_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_0_WIDTH 8U +#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_69 +#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F0_0 + +#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F1_0_WIDTH 8U +#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_69 +#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F1_0 + +#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F2_0_WIDTH 8U +#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_69 +#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F2_0 + +#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_69__TRP_AB_F0_1_WIDTH 8U +#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_69 +#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_69__TRP_AB_F0_1 + +#define LPDDR4__DENALI_CTL_70_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_70__TRP_AB_F1_1_WIDTH 8U +#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_70 +#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_70__TRP_AB_F1_1 + +#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_70__TRP_AB_F2_1_WIDTH 8U +#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_70 +#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_70__TRP_AB_F2_1 + +#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_70 +#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_70__REG_DIMM_ENABLE + +#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_SHIFT 24U +#define LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING_WIDTH 2U +#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_70 +#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_70__ADDRESS_MIRRORING + +#define LPDDR4__DENALI_CTL_71_READ_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN_WOSET 0U +#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_71 +#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_71__OPTIMAL_RMODW_EN + +#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_SHIFT 8U +#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__MC_RESERVED2_WOSET 0U +#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_71 +#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_71__MC_RESERVED2 + +#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_SHIFT 16U +#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WIDTH 1U +#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WOCLR 0U +#define LPDDR4__DENALI_CTL_71__NO_MEMORY_DM_WOSET 0U +#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_71 +#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_71__NO_MEMORY_DM + +#define LPDDR4__DENALI_CTL_72_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_SHIFT 0U +#define LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT_WIDTH 26U +#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_72 +#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_72__CA_PARITY_ERROR_INJECT + +#define LPDDR4__DENALI_CTL_73_READ_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_SHIFT 0U +#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WIDTH 1U +#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WOCLR 0U +#define LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR_WOSET 0U +#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_73 +#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_73__CA_PARITY_ERROR + +#define LPDDR4__DENALI_CTL_73__AREFRESH_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_73__AREFRESH_SHIFT 8U +#define LPDDR4__DENALI_CTL_73__AREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_73__AREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_73__AREFRESH_WOSET 0U +#define LPDDR4__AREFRESH__REG DENALI_CTL_73 +#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_73__AREFRESH + +#define LPDDR4__DENALI_CTL_73__AREF_STATUS_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_73__AREF_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_73__AREF_STATUS_WOSET 0U +#define LPDDR4__AREF_STATUS__REG DENALI_CTL_73 +#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_73__AREF_STATUS + +#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_73__TREF_ENABLE_WOSET 0U +#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_73 +#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_73__TREF_ENABLE + +#define LPDDR4__DENALI_CTL_74_READ_MASK 0x03FF3F07U +#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x03FF3F07U +#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD_WIDTH 3U +#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_74 +#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_74__TRFC_OPT_THRESHOLD + +#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_74 +#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_74__CS_COMPARISON_FOR_REFRESH_DEPTH + +#define LPDDR4__DENALI_CTL_74__TRFC_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_74__TRFC_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_74__TRFC_F0_WIDTH 10U +#define LPDDR4__TRFC_F0__REG DENALI_CTL_74 +#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_74__TRFC_F0 + +#define LPDDR4__DENALI_CTL_75_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_75__TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_75__TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_75__TREF_F0_WIDTH 20U +#define LPDDR4__TREF_F0__REG DENALI_CTL_75 +#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_75__TREF_F0 + +#define LPDDR4__DENALI_CTL_76_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_76__TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_76__TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_76__TRFC_F1_WIDTH 10U +#define LPDDR4__TRFC_F1__REG DENALI_CTL_76 +#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_76__TRFC_F1 + +#define LPDDR4__DENALI_CTL_77_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_77__TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_77__TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_77__TREF_F1_WIDTH 20U +#define LPDDR4__TREF_F1__REG DENALI_CTL_77 +#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_77__TREF_F1 + +#define LPDDR4__DENALI_CTL_78_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_78__TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_78__TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_78__TRFC_F2_WIDTH 10U +#define LPDDR4__TRFC_F2__REG DENALI_CTL_78 +#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_78__TRFC_F2 + +#define LPDDR4__DENALI_CTL_79_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_79__TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_79__TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_79__TREF_F2_WIDTH 20U +#define LPDDR4__TREF_F2__REG DENALI_CTL_79 +#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_79__TREF_F2 + +#define LPDDR4__DENALI_CTL_80_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_CTL_80__TREF_INTERVAL_WIDTH 20U +#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_80 +#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_80__TREF_INTERVAL + +#define LPDDR4__DENALI_CTL_81_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_81__TRFC_PB_F0_WIDTH 10U +#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_81 +#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F0 + +#define LPDDR4__DENALI_CTL_82_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_82__TREFI_PB_F0_WIDTH 20U +#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_82 +#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F0 + +#define LPDDR4__DENALI_CTL_83_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_83__TRFC_PB_F1_WIDTH 10U +#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_83 +#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F1 + +#define LPDDR4__DENALI_CTL_84_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_84__TREFI_PB_F1_WIDTH 20U +#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_84 +#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F1 + +#define LPDDR4__DENALI_CTL_85_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_85__TRFC_PB_F2_WIDTH 10U +#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_85 +#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_85__TRFC_PB_F2 + +#define LPDDR4__DENALI_CTL_86_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_86__TREFI_PB_F2_WIDTH 20U +#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_86 +#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_86__TREFI_PB_F2 + +#define LPDDR4__DENALI_CTL_86__PBR_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_86__PBR_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_86__PBR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_86__PBR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_86__PBR_EN_WOSET 0U +#define LPDDR4__PBR_EN__REG DENALI_CTL_86 +#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_86__PBR_EN + +#define LPDDR4__DENALI_CTL_87_READ_MASK 0x0FFFFF01U +#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x0FFFFF01U +#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_SHIFT 0U +#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WIDTH 1U +#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WOCLR 0U +#define LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER_WOSET 0U +#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_87 +#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_87__PBR_NUMERIC_ORDER + +#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT_WIDTH 16U +#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_87 +#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_87__PBR_MAX_BANK_WAIT + +#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_SHIFT 24U +#define LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY_WIDTH 4U +#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_87 +#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_87__PBR_BANK_SELECT_DELAY + +#define LPDDR4__DENALI_CTL_88_READ_MASK 0x001F1F01U +#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x001F1F01U +#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN_WOSET 0U +#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_88 +#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_88__PBR_CONT_REQ_EN + +#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_88 +#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_EN_THRESHOLD + +#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 16U +#define LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_88 +#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_88__AREF_PBR_CONT_DIS_THRESHOLD + +#define LPDDR4__DENALI_CTL_89_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_89__TPDEX_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_89__TPDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_89__TPDEX_F0_WIDTH 16U +#define LPDDR4__TPDEX_F0__REG DENALI_CTL_89 +#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_89__TPDEX_F0 + +#define LPDDR4__DENALI_CTL_89__TPDEX_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_89__TPDEX_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_89__TPDEX_F1_WIDTH 16U +#define LPDDR4__TPDEX_F1__REG DENALI_CTL_89 +#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_89__TPDEX_F1 + +#define LPDDR4__DENALI_CTL_90_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_90__TPDEX_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_90__TPDEX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_90__TPDEX_F2_WIDTH 16U +#define LPDDR4__TPDEX_F2__REG DENALI_CTL_90 +#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_90__TPDEX_F2 + +#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH 8U +#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90 +#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0 + +#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH 8U +#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90 +#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1 + +#define LPDDR4__DENALI_CTL_91_READ_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_CTL_91__TMRRI_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_91__TMRRI_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_91__TMRRI_F2_WIDTH 8U +#define LPDDR4__TMRRI_F2__REG DENALI_CTL_91 +#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_91__TMRRI_F2 + +#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_91__TCKELCS_F0_WIDTH 5U +#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_91 +#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F0 + +#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH 5U +#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91 +#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0 + +#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH 5U +#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91 +#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0 + +#define LPDDR4__DENALI_CTL_92_READ_MASK 0x1F1F1F0FU +#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x1F1F1F0FU +#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_92__TZQCKE_F0_WIDTH 4U +#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_92 +#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F0 + +#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_92__TCKELCS_F1_WIDTH 5U +#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_92 +#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F1 + +#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH 5U +#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92 +#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1 + +#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH 5U +#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92 +#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1 + +#define LPDDR4__DENALI_CTL_93_READ_MASK 0x1F1F1F0FU +#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0x1F1F1F0FU +#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_93__TZQCKE_F1_WIDTH 4U +#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_93 +#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F1 + +#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_93__TCKELCS_F2_WIDTH 5U +#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_93 +#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKELCS_F2 + +#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH 5U +#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93 +#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2 + +#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH 5U +#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93 +#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2 + +#define LPDDR4__DENALI_CTL_94_READ_MASK 0x1F011F0FU +#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0x1F011F0FU +#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_94__TZQCKE_F2_WIDTH 4U +#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_94 +#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_94__TZQCKE_F2 + +#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F0_WIDTH 5U +#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_94 +#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F0 + +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94 +#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0 + +#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH 5U +#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94 +#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1 + +#define LPDDR4__DENALI_CTL_95_READ_MASK 0x00011F01U +#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0x00011F01U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_95 +#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F1 + +#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_95__TCSCKE_F2_WIDTH 5U +#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_95 +#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_95__TCSCKE_F2 + +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET 0U +#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95 +#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2 + +#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_96__TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_96__TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_96__TXSR_F0_WIDTH 16U +#define LPDDR4__TXSR_F0__REG DENALI_CTL_96 +#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_96__TXSR_F0 + +#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH 16U +#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96 +#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0 + +#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_97__TXSR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_97__TXSR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_97__TXSR_F1_WIDTH 16U +#define LPDDR4__TXSR_F1__REG DENALI_CTL_97 +#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_97__TXSR_F1 + +#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH 16U +#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97 +#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1 + +#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_98__TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_98__TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_98__TXSR_F2_WIDTH 16U +#define LPDDR4__TXSR_F2__REG DENALI_CTL_98 +#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_98__TXSR_F2 + +#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH 16U +#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98 +#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2 + +#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_99__TXPR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_99__TXPR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_99__TXPR_F0_WIDTH 16U +#define LPDDR4__TXPR_F0__REG DENALI_CTL_99 +#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_99__TXPR_F0 + +#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH 16U +#define LPDDR4__TXPR_F1__REG DENALI_CTL_99 +#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1 + +#define LPDDR4__DENALI_CTL_100_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_100__TXPR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_100__TXPR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_100__TXPR_F2_WIDTH 16U +#define LPDDR4__TXPR_F2__REG DENALI_CTL_100 +#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_100__TXPR_F2 + +#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH 8U +#define LPDDR4__TSR_F0__REG DENALI_CTL_100 +#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0 + +#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH 3U +#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100 +#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0 + +#define LPDDR4__DENALI_CTL_101_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_101__TCSCKEH_F0_WIDTH 5U +#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_101 +#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_101__TCSCKEH_F0 + +#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_101__TCKELCMD_F0_WIDTH 5U +#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_101 +#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELCMD_F0 + +#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH 5U +#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101 +#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0 + +#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH 5U +#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101 +#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0 + +#define LPDDR4__DENALI_CTL_102_READ_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0x1F07FF1FU +#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_102__TCKELPD_F0_WIDTH 5U +#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_102 +#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_102__TCKELPD_F0 + +#define LPDDR4__DENALI_CTL_102__TSR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_102__TSR_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_102__TSR_F1_WIDTH 8U +#define LPDDR4__TSR_F1__REG DENALI_CTL_102 +#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_102__TSR_F1 + +#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH 3U +#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102 +#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1 + +#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH 5U +#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102 +#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1 + +#define LPDDR4__DENALI_CTL_103_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_103__TCKELCMD_F1_WIDTH 5U +#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_103 +#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELCMD_F1 + +#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_103__TCKEHCMD_F1_WIDTH 5U +#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_103 +#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_103__TCKEHCMD_F1 + +#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH 5U +#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103 +#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1 + +#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH 5U +#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103 +#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1 + +#define LPDDR4__DENALI_CTL_104_READ_MASK 0x1F1F07FFU +#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0x1F1F07FFU +#define LPDDR4__DENALI_CTL_104__TSR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_104__TSR_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_104__TSR_F2_WIDTH 8U +#define LPDDR4__TSR_F2__REG DENALI_CTL_104 +#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_104__TSR_F2 + +#define LPDDR4__DENALI_CTL_104__TESCKE_F2_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_104__TESCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_104__TESCKE_F2_WIDTH 3U +#define LPDDR4__TESCKE_F2__REG DENALI_CTL_104 +#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_104__TESCKE_F2 + +#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH 5U +#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104 +#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2 + +#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH 5U +#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104 +#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2 + +#define LPDDR4__DENALI_CTL_105_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_105__TCKEHCMD_F2_WIDTH 5U +#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_105 +#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_105__TCKEHCMD_F2 + +#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_105__TCKCKEL_F2_WIDTH 5U +#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_105 +#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_105__TCKCKEL_F2 + +#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH 5U +#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105 +#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2 + +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH 5U +#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105 +#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0 + +#define LPDDR4__DENALI_CTL_106_READ_MASK 0x01011F1FU +#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0x01011F1FU +#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_106__TCMDCKE_F1_WIDTH 5U +#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_106 +#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_106__TCMDCKE_F1 + +#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_106__TCMDCKE_F2_WIDTH 5U +#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_106 +#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_106__TCMDCKE_F2 + +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106 +#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT 24U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET 0U +#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106 +#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH + +#define LPDDR4__DENALI_CTL_107_READ_MASK 0x7F000701U +#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x7F000701U +#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_SHIFT 0U +#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WIDTH 1U +#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WOCLR 0U +#define LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH_WOSET 0U +#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_107 +#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_107__ENABLE_QUICK_SREFRESH + +#define LPDDR4__DENALI_CTL_107__CKE_DELAY_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_107__CKE_DELAY_SHIFT 8U +#define LPDDR4__DENALI_CTL_107__CKE_DELAY_WIDTH 3U +#define LPDDR4__CKE_DELAY__REG DENALI_CTL_107 +#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_107__CKE_DELAY + +#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT 16U +#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH 5U +#define LPDDR4__DFS_CMD__REG DENALI_CTL_107 +#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD + +#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH 7U +#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107 +#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS + +#define LPDDR4__DENALI_CTL_108_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_108__DFS_ZQ_EN_WOSET 0U +#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_108 +#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_108__DFS_ZQ_EN + +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_109 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109 +#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFF070707U +#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFF070707U +#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_SHIFT 0U +#define LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG_WIDTH 3U +#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_110 +#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_110__ZQ_STATUS_LOG + +#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_SHIFT 8U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED3_WIDTH 3U +#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED3 + +#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT 16U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH 3U +#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4 + +#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT 24U +#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH 8U +#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110 +#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5 + +#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_SHIFT 0U +#define LPDDR4__DENALI_CTL_111__MC_RESERVED6_WIDTH 8U +#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_111 +#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_111__MC_RESERVED6 + +#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_SHIFT 8U +#define LPDDR4__DENALI_CTL_111__MC_RESERVED7_WIDTH 8U +#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_111 +#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_111__MC_RESERVED7 + +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_112 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_114_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_114 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_115_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_115 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_116 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_116__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116 +#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_117 +#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117 +#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118 +#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118 +#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119 +#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0 + +#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_121_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_122_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_123_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_124_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_125_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125 +#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0 + +#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126 +#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1 + +#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_128_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_129_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_130_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_131_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_132_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132 +#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1 + +#define LPDDR4__DENALI_CTL_133_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133 +#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2 + +#define LPDDR4__DENALI_CTL_134_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_135_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_136_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_137_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137 +#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138 +#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_139_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH 20U +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139 +#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2 + +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT 24U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH 1U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR 0U +#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET 0U +#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139 +#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF + +#define LPDDR4__DENALI_CTL_140_READ_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x00010103U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140 +#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140 +#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1 + +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140 +#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE + +#define LPDDR4__DENALI_CTL_141_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_142_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_143_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_144_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_145_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_146_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_147_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147 +#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_148_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148 +#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 24U +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149 +#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT 24U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET 0U +#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149 +#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL + +#define LPDDR4__DENALI_CTL_150_READ_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT 0U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH 3U +#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150 +#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND + +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT 8U +#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH 8U +#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150 +#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM + +#define LPDDR4__DENALI_CTL_151_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH 17U +#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151 +#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA + +#define LPDDR4__DENALI_CTL_152_READ_MASK 0x0F03FFFFU +#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0x0F03FFFFU +#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK 0x0003FFFFU +#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH 18U +#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152 +#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS + +#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT 24U +#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH 4U +#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152 +#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS + +#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT 0U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH 1U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR 0U +#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET 0U +#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153 +#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS + +#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH 32U +#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154 +#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0 + +#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH 32U +#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155 +#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1 + +#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_156__PPR_DATA_2_WIDTH 32U +#define LPDDR4__PPR_DATA_2__REG DENALI_CTL_156 +#define LPDDR4__PPR_DATA_2__FLD LPDDR4__DENALI_CTL_156__PPR_DATA_2 + +#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_157__PPR_DATA_3_WIDTH 32U +#define LPDDR4__PPR_DATA_3__REG DENALI_CTL_157 +#define LPDDR4__PPR_DATA_3__FLD LPDDR4__DENALI_CTL_157__PPR_DATA_3 + +#define LPDDR4__DENALI_CTL_158_READ_MASK 0xFFFF0103U +#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0xFFFF0103U +#define LPDDR4__DENALI_CTL_158__PPR_STATUS_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_158__PPR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_158__PPR_STATUS_WIDTH 2U +#define LPDDR4__PPR_STATUS__REG DENALI_CTL_158 +#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_158__PPR_STATUS + +#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_SHIFT 8U +#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WIDTH 1U +#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WOCLR 0U +#define LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL_WOSET 0U +#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_158 +#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_158__FM_OVRIDE_CONTROL + +#define LPDDR4__DENALI_CTL_158__CKSRE_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_158__CKSRE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_158__CKSRE_F0_WIDTH 8U +#define LPDDR4__CKSRE_F0__REG DENALI_CTL_158 +#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_158__CKSRE_F0 + +#define LPDDR4__DENALI_CTL_158__CKSRX_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_158__CKSRX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_158__CKSRX_F0_WIDTH 8U +#define LPDDR4__CKSRX_F0__REG DENALI_CTL_158 +#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_158__CKSRX_F0 + +#define LPDDR4__DENALI_CTL_159_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_159__CKSRE_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_159__CKSRE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_159__CKSRE_F1_WIDTH 8U +#define LPDDR4__CKSRE_F1__REG DENALI_CTL_159 +#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_159__CKSRE_F1 + +#define LPDDR4__DENALI_CTL_159__CKSRX_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_159__CKSRX_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_159__CKSRX_F1_WIDTH 8U +#define LPDDR4__CKSRX_F1__REG DENALI_CTL_159 +#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_159__CKSRX_F1 + +#define LPDDR4__DENALI_CTL_159__CKSRE_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_159__CKSRE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_159__CKSRE_F2_WIDTH 8U +#define LPDDR4__CKSRE_F2__REG DENALI_CTL_159 +#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_159__CKSRE_F2 + +#define LPDDR4__DENALI_CTL_159__CKSRX_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_159__CKSRX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_159__CKSRX_F2_WIDTH 8U +#define LPDDR4__CKSRX_F2__REG DENALI_CTL_159 +#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_159__CKSRX_F2 + +#define LPDDR4__DENALI_CTL_160_READ_MASK 0x0F0F0003U +#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x0F0F0003U +#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE_WIDTH 2U +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_160 +#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_160__LOWPOWER_REFRESH_ENABLE + +#define LPDDR4__DENALI_CTL_160__LP_CMD_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_160__LP_CMD_SHIFT 8U +#define LPDDR4__DENALI_CTL_160__LP_CMD_WIDTH 7U +#define LPDDR4__LP_CMD__REG DENALI_CTL_160 +#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_160__LP_CMD + +#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_160 +#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_160 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SR_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_161_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_161 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_161 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_161 +#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_161 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_161__LPI_SRPD_SHORT_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_162_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_162 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_162 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_162 +#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F0 + +#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_162 +#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_IDLE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_163 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_163 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_163 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_163 +#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_163__LPI_PD_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_164_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_164 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_164 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_164 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_164 +#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_164__LPI_TIMER_WAKEUP_F1 + +#define LPDDR4__DENALI_CTL_165_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_165 +#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_IDLE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_165 +#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_165 +#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_165 +#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_166_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_166 +#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_PD_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_166 +#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_SHORT_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_166 +#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_166 +#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_166__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_167_READ_MASK 0x00013F0FU +#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x00013F0FU +#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2_WIDTH 4U +#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_167 +#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_167__LPI_TIMER_WAKEUP_F2 + +#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN_WIDTH 6U +#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_167 +#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_167__LPI_WAKEUP_EN + +#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN_WOSET 0U +#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_167 +#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_167__LPI_CTRL_REQ_EN + +#define LPDDR4__DENALI_CTL_168_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT_WIDTH 12U +#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_168 +#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_168__LPI_TIMER_COUNT + +#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_SHIFT 16U +#define LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT_WIDTH 12U +#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_168 +#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_168__LPI_WAKEUP_TIMEOUT + +#define LPDDR4__DENALI_CTL_169_READ_MASK 0x0F0F7F07U +#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x0F0F7F07U +#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_SHIFT 0U +#define LPDDR4__DENALI_CTL_169__TDFI_LP_RESP_WIDTH 3U +#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_169 +#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_169__TDFI_LP_RESP + +#define LPDDR4__DENALI_CTL_169__LP_STATE_MASK 0x00007F00U +#define LPDDR4__DENALI_CTL_169__LP_STATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_169__LP_STATE_WIDTH 7U +#define LPDDR4__LP_STATE__REG DENALI_CTL_169 +#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_169__LP_STATE + +#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_169 +#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_ENTRY_EN + +#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN_WIDTH 4U +#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_169 +#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_EXIT_EN + +#define LPDDR4__DENALI_CTL_170_READ_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x000FFF07U +#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN_WIDTH 3U +#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_170 +#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_170__LP_AUTO_MEM_GATE_EN + +#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_170 +#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_170__LP_AUTO_PD_IDLE + +#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF0FFFU +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_171 +#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_SHORT_IDLE + +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_171 +#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_IDLE + +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_171 +#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_171__LP_AUTO_SR_LONG_MC_GATE_IDLE + +#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__HW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173 +#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__HW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__LPC_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174 +#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__LPC_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_175_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_175 +#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_CTRLUPD_EN + +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_175 +#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_PHYUPD_EN + +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN_WOSET 0U +#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_175 +#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_PHYMSTR_EN + +#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN_WOSET 0U +#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_175 +#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_175__LPC_SR_EXIT_CMD_EN + +#define LPDDR4__DENALI_CTL_176_READ_MASK 0x0101FF01U +#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0x0101FF01U +#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN_WOSET 0U +#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_176 +#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_176__LPC_SR_ZQ_EN + +#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_MASK 0x0001FF00U +#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_SHIFT 8U +#define LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY_WIDTH 9U +#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_176 +#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_176__PWRDN_SHIFT_DELAY + +#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_176__DFS_ENABLE_WOSET 0U +#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_176 +#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_176__DFS_ENABLE + +#define LPDDR4__DENALI_CTL_177_READ_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0x00000107U +#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_SHIFT 0U +#define LPDDR4__DENALI_CTL_177__DFS_DLL_OFF_WIDTH 3U +#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_177 +#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_177__DFS_DLL_OFF + +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN_WOSET 0U +#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_177 +#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_EN + +#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U +#define LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_178 +#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_178__DFS_PHY_REG_WRITE_ADDR + +#define LPDDR4__DENALI_CTL_179_READ_MASK 0x03FFFF0FU +#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0x03FFFF0FU +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_SHIFT 0U +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK_WIDTH 4U +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_179 +#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_MASK + +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_179 +#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_WAIT + +#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_SHIFT 24U +#define LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY_WIDTH 2U +#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_179 +#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_179__CURRENT_REG_COPY + +#define LPDDR4__DENALI_CTL_180_READ_MASK 0x00000303U +#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0x00000303U +#define LPDDR4__DENALI_CTL_180__INIT_FREQ_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_180__INIT_FREQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_180__INIT_FREQ_WIDTH 2U +#define LPDDR4__INIT_FREQ__REG DENALI_CTL_180 +#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_180__INIT_FREQ + +#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_SHIFT 8U +#define LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ_WIDTH 2U +#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_180 +#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_180__DFIBUS_BOOT_FREQ + +#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_181 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F0 + +#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_182 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_182__DFS_PHY_REG_WRITE_DATA_F1 + +#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_183 +#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_183__DFS_PHY_REG_WRITE_DATA_F2 + +#define LPDDR4__DENALI_CTL_184_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0_WIDTH 24U +#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_184 +#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_CTL_185_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0_WIDTH 24U +#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_185 +#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_CTL_186_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1_WIDTH 24U +#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_186 +#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_CTL_187_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1_WIDTH 24U +#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_187 +#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_CTL_188_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2_WIDTH 24U +#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_188 +#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_188__TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_CTL_189_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2_WIDTH 24U +#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_189 +#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_189__TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_CTL_190_READ_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_MASK 0x07FFFFFFU +#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_CTL_190__WRITE_MODEREG_WIDTH 27U +#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_190 +#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_190__WRITE_MODEREG + +#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_191__MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_191__MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_CTL_191__MRW_STATUS_WIDTH 8U +#define LPDDR4__MRW_STATUS__REG DENALI_CTL_191 +#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_191__MRW_STATUS + +#define LPDDR4__DENALI_CTL_191__READ_MODEREG_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_191__READ_MODEREG_SHIFT 8U +#define LPDDR4__DENALI_CTL_191__READ_MODEREG_WIDTH 17U +#define LPDDR4__READ_MODEREG__REG DENALI_CTL_191 +#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_191__READ_MODEREG + +#define LPDDR4__DENALI_CTL_192_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0_WIDTH 32U +#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_192 +#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_192__PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_CTL_193_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1_WIDTH 8U +#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_193 +#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_193__PERIPHERAL_MRR_DATA_1 + +#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0_WIDTH 16U +#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_193 +#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_193__AUTO_TEMPCHK_VAL_0 + +#define LPDDR4__DENALI_CTL_194_READ_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x0301FFFFU +#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1_WIDTH 16U +#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_194 +#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_194__AUTO_TEMPCHK_VAL_1 + +#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_SHIFT 16U +#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WIDTH 1U +#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WOCLR 0U +#define LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG_WOSET 0U +#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_194 +#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_194__DISABLE_UPDATE_TVRCG + +#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_SHIFT 24U +#define LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC_WIDTH 2U +#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_194 +#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_194__MRW_DFS_UPDATE_FRC + +#define LPDDR4__DENALI_CTL_195_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_195 +#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F0 + +#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_195 +#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F0 + +#define LPDDR4__DENALI_CTL_196_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_196__TFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_196__TFC_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_196__TFC_F0_WIDTH 10U +#define LPDDR4__TFC_F0__REG DENALI_CTL_196 +#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_196__TFC_F0 + +#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_196__TCKFSPE_F0_WIDTH 5U +#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_196 +#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F0 + +#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_196__TCKFSPX_F0_WIDTH 5U +#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_196 +#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F0 + +#define LPDDR4__DENALI_CTL_197_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F0_WIDTH 20U +#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_197 +#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F0 + +#define LPDDR4__DENALI_CTL_198_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_198 +#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F1 + +#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_198 +#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F1 + +#define LPDDR4__DENALI_CTL_199_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_199__TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_199__TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_199__TFC_F1_WIDTH 10U +#define LPDDR4__TFC_F1__REG DENALI_CTL_199 +#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_199__TFC_F1 + +#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_199__TCKFSPE_F1_WIDTH 5U +#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_199 +#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F1 + +#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_199__TCKFSPX_F1_WIDTH 5U +#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_199 +#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F1 + +#define LPDDR4__DENALI_CTL_200_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F1_WIDTH 20U +#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_200 +#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F1 + +#define LPDDR4__DENALI_CTL_201_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_201 +#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_201__TVRCG_ENABLE_F2 + +#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2_WIDTH 10U +#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_201 +#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_201__TVRCG_DISABLE_F2 + +#define LPDDR4__DENALI_CTL_202_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_CTL_202__TFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_CTL_202__TFC_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_202__TFC_F2_WIDTH 10U +#define LPDDR4__TFC_F2__REG DENALI_CTL_202 +#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_202__TFC_F2 + +#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_202__TCKFSPE_F2_WIDTH 5U +#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_202 +#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_202__TCKFSPE_F2 + +#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_202__TCKFSPX_F2_WIDTH 5U +#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_202 +#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_202__TCKFSPX_F2 + +#define LPDDR4__DENALI_CTL_203_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_203__TVREF_LONG_F2_WIDTH 20U +#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_203 +#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_203__TVREF_LONG_F2 + +#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_204 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_204 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_204__MRR_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_205_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_205 +#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_205__MRR_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_205 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_205__MRW_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_206_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_206 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_206 +#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_206__MRW_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_207_READ_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x01FFFF01U +#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_SHIFT 0U +#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WIDTH 1U +#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WOCLR 0U +#define LPDDR4__DENALI_CTL_207__MR4_DLL_RST_WOSET 0U +#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_207 +#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_207__MR4_DLL_RST + +#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_207 +#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_208_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_208 +#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_209_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_209 +#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_210_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_210 +#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_211 +#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_212_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_212 +#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_213_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_213 +#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_214_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_214 +#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_215 +#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_216_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_216 +#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_217_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_217 +#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_218_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_218 +#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_219_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_219 +#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_220_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_220 +#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_221_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_221 +#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_222_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_222 +#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_222__MR0_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_223_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_223 +#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_223__MR1_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_224_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_224 +#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_224__MR2_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_225_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0_WIDTH 17U +#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_225 +#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_225__MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_CTL_226_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1_WIDTH 17U +#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_226 +#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_226__MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_CTL_227_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_227 +#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_228_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_228 +#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_229_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_229 +#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_230_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_230 +#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_230__MR3_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_231_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_231 +#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_231__MR3_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_232_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_232 +#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_232__MR3_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_233_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_233 +#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_234_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_234 +#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_235_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_235 +#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_236_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_236 +#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_236__MR4_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_237_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_237 +#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_237__MR4_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_238_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_238 +#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_238__MR4_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_239_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_239 +#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_240_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_240 +#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_241_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_241 +#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_242 +#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_242__MR5_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_243_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_243 +#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_243__MR5_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_244_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_244 +#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_244__MR5_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_245_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_245 +#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_246_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_246 +#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_247_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_247 +#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_248_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_248 +#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_248__MR6_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_249_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_249 +#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_249__MR6_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_250 +#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_250__MR6_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_250__MR8_DATA_0_WIDTH 8U +#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_250 +#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_250__MR8_DATA_0 + +#define LPDDR4__DENALI_CTL_251_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_251__MR8_DATA_1_WIDTH 8U +#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_251 +#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_251__MR8_DATA_1 + +#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_251 +#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_252_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_252 +#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_253_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_253 +#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_254_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_254 +#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR10_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_255 +#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_255__MR10_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_256_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_256 +#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_256__MR10_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_256 +#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_256__MR11_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_257_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_257 +#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_257 +#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_257 +#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_257 +#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_257__MR11_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_258_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_258 +#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_258__MR11_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_258 +#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_259_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_259 +#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_260 +#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_261_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_261 +#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_261__MR12_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_262 +#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_262__MR12_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_263 +#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_263__MR12_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_264__MR13_DATA_0_WIDTH 17U +#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_264 +#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_264__MR13_DATA_0 + +#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_265__MR13_DATA_1_WIDTH 17U +#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_265 +#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_265__MR13_DATA_1 + +#define LPDDR4__DENALI_CTL_266_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_266 +#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_267_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_267 +#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_268_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_268 +#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_269_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_269 +#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_269__MR14_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_270 +#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_270__MR14_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_271 +#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_271__MR14_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_271__MR16_DATA_0_WIDTH 8U +#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_271 +#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_271__MR16_DATA_0 + +#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_272__MR16_DATA_1_WIDTH 8U +#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_272 +#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_272__MR16_DATA_1 + +#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_272__MR17_DATA_0_WIDTH 8U +#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_272 +#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_272__MR17_DATA_0 + +#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_272__MR17_DATA_1_WIDTH 8U +#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_272 +#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_272__MR17_DATA_1 + +#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_272__MR20_DATA_0_WIDTH 8U +#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_272 +#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_272__MR20_DATA_0 + +#define LPDDR4__DENALI_CTL_273_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_273__MR20_DATA_1_WIDTH 8U +#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_273 +#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_273__MR20_DATA_1 + +#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0_WIDTH 17U +#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_273 +#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_0 + +#define LPDDR4__DENALI_CTL_274_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0_WIDTH 17U +#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_274 +#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_0 + +#define LPDDR4__DENALI_CTL_275_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0_WIDTH 17U +#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_275 +#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_0 + +#define LPDDR4__DENALI_CTL_276_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1_WIDTH 17U +#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_276 +#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_276__MR22_DATA_F0_1 + +#define LPDDR4__DENALI_CTL_277_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1_WIDTH 17U +#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_277 +#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_277__MR22_DATA_F1_1 + +#define LPDDR4__DENALI_CTL_278_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1_WIDTH 17U +#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_278 +#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_278__MR22_DATA_F2_1 + +#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_279__MR23_DATA_MASK 0x0001FFFFU +#define LPDDR4__DENALI_CTL_279__MR23_DATA_SHIFT 0U +#define LPDDR4__DENALI_CTL_279__MR23_DATA_WIDTH 17U +#define LPDDR4__MR23_DATA__REG DENALI_CTL_279 +#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_279__MR23_DATA + +#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_279 +#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_279__MR_FSP_DATA_VALID_F0 + +#define LPDDR4__DENALI_CTL_280_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_280 +#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F1 + +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2_WOSET 0U +#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_280 +#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_280__MR_FSP_DATA_VALID_F2 + +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_SHIFT 16U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE_WOSET 0U +#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_280 +#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_ACTIVE + +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_SHIFT 24U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE_WOSET 0U +#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_280 +#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_280__DFS_FSP_INSYNC_INACTIVE + +#define LPDDR4__DENALI_CTL_281_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_SHIFT 0U +#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW_WOSET 0U +#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_281 +#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_281__FSP_PHY_UPDATE_MRW + +#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_SHIFT 8U +#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP_WOSET 0U +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_281 +#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_281__DFS_ALWAYS_WRITE_FSP + +#define LPDDR4__DENALI_CTL_281__FSP_STATUS_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_281__FSP_STATUS_SHIFT 16U +#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__FSP_STATUS_WOSET 0U +#define LPDDR4__FSP_STATUS__REG DENALI_CTL_281 +#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_281__FSP_STATUS + +#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_SHIFT 24U +#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT_WOSET 0U +#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_281 +#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_281__FSP_OP_CURRENT + +#define LPDDR4__DENALI_CTL_282_READ_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_SHIFT 0U +#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT_WOSET 0U +#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_282 +#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_282__FSP_WR_CURRENT + +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_SHIFT 8U +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID_WOSET 0U +#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_282 +#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_282__FSP0_FRC_VALID + +#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_SHIFT 16U +#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID_WOSET 0U +#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_282 +#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_282__FSP1_FRC_VALID + +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_SHIFT 24U +#define LPDDR4__DENALI_CTL_282__FSP0_FRC_WIDTH 2U +#define LPDDR4__FSP0_FRC__REG DENALI_CTL_282 +#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_282__FSP0_FRC + +#define LPDDR4__DENALI_CTL_283_READ_MASK 0x3F030003U +#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x3F030003U +#define LPDDR4__DENALI_CTL_283__FSP1_FRC_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_283__FSP1_FRC_SHIFT 0U +#define LPDDR4__DENALI_CTL_283__FSP1_FRC_WIDTH 2U +#define LPDDR4__FSP1_FRC__REG DENALI_CTL_283 +#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_283__FSP1_FRC + +#define LPDDR4__DENALI_CTL_283__BIST_GO_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_283__BIST_GO_SHIFT 8U +#define LPDDR4__DENALI_CTL_283__BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_CTL_283__BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_CTL_283__BIST_GO_WOSET 0U +#define LPDDR4__BIST_GO__REG DENALI_CTL_283 +#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_283__BIST_GO + +#define LPDDR4__DENALI_CTL_283__BIST_RESULT_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_283__BIST_RESULT_SHIFT 16U +#define LPDDR4__DENALI_CTL_283__BIST_RESULT_WIDTH 2U +#define LPDDR4__BIST_RESULT__REG DENALI_CTL_283 +#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_283__BIST_RESULT + +#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_SHIFT 24U +#define LPDDR4__DENALI_CTL_283__ADDR_SPACE_WIDTH 6U +#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_283 +#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_283__ADDR_SPACE + +#define LPDDR4__DENALI_CTL_284_READ_MASK 0x00000101U +#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_SHIFT 0U +#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_284 +#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_CHECK + +#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_SHIFT 8U +#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_284 +#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_284__BIST_ADDR_CHECK + +#define LPDDR4__DENALI_CTL_285_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_285 +#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_285__BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_CTL_286_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1_WIDTH 3U +#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_286 +#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_286__BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_CTL_287_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_287 +#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_MASK_0 + +#define LPDDR4__DENALI_CTL_288_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1_WIDTH 32U +#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_288 +#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_288__BIST_DATA_MASK_1 + +#define LPDDR4__DENALI_CTL_289_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_289__BIST_TEST_MODE_WIDTH 3U +#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_289 +#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_289__BIST_TEST_MODE + +#define LPDDR4__DENALI_CTL_290_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_290 +#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_290__BIST_DATA_PATTERN_0 + +#define LPDDR4__DENALI_CTL_291_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_291 +#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_291__BIST_DATA_PATTERN_1 + +#define LPDDR4__DENALI_CTL_292_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_292 +#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_292__BIST_DATA_PATTERN_2 + +#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3_WIDTH 32U +#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_293 +#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_293__BIST_DATA_PATTERN_3 + +#define LPDDR4__DENALI_CTL_294_READ_MASK 0x000FFF01U +#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x000FFF01U +#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_SHIFT 0U +#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_294__BIST_RET_STATE_WOSET 0U +#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_294 +#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_294__BIST_RET_STATE + +#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_SHIFT 8U +#define LPDDR4__DENALI_CTL_294__BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_294 +#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_294__BIST_ERR_STOP + +#define LPDDR4__DENALI_CTL_295_READ_MASK 0x1F000FFFU +#define LPDDR4__DENALI_CTL_295_WRITE_MASK 0x1F000FFFU +#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_295 +#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_295__BIST_ERR_COUNT + +#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT_WOSET 0U +#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_295 +#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_295__BIST_RET_STATE_EXIT + +#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_SHIFT 24U +#define LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_295 +#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_295__LONG_COUNT_MASK + +#define LPDDR4__DENALI_CTL_296_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_296_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_SHIFT 0U +#define LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_296 +#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_296__AREF_NORM_THRESHOLD + +#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD_WIDTH 5U +#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_296 +#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_296__AREF_HIGH_THRESHOLD + +#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_SHIFT 16U +#define LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT_WIDTH 5U +#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_296 +#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_296__AREF_MAX_DEFICIT + +#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT_WIDTH 5U +#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_296 +#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_296__AREF_MAX_CREDIT + +#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI_WIDTH 4U +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_297 +#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_297__AREF_CMD_MAX_PER_TREFI + +#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_SHIFT 8U +#define LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD_WIDTH 3U +#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_297 +#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_297__ZQCS_OPT_THRESHOLD + +#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_297 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_297__ZQ_CALSTART_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_298_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_298 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_298 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_298__ZQ_CALLATCH_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_299 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_NORM_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_299 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_HIGH_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_300_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_300 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_300 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_300__ZQ_CALLATCH_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_301_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_301 +#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_301__ZQ_CS_TIMEOUT_F0 + +#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_301 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_301__ZQ_PROMOTE_THRESHOLD_F0 + +#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_302 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_302__ZQ_CALSTART_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_302 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_302__ZQ_CALSTART_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_303 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_303 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_303__ZQ_CS_NORM_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_304 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_HIGH_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_304 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_304__ZQ_CALSTART_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_305 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_305__ZQ_CALLATCH_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_305 +#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_305__ZQ_CS_TIMEOUT_F1 + +#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_306 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_306__ZQ_PROMOTE_THRESHOLD_F1 + +#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_306 +#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_306__ZQ_CALSTART_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_307 +#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_307__ZQ_CALSTART_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_307 +#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_307__ZQ_CALLATCH_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_308 +#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_308__ZQ_CS_NORM_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_308 +#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_308__ZQ_CS_HIGH_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_309 +#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_309__ZQ_CALSTART_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_309 +#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_309__ZQ_CALLATCH_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2_WIDTH 16U +#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_310 +#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_310__ZQ_CS_TIMEOUT_F2 + +#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_310 +#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_310__ZQ_PROMOTE_THRESHOLD_F2 + +#define LPDDR4__DENALI_CTL_311_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_SHIFT 0U +#define LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG_WIDTH 8U +#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_311 +#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_311__TIMEOUT_TIMER_LOG + +#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_311__ZQINIT_F0_WIDTH 12U +#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_311 +#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_311__ZQINIT_F0 + +#define LPDDR4__DENALI_CTL_312_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_312__ZQCL_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_312__ZQCL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_312__ZQCL_F0_WIDTH 12U +#define LPDDR4__ZQCL_F0__REG DENALI_CTL_312 +#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_312__ZQCL_F0 + +#define LPDDR4__DENALI_CTL_312__ZQCS_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_312__ZQCS_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_312__ZQCS_F0_WIDTH 12U +#define LPDDR4__ZQCS_F0__REG DENALI_CTL_312 +#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_312__ZQCS_F0 + +#define LPDDR4__DENALI_CTL_313_READ_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x007F0FFFU +#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_313__TZQCAL_F0_WIDTH 12U +#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_313 +#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_313__TZQCAL_F0 + +#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_313__TZQLAT_F0_WIDTH 7U +#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_313 +#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_313__TZQLAT_F0 + +#define LPDDR4__DENALI_CTL_314_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_314__ZQINIT_F1_WIDTH 12U +#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_314 +#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_314__ZQINIT_F1 + +#define LPDDR4__DENALI_CTL_314__ZQCL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_314__ZQCL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_314__ZQCL_F1_WIDTH 12U +#define LPDDR4__ZQCL_F1__REG DENALI_CTL_314 +#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_314__ZQCL_F1 + +#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_315__ZQCS_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_315__ZQCS_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_315__ZQCS_F1_WIDTH 12U +#define LPDDR4__ZQCS_F1__REG DENALI_CTL_315 +#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_315__ZQCS_F1 + +#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_315__TZQCAL_F1_WIDTH 12U +#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_315 +#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_315__TZQCAL_F1 + +#define LPDDR4__DENALI_CTL_316_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_316__TZQLAT_F1_WIDTH 7U +#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_316 +#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_316__TZQLAT_F1 + +#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_316__ZQINIT_F2_WIDTH 12U +#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_316 +#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_316__ZQINIT_F2 + +#define LPDDR4__DENALI_CTL_317_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_317__ZQCL_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_317__ZQCL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_317__ZQCL_F2_WIDTH 12U +#define LPDDR4__ZQCL_F2__REG DENALI_CTL_317 +#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_317__ZQCL_F2 + +#define LPDDR4__DENALI_CTL_317__ZQCS_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_317__ZQCS_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_317__ZQCS_F2_WIDTH 12U +#define LPDDR4__ZQCS_F2__REG DENALI_CTL_317 +#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_317__ZQCS_F2 + +#define LPDDR4__DENALI_CTL_318_READ_MASK 0x037F0FFFU +#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x037F0FFFU +#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_318__TZQCAL_F2_WIDTH 12U +#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_318 +#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_318__TZQCAL_F2 + +#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_318__TZQLAT_F2_WIDTH 7U +#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_318 +#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_318__TZQLAT_F2 + +#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 24U +#define LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_318 +#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_318__ZQ_SW_REQ_START_LATCH_MAP + +#define LPDDR4__DENALI_CTL_319_READ_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x0FFF0100U +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_SHIFT 0U +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_WIDTH 4U +#define LPDDR4__ZQ_REQ__REG DENALI_CTL_319 +#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_319__ZQ_REQ + +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_SHIFT 8U +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_319 +#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_319__ZQ_REQ_PENDING + +#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_319__ZQRESET_F0_WIDTH 12U +#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_319 +#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_319__ZQRESET_F0 + +#define LPDDR4__DENALI_CTL_320_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_320__ZQRESET_F1_WIDTH 12U +#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_320 +#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_320__ZQRESET_F1 + +#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_320__ZQRESET_F2_WIDTH 12U +#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_320 +#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_320__ZQRESET_F2 + +#define LPDDR4__DENALI_CTL_321_READ_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x03030101U +#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_SHIFT 0U +#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_CTL_321__NO_ZQ_INIT_WOSET 0U +#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_321 +#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_321__NO_ZQ_INIT + +#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_SHIFT 8U +#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_CTL_321__ZQCS_ROTATE_WOSET 0U +#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_321 +#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_321__ZQCS_ROTATE + +#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_321 +#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_321__ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_321 +#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_321__ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_CTL_322_READ_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_322 +#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_322__ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1_WIDTH 2U +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_322 +#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_322__ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_322__BANK_DIFF_0_WIDTH 2U +#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_322 +#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_322__BANK_DIFF_0 + +#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_322__BANK_DIFF_1_WIDTH 2U +#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_322 +#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_322__BANK_DIFF_1 + +#define LPDDR4__DENALI_CTL_323_READ_MASK 0x0F0F0707U +#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x0F0F0707U +#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_323__ROW_DIFF_0_WIDTH 3U +#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_323 +#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_323__ROW_DIFF_0 + +#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_323__ROW_DIFF_1_WIDTH 3U +#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_323 +#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_323__ROW_DIFF_1 + +#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_323__COL_DIFF_0_WIDTH 4U +#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_323 +#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_323__COL_DIFF_0 + +#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_SHIFT 24U +#define LPDDR4__DENALI_CTL_323__COL_DIFF_1_WIDTH 4U +#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_323 +#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_323__COL_DIFF_1 + +#define LPDDR4__DENALI_CTL_324_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_324 +#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_324__CS_VAL_LOWER_0 + +#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_SHIFT 16U +#define LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_324 +#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_324__CS_VAL_UPPER_0 + +#define LPDDR4__DENALI_CTL_325_READ_MASK 0x00FFFF03U +#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x00FFFF03U +#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_325__ROW_START_VAL_0_WIDTH 2U +#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_325 +#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_325__ROW_START_VAL_0 + +#define LPDDR4__DENALI_CTL_325__CS_MSK_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_325__CS_MSK_0_SHIFT 8U +#define LPDDR4__DENALI_CTL_325__CS_MSK_0_WIDTH 16U +#define LPDDR4__CS_MSK_0__REG DENALI_CTL_325 +#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_325__CS_MSK_0 + +#define LPDDR4__DENALI_CTL_326_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1_WIDTH 16U +#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_326 +#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_326__CS_VAL_LOWER_1 + +#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_SHIFT 16U +#define LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1_WIDTH 16U +#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_326 +#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_326__CS_VAL_UPPER_1 + +#define LPDDR4__DENALI_CTL_327_READ_MASK 0x03FFFF03U +#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x03FFFF03U +#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_327__ROW_START_VAL_1_WIDTH 2U +#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_327 +#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_327__ROW_START_VAL_1 + +#define LPDDR4__DENALI_CTL_327__CS_MSK_1_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_327__CS_MSK_1_SHIFT 8U +#define LPDDR4__DENALI_CTL_327__CS_MSK_1_WIDTH 16U +#define LPDDR4__CS_MSK_1__REG DENALI_CTL_327 +#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_327__CS_MSK_1 + +#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_SHIFT 24U +#define LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2_WIDTH 2U +#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_327 +#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_327__CS_MAP_NON_POW2 + +#define LPDDR4__DENALI_CTL_328_READ_MASK 0x1F011F01U +#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x1F011F01U +#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN_WOSET 0U +#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_328 +#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_328__CS_LOWER_ADDR_EN + +#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_SHIFT 8U +#define LPDDR4__DENALI_CTL_328__MC_RESERVED8_WIDTH 5U +#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_328 +#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_328__MC_RESERVED8 + +#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_SHIFT 16U +#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WIDTH 1U +#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WOCLR 0U +#define LPDDR4__DENALI_CTL_328__MC_RESERVED9_WOSET 0U +#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_328 +#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_328__MC_RESERVED9 + +#define LPDDR4__DENALI_CTL_328__APREBIT_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_328__APREBIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_328__APREBIT_WIDTH 5U +#define LPDDR4__APREBIT__REG DENALI_CTL_328 +#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_328__APREBIT + +#define LPDDR4__DENALI_CTL_329_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_CTL_329__AGE_COUNT_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_329__AGE_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_329__AGE_COUNT_WIDTH 8U +#define LPDDR4__AGE_COUNT__REG DENALI_CTL_329 +#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_329__AGE_COUNT + +#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_SHIFT 8U +#define LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT_WIDTH 8U +#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_329 +#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_329__COMMAND_AGE_COUNT + +#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__ADDR_CMP_EN_WOSET 0U +#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_329 +#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_329__ADDR_CMP_EN + +#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_SHIFT 24U +#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WIDTH 1U +#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WOCLR 0U +#define LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS_WOSET 0U +#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_329 +#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_329__ADDR_COLLISION_MPM_DIS + +#define LPDDR4__DENALI_CTL_330_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN_WOSET 0U +#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_330 +#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_330__BANK_SPLIT_EN + +#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__PLACEMENT_EN_WOSET 0U +#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_330 +#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_330__PLACEMENT_EN + +#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__PRIORITY_EN_WOSET 0U +#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_330 +#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_330__PRIORITY_EN + +#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_330__RW_SAME_EN_WOSET 0U +#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_330 +#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_330__RW_SAME_EN + +#define LPDDR4__DENALI_CTL_331_READ_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN_WOSET 0U +#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_331 +#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_331__RW_SAME_PAGE_EN + +#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__CS_SAME_EN_WOSET 0U +#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_331 +#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_331__CS_SAME_EN + +#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN_WOSET 0U +#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_331 +#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_331__W2R_SPLIT_EN + +#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 24U +#define LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_331 +#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_331__DISABLE_RW_GROUP_W_BNK_CONFLICT + +#define LPDDR4__DENALI_CTL_332_READ_MASK 0x0301011FU +#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0x0301011FU +#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_332 +#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_332__NUM_Q_ENTRIES_ACT_DISABLE + +#define LPDDR4__DENALI_CTL_332__SWAP_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_332__SWAP_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_332__SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_332__SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_332__SWAP_EN_WOSET 0U +#define LPDDR4__SWAP_EN__REG DENALI_CTL_332 +#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_332__SWAP_EN + +#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_SHIFT 16U +#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WIDTH 1U +#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WOCLR 0U +#define LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE_WOSET 0U +#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_332 +#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_332__DISABLE_RD_INTERLEAVE + +#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_SHIFT 24U +#define LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD_WIDTH 2U +#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_332 +#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_332__INHIBIT_DRAM_CMD + +#define LPDDR4__DENALI_CTL_333_READ_MASK 0x07010F03U +#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0x07010F03U +#define LPDDR4__DENALI_CTL_333__CS_MAP_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_333__CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_CTL_333__CS_MAP_WIDTH 2U +#define LPDDR4__CS_MAP__REG DENALI_CTL_333 +#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_333__CS_MAP + +#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_SHIFT 8U +#define LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT_WIDTH 4U +#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_333 +#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_333__BURST_ON_FLY_BIT + +#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_SHIFT 16U +#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WIDTH 1U +#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WOCLR 0U +#define LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION_WOSET 0U +#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_333 +#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_333__MEM_DP_REDUCTION + +#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_SHIFT 24U +#define LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_333 +#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_333__MEMDATA_RATIO_0 + +#define LPDDR4__DENALI_CTL_334_READ_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0x0F0F0F07U +#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1_WIDTH 3U +#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_334 +#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_334__MEMDATA_RATIO_1 + +#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_SHIFT 8U +#define LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_334 +#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE0_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_SHIFT 16U +#define LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_334 +#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE1_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_334 +#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_334__DEVICE2_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_335_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0_WIDTH 4U +#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_335 +#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_335__DEVICE3_BYTE0_CS0 + +#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_335 +#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE0_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_335 +#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE1_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_SHIFT 24U +#define LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_335 +#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_335__DEVICE2_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_336_READ_MASK 0x03011F0FU +#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0x03011F0FU +#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_SHIFT 0U +#define LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1_WIDTH 4U +#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_336 +#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_336__DEVICE3_BYTE0_CS1 + +#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_SHIFT 8U +#define LPDDR4__DENALI_CTL_336__Q_FULLNESS_WIDTH 5U +#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_336 +#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_336__Q_FULLNESS + +#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_SHIFT 16U +#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WIDTH 1U +#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WOCLR 0U +#define LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT_WOSET 0U +#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_336 +#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_336__IN_ORDER_ACCEPT + +#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_SHIFT 24U +#define LPDDR4__DENALI_CTL_336__WR_ORDER_REQ_WIDTH 2U +#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_336 +#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_336__WR_ORDER_REQ + +#define LPDDR4__DENALI_CTL_337_READ_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_SHIFT 0U +#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WIDTH 1U +#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WOCLR 0U +#define LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY_WOSET 0U +#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_337 +#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_337__CONTROLLER_BUSY + +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_SHIFT 8U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WIDTH 1U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WOCLR 0U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_WOSET 0U +#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_337 +#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_REQ + +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_337 +#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE_WOSET 0U +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_337 +#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_337__CTRLUPD_AREF_HP_ENABLE + +#define LPDDR4__DENALI_CTL_338_READ_MASK 0x01030303U +#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0x01030303U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_338 +#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F0 + +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_338 +#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F1 + +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2_WIDTH 2U +#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_338 +#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_338__PREAMBLE_SUPPORT_F2 + +#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_338 +#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_338__RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_CTL_339_READ_MASK 0x001F0101U +#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x001F0101U +#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_SHIFT 0U +#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_339__WR_DBI_EN_WOSET 0U +#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_339 +#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_339__WR_DBI_EN + +#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_SHIFT 8U +#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_339__RD_DBI_EN_WOSET 0U +#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_339 +#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_339__RD_DBI_EN + +#define LPDDR4__DENALI_CTL_339__DFI_ERROR_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_339__DFI_ERROR_SHIFT 16U +#define LPDDR4__DENALI_CTL_339__DFI_ERROR_WIDTH 5U +#define LPDDR4__DFI_ERROR__REG DENALI_CTL_339 +#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_339__DFI_ERROR + +#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_MASK 0x000FFFFFU +#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_SHIFT 0U +#define LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO_WIDTH 20U +#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_340 +#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_340__DFI_ERROR_INFO + +#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_SHIFT 24U +#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WIDTH 1U +#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WOCLR 0U +#define LPDDR4__DENALI_CTL_340__BG_ROTATE_EN_WOSET 0U +#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_340 +#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_340__BG_ROTATE_EN + +#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_SHIFT 0U +#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WIDTH 1U +#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WOCLR 0U +#define LPDDR4__DENALI_CTL_341__MC_RESERVED10_WOSET 0U +#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_341 +#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED10 + +#define LPDDR4__DENALI_CTL_342_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_SHIFT 0U +#define LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER_WIDTH 32U +#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_342 +#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_MASTER + +#define LPDDR4__DENALI_CTL_343_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_SHIFT 0U +#define LPDDR4__DENALI_CTL_343__INT_MASK_MASTER_WIDTH 32U +#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_343 +#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_343__INT_MASK_MASTER + +#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT_WIDTH 32U +#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_344 +#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_STATUS_TIMEOUT + +#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_SHIFT 0U +#define LPDDR4__DENALI_CTL_345__MC_RESERVED11_WIDTH 16U +#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_345 +#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED11 + +#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_SHIFT 16U +#define LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER_WIDTH 16U +#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_345 +#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_STATUS_LOWPOWER + +#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_SHIFT 0U +#define LPDDR4__DENALI_CTL_346__MC_RESERVED12_WIDTH 16U +#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_346 +#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED12 + +#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_SHIFT 16U +#define LPDDR4__DENALI_CTL_346__MC_RESERVED13_WIDTH 16U +#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_346 +#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED13 + +#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_SHIFT 0U +#define LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING_WIDTH 32U +#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_347 +#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_STATUS_TRAINING + +#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_SHIFT 0U +#define LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF_WIDTH 32U +#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_348 +#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_STATUS_USERIF + +#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_SHIFT 0U +#define LPDDR4__DENALI_CTL_349__INT_STATUS_MISC_WIDTH 16U +#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_349 +#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_349__INT_STATUS_MISC + +#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_SHIFT 16U +#define LPDDR4__DENALI_CTL_349__INT_STATUS_BIST_WIDTH 8U +#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_349 +#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_349__INT_STATUS_BIST + +#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_SHIFT 24U +#define LPDDR4__DENALI_CTL_349__MC_RESERVED14_WIDTH 8U +#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_349 +#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED14 + +#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_350__INT_STATUS_DFI_WIDTH 8U +#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_350 +#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_DFI + +#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_SHIFT 8U +#define LPDDR4__DENALI_CTL_350__MC_RESERVED15_WIDTH 8U +#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_350 +#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED15 + +#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ_WIDTH 8U +#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_350 +#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_FREQ + +#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_350__INT_STATUS_INIT_WIDTH 8U +#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_350 +#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_350__INT_STATUS_INIT + +#define LPDDR4__DENALI_CTL_351_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_351__INT_STATUS_MODE_WIDTH 8U +#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_351 +#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_351__INT_STATUS_MODE + +#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY_WIDTH 8U +#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_351 +#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_STATUS_PARITY + +#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT_WIDTH 32U +#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_352 +#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_ACK_TIMEOUT + +#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_SHIFT 0U +#define LPDDR4__DENALI_CTL_353__MC_RESERVED16_WIDTH 16U +#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_353 +#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED16 + +#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_SHIFT 16U +#define LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER_WIDTH 16U +#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_353 +#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_ACK_LOWPOWER + +#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_SHIFT 0U +#define LPDDR4__DENALI_CTL_354__MC_RESERVED17_WIDTH 16U +#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_354 +#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED17 + +#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_SHIFT 16U +#define LPDDR4__DENALI_CTL_354__MC_RESERVED18_WIDTH 16U +#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_354 +#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED18 + +#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_SHIFT 0U +#define LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING_WIDTH 32U +#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_355 +#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_ACK_TRAINING + +#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_SHIFT 0U +#define LPDDR4__DENALI_CTL_356__INT_ACK_USERIF_WIDTH 32U +#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_356 +#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_ACK_USERIF + +#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_SHIFT 0U +#define LPDDR4__DENALI_CTL_357__INT_ACK_MISC_WIDTH 16U +#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_357 +#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_ACK_MISC + +#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_SHIFT 16U +#define LPDDR4__DENALI_CTL_357__INT_ACK_BIST_WIDTH 8U +#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_357 +#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_ACK_BIST + +#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_SHIFT 24U +#define LPDDR4__DENALI_CTL_357__MC_RESERVED19_WIDTH 8U +#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_357 +#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED19 + +#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_358__INT_ACK_DFI_WIDTH 8U +#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_358 +#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_ACK_DFI + +#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_SHIFT 8U +#define LPDDR4__DENALI_CTL_358__MC_RESERVED20_WIDTH 8U +#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_358 +#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED20 + +#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_358__INT_ACK_FREQ_WIDTH 8U +#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_358 +#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_ACK_FREQ + +#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_358__INT_ACK_INIT_WIDTH 8U +#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_358 +#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_ACK_INIT + +#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_359__INT_ACK_MODE_WIDTH 8U +#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_359 +#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_ACK_MODE + +#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_359__INT_ACK_PARITY_WIDTH 8U +#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_359 +#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_ACK_PARITY + +#define LPDDR4__DENALI_CTL_360_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_SHIFT 0U +#define LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT_WIDTH 32U +#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_360 +#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_360__INT_MASK_TIMEOUT + +#define LPDDR4__DENALI_CTL_361_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_SHIFT 0U +#define LPDDR4__DENALI_CTL_361__MC_RESERVED21_WIDTH 16U +#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_361 +#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_361__MC_RESERVED21 + +#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_SHIFT 16U +#define LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER_WIDTH 16U +#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_361 +#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_361__INT_MASK_LOWPOWER + +#define LPDDR4__DENALI_CTL_362_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_SHIFT 0U +#define LPDDR4__DENALI_CTL_362__MC_RESERVED22_WIDTH 16U +#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_362 +#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_362__MC_RESERVED22 + +#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_MASK 0xFFFF0000U +#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_SHIFT 16U +#define LPDDR4__DENALI_CTL_362__MC_RESERVED23_WIDTH 16U +#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_362 +#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_362__MC_RESERVED23 + +#define LPDDR4__DENALI_CTL_363_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_SHIFT 0U +#define LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING_WIDTH 32U +#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_363 +#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_363__INT_MASK_TRAINING + +#define LPDDR4__DENALI_CTL_364_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_SHIFT 0U +#define LPDDR4__DENALI_CTL_364__INT_MASK_USERIF_WIDTH 32U +#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_364 +#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_364__INT_MASK_USERIF + +#define LPDDR4__DENALI_CTL_365_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_SHIFT 0U +#define LPDDR4__DENALI_CTL_365__INT_MASK_MISC_WIDTH 16U +#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_365 +#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_365__INT_MASK_MISC + +#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_SHIFT 16U +#define LPDDR4__DENALI_CTL_365__INT_MASK_BIST_WIDTH 8U +#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_365 +#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_365__INT_MASK_BIST + +#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_SHIFT 24U +#define LPDDR4__DENALI_CTL_365__MC_RESERVED24_WIDTH 8U +#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_365 +#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_365__MC_RESERVED24 + +#define LPDDR4__DENALI_CTL_366_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_SHIFT 0U +#define LPDDR4__DENALI_CTL_366__INT_MASK_DFI_WIDTH 8U +#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_366 +#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_366__INT_MASK_DFI + +#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_SHIFT 8U +#define LPDDR4__DENALI_CTL_366__MC_RESERVED25_WIDTH 8U +#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_366 +#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_366__MC_RESERVED25 + +#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_SHIFT 16U +#define LPDDR4__DENALI_CTL_366__INT_MASK_FREQ_WIDTH 8U +#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_366 +#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_366__INT_MASK_FREQ + +#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_SHIFT 24U +#define LPDDR4__DENALI_CTL_366__INT_MASK_INIT_WIDTH 8U +#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_366 +#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_366__INT_MASK_INIT + +#define LPDDR4__DENALI_CTL_367_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_SHIFT 0U +#define LPDDR4__DENALI_CTL_367__INT_MASK_MODE_WIDTH 8U +#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_367 +#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_367__INT_MASK_MODE + +#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_SHIFT 8U +#define LPDDR4__DENALI_CTL_367__INT_MASK_PARITY_WIDTH 8U +#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_367 +#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_367__INT_MASK_PARITY + +#define LPDDR4__DENALI_CTL_368_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0_WIDTH 32U +#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_368 +#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_368__OUT_OF_RANGE_ADDR_0 + +#define LPDDR4__DENALI_CTL_369_READ_MASK 0x7F0FFF07U +#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x7F0FFF07U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1_WIDTH 3U +#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_369 +#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_ADDR_1 + +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_SHIFT 8U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH_WIDTH 12U +#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_369 +#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_LENGTH + +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_SHIFT 24U +#define LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE_WIDTH 7U +#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_369 +#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_369__OUT_OF_RANGE_TYPE + +#define LPDDR4__DENALI_CTL_370_READ_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U +#define LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_370 +#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_370__OUT_OF_RANGE_SOURCE_ID + +#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_371 +#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_371__BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_372 +#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_372__BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_373 +#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_373__BIST_EXP_DATA_2 + +#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3_WIDTH 32U +#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_374 +#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_374__BIST_EXP_DATA_3 + +#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_375 +#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_375__BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_376 +#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_376__BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_CTL_377_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_377 +#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_377__BIST_FAIL_DATA_2 + +#define LPDDR4__DENALI_CTL_378_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3_WIDTH 32U +#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_378 +#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_378__BIST_FAIL_DATA_3 + +#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_379 +#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_379__BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_CTL_380_READ_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1_WIDTH 3U +#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_380 +#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_380__BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0_WIDTH 32U +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_381 +#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_381__PORT_CMD_ERROR_ADDR_0 + +#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFF033F07U +#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFF033F07U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1_WIDTH 3U +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_382 +#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ADDR_1 + +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_SHIFT 8U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID_WIDTH 6U +#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_382 +#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_ID + +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_SHIFT 16U +#define LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE_WIDTH 2U +#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_382 +#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_382__PORT_CMD_ERROR_TYPE + +#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_382 +#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_382__TODTL_2CMD_F0 + +#define LPDDR4__DENALI_CTL_383_READ_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0x0FFF0F0FU +#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_383__TODTH_WR_F0_WIDTH 4U +#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_383 +#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_383__TODTH_WR_F0 + +#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_383__TODTH_RD_F0_WIDTH 4U +#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_383 +#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_383__TODTH_RD_F0 + +#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_383 +#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_383__TODTL_2CMD_F1 + +#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_383__TODTH_WR_F1_WIDTH 4U +#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_383 +#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_383__TODTH_WR_F1 + +#define LPDDR4__DENALI_CTL_384_READ_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0x0F0FFF0FU +#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_384__TODTH_RD_F1_WIDTH 4U +#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_384 +#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_384__TODTH_RD_F1 + +#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_384 +#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_384__TODTL_2CMD_F2 + +#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_384__TODTH_WR_F2_WIDTH 4U +#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_384 +#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_384__TODTH_WR_F2 + +#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_384__TODTH_RD_F2_WIDTH 4U +#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_384 +#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_384__TODTH_RD_F2 + +#define LPDDR4__DENALI_CTL_385_READ_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F0_WOSET 0U +#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_385 +#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F0 + +#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F1_WOSET 0U +#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_385 +#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F1 + +#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_CTL_385__ODT_EN_F2_WOSET 0U +#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_385 +#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_385__ODT_EN_F2 + +#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U +#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U +#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U +#define LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_385 +#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_385__EN_ODT_ASSERT_EXCEPT_RD + +#define LPDDR4__DENALI_CTL_386_READ_MASK 0x033F3F3FU +#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x033F3F3FU +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_386 +#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_386 +#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_386 +#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_386__WR_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_MASK 0x03000000U +#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_SHIFT 24U +#define LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_386 +#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_386__ODT_RD_MAP_CS0 + +#define LPDDR4__DENALI_CTL_387_READ_MASK 0x3F030303U +#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x3F030303U +#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_SHIFT 0U +#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_387 +#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS0 + +#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_SHIFT 8U +#define LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_387 +#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_387__ODT_RD_MAP_CS1 + +#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_MASK 0x00030000U +#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_SHIFT 16U +#define LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1_WIDTH 2U +#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_387 +#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_387__ODT_WR_MAP_CS1 + +#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_387 +#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_387__RD_TO_ODTH_F0 + +#define LPDDR4__DENALI_CTL_388_READ_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x1F1F3F3FU +#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_388 +#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F1 + +#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_388 +#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_388__RD_TO_ODTH_F2 + +#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_388 +#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F0 + +#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_388 +#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_388__RW2MRW_DLY_F1 + +#define LPDDR4__DENALI_CTL_389_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2_WIDTH 5U +#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_389 +#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_389__RW2MRW_DLY_F2 + +#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_389 +#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__R2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_389 +#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__R2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_389 +#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_389__W2R_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_390_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_390 +#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_390__W2W_DIFFCS_DLY_F0 + +#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_390 +#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__R2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_390 +#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__R2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_390 +#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_390__W2R_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_391_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_391 +#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_391__W2W_DIFFCS_DLY_F1 + +#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_391 +#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__R2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_391 +#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__R2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_391 +#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_391__W2R_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_392_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2_WIDTH 5U +#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_392 +#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_392__W2W_DIFFCS_DLY_F2 + +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_392 +#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F0 + +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_392 +#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F1 + +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2_WIDTH 5U +#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_392 +#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_392__R2W_SAMECS_DLY_F2 + +#define LPDDR4__DENALI_CTL_393_READ_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0x0F1F1F1FU +#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_MASK 0x0000001FU +#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_SHIFT 0U +#define LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_393 +#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__R2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_MASK 0x00001F00U +#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_SHIFT 8U +#define LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_393 +#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__W2R_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_MASK 0x001F0000U +#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY_WIDTH 5U +#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_393 +#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_393__W2W_SAMECS_DLY + +#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_393 +#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_393__TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_CTL_394_READ_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x0F070F07U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_394 +#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F0 + +#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_394 +#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_394 +#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MIN_F1 + +#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_394 +#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_394__TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_CTL_395_READ_MASK 0x07010107U +#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0x07010107U +#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2_WIDTH 3U +#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_395 +#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_395__TDQSCK_MIN_F2 + +#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_395 +#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_395__AXI0_ALL_STROBES_USED_ENABLE + +#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 16U +#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_395 +#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_395__AXI0_FIXED_PORT_PRIORITY_ENABLE + +#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_SHIFT 24U +#define LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_395 +#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_395__AXI0_R_PRIORITY + +#define LPDDR4__DENALI_CTL_396_READ_MASK 0xFF010307U +#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0xFF010307U +#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_SHIFT 0U +#define LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY_WIDTH 3U +#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_396 +#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_396__AXI0_W_PRIORITY + +#define LPDDR4__DENALI_CTL_396__CKE_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_CTL_396__CKE_STATUS_SHIFT 8U +#define LPDDR4__DENALI_CTL_396__CKE_STATUS_WIDTH 2U +#define LPDDR4__CKE_STATUS__REG DENALI_CTL_396 +#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_396__CKE_STATUS + +#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_MASK 0x00010000U +#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_SHIFT 16U +#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WIDTH 1U +#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WOCLR 0U +#define LPDDR4__DENALI_CTL_396__MEM_RST_VALID_WOSET 0U +#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_396 +#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_396__MEM_RST_VALID + +#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_396 +#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_396__TDFI_PHY_RDLAT_F0 + +#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_397 +#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_398 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F0 + +#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_399 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F0 + +#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_400 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F0 + +#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_401 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F0 + +#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_402 +#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F0 + +#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_403 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_CTL_404_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_404 +#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_404 +#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_404 +#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_RDCSLAT_F0 + +#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0_WIDTH 8U +#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_404 +#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_404__TDFI_RDDATA_EN_F0 + +#define LPDDR4__DENALI_CTL_405_READ_MASK 0xFF7FFFFFU +#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0xFF7FFFFFU +#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_405 +#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_WRCSLAT_F0 + +#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_SHIFT 8U +#define LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0_WIDTH 8U +#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_405 +#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_PHY_WRLAT_F0 + +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_SHIFT 16U +#define LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0_WIDTH 7U +#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_405 +#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLMSG_RESP_F0 + +#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_405 +#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_405__TDFI_PHY_RDLAT_F1 + +#define LPDDR4__DENALI_CTL_406_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_406 +#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_406__TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_407 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE0_F1 + +#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_408 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE1_F1 + +#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_409 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE2_F1 + +#define LPDDR4__DENALI_CTL_410_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_410 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_TYPE3_F1 + +#define LPDDR4__DENALI_CTL_411_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_411 +#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_411__TDFI_PHYUPD_RESP_F1 + +#define LPDDR4__DENALI_CTL_412_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_412 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_413 +#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_413 +#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_413 +#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_RDCSLAT_F1 + +#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1_WIDTH 8U +#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_413 +#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_413__TDFI_RDDATA_EN_F1 + +#define LPDDR4__DENALI_CTL_414_READ_MASK 0xFF7FFFFFU +#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0xFF7FFFFFU +#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_414 +#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_WRCSLAT_F1 + +#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1_WIDTH 8U +#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_414 +#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_PHY_WRLAT_F1 + +#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_SHIFT 16U +#define LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1_WIDTH 7U +#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_414 +#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_414__TDFI_CTRLMSG_RESP_F1 + +#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_414 +#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_414__TDFI_PHY_RDLAT_F2 + +#define LPDDR4__DENALI_CTL_415_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_415 +#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_415__TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_416 +#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_416__TDFI_PHYUPD_TYPE0_F2 + +#define LPDDR4__DENALI_CTL_417_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_417 +#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_417__TDFI_PHYUPD_TYPE1_F2 + +#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_418 +#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_418__TDFI_PHYUPD_TYPE2_F2 + +#define LPDDR4__DENALI_CTL_419_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_419 +#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_419__TDFI_PHYUPD_TYPE3_F2 + +#define LPDDR4__DENALI_CTL_420_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2_WIDTH 23U +#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_420 +#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_420__TDFI_PHYUPD_RESP_F2 + +#define LPDDR4__DENALI_CTL_421_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_421 +#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_421__TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_CTL_422_READ_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0xFFFF070FU +#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_422 +#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_422 +#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_422 +#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_RDCSLAT_F2 + +#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2_WIDTH 8U +#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_422 +#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_RDDATA_EN_F2 + +#define LPDDR4__DENALI_CTL_423_READ_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x007FFFFFU +#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_423 +#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_WRCSLAT_F2 + +#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2_WIDTH 8U +#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_423 +#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_PHY_WRLAT_F2 + +#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_SHIFT 16U +#define LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2_WIDTH 7U +#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_423 +#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_423__TDFI_CTRLMSG_RESP_F2 + +#define LPDDR4__DENALI_CTL_424_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_SHIFT 0U +#define LPDDR4__DENALI_CTL_424__DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_424 +#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_424__DLL_RST_DELAY + +#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_SHIFT 16U +#define LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_424 +#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_424__DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_MASK 0x7F000000U +#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS_WIDTH 7U +#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_424 +#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_424__UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_CTL_425_READ_MASK 0x0FFFFF03U +#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0x0FFFFF03U +#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_MASK 0x00000003U +#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE_WIDTH 2U +#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_425 +#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_425__DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_MASK 0x00FFFF00U +#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_SHIFT 8U +#define LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN_WIDTH 16U +#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_425 +#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_425__TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_425 +#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_425__TDFI_DRAM_CLK_DISABLE + +#define LPDDR4__DENALI_CTL_426_READ_MASK 0x01FF070FU +#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0x01FF070FU +#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE_WIDTH 4U +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_426 +#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_426__TDFI_DRAM_CLK_ENABLE + +#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_SHIFT 8U +#define LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT_WIDTH 3U +#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_426 +#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_426__TDFI_PARIN_LAT + +#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_MASK 0x00FF0000U +#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_SHIFT 16U +#define LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY_WIDTH 8U +#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_426 +#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_426__TDFI_WRDATA_DELAY + +#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_MASK 0x01000000U +#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_SHIFT 24U +#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U +#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U +#define LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_426 +#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_426__DISABLE_MEMORY_MASKED_WRITE + +#define LPDDR4__DENALI_CTL_427_READ_MASK 0x07070701U +#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x07070701U +#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_MASK 0x00000001U +#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_SHIFT 0U +#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WIDTH 1U +#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WOCLR 0U +#define LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER_WOSET 0U +#define LPDDR4__MULTI_CHANNEL_ZQ_CAL_MASTER__REG DENALI_CTL_427 +#define LPDDR4__MULTI_CHANNEL_ZQ_CAL_MASTER__FLD LPDDR4__DENALI_CTL_427__MULTI_CHANNEL_ZQ_CAL_MASTER + +#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_SHIFT 8U +#define LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT_WIDTH 3U +#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_427 +#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__STRATEGY_2TICK_COUNT + +#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT_WIDTH 3U +#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_427 +#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__BANK_ACTIVATE_2TICK_COUNT + +#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_MASK 0x07000000U +#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_SHIFT 24U +#define LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT_WIDTH 3U +#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_427 +#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_427__PRE_2TICK_COUNT + +#define LPDDR4__DENALI_CTL_428_READ_MASK 0x0F070707U +#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x0F070707U +#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_MASK 0x00000007U +#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_SHIFT 0U +#define LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT_WIDTH 3U +#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_428 +#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__STRATEGY_4TICK_COUNT + +#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_MASK 0x00000700U +#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_SHIFT 8U +#define LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT_WIDTH 3U +#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_428 +#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__BANK_ACTIVATE_4TICK_COUNT + +#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_MASK 0x00070000U +#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_SHIFT 16U +#define LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT_WIDTH 3U +#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_428 +#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_428__PRE_4TICK_COUNT + +#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_428 +#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_428__TMP_2X4_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_429_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_429 +#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_2X4_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_429 +#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_429 +#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_429__TMP_NXN_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_429 +#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_429__ODT_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_430_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_430 +#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_430__ODT_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_430 +#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRAS_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_430 +#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRAS_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_430 +#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_430__TRP_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_431_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_431 +#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TRP_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_431 +#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TWR_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_431 +#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TWR_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_431 +#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_431__TMP_4X2_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_432 +#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TMP_4X2_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_432 +#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TRFC_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_432 +#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_432__TRFC_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_MASK 0x0F000000U +#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_SHIFT 24U +#define LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_432 +#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_432__RL_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_433_READ_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0xFF0F0F0FU +#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_MASK 0x0000000FU +#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_SHIFT 0U +#define LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_433 +#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_433__RL_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_MASK 0x00000F00U +#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_SHIFT 8U +#define LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ_WIDTH 4U +#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_433 +#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_433__WL_TICK_PLUS_ADJ + +#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_MASK 0x000F0000U +#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_SHIFT 16U +#define LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ_WIDTH 4U +#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_433 +#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_433__WL_TICK_MINUS_ADJ + +#define LPDDR4__DENALI_CTL_433__NWR_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_CTL_433__NWR_F0_SHIFT 24U +#define LPDDR4__DENALI_CTL_433__NWR_F0_WIDTH 8U +#define LPDDR4__NWR_F0__REG DENALI_CTL_433 +#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_433__NWR_F0 + +#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_CTL_434__NWR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_CTL_434__NWR_F1_SHIFT 0U +#define LPDDR4__DENALI_CTL_434__NWR_F1_WIDTH 8U +#define LPDDR4__NWR_F1__REG DENALI_CTL_434 +#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_434__NWR_F1 + +#define LPDDR4__DENALI_CTL_434__NWR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_CTL_434__NWR_F2_SHIFT 8U +#define LPDDR4__DENALI_CTL_434__NWR_F2_WIDTH 8U +#define LPDDR4__NWR_F2__REG DENALI_CTL_434 +#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_434__NWR_F2 + +#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h new file mode 100644 index 0000000000..a5966d896d --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_phy_core_macros.h @@ -0,0 +1,1986 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_ +#define REG_LPDDR4_PHY_CORE_MACROS_H_ + +#define LPDDR4__DENALI_PHY_1792_READ_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1792_WRITE_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1792 +#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1792__PHY_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1793_READ_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1793_WRITE_MASK 0x1F030101U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1793 +#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1793 +#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_MULTICAST_EN + +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_SHIFT 16U +#define LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX_WIDTH 2U +#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1793 +#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1793__PHY_FREQ_SEL_INDEX + +#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1793 +#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1793__PHY_SW_GRP0_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1794_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1794_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1794 +#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP1_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1794 +#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP2_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1794 +#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP3_SHIFT_0 + +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1794 +#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1794__PHY_SW_GRP0_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1795_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1795_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1795 +#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP1_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1795 +#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP2_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1795 +#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP3_SHIFT_1 + +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1795 +#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1795__PHY_SW_GRP0_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1796_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1796_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1796 +#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP1_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1796 +#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP2_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1796 +#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP3_SHIFT_2 + +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1796 +#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1796__PHY_SW_GRP0_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1797_READ_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1797_WRITE_MASK 0x001F1F1FU +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1797 +#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP1_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1797 +#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP2_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3_WIDTH 5U +#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1797 +#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1797__PHY_SW_GRP3_SHIFT_3 + +#define LPDDR4__DENALI_PHY_1798_READ_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1798_WRITE_MASK 0x011F07FFU +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1798 +#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_SLAVE_DELAY + +#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1798 +#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1798__PHY_SW_GRP_BYPASS_SHIFT + +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1798 +#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1798__PHY_GRP_BYPASS_OVERRIDE + +#define LPDDR4__DENALI_PHY_1799_READ_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1799_WRITE_MASK 0x07FF0100U +#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1799 +#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1799__SC_PHY_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1799 +#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1799__PHY_MANUAL_UPDATE_PHYUPD_ENABLE + +#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START_WIDTH 11U +#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1799 +#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1799__PHY_CSLVL_START + +#define LPDDR4__DENALI_PHY_1800_READ_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1800_WRITE_MASK 0x000107FFU +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_SHIFT 0U +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1800 +#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1800__PHY_CSLVL_COARSE_DLY + +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE_WOSET 0U +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1800 +#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1800__PHY_CSLVL_DEBUG_MODE + +#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1800 +#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1800__SC_PHY_CSLVL_DEBUG_CONT + +#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U +#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1801 +#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1801__SC_PHY_CSLVL_ERROR_CLR + +#define LPDDR4__DENALI_PHY_1802_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1802_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1802 +#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1802__PHY_CSLVL_OBS0 + +#define LPDDR4__DENALI_PHY_1803_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1803_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1803 +#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1803__PHY_CSLVL_OBS1 + +#define LPDDR4__DENALI_PHY_1804_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1804_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2_WIDTH 32U +#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1804 +#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1804__PHY_CSLVL_OBS2 + +#define LPDDR4__DENALI_PHY_1805_READ_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1805_WRITE_MASK 0x0101FF01U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE_WOSET 0U +#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1805 +#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1805__PHY_CSLVL_ENABLE + +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U +#define LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1805 +#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1805__PHY_CSLVL_PERIODIC_START_OFFSET + +#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1805 +#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1805__PHY_LP4_BOOT_DISABLE + +#define LPDDR4__DENALI_PHY_1806_READ_MASK 0x0007FF0FU +#define LPDDR4__DENALI_PHY_1806_WRITE_MASK 0x0007FF0FU +#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1806 +#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1806__PHY_CSLVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_SHIFT 8U +#define LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR_WIDTH 11U +#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1806 +#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1806__PHY_CSLVL_QTR + +#define LPDDR4__DENALI_PHY_1807_READ_MASK 0xFF0F07FFU +#define LPDDR4__DENALI_PHY_1807_WRITE_MASK 0xFF0F07FFU +#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK_WIDTH 11U +#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1807 +#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CHK + +#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1807 +#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1807__PHY_CSLVL_COARSE_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP_WIDTH 8U +#define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1807 +#define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1807__PHY_CALVL_CS_MAP + +#define LPDDR4__DENALI_PHY_1808_READ_MASK 0x01030007U +#define LPDDR4__DENALI_PHY_1808_WRITE_MASK 0x01030007U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1808 +#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE + +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1808 +#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_SNAP_OBS_REGS + +#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE_WIDTH 2U +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1808 +#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1808__PHY_DFI_PHYUPD_TYPE + +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR_WOSET 0U +#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1808 +#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1808__PHY_ADRCTL_LPDDR + +#define LPDDR4__DENALI_PHY_1809_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1809_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE_WOSET 0U +#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1809 +#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1809__PHY_LP4_ACTIVE + +#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS_WOSET 0U +#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1809 +#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1809__PHY_LPDDR3_CS + +#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__REG DENALI_PHY_1809 +#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_SAMPLE_WAIT + +#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1809 +#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1809__PHY_CLK_DC_CAL_TIMEOUT + +#define LPDDR4__DENALI_PHY_1810_READ_MASK 0xFF3F0103U +#define LPDDR4__DENALI_PHY_1810_WRITE_MASK 0xFF3F0103U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT_WIDTH 2U +#define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1810 +#define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_WEIGHT + +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U +#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1810 +#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_FREQ_CHG_ADJ + +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_SHIFT 16U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START_WIDTH 6U +#define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1810 +#define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_START + +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_MASK 0xFF000000U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1810 +#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1810__PHY_CLK_DC_ADJUST_SAMPLE_CNT + +#define LPDDR4__DENALI_PHY_1811_READ_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1811_WRITE_MASK 0x010101FFU +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT 0U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__REG DENALI_PHY_1811 +#define LPDDR4__PHY_CLK_DC_ADJUST_THRSHLD__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_THRSHLD + +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_SHIFT 8U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT_WOSET 0U +#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__REG DENALI_PHY_1811 +#define LPDDR4__PHY_CLK_DC_ADJUST_DIRECT__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_ADJUST_DIRECT + +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_SHIFT 16U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY_WOSET 0U +#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1811 +#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_POLARITY + +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_SHIFT 24U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WIDTH 1U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WOCLR 0U +#define LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START_WOSET 0U +#define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1811 +#define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1811__PHY_CLK_DC_CAL_START + +#define LPDDR4__DENALI_PHY_1812_READ_MASK 0x0F0F0100U +#define LPDDR4__DENALI_PHY_1812_WRITE_MASK 0x0F0F0100U +#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 0U +#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U +#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U +#define LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1812 +#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1812__SC_PHY_UPDATE_CLK_CAL_VALUES + +#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1812 +#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1812__PHY_CONTINUOUS_CLK_CAL_UPDATE + +#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1812 +#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_0 + +#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1812 +#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1812__PHY_SW_TXIO_CTRL_1 + +#define LPDDR4__DENALI_PHY_1813_READ_MASK 0x0F010F0FU +#define LPDDR4__DENALI_PHY_1813_WRITE_MASK 0x0F010F0FU +#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1813 +#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_2 + +#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3_WIDTH 4U +#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1813 +#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1813__PHY_SW_TXIO_CTRL_3 + +#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1813 +#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1813__PHY_MEMCLK_SW_TXIO_CTRL + +#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1813 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1813__PHY_ADRCTL_SW_TXPWR_CTRL_0 + +#define LPDDR4__DENALI_PHY_1814_READ_MASK 0x010F0F0FU +#define LPDDR4__DENALI_PHY_1814_WRITE_MASK 0x010F0F0FU +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1814 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_1 + +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1814 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_2 + +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1814 +#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1814__PHY_ADRCTL_SW_TXPWR_CTRL_3 + +#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1814 +#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1814__PHY_MEMCLK_SW_TXPWR_CTRL + +#define LPDDR4__DENALI_PHY_1815_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1815_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1815 +#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1815__PHY_TOP_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1815 +#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1815__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL_WIDTH 16U +#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1815 +#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1815__PHY_STATIC_TOG_CONTROL + +#define LPDDR4__DENALI_PHY_1816_READ_MASK 0x0001010FU +#define LPDDR4__DENALI_PHY_1816_WRITE_MASK 0x0001010FU +#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1816 +#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1816__PHY_ADRCTL_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1816 +#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1816__PHY_MEMCLK_STATIC_TOG_DISABLE + +#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1816 +#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1816__PHY_LP4_BOOT_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1817_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1817_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS_WIDTH 32U +#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1817 +#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1817__PHY_CLK_SWITCH_OBS + +#define LPDDR4__DENALI_PHY_1818_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1818_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT_WIDTH 16U +#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1818 +#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1818__PHY_PLL_WAIT + +#define LPDDR4__DENALI_PHY_1819_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1819_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1819 +#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1819__PHY_SW_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1820_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1820_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1820 +#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_0 + +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1820 +#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_1 + +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1820 +#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_2 + +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3_WIDTH 4U +#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1820 +#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1820__PHY_SET_DFI_INPUT_3 + +#define LPDDR4__DENALI_PHY_1821_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1821_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1821 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT0_0 + +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1821 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT1_0 + +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1821 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT2_0 + +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1821 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1821__PHY_CS_ACS_ALLOCATION_BIT3_0 + +#define LPDDR4__DENALI_PHY_1822_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1822_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1822 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT0_1 + +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1822 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT1_1 + +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1822 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT2_1 + +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 24U +#define LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1822 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1822__PHY_CS_ACS_ALLOCATION_BIT3_1 + +#define LPDDR4__DENALI_PHY_1823_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1823_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1823 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT0_2 + +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT 8U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1823 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT1_2 + +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1823 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT2_2 + +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT 24U +#define LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1823 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1823__PHY_CS_ACS_ALLOCATION_BIT3_2 + +#define LPDDR4__DENALI_PHY_1824_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1824_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1824 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT0_3 + +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT 8U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1824 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT1_3 + +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT 16U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1824 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT2_3 + +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH 4U +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1824 +#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1824__PHY_CS_ACS_ALLOCATION_BIT3_3 + +#define LPDDR4__DENALI_PHY_1825_READ_MASK 0x00FF01FFU +#define LPDDR4__DENALI_PHY_1825_WRITE_MASK 0x00FF01FFU +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1825 +#define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_ADJUST_0 + +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE_WOSET 0U +#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1825 +#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_INIT_DISABLE + +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_SHIFT 16U +#define LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U +#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1825 +#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1825__PHY_CLK_DC_DM_THRSHLD + +#define LPDDR4__DENALI_PHY_1826_READ_MASK 0xFFFF1FFFU +#define LPDDR4__DENALI_PHY_1826_WRITE_MASK 0xFFFF1FFFU +#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1826 +#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1826__PHY_LP4_BOOT_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1826 +#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1826__PHY_PLL_CTRL_OVERRIDE + +#define LPDDR4__DENALI_PHY_1827_READ_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1827_WRITE_MASK 0x0000FF01U +#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1827 +#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1827__PHY_USE_PLL_DSKEWCALLOCK + +#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_SHIFT 8U +#define LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL_WIDTH 8U +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1827 +#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1827__PHY_PLL_SPO_CAL_CTRL + +#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 16U +#define LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1827 +#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1827__SC_PHY_PLL_SPO_CAL_SNAP_OBS + +#define LPDDR4__DENALI_PHY_1828_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1828_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1828 +#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1828__PHY_PLL_OBS_0 + +#define LPDDR4__DENALI_PHY_1829_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1829_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1829 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1829__PHY_PLL_SPO_CAL_OBS_0 + +#define LPDDR4__DENALI_PHY_1830_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1830_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0_WIDTH 12U +#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1830 +#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1830__PHY_PLL_DESKEWCALIN_0 + +#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH 12U +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1830 +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1830__PHY_LP4_BOOT_PLL_DESKEWCALIN_0 + +#define LPDDR4__DENALI_PHY_1831_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1831_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1_WIDTH 16U +#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1831 +#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1831__PHY_PLL_OBS_1 + +#define LPDDR4__DENALI_PHY_1832_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1832_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1832 +#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1832__PHY_PLL_SPO_CAL_OBS_1 + +#define LPDDR4__DENALI_PHY_1833_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1833_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1_WIDTH 12U +#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1833 +#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1833__PHY_PLL_DESKEWCALIN_1 + +#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH 12U +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1833 +#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1833__PHY_LP4_BOOT_PLL_DESKEWCALIN_1 + +#define LPDDR4__DENALI_PHY_1834_READ_MASK 0x0F010101U +#define LPDDR4__DENALI_PHY_1834_WRITE_MASK 0x0F010101U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL_WOSET 0U +#define LPDDR4__PHY_PLL_TESTOUT_SEL__REG DENALI_PHY_1834 +#define LPDDR4__PHY_PLL_TESTOUT_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_PLL_TESTOUT_SEL + +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_SHIFT 8U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL_WOSET 0U +#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1834 +#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_PLL_REFOUT_SEL + +#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1834 +#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1834__PHY_LP4_BOOT_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT_WIDTH 4U +#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1834 +#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1834__PHY_TCKSRE_WAIT + +#define LPDDR4__DENALI_PHY_1835_READ_MASK 0x03FF01FFU +#define LPDDR4__DENALI_PHY_1835_WRITE_MASK 0x03FF01FFU +#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_SHIFT 0U +#define LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP_WIDTH 8U +#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1835 +#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1835__PHY_LP_WAKEUP + +#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_SHIFT 8U +#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN_WOSET 0U +#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1835 +#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1835__PHY_LS_IDLE_EN + +#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x03FF0000U +#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 16U +#define LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1835 +#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1835__PHY_LP_CTRLUPD_CNTR_CFG + +#define LPDDR4__DENALI_PHY_1836_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1836_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL_WIDTH 17U +#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1836 +#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1836__PHY_DS_EXIT_CTRL + +#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_SHIFT 24U +#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WIDTH 1U +#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WOCLR 0U +#define LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY_WOSET 0U +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1836 +#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1836__PHY_TDFI_PHY_WRDELAY + +#define LPDDR4__DENALI_PHY_1837_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1837_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1837 +#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1837__PHY_PAD_FDBK_TERM + +#define LPDDR4__DENALI_PHY_1838_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1838_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1838 +#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1838__PHY_PAD_DATA_TERM + +#define LPDDR4__DENALI_PHY_1839_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1839_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM_WIDTH 17U +#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1839 +#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1839__PHY_PAD_DQS_TERM + +#define LPDDR4__DENALI_PHY_1840_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1840_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1840 +#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1840__PHY_PAD_ADDR_TERM + +#define LPDDR4__DENALI_PHY_1841_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1841_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1841 +#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1841__PHY_PAD_CLK_TERM + +#define LPDDR4__DENALI_PHY_1842_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1842_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1842 +#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1842__PHY_PAD_ERR_TERM + +#define LPDDR4__DENALI_PHY_1843_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1843_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1843 +#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1843__PHY_PAD_CKE_TERM + +#define LPDDR4__DENALI_PHY_1844_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1844_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1844 +#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1844__PHY_PAD_RST_TERM + +#define LPDDR4__DENALI_PHY_1845_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1845_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1845 +#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1845__PHY_PAD_CS_TERM + +#define LPDDR4__DENALI_PHY_1846_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1846_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_SHIFT 0U +#define LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM_WIDTH 18U +#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1846 +#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1846__PHY_PAD_ODT_TERM + +#define LPDDR4__DENALI_PHY_1847_READ_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1847_WRITE_MASK 0x1FFF03FFU +#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL_WIDTH 10U +#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1847 +#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_RX_CAL + +#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U +#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1847 +#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1847__PHY_ADRCTL_LP3_RX_CAL + +#define LPDDR4__DENALI_PHY_1848_READ_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1848_WRITE_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0_WIDTH 13U +#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1848 +#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_MODE_0 + +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0_WOSET 0U +#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1848 +#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_CLEAR_0 + +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0_WOSET 0U +#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1848 +#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1848__PHY_CAL_START_0 + +#define LPDDR4__DENALI_PHY_1849_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1849_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1849 +#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1849__PHY_CAL_INTERVAL_COUNT_0 + +#define LPDDR4__DENALI_PHY_1850_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1850_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1850 +#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1850__PHY_CAL_SAMPLE_WAIT_0 + +#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1850 +#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1850__PHY_LP4_BOOT_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1851_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1851_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1851 +#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1851__PHY_CAL_RESULT_OBS_0 + +#define LPDDR4__DENALI_PHY_1852_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1852_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1852 +#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1852__PHY_CAL_RESULT2_OBS_0 + +#define LPDDR4__DENALI_PHY_1853_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1853_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1853 +#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1853__PHY_CAL_RESULT4_OBS_0 + +#define LPDDR4__DENALI_PHY_1854_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1854_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1854 +#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1854__PHY_CAL_RESULT5_OBS_0 + +#define LPDDR4__DENALI_PHY_1855_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1855_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1855 +#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1855__PHY_CAL_RESULT6_OBS_0 + +#define LPDDR4__DENALI_PHY_1856_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1856_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0_WIDTH 24U +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1856 +#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1856__PHY_CAL_RESULT7_OBS_0 + +#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0_WIDTH 7U +#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1856 +#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1856__PHY_CAL_CPTR_CNT_0 + +#define LPDDR4__DENALI_PHY_1857_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1857_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1857 +#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_PU_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1857 +#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_PD_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1857 +#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_RCV_FINE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0_WOSET 0U +#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1857 +#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1857__PHY_CAL_DBG_CFG_0 + +#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U +#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U +#define LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0_WOSET 0U +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1858 +#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1858__SC_PHY_PAD_DBG_CONT_0 + +#define LPDDR4__DENALI_PHY_1859_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1859_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0_WIDTH 32U +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1859 +#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1859__PHY_CAL_RESULT3_OBS_0 + +#define LPDDR4__DENALI_PHY_1860_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1860_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0_WIDTH 8U +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1860 +#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1860__PHY_ADRCTL_PVT_MAP_0 + +#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U +#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1860 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1860__PHY_CAL_SLOPE_ADJ_0 + +#define LPDDR4__DENALI_PHY_1861_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1861_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1861 +#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1861__PHY_CAL_SLOPE_ADJ_PASS2_0 + +#define LPDDR4__DENALI_PHY_1862_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1862_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1862 +#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1862__PHY_CAL_TWO_PASS_CFG_0 + +#define LPDDR4__DENALI_PHY_1863_READ_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1863_WRITE_MASK 0x3F7FFFFFU +#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU +#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1863 +#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1863__PHY_CAL_SW_CAL_CFG_0 + +#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1863 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1863__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1864_READ_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1864_WRITE_MASK 0x3F3F1F3FU +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1864 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1864 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1864 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1864 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1864__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1865_READ_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1865_WRITE_MASK 0x1F3F3F1FU +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1865 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 + +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1865 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1865 +#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1865 +#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1865__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1866_READ_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1866_WRITE_MASK 0x001F3F3FU +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1866 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1866 +#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1866 +#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1866__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 + +#define LPDDR4__DENALI_PHY_1867_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1867_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL_WIDTH 16U +#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1867 +#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1867__PHY_PAD_ATB_CTRL + +#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1867 +#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1867__PHY_ADRCTL_MANUAL_UPDATE + +#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_SHIFT 24U +#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U +#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U +#define LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1867 +#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1867__PHY_AC_LPBK_ERR_CLEAR + +#define LPDDR4__DENALI_PHY_1868_READ_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1868_WRITE_MASK 0x01FF0F03U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT_WIDTH 2U +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1868 +#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE_WIDTH 4U +#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1868 +#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_MASK 0x01FF0000U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL_WIDTH 9U +#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1868 +#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1868__PHY_AC_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1869_READ_MASK 0x00000F7FU +#define LPDDR4__DENALI_PHY_1869_WRITE_MASK 0x00000F7FU +#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_MASK 0x0000007FU +#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_SHIFT 0U +#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START_WIDTH 7U +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1869 +#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_START + +#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_MASK 0x00000F00U +#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_SHIFT 8U +#define LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1869 +#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1869__PHY_AC_PRBS_PATTERN_MASK + +#define LPDDR4__DENALI_PHY_1870_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1870_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1870 +#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1870__PHY_AC_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1871_READ_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1871_WRITE_MASK 0x003F0101U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1871 +#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1871 +#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_ENABLE + +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1871 +#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1871__PHY_AC_CLK_LPBK_CONTROL + +#define LPDDR4__DENALI_PHY_1872_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1872_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1872 +#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1872__PHY_AC_CLK_LPBK_RESULT_OBS + +#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1872 +#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1872__PHY_AC_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1872 +#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1872__PHY_TOP_PWR_RDC_DISABLE + +#define LPDDR4__DENALI_PHY_1873_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1873_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1873 +#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1873__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1874_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1874_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1874 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1874__PHY_DATA_BYTE_ORDER_SEL + +#define LPDDR4__DENALI_PHY_1875_READ_MASK 0x071F01FFU +#define LPDDR4__DENALI_PHY_1875_WRITE_MASK 0x071F01FFU +#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU +#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U +#define LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1875 +#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1875__PHY_DATA_BYTE_ORDER_SEL_HIGH + +#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_SHIFT 8U +#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WIDTH 1U +#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WOCLR 0U +#define LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT_WOSET 0U +#define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1875 +#define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1875__PHY_LPDDR4_CONNECT + +#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_MASK 0x001F0000U +#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_SHIFT 16U +#define LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP_WIDTH 5U +#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1875 +#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1875__PHY_CALVL_DEVICE_MAP + +#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE_WIDTH 3U +#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1875 +#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1875__PHY_ADR_DISABLE + +#define LPDDR4__DENALI_PHY_1876_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1876_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1876 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 + +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000300U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 8U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1876 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 + +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK 0x00030000U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1876 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2 + +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK 0x03000000U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT 24U +#define LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH 2U +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1876 +#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1876__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3 + +#define LPDDR4__DENALI_PHY_1877_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1877_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE_WIDTH 32U +#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1877 +#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1877__PHY_DDL_AC_ENABLE + +#define LPDDR4__DENALI_PHY_1878_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1878_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE_WIDTH 26U +#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1878 +#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1878__PHY_DDL_AC_MODE + +#define LPDDR4__DENALI_PHY_1879_READ_MASK 0x00FF073FU +#define LPDDR4__DENALI_PHY_1879_WRITE_MASK 0x00FF073FU +#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_MASK 0x0000003FU +#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK_WIDTH 6U +#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1879 +#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1879__PHY_DDL_AC_MASK + +#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U +#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_SHIFT 8U +#define LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG_WIDTH 3U +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1879 +#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1879__PHY_INIT_UPDATE_CONFIG + +#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U +#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U +#define LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1879 +#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1879__PHY_DDL_TRACK_UPD_THRESHOLD_AC + +#define LPDDR4__DENALI_PHY_1880_READ_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_1880_WRITE_MASK 0x0707FFFFU +#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH 16U +#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1880 +#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1880__PHY_CA_PARITY_ERR_PULSE_MIN + +#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_MASK 0x00070000U +#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN_WIDTH 3U +#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1880 +#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1880__PHY_ERR_MASK_EN + +#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS_WIDTH 3U +#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1880 +#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1880__PHY_ERR_STATUS + +#define LPDDR4__DENALI_PHY_1881_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1881_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1881 +#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1881__PHY_DS0_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1882_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1882_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1882 +#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1882__PHY_DS1_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1883_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1883_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1883 +#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1883__PHY_DS2_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1884_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1884_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U +#define LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER_WIDTH 32U +#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1884 +#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1884__PHY_DS3_DQS_ERR_COUNTER + +#define LPDDR4__DENALI_PHY_1885_READ_MASK 0x0F0FFF03U +#define LPDDR4__DENALI_PHY_1885_WRITE_MASK 0x0F0FFF03U +#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_MASK 0x00000003U +#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN_WIDTH 2U +#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1885 +#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1885__PHY_DLL_RST_EN + +#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_MASK 0x000FFF00U +#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS_WIDTH 12U +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1885 +#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1885__PHY_AC_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS_WIDTH 4U +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1885 +#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1885__PHY_DS_INIT_COMPLETE_OBS + +#define LPDDR4__DENALI_PHY_1886_READ_MASK 0x1F010101U +#define LPDDR4__DENALI_PHY_1886_WRITE_MASK 0x1F010101U +#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_SHIFT 0U +#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WIDTH 1U +#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WOCLR 0U +#define LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK_WOSET 0U +#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1886 +#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1886__PHY_UPDATE_MASK + +#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_MASK 0x00000100U +#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_SHIFT 8U +#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1886__PHY_ERR_IE_WOSET 0U +#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1886 +#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1886__PHY_ERR_IE + +#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_SHIFT 16U +#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE_WOSET 0U +#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__REG DENALI_PHY_1886 +#define LPDDR4__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1886__PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE + +#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x1F000000U +#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 24U +#define LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 5U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1886 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1886__PHY_GRP_SLV_DLY_ENC_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1887_READ_MASK 0x0707FF0FU +#define LPDDR4__DENALI_PHY_1887_WRITE_MASK 0x0707FF0FU +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x0000000FU +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 0U +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 4U +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1887 +#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SELECT + +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x0007FF00U +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 8U +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1887 +#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SLV_DLY_ENC_OBS + +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_SHIFT 24U +#define LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS_WIDTH 3U +#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1887 +#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1887__PHY_GRP_SHIFT_OBS + +#define LPDDR4__DENALI_PHY_1888_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1888_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1888 +#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1888__PHY_PAD_CAL_IO_CFG_0 + +#define LPDDR4__DENALI_PHY_1889_READ_MASK 0x0703FFFFU +#define LPDDR4__DENALI_PHY_1889_WRITE_MASK 0x0703FFFFU +#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_SHIFT 0U +#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG_WIDTH 18U +#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1889 +#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_IO_CFG + +#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK 0x07000000U +#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT 24U +#define LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH 3U +#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1889 +#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1889__PHY_PAD_ACS_RX_PCLK_CLK_SEL + +#define LPDDR4__DENALI_PHY_1890_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1890_WRITE_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_MASK 0x00000001U +#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_SHIFT 0U +#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WIDTH 1U +#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WOCLR 0U +#define LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS_WOSET 0U +#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1890 +#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1890__PHY_PLL_BYPASS + +#define LPDDR4__DENALI_PHY_1891_READ_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1891_WRITE_MASK 0x00011FFFU +#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_MASK 0x00001FFFU +#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL_WIDTH 13U +#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1891 +#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1891__PHY_PLL_CTRL + +#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_SHIFT 16U +#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WIDTH 1U +#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WOCLR 0U +#define LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL_WOSET 0U +#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1891 +#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1891__PHY_LOW_FREQ_SEL + +#define LPDDR4__DENALI_PHY_1892_READ_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1892_WRITE_MASK 0x0F0F0FFFU +#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU +#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_SHIFT 0U +#define LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC_WIDTH 12U +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1892 +#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1892__PHY_PAD_VREF_CTRL_AC + +#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U +#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U +#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1892 +#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1892__PHY_CSLVL_CAPTURE_CNT + +#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U +#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_SHIFT 24U +#define LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP_WIDTH 4U +#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1892 +#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1892__PHY_CSLVL_DLY_STEP + +#define LPDDR4__DENALI_PHY_1893_READ_MASK 0x010103FFU +#define LPDDR4__DENALI_PHY_1893_WRITE_MASK 0x010103FFU +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_MASK 0x000003FFU +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_WIDTH 10U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1893 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN + +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U +#define LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1893 +#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1893__PHY_SW_CSLVL_DVW_MIN_EN + +#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1893 +#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1893__PHY_LVL_MEAS_DLY_STEP_ENABLE + +#define LPDDR4__DENALI_PHY_1894_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1894_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1894 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1894__PHY_GRP0_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1894 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1894__PHY_GRP1_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1895_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1895_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1895 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1895__PHY_GRP2_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U +#define LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1895 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1895__PHY_GRP3_SLAVE_DELAY_0 + +#define LPDDR4__DENALI_PHY_1896_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1896_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1896 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1896__PHY_GRP0_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1896 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1896__PHY_GRP1_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1897_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1897_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U +#define LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1897 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1897__PHY_GRP2_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_SHIFT 16U +#define LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1897 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1897__PHY_GRP3_SLAVE_DELAY_1 + +#define LPDDR4__DENALI_PHY_1898_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1898_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1898 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1898__PHY_GRP0_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1898 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1898__PHY_GRP1_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1899_READ_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1899_WRITE_MASK 0x07FF07FFU +#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1899 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1899__PHY_GRP2_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_MASK 0x07FF0000U +#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_SHIFT 16U +#define LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1899 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1899__PHY_GRP3_SLAVE_DELAY_2 + +#define LPDDR4__DENALI_PHY_1900_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1900_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1900 +#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1900__PHY_GRP0_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1901_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1901_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1901 +#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1901__PHY_GRP1_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1902_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1902_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1902 +#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1902__PHY_GRP2_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1903_READ_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1903_WRITE_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_MASK 0x000007FFU +#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_SHIFT 0U +#define LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3_WIDTH 11U +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1903 +#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1903__PHY_GRP3_SLAVE_DELAY_3 + +#define LPDDR4__DENALI_PHY_1904_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1904_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U +#define LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U +#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1904 +#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1904__PHY_CLK_DC_CAL_CLK_SEL + +#define LPDDR4__DENALI_PHY_1905_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1905_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1905 +#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1905__PHY_PAD_FDBK_DRIVE + +#define LPDDR4__DENALI_PHY_1906_READ_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1906_WRITE_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU +#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2_WIDTH 18U +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1906 +#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1906__PHY_PAD_FDBK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1907_READ_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1907_WRITE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU +#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE_WIDTH 31U +#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1907 +#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1907__PHY_PAD_DATA_DRIVE + +#define LPDDR4__DENALI_PHY_1908_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1908_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1908 +#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1908__PHY_PAD_DQS_DRIVE + +#define LPDDR4__DENALI_PHY_1909_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1909_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1909 +#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1909__PHY_PAD_ADDR_DRIVE + +#define LPDDR4__DENALI_PHY_1910_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1910_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1910 +#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1910__PHY_PAD_ADDR_DRIVE2 + +#define LPDDR4__DENALI_PHY_1911_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1911_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE_WIDTH 32U +#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1911 +#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1911__PHY_PAD_CLK_DRIVE + +#define LPDDR4__DENALI_PHY_1912_READ_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1912_WRITE_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_MASK 0x0007FFFFU +#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2_WIDTH 19U +#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1912 +#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1912__PHY_PAD_CLK_DRIVE2 + +#define LPDDR4__DENALI_PHY_1913_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1913_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1913 +#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1913__PHY_PAD_ERR_DRIVE + +#define LPDDR4__DENALI_PHY_1914_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1914_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1914 +#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1914__PHY_PAD_ERR_DRIVE2 + +#define LPDDR4__DENALI_PHY_1915_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1915_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1915 +#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1915__PHY_PAD_CKE_DRIVE + +#define LPDDR4__DENALI_PHY_1916_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1916_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1916 +#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1916__PHY_PAD_CKE_DRIVE2 + +#define LPDDR4__DENALI_PHY_1917_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1917_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1917 +#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1917__PHY_PAD_RST_DRIVE + +#define LPDDR4__DENALI_PHY_1918_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1918_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1918 +#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1918__PHY_PAD_RST_DRIVE2 + +#define LPDDR4__DENALI_PHY_1919_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1919_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1919 +#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1919__PHY_PAD_CS_DRIVE + +#define LPDDR4__DENALI_PHY_1920_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1920_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1920 +#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1920__PHY_PAD_CS_DRIVE2 + +#define LPDDR4__DENALI_PHY_1921_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1921_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_SHIFT 0U +#define LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE_WIDTH 30U +#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1921 +#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1921__PHY_PAD_ODT_DRIVE + +#define LPDDR4__DENALI_PHY_1922_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1922_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_SHIFT 0U +#define LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2_WIDTH 28U +#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1922 +#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1922__PHY_PAD_ODT_DRIVE2 + +#define LPDDR4__DENALI_PHY_1923_READ_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1923_WRITE_MASK 0x7FFFFF07U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_SHIFT 0U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0_WIDTH 3U +#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1923 +#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_CLK_SELECT_0 + +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1923 +#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_VREF_SWITCH_TIMER_0 + +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_SHIFT 24U +#define LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0_WIDTH 7U +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1923 +#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1923__PHY_CAL_SETTLING_PRD_0 + +#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h new file mode 100644 index 0000000000..e36327f644 --- /dev/null +++ b/drivers/ram/k3-ddrss/am62a/lpddr4_pi_macros.h @@ -0,0 +1,6892 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef REG_LPDDR4_PI_MACROS_H_ +#define REG_LPDDR4_PI_MACROS_H_ + +#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U +#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U +#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U +#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U +#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U +#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U +#define LPDDR4__PI_START__REG DENALI_PI_0 +#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START + +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U +#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U +#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0 +#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS + +#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U +#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U +#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1 +#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0 + +#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U +#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U +#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2 +#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1 + +#define LPDDR4__DENALI_PI_3_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U +#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U +#define LPDDR4__PI_ID__REG DENALI_PI_3 +#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID + +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK 0x00010000U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT 16U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH 1U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR 0U +#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET 0U +#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3 +#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI + +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT 24U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH 1U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR 0U +#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET 0U +#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3 +#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ + +#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET 0U +#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4 +#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN + +#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK 0x00000300U +#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT 8U +#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH 2U +#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4 +#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD + +#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT 16U +#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH 16U +#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4 +#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP + +#define LPDDR4__DENALI_PI_5_READ_MASK 0x030100FFU +#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x030100FFU +#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT 0U +#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH 8U +#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5 +#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0 + +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT 8U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5 +#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ + +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK 0x00010000U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT 16U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH 1U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR 0U +#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET 0U +#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5 +#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION + +#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT 24U +#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5 +#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_6_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00000001U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 0U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6 +#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R + +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x00000100U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 8U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U +#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6 +#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R + +#define LPDDR4__DENALI_PI_7_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_7_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7 +#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX + +#define LPDDR4__DENALI_PI_8_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_8_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8 +#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP + +#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH 20U +#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9 +#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP + +#define LPDDR4__DENALI_PI_10_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_10_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10 +#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX + +#define LPDDR4__DENALI_PI_11_READ_MASK 0x0000011FU +#define LPDDR4__DENALI_PI_11_WRITE_MASK 0x0000011FU +#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT 0U +#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH 5U +#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11 +#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ + +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET 0U +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11 +#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY + +#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U +#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12 +#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP + +#define LPDDR4__DENALI_PI_13_READ_MASK 0x010F0101U +#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x010F0101U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00000001U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 0U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U +#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13 +#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N + +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 8U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U +#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13 +#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1 + +#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH 4U +#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13 +#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP + +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK 0x01000000U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT 24U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH 1U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR 0U +#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET 0U +#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13 +#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL + +#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU +#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU +#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH 4U +#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14 +#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK + +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U +#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U +#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14 +#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE + +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14 +#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN + +#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U +#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U +#define LPDDR4__PI_TMRR__REG DENALI_PI_14 +#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR + +#define LPDDR4__DENALI_PI_15_READ_MASK 0x0101070FU +#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x0101070FU +#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT 0U +#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH 4U +#define LPDDR4__PI_TMPRR__REG DENALI_PI_15 +#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR + +#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK 0x00000700U +#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH 3U +#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15 +#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN + +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00010000U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 16U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15 +#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY + +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x01000000U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 24U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U +#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U +#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15 +#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2 + +#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U +#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16 +#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL + +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U +#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U +#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16 +#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS + +#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U +#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17 +#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U +#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD + +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U +#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17 +#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE + +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U +#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17 +#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0 + +#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U +#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1 + +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2 + +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U +#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U +#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18 +#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3 + +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18 +#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0 + +#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1 + +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2 + +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U +#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19 +#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3 + +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19 +#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0 + +#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U +#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U +#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20 +#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U +#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U +#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT + +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20 +#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0 + +#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0 + +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U +#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21 +#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0 + +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21 +#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1 + +#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1 + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1 + +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22 +#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1 + +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22 +#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2 + +#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2 + +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2 + +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U +#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23 +#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2 + +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23 +#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3 + +#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3 + +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3 + +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U +#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24 +#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3 + +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U +#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24 +#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START + +#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25 +#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR + +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25 +#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD + +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25 +#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ + +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25 +#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN + +#define LPDDR4__DENALI_PI_26_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26 +#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN + +#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_26 +#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_MPD_PERIOD_EN + +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00010000U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 16U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U +#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26 +#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY + +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 24U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U +#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U +#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26 +#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT + +#define LPDDR4__DENALI_PI_27_READ_MASK 0x3F030F00U +#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x3F030F00U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_SHIFT 0U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_REQ_WOSET 0U +#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_27 +#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_REQ + +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_SHIFT 8U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW_WIDTH 4U +#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_27 +#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SW + +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00030000U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 16U +#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U +#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27 +#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS + +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 24U +#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U +#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27 +#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN + +#define LPDDR4__DENALI_PI_28_READ_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x01FFFF3FU +#define LPDDR4__DENALI_PI_28__PI_WLMRD_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_28__PI_WLMRD_SHIFT 0U +#define LPDDR4__DENALI_PI_28__PI_WLMRD_WIDTH 6U +#define LPDDR4__PI_WLMRD__REG DENALI_PI_28 +#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_28__PI_WLMRD + +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 8U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL + +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28 +#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U +#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE + +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U +#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29 +#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP + +#define LPDDR4__DENALI_PI_30_READ_MASK 0x00FF0101U +#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x00FF0101U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_SHIFT 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_30 +#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000100U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30 +#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30 +#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN + +#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31 +#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP + +#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32 +#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX + +#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33 +#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U +#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U +#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33 +#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR + +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U +#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U +#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33 +#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD + +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U +#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U +#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33 +#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE + +#define LPDDR4__DENALI_PI_34_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_SHIFT 0U +#define LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING_WIDTH 4U +#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_34 +#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_34__PI_ADDRESS_MIRRORING + +#define LPDDR4__DENALI_PI_35_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_35_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_SHIFT 0U +#define LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT_WIDTH 26U +#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_35 +#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_35__PI_CA_PARITY_ERROR_INJECT + +#define LPDDR4__DENALI_PI_36_READ_MASK 0x00000F07U +#define LPDDR4__DENALI_PI_36_WRITE_MASK 0x00000F07U +#define LPDDR4__DENALI_PI_36__PI_RESERVED3_MASK 0x00000007U +#define LPDDR4__DENALI_PI_36__PI_RESERVED3_SHIFT 0U +#define LPDDR4__DENALI_PI_36__PI_RESERVED3_WIDTH 3U +#define LPDDR4__PI_RESERVED3__REG DENALI_PI_36 +#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_36__PI_RESERVED3 + +#define LPDDR4__DENALI_PI_36__PI_RESERVED4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_36__PI_RESERVED4_SHIFT 8U +#define LPDDR4__DENALI_PI_36__PI_RESERVED4_WIDTH 4U +#define LPDDR4__PI_RESERVED4__REG DENALI_PI_36 +#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_36__PI_RESERVED4 + +#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_36 +#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_REQ + +#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_36 +#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_GATE_REQ + +#define LPDDR4__DENALI_PI_37_READ_MASK 0x0000030FU +#define LPDDR4__DENALI_PI_37_WRITE_MASK 0x0000030FU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_SHIFT 0U +#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW_WIDTH 4U +#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_37 +#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SW + +#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_SHIFT 8U +#define LPDDR4__DENALI_PI_37__PI_RDLVL_CS_WIDTH 2U +#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_37 +#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_CS + +#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_38 +#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_0 + +#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_39 +#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_1 + +#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_40 +#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_2 + +#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_41 +#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_3 + +#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_SHIFT 0U +#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_42 +#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_4 + +#define LPDDR4__DENALI_PI_43_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_43_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_SHIFT 0U +#define LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_43 +#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PAT_5 + +#define LPDDR4__DENALI_PI_44_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_44_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_SHIFT 0U +#define LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_44 +#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_PAT_6 + +#define LPDDR4__DENALI_PI_45_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_45_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_SHIFT 0U +#define LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7_WIDTH 32U +#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_45 +#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_PAT_7 + +#define LPDDR4__DENALI_PI_46_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN_WIDTH 4U +#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_46 +#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_SEQ_EN + +#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_46 +#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_46 +#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_46 +#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_46__PI_RDLVL_GATE_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_47_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_47_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_47 +#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_DISABLE_DFS + +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_47 +#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_47 +#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_GATE_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_47 +#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_47__PI_RDLVL_ROTATE + +#define LPDDR4__DENALI_PI_48_READ_MASK 0x000F0F01U +#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x000F0F01U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE_WOSET 0U +#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_48 +#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_ROTATE + +#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_SHIFT 8U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_48 +#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_CS_MAP + +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_SHIFT 16U +#define LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP_WIDTH 4U +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_48 +#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_GATE_CS_MAP + +#define LPDDR4__DENALI_PI_49_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_49_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_SHIFT 0U +#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR_WIDTH 10U +#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_49 +#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_RR + +#define LPDDR4__DENALI_PI_50_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_50_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_50 +#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_50__PI_TDFI_RDLVL_RESP + +#define LPDDR4__DENALI_PI_51_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_51 +#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_51 +#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_51__PI_TDFI_RDLVL_EN + +#define LPDDR4__DENALI_PI_52_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_52_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_52 +#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_52__PI_TDFI_RDLVL_MAX + +#define LPDDR4__DENALI_PI_53_READ_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x00FFFF01U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WIDTH 1U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOCLR 0U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS_WOSET 0U +#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_53 +#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_SHIFT 8U +#define LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_53 +#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_53__PI_RDLVL_INTERVAL + +#define LPDDR4__DENALI_PI_54_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL_WIDTH 16U +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_54 +#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_GATE_INTERVAL + +#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_SHIFT 16U +#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_54 +#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_START + +#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_SHIFT 24U +#define LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM_WIDTH 4U +#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_54 +#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_54__PI_RDLVL_PATTERN_NUM + +#define LPDDR4__DENALI_PI_55_READ_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x01011F1FU +#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_55 +#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_55 +#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_55__PI_RDLVL_GATE_STROBE_NUM + +#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_55 +#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_55__PI_RD_PREAMBLE_TRAINING_EN + +#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE_WOSET 0U +#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_55 +#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_55__PI_REG_DIMM_ENABLE + +#define LPDDR4__DENALI_PI_56_READ_MASK 0x0F00FFFFU +#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x0F00FFFFU +#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_56 +#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_RDDATA_EN + +#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_SHIFT 8U +#define LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT_WIDTH 8U +#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_56 +#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_56__PI_TDFI_PHY_WRLAT + +#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_MASK 0x00010000U +#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_SHIFT 16U +#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_56__PI_CALVL_REQ_WOSET 0U +#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_56 +#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_56__PI_CALVL_REQ + +#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_SHIFT 24U +#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW_WIDTH 4U +#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_56 +#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_SW + +#define LPDDR4__DENALI_PI_57_READ_MASK 0x030F0103U +#define LPDDR4__DENALI_PI_57_WRITE_MASK 0x030F0103U +#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_MASK 0x00000003U +#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_SHIFT 0U +#define LPDDR4__DENALI_PI_57__PI_CALVL_CS_WIDTH 2U +#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_57 +#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_57__PI_CALVL_CS + +#define LPDDR4__DENALI_PI_57__PI_RESERVED5_MASK 0x00000100U +#define LPDDR4__DENALI_PI_57__PI_RESERVED5_SHIFT 8U +#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WIDTH 1U +#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOCLR 0U +#define LPDDR4__DENALI_PI_57__PI_RESERVED5_WOSET 0U +#define LPDDR4__PI_RESERVED5__REG DENALI_PI_57 +#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_57__PI_RESERVED5 + +#define LPDDR4__DENALI_PI_57__PI_RESERVED6_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_57__PI_RESERVED6_SHIFT 16U +#define LPDDR4__DENALI_PI_57__PI_RESERVED6_WIDTH 4U +#define LPDDR4__PI_RESERVED6__REG DENALI_PI_57 +#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_57__PI_RESERVED6 + +#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_MASK 0x03000000U +#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN_WIDTH 2U +#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_57 +#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_57__PI_CALVL_SEQ_EN + +#define LPDDR4__DENALI_PI_58_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_58_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_MASK 0x00000001U +#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_SHIFT 0U +#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_58 +#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_58__PI_CALVL_PERIODIC + +#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_58 +#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_58 +#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_58__PI_CALVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_SHIFT 24U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE_WOSET 0U +#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_58 +#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_58__PI_CALVL_ROTATE + +#define LPDDR4__DENALI_PI_59_READ_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_59_WRITE_MASK 0x0000FF0FU +#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_SHIFT 0U +#define LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_59 +#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_59__PI_CALVL_CS_MAP + +#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_59 +#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_59__PI_TDFI_CALVL_EN + +#define LPDDR4__DENALI_PI_60_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_60_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_60 +#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_60__PI_TDFI_CALVL_RESP + +#define LPDDR4__DENALI_PI_61_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_61 +#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_61__PI_TDFI_CALVL_MAX + +#define LPDDR4__DENALI_PI_62_READ_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_62_WRITE_MASK 0xFFFF0301U +#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WIDTH 1U +#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOCLR 0U +#define LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK_WOSET 0U +#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_62 +#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_62__PI_CALVL_RESP_MASK + +#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_62 +#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_62__PI_CALVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_SHIFT 16U +#define LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_62 +#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_62__PI_CALVL_INTERVAL + +#define LPDDR4__DENALI_PI_63_READ_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x1F1F3F1FU +#define LPDDR4__DENALI_PI_63__PI_TCACKEL_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_63__PI_TCACKEL_SHIFT 0U +#define LPDDR4__DENALI_PI_63__PI_TCACKEL_WIDTH 5U +#define LPDDR4__PI_TCACKEL__REG DENALI_PI_63 +#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_63__PI_TCACKEL + +#define LPDDR4__DENALI_PI_63__PI_TCAMRD_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_63__PI_TCAMRD_SHIFT 8U +#define LPDDR4__DENALI_PI_63__PI_TCAMRD_WIDTH 6U +#define LPDDR4__PI_TCAMRD__REG DENALI_PI_63 +#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_63__PI_TCAMRD + +#define LPDDR4__DENALI_PI_63__PI_TCACKEH_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_63__PI_TCACKEH_SHIFT 16U +#define LPDDR4__DENALI_PI_63__PI_TCACKEH_WIDTH 5U +#define LPDDR4__PI_TCACKEH__REG DENALI_PI_63 +#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_63__PI_TCACKEH + +#define LPDDR4__DENALI_PI_63__PI_TCAEXT_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_63__PI_TCAEXT_SHIFT 24U +#define LPDDR4__DENALI_PI_63__PI_TCAEXT_WIDTH 5U +#define LPDDR4__PI_TCAEXT__REG DENALI_PI_63 +#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_63__PI_TCAEXT + +#define LPDDR4__DENALI_PI_64_READ_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_64_WRITE_MASK 0xFF0F0F01U +#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN_WOSET 0U +#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_64 +#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_64__PI_CA_TRAIN_VREF_EN + +#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U +#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_64 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_64 +#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_64__PI_CALVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_SHIFT 24U +#define LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_64 +#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_64__PI_TDFI_INIT_START_MIN + +#define LPDDR4__DENALI_PI_65_READ_MASK 0x017F1FFFU +#define LPDDR4__DENALI_PI_65_WRITE_MASK 0x017F1FFFU +#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_SHIFT 0U +#define LPDDR4__DENALI_PI_65__PI_TCKCKEH_WIDTH 8U +#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_65 +#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_65__PI_TCKCKEH + +#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_SHIFT 8U +#define LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM_WIDTH 5U +#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_65 +#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_65__PI_CALVL_STROBE_NUM + +#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_SHIFT 16U +#define LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF_WIDTH 7U +#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_65 +#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_65__PI_SW_CA_TRAIN_VREF + +#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_65 +#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_65__PI_REFRESH_BETWEEN_SEGMENT_DISABLE + +#define LPDDR4__DENALI_PI_66_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_66_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_SHIFT 0U +#define LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START_WIDTH 8U +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_66 +#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_66__PI_CLKDISABLE_2_INIT_START + +#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U +#define LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_66 +#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_66__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE + +#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U +#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U +#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U +#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U +#define LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_66 +#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_66__PI_DRAM_CLK_DISABLE_DEASSERT_SEL + +#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 24U +#define LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_66 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_66__PI_TDFI_INIT_COMPLETE_MIN + +#define LPDDR4__DENALI_PI_67_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_67__PI_VREF_CS_MASK 0x00000003U +#define LPDDR4__DENALI_PI_67__PI_VREF_CS_SHIFT 0U +#define LPDDR4__DENALI_PI_67__PI_VREF_CS_WIDTH 2U +#define LPDDR4__PI_VREF_CS__REG DENALI_PI_67 +#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_67__PI_VREF_CS + +#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN_WOSET 0U +#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_67 +#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_67__PI_VREF_PDA_EN + +#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_MASK 0x00010000U +#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_SHIFT 16U +#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_67 +#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_67__PI_VREFLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 24U +#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U +#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U +#define LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_67 +#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_67__PI_MC_DFS_PI_SET_VREF_ENABLE + +#define LPDDR4__DENALI_PI_68_READ_MASK 0x0F0701FFU +#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x0F0701FFU +#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT 0U +#define LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH 8U +#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_68 +#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_68__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT + +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_VREF_EN + +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_MASK 0x00070000U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM_WIDTH 3U +#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_BST_NUM + +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_SHIFT 24U +#define LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_68 +#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_RESP_MASK + +#define LPDDR4__DENALI_PI_69_READ_MASK 0x1F1F0F01U +#define LPDDR4__DENALI_PI_69_WRITE_MASK 0x1F1F0F01U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_MASK 0x00000001U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_SHIFT 0U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WIDTH 1U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOCLR 0U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE_WOSET 0U +#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_69 +#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_ROTATE + +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_SHIFT 8U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP_WIDTH 4U +#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_69 +#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_CS_MAP + +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 16U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_69 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_INITIAL_STEPSIZE + +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 24U +#define LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_69 +#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_69__PI_WDQLVL_VREF_NORMAL_STEPSIZE + +#define LPDDR4__DENALI_PI_70_READ_MASK 0x030F0001U +#define LPDDR4__DENALI_PI_70_WRITE_MASK 0x030F0001U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_MASK 0x00000001U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_SHIFT 0U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WIDTH 1U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOCLR 0U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC_WOSET 0U +#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_70 +#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_PERIODIC + +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_MASK 0x00000100U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_SHIFT 8U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ_WOSET 0U +#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_70 +#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_REQ + +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_SHIFT 16U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW_WIDTH 4U +#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_70 +#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SW + +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_MASK 0x03000000U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_SHIFT 24U +#define LPDDR4__DENALI_PI_70__PI_WDQLVL_CS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_70 +#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_70__PI_WDQLVL_CS + +#define LPDDR4__DENALI_PI_71_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN_WIDTH 8U +#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_71 +#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_71__PI_TDFI_WDQLVL_EN + +#define LPDDR4__DENALI_PI_72_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_72_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_SHIFT 0U +#define LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_72 +#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_72__PI_TDFI_WDQLVL_RESP + +#define LPDDR4__DENALI_PI_73_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_73_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_SHIFT 0U +#define LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX_WIDTH 32U +#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_73 +#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_73__PI_TDFI_WDQLVL_MAX + +#define LPDDR4__DENALI_PI_74_READ_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0101FFFFU +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_SHIFT 0U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL_WIDTH 16U +#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_74 +#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_INTERVAL + +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_74 +#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_SREF_EXIT + +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_SHIFT 24U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT_WOSET 0U +#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_74 +#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_ON_MPD_EXIT + +#define LPDDR4__DENALI_PI_75_READ_MASK 0x00030301U +#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x00030301U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_MASK 0x00000001U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_SHIFT 0U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WIDTH 1U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOCLR 0U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS_WOSET 0U +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_75 +#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_DISABLE_DFS + +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_MASK 0x00000300U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_75 +#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_ERROR_STATUS + +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT 16U +#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH 2U +#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_75 +#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NEED_SAVE_RESTORE + +#define LPDDR4__DENALI_PI_76_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_76_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH 32U +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_76 +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_DRAM_LVL_START_ADDR_0 + +#define LPDDR4__DENALI_PI_77_READ_MASK 0x00010107U +#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x00010107U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH 3U +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_77 +#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DRAM_LVL_START_ADDR_1 + +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_77 +#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_77__PI_WDQLVL_DM_LEVEL_EN + +#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_MASK 0x00010000U +#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_SHIFT 16U +#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WIDTH 1U +#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOCLR 0U +#define LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM_WOSET 0U +#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_77 +#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_77__PI_NO_MEMORY_DM + +#define LPDDR4__DENALI_PI_78_READ_MASK 0x010003FFU +#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x010003FFU +#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_SHIFT 0U +#define LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_78 +#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_78__PI_TDFI_WDQLVL_WW + +#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_MASK 0x00010000U +#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT 16U +#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH 1U +#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR 0U +#define LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET 0U +#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_78 +#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_78__PI_SWLVL_SM2_DM_NIBBLE_START + +#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_MASK 0x01000000U +#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_SHIFT 24U +#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WIDTH 1U +#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOCLR 0U +#define LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE_WOSET 0U +#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_78 +#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_78__PI_WDQLVL_NIBBLE_MODE + +#define LPDDR4__DENALI_PI_79_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_79 +#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_OSC_EN + +#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN_WOSET 0U +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_79 +#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_79__PI_DQS_OSC_PERIOD_EN + +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN_WOSET 0U +#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_79 +#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_EN + +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT 24U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH 1U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR 0U +#define LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN_WOSET 0U +#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_79 +#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_79__PI_WDQLVL_PDA_VREF_TRAIN + +#define LPDDR4__DENALI_PI_80_READ_MASK 0x07030F01U +#define LPDDR4__DENALI_PI_80_WRITE_MASK 0x07030F01U +#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_MASK 0x00000001U +#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_SHIFT 0U +#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN_WOSET 0U +#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_80 +#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_80__PI_PARALLEL_WDQLVL_EN + +#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_SHIFT 8U +#define LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK_WIDTH 4U +#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_80 +#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_80__PI_DBILVL_RESP_MASK + +#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_MASK 0x00030000U +#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_SHIFT 16U +#define LPDDR4__DENALI_PI_80__PI_BANK_DIFF_WIDTH 2U +#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_80 +#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_80__PI_BANK_DIFF + +#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_MASK 0x07000000U +#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_SHIFT 24U +#define LPDDR4__DENALI_PI_80__PI_ROW_DIFF_WIDTH 3U +#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_80 +#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_80__PI_ROW_DIFF + +#define LPDDR4__DENALI_PI_81_READ_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0F0F0F1FU +#define LPDDR4__DENALI_PI_81__PI_TCCD_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_81__PI_TCCD_SHIFT 0U +#define LPDDR4__DENALI_PI_81__PI_TCCD_WIDTH 5U +#define LPDDR4__PI_TCCD__REG DENALI_PI_81 +#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_81__PI_TCCD + +#define LPDDR4__DENALI_PI_81__PI_RESERVED7_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_81__PI_RESERVED7_SHIFT 8U +#define LPDDR4__DENALI_PI_81__PI_RESERVED7_WIDTH 4U +#define LPDDR4__PI_RESERVED7__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_81__PI_RESERVED7 + +#define LPDDR4__DENALI_PI_81__PI_RESERVED8_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_81__PI_RESERVED8_SHIFT 16U +#define LPDDR4__DENALI_PI_81__PI_RESERVED8_WIDTH 4U +#define LPDDR4__PI_RESERVED8__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_81__PI_RESERVED8 + +#define LPDDR4__DENALI_PI_81__PI_RESERVED9_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_81__PI_RESERVED9_SHIFT 24U +#define LPDDR4__DENALI_PI_81__PI_RESERVED9_WIDTH 4U +#define LPDDR4__PI_RESERVED9__REG DENALI_PI_81 +#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_81__PI_RESERVED9 + +#define LPDDR4__DENALI_PI_82_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_82_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_82__PI_RESERVED10_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_82__PI_RESERVED10_SHIFT 0U +#define LPDDR4__DENALI_PI_82__PI_RESERVED10_WIDTH 4U +#define LPDDR4__PI_RESERVED10__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_82__PI_RESERVED10 + +#define LPDDR4__DENALI_PI_82__PI_RESERVED11_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_82__PI_RESERVED11_SHIFT 8U +#define LPDDR4__DENALI_PI_82__PI_RESERVED11_WIDTH 4U +#define LPDDR4__PI_RESERVED11__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_82__PI_RESERVED11 + +#define LPDDR4__DENALI_PI_82__PI_RESERVED12_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_82__PI_RESERVED12_SHIFT 16U +#define LPDDR4__DENALI_PI_82__PI_RESERVED12_WIDTH 4U +#define LPDDR4__PI_RESERVED12__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_82__PI_RESERVED12 + +#define LPDDR4__DENALI_PI_82__PI_RESERVED13_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_82__PI_RESERVED13_SHIFT 24U +#define LPDDR4__DENALI_PI_82__PI_RESERVED13_WIDTH 4U +#define LPDDR4__PI_RESERVED13__REG DENALI_PI_82 +#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_82__PI_RESERVED13 + +#define LPDDR4__DENALI_PI_83_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_83_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_83__PI_RESERVED14_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_83__PI_RESERVED14_SHIFT 0U +#define LPDDR4__DENALI_PI_83__PI_RESERVED14_WIDTH 4U +#define LPDDR4__PI_RESERVED14__REG DENALI_PI_83 +#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_83__PI_RESERVED14 + +#define LPDDR4__DENALI_PI_83__PI_RESERVED15_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_83__PI_RESERVED15_SHIFT 8U +#define LPDDR4__DENALI_PI_83__PI_RESERVED15_WIDTH 4U +#define LPDDR4__PI_RESERVED15__REG DENALI_PI_83 +#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_83__PI_RESERVED15 + +#define LPDDR4__DENALI_PI_83__PI_RESERVED16_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_83__PI_RESERVED16_SHIFT 16U +#define LPDDR4__DENALI_PI_83__PI_RESERVED16_WIDTH 4U +#define LPDDR4__PI_RESERVED16__REG DENALI_PI_83 +#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_83__PI_RESERVED16 + +#define LPDDR4__DENALI_PI_83__PI_RESERVED17_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_83__PI_RESERVED17_SHIFT 24U +#define LPDDR4__DENALI_PI_83__PI_RESERVED17_WIDTH 4U +#define LPDDR4__PI_RESERVED17__REG DENALI_PI_83 +#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_83__PI_RESERVED17 + +#define LPDDR4__DENALI_PI_84_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_84_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_84__PI_RESERVED18_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_84__PI_RESERVED18_SHIFT 0U +#define LPDDR4__DENALI_PI_84__PI_RESERVED18_WIDTH 4U +#define LPDDR4__PI_RESERVED18__REG DENALI_PI_84 +#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_84__PI_RESERVED18 + +#define LPDDR4__DENALI_PI_84__PI_RESERVED19_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_84__PI_RESERVED19_SHIFT 8U +#define LPDDR4__DENALI_PI_84__PI_RESERVED19_WIDTH 4U +#define LPDDR4__PI_RESERVED19__REG DENALI_PI_84 +#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_84__PI_RESERVED19 + +#define LPDDR4__DENALI_PI_84__PI_RESERVED20_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_84__PI_RESERVED20_SHIFT 16U +#define LPDDR4__DENALI_PI_84__PI_RESERVED20_WIDTH 4U +#define LPDDR4__PI_RESERVED20__REG DENALI_PI_84 +#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_84__PI_RESERVED20 + +#define LPDDR4__DENALI_PI_84__PI_RESERVED21_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_84__PI_RESERVED21_SHIFT 24U +#define LPDDR4__DENALI_PI_84__PI_RESERVED21_WIDTH 4U +#define LPDDR4__PI_RESERVED21__REG DENALI_PI_84 +#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_84__PI_RESERVED21 + +#define LPDDR4__DENALI_PI_85_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_85_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_85__PI_RESERVED22_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_85__PI_RESERVED22_SHIFT 0U +#define LPDDR4__DENALI_PI_85__PI_RESERVED22_WIDTH 4U +#define LPDDR4__PI_RESERVED22__REG DENALI_PI_85 +#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_85__PI_RESERVED22 + +#define LPDDR4__DENALI_PI_85__PI_RESERVED23_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_85__PI_RESERVED23_SHIFT 8U +#define LPDDR4__DENALI_PI_85__PI_RESERVED23_WIDTH 4U +#define LPDDR4__PI_RESERVED23__REG DENALI_PI_85 +#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_85__PI_RESERVED23 + +#define LPDDR4__DENALI_PI_85__PI_RESERVED24_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_85__PI_RESERVED24_SHIFT 16U +#define LPDDR4__DENALI_PI_85__PI_RESERVED24_WIDTH 4U +#define LPDDR4__PI_RESERVED24__REG DENALI_PI_85 +#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_85__PI_RESERVED24 + +#define LPDDR4__DENALI_PI_85__PI_RESERVED25_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_85__PI_RESERVED25_SHIFT 24U +#define LPDDR4__DENALI_PI_85__PI_RESERVED25_WIDTH 4U +#define LPDDR4__PI_RESERVED25__REG DENALI_PI_85 +#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_85__PI_RESERVED25 + +#define LPDDR4__DENALI_PI_86_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_86_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_86__PI_RESERVED26_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_86__PI_RESERVED26_SHIFT 0U +#define LPDDR4__DENALI_PI_86__PI_RESERVED26_WIDTH 4U +#define LPDDR4__PI_RESERVED26__REG DENALI_PI_86 +#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_86__PI_RESERVED26 + +#define LPDDR4__DENALI_PI_87_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_87_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_87__PI_INT_STATUS_WIDTH 30U +#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_87 +#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_87__PI_INT_STATUS + +#define LPDDR4__DENALI_PI_88__PI_INT_ACK_MASK 0x1FFFFFFFU +#define LPDDR4__DENALI_PI_88__PI_INT_ACK_SHIFT 0U +#define LPDDR4__DENALI_PI_88__PI_INT_ACK_WIDTH 29U +#define LPDDR4__PI_INT_ACK__REG DENALI_PI_88 +#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_88__PI_INT_ACK + +#define LPDDR4__DENALI_PI_89_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_89_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_INT_MASK_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_89__PI_INT_MASK_SHIFT 0U +#define LPDDR4__DENALI_PI_89__PI_INT_MASK_WIDTH 30U +#define LPDDR4__PI_INT_MASK__REG DENALI_PI_89 +#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_89__PI_INT_MASK + +#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_90 +#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_EXP_DATA_0 + +#define LPDDR4__DENALI_PI_91_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_91_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_91 +#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_EXP_DATA_1 + +#define LPDDR4__DENALI_PI_92_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_92_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_92 +#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_92__PI_BIST_EXP_DATA_2 + +#define LPDDR4__DENALI_PI_93_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_93_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3_WIDTH 32U +#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_93 +#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_93__PI_BIST_EXP_DATA_3 + +#define LPDDR4__DENALI_PI_94_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_94_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_94 +#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_94__PI_BIST_FAIL_DATA_0 + +#define LPDDR4__DENALI_PI_95_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_95_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_95 +#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_95__PI_BIST_FAIL_DATA_1 + +#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_96 +#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_96__PI_BIST_FAIL_DATA_2 + +#define LPDDR4__DENALI_PI_97_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_97_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_97 +#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_97__PI_BIST_FAIL_DATA_3 + +#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_SHIFT 0U +#define LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0_WIDTH 32U +#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_98 +#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_FAIL_ADDR_0 + +#define LPDDR4__DENALI_PI_99_READ_MASK 0x011F3F07U +#define LPDDR4__DENALI_PI_99_WRITE_MASK 0x011F3F07U +#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_SHIFT 0U +#define LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1_WIDTH 3U +#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_99 +#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_FAIL_ADDR_1 + +#define LPDDR4__DENALI_PI_99__PI_BSTLEN_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_99__PI_BSTLEN_SHIFT 8U +#define LPDDR4__DENALI_PI_99__PI_BSTLEN_WIDTH 6U +#define LPDDR4__PI_BSTLEN__REG DENALI_PI_99 +#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_99__PI_BSTLEN + +#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_SHIFT 16U +#define LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK_WIDTH 5U +#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_99 +#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_99__PI_LONG_COUNT_MASK + +#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN_WOSET 0U +#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_99 +#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_99__PI_CMD_SWAP_EN + +#define LPDDR4__DENALI_PI_100_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_SHIFT 0U +#define LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX_WIDTH 5U +#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_100 +#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_100__PI_PARITY_IN_MUX + +#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_SHIFT 8U +#define LPDDR4__DENALI_PI_100__PI_ACT_N_MUX_WIDTH 5U +#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_100 +#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_100__PI_ACT_N_MUX + +#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_SHIFT 16U +#define LPDDR4__DENALI_PI_100__PI_BG_MUX_0_WIDTH 5U +#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_100 +#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_0 + +#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_SHIFT 24U +#define LPDDR4__DENALI_PI_100__PI_BG_MUX_1_WIDTH 5U +#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_100 +#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_100__PI_BG_MUX_1 + +#define LPDDR4__DENALI_PI_101_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_101_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_SHIFT 0U +#define LPDDR4__DENALI_PI_101__PI_RAS_N_MUX_WIDTH 5U +#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_101 +#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_RAS_N_MUX + +#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_SHIFT 8U +#define LPDDR4__DENALI_PI_101__PI_CAS_N_MUX_WIDTH 5U +#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_101 +#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_CAS_N_MUX + +#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_SHIFT 16U +#define LPDDR4__DENALI_PI_101__PI_WE_N_MUX_WIDTH 5U +#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_101 +#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_101__PI_WE_N_MUX + +#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_SHIFT 24U +#define LPDDR4__DENALI_PI_101__PI_BANK_MUX_0_WIDTH 5U +#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_101 +#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_101__PI_BANK_MUX_0 + +#define LPDDR4__DENALI_PI_102_READ_MASK 0x0303011FU +#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0303011FU +#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_SHIFT 0U +#define LPDDR4__DENALI_PI_102__PI_BANK_MUX_1_WIDTH 5U +#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_102 +#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_102__PI_BANK_MUX_1 + +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN_WOSET 0U +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_102 +#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_EN + +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 16U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_102 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE0 + +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 24U +#define LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_102 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_102__PI_DATA_BYTE_SWAP_SLICE1 + +#define LPDDR4__DENALI_PI_103_READ_MASK 0x00010303U +#define LPDDR4__DENALI_PI_103_WRITE_MASK 0x00010303U +#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 0U +#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_103 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE2 + +#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000300U +#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 8U +#define LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_103 +#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_103__PI_DATA_BYTE_SWAP_SLICE3 + +#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_103 +#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_103__PI_CTRLUPD_REQ_PER_AREF_EN + +#define LPDDR4__DENALI_PI_104_READ_MASK 0x0703FFFFU +#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0703FFFFU +#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_SHIFT 0U +#define LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN_WIDTH 16U +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_104 +#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_104__PI_TDFI_CTRLUPD_MIN + +#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_MASK 0x00030000U +#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_SHIFT 16U +#define LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS_WIDTH 2U +#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_104 +#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_104__PI_UPDATE_ERROR_STATUS + +#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_MASK 0x07000000U +#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_SHIFT 24U +#define LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT_WIDTH 3U +#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_104 +#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_104__PI_TDFI_PARIN_LAT + +#define LPDDR4__DENALI_PI_105_READ_MASK 0xFF010301U +#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFF010301U +#define LPDDR4__DENALI_PI_105__PI_BIST_GO_MASK 0x00000001U +#define LPDDR4__DENALI_PI_105__PI_BIST_GO_SHIFT 0U +#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WIDTH 1U +#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOCLR 0U +#define LPDDR4__DENALI_PI_105__PI_BIST_GO_WOSET 0U +#define LPDDR4__PI_BIST_GO__REG DENALI_PI_105 +#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_105__PI_BIST_GO + +#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_MASK 0x00000300U +#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_SHIFT 8U +#define LPDDR4__DENALI_PI_105__PI_BIST_RESULT_WIDTH 2U +#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_105 +#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_105__PI_BIST_RESULT + +#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_MASK 0x00010000U +#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_SHIFT 16U +#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WIDTH 1U +#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOCLR 0U +#define LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE_WOSET 0U +#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_105 +#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_105__PI_BIST_LFSR_PATTERN_DONE + +#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_SHIFT 24U +#define LPDDR4__DENALI_PI_105__PI_ADDR_SPACE_WIDTH 8U +#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_105 +#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_105__PI_ADDR_SPACE + +#define LPDDR4__DENALI_PI_106_READ_MASK 0x00000101U +#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x00000101U +#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_SHIFT 0U +#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_106 +#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_DATA_CHECK + +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_MASK 0x00000100U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_SHIFT 8U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WIDTH 1U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOCLR 0U +#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK_WOSET 0U +#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_106 +#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_CHECK + +#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_SHIFT 0U +#define LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0_WIDTH 32U +#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_107 +#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_START_ADDRESS_0 + +#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000FF07U +#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000FF07U +#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_MASK 0x00000007U +#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_SHIFT 0U +#define LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1_WIDTH 3U +#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_108 +#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_START_ADDRESS_1 + +#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_SHIFT 8U +#define LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN_WIDTH 8U +#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_108 +#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_108__PI_MBIST_INIT_PATTERN + +#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_SHIFT 0U +#define LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_109 +#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_DATA_MASK_0 + +#define LPDDR4__DENALI_PI_110_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_110_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_SHIFT 0U +#define LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1_WIDTH 32U +#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_110 +#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_DATA_MASK_1 + +#define LPDDR4__DENALI_PI_111_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_111_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_SHIFT 0U +#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_111 +#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_COUNT + +#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_SHIFT 16U +#define LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP_WIDTH 12U +#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_111 +#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_111__PI_BIST_ERR_STOP + +#define LPDDR4__DENALI_PI_112_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_112_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_112 +#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_0_0 + +#define LPDDR4__DENALI_PI_113_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_113_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_113 +#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_0_1 + +#define LPDDR4__DENALI_PI_114_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_114_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_114 +#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_1_0 + +#define LPDDR4__DENALI_PI_115_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_115_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_115 +#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_1_1 + +#define LPDDR4__DENALI_PI_116_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_116_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_116 +#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_2_0 + +#define LPDDR4__DENALI_PI_117_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_117_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_117 +#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_2_1 + +#define LPDDR4__DENALI_PI_118_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_118_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_SHIFT 0U +#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_118 +#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_3_0 + +#define LPDDR4__DENALI_PI_119_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_119_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_SHIFT 0U +#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_119 +#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_3_1 + +#define LPDDR4__DENALI_PI_120_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_120_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_SHIFT 0U +#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_120 +#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_4_0 + +#define LPDDR4__DENALI_PI_121_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_121_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_SHIFT 0U +#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_121 +#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_4_1 + +#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_SHIFT 0U +#define LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_122 +#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_ADDR_MASK_5_0 + +#define LPDDR4__DENALI_PI_123_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_123_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_SHIFT 0U +#define LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_123 +#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_ADDR_MASK_5_1 + +#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_SHIFT 0U +#define LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_124 +#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_124__PI_BIST_ADDR_MASK_6_0 + +#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_SHIFT 0U +#define LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_125 +#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_125__PI_BIST_ADDR_MASK_6_1 + +#define LPDDR4__DENALI_PI_126_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_126_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_SHIFT 0U +#define LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_126 +#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_ADDR_MASK_7_0 + +#define LPDDR4__DENALI_PI_127_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_SHIFT 0U +#define LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_127 +#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_ADDR_MASK_7_1 + +#define LPDDR4__DENALI_PI_128_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_128_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_SHIFT 0U +#define LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_128 +#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_128__PI_BIST_ADDR_MASK_8_0 + +#define LPDDR4__DENALI_PI_129_READ_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_SHIFT 0U +#define LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_129 +#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_129__PI_BIST_ADDR_MASK_8_1 + +#define LPDDR4__DENALI_PI_130_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_130_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_SHIFT 0U +#define LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0_WIDTH 32U +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_130 +#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_130__PI_BIST_ADDR_MASK_9_0 + +#define LPDDR4__DENALI_PI_131_READ_MASK 0x0303070FU +#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x0303070FU +#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_SHIFT 0U +#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1_WIDTH 4U +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MASK_9_1 + +#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_MASK 0x00000700U +#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_SHIFT 8U +#define LPDDR4__DENALI_PI_131__PI_BIST_MODE_WIDTH 3U +#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_MODE + +#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_MASK 0x00030000U +#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_SHIFT 16U +#define LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_ADDR_MODE + +#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_MASK 0x03000000U +#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_SHIFT 24U +#define LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE_WIDTH 2U +#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_131 +#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_131__PI_BIST_PAT_MODE + +#define LPDDR4__DENALI_PI_132_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_132_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_SHIFT 0U +#define LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_132 +#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_132__PI_BIST_USER_PAT_0 + +#define LPDDR4__DENALI_PI_133_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_133_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_SHIFT 0U +#define LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_133 +#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_133__PI_BIST_USER_PAT_1 + +#define LPDDR4__DENALI_PI_134_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_134_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_SHIFT 0U +#define LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_134 +#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_134__PI_BIST_USER_PAT_2 + +#define LPDDR4__DENALI_PI_135_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_135_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_SHIFT 0U +#define LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3_WIDTH 32U +#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_135 +#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_135__PI_BIST_USER_PAT_3 + +#define LPDDR4__DENALI_PI_136_READ_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_SHIFT 0U +#define LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM_WIDTH 7U +#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_136 +#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_136__PI_BIST_PAT_NUM + +#define LPDDR4__DENALI_PI_137_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_137_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_SHIFT 0U +#define LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_137 +#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_137__PI_BIST_STAGE_0 + +#define LPDDR4__DENALI_PI_138_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_138_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_SHIFT 0U +#define LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_138 +#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_138__PI_BIST_STAGE_1 + +#define LPDDR4__DENALI_PI_139_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_139_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_SHIFT 0U +#define LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_139 +#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_139__PI_BIST_STAGE_2 + +#define LPDDR4__DENALI_PI_140_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_SHIFT 0U +#define LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_140 +#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_140__PI_BIST_STAGE_3 + +#define LPDDR4__DENALI_PI_141_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_SHIFT 0U +#define LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_141 +#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_141__PI_BIST_STAGE_4 + +#define LPDDR4__DENALI_PI_142_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_SHIFT 0U +#define LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_142 +#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_142__PI_BIST_STAGE_5 + +#define LPDDR4__DENALI_PI_143_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_SHIFT 0U +#define LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_143 +#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_143__PI_BIST_STAGE_6 + +#define LPDDR4__DENALI_PI_144_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_SHIFT 0U +#define LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7_WIDTH 30U +#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_144 +#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_144__PI_BIST_STAGE_7 + +#define LPDDR4__DENALI_PI_145_READ_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_145_WRITE_MASK 0x0101010FU +#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_SHIFT 0U +#define LPDDR4__DENALI_PI_145__PI_COL_DIFF_WIDTH 4U +#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_145 +#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_145__PI_COL_DIFF + +#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN_WOSET 0U +#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_145 +#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_145__PI_BG_ROTATE_EN + +#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_SHIFT 16U +#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WIDTH 1U +#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOCLR 0U +#define LPDDR4__DENALI_PI_145__PI_CRC_CALC_WOSET 0U +#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_145 +#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_145__PI_CRC_CALC + +#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_MASK 0x01000000U +#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_SHIFT 24U +#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN_WOSET 0U +#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_145 +#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_145__PI_SELF_REFRESH_EN + +#define LPDDR4__DENALI_PI_146_READ_MASK 0x00010101U +#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x00010101U +#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT 0U +#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146 +#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_MC_PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_SHIFT 8U +#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT_WOSET 0U +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_146 +#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_146__PI_PWRUP_SREFRESH_EXIT + +#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x00010000U +#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 16U +#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_146 +#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_146__PI_SREFRESH_EXIT_NO_REFRESH + +#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ_WOSET 0U +#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_146 +#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_146__PI_SREF_ENTRY_REQ + +#define LPDDR4__DENALI_PI_147_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_MASK 0x00000001U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_SHIFT 0U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_147 +#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_BT_INIT + +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_MASK 0x00000100U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_SHIFT 8U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT_WOSET 0U +#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_147 +#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_MRW_INIT + +#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x00010000U +#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 16U +#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_147 +#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_PHY_IND_TRAIN_INIT + +#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT_WOSET 0U +#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_147 +#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_147__PI_NO_AUTO_MRR_INIT + +#define LPDDR4__DENALI_PI_148_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_SHIFT 0U +#define LPDDR4__DENALI_PI_148__PI_TRST_PWRON_WIDTH 32U +#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_148 +#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_148__PI_TRST_PWRON + +#define LPDDR4__DENALI_PI_149_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_149_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_SHIFT 0U +#define LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE_WIDTH 32U +#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_149 +#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_149__PI_CKE_INACTIVE + +#define LPDDR4__DENALI_PI_150_READ_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_150_WRITE_MASK 0xFFFF0101U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_MASK 0x00000001U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_SHIFT 0U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_WOSET 0U +#define LPDDR4__PI_DLL_RST__REG DENALI_PI_150 +#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST + +#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_MASK 0x00000100U +#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_SHIFT 8U +#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN_WOSET 0U +#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_150 +#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_150__PI_DRAM_INIT_EN + +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_SHIFT 16U +#define LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY_WIDTH 16U +#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_150 +#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_150__PI_DLL_RST_DELAY + +#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_SHIFT 0U +#define LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY_WIDTH 8U +#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_151 +#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_151__PI_DLL_RST_ADJ_DLY + +#define LPDDR4__DENALI_PI_152_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_152_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG_WIDTH 26U +#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_152 +#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_152__PI_WRITE_MODEREG + +#define LPDDR4__DENALI_PI_153_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_SHIFT 0U +#define LPDDR4__DENALI_PI_153__PI_MRW_STATUS_WIDTH 8U +#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_153 +#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_153__PI_MRW_STATUS + +#define LPDDR4__DENALI_PI_153__PI_RESERVED27_MASK 0x00000100U +#define LPDDR4__DENALI_PI_153__PI_RESERVED27_SHIFT 8U +#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WIDTH 1U +#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOCLR 0U +#define LPDDR4__DENALI_PI_153__PI_RESERVED27_WOSET 0U +#define LPDDR4__PI_RESERVED27__REG DENALI_PI_153 +#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_153__PI_RESERVED27 + +#define LPDDR4__DENALI_PI_154_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_SHIFT 0U +#define LPDDR4__DENALI_PI_154__PI_READ_MODEREG_WIDTH 17U +#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_154 +#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_154__PI_READ_MODEREG + +#define LPDDR4__DENALI_PI_155_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_155 +#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_155__PI_PERIPHERAL_MRR_DATA_0 + +#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_MASK 0x01000000U +#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_SHIFT 24U +#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WIDTH 1U +#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOCLR 0U +#define LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT_WOSET 0U +#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_155 +#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_155__PI_NO_ZQ_INIT + +#define LPDDR4__DENALI_PI_156_READ_MASK 0x0101000FU +#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x0101000FU +#define LPDDR4__DENALI_PI_156__PI_RESERVED28_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_156__PI_RESERVED28_SHIFT 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED28_WIDTH 4U +#define LPDDR4__PI_RESERVED28__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_156__PI_RESERVED28 + +#define LPDDR4__DENALI_PI_156__PI_RESERVED29_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_156__PI_RESERVED29_SHIFT 8U +#define LPDDR4__DENALI_PI_156__PI_RESERVED29_WIDTH 4U +#define LPDDR4__PI_RESERVED29__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_156__PI_RESERVED29 + +#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_MASK 0x00010000U +#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_SHIFT 16U +#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING_WOSET 0U +#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_156 +#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_156__PI_ZQ_REQ_PENDING + +#define LPDDR4__DENALI_PI_156__PI_RESERVED30_MASK 0x01000000U +#define LPDDR4__DENALI_PI_156__PI_RESERVED30_SHIFT 24U +#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WIDTH 1U +#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOCLR 0U +#define LPDDR4__DENALI_PI_156__PI_RESERVED30_WOSET 0U +#define LPDDR4__PI_RESERVED30__REG DENALI_PI_156 +#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_156__PI_RESERVED30 + +#define LPDDR4__DENALI_PI_157_READ_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_157_WRITE_MASK 0xFF010F07U +#define LPDDR4__DENALI_PI_157__PI_RESERVED31_MASK 0x00000007U +#define LPDDR4__DENALI_PI_157__PI_RESERVED31_SHIFT 0U +#define LPDDR4__DENALI_PI_157__PI_RESERVED31_WIDTH 3U +#define LPDDR4__PI_RESERVED31__REG DENALI_PI_157 +#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_157__PI_RESERVED31 + +#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_SHIFT 8U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_157 +#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_SRC_SEL_0 + +#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_SHIFT 16U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WIDTH 1U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOCLR 0U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_157 +#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_CAP_SEL_0 + +#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_SHIFT 24U +#define LPDDR4__DENALI_PI_157__PI_MONITOR_0_WIDTH 8U +#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_157 +#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_157__PI_MONITOR_0 + +#define LPDDR4__DENALI_PI_158_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_SHIFT 0U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_158 +#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_1 + +#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_SHIFT 8U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WIDTH 1U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOCLR 0U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_158 +#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_CAP_SEL_1 + +#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_SHIFT 16U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_1_WIDTH 8U +#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_158 +#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_1 + +#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_SHIFT 24U +#define LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_158 +#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_158__PI_MONITOR_SRC_SEL_2 + +#define LPDDR4__DENALI_PI_159_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_SHIFT 0U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WIDTH 1U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOCLR 0U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_159 +#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_2 + +#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_SHIFT 8U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_2_WIDTH 8U +#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_159 +#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_2 + +#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_SHIFT 16U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_159 +#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_SRC_SEL_3 + +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_SHIFT 24U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WIDTH 1U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOCLR 0U +#define LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_159 +#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_159__PI_MONITOR_CAP_SEL_3 + +#define LPDDR4__DENALI_PI_160_READ_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_160_WRITE_MASK 0xFF010FFFU +#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_SHIFT 0U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_3_WIDTH 8U +#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_160 +#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_3 + +#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_SHIFT 8U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_160 +#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_SRC_SEL_4 + +#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_SHIFT 16U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WIDTH 1U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOCLR 0U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_160 +#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_CAP_SEL_4 + +#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_SHIFT 24U +#define LPDDR4__DENALI_PI_160__PI_MONITOR_4_WIDTH 8U +#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_160 +#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_160__PI_MONITOR_4 + +#define LPDDR4__DENALI_PI_161_READ_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0FFF010FU +#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_SHIFT 0U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_161 +#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_5 + +#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_SHIFT 8U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WIDTH 1U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOCLR 0U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_161 +#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_CAP_SEL_5 + +#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_SHIFT 16U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_5_WIDTH 8U +#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_161 +#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_5 + +#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_SHIFT 24U +#define LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_161 +#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_161__PI_MONITOR_SRC_SEL_6 + +#define LPDDR4__DENALI_PI_162_READ_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x010FFF01U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_SHIFT 0U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_162 +#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_6 + +#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_SHIFT 8U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_6_WIDTH 8U +#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_162 +#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_6 + +#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_SHIFT 16U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7_WIDTH 4U +#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_162 +#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_SRC_SEL_7 + +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_SHIFT 24U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WIDTH 1U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOCLR 0U +#define LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7_WOSET 0U +#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_162 +#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_162__PI_MONITOR_CAP_SEL_7 + +#define LPDDR4__DENALI_PI_163_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_163_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_SHIFT 0U +#define LPDDR4__DENALI_PI_163__PI_MONITOR_7_WIDTH 8U +#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_163 +#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_163__PI_MONITOR_7 + +#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_SHIFT 0U +#define LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE_WIDTH 8U +#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_164 +#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_164__PI_MONITOR_STROBE + +#define LPDDR4__DENALI_PI_165_READ_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x011F1F01U +#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_MASK 0x00000001U +#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_SHIFT 0U +#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WIDTH 1U +#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOCLR 0U +#define LPDDR4__DENALI_PI_165__PI_DLL_LOCK_WOSET 0U +#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_165 +#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_165__PI_DLL_LOCK + +#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_SHIFT 8U +#define LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS_WIDTH 5U +#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_165 +#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_165__PI_FREQ_NUMBER_STATUS + +#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_SHIFT 16U +#define LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM_WIDTH 5U +#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_165 +#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_165__PI_FREQ_RETENTION_NUM + +#define LPDDR4__DENALI_PI_165__PI_RESERVED32_MASK 0x01000000U +#define LPDDR4__DENALI_PI_165__PI_RESERVED32_SHIFT 24U +#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WIDTH 1U +#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOCLR 0U +#define LPDDR4__DENALI_PI_165__PI_RESERVED32_WOSET 0U +#define LPDDR4__PI_RESERVED32__REG DENALI_PI_165 +#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_165__PI_RESERVED32 + +#define LPDDR4__DENALI_PI_166_READ_MASK 0x01010103U +#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x01010103U +#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_MASK 0x00000003U +#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_SHIFT 0U +#define LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE_WIDTH 2U +#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_166 +#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_166__PI_PHYMSTR_TYPE + +#define LPDDR4__DENALI_PI_166__PI_RESERVED33_MASK 0x00000100U +#define LPDDR4__DENALI_PI_166__PI_RESERVED33_SHIFT 8U +#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WIDTH 1U +#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOCLR 0U +#define LPDDR4__DENALI_PI_166__PI_RESERVED33_WOSET 0U +#define LPDDR4__PI_RESERVED33__REG DENALI_PI_166 +#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_166__PI_RESERVED33 + +#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN_WOSET 0U +#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_166 +#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_166__PI_POWER_REDUC_EN + +#define LPDDR4__DENALI_PI_166__PI_RESERVED34_MASK 0x01000000U +#define LPDDR4__DENALI_PI_166__PI_RESERVED34_SHIFT 24U +#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WIDTH 1U +#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOCLR 0U +#define LPDDR4__DENALI_PI_166__PI_RESERVED34_WOSET 0U +#define LPDDR4__PI_RESERVED34__REG DENALI_PI_166 +#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_166__PI_RESERVED34 + +#define LPDDR4__DENALI_PI_167_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_167__PI_RESERVED35_MASK 0x00000001U +#define LPDDR4__DENALI_PI_167__PI_RESERVED35_SHIFT 0U +#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WIDTH 1U +#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOCLR 0U +#define LPDDR4__DENALI_PI_167__PI_RESERVED35_WOSET 0U +#define LPDDR4__PI_RESERVED35__REG DENALI_PI_167 +#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_167__PI_RESERVED35 + +#define LPDDR4__DENALI_PI_167__PI_RESERVED36_MASK 0x00000100U +#define LPDDR4__DENALI_PI_167__PI_RESERVED36_SHIFT 8U +#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WIDTH 1U +#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOCLR 0U +#define LPDDR4__DENALI_PI_167__PI_RESERVED36_WOSET 0U +#define LPDDR4__PI_RESERVED36__REG DENALI_PI_167 +#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_167__PI_RESERVED36 + +#define LPDDR4__DENALI_PI_167__PI_RESERVED37_MASK 0x00010000U +#define LPDDR4__DENALI_PI_167__PI_RESERVED37_SHIFT 16U +#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WIDTH 1U +#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOCLR 0U +#define LPDDR4__DENALI_PI_167__PI_RESERVED37_WOSET 0U +#define LPDDR4__PI_RESERVED37__REG DENALI_PI_167 +#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_167__PI_RESERVED37 + +#define LPDDR4__DENALI_PI_167__PI_RESERVED38_MASK 0x01000000U +#define LPDDR4__DENALI_PI_167__PI_RESERVED38_SHIFT 24U +#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WIDTH 1U +#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOCLR 0U +#define LPDDR4__DENALI_PI_167__PI_RESERVED38_WOSET 0U +#define LPDDR4__PI_RESERVED38__REG DENALI_PI_167 +#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_167__PI_RESERVED38 + +#define LPDDR4__DENALI_PI_168_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_168__PI_RESERVED39_MASK 0x00000001U +#define LPDDR4__DENALI_PI_168__PI_RESERVED39_SHIFT 0U +#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WIDTH 1U +#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOCLR 0U +#define LPDDR4__DENALI_PI_168__PI_RESERVED39_WOSET 0U +#define LPDDR4__PI_RESERVED39__REG DENALI_PI_168 +#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_168__PI_RESERVED39 + +#define LPDDR4__DENALI_PI_168__PI_RESERVED40_MASK 0x00000100U +#define LPDDR4__DENALI_PI_168__PI_RESERVED40_SHIFT 8U +#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WIDTH 1U +#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOCLR 0U +#define LPDDR4__DENALI_PI_168__PI_RESERVED40_WOSET 0U +#define LPDDR4__PI_RESERVED40__REG DENALI_PI_168 +#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_168__PI_RESERVED40 + +#define LPDDR4__DENALI_PI_168__PI_RESERVED41_MASK 0x00010000U +#define LPDDR4__DENALI_PI_168__PI_RESERVED41_SHIFT 16U +#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WIDTH 1U +#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOCLR 0U +#define LPDDR4__DENALI_PI_168__PI_RESERVED41_WOSET 0U +#define LPDDR4__PI_RESERVED41__REG DENALI_PI_168 +#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_168__PI_RESERVED41 + +#define LPDDR4__DENALI_PI_168__PI_RESERVED42_MASK 0x01000000U +#define LPDDR4__DENALI_PI_168__PI_RESERVED42_SHIFT 24U +#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WIDTH 1U +#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOCLR 0U +#define LPDDR4__DENALI_PI_168__PI_RESERVED42_WOSET 0U +#define LPDDR4__PI_RESERVED42__REG DENALI_PI_168 +#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_168__PI_RESERVED42 + +#define LPDDR4__DENALI_PI_169_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_169__PI_RESERVED43_MASK 0x00000001U +#define LPDDR4__DENALI_PI_169__PI_RESERVED43_SHIFT 0U +#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WIDTH 1U +#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOCLR 0U +#define LPDDR4__DENALI_PI_169__PI_RESERVED43_WOSET 0U +#define LPDDR4__PI_RESERVED43__REG DENALI_PI_169 +#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_169__PI_RESERVED43 + +#define LPDDR4__DENALI_PI_169__PI_RESERVED44_MASK 0x00000100U +#define LPDDR4__DENALI_PI_169__PI_RESERVED44_SHIFT 8U +#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WIDTH 1U +#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOCLR 0U +#define LPDDR4__DENALI_PI_169__PI_RESERVED44_WOSET 0U +#define LPDDR4__PI_RESERVED44__REG DENALI_PI_169 +#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_169__PI_RESERVED44 + +#define LPDDR4__DENALI_PI_169__PI_RESERVED45_MASK 0x00010000U +#define LPDDR4__DENALI_PI_169__PI_RESERVED45_SHIFT 16U +#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WIDTH 1U +#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOCLR 0U +#define LPDDR4__DENALI_PI_169__PI_RESERVED45_WOSET 0U +#define LPDDR4__PI_RESERVED45__REG DENALI_PI_169 +#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_169__PI_RESERVED45 + +#define LPDDR4__DENALI_PI_169__PI_RESERVED46_MASK 0x01000000U +#define LPDDR4__DENALI_PI_169__PI_RESERVED46_SHIFT 24U +#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WIDTH 1U +#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOCLR 0U +#define LPDDR4__DENALI_PI_169__PI_RESERVED46_WOSET 0U +#define LPDDR4__PI_RESERVED46__REG DENALI_PI_169 +#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_169__PI_RESERVED46 + +#define LPDDR4__DENALI_PI_170_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_170__PI_RESERVED47_MASK 0x00000001U +#define LPDDR4__DENALI_PI_170__PI_RESERVED47_SHIFT 0U +#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WIDTH 1U +#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOCLR 0U +#define LPDDR4__DENALI_PI_170__PI_RESERVED47_WOSET 0U +#define LPDDR4__PI_RESERVED47__REG DENALI_PI_170 +#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_170__PI_RESERVED47 + +#define LPDDR4__DENALI_PI_170__PI_RESERVED48_MASK 0x00000100U +#define LPDDR4__DENALI_PI_170__PI_RESERVED48_SHIFT 8U +#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WIDTH 1U +#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOCLR 0U +#define LPDDR4__DENALI_PI_170__PI_RESERVED48_WOSET 0U +#define LPDDR4__PI_RESERVED48__REG DENALI_PI_170 +#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_170__PI_RESERVED48 + +#define LPDDR4__DENALI_PI_170__PI_RESERVED49_MASK 0x00010000U +#define LPDDR4__DENALI_PI_170__PI_RESERVED49_SHIFT 16U +#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WIDTH 1U +#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOCLR 0U +#define LPDDR4__DENALI_PI_170__PI_RESERVED49_WOSET 0U +#define LPDDR4__PI_RESERVED49__REG DENALI_PI_170 +#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_170__PI_RESERVED49 + +#define LPDDR4__DENALI_PI_170__PI_RESERVED50_MASK 0x01000000U +#define LPDDR4__DENALI_PI_170__PI_RESERVED50_SHIFT 24U +#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WIDTH 1U +#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOCLR 0U +#define LPDDR4__DENALI_PI_170__PI_RESERVED50_WOSET 0U +#define LPDDR4__PI_RESERVED50__REG DENALI_PI_170 +#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_170__PI_RESERVED50 + +#define LPDDR4__DENALI_PI_171_READ_MASK 0x00FF0101U +#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x00FF0101U +#define LPDDR4__DENALI_PI_171__PI_RESERVED51_MASK 0x00000001U +#define LPDDR4__DENALI_PI_171__PI_RESERVED51_SHIFT 0U +#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WIDTH 1U +#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOCLR 0U +#define LPDDR4__DENALI_PI_171__PI_RESERVED51_WOSET 0U +#define LPDDR4__PI_RESERVED51__REG DENALI_PI_171 +#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_171__PI_RESERVED51 + +#define LPDDR4__DENALI_PI_171__PI_RESERVED52_MASK 0x00000100U +#define LPDDR4__DENALI_PI_171__PI_RESERVED52_SHIFT 8U +#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WIDTH 1U +#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOCLR 0U +#define LPDDR4__DENALI_PI_171__PI_RESERVED52_WOSET 0U +#define LPDDR4__PI_RESERVED52__REG DENALI_PI_171 +#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_171__PI_RESERVED52 + +#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_SHIFT 16U +#define LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_171 +#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_171__PI_WRLVL_MAX_STROBE_PEND + +#define LPDDR4__DENALI_PI_172_READ_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_SHIFT 0U +#define LPDDR4__DENALI_PI_172__PI_TREFBW_THR_WIDTH 9U +#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_172 +#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_172__PI_TREFBW_THR + +#define LPDDR4__DENALI_PI_173_READ_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U +#define LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_173 +#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_173__PI_FREQ_CHANGE_REG_COPY + +#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F011F01U +#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F011F01U +#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U +#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U +#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U +#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U +#define LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF_WOSET 0U +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_174 +#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_174__PI_FREQ_SEL_FROM_REGIF + +#define LPDDR4__DENALI_PI_174__PI_RESERVED53_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_174__PI_RESERVED53_SHIFT 8U +#define LPDDR4__DENALI_PI_174__PI_RESERVED53_WIDTH 5U +#define LPDDR4__PI_RESERVED53__REG DENALI_PI_174 +#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_174__PI_RESERVED53 + +#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_MASK 0x00010000U +#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_SHIFT 16U +#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WIDTH 1U +#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOCLR 0U +#define LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN_WOSET 0U +#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_174 +#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_174__PI_PARALLEL_CALVL_EN + +#define LPDDR4__DENALI_PI_174__PI_CATR_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_174__PI_CATR_SHIFT 24U +#define LPDDR4__DENALI_PI_174__PI_CATR_WIDTH 4U +#define LPDDR4__PI_CATR__REG DENALI_PI_174 +#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_174__PI_CATR + +#define LPDDR4__DENALI_PI_175_READ_MASK 0x01010101U +#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x01010101U +#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_MASK 0x00000001U +#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_SHIFT 0U +#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WIDTH 1U +#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOCLR 0U +#define LPDDR4__DENALI_PI_175__PI_NO_CATR_READ_WOSET 0U +#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_175 +#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_175__PI_NO_CATR_READ + +#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_MASK 0x00000100U +#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_SHIFT 8U +#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WIDTH 1U +#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOCLR 0U +#define LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE_WOSET 0U +#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_175 +#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_175__PI_MASK_INIT_COMPLETE + +#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_MASK 0x00010000U +#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_SHIFT 16U +#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WIDTH 1U +#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOCLR 0U +#define LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC_WOSET 0U +#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_175 +#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_175__PI_DISCONNECT_MC + +#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_MASK 0x01000000U +#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_SHIFT 24U +#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WIDTH 1U +#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOCLR 0U +#define LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ_WOSET 0U +#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_175 +#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_175__PI_DISABLE_PHYMSTR_REQ + +#define LPDDR4__DENALI_PI_176_READ_MASK 0xFFFF0701U +#define LPDDR4__DENALI_PI_176_WRITE_MASK 0xFFFF0701U +#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_MASK 0x00000001U +#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_SHIFT 0U +#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WIDTH 1U +#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOCLR 0U +#define LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START_WOSET 0U +#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_176 +#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_176__PI_NOTCARE_MC_INIT_START + +#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK 0x00000700U +#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT 8U +#define LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH 3U +#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_176 +#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_176__PI_PHYMSTR_REQ_ACK_LOOP_DELAY + +#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_176__PI_TVREF_F0_WIDTH 16U +#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_176 +#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TVREF_F0 + +#define LPDDR4__DENALI_PI_177_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_177_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_177__PI_TVREF_F1_WIDTH 16U +#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_177 +#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F1 + +#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_177__PI_TVREF_F2_WIDTH 16U +#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_177 +#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_177__PI_TVREF_F2 + +#define LPDDR4__DENALI_PI_178_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_178__PI_TSDO_F0_WIDTH 8U +#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_178 +#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F0 + +#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_178__PI_TSDO_F1_WIDTH 8U +#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_178 +#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F1 + +#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_178__PI_TSDO_F2_WIDTH 8U +#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_178 +#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_178__PI_TSDO_F2 + +#define LPDDR4__DENALI_PI_179_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_179 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_179__PI_TDELAY_RDWR_2_BUS_IDLE_F0 + +#define LPDDR4__DENALI_PI_180_READ_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_180 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_180__PI_TDELAY_RDWR_2_BUS_IDLE_F1 + +#define LPDDR4__DENALI_PI_181_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_181 +#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_181__PI_TDELAY_RDWR_2_BUS_IDLE_F2 + +#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_181__PI_ZQINIT_F0_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_181 +#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_181__PI_ZQINIT_F0 + +#define LPDDR4__DENALI_PI_182_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F1_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_182 +#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F1 + +#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_182__PI_ZQINIT_F2_WIDTH 12U +#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_182 +#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_182__PI_ZQINIT_F2 + +#define LPDDR4__DENALI_PI_183_READ_MASK 0xFF0F3F7FU +#define LPDDR4__DENALI_PI_183_WRITE_MASK 0xFF0F3F7FU +#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_183__PI_WRLAT_F0_WIDTH 7U +#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_183 +#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_183__PI_WRLAT_F0 + +#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0_WIDTH 6U +#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_183 +#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_ADDITIVE_LAT_F0 + +#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0_WIDTH 4U +#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_183 +#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_183__PI_CA_PARITY_LAT_F0 + +#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH 8U +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_183 +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_183__PI_TPARITY_ERROR_CMD_INHIBIT_F0 + +#define LPDDR4__DENALI_PI_184_READ_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x0F3F7F7FU +#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_184 +#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_184__PI_CASLAT_LIN_F0 + +#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_184__PI_WRLAT_F1_WIDTH 7U +#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_184 +#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_184__PI_WRLAT_F1 + +#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1_WIDTH 6U +#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_184 +#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_ADDITIVE_LAT_F1 + +#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1_WIDTH 4U +#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_184 +#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_184__PI_CA_PARITY_LAT_F1 + +#define LPDDR4__DENALI_PI_185_READ_MASK 0x3F7F7FFFU +#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x3F7F7FFFU +#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH 8U +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_185 +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_185__PI_TPARITY_ERROR_CMD_INHIBIT_F1 + +#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_185 +#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_185__PI_CASLAT_LIN_F1 + +#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_185__PI_WRLAT_F2_WIDTH 7U +#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_185 +#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_185__PI_WRLAT_F2 + +#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2_WIDTH 6U +#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_185 +#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_185__PI_ADDITIVE_LAT_F2 + +#define LPDDR4__DENALI_PI_186_READ_MASK 0x007FFF0FU +#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x007FFF0FU +#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2_WIDTH 4U +#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_186 +#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_186__PI_CA_PARITY_LAT_F2 + +#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH 8U +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_186 +#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_186__PI_TPARITY_ERROR_CMD_INHIBIT_F2 + +#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2_WIDTH 7U +#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_186 +#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_186__PI_CASLAT_LIN_F2 + +#define LPDDR4__DENALI_PI_187_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_187__PI_TRFC_F0_WIDTH 10U +#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_187 +#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_187__PI_TRFC_F0 + +#define LPDDR4__DENALI_PI_188_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_188__PI_TREF_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_188__PI_TREF_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_188__PI_TREF_F0_WIDTH 20U +#define LPDDR4__PI_TREF_F0__REG DENALI_PI_188 +#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_188__PI_TREF_F0 + +#define LPDDR4__DENALI_PI_189_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_189__PI_TRFC_F1_WIDTH 10U +#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_189 +#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_189__PI_TRFC_F1 + +#define LPDDR4__DENALI_PI_190_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_190__PI_TREF_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_190__PI_TREF_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_190__PI_TREF_F1_WIDTH 20U +#define LPDDR4__PI_TREF_F1__REG DENALI_PI_190 +#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_190__PI_TREF_F1 + +#define LPDDR4__DENALI_PI_191_READ_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_191__PI_TRFC_F2_WIDTH 10U +#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_191 +#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_191__PI_TRFC_F2 + +#define LPDDR4__DENALI_PI_192_READ_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x0F0FFFFFU +#define LPDDR4__DENALI_PI_192__PI_TREF_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_192__PI_TREF_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_192__PI_TREF_F2_WIDTH 20U +#define LPDDR4__PI_TREF_F2__REG DENALI_PI_192 +#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_192__PI_TREF_F2 + +#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_192 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_192__PI_TDFI_CTRL_DELAY_F0 + +#define LPDDR4__DENALI_PI_193_READ_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x03030F0FU +#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_193 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F1 + +#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_193 +#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_193__PI_TDFI_CTRL_DELAY_F2 + +#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_193 +#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F0 + +#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_193 +#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_193__PI_WRLVL_EN_F1 + +#define LPDDR4__DENALI_PI_194_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_194 +#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_194__PI_WRLVL_EN_F2 + +#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_194 +#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_WRLVL_WW_F0 + +#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_195 +#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F1 + +#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_195 +#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_WRLVL_WW_F2 + +#define LPDDR4__DENALI_PI_196_READ_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x01FF01FFU +#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_196 +#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F0 + +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_MASK 0x00000100U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WIDTH 1U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOCLR 0U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F0_WOSET 0U +#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_196 +#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F0 + +#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_196 +#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_196__PI_TODTL_2CMD_F1 + +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_MASK 0x01000000U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WIDTH 1U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOCLR 0U +#define LPDDR4__DENALI_PI_196__PI_ODT_EN_F1_WOSET 0U +#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_196 +#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_196__PI_ODT_EN_F1 + +#define LPDDR4__DENALI_PI_197_READ_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x0F0F01FFU +#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2_WIDTH 8U +#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_197 +#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_197__PI_TODTL_2CMD_F2 + +#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_MASK 0x00000100U +#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WIDTH 1U +#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOCLR 0U +#define LPDDR4__DENALI_PI_197__PI_ODT_EN_F2_WOSET 0U +#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_197 +#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_197__PI_ODT_EN_F2 + +#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_197__PI_ODTLON_F0_WIDTH 4U +#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_197 +#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_197__PI_ODTLON_F0 + +#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_197 +#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_197__PI_TODTON_MIN_F0 + +#define LPDDR4__DENALI_PI_198_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_198__PI_ODTLON_F1_WIDTH 4U +#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_198 +#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F1 + +#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_198 +#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F1 + +#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_198__PI_ODTLON_F2_WIDTH 4U +#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_198 +#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_198__PI_ODTLON_F2 + +#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2_WIDTH 4U +#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_198 +#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_198__PI_TODTON_MIN_F2 + +#define LPDDR4__DENALI_PI_199_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_199 +#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F0 + +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_199 +#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F1 + +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_199 +#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_199__PI_WR_TO_ODTH_F2 + +#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0_WIDTH 6U +#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_199 +#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_199__PI_RD_TO_ODTH_F0 + +#define LPDDR4__DENALI_PI_200_READ_MASK 0x03033F3FU +#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x03033F3FU +#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1_WIDTH 6U +#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_200 +#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F1 + +#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2_WIDTH 6U +#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_200 +#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_200__PI_RD_TO_ODTH_F2 + +#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_200 +#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_EN_F0 + +#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_200 +#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_200__PI_RDLVL_GATE_EN_F0 + +#define LPDDR4__DENALI_PI_201_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_201_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_201 +#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F1 + +#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_201 +#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F1 + +#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_201 +#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_EN_F2 + +#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_201 +#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_201__PI_RDLVL_GATE_EN_F2 + +#define LPDDR4__DENALI_PI_202_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_202_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0_WIDTH 8U +#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_202 +#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F0 + +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1_WIDTH 8U +#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_202 +#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F1 + +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2_WIDTH 8U +#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_202 +#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_202__PI_TWR_MPR_F2 + +#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_202 +#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_202__PI_RDLVL_PAT0_EN_F0 + +#define LPDDR4__DENALI_PI_203_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_203_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_203 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_RXCAL_EN_F0 + +#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_203 +#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_DFE_EN_F0 + +#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_203 +#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_MULTI_EN_F0 + +#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_203 +#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_203__PI_RDLVL_PAT0_EN_F1 + +#define LPDDR4__DENALI_PI_204_READ_MASK 0x03030303U +#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x03030303U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_204 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_RXCAL_EN_F1 + +#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_204 +#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_DFE_EN_F1 + +#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_204 +#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_MULTI_EN_F1 + +#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_MASK 0x03000000U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_204 +#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_204__PI_RDLVL_PAT0_EN_F2 + +#define LPDDR4__DENALI_PI_205_READ_MASK 0xFF030303U +#define LPDDR4__DENALI_PI_205_WRITE_MASK 0xFF030303U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_205 +#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_RXCAL_EN_F2 + +#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_205 +#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_DFE_EN_F2 + +#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2_WIDTH 2U +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_205 +#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_205__PI_RDLVL_MULTI_EN_F2 + +#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_205 +#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_205__PI_RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_206_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_206_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_206 +#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_206 +#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_206__PI_RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_206 +#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_206 +#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_206__PI_WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_207_READ_MASK 0x070707FFU +#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x070707FFU +#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_207 +#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_207__PI_WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000700U +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_207 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F0 + +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_MASK 0x00070000U +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_207 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F1 + +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_MASK 0x07000000U +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_207 +#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_PHY_WRDATA_F2 + +#define LPDDR4__DENALI_PI_208_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_208 +#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CC_F0 + +#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_208 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_208__PI_TDFI_CALVL_CAPTURE_F0 + +#define LPDDR4__DENALI_PI_209_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_209 +#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CC_F1 + +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_209 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_CAPTURE_F1 + +#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_210 +#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CC_F2 + +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_210 +#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_CAPTURE_F2 + +#define LPDDR4__DENALI_PI_211_READ_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x1F030303U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_MASK 0x00000003U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_211 +#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F0 + +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_211 +#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F1 + +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_211 +#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_211__PI_CALVL_EN_F2 + +#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_211__PI_TMRZ_F0_WIDTH 5U +#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_211 +#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_211__PI_TMRZ_F0 + +#define LPDDR4__DENALI_PI_212_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_212__PI_TCAENT_F0_WIDTH 14U +#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_212 +#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_212__PI_TCAENT_F0 + +#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_212__PI_TMRZ_F1_WIDTH 5U +#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_212 +#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_212__PI_TMRZ_F1 + +#define LPDDR4__DENALI_PI_213_READ_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x001F3FFFU +#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_213__PI_TCAENT_F1_WIDTH 14U +#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_213 +#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_213__PI_TCAENT_F1 + +#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_213__PI_TMRZ_F2_WIDTH 5U +#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_213 +#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_213__PI_TMRZ_F2 + +#define LPDDR4__DENALI_PI_214_READ_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x1F1F3FFFU +#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_MASK 0x00003FFFU +#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_214__PI_TCAENT_F2_WIDTH 14U +#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_214 +#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_214__PI_TCAENT_F2 + +#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_214 +#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CACSCA_F0 + +#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_214 +#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_214__PI_TDFI_CASEL_F0 + +#define LPDDR4__DENALI_PI_215_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_215 +#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_SHORT_F0 + +#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_215 +#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_215__PI_TVREF_LONG_F0 + +#define LPDDR4__DENALI_PI_216_READ_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x03FF1F1FU +#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_216 +#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CACSCA_F1 + +#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_216 +#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_216__PI_TDFI_CASEL_F1 + +#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_216 +#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_216__PI_TVREF_SHORT_F1 + +#define LPDDR4__DENALI_PI_217_READ_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_217_WRITE_MASK 0x1F1F03FFU +#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_217 +#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_217__PI_TVREF_LONG_F1 + +#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_217 +#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CACSCA_F2 + +#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2_WIDTH 5U +#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_217 +#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_CASEL_F2 + +#define LPDDR4__DENALI_PI_218_READ_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_218_WRITE_MASK 0x03FF03FFU +#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_218 +#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_SHORT_F2 + +#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2_WIDTH 10U +#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_218 +#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_218__PI_TVREF_LONG_F2 + +#define LPDDR4__DENALI_PI_219_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_219_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_219 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_219 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_219 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_219 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_219__PI_CALVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_220_READ_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_220_WRITE_MASK 0x0F0F7F7FU +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_220 +#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_220 +#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_220 +#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_220 +#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_220__PI_CALVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_221_READ_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFF1F0F0FU +#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_221 +#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_221__PI_CALVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_221 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_CALVL_STROBE_F0 + +#define LPDDR4__DENALI_PI_221__PI_TXP_F0_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_221__PI_TXP_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_221__PI_TXP_F0_WIDTH 5U +#define LPDDR4__PI_TXP_F0__REG DENALI_PI_221 +#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_221__PI_TXP_F0 + +#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_221 +#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRWCKEL_F0 + +#define LPDDR4__DENALI_PI_222_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_222_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_222__PI_TCKELCK_F0_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_222 +#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_222__PI_TCKELCK_F0 + +#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_222__PI_TDFI_CALVL_STROBE_F1 + +#define LPDDR4__DENALI_PI_222__PI_TXP_F1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_222__PI_TXP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_222__PI_TXP_F1_WIDTH 5U +#define LPDDR4__PI_TXP_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_222__PI_TXP_F1 + +#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_222 +#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_222__PI_TMRWCKEL_F1 + +#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF1F0F1FU +#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_223__PI_TCKELCK_F1_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_223 +#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_223__PI_TCKELCK_F1 + +#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_223 +#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_223__PI_TDFI_CALVL_STROBE_F2 + +#define LPDDR4__DENALI_PI_223__PI_TXP_F2_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_223__PI_TXP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_223__PI_TXP_F2_WIDTH 5U +#define LPDDR4__PI_TXP_F2__REG DENALI_PI_223 +#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_223__PI_TXP_F2 + +#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2_WIDTH 8U +#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_223 +#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_223__PI_TMRWCKEL_F2 + +#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFFFF1FU +#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFFFF1FU +#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_224__PI_TCKELCK_F2_WIDTH 5U +#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_224 +#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_224__PI_TCKELCK_F2 + +#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_MASK 0xFFFFFF00U +#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_224 +#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_224__PI_TDFI_INIT_START_F0 + +#define LPDDR4__DENALI_PI_225_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_225_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_225 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_225__PI_TDFI_INIT_COMPLETE_F0 + +#define LPDDR4__DENALI_PI_226_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_226 +#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_226__PI_TDFI_INIT_START_F1 + +#define LPDDR4__DENALI_PI_227_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_227_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_227 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_227__PI_TDFI_INIT_COMPLETE_F1 + +#define LPDDR4__DENALI_PI_228_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_228_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_228 +#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_INIT_START_F2 + +#define LPDDR4__DENALI_PI_229_READ_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x3FFFFFFFU +#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2_WIDTH 24U +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_229 +#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_229__PI_TDFI_INIT_COMPLETE_F2 + +#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_229 +#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_229__PI_TCKEHDQS_F0 + +#define LPDDR4__DENALI_PI_230_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_230_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_230__PI_TFC_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_230__PI_TFC_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_230__PI_TFC_F0_WIDTH 10U +#define LPDDR4__PI_TFC_F0__REG DENALI_PI_230 +#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_230__PI_TFC_F0 + +#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_230 +#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_230__PI_TCKEHDQS_F1 + +#define LPDDR4__DENALI_PI_231_READ_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x003F03FFU +#define LPDDR4__DENALI_PI_231__PI_TFC_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_231__PI_TFC_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_231__PI_TFC_F1_WIDTH 10U +#define LPDDR4__PI_TFC_F1__REG DENALI_PI_231 +#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_231__PI_TFC_F1 + +#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2_WIDTH 6U +#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_231 +#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_231__PI_TCKEHDQS_F2 + +#define LPDDR4__DENALI_PI_232_READ_MASK 0x030303FFU +#define LPDDR4__DENALI_PI_232_WRITE_MASK 0x030303FFU +#define LPDDR4__DENALI_PI_232__PI_TFC_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_232__PI_TFC_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_232__PI_TFC_F2_WIDTH 10U +#define LPDDR4__PI_TFC_F2__REG DENALI_PI_232 +#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_232__PI_TFC_F2 + +#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F0_WIDTH 2U +#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_232 +#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F0 + +#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_232__PI_VREF_EN_F1_WIDTH 2U +#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_232 +#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_232__PI_VREF_EN_F1 + +#define LPDDR4__DENALI_PI_233_READ_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x0003FF03U +#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_233__PI_VREF_EN_F2_WIDTH 2U +#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_233 +#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_233__PI_VREF_EN_F2 + +#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_MASK 0x0003FF00U +#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_233 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_233__PI_TDFI_WDQLVL_WR_F0 + +#define LPDDR4__DENALI_PI_234_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_234_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_234 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_234__PI_TDFI_WDQLVL_RW_F0 + +#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_234 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_START_POINT_F0 + +#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_234 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_234__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 + +#define LPDDR4__DENALI_PI_235_READ_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_235_WRITE_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_235 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_VREF_DELTA_F0 + +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_MASK 0x00000300U +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_235 +#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_EN_F0 + +#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_235 +#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_235__PI_NTP_TRAIN_EN_F0 + +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0_WIDTH 5U +#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_235 +#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_235__PI_WDQLVL_CL_F0 + +#define LPDDR4__DENALI_PI_236_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_236 +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_RDLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH 8U +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_236 +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_236__PI_WDQLVL_WRLAT_ADJ_F0 + +#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_236 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_236__PI_TDFI_WDQLVL_WR_F1 + +#define LPDDR4__DENALI_PI_237_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_237_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_237 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_237__PI_TDFI_WDQLVL_RW_F1 + +#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_237 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_START_POINT_F1 + +#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_237 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_237__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 + +#define LPDDR4__DENALI_PI_238_READ_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_238 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_VREF_DELTA_F1 + +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_MASK 0x00000300U +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_238 +#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_EN_F1 + +#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_MASK 0x00030000U +#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_238 +#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_238__PI_NTP_TRAIN_EN_F1 + +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1_WIDTH 5U +#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_238 +#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_238__PI_WDQLVL_CL_F1 + +#define LPDDR4__DENALI_PI_239_READ_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x03FFFFFFU +#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_239 +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_RDLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH 8U +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_239 +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_239__PI_WDQLVL_WRLAT_ADJ_F1 + +#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_MASK 0x03FF0000U +#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_239 +#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_239__PI_TDFI_WDQLVL_WR_F2 + +#define LPDDR4__DENALI_PI_240_READ_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x7F7F03FFU +#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU +#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_240 +#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_240__PI_TDFI_WDQLVL_RW_F2 + +#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_240 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_START_POINT_F2 + +#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_240 +#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_240__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 + +#define LPDDR4__DENALI_PI_241_READ_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x1F03030FU +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_241 +#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_VREF_DELTA_F2 + +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2_WIDTH 2U +#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_241 +#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_EN_F2 + +#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U +#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2_WIDTH 2U +#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_241 +#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_241__PI_NTP_TRAIN_EN_F2 + +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2_WIDTH 5U +#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_241 +#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_241__PI_WDQLVL_CL_F2 + +#define LPDDR4__DENALI_PI_242_READ_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x0303FFFFU +#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_242 +#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_RDLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH 8U +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_242 +#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_242__PI_WDQLVL_WRLAT_ADJ_F2 + +#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0_WIDTH 2U +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_242 +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F0 + +#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1_WIDTH 2U +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_242 +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_242__PI_RD_DBI_LEVEL_EN_F1 + +#define LPDDR4__DENALI_PI_243_READ_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PI_243_WRITE_MASK 0xFFFFFF03U +#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2_WIDTH 2U +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_243 +#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_243__PI_RD_DBI_LEVEL_EN_F2 + +#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_243__PI_TRTP_F0_WIDTH 8U +#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_243 +#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRTP_F0 + +#define LPDDR4__DENALI_PI_243__PI_TRP_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_243__PI_TRP_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_243__PI_TRP_F0_WIDTH 8U +#define LPDDR4__PI_TRP_F0__REG DENALI_PI_243 +#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_243__PI_TRP_F0 + +#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_243__PI_TRCD_F0_WIDTH 8U +#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_243 +#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_243__PI_TRCD_F0 + +#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FF3F1FU +#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FF3F1FU +#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_244__PI_TCCD_L_F0_WIDTH 5U +#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_244 +#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_244__PI_TCCD_L_F0 + +#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_244__PI_TWTR_F0_WIDTH 6U +#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_244 +#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWTR_F0 + +#define LPDDR4__DENALI_PI_244__PI_TWR_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_244__PI_TWR_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_244__PI_TWR_F0_WIDTH 8U +#define LPDDR4__PI_TWR_F0__REG DENALI_PI_244 +#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_244__PI_TWR_F0 + +#define LPDDR4__DENALI_PI_245_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0_WIDTH 20U +#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_245 +#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_245__PI_TRAS_MAX_F0 + +#define LPDDR4__DENALI_PI_246_READ_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0_WIDTH 9U +#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_246 +#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_246__PI_TRAS_MIN_F0 + +#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_246 +#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_246__PI_TDQSCK_MAX_F0 + +#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_246__PI_TCCDMW_F0_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_246 +#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_246__PI_TCCDMW_F0 + +#define LPDDR4__DENALI_PI_247_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_247_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_247__PI_TSR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_247__PI_TSR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_247__PI_TSR_F0_WIDTH 8U +#define LPDDR4__PI_TSR_F0__REG DENALI_PI_247 +#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_247__PI_TSR_F0 + +#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_247__PI_TMRD_F0_WIDTH 8U +#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_247 +#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRD_F0 + +#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_247__PI_TMRW_F0_WIDTH 8U +#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_247 +#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_247__PI_TMRW_F0 + +#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_247__PI_TMOD_F0_WIDTH 8U +#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_247 +#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_247__PI_TMOD_F0 + +#define LPDDR4__DENALI_PI_248_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_248_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0_WIDTH 8U +#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_248 +#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMOD_PAR_F0 + +#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0_WIDTH 8U +#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_248 +#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_248__PI_TMRD_PAR_F0 + +#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_248__PI_TRTP_F1_WIDTH 8U +#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_248 +#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRTP_F1 + +#define LPDDR4__DENALI_PI_248__PI_TRP_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_248__PI_TRP_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_248__PI_TRP_F1_WIDTH 8U +#define LPDDR4__PI_TRP_F1__REG DENALI_PI_248 +#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_248__PI_TRP_F1 + +#define LPDDR4__DENALI_PI_249_READ_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_249_WRITE_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_249__PI_TRCD_F1_WIDTH 8U +#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_249 +#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_249__PI_TRCD_F1 + +#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_249__PI_TCCD_L_F1_WIDTH 5U +#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_249 +#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_249__PI_TCCD_L_F1 + +#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_249__PI_TWTR_F1_WIDTH 6U +#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_249 +#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWTR_F1 + +#define LPDDR4__DENALI_PI_249__PI_TWR_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_249__PI_TWR_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_249__PI_TWR_F1_WIDTH 8U +#define LPDDR4__PI_TWR_F1__REG DENALI_PI_249 +#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_249__PI_TWR_F1 + +#define LPDDR4__DENALI_PI_250_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1_WIDTH 20U +#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_250 +#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_250__PI_TRAS_MAX_F1 + +#define LPDDR4__DENALI_PI_251_READ_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1_WIDTH 9U +#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_251 +#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_251__PI_TRAS_MIN_F1 + +#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_251 +#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_251__PI_TDQSCK_MAX_F1 + +#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_251__PI_TCCDMW_F1_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_251 +#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_251__PI_TCCDMW_F1 + +#define LPDDR4__DENALI_PI_252_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_252_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_252__PI_TSR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_252__PI_TSR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_252__PI_TSR_F1_WIDTH 8U +#define LPDDR4__PI_TSR_F1__REG DENALI_PI_252 +#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_252__PI_TSR_F1 + +#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_252__PI_TMRD_F1_WIDTH 8U +#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_252 +#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRD_F1 + +#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_252__PI_TMRW_F1_WIDTH 8U +#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_252 +#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_252__PI_TMRW_F1 + +#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_252__PI_TMOD_F1_WIDTH 8U +#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_252 +#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_252__PI_TMOD_F1 + +#define LPDDR4__DENALI_PI_253_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_253_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1_WIDTH 8U +#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_253 +#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMOD_PAR_F1 + +#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1_WIDTH 8U +#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_253 +#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_253__PI_TMRD_PAR_F1 + +#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_253__PI_TRTP_F2_WIDTH 8U +#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_253 +#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRTP_F2 + +#define LPDDR4__DENALI_PI_253__PI_TRP_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_253__PI_TRP_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_253__PI_TRP_F2_WIDTH 8U +#define LPDDR4__PI_TRP_F2__REG DENALI_PI_253 +#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_253__PI_TRP_F2 + +#define LPDDR4__DENALI_PI_254_READ_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_254_WRITE_MASK 0xFF3F1FFFU +#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_254__PI_TRCD_F2_WIDTH 8U +#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_254 +#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_254__PI_TRCD_F2 + +#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_254__PI_TCCD_L_F2_WIDTH 5U +#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_254 +#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_254__PI_TCCD_L_F2 + +#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_254__PI_TWTR_F2_WIDTH 6U +#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_254 +#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWTR_F2 + +#define LPDDR4__DENALI_PI_254__PI_TWR_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_254__PI_TWR_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_254__PI_TWR_F2_WIDTH 8U +#define LPDDR4__PI_TWR_F2__REG DENALI_PI_254 +#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_254__PI_TWR_F2 + +#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_MASK 0x000FFFFFU +#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2_WIDTH 20U +#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_255 +#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_255__PI_TRAS_MAX_F2 + +#define LPDDR4__DENALI_PI_256_READ_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x3F0F01FFU +#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_MASK 0x000001FFU +#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2_WIDTH 9U +#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_256 +#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_256__PI_TRAS_MIN_F2 + +#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2_WIDTH 4U +#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_256 +#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_256__PI_TDQSCK_MAX_F2 + +#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_256__PI_TCCDMW_F2_WIDTH 6U +#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_256 +#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_256__PI_TCCDMW_F2 + +#define LPDDR4__DENALI_PI_257_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_257_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_257__PI_TSR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_257__PI_TSR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_257__PI_TSR_F2_WIDTH 8U +#define LPDDR4__PI_TSR_F2__REG DENALI_PI_257 +#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_257__PI_TSR_F2 + +#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_257__PI_TMRD_F2_WIDTH 8U +#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_257 +#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRD_F2 + +#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_257__PI_TMRW_F2_WIDTH 8U +#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_257 +#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_257__PI_TMRW_F2 + +#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_SHIFT 24U +#define LPDDR4__DENALI_PI_257__PI_TMOD_F2_WIDTH 8U +#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_257 +#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_257__PI_TMOD_F2 + +#define LPDDR4__DENALI_PI_258_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2_WIDTH 8U +#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_258 +#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMOD_PAR_F2 + +#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2_WIDTH 8U +#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_258 +#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_258__PI_TMRD_PAR_F2 + +#define LPDDR4__DENALI_PI_259_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_259_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_259 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_259__PI_TDFI_CTRLUPD_MAX_F0 + +#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_260 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_260__PI_TDFI_CTRLUPD_INTERVAL_F0 + +#define LPDDR4__DENALI_PI_261_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_261_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_261 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_261__PI_TDFI_CTRLUPD_MAX_F1 + +#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_262 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_262__PI_TDFI_CTRLUPD_INTERVAL_F1 + +#define LPDDR4__DENALI_PI_263_READ_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_263_WRITE_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU +#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_263 +#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_263__PI_TDFI_CTRLUPD_MAX_F2 + +#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_264 +#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_264__PI_TDFI_CTRLUPD_INTERVAL_F2 + +#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_265__PI_TXSR_F0_WIDTH 16U +#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_265 +#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F0 + +#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_265__PI_TXSR_F1_WIDTH 16U +#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_265 +#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_265__PI_TXSR_F1 + +#define LPDDR4__DENALI_PI_266_READ_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x3F3FFFFFU +#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_266__PI_TXSR_F2_WIDTH 16U +#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_266 +#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_266__PI_TXSR_F2 + +#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F0_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_266 +#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F0 + +#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_266__PI_TEXCKE_F1_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_266 +#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_266__PI_TEXCKE_F1 + +#define LPDDR4__DENALI_PI_267_READ_MASK 0x00FFFF3FU +#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x00FFFF3FU +#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_267__PI_TEXCKE_F2_WIDTH 6U +#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_267 +#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_267__PI_TEXCKE_F2 + +#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_MASK 0x00FFFF00U +#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_267__PI_TDLL_F0_WIDTH 16U +#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_267 +#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_267__PI_TDLL_F0 + +#define LPDDR4__DENALI_PI_268_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_268_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_268__PI_TDLL_F1_WIDTH 16U +#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_268 +#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F1 + +#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_268__PI_TDLL_F2_WIDTH 16U +#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_268 +#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_268__PI_TDLL_F2 + +#define LPDDR4__DENALI_PI_269_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F0_WIDTH 8U +#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_269 +#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F0 + +#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_SHIFT 8U +#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F0_WIDTH 8U +#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_269 +#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F0 + +#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_269__PI_TCKSRX_F1_WIDTH 8U +#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_269 +#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRX_F1 + +#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_SHIFT 24U +#define LPDDR4__DENALI_PI_269__PI_TCKSRE_F1_WIDTH 8U +#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_269 +#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_269__PI_TCKSRE_F1 + +#define LPDDR4__DENALI_PI_270_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_270__PI_TCKSRX_F2_WIDTH 8U +#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_270 +#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRX_F2 + +#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_270__PI_TCKSRE_F2_WIDTH 8U +#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_270 +#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_270__PI_TCKSRE_F2 + +#define LPDDR4__DENALI_PI_271_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_271__PI_TINIT_F0_WIDTH 24U +#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_271 +#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_271__PI_TINIT_F0 + +#define LPDDR4__DENALI_PI_272_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_272__PI_TINIT3_F0_WIDTH 24U +#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_272 +#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_272__PI_TINIT3_F0 + +#define LPDDR4__DENALI_PI_273_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_273_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_273__PI_TINIT4_F0_WIDTH 24U +#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_273 +#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_273__PI_TINIT4_F0 + +#define LPDDR4__DENALI_PI_274_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_274_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_274__PI_TINIT5_F0_WIDTH 24U +#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_274 +#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_274__PI_TINIT5_F0 + +#define LPDDR4__DENALI_PI_275_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_275_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_275__PI_TXSNR_F0_WIDTH 16U +#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_275 +#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_275__PI_TXSNR_F0 + +#define LPDDR4__DENALI_PI_276_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_276_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_276__PI_TINIT_F1_WIDTH 24U +#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_276 +#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_276__PI_TINIT_F1 + +#define LPDDR4__DENALI_PI_277_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_277_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_277__PI_TINIT3_F1_WIDTH 24U +#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_277 +#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_277__PI_TINIT3_F1 + +#define LPDDR4__DENALI_PI_278_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_278_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_278__PI_TINIT4_F1_WIDTH 24U +#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_278 +#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_278__PI_TINIT4_F1 + +#define LPDDR4__DENALI_PI_279_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_279_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_279__PI_TINIT5_F1_WIDTH 24U +#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_279 +#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_279__PI_TINIT5_F1 + +#define LPDDR4__DENALI_PI_280_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_280_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_280__PI_TXSNR_F1_WIDTH 16U +#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_280 +#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_280__PI_TXSNR_F1 + +#define LPDDR4__DENALI_PI_281_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_281_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_281__PI_TINIT_F2_WIDTH 24U +#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_281 +#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_281__PI_TINIT_F2 + +#define LPDDR4__DENALI_PI_282_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_282_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_282__PI_TINIT3_F2_WIDTH 24U +#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_282 +#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_282__PI_TINIT3_F2 + +#define LPDDR4__DENALI_PI_283_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_283_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_283__PI_TINIT4_F2_WIDTH 24U +#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_283 +#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_283__PI_TINIT4_F2 + +#define LPDDR4__DENALI_PI_284_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_284_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_284__PI_TINIT5_F2_WIDTH 24U +#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_284 +#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_284__PI_TINIT5_F2 + +#define LPDDR4__DENALI_PI_285_READ_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_285_WRITE_MASK 0x0FFFFFFFU +#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_285__PI_TXSNR_F2_WIDTH 16U +#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_285 +#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_285__PI_TXSNR_F2 + +#define LPDDR4__DENALI_PI_285__PI_RESERVED54_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_285__PI_RESERVED54_SHIFT 16U +#define LPDDR4__DENALI_PI_285__PI_RESERVED54_WIDTH 12U +#define LPDDR4__PI_RESERVED54__REG DENALI_PI_285 +#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_285__PI_RESERVED54 + +#define LPDDR4__DENALI_PI_286_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_286_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_286__PI_RESERVED55_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_286__PI_RESERVED55_SHIFT 0U +#define LPDDR4__DENALI_PI_286__PI_RESERVED55_WIDTH 12U +#define LPDDR4__PI_RESERVED55__REG DENALI_PI_286 +#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_286__PI_RESERVED55 + +#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_SHIFT 16U +#define LPDDR4__DENALI_PI_286__PI_TZQCAL_F0_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_286 +#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_286__PI_TZQCAL_F0 + +#define LPDDR4__DENALI_PI_287_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_287_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_287__PI_TZQLAT_F0_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_287 +#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_287__PI_TZQLAT_F0 + +#define LPDDR4__DENALI_PI_287__PI_RESERVED56_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_287__PI_RESERVED56_SHIFT 8U +#define LPDDR4__DENALI_PI_287__PI_RESERVED56_WIDTH 12U +#define LPDDR4__PI_RESERVED56__REG DENALI_PI_287 +#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_287__PI_RESERVED56 + +#define LPDDR4__DENALI_PI_288_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_288_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_288__PI_RESERVED57_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_288__PI_RESERVED57_SHIFT 0U +#define LPDDR4__DENALI_PI_288__PI_RESERVED57_WIDTH 12U +#define LPDDR4__PI_RESERVED57__REG DENALI_PI_288 +#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_288__PI_RESERVED57 + +#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_SHIFT 16U +#define LPDDR4__DENALI_PI_288__PI_TZQCAL_F1_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_288 +#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_288__PI_TZQCAL_F1 + +#define LPDDR4__DENALI_PI_289_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_289_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_289__PI_TZQLAT_F1_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_289 +#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_289__PI_TZQLAT_F1 + +#define LPDDR4__DENALI_PI_289__PI_RESERVED58_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_289__PI_RESERVED58_SHIFT 8U +#define LPDDR4__DENALI_PI_289__PI_RESERVED58_WIDTH 12U +#define LPDDR4__PI_RESERVED58__REG DENALI_PI_289 +#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_289__PI_RESERVED58 + +#define LPDDR4__DENALI_PI_290_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_290_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_290__PI_RESERVED59_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_290__PI_RESERVED59_SHIFT 0U +#define LPDDR4__DENALI_PI_290__PI_RESERVED59_WIDTH 12U +#define LPDDR4__PI_RESERVED59__REG DENALI_PI_290 +#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_290__PI_RESERVED59 + +#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_290__PI_TZQCAL_F2_WIDTH 12U +#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_290 +#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_290__PI_TZQCAL_F2 + +#define LPDDR4__DENALI_PI_291_READ_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_291_WRITE_MASK 0x000FFF7FU +#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_SHIFT 0U +#define LPDDR4__DENALI_PI_291__PI_TZQLAT_F2_WIDTH 7U +#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_291 +#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_291__PI_TZQLAT_F2 + +#define LPDDR4__DENALI_PI_291__PI_RESERVED60_MASK 0x000FFF00U +#define LPDDR4__DENALI_PI_291__PI_RESERVED60_SHIFT 8U +#define LPDDR4__DENALI_PI_291__PI_RESERVED60_WIDTH 12U +#define LPDDR4__PI_RESERVED60__REG DENALI_PI_291 +#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_291__PI_RESERVED60 + +#define LPDDR4__DENALI_PI_292_READ_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_292_WRITE_MASK 0x0FFF0FFFU +#define LPDDR4__DENALI_PI_292__PI_RESERVED61_MASK 0x00000FFFU +#define LPDDR4__DENALI_PI_292__PI_RESERVED61_SHIFT 0U +#define LPDDR4__DENALI_PI_292__PI_RESERVED61_WIDTH 12U +#define LPDDR4__PI_RESERVED61__REG DENALI_PI_292 +#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_292__PI_RESERVED61 + +#define LPDDR4__DENALI_PI_292__PI_RESERVED62_MASK 0x0FFF0000U +#define LPDDR4__DENALI_PI_292__PI_RESERVED62_SHIFT 16U +#define LPDDR4__DENALI_PI_292__PI_RESERVED62_WIDTH 12U +#define LPDDR4__PI_RESERVED62__REG DENALI_PI_292 +#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_292__PI_RESERVED62 + +#define LPDDR4__DENALI_PI_293_READ_MASK 0x030F0F0FU +#define LPDDR4__DENALI_PI_293_WRITE_MASK 0x030F0F0FU +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_293 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F0 + +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_293 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F1 + +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U +#define LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_293 +#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_293__PI_WDQ_OSC_DELTA_INDEX_F2 + +#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_MASK 0x03000000U +#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_SHIFT 24U +#define LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_293 +#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_293__PI_PREAMBLE_SUPPORT_F0 + +#define LPDDR4__DENALI_PI_294_READ_MASK 0x07070303U +#define LPDDR4__DENALI_PI_294_WRITE_MASK 0x07070303U +#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_MASK 0x00000003U +#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_SHIFT 0U +#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_294 +#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F1 + +#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_MASK 0x00000300U +#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_SHIFT 8U +#define LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2_WIDTH 2U +#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_294 +#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_294__PI_PREAMBLE_SUPPORT_F2 + +#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_MASK 0x00070000U +#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_SHIFT 16U +#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0_WIDTH 3U +#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_294 +#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_0 + +#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_MASK 0x07000000U +#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_SHIFT 24U +#define LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1_WIDTH 3U +#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_294 +#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_294__PI_MEMDATA_RATIO_1 + +#define LPDDR4__DENALI_PI_295_READ_MASK 0x0F0F0707U +#define LPDDR4__DENALI_PI_295_WRITE_MASK 0x0F0F0707U +#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_MASK 0x00000007U +#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_SHIFT 0U +#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2_WIDTH 3U +#define LPDDR4__PI_MEMDATA_RATIO_2__REG DENALI_PI_295 +#define LPDDR4__PI_MEMDATA_RATIO_2__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_2 + +#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_MASK 0x00000700U +#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_SHIFT 8U +#define LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3_WIDTH 3U +#define LPDDR4__PI_MEMDATA_RATIO_3__REG DENALI_PI_295 +#define LPDDR4__PI_MEMDATA_RATIO_3__FLD LPDDR4__DENALI_PI_295__PI_MEMDATA_RATIO_3 + +#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_SHIFT 16U +#define LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0_WIDTH 4U +#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_295 +#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_RD_MAP_CS0 + +#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_SHIFT 24U +#define LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0_WIDTH 4U +#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_295 +#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_295__PI_ODT_WR_MAP_CS0 + +#define LPDDR4__DENALI_PI_296_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_296_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_SHIFT 0U +#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1_WIDTH 4U +#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_296 +#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS1 + +#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_SHIFT 8U +#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1_WIDTH 4U +#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_296 +#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS1 + +#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_SHIFT 16U +#define LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2_WIDTH 4U +#define LPDDR4__PI_ODT_RD_MAP_CS2__REG DENALI_PI_296 +#define LPDDR4__PI_ODT_RD_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_RD_MAP_CS2 + +#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_SHIFT 24U +#define LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2_WIDTH 4U +#define LPDDR4__PI_ODT_WR_MAP_CS2__REG DENALI_PI_296 +#define LPDDR4__PI_ODT_WR_MAP_CS2__FLD LPDDR4__DENALI_PI_296__PI_ODT_WR_MAP_CS2 + +#define LPDDR4__DENALI_PI_297_READ_MASK 0x7F7F0F0FU +#define LPDDR4__DENALI_PI_297_WRITE_MASK 0x7F7F0F0FU +#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_SHIFT 0U +#define LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3_WIDTH 4U +#define LPDDR4__PI_ODT_RD_MAP_CS3__REG DENALI_PI_297 +#define LPDDR4__PI_ODT_RD_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_RD_MAP_CS3 + +#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_SHIFT 8U +#define LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3_WIDTH 4U +#define LPDDR4__PI_ODT_WR_MAP_CS3__REG DENALI_PI_297 +#define LPDDR4__PI_ODT_WR_MAP_CS3__FLD LPDDR4__DENALI_PI_297__PI_ODT_WR_MAP_CS3 + +#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_297 +#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_0 + +#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_297 +#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_297__PI_VREF_VAL_DEV0_1 + +#define LPDDR4__DENALI_PI_298_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_298_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV0_2__REG DENALI_PI_298 +#define LPDDR4__PI_VREF_VAL_DEV0_2__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_2 + +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV0_3__REG DENALI_PI_298 +#define LPDDR4__PI_VREF_VAL_DEV0_3__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV0_3 + +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_298 +#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_0 + +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_298 +#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_298__PI_VREF_VAL_DEV1_1 + +#define LPDDR4__DENALI_PI_299_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV1_2__REG DENALI_PI_299 +#define LPDDR4__PI_VREF_VAL_DEV1_2__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_2 + +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV1_3__REG DENALI_PI_299 +#define LPDDR4__PI_VREF_VAL_DEV1_3__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV1_3 + +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV2_0__REG DENALI_PI_299 +#define LPDDR4__PI_VREF_VAL_DEV2_0__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_0 + +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV2_1__REG DENALI_PI_299 +#define LPDDR4__PI_VREF_VAL_DEV2_1__FLD LPDDR4__DENALI_PI_299__PI_VREF_VAL_DEV2_1 + +#define LPDDR4__DENALI_PI_300_READ_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_300_WRITE_MASK 0x7F7F7F7FU +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV2_2__REG DENALI_PI_300 +#define LPDDR4__PI_VREF_VAL_DEV2_2__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_2 + +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV2_3__REG DENALI_PI_300 +#define LPDDR4__PI_VREF_VAL_DEV2_3__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV2_3 + +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_MASK 0x007F0000U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_SHIFT 16U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV3_0__REG DENALI_PI_300 +#define LPDDR4__PI_VREF_VAL_DEV3_0__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_0 + +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_MASK 0x7F000000U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_SHIFT 24U +#define LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV3_1__REG DENALI_PI_300 +#define LPDDR4__PI_VREF_VAL_DEV3_1__FLD LPDDR4__DENALI_PI_300__PI_VREF_VAL_DEV3_1 + +#define LPDDR4__DENALI_PI_301_READ_MASK 0x03037F7FU +#define LPDDR4__DENALI_PI_301_WRITE_MASK 0x03037F7FU +#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_MASK 0x0000007FU +#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_SHIFT 0U +#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV3_2__REG DENALI_PI_301 +#define LPDDR4__PI_VREF_VAL_DEV3_2__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_2 + +#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_MASK 0x00007F00U +#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_SHIFT 8U +#define LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3_WIDTH 7U +#define LPDDR4__PI_VREF_VAL_DEV3_3__REG DENALI_PI_301 +#define LPDDR4__PI_VREF_VAL_DEV3_3__FLD LPDDR4__DENALI_PI_301__PI_VREF_VAL_DEV3_3 + +#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_MASK 0x00030000U +#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_SHIFT 16U +#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0_WIDTH 2U +#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_301 +#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_0 + +#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_MASK 0x03000000U +#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_SHIFT 24U +#define LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1_WIDTH 2U +#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_301 +#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_301__PI_SLICE_PER_DEV_1 + +#define LPDDR4__DENALI_PI_302_READ_MASK 0x3F3F0303U +#define LPDDR4__DENALI_PI_302_WRITE_MASK 0x3F3F0303U +#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_MASK 0x00000003U +#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_SHIFT 0U +#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2_WIDTH 2U +#define LPDDR4__PI_SLICE_PER_DEV_2__REG DENALI_PI_302 +#define LPDDR4__PI_SLICE_PER_DEV_2__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_2 + +#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_MASK 0x00000300U +#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_SHIFT 8U +#define LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3_WIDTH 2U +#define LPDDR4__PI_SLICE_PER_DEV_3__REG DENALI_PI_302 +#define LPDDR4__PI_SLICE_PER_DEV_3__FLD LPDDR4__DENALI_PI_302__PI_SLICE_PER_DEV_3 + +#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_302 +#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_0 + +#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_302 +#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_302__PI_MR6_VREF_0_1 + +#define LPDDR4__DENALI_PI_303_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_303_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_0_2__REG DENALI_PI_303 +#define LPDDR4__PI_MR6_VREF_0_2__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_2 + +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_0_3__REG DENALI_PI_303 +#define LPDDR4__PI_MR6_VREF_0_3__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_0_3 + +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_303 +#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_0 + +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_303 +#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_303__PI_MR6_VREF_1_1 + +#define LPDDR4__DENALI_PI_304_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_304_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_1_2__REG DENALI_PI_304 +#define LPDDR4__PI_MR6_VREF_1_2__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_2 + +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_1_3__REG DENALI_PI_304 +#define LPDDR4__PI_MR6_VREF_1_3__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_1_3 + +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_2_0__REG DENALI_PI_304 +#define LPDDR4__PI_MR6_VREF_2_0__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_0 + +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_2_1__REG DENALI_PI_304 +#define LPDDR4__PI_MR6_VREF_2_1__FLD LPDDR4__DENALI_PI_304__PI_MR6_VREF_2_1 + +#define LPDDR4__DENALI_PI_305_READ_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_305_WRITE_MASK 0x3F3F3F3FU +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_2_2__REG DENALI_PI_305 +#define LPDDR4__PI_MR6_VREF_2_2__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_2 + +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_2_3__REG DENALI_PI_305 +#define LPDDR4__PI_MR6_VREF_2_3__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_2_3 + +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_MASK 0x003F0000U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_SHIFT 16U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_3_0__REG DENALI_PI_305 +#define LPDDR4__PI_MR6_VREF_3_0__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_0 + +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_MASK 0x3F000000U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_SHIFT 24U +#define LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_3_1__REG DENALI_PI_305 +#define LPDDR4__PI_MR6_VREF_3_1__FLD LPDDR4__DENALI_PI_305__PI_MR6_VREF_3_1 + +#define LPDDR4__DENALI_PI_306_READ_MASK 0xFFFF3F3FU +#define LPDDR4__DENALI_PI_306_WRITE_MASK 0xFFFF3F3FU +#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_MASK 0x0000003FU +#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_SHIFT 0U +#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_3_2__REG DENALI_PI_306 +#define LPDDR4__PI_MR6_VREF_3_2__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_2 + +#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_MASK 0x00003F00U +#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_SHIFT 8U +#define LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3_WIDTH 6U +#define LPDDR4__PI_MR6_VREF_3_3__REG DENALI_PI_306 +#define LPDDR4__PI_MR6_VREF_3_3__FLD LPDDR4__DENALI_PI_306__PI_MR6_VREF_3_3 + +#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_PI_306__PI_MR13_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_306 +#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR13_DATA_0 + +#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_306__PI_MR15_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_306 +#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_306__PI_MR15_DATA_0 + +#define LPDDR4__DENALI_PI_307_READ_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_307_WRITE_MASK 0x00FFFFFFU +#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_307__PI_MR16_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_307 +#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR16_DATA_0 + +#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_307__PI_MR17_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_307 +#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR17_DATA_0 + +#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_SHIFT 16U +#define LPDDR4__DENALI_PI_307__PI_MR20_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_307 +#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_307__PI_MR20_DATA_0 + +#define LPDDR4__DENALI_PI_308_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_308_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_SHIFT 0U +#define LPDDR4__DENALI_PI_308__PI_MR32_DATA_0_WIDTH 17U +#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_308 +#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR32_DATA_0 + +#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_SHIFT 24U +#define LPDDR4__DENALI_PI_308__PI_MR40_DATA_0_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_308 +#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_308__PI_MR40_DATA_0 + +#define LPDDR4__DENALI_PI_309_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_309_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_309__PI_MR13_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_309 +#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR13_DATA_1 + +#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_SHIFT 8U +#define LPDDR4__DENALI_PI_309__PI_MR15_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_309 +#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR15_DATA_1 + +#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_SHIFT 16U +#define LPDDR4__DENALI_PI_309__PI_MR16_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_309 +#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR16_DATA_1 + +#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_SHIFT 24U +#define LPDDR4__DENALI_PI_309__PI_MR17_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_309 +#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_309__PI_MR17_DATA_1 + +#define LPDDR4__DENALI_PI_310_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_310_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_310__PI_MR20_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_310 +#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR20_DATA_1 + +#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_SHIFT 8U +#define LPDDR4__DENALI_PI_310__PI_MR32_DATA_1_WIDTH 17U +#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_310 +#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_310__PI_MR32_DATA_1 + +#define LPDDR4__DENALI_PI_311_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_311_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_311__PI_MR40_DATA_1_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_311 +#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_311__PI_MR40_DATA_1 + +#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_311__PI_MR13_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_311 +#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR13_DATA_2 + +#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_SHIFT 16U +#define LPDDR4__DENALI_PI_311__PI_MR15_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_311 +#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR15_DATA_2 + +#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_SHIFT 24U +#define LPDDR4__DENALI_PI_311__PI_MR16_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_311 +#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_311__PI_MR16_DATA_2 + +#define LPDDR4__DENALI_PI_312_READ_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_312_WRITE_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_312__PI_MR17_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_312 +#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR17_DATA_2 + +#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_SHIFT 8U +#define LPDDR4__DENALI_PI_312__PI_MR20_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_312 +#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_312__PI_MR20_DATA_2 + +#define LPDDR4__DENALI_PI_313_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_313_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_313__PI_MR32_DATA_2_WIDTH 17U +#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_313 +#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR32_DATA_2 + +#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_SHIFT 24U +#define LPDDR4__DENALI_PI_313__PI_MR40_DATA_2_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_313 +#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_313__PI_MR40_DATA_2 + +#define LPDDR4__DENALI_PI_314_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_314_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_314__PI_MR13_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_314 +#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR13_DATA_3 + +#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_SHIFT 8U +#define LPDDR4__DENALI_PI_314__PI_MR15_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_314 +#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR15_DATA_3 + +#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_SHIFT 16U +#define LPDDR4__DENALI_PI_314__PI_MR16_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_314 +#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR16_DATA_3 + +#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_SHIFT 24U +#define LPDDR4__DENALI_PI_314__PI_MR17_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_314 +#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_314__PI_MR17_DATA_3 + +#define LPDDR4__DENALI_PI_315_READ_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_315_WRITE_MASK 0x01FFFFFFU +#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_315__PI_MR20_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_315 +#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR20_DATA_3 + +#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_SHIFT 8U +#define LPDDR4__DENALI_PI_315__PI_MR32_DATA_3_WIDTH 17U +#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_315 +#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_315__PI_MR32_DATA_3 + +#define LPDDR4__DENALI_PI_316_READ_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_PI_316_WRITE_MASK 0x1F1F1FFFU +#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_316__PI_MR40_DATA_3_WIDTH 8U +#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_316 +#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_316__PI_MR40_DATA_3 + +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_SHIFT 8U +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_0_WIDTH 5U +#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_316 +#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_0 + +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_SHIFT 16U +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_1_WIDTH 5U +#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_316 +#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_1 + +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_SHIFT 24U +#define LPDDR4__DENALI_PI_316__PI_CKE_MUX_2_WIDTH 5U +#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_316 +#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_316__PI_CKE_MUX_2 + +#define LPDDR4__DENALI_PI_317_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_317_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_SHIFT 0U +#define LPDDR4__DENALI_PI_317__PI_CKE_MUX_3_WIDTH 5U +#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_317 +#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_317__PI_CKE_MUX_3 + +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_SHIFT 8U +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_0_WIDTH 5U +#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_317 +#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_0 + +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_SHIFT 16U +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_1_WIDTH 5U +#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_317 +#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_1 + +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_SHIFT 24U +#define LPDDR4__DENALI_PI_317__PI_CS_MUX_2_WIDTH 5U +#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_317 +#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_317__PI_CS_MUX_2 + +#define LPDDR4__DENALI_PI_318_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_318_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_SHIFT 0U +#define LPDDR4__DENALI_PI_318__PI_CS_MUX_3_WIDTH 5U +#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_318 +#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_318__PI_CS_MUX_3 + +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_SHIFT 8U +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_0_WIDTH 5U +#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_318 +#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_0 + +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_SHIFT 16U +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_1_WIDTH 5U +#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_318 +#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_1 + +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_SHIFT 24U +#define LPDDR4__DENALI_PI_318__PI_ODT_MUX_2_WIDTH 5U +#define LPDDR4__PI_ODT_MUX_2__REG DENALI_PI_318 +#define LPDDR4__PI_ODT_MUX_2__FLD LPDDR4__DENALI_PI_318__PI_ODT_MUX_2 + +#define LPDDR4__DENALI_PI_319_READ_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_319_WRITE_MASK 0x1F1F1F1FU +#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_SHIFT 0U +#define LPDDR4__DENALI_PI_319__PI_ODT_MUX_3_WIDTH 5U +#define LPDDR4__PI_ODT_MUX_3__REG DENALI_PI_319 +#define LPDDR4__PI_ODT_MUX_3__FLD LPDDR4__DENALI_PI_319__PI_ODT_MUX_3 + +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_MASK 0x00001F00U +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_SHIFT 8U +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0_WIDTH 5U +#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_319 +#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_0 + +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_MASK 0x001F0000U +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_SHIFT 16U +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1_WIDTH 5U +#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_319 +#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_1 + +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_MASK 0x1F000000U +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_SHIFT 24U +#define LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2_WIDTH 5U +#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_319 +#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_319__PI_RESET_N_MUX_2 + +#define LPDDR4__DENALI_PI_320_READ_MASK 0x01FFFF1FU +#define LPDDR4__DENALI_PI_320_WRITE_MASK 0x01FFFF1FU +#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_MASK 0x0000001FU +#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_SHIFT 0U +#define LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3_WIDTH 5U +#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_320 +#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_320__PI_RESET_N_MUX_3 + +#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_MASK 0x01FFFF00U +#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_SHIFT 8U +#define LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0_WIDTH 17U +#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_320 +#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_320__PI_MRSINGLE_DATA_0 + +#define LPDDR4__DENALI_PI_321_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_321_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_SHIFT 0U +#define LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1_WIDTH 17U +#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_321 +#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_321__PI_MRSINGLE_DATA_1 + +#define LPDDR4__DENALI_PI_322_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_322_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_SHIFT 0U +#define LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2_WIDTH 17U +#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_322 +#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_322__PI_MRSINGLE_DATA_2 + +#define LPDDR4__DENALI_PI_323_READ_MASK 0x0F01FFFFU +#define LPDDR4__DENALI_PI_323_WRITE_MASK 0x0F01FFFFU +#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_SHIFT 0U +#define LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3_WIDTH 17U +#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_323 +#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_323__PI_MRSINGLE_DATA_3 + +#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_SHIFT 24U +#define LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_323 +#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_323__PI_ZQ_CAL_START_MAP_0 + +#define LPDDR4__DENALI_PI_324_READ_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_324_WRITE_MASK 0x0F0F0F0FU +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_324 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_0 + +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_SHIFT 8U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_324 +#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_1 + +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_324 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_LATCH_MAP_1 + +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_SHIFT 24U +#define LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_324 +#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_324__PI_ZQ_CAL_START_MAP_2 + +#define LPDDR4__DENALI_PI_325_READ_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_325_WRITE_MASK 0x000F0F0FU +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_325 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_2 + +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_SHIFT 8U +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_325 +#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_START_MAP_3 + +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U +#define LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_325 +#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_325__PI_ZQ_CAL_LATCH_MAP_3 + +#define LPDDR4__DENALI_PI_326_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_326_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_326 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_0_0 + +#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_326 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_326__PI_DQS_OSC_BASE_VALUE_1_0 + +#define LPDDR4__DENALI_PI_327_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_327_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU +#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_327 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_0_1 + +#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U +#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_327 +#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_327__PI_DQS_OSC_BASE_VALUE_1_1 + +#define LPDDR4__DENALI_PI_328_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_328_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_328 +#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_328__PI_MR0_DATA_F0_0 + +#define LPDDR4__DENALI_PI_329_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_329_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_329 +#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_329__PI_MR1_DATA_F0_0 + +#define LPDDR4__DENALI_PI_330_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_330_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_330 +#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_330__PI_MR2_DATA_F0_0 + +#define LPDDR4__DENALI_PI_331_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_331_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_331 +#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_331__PI_MR3_DATA_F0_0 + +#define LPDDR4__DENALI_PI_332_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_332_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_332 +#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_332__PI_MR4_DATA_F0_0 + +#define LPDDR4__DENALI_PI_333_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_333_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_333 +#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_333__PI_MR5_DATA_F0_0 + +#define LPDDR4__DENALI_PI_334_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_334_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_334 +#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR6_DATA_F0_0 + +#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_334 +#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_334__PI_MR11_DATA_F0_0 + +#define LPDDR4__DENALI_PI_335_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_335_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_SHIFT 0U +#define LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_335 +#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR12_DATA_F0_0 + +#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_SHIFT 8U +#define LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_335 +#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR14_DATA_F0_0 + +#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_SHIFT 16U +#define LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_335 +#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR22_DATA_F0_0 + +#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_SHIFT 24U +#define LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_335 +#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_335__PI_MR23_DATA_F0_0 + +#define LPDDR4__DENALI_PI_336_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_336_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_336 +#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_336__PI_MR0_DATA_F1_0 + +#define LPDDR4__DENALI_PI_337_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_337_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_337 +#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_337__PI_MR1_DATA_F1_0 + +#define LPDDR4__DENALI_PI_338_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_338_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_338 +#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_338__PI_MR2_DATA_F1_0 + +#define LPDDR4__DENALI_PI_339_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_339_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_339 +#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_339__PI_MR3_DATA_F1_0 + +#define LPDDR4__DENALI_PI_340_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_340_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_340 +#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_340__PI_MR4_DATA_F1_0 + +#define LPDDR4__DENALI_PI_341_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_341_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_341 +#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_341__PI_MR5_DATA_F1_0 + +#define LPDDR4__DENALI_PI_342_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_342_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_342 +#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR6_DATA_F1_0 + +#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_342 +#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_342__PI_MR11_DATA_F1_0 + +#define LPDDR4__DENALI_PI_343_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_343_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_SHIFT 0U +#define LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_343 +#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR12_DATA_F1_0 + +#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_SHIFT 8U +#define LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_343 +#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR14_DATA_F1_0 + +#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_SHIFT 16U +#define LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_343 +#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR22_DATA_F1_0 + +#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_SHIFT 24U +#define LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_343 +#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_343__PI_MR23_DATA_F1_0 + +#define LPDDR4__DENALI_PI_344_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_344_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_344 +#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_344__PI_MR0_DATA_F2_0 + +#define LPDDR4__DENALI_PI_345_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_345_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_345 +#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_345__PI_MR1_DATA_F2_0 + +#define LPDDR4__DENALI_PI_346_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_346_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_346 +#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_346__PI_MR2_DATA_F2_0 + +#define LPDDR4__DENALI_PI_347_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_347_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_347 +#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_347__PI_MR3_DATA_F2_0 + +#define LPDDR4__DENALI_PI_348_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_348_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_348 +#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_348__PI_MR4_DATA_F2_0 + +#define LPDDR4__DENALI_PI_349_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_349_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_349 +#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_349__PI_MR5_DATA_F2_0 + +#define LPDDR4__DENALI_PI_350_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_350_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_350 +#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR6_DATA_F2_0 + +#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_350 +#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_350__PI_MR11_DATA_F2_0 + +#define LPDDR4__DENALI_PI_351_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_351_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_SHIFT 0U +#define LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_351 +#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR12_DATA_F2_0 + +#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_SHIFT 8U +#define LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_351 +#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR14_DATA_F2_0 + +#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_SHIFT 16U +#define LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_351 +#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR22_DATA_F2_0 + +#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_SHIFT 24U +#define LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_351 +#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_351__PI_MR23_DATA_F2_0 + +#define LPDDR4__DENALI_PI_352_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_352_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_352 +#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_352__PI_MR0_DATA_F0_1 + +#define LPDDR4__DENALI_PI_353_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_353_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_353 +#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_353__PI_MR1_DATA_F0_1 + +#define LPDDR4__DENALI_PI_354_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_354_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_354 +#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_354__PI_MR2_DATA_F0_1 + +#define LPDDR4__DENALI_PI_355_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_355_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_355 +#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_355__PI_MR3_DATA_F0_1 + +#define LPDDR4__DENALI_PI_356_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_356_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_356 +#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_356__PI_MR4_DATA_F0_1 + +#define LPDDR4__DENALI_PI_357_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_357_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_357 +#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_357__PI_MR5_DATA_F0_1 + +#define LPDDR4__DENALI_PI_358_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_358_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_358 +#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR6_DATA_F0_1 + +#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_358 +#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_358__PI_MR11_DATA_F0_1 + +#define LPDDR4__DENALI_PI_359_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_359_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_SHIFT 0U +#define LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_359 +#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR12_DATA_F0_1 + +#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_SHIFT 8U +#define LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_359 +#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR14_DATA_F0_1 + +#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_SHIFT 16U +#define LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_359 +#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR22_DATA_F0_1 + +#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_SHIFT 24U +#define LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_359 +#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_359__PI_MR23_DATA_F0_1 + +#define LPDDR4__DENALI_PI_360_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_360_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_360 +#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_360__PI_MR0_DATA_F1_1 + +#define LPDDR4__DENALI_PI_361_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_361_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_361 +#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_361__PI_MR1_DATA_F1_1 + +#define LPDDR4__DENALI_PI_362_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_362_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_362 +#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_362__PI_MR2_DATA_F1_1 + +#define LPDDR4__DENALI_PI_363_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_363_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_363 +#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_363__PI_MR3_DATA_F1_1 + +#define LPDDR4__DENALI_PI_364_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_364_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_364 +#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_364__PI_MR4_DATA_F1_1 + +#define LPDDR4__DENALI_PI_365_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_365_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_365 +#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_365__PI_MR5_DATA_F1_1 + +#define LPDDR4__DENALI_PI_366_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_366_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_366 +#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR6_DATA_F1_1 + +#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_366 +#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_366__PI_MR11_DATA_F1_1 + +#define LPDDR4__DENALI_PI_367_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_367_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_SHIFT 0U +#define LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_367 +#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR12_DATA_F1_1 + +#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_SHIFT 8U +#define LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_367 +#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR14_DATA_F1_1 + +#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_SHIFT 16U +#define LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_367 +#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR22_DATA_F1_1 + +#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_SHIFT 24U +#define LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_367 +#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_367__PI_MR23_DATA_F1_1 + +#define LPDDR4__DENALI_PI_368_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_368_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_368 +#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_368__PI_MR0_DATA_F2_1 + +#define LPDDR4__DENALI_PI_369_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_369_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_369 +#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_369__PI_MR1_DATA_F2_1 + +#define LPDDR4__DENALI_PI_370_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_370_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_370 +#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_370__PI_MR2_DATA_F2_1 + +#define LPDDR4__DENALI_PI_371_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_371_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_371 +#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_371__PI_MR3_DATA_F2_1 + +#define LPDDR4__DENALI_PI_372_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_372_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_372 +#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_372__PI_MR4_DATA_F2_1 + +#define LPDDR4__DENALI_PI_373_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_373_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_373 +#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_373__PI_MR5_DATA_F2_1 + +#define LPDDR4__DENALI_PI_374_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_374_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_374 +#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR6_DATA_F2_1 + +#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_374 +#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_374__PI_MR11_DATA_F2_1 + +#define LPDDR4__DENALI_PI_375_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_375_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_SHIFT 0U +#define LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_375 +#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR12_DATA_F2_1 + +#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_SHIFT 8U +#define LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_375 +#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR14_DATA_F2_1 + +#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_SHIFT 16U +#define LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_375 +#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR22_DATA_F2_1 + +#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_SHIFT 24U +#define LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_375 +#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_375__PI_MR23_DATA_F2_1 + +#define LPDDR4__DENALI_PI_376_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_376_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F0_2__REG DENALI_PI_376 +#define LPDDR4__PI_MR0_DATA_F0_2__FLD LPDDR4__DENALI_PI_376__PI_MR0_DATA_F0_2 + +#define LPDDR4__DENALI_PI_377_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_377_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_377 +#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_377__PI_MR1_DATA_F0_2 + +#define LPDDR4__DENALI_PI_378_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_378_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_378 +#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_378__PI_MR2_DATA_F0_2 + +#define LPDDR4__DENALI_PI_379_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_379_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_379 +#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_379__PI_MR3_DATA_F0_2 + +#define LPDDR4__DENALI_PI_380_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_380_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F0_2__REG DENALI_PI_380 +#define LPDDR4__PI_MR4_DATA_F0_2__FLD LPDDR4__DENALI_PI_380__PI_MR4_DATA_F0_2 + +#define LPDDR4__DENALI_PI_381_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_381_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F0_2__REG DENALI_PI_381 +#define LPDDR4__PI_MR5_DATA_F0_2__FLD LPDDR4__DENALI_PI_381__PI_MR5_DATA_F0_2 + +#define LPDDR4__DENALI_PI_382_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_382_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F0_2__REG DENALI_PI_382 +#define LPDDR4__PI_MR6_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR6_DATA_F0_2 + +#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_SHIFT 24U +#define LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_382 +#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_382__PI_MR11_DATA_F0_2 + +#define LPDDR4__DENALI_PI_383_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_383_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_SHIFT 0U +#define LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_383 +#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR12_DATA_F0_2 + +#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_SHIFT 8U +#define LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_383 +#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR14_DATA_F0_2 + +#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_SHIFT 16U +#define LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_383 +#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR22_DATA_F0_2 + +#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_SHIFT 24U +#define LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_383 +#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_383__PI_MR23_DATA_F0_2 + +#define LPDDR4__DENALI_PI_384_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_384_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F1_2__REG DENALI_PI_384 +#define LPDDR4__PI_MR0_DATA_F1_2__FLD LPDDR4__DENALI_PI_384__PI_MR0_DATA_F1_2 + +#define LPDDR4__DENALI_PI_385_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_385_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_385 +#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_385__PI_MR1_DATA_F1_2 + +#define LPDDR4__DENALI_PI_386_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_386_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_386 +#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_386__PI_MR2_DATA_F1_2 + +#define LPDDR4__DENALI_PI_387_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_387_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_387 +#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_387__PI_MR3_DATA_F1_2 + +#define LPDDR4__DENALI_PI_388_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_388_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F1_2__REG DENALI_PI_388 +#define LPDDR4__PI_MR4_DATA_F1_2__FLD LPDDR4__DENALI_PI_388__PI_MR4_DATA_F1_2 + +#define LPDDR4__DENALI_PI_389_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_389_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F1_2__REG DENALI_PI_389 +#define LPDDR4__PI_MR5_DATA_F1_2__FLD LPDDR4__DENALI_PI_389__PI_MR5_DATA_F1_2 + +#define LPDDR4__DENALI_PI_390_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_390_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F1_2__REG DENALI_PI_390 +#define LPDDR4__PI_MR6_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR6_DATA_F1_2 + +#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_SHIFT 24U +#define LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_390 +#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_390__PI_MR11_DATA_F1_2 + +#define LPDDR4__DENALI_PI_391_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_391_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_SHIFT 0U +#define LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_391 +#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR12_DATA_F1_2 + +#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_SHIFT 8U +#define LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_391 +#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR14_DATA_F1_2 + +#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_SHIFT 16U +#define LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_391 +#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR22_DATA_F1_2 + +#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_SHIFT 24U +#define LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_391 +#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_391__PI_MR23_DATA_F1_2 + +#define LPDDR4__DENALI_PI_392_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_392_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F2_2__REG DENALI_PI_392 +#define LPDDR4__PI_MR0_DATA_F2_2__FLD LPDDR4__DENALI_PI_392__PI_MR0_DATA_F2_2 + +#define LPDDR4__DENALI_PI_393_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_393_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_393 +#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_393__PI_MR1_DATA_F2_2 + +#define LPDDR4__DENALI_PI_394_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_394_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_394 +#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_394__PI_MR2_DATA_F2_2 + +#define LPDDR4__DENALI_PI_395_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_395_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_395 +#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_395__PI_MR3_DATA_F2_2 + +#define LPDDR4__DENALI_PI_396_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_396_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F2_2__REG DENALI_PI_396 +#define LPDDR4__PI_MR4_DATA_F2_2__FLD LPDDR4__DENALI_PI_396__PI_MR4_DATA_F2_2 + +#define LPDDR4__DENALI_PI_397_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_397_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F2_2__REG DENALI_PI_397 +#define LPDDR4__PI_MR5_DATA_F2_2__FLD LPDDR4__DENALI_PI_397__PI_MR5_DATA_F2_2 + +#define LPDDR4__DENALI_PI_398_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_398_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F2_2__REG DENALI_PI_398 +#define LPDDR4__PI_MR6_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR6_DATA_F2_2 + +#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_SHIFT 24U +#define LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_398 +#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_398__PI_MR11_DATA_F2_2 + +#define LPDDR4__DENALI_PI_399_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_399_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_SHIFT 0U +#define LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_399 +#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR12_DATA_F2_2 + +#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_SHIFT 8U +#define LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_399 +#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR14_DATA_F2_2 + +#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_SHIFT 16U +#define LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_399 +#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR22_DATA_F2_2 + +#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_SHIFT 24U +#define LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_399 +#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_399__PI_MR23_DATA_F2_2 + +#define LPDDR4__DENALI_PI_400_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_400_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F0_3__REG DENALI_PI_400 +#define LPDDR4__PI_MR0_DATA_F0_3__FLD LPDDR4__DENALI_PI_400__PI_MR0_DATA_F0_3 + +#define LPDDR4__DENALI_PI_401_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_401_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_401 +#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_401__PI_MR1_DATA_F0_3 + +#define LPDDR4__DENALI_PI_402_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_402_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_402 +#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_402__PI_MR2_DATA_F0_3 + +#define LPDDR4__DENALI_PI_403_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_403_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_403 +#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_403__PI_MR3_DATA_F0_3 + +#define LPDDR4__DENALI_PI_404_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_404_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F0_3__REG DENALI_PI_404 +#define LPDDR4__PI_MR4_DATA_F0_3__FLD LPDDR4__DENALI_PI_404__PI_MR4_DATA_F0_3 + +#define LPDDR4__DENALI_PI_405_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_405_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F0_3__REG DENALI_PI_405 +#define LPDDR4__PI_MR5_DATA_F0_3__FLD LPDDR4__DENALI_PI_405__PI_MR5_DATA_F0_3 + +#define LPDDR4__DENALI_PI_406_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_406_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F0_3__REG DENALI_PI_406 +#define LPDDR4__PI_MR6_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR6_DATA_F0_3 + +#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_SHIFT 24U +#define LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_406 +#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_406__PI_MR11_DATA_F0_3 + +#define LPDDR4__DENALI_PI_407_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_407_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_SHIFT 0U +#define LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_407 +#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR12_DATA_F0_3 + +#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_SHIFT 8U +#define LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_407 +#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR14_DATA_F0_3 + +#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_SHIFT 16U +#define LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_407 +#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR22_DATA_F0_3 + +#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_SHIFT 24U +#define LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_407 +#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_407__PI_MR23_DATA_F0_3 + +#define LPDDR4__DENALI_PI_408_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_408_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F1_3__REG DENALI_PI_408 +#define LPDDR4__PI_MR0_DATA_F1_3__FLD LPDDR4__DENALI_PI_408__PI_MR0_DATA_F1_3 + +#define LPDDR4__DENALI_PI_409_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_409_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_409 +#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_409__PI_MR1_DATA_F1_3 + +#define LPDDR4__DENALI_PI_410_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_410_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_410 +#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_410__PI_MR2_DATA_F1_3 + +#define LPDDR4__DENALI_PI_411_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_411_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_411 +#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_411__PI_MR3_DATA_F1_3 + +#define LPDDR4__DENALI_PI_412_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_412_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F1_3__REG DENALI_PI_412 +#define LPDDR4__PI_MR4_DATA_F1_3__FLD LPDDR4__DENALI_PI_412__PI_MR4_DATA_F1_3 + +#define LPDDR4__DENALI_PI_413_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_413_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F1_3__REG DENALI_PI_413 +#define LPDDR4__PI_MR5_DATA_F1_3__FLD LPDDR4__DENALI_PI_413__PI_MR5_DATA_F1_3 + +#define LPDDR4__DENALI_PI_414_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_414_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F1_3__REG DENALI_PI_414 +#define LPDDR4__PI_MR6_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR6_DATA_F1_3 + +#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_SHIFT 24U +#define LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_414 +#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_414__PI_MR11_DATA_F1_3 + +#define LPDDR4__DENALI_PI_415_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_415_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_SHIFT 0U +#define LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_415 +#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR12_DATA_F1_3 + +#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_SHIFT 8U +#define LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_415 +#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR14_DATA_F1_3 + +#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_SHIFT 16U +#define LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_415 +#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR22_DATA_F1_3 + +#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_SHIFT 24U +#define LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_415 +#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_415__PI_MR23_DATA_F1_3 + +#define LPDDR4__DENALI_PI_416_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_416_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR0_DATA_F2_3__REG DENALI_PI_416 +#define LPDDR4__PI_MR0_DATA_F2_3__FLD LPDDR4__DENALI_PI_416__PI_MR0_DATA_F2_3 + +#define LPDDR4__DENALI_PI_417_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_417_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_417 +#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_417__PI_MR1_DATA_F2_3 + +#define LPDDR4__DENALI_PI_418_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_418_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_418 +#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_418__PI_MR2_DATA_F2_3 + +#define LPDDR4__DENALI_PI_419_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_419_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_419 +#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_419__PI_MR3_DATA_F2_3 + +#define LPDDR4__DENALI_PI_420_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_420_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR4_DATA_F2_3__REG DENALI_PI_420 +#define LPDDR4__PI_MR4_DATA_F2_3__FLD LPDDR4__DENALI_PI_420__PI_MR4_DATA_F2_3 + +#define LPDDR4__DENALI_PI_421_READ_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_421_WRITE_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR5_DATA_F2_3__REG DENALI_PI_421 +#define LPDDR4__PI_MR5_DATA_F2_3__FLD LPDDR4__DENALI_PI_421__PI_MR5_DATA_F2_3 + +#define LPDDR4__DENALI_PI_422_READ_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_422_WRITE_MASK 0xFF01FFFFU +#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_MASK 0x0001FFFFU +#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3_WIDTH 17U +#define LPDDR4__PI_MR6_DATA_F2_3__REG DENALI_PI_422 +#define LPDDR4__PI_MR6_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR6_DATA_F2_3 + +#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_SHIFT 24U +#define LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_422 +#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_422__PI_MR11_DATA_F2_3 + +#define LPDDR4__DENALI_PI_423_READ_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_423_WRITE_MASK 0xFFFFFFFFU +#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_MASK 0x000000FFU +#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_SHIFT 0U +#define LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_423 +#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR12_DATA_F2_3 + +#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_MASK 0x0000FF00U +#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_SHIFT 8U +#define LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_423 +#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR14_DATA_F2_3 + +#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_MASK 0x00FF0000U +#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_SHIFT 16U +#define LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_423 +#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR22_DATA_F2_3 + +#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_MASK 0xFF000000U +#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_SHIFT 24U +#define LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3_WIDTH 8U +#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_423 +#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_423__PI_MR23_DATA_F2_3 + +#endif /* REG_LPDDR4_PI_MACROS_H_ */ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h index f22a20a07c..e233c5b1a3 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_0_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h index df5ab95166..8d5196a6ce 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_1_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h index 924013e355..5e781e6815 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_address_slice_2_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h similarity index 82% rename from drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h rename to drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h index d46b77b23f..9ea46fe48a 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_ctl_regs_rw_masks.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef LPDDR4_RW_MASKS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h similarity index 94% rename from drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h rename to drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h index 94202c9d94..4db3125952 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_if.h @@ -2,12 +2,12 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef LPDDR4_16BIT_IF_H -#define LPDDR4_16BIT_IF_H +#ifndef LPDDR4_AM64_IF_H +#define LPDDR4_AM64_IF_H #include @@ -105,4 +105,4 @@ typedef enum { LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U } lpddr4_intr_phyindepinterrupt; -#endif /* LPDDR4_16BIT_IF_H */ +#endif /* LPDDR4_AM64_IF_H */ diff --git a/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h new file mode 100644 index 0000000000..e2a23c3637 --- /dev/null +++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_obj_if.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_AM64_OBJ_IF_H +#define LPDDR4_AM64_OBJ_IF_H + +#include "lpddr4_am64_if.h" + +#endif /* LPDDR4_AM64_OBJ_IF_H */ diff --git a/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h b/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h new file mode 100644 index 0000000000..53b76f0888 --- /dev/null +++ b/drivers/ram/k3-ddrss/am64/lpddr4_am64_structs_if.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_AM64_STRUCTS_IF_H +#define LPDDR4_AM64_STRUCTS_IF_H + +#include +#include "lpddr4_am64_if.h" + +#endif /* LPDDR4_AM64_STRUCTS_IF_H */ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h rename to drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h index 21e96c9a90..bd29fad185 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_ctl_regs.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_CTL_REGS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h index d3bf24e677..c7358586c5 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_0_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h index d60bb6afe8..bf919afeea 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_data_slice_1_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h index 3df803e9ef..b006526808 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_ddr_controller_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h index dcfd7d9e86..1cf952913e 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_phy_core_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h rename to drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h index 9aa281af21..9c240d3a79 100644 --- a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h +++ b/drivers/ram/k3-ddrss/am64/lpddr4_pi_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_PI_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h index 298aa5e6cb..94a16199c5 100644 --- a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h +++ b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef CPS_DRV_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h index 58ba340e78..7fd3f1a8ac 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_address_slice_0_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h index 4113608434..9363035d29 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_ctl_regs.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_CTL_REGS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h index ad45dd98d7..73c027b338 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_0_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h index 5385e1e87b..c1999750a2 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_1_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h index f6edad4eab..ff534b007b 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_2_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h index 73e5f71df9..800c2a8e40 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_data_slice_3_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h index 4e33d04d1c..f0a4fa00c7 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_ddr_controller_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h similarity index 82% rename from drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h index 71122946b4..f760ed8420 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_ctl_regs_rw_masks.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef LPDDR4_RW_MASKS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h similarity index 93% rename from drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h index f14ca245ee..3d738c5763 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_if.h @@ -2,12 +2,12 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef LPDDR4_32BIT_IF_H -#define LPDDR4_32BIT_IF_H +#ifndef LPDDR4_J721E_IF_H +#define LPDDR4_J721E_IF_H #include @@ -88,4 +88,4 @@ typedef enum { LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U } lpddr4_intr_phyindepinterrupt; -#endif /* LPDDR4_32BIT_IF_H */ +#endif /* LPDDR4_J721E_IF_H */ diff --git a/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h new file mode 100644 index 0000000000..8b38cebb0f --- /dev/null +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_obj_if.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_J721E_OBJ_IF_H +#define LPDDR4_J721E_OBJ_IF_H + +#include "lpddr4_j721e_if.h" + +#endif /* LPDDR4_J721E_OBJ_IF_H */ diff --git a/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h new file mode 100644 index 0000000000..c877195281 --- /dev/null +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_j721e_structs_if.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_J721E_STRUCTS_IF_H +#define LPDDR4_J721E_STRUCTS_IF_H + +#include +#include "lpddr4_j721e_if.h" + +#endif /* LPDDR4_J721E_STRUCTS_IF_H */ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h index d8c7a5222e..d1a9e74a47 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_phy_core_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h similarity index 99% rename from drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h rename to drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h index 7f1754a499..8e428cb848 100644 --- a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h +++ b/drivers/ram/k3-ddrss/j721e/lpddr4_pi_macros.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef REG_LPDDR4_PI_MACROS_H_ diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c index 78ad966a17..11ef242a37 100644 --- a/drivers/ram/k3-ddrss/lpddr4.c +++ b/drivers/ram/k3-ddrss/lpddr4.c @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -13,14 +13,6 @@ #include "lpddr4.h" #include "lpddr4_structs_if.h" -#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY -#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U -#endif - -#ifndef LPDDR4_CPS_NS_DELAY_TIME -#define LPDDR4_CPS_NS_DELAY_TIME 10000000U -#endif - static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay); static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd); static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd); @@ -51,10 +43,7 @@ static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_l static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max); static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max); static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max); -#ifdef REG_WRITE_VERIF static u32 lpddr4_getphyrwmask(u32 regoffset); -static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); -#endif u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay) { @@ -202,8 +191,6 @@ u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoff return result; } -#ifdef REG_WRITE_VERIF - static u32 lpddr4_getphyrwmask(u32 regoffset) { u32 rwmask = 0U; @@ -231,33 +218,43 @@ static u32 lpddr4_getphyrwmask(u32 regoffset) return rwmask; } -static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue) +u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount) { u32 result = (u32)0; + u32 aindex; u32 regreadval = 0U; u32 rwmask = 0U; - result = lpddr4_readreg(pd, cpp, regoffset, ®readval); + result = lpddr4_deferredregverifysf(pd, cpp); + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL)) + result = EINVAL; if (result == (u32)0) { - switch (cpp) { - case LPDDR4_PHY_INDEP_REGS: - rwmask = g_lpddr4_pi_rw_mask[regoffset]; - break; - case LPDDR4_PHY_REGS: - rwmask = lpddr4_getphyrwmask(regoffset); - break; - default: - rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset]; - break; - } + for (aindex = 0; aindex < regcount; aindex++) { + result = lpddr4_readreg(pd, cpp, (u32)regnum[aindex], ®readval); - if ((rwmask & regreadval) != (regvalue & rwmask)) - result = EIO; + if (result == (u32)0) { + switch (cpp) { + case LPDDR4_PHY_INDEP_REGS: + rwmask = g_lpddr4_pi_rw_mask[(u32)regnum[aindex]]; + break; + case LPDDR4_PHY_REGS: + rwmask = lpddr4_getphyrwmask((u32)regnum[aindex]); + break; + default: + rwmask = g_lpddr4_ddr_controller_rw_mask[(u32)regnum[aindex]]; + break; + } + + if ((rwmask & regreadval) != ((u32)(regvalues[aindex]) & rwmask)) { + result = EIO; + break; + } + } + } } return result; } -#endif u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue) { @@ -284,11 +281,6 @@ u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regof CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue); } } -#ifdef REG_WRITE_VERIF - if (result == (u32)0) - result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue); - -#endif return result; } @@ -346,9 +338,6 @@ u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 } } -#ifdef ASILC -#endif - return result; } diff --git a/drivers/ram/k3-ddrss/lpddr4.h b/drivers/ram/k3-ddrss/lpddr4.h index 5b77ea9e6e..0fcd6d78ef 100644 --- a/drivers/ram/k3-ddrss/lpddr4.h +++ b/drivers/ram/k3-ddrss/lpddr4.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef LPDDR4_H @@ -11,19 +11,13 @@ #include "lpddr4_ctl_regs.h" #include "lpddr4_sanity.h" -#ifdef CONFIG_K3_AM64_DDRSS -#include "lpddr4_16bit.h" -#include "lpddr4_16bit_sanity.h" -#else -#include "lpddr4_32bit.h" -#include "lpddr4_32bit_sanity.h" -#endif -#ifdef REG_WRITE_VERIF -#include "lpddr4_ctl_regs_rw_masks.h" -#endif -#ifdef __cplusplus -extern "C" { +#if defined (CONFIG_K3_AM64_DDRSS) || defined (CONFIG_K3_AM62A_DDRSS) +#include "lpddr4_am6x.h" +#include "lpddr4_am6x_sanity.h" +#else +#include "lpddr4_j721e.h" +#include "lpddr4_j721e_sanity.h" #endif #define PRODUCT_ID (0x1046U) @@ -56,6 +50,14 @@ extern "C" { #define CDN_TRUE 1U #define CDN_FALSE 0U +#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY +#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U +#endif + +#ifndef LPDDR4_CPS_NS_DELAY_TIME +#define LPDDR4_CPS_NS_DELAY_TIME 10000000U +#endif + void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound); volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset); u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay); @@ -66,8 +68,5 @@ u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd); void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr); u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus); u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset); -#ifdef __cplusplus -} -#endif #endif /* LPDDR4_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.h b/drivers/ram/k3-ddrss/lpddr4_16bit.h deleted file mode 100644 index d663389e60..0000000000 --- a/drivers/ram/k3-ddrss/lpddr4_16bit.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/* - * Cadence DDR Driver - * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef LPDDR4_16BIT_H -#define LPDDR4_16BIT_H - -#define DSLICE_NUM (2U) -#define ASLICE_NUM (3U) - -#ifdef __cplusplus -extern "C" { -#endif - -#define DSLICE0_REG_COUNT (126U) -#define DSLICE1_REG_COUNT (126U) -#define ASLICE0_REG_COUNT (42U) -#define ASLICE1_REG_COUNT (42U) -#define ASLICE2_REG_COUNT (42U) -#define PHY_CORE_REG_COUNT (126U) - -#define GRP_SHIFT 1 -#define INT_SHIFT 2 - -#ifdef __cplusplus -} -#endif - -#endif /* LPDDR4_16BIT_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c new file mode 100644 index 0000000000..2b871cc76d --- /dev/null +++ b/drivers/ram/k3-ddrss/lpddr4_am62a_ctl_regs_rw_masks.c @@ -0,0 +1,1726 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include + +u32 g_lpddr4_ddr_controller_rw_mask[] = { + 0x00000F01U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x01FFFFFFU, + 0x03030300U, + 0x01030100U, + 0x1F1F013FU, + 0x0303031FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0xFFFFFF01U, + 0x0001FFFFU, + 0x000F7FFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF00FFFFU, + 0x0000FFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x0F3F7F7FU, + 0xFFFFFFFFU, + 0x0F3F7F7FU, + 0xFFFFFFFFU, + 0x0F3F7F7FU, + 0xFFFFFFFFU, + 0xFF1F1F07U, + 0x0001FFFFU, + 0x3F3F01FFU, + 0x1F01FFFFU, + 0x01FFFFFFU, + 0x3F3F01FFU, + 0x1F01FFFFU, + 0x01FFFFFFU, + 0x3F3F01FFU, + 0xFF01FFFFU, + 0x00FFFFFFU, + 0x1F0FFFFFU, + 0xFFFF3FFFU, + 0x0000FFFFU, + 0x1F0FFFFFU, + 0xFFFF3FFFU, + 0x0000FFFFU, + 0x1F0FFFFFU, + 0x07073FFFU, + 0xFFFF0107U, + 0xFFFFFFFFU, + 0x0101010FU, + 0x3FFFFFFFU, + 0xFFFFFFFFU, + 0x0301FFFFU, + 0x00010101U, + 0x03FFFFFFU, + 0x01000000U, + 0x03FF3F07U, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x010FFFFFU, + 0x0FFFFF01U, + 0x001F1F01U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x1F1F1FFFU, + 0x1F1F1F0FU, + 0x1F1F1F0FU, + 0x1F011F0FU, + 0x00011F01U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x07FFFFFFU, + 0x1F1F1F1FU, + 0x1F07FF1FU, + 0x1F1F1F1FU, + 0x1F1F07FFU, + 0x1F1F1F1FU, + 0x01011F1FU, + 0x7F000701U, + 0x00FFFF01U, + 0xFFFFFFFFU, + 0xFF070700U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x010FFFFFU, + 0x00010100U, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x01FFFFFFU, + 0x0000FF00U, + 0x0001FFFFU, + 0x0F03FFFFU, + 0x00000001U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0100U, + 0xFFFFFFFFU, + 0x0F0F0003U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x00013F0FU, + 0x0FFF0FFFU, + 0x0F0F0007U, + 0x000FFF07U, + 0xFFFF0FFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x01010101U, + 0x0101FF01U, + 0x00000107U, + 0xFFFFFFFFU, + 0x00FFFF0FU, + 0x00000303U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x07FFFFFFU, + 0x01FFFF00U, + 0x00000000U, + 0x00000000U, + 0x03010000U, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x000FFFFFU, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x000FFFFFU, + 0x03FF03FFU, + 0x1F1F03FFU, + 0x000FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x01FFFF01U, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x01FFFF00U, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0101FFFFU, + 0x00000101U, + 0x01010101U, + 0x03010101U, + 0x3F000003U, + 0x00000101U, + 0xFFFFFFFFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x000FFF00U, + 0x1F000000U, + 0x1F1F1F1FU, + 0xFFFF070FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x000FFF00U, + 0x0FFF0FFFU, + 0x007F0FFFU, + 0x0FFF0FFFU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x037F0FFFU, + 0x0FFF0000U, + 0x0FFF0FFFU, + 0x03030101U, + 0x03030303U, + 0x0F0F0707U, + 0xFFFFFFFFU, + 0x00FFFF03U, + 0xFFFFFFFFU, + 0x03FFFF03U, + 0x1F011F01U, + 0x0101FFFFU, + 0x01010101U, + 0x03010101U, + 0x0301011FU, + 0x07010F03U, + 0x0F0F0F07U, + 0x0F0F0F0FU, + 0x03011F0FU, + 0x01010000U, + 0x01030303U, + 0x00000101U, + 0x01000000U, + 0x00000000U, + 0x00000000U, + 0xFFFFFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFF000000U, + 0x0FFF0F0FU, + 0x0F0FFF0FU, + 0x01010101U, + 0x033F3F3FU, + 0x3F030303U, + 0x1F1F3F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x0F1F1F1FU, + 0x0F070F07U, + 0x07010107U, + 0xFF000007U, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0xFFFF070FU, + 0xFF7FFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0xFFFF070FU, + 0xFF7FFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x007FFFFFU, + 0xFFFFFFFFU, + 0xFFFF070FU, + 0x007FFFFFU, + 0x00FFFFFFU, + 0x0FFFFF03U, + 0x01FF070FU, + 0x07070701U, + 0x0F070707U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0xFF0F0F0FU, + 0x0000FFFFU +}; + +u32 g_lpddr4_pi_rw_mask[] = { + 0x00000F01U, + 0x00000000U, + 0x00000000U, + 0x01000000U, + 0xFFFF0301U, + 0x030100FFU, + 0x00000101U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x0000011FU, + 0xFFFFFFFFU, + 0x010F0101U, + 0x0F011F0FU, + 0x0101070FU, + 0x000FFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000007U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x01000000U, + 0x01010101U, + 0x3F030F00U, + 0x01FFFF3FU, + 0x0F010F01U, + 0x00FF0001U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0F0F0F1FU, + 0x0000000FU, + 0x03FFFFFFU, + 0x00000F07U, + 0x0000030FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101010FU, + 0x01010101U, + 0x000F0F01U, + 0x000003FFU, + 0xFFFFFFFFU, + 0x0000FF0FU, + 0xFFFFFFFFU, + 0x00FFFF00U, + 0x0F0FFFFFU, + 0x01011F1FU, + 0x0F000000U, + 0x030F0103U, + 0x01010101U, + 0x0000FF0FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0001U, + 0x1F1F3F1FU, + 0xFF0F0F01U, + 0x017F1FFFU, + 0xFF01FFFFU, + 0x01010103U, + 0x0F0701FFU, + 0x1F1F0F01U, + 0x030F0001U, + 0x000000FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0101FFFFU, + 0x00030001U, + 0xFFFFFFFFU, + 0x00010107U, + 0x010003FFU, + 0x01010101U, + 0x07030F01U, + 0x0F0F0F1FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0000000FU, + 0x00000000U, + 0x00000000U, + 0x3FFFFFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x011F3F00U, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x0303011FU, + 0x00010303U, + 0x0700FFFFU, + 0xFF000001U, + 0x00000101U, + 0xFFFFFFFFU, + 0x0000FF07U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0FFF0000U, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0xFFFFFFFFU, + 0x0303070FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000007FU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x3FFFFFFFU, + 0x0101010FU, + 0x00010101U, + 0x01010101U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFF0101U, + 0x000000FFU, + 0x03FFFFFFU, + 0x00000100U, + 0x0001FFFFU, + 0x01000000U, + 0x0100000FU, + 0x00010F07U, + 0x0F00010FU, + 0x010F0001U, + 0x00010F00U, + 0x0F00010FU, + 0x010F0001U, + 0x00000000U, + 0x00000000U, + 0x011F0000U, + 0x01010103U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x01010101U, + 0x00FF0101U, + 0x000001FFU, + 0x0000001FU, + 0x0F011F01U, + 0x01010101U, + 0xFFFF0701U, + 0xFFFFFFFFU, + 0x00FFFFFFU, + 0x000000FFU, + 0x000000FFU, + 0x000FFFFFU, + 0x0FFF0FFFU, + 0xFF0F3F7FU, + 0x0F3F7F7FU, + 0x3F7F7FFFU, + 0x007FFF0FU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x000FFFFFU, + 0x000003FFU, + 0x0F0FFFFFU, + 0x03030F0FU, + 0x0003FF03U, + 0x03FF03FFU, + 0x01FF01FFU, + 0x0F0F01FFU, + 0x0F0F0F0FU, + 0x3F3F3F3FU, + 0x03033F3FU, + 0x03030303U, + 0x03FFFFFFU, + 0x03030303U, + 0x03030303U, + 0xFF030303U, + 0xFFFFFFFFU, + 0x070707FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F030303U, + 0x001F3FFFU, + 0x001F3FFFU, + 0x1F1F3FFFU, + 0x03FF03FFU, + 0x03FF1F1FU, + 0x1F1F03FFU, + 0x03FF03FFU, + 0x7F7F7F7FU, + 0x0F0F7F7FU, + 0xFF1F0F0FU, + 0xFF1F0F1FU, + 0xFF1F0F1FU, + 0xFFFFFF1FU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x3FFFFFFFU, + 0x003F03FFU, + 0x003F03FFU, + 0x030303FFU, + 0x0003FF03U, + 0x7F7F03FFU, + 0x1F03030FU, + 0x03FFFFFFU, + 0x7F7F03FFU, + 0x1F03030FU, + 0x03FFFFFFU, + 0x7F7F03FFU, + 0x1F03030FU, + 0x0303FFFFU, + 0xFFFFFF03U, + 0x00FF3F1FU, + 0x000FFFFFU, + 0x3F0F01FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF3F1FFFU, + 0x000FFFFFU, + 0x3F0F01FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFF3F1FFFU, + 0x000FFFFFU, + 0x3F0F01FFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0x001FFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x3F3FFFFFU, + 0x00FFFF3FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0000FFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x00FFFFFFU, + 0x0FFFFFFFU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x000FFF7FU, + 0x0FFF0FFFU, + 0x030F0F0FU, + 0x07070303U, + 0x0F0F0707U, + 0x0F0F0F0FU, + 0x7F7F0F0FU, + 0x7F7F7F7FU, + 0x7F7F7F7FU, + 0x7F7F7F7FU, + 0x03037F7FU, + 0x00000303U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0xFFFF0000U, + 0x00FFFFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0xFFFFFFFFU, + 0x0000FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x01FFFFFFU, + 0x1F1F1FFFU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x01FFFF1FU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0F01FFFFU, + 0x0F0F0F0FU, + 0x000F0F0FU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0xFF01FFFFU, + 0xFFFFFFFFU +}; + +u32 g_lpddr4_data_slice_0_rw_mask[] = { + 0x07FF7F07U, + 0x0703FF0FU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0x00000001U, + 0xFFFFFFFFU, + 0x00000000U, + 0x7F0101FFU, + 0x010101FFU, + 0x03FF003FU, + 0x01FF000FU, + 0x01FF0701U, + 0x00000003U, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0x3F030001U, + 0x0F3FFF0FU, + 0x1F030F3FU, + 0x03FFFFFFU, + 0x00073FFFU, + 0x0F0F07FFU, + 0x000FFFFFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0xFF1F07FFU, + 0xFF3F03FFU, + 0x010101FFU, + 0x01010703U, + 0x00000101U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x007F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F0703FFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F010303U, + 0x0F1F1F1FU, + 0xFF3F07FFU, + 0x0FFF0FFFU, + 0x001F0F3FU, + 0x03FF03FFU, + 0x01FF0FFFU, + 0x00000F01U, + 0x000003FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F7F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_data_slice_1_rw_mask[] = { + 0x07FF7F07U, + 0x0703FF0FU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0x00000001U, + 0xFFFFFFFFU, + 0x00000000U, + 0x7F0101FFU, + 0x010101FFU, + 0x03FF003FU, + 0x01FF000FU, + 0x01FF0701U, + 0x00000003U, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0x3F030001U, + 0x0F3FFF0FU, + 0x1F030F3FU, + 0x03FFFFFFU, + 0x00073FFFU, + 0x0F0F07FFU, + 0x000FFFFFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0xFF1F07FFU, + 0xFF3F03FFU, + 0x010101FFU, + 0x01010703U, + 0x00000101U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x007F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F0703FFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F010303U, + 0x0F1F1F1FU, + 0xFF3F07FFU, + 0x0FFF0FFFU, + 0x001F0F3FU, + 0x03FF03FFU, + 0x01FF0FFFU, + 0x00000F01U, + 0x000003FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F7F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_data_slice_2_rw_mask[] = { + 0x07FF7F07U, + 0x0703FF0FU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0x00000001U, + 0xFFFFFFFFU, + 0x00000000U, + 0x7F0101FFU, + 0x010101FFU, + 0x03FF003FU, + 0x01FF000FU, + 0x01FF0701U, + 0x00000003U, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0x3F030001U, + 0x0F3FFF0FU, + 0x1F030F3FU, + 0x03FFFFFFU, + 0x00073FFFU, + 0x0F0F07FFU, + 0x000FFFFFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0xFF1F07FFU, + 0xFF3F03FFU, + 0x010101FFU, + 0x01010703U, + 0x00000101U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x007F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F0703FFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F010303U, + 0x0F1F1F1FU, + 0xFF3F07FFU, + 0x0FFF0FFFU, + 0x001F0F3FU, + 0x03FF03FFU, + 0x01FF0FFFU, + 0x00000F01U, + 0x000003FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F7F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_data_slice_3_rw_mask[] = { + 0x07FF7F07U, + 0x0703FF0FU, + 0x010303FFU, + 0x3F3F3F3FU, + 0x3F3F3F3FU, + 0x01030F3FU, + 0x1F1F0301U, + 0x1F030F0FU, + 0x0101FF03U, + 0x00000001U, + 0xFFFFFFFFU, + 0x00000000U, + 0x7F0101FFU, + 0x010101FFU, + 0x03FF003FU, + 0x01FF000FU, + 0x01FF0701U, + 0x00000003U, + 0x00000000U, + 0x00000301U, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x070F0107U, + 0x0F0F0F0FU, + 0x3F030001U, + 0x0F3FFF0FU, + 0x1F030F3FU, + 0x03FFFFFFU, + 0x00073FFFU, + 0x0F0F07FFU, + 0x000FFFFFU, + 0x000001FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0001FFFFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x00000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7FFFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x01FF01FFU, + 0x000001FFU, + 0x0003FFFFU, + 0x01FF01FFU, + 0xFF1F07FFU, + 0xFF3F03FFU, + 0x010101FFU, + 0x01010703U, + 0x00000101U, + 0x07FFFF07U, + 0x7F03FFFFU, + 0xFF01037FU, + 0x07FF07FFU, + 0x0103FFFFU, + 0x1F1F0F3FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x007F1F1FU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x1F0703FFU, + 0x00000007U, + 0xFFFFFFFFU, + 0xFFFFFF0FU, + 0x0FFFFFFFU, + 0x03FFFF01U, + 0x1F010303U, + 0x0F1F1F1FU, + 0xFF3F07FFU, + 0x0FFF0FFFU, + 0x001F0F3FU, + 0x03FF03FFU, + 0x01FF0FFFU, + 0x00000F01U, + 0x000003FFU, + 0x00030703U, + 0x07FF03FFU, + 0xFFFF0101U, + 0x001F7F7FU, + 0xFFFFFFFFU, + 0x0000000FU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x03FF07FFU, + 0x0003FF03U, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF03FFU, + 0x03FF070FU, + 0x000103FFU, + 0x000F03FFU, + 0x010F07FFU, + 0x000003FFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0xFFFFFFFFU, + 0x0003033FU +}; + +u32 g_lpddr4_address_slice_0_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x3FFFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0xFFFFFF03U, + 0x01FFFFFFU, + 0x3F03FFFFU, + 0x0101FFFFU, + 0x00003F01U, + 0x07FF07FFU, + 0x07FF1F07U, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x03FF010FU, + 0x0000FF01U +}; + +u32 g_lpddr4_address_slice_1_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x3FFFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0xFFFFFF03U, + 0x01FFFFFFU, + 0x3F03FFFFU, + 0x0101FFFFU, + 0x00003F01U, + 0x07FF07FFU, + 0x07FF1F07U, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x03FF010FU, + 0x0000FF01U +}; + +u32 g_lpddr4_address_slice_2_rw_mask[] = { + 0x000107FFU, + 0x00000000U, + 0x0F000000U, + 0x00000000U, + 0x01000707U, + 0x011F7F7FU, + 0x01000301U, + 0x07FFFFFFU, + 0x0000003FU, + 0x00000000U, + 0x00000000U, + 0x07FF07FFU, + 0x000007FFU, + 0x00FFFFFFU, + 0x03FFFFFFU, + 0x01FF0F03U, + 0x07000001U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x000FFFFFU, + 0x3FFFFFFFU, + 0x3F3F03FFU, + 0x3F0F3F3FU, + 0xFFFFFF03U, + 0x01FFFFFFU, + 0x3F03FFFFU, + 0x0101FFFFU, + 0x00003F01U, + 0x07FF07FFU, + 0x07FF1F07U, + 0x1F07FF1FU, + 0x001F07FFU, + 0x001F07FFU, + 0x001F07FFU, + 0x000F07FFU, + 0xFF3F07FFU, + 0x0103FFFFU, + 0x0000000FU, + 0x03FF010FU, + 0x0000FF01U +}; + +u32 g_lpddr4_phy_core_rw_mask[] = { + 0x00000003U, + 0x1F030101U, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x1F1F1F1FU, + 0x001F1F1FU, + 0x011F07FFU, + 0x07FF0100U, + 0x000107FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x0101FF01U, + 0x0007FF0FU, + 0xFF0F07FFU, + 0x01030007U, + 0xFFFF0101U, + 0xFF3F0103U, + 0x010101FFU, + 0x0F0F0100U, + 0x0F010F0FU, + 0x010F0F0FU, + 0xFFFF0101U, + 0x0001010FU, + 0x00000000U, + 0x0000FFFFU, + 0x00000001U, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x0F0F0F0FU, + 0x00FF01FFU, + 0xFFFF1FFFU, + 0x0000FF01U, + 0x00000000U, + 0x00000000U, + 0x0FFF0FFFU, + 0x00000000U, + 0x00000000U, + 0x0FFF0FFFU, + 0x0F010101U, + 0x03FF01FFU, + 0x0101FFFFU, + 0x0003FFFFU, + 0x0001FFFFU, + 0x0001FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x0003FFFFU, + 0x1FFF03FFU, + 0x00001FFFU, + 0xFFFFFFFFU, + 0x000007FFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x7F000000U, + 0x01FFFFFFU, + 0x00000000U, + 0x00000000U, + 0x0FFFFFFFU, + 0x000FFFFFU, + 0x01FFFFFFU, + 0x3F7FFFFFU, + 0x3F3F1F3FU, + 0x1F3F3F1FU, + 0x001F3F3FU, + 0x0000FFFFU, + 0x01FF0F03U, + 0x00000F7FU, + 0x00000000U, + 0x003F0101U, + 0x01010000U, + 0x00000001U, + 0xFFFFFFFFU, + 0x071F01FFU, + 0x03030303U, + 0xFFFFFFFFU, + 0x03FFFFFFU, + 0x00FF073FU, + 0x0707FFFFU, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000003U, + 0x1F010101U, + 0x0000000FU, + 0x0003FFFFU, + 0x0703FFFFU, + 0x00000001U, + 0x00011FFFU, + 0x0F0F0FFFU, + 0x010103FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x07FF07FFU, + 0x000007FFU, + 0x000007FFU, + 0x000007FFU, + 0x000007FFU, + 0x00000007U, + 0x3FFFFFFFU, + 0x0003FFFFU, + 0x7FFFFFFFU, + 0xFFFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0xFFFFFFFFU, + 0x0007FFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x3FFFFFFFU, + 0x0FFFFFFFU, + 0x7FFFFF07U +}; diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c similarity index 99% rename from drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c rename to drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c index 09b0e3c5a0..249b56db65 100644 --- a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c +++ b/drivers/ram/k3-ddrss/lpddr4_am64_ctl_regs_rw_masks.c @@ -2,12 +2,12 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #include -#include "lpddr4_ctl_regs_rw_masks.h" +#include u32 g_lpddr4_ddr_controller_rw_mask[] = { 0x00000F01U, diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.c b/drivers/ram/k3-ddrss/lpddr4_am6x.c similarity index 97% rename from drivers/ram/k3-ddrss/lpddr4_16bit.c rename to drivers/ram/k3-ddrss/lpddr4_am6x.c index b749b74897..8ccc1f1aff 100644 --- a/drivers/ram/k3-ddrss/lpddr4_16bit.c +++ b/drivers/ram/k3-ddrss/lpddr4_am6x.c @@ -2,19 +2,18 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #include - #include "cps_drv_lpddr4.h" #include "lpddr4_ctl_regs.h" #include "lpddr4_if.h" #include "lpddr4.h" #include "lpddr4_structs_if.h" -static u32 ctlintmap[51][3] = { +static u16 ctlintmap[51][3] = { { 0, 0, 7 }, { 1, 0, 8 }, { 2, 0, 9 }, @@ -86,6 +85,7 @@ u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd) CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval); regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG))); CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval); + return result; } @@ -345,15 +345,18 @@ u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mr result = (u32)EIO; } else { *mrrstatus = (u8)0; +#ifdef CONFIG_K3_AM64_DDRSS lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG)); +#else + lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG)); + *mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG)); +#endif *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata); result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE); } return result; } -#ifdef REG_WRITE_VERIF - u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) { u32 rwmask = 0U; @@ -370,7 +373,6 @@ u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) } return rwmask; } -#endif u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam) { diff --git a/drivers/ram/k3-ddrss/lpddr4_am6x.h b/drivers/ram/k3-ddrss/lpddr4_am6x.h new file mode 100644 index 0000000000..bc707d9905 --- /dev/null +++ b/drivers/ram/k3-ddrss/lpddr4_am6x.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Cadence DDR Driver + * + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef LPDDR4_AM6X_H +#define LPDDR4_AM6X_H + +#ifdef CONFIG_K3_AM64_DDRSS +#include "lpddr4_am64_ctl_regs_rw_masks.h" +#elif CONFIG_K3_AM62A_DDRSS +#include "lpddr4_am62a_ctl_regs_rw_masks.h" +#endif + +#ifdef CONFIG_K3_AM64_DDRSS +#define DSLICE_NUM (2U) +#define ASLICE_NUM (2U) +#define DSLICE0_REG_COUNT (126U) +#define DSLICE1_REG_COUNT (126U) +#define ASLICE0_REG_COUNT (42U) +#define ASLICE1_REG_COUNT (42U) +#define ASLICE2_REG_COUNT (42U) +#define PHY_CORE_REG_COUNT (126U) + +#elif CONFIG_K3_AM62A_DDRSS +#define DSLICE_NUM (4U) +#define ASLICE_NUM (3U) +#define DSLICE0_REG_COUNT (136U) +#define DSLICE1_REG_COUNT (136U) +#define DSLICE2_REG_COUNT (136U) +#define DSLICE3_REG_COUNT (136U) +#define ASLICE0_REG_COUNT (48U) +#define ASLICE1_REG_COUNT (48U) +#define ASLICE2_REG_COUNT (48U) +#define PHY_CORE_REG_COUNT (132U) + +#endif + +#define GRP_SHIFT 1 +#define INT_SHIFT 2 + +#endif /* LPDDR4_AM6X_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h similarity index 97% rename from drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h rename to drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h index fde05cea1f..18762cbb28 100644 --- a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h +++ b/drivers/ram/k3-ddrss/lpddr4_am6x_sanity.h @@ -2,19 +2,19 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef LPDDR4_16BIT_SANITY_H -#define LPDDR4_16BIT_SANITY_H +#ifndef LPDDR4_AM6X_SANITY_H +#define LPDDR4_AM6X_SANITY_H #include #include #include -#ifdef __cplusplus -extern "C" { -#endif +#include +#include +#include static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus); static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr); @@ -250,8 +250,4 @@ static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, cons return ret; } -#ifdef __cplusplus -} -#endif - -#endif /* LPDDR4_16BIT_SANITY_H */ +#endif /* LPDDR4_AM6X_SANITY_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_if.h b/drivers/ram/k3-ddrss/lpddr4_if.h index 7562989d99..1d8bcf7d38 100644 --- a/drivers/ram/k3-ddrss/lpddr4_if.h +++ b/drivers/ram/k3-ddrss/lpddr4_if.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef LPDDR4_IF_H @@ -11,9 +11,11 @@ #include #ifdef CONFIG_K3_AM64_DDRSS -#include +#include +#elif CONFIG_K3_AM62A_DDRSS +#include #else -#include +#include #endif typedef struct lpddr4_config_s lpddr4_config; @@ -141,4 +143,6 @@ u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum * u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval); +u32 lpddr4_deferredregverify(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount); + #endif /* LPDDR4_IF_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.c b/drivers/ram/k3-ddrss/lpddr4_j721e.c similarity index 98% rename from drivers/ram/k3-ddrss/lpddr4_32bit.c rename to drivers/ram/k3-ddrss/lpddr4_j721e.c index ab2e44891d..5db7e5c228 100644 --- a/drivers/ram/k3-ddrss/lpddr4_32bit.c +++ b/drivers/ram/k3-ddrss/lpddr4_j721e.c @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #include @@ -273,8 +273,6 @@ u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mr return result; } -#ifdef REG_WRITE_VERIF - u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) { u32 rwmask = 0U; @@ -299,4 +297,3 @@ u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset) } return rwmask; } -#endif diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.h b/drivers/ram/k3-ddrss/lpddr4_j721e.h similarity index 56% rename from drivers/ram/k3-ddrss/lpddr4_32bit.h rename to drivers/ram/k3-ddrss/lpddr4_j721e.h index 1f7fe658af..f115af7785 100644 --- a/drivers/ram/k3-ddrss/lpddr4_32bit.h +++ b/drivers/ram/k3-ddrss/lpddr4_j721e.h @@ -2,20 +2,18 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef LPDDR4_32BIT_H -#define LPDDR4_32BIT_H +#ifndef LPDDR4_J721E_H +#define LPDDR4_J721E_H + +#include "lpddr4_j721e_ctl_regs_rw_masks.h" #define DSLICE_NUM (4U) #define ASLICE_NUM (1U) -#ifdef __cplusplus -extern "C" { -#endif - #define DSLICE0_REG_COUNT (140U) #define DSLICE1_REG_COUNT (140U) #define DSLICE2_REG_COUNT (140U) @@ -23,8 +21,4 @@ extern "C" { #define ASLICE0_REG_COUNT (52U) #define PHY_CORE_REG_COUNT (140U) -#ifdef __cplusplus -} -#endif - -#endif /* LPDDR4_32BIT_H */ +#endif /* LPDDR4_J721E_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c similarity index 99% rename from drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c rename to drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c index 70f0ef5942..24394747da 100644 --- a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c +++ b/drivers/ram/k3-ddrss/lpddr4_j721e_ctl_regs_rw_masks.c @@ -2,12 +2,12 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #include -#include "lpddr4_ctl_regs_rw_masks.h" +#include u32 g_lpddr4_ddr_controller_rw_mask[] = { 0x00000F01U, diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h similarity index 96% rename from drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h rename to drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h index 334eecc8aa..174002f120 100644 --- a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h +++ b/drivers/ram/k3-ddrss/lpddr4_j721e_sanity.h @@ -2,19 +2,16 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ -#ifndef LPDDR4_32BIT_SANITY_H -#define LPDDR4_32BIT_SANITY_H +#ifndef LPDDR4_J721E_SANITY_H +#define LPDDR4_J721E_SANITY_H #include #include #include -#ifdef __cplusplus -extern "C" { -#endif static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus); static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr); @@ -216,8 +213,4 @@ static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, cons return ret; } -#ifdef __cplusplus -} -#endif - -#endif /* LPDDR4_32BIT_SANITY_H */ +#endif /* LPDDR4_J721E_SANITY_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/drivers/ram/k3-ddrss/lpddr4_obj_if.c index 370242f5bd..63b259c33d 100644 --- a/drivers/ram/k3-ddrss/lpddr4_obj_if.c +++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.c @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #include "lpddr4_obj_if.h" @@ -45,6 +45,7 @@ lpddr4_obj *lpddr4_getinstance(void) .getrefreshrate = lpddr4_getrefreshrate, .setrefreshrate = lpddr4_setrefreshrate, .refreshperchipselect = lpddr4_refreshperchipselect, + .deferredregverify = lpddr4_deferredregverify, }; return &driver; diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/drivers/ram/k3-ddrss/lpddr4_obj_if.h index d538e61b74..b1bbb5cc1a 100644 --- a/drivers/ram/k3-ddrss/lpddr4_obj_if.h +++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef lpddr4_obj_if_h @@ -79,6 +79,8 @@ typedef struct lpddr4_obj_s { u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval); + + u32 (*deferredregverify)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regvalues[], u16 regnum[], u16 regcount); } lpddr4_obj; extern lpddr4_obj *lpddr4_getinstance(void); diff --git a/drivers/ram/k3-ddrss/lpddr4_private.h b/drivers/ram/k3-ddrss/lpddr4_private.h deleted file mode 100644 index 3d5017ea47..0000000000 --- a/drivers/ram/k3-ddrss/lpddr4_private.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause */ -/********************************************************************** - * Copyright (C) 2012-2018 Cadence Design Systems, Inc. - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ - ********************************************************************** - * Cadence Core Driver for LPDDR4. - ********************************************************************** - */ - -#ifndef LPDDR4_PRIV_H -#define LPDDR4_PRIV_H - -#define PRODUCT_ID (0x1046U) -#define VERSION_0 (0x54d5da40U) -#define VERSION_1 (0xc1865a1U) - -#define LPDDR4_BIT_MASK (0x1U) -#define BYTE_MASK (0xffU) -#define NIBBLE_MASK (0xfU) - -#define WORD_SHIFT (32U) -#define WORD_MASK (0xffffffffU) -#define SLICE_WIDTH (0x100) -/* Number of Data slices */ -#define DSLICE_NUM (4U) -/*Number of Address Slices */ -#define ASLICE_NUM (1U) - -/* Number of accessible registers in each slice */ -#define DSLICE0_REG_COUNT (140U) -#define DSLICE1_REG_COUNT (140U) -#define DSLICE2_REG_COUNT (140U) -#define DSLICE3_REG_COUNT (140U) -#define ASLICE0_REG_COUNT (52U) -#define PHY_CORE_REG_COUNT (140U) - -#define CTL_OFFSET 0 -#define PI_OFFSET (((uint32_t)1) << 11) -#define PHY_OFFSET (((uint32_t)1) << 12) - -/* BIT[17] on INT_MASK_1 register. */ -#define CTL_INT_MASK_ALL ((uint32_t)LPDDR4_LOR_BITS - WORD_SHIFT) - -/* Init Error information bits */ -#define PLL_READY (0x3U) -#define IO_CALIB_DONE ((uint32_t)0x1U << 23U) -#define IO_CALIB_FIELD ((uint32_t)NIBBLE_MASK << 28U) -#define IO_CALIB_STATE ((uint32_t)0xBU << 28U) -#define RX_CAL_DONE ((uint32_t)LPDDR4_BIT_MASK << 4U) -#define CA_TRAIN_RL (((uint32_t)LPDDR4_BIT_MASK << 5U) | \ - ((uint32_t)LPDDR4_BIT_MASK << 4U)) -#define WR_LVL_STATE (((uint32_t)NIBBLE_MASK) << 13U) -#define GATE_LVL_ERROR_FIELDS (((uint32_t)LPDDR4_BIT_MASK << 7U) | \ - ((uint32_t)LPDDR4_BIT_MASK << 6U)) -#define READ_LVL_ERROR_FIELDS ((((uint32_t)NIBBLE_MASK) << 28U) | \ - (((uint32_t)BYTE_MASK) << 16U)) -#define DQ_LVL_STATUS (((uint32_t)LPDDR4_BIT_MASK << 26U) | \ - (((uint32_t)BYTE_MASK) << 18U)) - -#endif /* LPDDR4_PRIV_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_sanity.h b/drivers/ram/k3-ddrss/lpddr4_sanity.h index 750e00d3f5..d5e61ff5ea 100644 --- a/drivers/ram/k3-ddrss/lpddr4_sanity.h +++ b/drivers/ram/k3-ddrss/lpddr4_sanity.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef LPDDR4_SANITY_H @@ -12,9 +12,6 @@ #include #include #include "lpddr4_if.h" -#ifdef __cplusplus -extern "C" { -#endif static inline u32 lpddr4_configsf(const lpddr4_config *obj); static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj); @@ -37,7 +34,7 @@ static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lp static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off); static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); -static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); +static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val); static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); #define lpddr4_probesf lpddr4_sanityfunction1 @@ -70,6 +67,7 @@ static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lp #define lpddr4_getrefreshratesf lpddr4_sanityfunction28 #define lpddr4_setrefreshratesf lpddr4_sanityfunction29 #define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3 +#define lpddr4_deferredregverifysf lpddr4_sanityfunction5 static inline u32 lpddr4_configsf(const lpddr4_config *obj) { @@ -390,15 +388,15 @@ static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lp return ret; } -static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max) +static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref_val, const u32 *tras_max_val) { u32 ret = 0; if (fspnum == NULL) { ret = EINVAL; - } else if (tref == NULL) { + } else if (tref_val == NULL) { ret = EINVAL; - } else if (tras_max == NULL) { + } else if (tras_max_val == NULL) { ret = EINVAL; } else if (lpddr4_privatedatasf(pd) == EINVAL) { ret = EINVAL; @@ -438,8 +436,4 @@ static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lp return ret; } -#ifdef __cplusplus -} -#endif - #endif /* LPDDR4_SANITY_H */ diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h index f2f1210c3c..b09e708de4 100644 --- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h +++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h @@ -2,8 +2,8 @@ /* * Cadence DDR Driver * - * Copyright (C) 2012-2021 Cadence Design Systems, Inc. - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2012-2022 Cadence Design Systems, Inc. + * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef LPDDR4_STRUCTS_IF_H From 253802912a65fde6ba9328462ef4b8574932c8f3 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:51 -0500 Subject: [PATCH 138/424] arm: dts: introduce am62a7 dtbs from linux kernel Introduce the basic am62a7 SoC dtbs from the v6.1-rc3 tag of the linux kernel along with the new am62a specific pinmux definition that we will use to generate the dtbs for the u-boot-spl and u-boot binaries Co-developed-by: Vignesh Raghavendra Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- arch/arm/dts/k3-am62a-main.dtsi | 298 ++++++++++++++++++++++++++++++ arch/arm/dts/k3-am62a-mcu.dtsi | 39 ++++ arch/arm/dts/k3-am62a-wakeup.dtsi | 54 ++++++ arch/arm/dts/k3-am62a.dtsi | 122 ++++++++++++ arch/arm/dts/k3-am62a7-sk.dts | 223 ++++++++++++++++++++++ arch/arm/dts/k3-am62a7.dtsi | 103 +++++++++++ include/dt-bindings/pinctrl/k3.h | 3 + 7 files changed, 842 insertions(+) create mode 100644 arch/arm/dts/k3-am62a-main.dtsi create mode 100644 arch/arm/dts/k3-am62a-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62a-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62a.dtsi create mode 100644 arch/arm/dts/k3-am62a7-sk.dts create mode 100644 arch/arm/dts/k3-am62a7.dtsi diff --git a/arch/arm/dts/k3-am62a-main.dtsi b/arch/arm/dts/k3-am62a-main.dtsi new file mode 100644 index 0000000000..bc4b50bcd1 --- /dev/null +++ b/arch/arm/dts/k3-am62a-main.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family Main Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@100000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00100000 0x20000>; + }; + + dmss: bus@48000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + reg-names = "target_data", "rt", "scfg"; + #mbox-cells = <1>; + interrupt-names = "rx_012"; + interrupts = ; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + reg = <0x00 0x44043000 0x00 0xfe0>; + reg-names = "debug_messages"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + status = "disabled"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + status = "disabled"; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + status = "disabled"; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + bus-width = <4>; + no-1-8-v; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a-mcu.dtsi b/arch/arm/dts/k3-am62a-mcu.dtsi new file mode 100644 index 0000000000..6d1e501b94 --- /dev/null +++ b/arch/arm/dts/k3-am62a-mcu.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + status = "disabled"; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a-wakeup.dtsi b/arch/arm/dts/k3-am62a-wakeup.dtsi new file mode 100644 index 0000000000..99afac40e8 --- /dev/null +++ b/arch/arm/dts/k3-am62a-wakeup.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + status = "disabled"; + }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/k3-am62a.dtsi b/arch/arm/dts/k3-am62a.dtsi new file mode 100644 index 0000000000..6eb87c3f9f --- /dev/null +++ b/arch/arm/dts/k3-am62a.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A SoC Family + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM62A SoC"; + compatible = "ti,am62a7"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00100000>, /* C7x_0 */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */ + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */ + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62a-main.dtsi" +#include "k3-am62a-mcu.dtsi" +#include "k3-am62a-wakeup.dtsi" diff --git a/arch/arm/dts/k3-am62a7-sk.dts b/arch/arm/dts/k3-am62a7-sk.dts new file mode 100644 index 0000000000..576dbce80a --- /dev/null +++ b/arch/arm/dts/k3-am62a7-sk.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A SK: https://www.ti.com/lit/zip/sprr459 + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include "k3-am62a7.dtsi" + +/ { + compatible = "ti,am62a7-sk", "ti,am62a7"; + model = "Texas Instruments AM62A7 SK"; + + aliases { + serial2 = &main_uart0; + mmc1 = &sdhci1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS25750 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS63070 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM5141-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62a-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62AX_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62AX_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "BT_EN_SOC", "MMC1_SD_EN", + "VPP_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", + "GPIO_HDMI_RSTn", "CSI_GPIO0", + "CSI_GPIO1", "WLAN_ALERTn", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "PD_I2C_IRQ", "IO_EXP_TEST_LED"; + }; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + vmmc-supply = <&vdd_mmc1>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_gpio0 { + status = "okay"; +}; + +&main_gpio1 { + status = "okay"; +}; + +&main_gpio_intr { + status = "okay"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; diff --git a/arch/arm/dts/k3-am62a7.dtsi b/arch/arm/dts/k3-am62a7.dtsi new file mode 100644 index 0000000000..331d89fda2 --- /dev/null +++ b/arch/arm/dts/k3-am62a7.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62A7 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/zip/spruj16 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62a.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index a5204ab91d..e8418318eb 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -44,4 +44,7 @@ #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif From 6bdfa69155d8816ccb0512ed8b4adf19c3b8cc32 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:52 -0500 Subject: [PATCH 139/424] arm: dts: introduce am62a7 u-boot dtbs Introduce the base dts files needed for u-boot or to augment the linux dtbs for use in the u-boot-spl and u-boot binaries Signed-off-by: Vignesh Raghavendra Signed-off-by: Bryan Brattlof --- arch/arm/dts/Makefile | 3 + arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi | 2798 +++++++++++++++++ arch/arm/dts/k3-am62a-ddr.dtsi | 2814 ++++++++++++++++++ arch/arm/dts/k3-am62a7-r5-sk.dts | 143 + arch/arm/dts/k3-am62a7-sk-u-boot.dtsi | 140 + 5 files changed, 5898 insertions(+) create mode 100644 arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi create mode 100644 arch/arm/dts/k3-am62a-ddr.dtsi create mode 100644 arch/arm/dts/k3-am62a7-r5-sk.dts create mode 100644 arch/arm/dts/k3-am62a7-sk-u-boot.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 43951a7731..b3baaf4829 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1259,6 +1259,9 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ k3-am625-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM625) += k3-am62a7-sk.dtb \ + k3-am62a7-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi new file mode 100644 index 0000000000..9f50d7eae6 --- /dev/null +++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi @@ -0,0 +1,2798 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01 + * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1866MHz + * Density (per channel): 8Gb + * Number of Ranks: 2 + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004B4B +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x00720014 +#define DDRSS_CTL_51_DATA 0x09140050 +#define DDRSS_CTL_52_DATA 0x00004D22 +#define DDRSS_CTL_53_DATA 0x00720014 +#define DDRSS_CTL_54_DATA 0x09140050 +#define DDRSS_CTL_55_DATA 0x09004D22 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090F2005 +#define DDRSS_CTL_59_DATA 0x00001B13 +#define DDRSS_CTL_60_DATA 0x0E00FFCD +#define DDRSS_CTL_61_DATA 0x090F200F +#define DDRSS_CTL_62_DATA 0x00001B13 +#define DDRSS_CTL_63_DATA 0x0E00FFCD +#define DDRSS_CTL_64_DATA 0x0304200F +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x24232423 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x04464607 +#define DDRSS_CTL_69_DATA 0x03282803 +#define DDRSS_CTL_70_DATA 0x00002828 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x000E0803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x0000020B +#define DDRSS_CTL_77_DATA 0x00001C64 +#define DDRSS_CTL_78_DATA 0x0000020B +#define DDRSS_CTL_79_DATA 0x00001C64 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x00000007 +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000106 +#define DDRSS_CTL_84_DATA 0x00000386 +#define DDRSS_CTL_85_DATA 0x00000106 +#define DDRSS_CTL_86_DATA 0x00000386 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000E0005 +#define DDRSS_CTL_90_DATA 0x2608000E +#define DDRSS_CTL_91_DATA 0x0A050526 +#define DDRSS_CTL_92_DATA 0x1B0E0A03 +#define DDRSS_CTL_93_DATA 0x1B0E0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x000F000F +#define DDRSS_CTL_97_DATA 0x02190219 +#define DDRSS_CTL_98_DATA 0x02190219 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041C04 +#define DDRSS_CTL_103_DATA 0x0E0A0E0A +#define DDRSS_CTL_104_DATA 0x0A04041C +#define DDRSS_CTL_105_DATA 0x030E0A0E +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00071900 +#define DDRSS_CTL_127_DATA 0x00071900 +#define DDRSS_CTL_128_DATA 0x00071900 +#define DDRSS_CTL_129_DATA 0x00071900 +#define DDRSS_CTL_130_DATA 0x00071900 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000C6BC +#define DDRSS_CTL_133_DATA 0x00071900 +#define DDRSS_CTL_134_DATA 0x00071900 +#define DDRSS_CTL_135_DATA 0x00071900 +#define DDRSS_CTL_136_DATA 0x00071900 +#define DDRSS_CTL_137_DATA 0x00071900 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000C6BC +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00BB0176 +#define DDRSS_CTL_199_DATA 0x0E0E01D3 +#define DDRSS_CTL_200_DATA 0x000001D3 +#define DDRSS_CTL_201_DATA 0x00BB0176 +#define DDRSS_CTL_202_DATA 0x0E0E01D3 +#define DDRSS_CTL_203_DATA 0x000001D3 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000064 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000064 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000064 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000064 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000031 +#define DDRSS_CTL_231_DATA 0x000000B1 +#define DDRSS_CTL_232_DATA 0x000000B1 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x55005555 +#define DDRSS_CTL_258_DATA 0x00002755 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x074A0040 +#define DDRSS_CTL_316_DATA 0x00020038 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x0038074A +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x005E005E +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000202 +#define DDRSS_CTL_324_DATA 0x0FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0x1FFF1000 +#define DDRSS_CTL_327_DATA 0x000FFF00 +#define DDRSS_CTL_328_DATA 0x0B000001 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C03 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0E081B1B +#define DDRSS_CTL_389_DATA 0x0008030E +#define DDRSS_CTL_390_DATA 0x0B12030E +#define DDRSS_CTL_391_DATA 0x0B120314 +#define DDRSS_CTL_392_DATA 0x12120814 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x07030701 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03050202 +#define DDRSS_CTL_405_DATA 0x37200201 +#define DDRSS_CTL_406_DATA 0x000038C8 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000FF84 +#define DDRSS_CTL_412_DATA 0x000237D0 +#define DDRSS_CTL_413_DATA 0x111F0402 +#define DDRSS_CTL_414_DATA 0x37200C0D +#define DDRSS_CTL_415_DATA 0x000038C8 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000FF84 +#define DDRSS_CTL_421_DATA 0x000237D0 +#define DDRSS_CTL_422_DATA 0x111F0402 +#define DDRSS_CTL_423_DATA 0x00200C0D +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x000F0001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x0F000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x000F0F00 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x0000170F +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010F00 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x02010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x01180118 +#define DDRSS_PI_178_DATA 0x00262601 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005E +#define DDRSS_PI_181_DATA 0x0002005E +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x0000000E +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x0000020B +#define DDRSS_PI_190_DATA 0x00001C64 +#define DDRSS_PI_191_DATA 0x0000020B +#define DDRSS_PI_192_DATA 0x04001C64 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00270027 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001B0043 +#define DDRSS_PI_210_DATA 0x001B0043 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301D3 +#define DDRSS_PI_214_DATA 0x010001D3 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01D40100 +#define DDRSS_PI_217_DATA 0x010001D4 +#define DDRSS_PI_218_DATA 0x01D401D4 +#define DDRSS_PI_219_DATA 0x32103200 +#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1C11090D +#define DDRSS_PI_223_DATA 0x1C110913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0021000D +#define DDRSS_PI_231_DATA 0x002101D3 +#define DDRSS_PI_232_DATA 0x000001D3 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00250204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000101 +#define DDRSS_PI_239_DATA 0x00250C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000101 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000062B +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x280F0000 +#define DDRSS_PI_249_DATA 0x24090023 +#define DDRSS_PI_250_DATA 0x0000E638 +#define DDRSS_PI_251_DATA 0x20070050 +#define DDRSS_PI_252_DATA 0x1B131B1C +#define DDRSS_PI_253_DATA 0x280F0000 +#define DDRSS_PI_254_DATA 0x24090023 +#define DDRSS_PI_255_DATA 0x0000E638 +#define DDRSS_PI_256_DATA 0x20070050 +#define DDRSS_PI_257_DATA 0x1B131B1C +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000038C8 +#define DDRSS_PI_262_DATA 0x000237D0 +#define DDRSS_PI_263_DATA 0x000038C8 +#define DDRSS_PI_264_DATA 0x000237D0 +#define DDRSS_PI_265_DATA 0x0219000F +#define DDRSS_PI_266_DATA 0x03030219 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x0000000F +#define DDRSS_PI_276_DATA 0x0005B18F +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000E94 +#define DDRSS_PI_280_DATA 0x00000219 +#define DDRSS_PI_281_DATA 0x0005B18F +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000E94 +#define DDRSS_PI_285_DATA 0x01000219 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x074A0040 +#define DDRSS_PI_289_DATA 0x00010038 +#define DDRSS_PI_290_DATA 0x074A0040 +#define DDRSS_PI_291_DATA 0x00000338 +#define DDRSS_PI_292_DATA 0x0028005D +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000064 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x000000B1 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x55000000 +#define DDRSS_PI_343_DATA 0x20162B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000064 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x000000B1 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x55000000 +#define DDRSS_PI_351_DATA 0x20162B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000031 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000064 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x000000B1 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x55000000 +#define DDRSS_PI_367_DATA 0x20162B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000064 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x000000B1 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x55000000 +#define DDRSS_PI_375_DATA 0x20162B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000031 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000064 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x000000B1 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x55000000 +#define DDRSS_PI_391_DATA 0x20162B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000064 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x000000B1 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x55000000 +#define DDRSS_PI_399_DATA 0x20162B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000031 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000064 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x000000B1 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x55000000 +#define DDRSS_PI_415_DATA 0x20162B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000064 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x000000B1 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x55000000 +#define DDRSS_PI_423_DATA 0x20162B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000004 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02040010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C32 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x011E0120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x000002DD +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x045D045D +#define DDRSS_PHY_114_DATA 0x045D045D +#define DDRSS_PHY_115_DATA 0x045D045D +#define DDRSS_PHY_116_DATA 0x045D045D +#define DDRSS_PHY_117_DATA 0x0000045D +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00B200A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000004 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02040010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C32 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x011E0120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x000002DD +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x045D045D +#define DDRSS_PHY_370_DATA 0x045D045D +#define DDRSS_PHY_371_DATA 0x045D045D +#define DDRSS_PHY_372_DATA 0x045D045D +#define DDRSS_PHY_373_DATA 0x0000045D +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00B200A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000004 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02040010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C32 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x011E0120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x000002DD +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x045D045D +#define DDRSS_PHY_626_DATA 0x045D045D +#define DDRSS_PHY_627_DATA 0x045D045D +#define DDRSS_PHY_628_DATA 0x045D045D +#define DDRSS_PHY_629_DATA 0x0000045D +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00B200A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000004 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02040010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C32 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x011E0120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x000002DD +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x045D045D +#define DDRSS_PHY_882_DATA 0x045D045D +#define DDRSS_PHY_883_DATA 0x045D045D +#define DDRSS_PHY_884_DATA 0x045D045D +#define DDRSS_PHY_885_DATA 0x0000045D +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00B200A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00005201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x00000AC4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F11 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a-ddr.dtsi new file mode 100644 index 0000000000..15a0799550 --- /dev/null +++ b/arch/arm/dts/k3-am62a-ddr.dtsi @@ -0,0 +1,2814 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + memorycontroller: memory-controller@f308000 { + compatible = "ti,am62a-ddrss"; + reg = <0x00 0x0f308000 0x00 0x4000>, + <0x00 0x43014000 0x00 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + ti,ddr-freq1 = ; + ti,ddr-freq2 = ; + ti,ddr-fhs-cnt = ; + + power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>, + <&k3_pds 55 TI_SCI_PD_SHARED>; + clocks = <&k3_clks 170 1>, <&k3_clks 16 4>; + + u-boot,dm-spl; + + ti,ctl-data = < + DDRSS_CTL_0_DATA + DDRSS_CTL_1_DATA + DDRSS_CTL_2_DATA + DDRSS_CTL_3_DATA + DDRSS_CTL_4_DATA + DDRSS_CTL_5_DATA + DDRSS_CTL_6_DATA + DDRSS_CTL_7_DATA + DDRSS_CTL_8_DATA + DDRSS_CTL_9_DATA + DDRSS_CTL_10_DATA + DDRSS_CTL_11_DATA + DDRSS_CTL_12_DATA + DDRSS_CTL_13_DATA + DDRSS_CTL_14_DATA + DDRSS_CTL_15_DATA + DDRSS_CTL_16_DATA + DDRSS_CTL_17_DATA + DDRSS_CTL_18_DATA + DDRSS_CTL_19_DATA + DDRSS_CTL_20_DATA + DDRSS_CTL_21_DATA + DDRSS_CTL_22_DATA + DDRSS_CTL_23_DATA + DDRSS_CTL_24_DATA + DDRSS_CTL_25_DATA + DDRSS_CTL_26_DATA + DDRSS_CTL_27_DATA + DDRSS_CTL_28_DATA + DDRSS_CTL_29_DATA + DDRSS_CTL_30_DATA + DDRSS_CTL_31_DATA + DDRSS_CTL_32_DATA + DDRSS_CTL_33_DATA + DDRSS_CTL_34_DATA + DDRSS_CTL_35_DATA + DDRSS_CTL_36_DATA + DDRSS_CTL_37_DATA + DDRSS_CTL_38_DATA + DDRSS_CTL_39_DATA + DDRSS_CTL_40_DATA + DDRSS_CTL_41_DATA + DDRSS_CTL_42_DATA + DDRSS_CTL_43_DATA + DDRSS_CTL_44_DATA + DDRSS_CTL_45_DATA + DDRSS_CTL_46_DATA + DDRSS_CTL_47_DATA + DDRSS_CTL_48_DATA + DDRSS_CTL_49_DATA + DDRSS_CTL_50_DATA + DDRSS_CTL_51_DATA + DDRSS_CTL_52_DATA + DDRSS_CTL_53_DATA + DDRSS_CTL_54_DATA + DDRSS_CTL_55_DATA + DDRSS_CTL_56_DATA + DDRSS_CTL_57_DATA + DDRSS_CTL_58_DATA + DDRSS_CTL_59_DATA + DDRSS_CTL_60_DATA + DDRSS_CTL_61_DATA + DDRSS_CTL_62_DATA + DDRSS_CTL_63_DATA + DDRSS_CTL_64_DATA + DDRSS_CTL_65_DATA + DDRSS_CTL_66_DATA + DDRSS_CTL_67_DATA + DDRSS_CTL_68_DATA + DDRSS_CTL_69_DATA + DDRSS_CTL_70_DATA + DDRSS_CTL_71_DATA + DDRSS_CTL_72_DATA + DDRSS_CTL_73_DATA + DDRSS_CTL_74_DATA + DDRSS_CTL_75_DATA + DDRSS_CTL_76_DATA + DDRSS_CTL_77_DATA + DDRSS_CTL_78_DATA + DDRSS_CTL_79_DATA + DDRSS_CTL_80_DATA + DDRSS_CTL_81_DATA + DDRSS_CTL_82_DATA + DDRSS_CTL_83_DATA + DDRSS_CTL_84_DATA + DDRSS_CTL_85_DATA + DDRSS_CTL_86_DATA + DDRSS_CTL_87_DATA + DDRSS_CTL_88_DATA + DDRSS_CTL_89_DATA + DDRSS_CTL_90_DATA + DDRSS_CTL_91_DATA + DDRSS_CTL_92_DATA + DDRSS_CTL_93_DATA + DDRSS_CTL_94_DATA + DDRSS_CTL_95_DATA + DDRSS_CTL_96_DATA + DDRSS_CTL_97_DATA + DDRSS_CTL_98_DATA + DDRSS_CTL_99_DATA + DDRSS_CTL_100_DATA + DDRSS_CTL_101_DATA + DDRSS_CTL_102_DATA + DDRSS_CTL_103_DATA + DDRSS_CTL_104_DATA + DDRSS_CTL_105_DATA + DDRSS_CTL_106_DATA + DDRSS_CTL_107_DATA + DDRSS_CTL_108_DATA + DDRSS_CTL_109_DATA + DDRSS_CTL_110_DATA + DDRSS_CTL_111_DATA + DDRSS_CTL_112_DATA + DDRSS_CTL_113_DATA + DDRSS_CTL_114_DATA + DDRSS_CTL_115_DATA + DDRSS_CTL_116_DATA + DDRSS_CTL_117_DATA + DDRSS_CTL_118_DATA + DDRSS_CTL_119_DATA + DDRSS_CTL_120_DATA + DDRSS_CTL_121_DATA + DDRSS_CTL_122_DATA + DDRSS_CTL_123_DATA + DDRSS_CTL_124_DATA + DDRSS_CTL_125_DATA + DDRSS_CTL_126_DATA + DDRSS_CTL_127_DATA + DDRSS_CTL_128_DATA + DDRSS_CTL_129_DATA + DDRSS_CTL_130_DATA + DDRSS_CTL_131_DATA + DDRSS_CTL_132_DATA + DDRSS_CTL_133_DATA + DDRSS_CTL_134_DATA + DDRSS_CTL_135_DATA + DDRSS_CTL_136_DATA + DDRSS_CTL_137_DATA + DDRSS_CTL_138_DATA + DDRSS_CTL_139_DATA + DDRSS_CTL_140_DATA + DDRSS_CTL_141_DATA + DDRSS_CTL_142_DATA + DDRSS_CTL_143_DATA + DDRSS_CTL_144_DATA + DDRSS_CTL_145_DATA + DDRSS_CTL_146_DATA + DDRSS_CTL_147_DATA + DDRSS_CTL_148_DATA + DDRSS_CTL_149_DATA + DDRSS_CTL_150_DATA + DDRSS_CTL_151_DATA + DDRSS_CTL_152_DATA + DDRSS_CTL_153_DATA + DDRSS_CTL_154_DATA + DDRSS_CTL_155_DATA + DDRSS_CTL_156_DATA + DDRSS_CTL_157_DATA + DDRSS_CTL_158_DATA + DDRSS_CTL_159_DATA + DDRSS_CTL_160_DATA + DDRSS_CTL_161_DATA + DDRSS_CTL_162_DATA + DDRSS_CTL_163_DATA + DDRSS_CTL_164_DATA + DDRSS_CTL_165_DATA + DDRSS_CTL_166_DATA + DDRSS_CTL_167_DATA + DDRSS_CTL_168_DATA + DDRSS_CTL_169_DATA + DDRSS_CTL_170_DATA + DDRSS_CTL_171_DATA + DDRSS_CTL_172_DATA + DDRSS_CTL_173_DATA + DDRSS_CTL_174_DATA + DDRSS_CTL_175_DATA + DDRSS_CTL_176_DATA + DDRSS_CTL_177_DATA + DDRSS_CTL_178_DATA + DDRSS_CTL_179_DATA + DDRSS_CTL_180_DATA + DDRSS_CTL_181_DATA + DDRSS_CTL_182_DATA + DDRSS_CTL_183_DATA + DDRSS_CTL_184_DATA + DDRSS_CTL_185_DATA + DDRSS_CTL_186_DATA + DDRSS_CTL_187_DATA + DDRSS_CTL_188_DATA + DDRSS_CTL_189_DATA + DDRSS_CTL_190_DATA + DDRSS_CTL_191_DATA + DDRSS_CTL_192_DATA + DDRSS_CTL_193_DATA + DDRSS_CTL_194_DATA + DDRSS_CTL_195_DATA + DDRSS_CTL_196_DATA + DDRSS_CTL_197_DATA + DDRSS_CTL_198_DATA + DDRSS_CTL_199_DATA + DDRSS_CTL_200_DATA + DDRSS_CTL_201_DATA + DDRSS_CTL_202_DATA + DDRSS_CTL_203_DATA + DDRSS_CTL_204_DATA + DDRSS_CTL_205_DATA + DDRSS_CTL_206_DATA + DDRSS_CTL_207_DATA + DDRSS_CTL_208_DATA + DDRSS_CTL_209_DATA + DDRSS_CTL_210_DATA + DDRSS_CTL_211_DATA + DDRSS_CTL_212_DATA + DDRSS_CTL_213_DATA + DDRSS_CTL_214_DATA + DDRSS_CTL_215_DATA + DDRSS_CTL_216_DATA + DDRSS_CTL_217_DATA + DDRSS_CTL_218_DATA + DDRSS_CTL_219_DATA + DDRSS_CTL_220_DATA + DDRSS_CTL_221_DATA + DDRSS_CTL_222_DATA + DDRSS_CTL_223_DATA + DDRSS_CTL_224_DATA + DDRSS_CTL_225_DATA + DDRSS_CTL_226_DATA + DDRSS_CTL_227_DATA + DDRSS_CTL_228_DATA + DDRSS_CTL_229_DATA + DDRSS_CTL_230_DATA + DDRSS_CTL_231_DATA + DDRSS_CTL_232_DATA + DDRSS_CTL_233_DATA + DDRSS_CTL_234_DATA + DDRSS_CTL_235_DATA + DDRSS_CTL_236_DATA + DDRSS_CTL_237_DATA + DDRSS_CTL_238_DATA + DDRSS_CTL_239_DATA + DDRSS_CTL_240_DATA + DDRSS_CTL_241_DATA + DDRSS_CTL_242_DATA + DDRSS_CTL_243_DATA + DDRSS_CTL_244_DATA + DDRSS_CTL_245_DATA + DDRSS_CTL_246_DATA + DDRSS_CTL_247_DATA + DDRSS_CTL_248_DATA + DDRSS_CTL_249_DATA + DDRSS_CTL_250_DATA + DDRSS_CTL_251_DATA + DDRSS_CTL_252_DATA + DDRSS_CTL_253_DATA + DDRSS_CTL_254_DATA + DDRSS_CTL_255_DATA + DDRSS_CTL_256_DATA + DDRSS_CTL_257_DATA + DDRSS_CTL_258_DATA + DDRSS_CTL_259_DATA + DDRSS_CTL_260_DATA + DDRSS_CTL_261_DATA + DDRSS_CTL_262_DATA + DDRSS_CTL_263_DATA + DDRSS_CTL_264_DATA + DDRSS_CTL_265_DATA + DDRSS_CTL_266_DATA + DDRSS_CTL_267_DATA + DDRSS_CTL_268_DATA + DDRSS_CTL_269_DATA + DDRSS_CTL_270_DATA + DDRSS_CTL_271_DATA + DDRSS_CTL_272_DATA + DDRSS_CTL_273_DATA + DDRSS_CTL_274_DATA + DDRSS_CTL_275_DATA + DDRSS_CTL_276_DATA + DDRSS_CTL_277_DATA + DDRSS_CTL_278_DATA + DDRSS_CTL_279_DATA + DDRSS_CTL_280_DATA + DDRSS_CTL_281_DATA + DDRSS_CTL_282_DATA + DDRSS_CTL_283_DATA + DDRSS_CTL_284_DATA + DDRSS_CTL_285_DATA + DDRSS_CTL_286_DATA + DDRSS_CTL_287_DATA + DDRSS_CTL_288_DATA + DDRSS_CTL_289_DATA + DDRSS_CTL_290_DATA + DDRSS_CTL_291_DATA + DDRSS_CTL_292_DATA + DDRSS_CTL_293_DATA + DDRSS_CTL_294_DATA + DDRSS_CTL_295_DATA + DDRSS_CTL_296_DATA + DDRSS_CTL_297_DATA + DDRSS_CTL_298_DATA + DDRSS_CTL_299_DATA + DDRSS_CTL_300_DATA + DDRSS_CTL_301_DATA + DDRSS_CTL_302_DATA + DDRSS_CTL_303_DATA + DDRSS_CTL_304_DATA + DDRSS_CTL_305_DATA + DDRSS_CTL_306_DATA + DDRSS_CTL_307_DATA + DDRSS_CTL_308_DATA + DDRSS_CTL_309_DATA + DDRSS_CTL_310_DATA + DDRSS_CTL_311_DATA + DDRSS_CTL_312_DATA + DDRSS_CTL_313_DATA + DDRSS_CTL_314_DATA + DDRSS_CTL_315_DATA + DDRSS_CTL_316_DATA + DDRSS_CTL_317_DATA + DDRSS_CTL_318_DATA + DDRSS_CTL_319_DATA + DDRSS_CTL_320_DATA + DDRSS_CTL_321_DATA + DDRSS_CTL_322_DATA + DDRSS_CTL_323_DATA + DDRSS_CTL_324_DATA + DDRSS_CTL_325_DATA + DDRSS_CTL_326_DATA + DDRSS_CTL_327_DATA + DDRSS_CTL_328_DATA + DDRSS_CTL_329_DATA + DDRSS_CTL_330_DATA + DDRSS_CTL_331_DATA + DDRSS_CTL_332_DATA + DDRSS_CTL_333_DATA + DDRSS_CTL_334_DATA + DDRSS_CTL_335_DATA + DDRSS_CTL_336_DATA + DDRSS_CTL_337_DATA + DDRSS_CTL_338_DATA + DDRSS_CTL_339_DATA + DDRSS_CTL_340_DATA + DDRSS_CTL_341_DATA + DDRSS_CTL_342_DATA + DDRSS_CTL_343_DATA + DDRSS_CTL_344_DATA + DDRSS_CTL_345_DATA + DDRSS_CTL_346_DATA + DDRSS_CTL_347_DATA + DDRSS_CTL_348_DATA + DDRSS_CTL_349_DATA + DDRSS_CTL_350_DATA + DDRSS_CTL_351_DATA + DDRSS_CTL_352_DATA + DDRSS_CTL_353_DATA + DDRSS_CTL_354_DATA + DDRSS_CTL_355_DATA + DDRSS_CTL_356_DATA + DDRSS_CTL_357_DATA + DDRSS_CTL_358_DATA + DDRSS_CTL_359_DATA + DDRSS_CTL_360_DATA + DDRSS_CTL_361_DATA + DDRSS_CTL_362_DATA + DDRSS_CTL_363_DATA + DDRSS_CTL_364_DATA + DDRSS_CTL_365_DATA + DDRSS_CTL_366_DATA + DDRSS_CTL_367_DATA + DDRSS_CTL_368_DATA + DDRSS_CTL_369_DATA + DDRSS_CTL_370_DATA + DDRSS_CTL_371_DATA + DDRSS_CTL_372_DATA + DDRSS_CTL_373_DATA + DDRSS_CTL_374_DATA + DDRSS_CTL_375_DATA + DDRSS_CTL_376_DATA + DDRSS_CTL_377_DATA + DDRSS_CTL_378_DATA + DDRSS_CTL_379_DATA + DDRSS_CTL_380_DATA + DDRSS_CTL_381_DATA + DDRSS_CTL_382_DATA + DDRSS_CTL_383_DATA + DDRSS_CTL_384_DATA + DDRSS_CTL_385_DATA + DDRSS_CTL_386_DATA + DDRSS_CTL_387_DATA + DDRSS_CTL_388_DATA + DDRSS_CTL_389_DATA + DDRSS_CTL_390_DATA + DDRSS_CTL_391_DATA + DDRSS_CTL_392_DATA + DDRSS_CTL_393_DATA + DDRSS_CTL_394_DATA + DDRSS_CTL_395_DATA + DDRSS_CTL_396_DATA + DDRSS_CTL_397_DATA + DDRSS_CTL_398_DATA + DDRSS_CTL_399_DATA + DDRSS_CTL_400_DATA + DDRSS_CTL_401_DATA + DDRSS_CTL_402_DATA + DDRSS_CTL_403_DATA + DDRSS_CTL_404_DATA + DDRSS_CTL_405_DATA + DDRSS_CTL_406_DATA + DDRSS_CTL_407_DATA + DDRSS_CTL_408_DATA + DDRSS_CTL_409_DATA + DDRSS_CTL_410_DATA + DDRSS_CTL_411_DATA + DDRSS_CTL_412_DATA + DDRSS_CTL_413_DATA + DDRSS_CTL_414_DATA + DDRSS_CTL_415_DATA + DDRSS_CTL_416_DATA + DDRSS_CTL_417_DATA + DDRSS_CTL_418_DATA + DDRSS_CTL_419_DATA + DDRSS_CTL_420_DATA + DDRSS_CTL_421_DATA + DDRSS_CTL_422_DATA + DDRSS_CTL_423_DATA + DDRSS_CTL_424_DATA + DDRSS_CTL_425_DATA + DDRSS_CTL_426_DATA + DDRSS_CTL_427_DATA + DDRSS_CTL_428_DATA + DDRSS_CTL_429_DATA + DDRSS_CTL_430_DATA + DDRSS_CTL_431_DATA + DDRSS_CTL_432_DATA + DDRSS_CTL_433_DATA + DDRSS_CTL_434_DATA + >; + + ti,pi-data = < + DDRSS_PI_0_DATA + DDRSS_PI_1_DATA + DDRSS_PI_2_DATA + DDRSS_PI_3_DATA + DDRSS_PI_4_DATA + DDRSS_PI_5_DATA + DDRSS_PI_6_DATA + DDRSS_PI_7_DATA + DDRSS_PI_8_DATA + DDRSS_PI_9_DATA + DDRSS_PI_10_DATA + DDRSS_PI_11_DATA + DDRSS_PI_12_DATA + DDRSS_PI_13_DATA + DDRSS_PI_14_DATA + DDRSS_PI_15_DATA + DDRSS_PI_16_DATA + DDRSS_PI_17_DATA + DDRSS_PI_18_DATA + DDRSS_PI_19_DATA + DDRSS_PI_20_DATA + DDRSS_PI_21_DATA + DDRSS_PI_22_DATA + DDRSS_PI_23_DATA + DDRSS_PI_24_DATA + DDRSS_PI_25_DATA + DDRSS_PI_26_DATA + DDRSS_PI_27_DATA + DDRSS_PI_28_DATA + DDRSS_PI_29_DATA + DDRSS_PI_30_DATA + DDRSS_PI_31_DATA + DDRSS_PI_32_DATA + DDRSS_PI_33_DATA + DDRSS_PI_34_DATA + DDRSS_PI_35_DATA + DDRSS_PI_36_DATA + DDRSS_PI_37_DATA + DDRSS_PI_38_DATA + DDRSS_PI_39_DATA + DDRSS_PI_40_DATA + DDRSS_PI_41_DATA + DDRSS_PI_42_DATA + DDRSS_PI_43_DATA + DDRSS_PI_44_DATA + DDRSS_PI_45_DATA + DDRSS_PI_46_DATA + DDRSS_PI_47_DATA + DDRSS_PI_48_DATA + DDRSS_PI_49_DATA + DDRSS_PI_50_DATA + DDRSS_PI_51_DATA + DDRSS_PI_52_DATA + DDRSS_PI_53_DATA + DDRSS_PI_54_DATA + DDRSS_PI_55_DATA + DDRSS_PI_56_DATA + DDRSS_PI_57_DATA + DDRSS_PI_58_DATA + DDRSS_PI_59_DATA + DDRSS_PI_60_DATA + DDRSS_PI_61_DATA + DDRSS_PI_62_DATA + DDRSS_PI_63_DATA + DDRSS_PI_64_DATA + DDRSS_PI_65_DATA + DDRSS_PI_66_DATA + DDRSS_PI_67_DATA + DDRSS_PI_68_DATA + DDRSS_PI_69_DATA + DDRSS_PI_70_DATA + DDRSS_PI_71_DATA + DDRSS_PI_72_DATA + DDRSS_PI_73_DATA + DDRSS_PI_74_DATA + DDRSS_PI_75_DATA + DDRSS_PI_76_DATA + DDRSS_PI_77_DATA + DDRSS_PI_78_DATA + DDRSS_PI_79_DATA + DDRSS_PI_80_DATA + DDRSS_PI_81_DATA + DDRSS_PI_82_DATA + DDRSS_PI_83_DATA + DDRSS_PI_84_DATA + DDRSS_PI_85_DATA + DDRSS_PI_86_DATA + DDRSS_PI_87_DATA + DDRSS_PI_88_DATA + DDRSS_PI_89_DATA + DDRSS_PI_90_DATA + DDRSS_PI_91_DATA + DDRSS_PI_92_DATA + DDRSS_PI_93_DATA + DDRSS_PI_94_DATA + DDRSS_PI_95_DATA + DDRSS_PI_96_DATA + DDRSS_PI_97_DATA + DDRSS_PI_98_DATA + DDRSS_PI_99_DATA + DDRSS_PI_100_DATA + DDRSS_PI_101_DATA + DDRSS_PI_102_DATA + DDRSS_PI_103_DATA + DDRSS_PI_104_DATA + DDRSS_PI_105_DATA + DDRSS_PI_106_DATA + DDRSS_PI_107_DATA + DDRSS_PI_108_DATA + DDRSS_PI_109_DATA + DDRSS_PI_110_DATA + DDRSS_PI_111_DATA + DDRSS_PI_112_DATA + DDRSS_PI_113_DATA + DDRSS_PI_114_DATA + DDRSS_PI_115_DATA + DDRSS_PI_116_DATA + DDRSS_PI_117_DATA + DDRSS_PI_118_DATA + DDRSS_PI_119_DATA + DDRSS_PI_120_DATA + DDRSS_PI_121_DATA + DDRSS_PI_122_DATA + DDRSS_PI_123_DATA + DDRSS_PI_124_DATA + DDRSS_PI_125_DATA + DDRSS_PI_126_DATA + DDRSS_PI_127_DATA + DDRSS_PI_128_DATA + DDRSS_PI_129_DATA + DDRSS_PI_130_DATA + DDRSS_PI_131_DATA + DDRSS_PI_132_DATA + DDRSS_PI_133_DATA + DDRSS_PI_134_DATA + DDRSS_PI_135_DATA + DDRSS_PI_136_DATA + DDRSS_PI_137_DATA + DDRSS_PI_138_DATA + DDRSS_PI_139_DATA + DDRSS_PI_140_DATA + DDRSS_PI_141_DATA + DDRSS_PI_142_DATA + DDRSS_PI_143_DATA + DDRSS_PI_144_DATA + DDRSS_PI_145_DATA + DDRSS_PI_146_DATA + DDRSS_PI_147_DATA + DDRSS_PI_148_DATA + DDRSS_PI_149_DATA + DDRSS_PI_150_DATA + DDRSS_PI_151_DATA + DDRSS_PI_152_DATA + DDRSS_PI_153_DATA + DDRSS_PI_154_DATA + DDRSS_PI_155_DATA + DDRSS_PI_156_DATA + DDRSS_PI_157_DATA + DDRSS_PI_158_DATA + DDRSS_PI_159_DATA + DDRSS_PI_160_DATA + DDRSS_PI_161_DATA + DDRSS_PI_162_DATA + DDRSS_PI_163_DATA + DDRSS_PI_164_DATA + DDRSS_PI_165_DATA + DDRSS_PI_166_DATA + DDRSS_PI_167_DATA + DDRSS_PI_168_DATA + DDRSS_PI_169_DATA + DDRSS_PI_170_DATA + DDRSS_PI_171_DATA + DDRSS_PI_172_DATA + DDRSS_PI_173_DATA + DDRSS_PI_174_DATA + DDRSS_PI_175_DATA + DDRSS_PI_176_DATA + DDRSS_PI_177_DATA + DDRSS_PI_178_DATA + DDRSS_PI_179_DATA + DDRSS_PI_180_DATA + DDRSS_PI_181_DATA + DDRSS_PI_182_DATA + DDRSS_PI_183_DATA + DDRSS_PI_184_DATA + DDRSS_PI_185_DATA + DDRSS_PI_186_DATA + DDRSS_PI_187_DATA + DDRSS_PI_188_DATA + DDRSS_PI_189_DATA + DDRSS_PI_190_DATA + DDRSS_PI_191_DATA + DDRSS_PI_192_DATA + DDRSS_PI_193_DATA + DDRSS_PI_194_DATA + DDRSS_PI_195_DATA + DDRSS_PI_196_DATA + DDRSS_PI_197_DATA + DDRSS_PI_198_DATA + DDRSS_PI_199_DATA + DDRSS_PI_200_DATA + DDRSS_PI_201_DATA + DDRSS_PI_202_DATA + DDRSS_PI_203_DATA + DDRSS_PI_204_DATA + DDRSS_PI_205_DATA + DDRSS_PI_206_DATA + DDRSS_PI_207_DATA + DDRSS_PI_208_DATA + DDRSS_PI_209_DATA + DDRSS_PI_210_DATA + DDRSS_PI_211_DATA + DDRSS_PI_212_DATA + DDRSS_PI_213_DATA + DDRSS_PI_214_DATA + DDRSS_PI_215_DATA + DDRSS_PI_216_DATA + DDRSS_PI_217_DATA + DDRSS_PI_218_DATA + DDRSS_PI_219_DATA + DDRSS_PI_220_DATA + DDRSS_PI_221_DATA + DDRSS_PI_222_DATA + DDRSS_PI_223_DATA + DDRSS_PI_224_DATA + DDRSS_PI_225_DATA + DDRSS_PI_226_DATA + DDRSS_PI_227_DATA + DDRSS_PI_228_DATA + DDRSS_PI_229_DATA + DDRSS_PI_230_DATA + DDRSS_PI_231_DATA + DDRSS_PI_232_DATA + DDRSS_PI_233_DATA + DDRSS_PI_234_DATA + DDRSS_PI_235_DATA + DDRSS_PI_236_DATA + DDRSS_PI_237_DATA + DDRSS_PI_238_DATA + DDRSS_PI_239_DATA + DDRSS_PI_240_DATA + DDRSS_PI_241_DATA + DDRSS_PI_242_DATA + DDRSS_PI_243_DATA + DDRSS_PI_244_DATA + DDRSS_PI_245_DATA + DDRSS_PI_246_DATA + DDRSS_PI_247_DATA + DDRSS_PI_248_DATA + DDRSS_PI_249_DATA + DDRSS_PI_250_DATA + DDRSS_PI_251_DATA + DDRSS_PI_252_DATA + DDRSS_PI_253_DATA + DDRSS_PI_254_DATA + DDRSS_PI_255_DATA + DDRSS_PI_256_DATA + DDRSS_PI_257_DATA + DDRSS_PI_258_DATA + DDRSS_PI_259_DATA + DDRSS_PI_260_DATA + DDRSS_PI_261_DATA + DDRSS_PI_262_DATA + DDRSS_PI_263_DATA + DDRSS_PI_264_DATA + DDRSS_PI_265_DATA + DDRSS_PI_266_DATA + DDRSS_PI_267_DATA + DDRSS_PI_268_DATA + DDRSS_PI_269_DATA + DDRSS_PI_270_DATA + DDRSS_PI_271_DATA + DDRSS_PI_272_DATA + DDRSS_PI_273_DATA + DDRSS_PI_274_DATA + DDRSS_PI_275_DATA + DDRSS_PI_276_DATA + DDRSS_PI_277_DATA + DDRSS_PI_278_DATA + DDRSS_PI_279_DATA + DDRSS_PI_280_DATA + DDRSS_PI_281_DATA + DDRSS_PI_282_DATA + DDRSS_PI_283_DATA + DDRSS_PI_284_DATA + DDRSS_PI_285_DATA + DDRSS_PI_286_DATA + DDRSS_PI_287_DATA + DDRSS_PI_288_DATA + DDRSS_PI_289_DATA + DDRSS_PI_290_DATA + DDRSS_PI_291_DATA + DDRSS_PI_292_DATA + DDRSS_PI_293_DATA + DDRSS_PI_294_DATA + DDRSS_PI_295_DATA + DDRSS_PI_296_DATA + DDRSS_PI_297_DATA + DDRSS_PI_298_DATA + DDRSS_PI_299_DATA + DDRSS_PI_300_DATA + DDRSS_PI_301_DATA + DDRSS_PI_302_DATA + DDRSS_PI_303_DATA + DDRSS_PI_304_DATA + DDRSS_PI_305_DATA + DDRSS_PI_306_DATA + DDRSS_PI_307_DATA + DDRSS_PI_308_DATA + DDRSS_PI_309_DATA + DDRSS_PI_310_DATA + DDRSS_PI_311_DATA + DDRSS_PI_312_DATA + DDRSS_PI_313_DATA + DDRSS_PI_314_DATA + DDRSS_PI_315_DATA + DDRSS_PI_316_DATA + DDRSS_PI_317_DATA + DDRSS_PI_318_DATA + DDRSS_PI_319_DATA + DDRSS_PI_320_DATA + DDRSS_PI_321_DATA + DDRSS_PI_322_DATA + DDRSS_PI_323_DATA + DDRSS_PI_324_DATA + DDRSS_PI_325_DATA + DDRSS_PI_326_DATA + DDRSS_PI_327_DATA + DDRSS_PI_328_DATA + DDRSS_PI_329_DATA + DDRSS_PI_330_DATA + DDRSS_PI_331_DATA + DDRSS_PI_332_DATA + DDRSS_PI_333_DATA + DDRSS_PI_334_DATA + DDRSS_PI_335_DATA + DDRSS_PI_336_DATA + DDRSS_PI_337_DATA + DDRSS_PI_338_DATA + DDRSS_PI_339_DATA + DDRSS_PI_340_DATA + DDRSS_PI_341_DATA + DDRSS_PI_342_DATA + DDRSS_PI_343_DATA + DDRSS_PI_344_DATA + DDRSS_PI_345_DATA + DDRSS_PI_346_DATA + DDRSS_PI_347_DATA + DDRSS_PI_348_DATA + DDRSS_PI_349_DATA + DDRSS_PI_350_DATA + DDRSS_PI_351_DATA + DDRSS_PI_352_DATA + DDRSS_PI_353_DATA + DDRSS_PI_354_DATA + DDRSS_PI_355_DATA + DDRSS_PI_356_DATA + DDRSS_PI_357_DATA + DDRSS_PI_358_DATA + DDRSS_PI_359_DATA + DDRSS_PI_360_DATA + DDRSS_PI_361_DATA + DDRSS_PI_362_DATA + DDRSS_PI_363_DATA + DDRSS_PI_364_DATA + DDRSS_PI_365_DATA + DDRSS_PI_366_DATA + DDRSS_PI_367_DATA + DDRSS_PI_368_DATA + DDRSS_PI_369_DATA + DDRSS_PI_370_DATA + DDRSS_PI_371_DATA + DDRSS_PI_372_DATA + DDRSS_PI_373_DATA + DDRSS_PI_374_DATA + DDRSS_PI_375_DATA + DDRSS_PI_376_DATA + DDRSS_PI_377_DATA + DDRSS_PI_378_DATA + DDRSS_PI_379_DATA + DDRSS_PI_380_DATA + DDRSS_PI_381_DATA + DDRSS_PI_382_DATA + DDRSS_PI_383_DATA + DDRSS_PI_384_DATA + DDRSS_PI_385_DATA + DDRSS_PI_386_DATA + DDRSS_PI_387_DATA + DDRSS_PI_388_DATA + DDRSS_PI_389_DATA + DDRSS_PI_390_DATA + DDRSS_PI_391_DATA + DDRSS_PI_392_DATA + DDRSS_PI_393_DATA + DDRSS_PI_394_DATA + DDRSS_PI_395_DATA + DDRSS_PI_396_DATA + DDRSS_PI_397_DATA + DDRSS_PI_398_DATA + DDRSS_PI_399_DATA + DDRSS_PI_400_DATA + DDRSS_PI_401_DATA + DDRSS_PI_402_DATA + DDRSS_PI_403_DATA + DDRSS_PI_404_DATA + DDRSS_PI_405_DATA + DDRSS_PI_406_DATA + DDRSS_PI_407_DATA + DDRSS_PI_408_DATA + DDRSS_PI_409_DATA + DDRSS_PI_410_DATA + DDRSS_PI_411_DATA + DDRSS_PI_412_DATA + DDRSS_PI_413_DATA + DDRSS_PI_414_DATA + DDRSS_PI_415_DATA + DDRSS_PI_416_DATA + DDRSS_PI_417_DATA + DDRSS_PI_418_DATA + DDRSS_PI_419_DATA + DDRSS_PI_420_DATA + DDRSS_PI_421_DATA + DDRSS_PI_422_DATA + DDRSS_PI_423_DATA + >; + + ti,phy-data = < + DDRSS_PHY_0_DATA + DDRSS_PHY_1_DATA + DDRSS_PHY_2_DATA + DDRSS_PHY_3_DATA + DDRSS_PHY_4_DATA + DDRSS_PHY_5_DATA + DDRSS_PHY_6_DATA + DDRSS_PHY_7_DATA + DDRSS_PHY_8_DATA + DDRSS_PHY_9_DATA + DDRSS_PHY_10_DATA + DDRSS_PHY_11_DATA + DDRSS_PHY_12_DATA + DDRSS_PHY_13_DATA + DDRSS_PHY_14_DATA + DDRSS_PHY_15_DATA + DDRSS_PHY_16_DATA + DDRSS_PHY_17_DATA + DDRSS_PHY_18_DATA + DDRSS_PHY_19_DATA + DDRSS_PHY_20_DATA + DDRSS_PHY_21_DATA + DDRSS_PHY_22_DATA + DDRSS_PHY_23_DATA + DDRSS_PHY_24_DATA + DDRSS_PHY_25_DATA + DDRSS_PHY_26_DATA + DDRSS_PHY_27_DATA + DDRSS_PHY_28_DATA + DDRSS_PHY_29_DATA + DDRSS_PHY_30_DATA + DDRSS_PHY_31_DATA + DDRSS_PHY_32_DATA + DDRSS_PHY_33_DATA + DDRSS_PHY_34_DATA + DDRSS_PHY_35_DATA + DDRSS_PHY_36_DATA + DDRSS_PHY_37_DATA + DDRSS_PHY_38_DATA + DDRSS_PHY_39_DATA + DDRSS_PHY_40_DATA + DDRSS_PHY_41_DATA + DDRSS_PHY_42_DATA + DDRSS_PHY_43_DATA + DDRSS_PHY_44_DATA + DDRSS_PHY_45_DATA + DDRSS_PHY_46_DATA + DDRSS_PHY_47_DATA + DDRSS_PHY_48_DATA + DDRSS_PHY_49_DATA + DDRSS_PHY_50_DATA + DDRSS_PHY_51_DATA + DDRSS_PHY_52_DATA + DDRSS_PHY_53_DATA + DDRSS_PHY_54_DATA + DDRSS_PHY_55_DATA + DDRSS_PHY_56_DATA + DDRSS_PHY_57_DATA + DDRSS_PHY_58_DATA + DDRSS_PHY_59_DATA + DDRSS_PHY_60_DATA + DDRSS_PHY_61_DATA + DDRSS_PHY_62_DATA + DDRSS_PHY_63_DATA + DDRSS_PHY_64_DATA + DDRSS_PHY_65_DATA + DDRSS_PHY_66_DATA + DDRSS_PHY_67_DATA + DDRSS_PHY_68_DATA + DDRSS_PHY_69_DATA + DDRSS_PHY_70_DATA + DDRSS_PHY_71_DATA + DDRSS_PHY_72_DATA + DDRSS_PHY_73_DATA + DDRSS_PHY_74_DATA + DDRSS_PHY_75_DATA + DDRSS_PHY_76_DATA + DDRSS_PHY_77_DATA + DDRSS_PHY_78_DATA + DDRSS_PHY_79_DATA + DDRSS_PHY_80_DATA + DDRSS_PHY_81_DATA + DDRSS_PHY_82_DATA + DDRSS_PHY_83_DATA + DDRSS_PHY_84_DATA + DDRSS_PHY_85_DATA + DDRSS_PHY_86_DATA + DDRSS_PHY_87_DATA + DDRSS_PHY_88_DATA + DDRSS_PHY_89_DATA + DDRSS_PHY_90_DATA + DDRSS_PHY_91_DATA + DDRSS_PHY_92_DATA + DDRSS_PHY_93_DATA + DDRSS_PHY_94_DATA + DDRSS_PHY_95_DATA + DDRSS_PHY_96_DATA + DDRSS_PHY_97_DATA + DDRSS_PHY_98_DATA + DDRSS_PHY_99_DATA + DDRSS_PHY_100_DATA + DDRSS_PHY_101_DATA + DDRSS_PHY_102_DATA + DDRSS_PHY_103_DATA + DDRSS_PHY_104_DATA + DDRSS_PHY_105_DATA + DDRSS_PHY_106_DATA + DDRSS_PHY_107_DATA + DDRSS_PHY_108_DATA + DDRSS_PHY_109_DATA + DDRSS_PHY_110_DATA + DDRSS_PHY_111_DATA + DDRSS_PHY_112_DATA + DDRSS_PHY_113_DATA + DDRSS_PHY_114_DATA + DDRSS_PHY_115_DATA + DDRSS_PHY_116_DATA + DDRSS_PHY_117_DATA + DDRSS_PHY_118_DATA + DDRSS_PHY_119_DATA + DDRSS_PHY_120_DATA + DDRSS_PHY_121_DATA + DDRSS_PHY_122_DATA + DDRSS_PHY_123_DATA + DDRSS_PHY_124_DATA + DDRSS_PHY_125_DATA + DDRSS_PHY_126_DATA + DDRSS_PHY_127_DATA + DDRSS_PHY_128_DATA + DDRSS_PHY_129_DATA + DDRSS_PHY_130_DATA + DDRSS_PHY_131_DATA + DDRSS_PHY_132_DATA + DDRSS_PHY_133_DATA + DDRSS_PHY_134_DATA + DDRSS_PHY_135_DATA + DDRSS_PHY_136_DATA + DDRSS_PHY_137_DATA + DDRSS_PHY_138_DATA + DDRSS_PHY_139_DATA + DDRSS_PHY_140_DATA + DDRSS_PHY_141_DATA + DDRSS_PHY_142_DATA + DDRSS_PHY_143_DATA + DDRSS_PHY_144_DATA + DDRSS_PHY_145_DATA + DDRSS_PHY_146_DATA + DDRSS_PHY_147_DATA + DDRSS_PHY_148_DATA + DDRSS_PHY_149_DATA + DDRSS_PHY_150_DATA + DDRSS_PHY_151_DATA + DDRSS_PHY_152_DATA + DDRSS_PHY_153_DATA + DDRSS_PHY_154_DATA + DDRSS_PHY_155_DATA + DDRSS_PHY_156_DATA + DDRSS_PHY_157_DATA + DDRSS_PHY_158_DATA + DDRSS_PHY_159_DATA + DDRSS_PHY_160_DATA + DDRSS_PHY_161_DATA + DDRSS_PHY_162_DATA + DDRSS_PHY_163_DATA + DDRSS_PHY_164_DATA + DDRSS_PHY_165_DATA + DDRSS_PHY_166_DATA + DDRSS_PHY_167_DATA + DDRSS_PHY_168_DATA + DDRSS_PHY_169_DATA + DDRSS_PHY_170_DATA + DDRSS_PHY_171_DATA + DDRSS_PHY_172_DATA + DDRSS_PHY_173_DATA + DDRSS_PHY_174_DATA + DDRSS_PHY_175_DATA + DDRSS_PHY_176_DATA + DDRSS_PHY_177_DATA + DDRSS_PHY_178_DATA + DDRSS_PHY_179_DATA + DDRSS_PHY_180_DATA + DDRSS_PHY_181_DATA + DDRSS_PHY_182_DATA + DDRSS_PHY_183_DATA + DDRSS_PHY_184_DATA + DDRSS_PHY_185_DATA + DDRSS_PHY_186_DATA + DDRSS_PHY_187_DATA + DDRSS_PHY_188_DATA + DDRSS_PHY_189_DATA + DDRSS_PHY_190_DATA + DDRSS_PHY_191_DATA + DDRSS_PHY_192_DATA + DDRSS_PHY_193_DATA + DDRSS_PHY_194_DATA + DDRSS_PHY_195_DATA + DDRSS_PHY_196_DATA + DDRSS_PHY_197_DATA + DDRSS_PHY_198_DATA + DDRSS_PHY_199_DATA + DDRSS_PHY_200_DATA + DDRSS_PHY_201_DATA + DDRSS_PHY_202_DATA + DDRSS_PHY_203_DATA + DDRSS_PHY_204_DATA + DDRSS_PHY_205_DATA + DDRSS_PHY_206_DATA + DDRSS_PHY_207_DATA + DDRSS_PHY_208_DATA + DDRSS_PHY_209_DATA + DDRSS_PHY_210_DATA + DDRSS_PHY_211_DATA + DDRSS_PHY_212_DATA + DDRSS_PHY_213_DATA + DDRSS_PHY_214_DATA + DDRSS_PHY_215_DATA + DDRSS_PHY_216_DATA + DDRSS_PHY_217_DATA + DDRSS_PHY_218_DATA + DDRSS_PHY_219_DATA + DDRSS_PHY_220_DATA + DDRSS_PHY_221_DATA + DDRSS_PHY_222_DATA + DDRSS_PHY_223_DATA + DDRSS_PHY_224_DATA + DDRSS_PHY_225_DATA + DDRSS_PHY_226_DATA + DDRSS_PHY_227_DATA + DDRSS_PHY_228_DATA + DDRSS_PHY_229_DATA + DDRSS_PHY_230_DATA + DDRSS_PHY_231_DATA + DDRSS_PHY_232_DATA + DDRSS_PHY_233_DATA + DDRSS_PHY_234_DATA + DDRSS_PHY_235_DATA + DDRSS_PHY_236_DATA + DDRSS_PHY_237_DATA + DDRSS_PHY_238_DATA + DDRSS_PHY_239_DATA + DDRSS_PHY_240_DATA + DDRSS_PHY_241_DATA + DDRSS_PHY_242_DATA + DDRSS_PHY_243_DATA + DDRSS_PHY_244_DATA + DDRSS_PHY_245_DATA + DDRSS_PHY_246_DATA + DDRSS_PHY_247_DATA + DDRSS_PHY_248_DATA + DDRSS_PHY_249_DATA + DDRSS_PHY_250_DATA + DDRSS_PHY_251_DATA + DDRSS_PHY_252_DATA + DDRSS_PHY_253_DATA + DDRSS_PHY_254_DATA + DDRSS_PHY_255_DATA + DDRSS_PHY_256_DATA + DDRSS_PHY_257_DATA + DDRSS_PHY_258_DATA + DDRSS_PHY_259_DATA + DDRSS_PHY_260_DATA + DDRSS_PHY_261_DATA + DDRSS_PHY_262_DATA + DDRSS_PHY_263_DATA + DDRSS_PHY_264_DATA + DDRSS_PHY_265_DATA + DDRSS_PHY_266_DATA + DDRSS_PHY_267_DATA + DDRSS_PHY_268_DATA + DDRSS_PHY_269_DATA + DDRSS_PHY_270_DATA + DDRSS_PHY_271_DATA + DDRSS_PHY_272_DATA + DDRSS_PHY_273_DATA + DDRSS_PHY_274_DATA + DDRSS_PHY_275_DATA + DDRSS_PHY_276_DATA + DDRSS_PHY_277_DATA + DDRSS_PHY_278_DATA + DDRSS_PHY_279_DATA + DDRSS_PHY_280_DATA + DDRSS_PHY_281_DATA + DDRSS_PHY_282_DATA + DDRSS_PHY_283_DATA + DDRSS_PHY_284_DATA + DDRSS_PHY_285_DATA + DDRSS_PHY_286_DATA + DDRSS_PHY_287_DATA + DDRSS_PHY_288_DATA + DDRSS_PHY_289_DATA + DDRSS_PHY_290_DATA + DDRSS_PHY_291_DATA + DDRSS_PHY_292_DATA + DDRSS_PHY_293_DATA + DDRSS_PHY_294_DATA + DDRSS_PHY_295_DATA + DDRSS_PHY_296_DATA + DDRSS_PHY_297_DATA + DDRSS_PHY_298_DATA + DDRSS_PHY_299_DATA + DDRSS_PHY_300_DATA + DDRSS_PHY_301_DATA + DDRSS_PHY_302_DATA + DDRSS_PHY_303_DATA + DDRSS_PHY_304_DATA + DDRSS_PHY_305_DATA + DDRSS_PHY_306_DATA + DDRSS_PHY_307_DATA + DDRSS_PHY_308_DATA + DDRSS_PHY_309_DATA + DDRSS_PHY_310_DATA + DDRSS_PHY_311_DATA + DDRSS_PHY_312_DATA + DDRSS_PHY_313_DATA + DDRSS_PHY_314_DATA + DDRSS_PHY_315_DATA + DDRSS_PHY_316_DATA + DDRSS_PHY_317_DATA + DDRSS_PHY_318_DATA + DDRSS_PHY_319_DATA + DDRSS_PHY_320_DATA + DDRSS_PHY_321_DATA + DDRSS_PHY_322_DATA + DDRSS_PHY_323_DATA + DDRSS_PHY_324_DATA + DDRSS_PHY_325_DATA + DDRSS_PHY_326_DATA + DDRSS_PHY_327_DATA + DDRSS_PHY_328_DATA + DDRSS_PHY_329_DATA + DDRSS_PHY_330_DATA + DDRSS_PHY_331_DATA + DDRSS_PHY_332_DATA + DDRSS_PHY_333_DATA + DDRSS_PHY_334_DATA + DDRSS_PHY_335_DATA + DDRSS_PHY_336_DATA + DDRSS_PHY_337_DATA + DDRSS_PHY_338_DATA + DDRSS_PHY_339_DATA + DDRSS_PHY_340_DATA + DDRSS_PHY_341_DATA + DDRSS_PHY_342_DATA + DDRSS_PHY_343_DATA + DDRSS_PHY_344_DATA + DDRSS_PHY_345_DATA + DDRSS_PHY_346_DATA + DDRSS_PHY_347_DATA + DDRSS_PHY_348_DATA + DDRSS_PHY_349_DATA + DDRSS_PHY_350_DATA + DDRSS_PHY_351_DATA + DDRSS_PHY_352_DATA + DDRSS_PHY_353_DATA + DDRSS_PHY_354_DATA + DDRSS_PHY_355_DATA + DDRSS_PHY_356_DATA + DDRSS_PHY_357_DATA + DDRSS_PHY_358_DATA + DDRSS_PHY_359_DATA + DDRSS_PHY_360_DATA + DDRSS_PHY_361_DATA + DDRSS_PHY_362_DATA + DDRSS_PHY_363_DATA + DDRSS_PHY_364_DATA + DDRSS_PHY_365_DATA + DDRSS_PHY_366_DATA + DDRSS_PHY_367_DATA + DDRSS_PHY_368_DATA + DDRSS_PHY_369_DATA + DDRSS_PHY_370_DATA + DDRSS_PHY_371_DATA + DDRSS_PHY_372_DATA + DDRSS_PHY_373_DATA + DDRSS_PHY_374_DATA + DDRSS_PHY_375_DATA + DDRSS_PHY_376_DATA + DDRSS_PHY_377_DATA + DDRSS_PHY_378_DATA + DDRSS_PHY_379_DATA + DDRSS_PHY_380_DATA + DDRSS_PHY_381_DATA + DDRSS_PHY_382_DATA + DDRSS_PHY_383_DATA + DDRSS_PHY_384_DATA + DDRSS_PHY_385_DATA + DDRSS_PHY_386_DATA + DDRSS_PHY_387_DATA + DDRSS_PHY_388_DATA + DDRSS_PHY_389_DATA + DDRSS_PHY_390_DATA + DDRSS_PHY_391_DATA + DDRSS_PHY_392_DATA + DDRSS_PHY_393_DATA + DDRSS_PHY_394_DATA + DDRSS_PHY_395_DATA + DDRSS_PHY_396_DATA + DDRSS_PHY_397_DATA + DDRSS_PHY_398_DATA + DDRSS_PHY_399_DATA + DDRSS_PHY_400_DATA + DDRSS_PHY_401_DATA + DDRSS_PHY_402_DATA + DDRSS_PHY_403_DATA + DDRSS_PHY_404_DATA + DDRSS_PHY_405_DATA + DDRSS_PHY_406_DATA + DDRSS_PHY_407_DATA + DDRSS_PHY_408_DATA + DDRSS_PHY_409_DATA + DDRSS_PHY_410_DATA + DDRSS_PHY_411_DATA + DDRSS_PHY_412_DATA + DDRSS_PHY_413_DATA + DDRSS_PHY_414_DATA + DDRSS_PHY_415_DATA + DDRSS_PHY_416_DATA + DDRSS_PHY_417_DATA + DDRSS_PHY_418_DATA + DDRSS_PHY_419_DATA + DDRSS_PHY_420_DATA + DDRSS_PHY_421_DATA + DDRSS_PHY_422_DATA + DDRSS_PHY_423_DATA + DDRSS_PHY_424_DATA + DDRSS_PHY_425_DATA + DDRSS_PHY_426_DATA + DDRSS_PHY_427_DATA + DDRSS_PHY_428_DATA + DDRSS_PHY_429_DATA + DDRSS_PHY_430_DATA + DDRSS_PHY_431_DATA + DDRSS_PHY_432_DATA + DDRSS_PHY_433_DATA + DDRSS_PHY_434_DATA + DDRSS_PHY_435_DATA + DDRSS_PHY_436_DATA + DDRSS_PHY_437_DATA + DDRSS_PHY_438_DATA + DDRSS_PHY_439_DATA + DDRSS_PHY_440_DATA + DDRSS_PHY_441_DATA + DDRSS_PHY_442_DATA + DDRSS_PHY_443_DATA + DDRSS_PHY_444_DATA + DDRSS_PHY_445_DATA + DDRSS_PHY_446_DATA + DDRSS_PHY_447_DATA + DDRSS_PHY_448_DATA + DDRSS_PHY_449_DATA + DDRSS_PHY_450_DATA + DDRSS_PHY_451_DATA + DDRSS_PHY_452_DATA + DDRSS_PHY_453_DATA + DDRSS_PHY_454_DATA + DDRSS_PHY_455_DATA + DDRSS_PHY_456_DATA + DDRSS_PHY_457_DATA + DDRSS_PHY_458_DATA + DDRSS_PHY_459_DATA + DDRSS_PHY_460_DATA + DDRSS_PHY_461_DATA + DDRSS_PHY_462_DATA + DDRSS_PHY_463_DATA + DDRSS_PHY_464_DATA + DDRSS_PHY_465_DATA + DDRSS_PHY_466_DATA + DDRSS_PHY_467_DATA + DDRSS_PHY_468_DATA + DDRSS_PHY_469_DATA + DDRSS_PHY_470_DATA + DDRSS_PHY_471_DATA + DDRSS_PHY_472_DATA + DDRSS_PHY_473_DATA + DDRSS_PHY_474_DATA + DDRSS_PHY_475_DATA + DDRSS_PHY_476_DATA + DDRSS_PHY_477_DATA + DDRSS_PHY_478_DATA + DDRSS_PHY_479_DATA + DDRSS_PHY_480_DATA + DDRSS_PHY_481_DATA + DDRSS_PHY_482_DATA + DDRSS_PHY_483_DATA + DDRSS_PHY_484_DATA + DDRSS_PHY_485_DATA + DDRSS_PHY_486_DATA + DDRSS_PHY_487_DATA + DDRSS_PHY_488_DATA + DDRSS_PHY_489_DATA + DDRSS_PHY_490_DATA + DDRSS_PHY_491_DATA + DDRSS_PHY_492_DATA + DDRSS_PHY_493_DATA + DDRSS_PHY_494_DATA + DDRSS_PHY_495_DATA + DDRSS_PHY_496_DATA + DDRSS_PHY_497_DATA + DDRSS_PHY_498_DATA + DDRSS_PHY_499_DATA + DDRSS_PHY_500_DATA + DDRSS_PHY_501_DATA + DDRSS_PHY_502_DATA + DDRSS_PHY_503_DATA + DDRSS_PHY_504_DATA + DDRSS_PHY_505_DATA + DDRSS_PHY_506_DATA + DDRSS_PHY_507_DATA + DDRSS_PHY_508_DATA + DDRSS_PHY_509_DATA + DDRSS_PHY_510_DATA + DDRSS_PHY_511_DATA + DDRSS_PHY_512_DATA + DDRSS_PHY_513_DATA + DDRSS_PHY_514_DATA + DDRSS_PHY_515_DATA + DDRSS_PHY_516_DATA + DDRSS_PHY_517_DATA + DDRSS_PHY_518_DATA + DDRSS_PHY_519_DATA + DDRSS_PHY_520_DATA + DDRSS_PHY_521_DATA + DDRSS_PHY_522_DATA + DDRSS_PHY_523_DATA + DDRSS_PHY_524_DATA + DDRSS_PHY_525_DATA + DDRSS_PHY_526_DATA + DDRSS_PHY_527_DATA + DDRSS_PHY_528_DATA + DDRSS_PHY_529_DATA + DDRSS_PHY_530_DATA + DDRSS_PHY_531_DATA + DDRSS_PHY_532_DATA + DDRSS_PHY_533_DATA + DDRSS_PHY_534_DATA + DDRSS_PHY_535_DATA + DDRSS_PHY_536_DATA + DDRSS_PHY_537_DATA + DDRSS_PHY_538_DATA + DDRSS_PHY_539_DATA + DDRSS_PHY_540_DATA + DDRSS_PHY_541_DATA + DDRSS_PHY_542_DATA + DDRSS_PHY_543_DATA + DDRSS_PHY_544_DATA + DDRSS_PHY_545_DATA + DDRSS_PHY_546_DATA + DDRSS_PHY_547_DATA + DDRSS_PHY_548_DATA + DDRSS_PHY_549_DATA + DDRSS_PHY_550_DATA + DDRSS_PHY_551_DATA + DDRSS_PHY_552_DATA + DDRSS_PHY_553_DATA + DDRSS_PHY_554_DATA + DDRSS_PHY_555_DATA + DDRSS_PHY_556_DATA + DDRSS_PHY_557_DATA + DDRSS_PHY_558_DATA + DDRSS_PHY_559_DATA + DDRSS_PHY_560_DATA + DDRSS_PHY_561_DATA + DDRSS_PHY_562_DATA + DDRSS_PHY_563_DATA + DDRSS_PHY_564_DATA + DDRSS_PHY_565_DATA + DDRSS_PHY_566_DATA + DDRSS_PHY_567_DATA + DDRSS_PHY_568_DATA + DDRSS_PHY_569_DATA + DDRSS_PHY_570_DATA + DDRSS_PHY_571_DATA + DDRSS_PHY_572_DATA + DDRSS_PHY_573_DATA + DDRSS_PHY_574_DATA + DDRSS_PHY_575_DATA + DDRSS_PHY_576_DATA + DDRSS_PHY_577_DATA + DDRSS_PHY_578_DATA + DDRSS_PHY_579_DATA + DDRSS_PHY_580_DATA + DDRSS_PHY_581_DATA + DDRSS_PHY_582_DATA + DDRSS_PHY_583_DATA + DDRSS_PHY_584_DATA + DDRSS_PHY_585_DATA + DDRSS_PHY_586_DATA + DDRSS_PHY_587_DATA + DDRSS_PHY_588_DATA + DDRSS_PHY_589_DATA + DDRSS_PHY_590_DATA + DDRSS_PHY_591_DATA + DDRSS_PHY_592_DATA + DDRSS_PHY_593_DATA + DDRSS_PHY_594_DATA + DDRSS_PHY_595_DATA + DDRSS_PHY_596_DATA + DDRSS_PHY_597_DATA + DDRSS_PHY_598_DATA + DDRSS_PHY_599_DATA + DDRSS_PHY_600_DATA + DDRSS_PHY_601_DATA + DDRSS_PHY_602_DATA + DDRSS_PHY_603_DATA + DDRSS_PHY_604_DATA + DDRSS_PHY_605_DATA + DDRSS_PHY_606_DATA + DDRSS_PHY_607_DATA + DDRSS_PHY_608_DATA + DDRSS_PHY_609_DATA + DDRSS_PHY_610_DATA + DDRSS_PHY_611_DATA + DDRSS_PHY_612_DATA + DDRSS_PHY_613_DATA + DDRSS_PHY_614_DATA + DDRSS_PHY_615_DATA + DDRSS_PHY_616_DATA + DDRSS_PHY_617_DATA + DDRSS_PHY_618_DATA + DDRSS_PHY_619_DATA + DDRSS_PHY_620_DATA + DDRSS_PHY_621_DATA + DDRSS_PHY_622_DATA + DDRSS_PHY_623_DATA + DDRSS_PHY_624_DATA + DDRSS_PHY_625_DATA + DDRSS_PHY_626_DATA + DDRSS_PHY_627_DATA + DDRSS_PHY_628_DATA + DDRSS_PHY_629_DATA + DDRSS_PHY_630_DATA + DDRSS_PHY_631_DATA + DDRSS_PHY_632_DATA + DDRSS_PHY_633_DATA + DDRSS_PHY_634_DATA + DDRSS_PHY_635_DATA + DDRSS_PHY_636_DATA + DDRSS_PHY_637_DATA + DDRSS_PHY_638_DATA + DDRSS_PHY_639_DATA + DDRSS_PHY_640_DATA + DDRSS_PHY_641_DATA + DDRSS_PHY_642_DATA + DDRSS_PHY_643_DATA + DDRSS_PHY_644_DATA + DDRSS_PHY_645_DATA + DDRSS_PHY_646_DATA + DDRSS_PHY_647_DATA + DDRSS_PHY_648_DATA + DDRSS_PHY_649_DATA + DDRSS_PHY_650_DATA + DDRSS_PHY_651_DATA + DDRSS_PHY_652_DATA + DDRSS_PHY_653_DATA + DDRSS_PHY_654_DATA + DDRSS_PHY_655_DATA + DDRSS_PHY_656_DATA + DDRSS_PHY_657_DATA + DDRSS_PHY_658_DATA + DDRSS_PHY_659_DATA + DDRSS_PHY_660_DATA + DDRSS_PHY_661_DATA + DDRSS_PHY_662_DATA + DDRSS_PHY_663_DATA + DDRSS_PHY_664_DATA + DDRSS_PHY_665_DATA + DDRSS_PHY_666_DATA + DDRSS_PHY_667_DATA + DDRSS_PHY_668_DATA + DDRSS_PHY_669_DATA + DDRSS_PHY_670_DATA + DDRSS_PHY_671_DATA + DDRSS_PHY_672_DATA + DDRSS_PHY_673_DATA + DDRSS_PHY_674_DATA + DDRSS_PHY_675_DATA + DDRSS_PHY_676_DATA + DDRSS_PHY_677_DATA + DDRSS_PHY_678_DATA + DDRSS_PHY_679_DATA + DDRSS_PHY_680_DATA + DDRSS_PHY_681_DATA + DDRSS_PHY_682_DATA + DDRSS_PHY_683_DATA + DDRSS_PHY_684_DATA + DDRSS_PHY_685_DATA + DDRSS_PHY_686_DATA + DDRSS_PHY_687_DATA + DDRSS_PHY_688_DATA + DDRSS_PHY_689_DATA + DDRSS_PHY_690_DATA + DDRSS_PHY_691_DATA + DDRSS_PHY_692_DATA + DDRSS_PHY_693_DATA + DDRSS_PHY_694_DATA + DDRSS_PHY_695_DATA + DDRSS_PHY_696_DATA + DDRSS_PHY_697_DATA + DDRSS_PHY_698_DATA + DDRSS_PHY_699_DATA + DDRSS_PHY_700_DATA + DDRSS_PHY_701_DATA + DDRSS_PHY_702_DATA + DDRSS_PHY_703_DATA + DDRSS_PHY_704_DATA + DDRSS_PHY_705_DATA + DDRSS_PHY_706_DATA + DDRSS_PHY_707_DATA + DDRSS_PHY_708_DATA + DDRSS_PHY_709_DATA + DDRSS_PHY_710_DATA + DDRSS_PHY_711_DATA + DDRSS_PHY_712_DATA + DDRSS_PHY_713_DATA + DDRSS_PHY_714_DATA + DDRSS_PHY_715_DATA + DDRSS_PHY_716_DATA + DDRSS_PHY_717_DATA + DDRSS_PHY_718_DATA + DDRSS_PHY_719_DATA + DDRSS_PHY_720_DATA + DDRSS_PHY_721_DATA + DDRSS_PHY_722_DATA + DDRSS_PHY_723_DATA + DDRSS_PHY_724_DATA + DDRSS_PHY_725_DATA + DDRSS_PHY_726_DATA + DDRSS_PHY_727_DATA + DDRSS_PHY_728_DATA + DDRSS_PHY_729_DATA + DDRSS_PHY_730_DATA + DDRSS_PHY_731_DATA + DDRSS_PHY_732_DATA + DDRSS_PHY_733_DATA + DDRSS_PHY_734_DATA + DDRSS_PHY_735_DATA + DDRSS_PHY_736_DATA + DDRSS_PHY_737_DATA + DDRSS_PHY_738_DATA + DDRSS_PHY_739_DATA + DDRSS_PHY_740_DATA + DDRSS_PHY_741_DATA + DDRSS_PHY_742_DATA + DDRSS_PHY_743_DATA + DDRSS_PHY_744_DATA + DDRSS_PHY_745_DATA + DDRSS_PHY_746_DATA + DDRSS_PHY_747_DATA + DDRSS_PHY_748_DATA + DDRSS_PHY_749_DATA + DDRSS_PHY_750_DATA + DDRSS_PHY_751_DATA + DDRSS_PHY_752_DATA + DDRSS_PHY_753_DATA + DDRSS_PHY_754_DATA + DDRSS_PHY_755_DATA + DDRSS_PHY_756_DATA + DDRSS_PHY_757_DATA + DDRSS_PHY_758_DATA + DDRSS_PHY_759_DATA + DDRSS_PHY_760_DATA + DDRSS_PHY_761_DATA + DDRSS_PHY_762_DATA + DDRSS_PHY_763_DATA + DDRSS_PHY_764_DATA + DDRSS_PHY_765_DATA + DDRSS_PHY_766_DATA + DDRSS_PHY_767_DATA + DDRSS_PHY_768_DATA + DDRSS_PHY_769_DATA + DDRSS_PHY_770_DATA + DDRSS_PHY_771_DATA + DDRSS_PHY_772_DATA + DDRSS_PHY_773_DATA + DDRSS_PHY_774_DATA + DDRSS_PHY_775_DATA + DDRSS_PHY_776_DATA + DDRSS_PHY_777_DATA + DDRSS_PHY_778_DATA + DDRSS_PHY_779_DATA + DDRSS_PHY_780_DATA + DDRSS_PHY_781_DATA + DDRSS_PHY_782_DATA + DDRSS_PHY_783_DATA + DDRSS_PHY_784_DATA + DDRSS_PHY_785_DATA + DDRSS_PHY_786_DATA + DDRSS_PHY_787_DATA + DDRSS_PHY_788_DATA + DDRSS_PHY_789_DATA + DDRSS_PHY_790_DATA + DDRSS_PHY_791_DATA + DDRSS_PHY_792_DATA + DDRSS_PHY_793_DATA + DDRSS_PHY_794_DATA + DDRSS_PHY_795_DATA + DDRSS_PHY_796_DATA + DDRSS_PHY_797_DATA + DDRSS_PHY_798_DATA + DDRSS_PHY_799_DATA + DDRSS_PHY_800_DATA + DDRSS_PHY_801_DATA + DDRSS_PHY_802_DATA + DDRSS_PHY_803_DATA + DDRSS_PHY_804_DATA + DDRSS_PHY_805_DATA + DDRSS_PHY_806_DATA + DDRSS_PHY_807_DATA + DDRSS_PHY_808_DATA + DDRSS_PHY_809_DATA + DDRSS_PHY_810_DATA + DDRSS_PHY_811_DATA + DDRSS_PHY_812_DATA + DDRSS_PHY_813_DATA + DDRSS_PHY_814_DATA + DDRSS_PHY_815_DATA + DDRSS_PHY_816_DATA + DDRSS_PHY_817_DATA + DDRSS_PHY_818_DATA + DDRSS_PHY_819_DATA + DDRSS_PHY_820_DATA + DDRSS_PHY_821_DATA + DDRSS_PHY_822_DATA + DDRSS_PHY_823_DATA + DDRSS_PHY_824_DATA + DDRSS_PHY_825_DATA + DDRSS_PHY_826_DATA + DDRSS_PHY_827_DATA + DDRSS_PHY_828_DATA + DDRSS_PHY_829_DATA + DDRSS_PHY_830_DATA + DDRSS_PHY_831_DATA + DDRSS_PHY_832_DATA + DDRSS_PHY_833_DATA + DDRSS_PHY_834_DATA + DDRSS_PHY_835_DATA + DDRSS_PHY_836_DATA + DDRSS_PHY_837_DATA + DDRSS_PHY_838_DATA + DDRSS_PHY_839_DATA + DDRSS_PHY_840_DATA + DDRSS_PHY_841_DATA + DDRSS_PHY_842_DATA + DDRSS_PHY_843_DATA + DDRSS_PHY_844_DATA + DDRSS_PHY_845_DATA + DDRSS_PHY_846_DATA + DDRSS_PHY_847_DATA + DDRSS_PHY_848_DATA + DDRSS_PHY_849_DATA + DDRSS_PHY_850_DATA + DDRSS_PHY_851_DATA + DDRSS_PHY_852_DATA + DDRSS_PHY_853_DATA + DDRSS_PHY_854_DATA + DDRSS_PHY_855_DATA + DDRSS_PHY_856_DATA + DDRSS_PHY_857_DATA + DDRSS_PHY_858_DATA + DDRSS_PHY_859_DATA + DDRSS_PHY_860_DATA + DDRSS_PHY_861_DATA + DDRSS_PHY_862_DATA + DDRSS_PHY_863_DATA + DDRSS_PHY_864_DATA + DDRSS_PHY_865_DATA + DDRSS_PHY_866_DATA + DDRSS_PHY_867_DATA + DDRSS_PHY_868_DATA + DDRSS_PHY_869_DATA + DDRSS_PHY_870_DATA + DDRSS_PHY_871_DATA + DDRSS_PHY_872_DATA + DDRSS_PHY_873_DATA + DDRSS_PHY_874_DATA + DDRSS_PHY_875_DATA + DDRSS_PHY_876_DATA + DDRSS_PHY_877_DATA + DDRSS_PHY_878_DATA + DDRSS_PHY_879_DATA + DDRSS_PHY_880_DATA + DDRSS_PHY_881_DATA + DDRSS_PHY_882_DATA + DDRSS_PHY_883_DATA + DDRSS_PHY_884_DATA + DDRSS_PHY_885_DATA + DDRSS_PHY_886_DATA + DDRSS_PHY_887_DATA + DDRSS_PHY_888_DATA + DDRSS_PHY_889_DATA + DDRSS_PHY_890_DATA + DDRSS_PHY_891_DATA + DDRSS_PHY_892_DATA + DDRSS_PHY_893_DATA + DDRSS_PHY_894_DATA + DDRSS_PHY_895_DATA + DDRSS_PHY_896_DATA + DDRSS_PHY_897_DATA + DDRSS_PHY_898_DATA + DDRSS_PHY_899_DATA + DDRSS_PHY_900_DATA + DDRSS_PHY_901_DATA + DDRSS_PHY_902_DATA + DDRSS_PHY_903_DATA + DDRSS_PHY_904_DATA + DDRSS_PHY_905_DATA + DDRSS_PHY_906_DATA + DDRSS_PHY_907_DATA + DDRSS_PHY_908_DATA + DDRSS_PHY_909_DATA + DDRSS_PHY_910_DATA + DDRSS_PHY_911_DATA + DDRSS_PHY_912_DATA + DDRSS_PHY_913_DATA + DDRSS_PHY_914_DATA + DDRSS_PHY_915_DATA + DDRSS_PHY_916_DATA + DDRSS_PHY_917_DATA + DDRSS_PHY_918_DATA + DDRSS_PHY_919_DATA + DDRSS_PHY_920_DATA + DDRSS_PHY_921_DATA + DDRSS_PHY_922_DATA + DDRSS_PHY_923_DATA + DDRSS_PHY_924_DATA + DDRSS_PHY_925_DATA + DDRSS_PHY_926_DATA + DDRSS_PHY_927_DATA + DDRSS_PHY_928_DATA + DDRSS_PHY_929_DATA + DDRSS_PHY_930_DATA + DDRSS_PHY_931_DATA + DDRSS_PHY_932_DATA + DDRSS_PHY_933_DATA + DDRSS_PHY_934_DATA + DDRSS_PHY_935_DATA + DDRSS_PHY_936_DATA + DDRSS_PHY_937_DATA + DDRSS_PHY_938_DATA + DDRSS_PHY_939_DATA + DDRSS_PHY_940_DATA + DDRSS_PHY_941_DATA + DDRSS_PHY_942_DATA + DDRSS_PHY_943_DATA + DDRSS_PHY_944_DATA + DDRSS_PHY_945_DATA + DDRSS_PHY_946_DATA + DDRSS_PHY_947_DATA + DDRSS_PHY_948_DATA + DDRSS_PHY_949_DATA + DDRSS_PHY_950_DATA + DDRSS_PHY_951_DATA + DDRSS_PHY_952_DATA + DDRSS_PHY_953_DATA + DDRSS_PHY_954_DATA + DDRSS_PHY_955_DATA + DDRSS_PHY_956_DATA + DDRSS_PHY_957_DATA + DDRSS_PHY_958_DATA + DDRSS_PHY_959_DATA + DDRSS_PHY_960_DATA + DDRSS_PHY_961_DATA + DDRSS_PHY_962_DATA + DDRSS_PHY_963_DATA + DDRSS_PHY_964_DATA + DDRSS_PHY_965_DATA + DDRSS_PHY_966_DATA + DDRSS_PHY_967_DATA + DDRSS_PHY_968_DATA + DDRSS_PHY_969_DATA + DDRSS_PHY_970_DATA + DDRSS_PHY_971_DATA + DDRSS_PHY_972_DATA + DDRSS_PHY_973_DATA + DDRSS_PHY_974_DATA + DDRSS_PHY_975_DATA + DDRSS_PHY_976_DATA + DDRSS_PHY_977_DATA + DDRSS_PHY_978_DATA + DDRSS_PHY_979_DATA + DDRSS_PHY_980_DATA + DDRSS_PHY_981_DATA + DDRSS_PHY_982_DATA + DDRSS_PHY_983_DATA + DDRSS_PHY_984_DATA + DDRSS_PHY_985_DATA + DDRSS_PHY_986_DATA + DDRSS_PHY_987_DATA + DDRSS_PHY_988_DATA + DDRSS_PHY_989_DATA + DDRSS_PHY_990_DATA + DDRSS_PHY_991_DATA + DDRSS_PHY_992_DATA + DDRSS_PHY_993_DATA + DDRSS_PHY_994_DATA + DDRSS_PHY_995_DATA + DDRSS_PHY_996_DATA + DDRSS_PHY_997_DATA + DDRSS_PHY_998_DATA + DDRSS_PHY_999_DATA + DDRSS_PHY_1000_DATA + DDRSS_PHY_1001_DATA + DDRSS_PHY_1002_DATA + DDRSS_PHY_1003_DATA + DDRSS_PHY_1004_DATA + DDRSS_PHY_1005_DATA + DDRSS_PHY_1006_DATA + DDRSS_PHY_1007_DATA + DDRSS_PHY_1008_DATA + DDRSS_PHY_1009_DATA + DDRSS_PHY_1010_DATA + DDRSS_PHY_1011_DATA + DDRSS_PHY_1012_DATA + DDRSS_PHY_1013_DATA + DDRSS_PHY_1014_DATA + DDRSS_PHY_1015_DATA + DDRSS_PHY_1016_DATA + DDRSS_PHY_1017_DATA + DDRSS_PHY_1018_DATA + DDRSS_PHY_1019_DATA + DDRSS_PHY_1020_DATA + DDRSS_PHY_1021_DATA + DDRSS_PHY_1022_DATA + DDRSS_PHY_1023_DATA + DDRSS_PHY_1024_DATA + DDRSS_PHY_1025_DATA + DDRSS_PHY_1026_DATA + DDRSS_PHY_1027_DATA + DDRSS_PHY_1028_DATA + DDRSS_PHY_1029_DATA + DDRSS_PHY_1030_DATA + DDRSS_PHY_1031_DATA + DDRSS_PHY_1032_DATA + DDRSS_PHY_1033_DATA + DDRSS_PHY_1034_DATA + DDRSS_PHY_1035_DATA + DDRSS_PHY_1036_DATA + DDRSS_PHY_1037_DATA + DDRSS_PHY_1038_DATA + DDRSS_PHY_1039_DATA + DDRSS_PHY_1040_DATA + DDRSS_PHY_1041_DATA + DDRSS_PHY_1042_DATA + DDRSS_PHY_1043_DATA + DDRSS_PHY_1044_DATA + DDRSS_PHY_1045_DATA + DDRSS_PHY_1046_DATA + DDRSS_PHY_1047_DATA + DDRSS_PHY_1048_DATA + DDRSS_PHY_1049_DATA + DDRSS_PHY_1050_DATA + DDRSS_PHY_1051_DATA + DDRSS_PHY_1052_DATA + DDRSS_PHY_1053_DATA + DDRSS_PHY_1054_DATA + DDRSS_PHY_1055_DATA + DDRSS_PHY_1056_DATA + DDRSS_PHY_1057_DATA + DDRSS_PHY_1058_DATA + DDRSS_PHY_1059_DATA + DDRSS_PHY_1060_DATA + DDRSS_PHY_1061_DATA + DDRSS_PHY_1062_DATA + DDRSS_PHY_1063_DATA + DDRSS_PHY_1064_DATA + DDRSS_PHY_1065_DATA + DDRSS_PHY_1066_DATA + DDRSS_PHY_1067_DATA + DDRSS_PHY_1068_DATA + DDRSS_PHY_1069_DATA + DDRSS_PHY_1070_DATA + DDRSS_PHY_1071_DATA + DDRSS_PHY_1072_DATA + DDRSS_PHY_1073_DATA + DDRSS_PHY_1074_DATA + DDRSS_PHY_1075_DATA + DDRSS_PHY_1076_DATA + DDRSS_PHY_1077_DATA + DDRSS_PHY_1078_DATA + DDRSS_PHY_1079_DATA + DDRSS_PHY_1080_DATA + DDRSS_PHY_1081_DATA + DDRSS_PHY_1082_DATA + DDRSS_PHY_1083_DATA + DDRSS_PHY_1084_DATA + DDRSS_PHY_1085_DATA + DDRSS_PHY_1086_DATA + DDRSS_PHY_1087_DATA + DDRSS_PHY_1088_DATA + DDRSS_PHY_1089_DATA + DDRSS_PHY_1090_DATA + DDRSS_PHY_1091_DATA + DDRSS_PHY_1092_DATA + DDRSS_PHY_1093_DATA + DDRSS_PHY_1094_DATA + DDRSS_PHY_1095_DATA + DDRSS_PHY_1096_DATA + DDRSS_PHY_1097_DATA + DDRSS_PHY_1098_DATA + DDRSS_PHY_1099_DATA + DDRSS_PHY_1100_DATA + DDRSS_PHY_1101_DATA + DDRSS_PHY_1102_DATA + DDRSS_PHY_1103_DATA + DDRSS_PHY_1104_DATA + DDRSS_PHY_1105_DATA + DDRSS_PHY_1106_DATA + DDRSS_PHY_1107_DATA + DDRSS_PHY_1108_DATA + DDRSS_PHY_1109_DATA + DDRSS_PHY_1110_DATA + DDRSS_PHY_1111_DATA + DDRSS_PHY_1112_DATA + DDRSS_PHY_1113_DATA + DDRSS_PHY_1114_DATA + DDRSS_PHY_1115_DATA + DDRSS_PHY_1116_DATA + DDRSS_PHY_1117_DATA + DDRSS_PHY_1118_DATA + DDRSS_PHY_1119_DATA + DDRSS_PHY_1120_DATA + DDRSS_PHY_1121_DATA + DDRSS_PHY_1122_DATA + DDRSS_PHY_1123_DATA + DDRSS_PHY_1124_DATA + DDRSS_PHY_1125_DATA + DDRSS_PHY_1126_DATA + DDRSS_PHY_1127_DATA + DDRSS_PHY_1128_DATA + DDRSS_PHY_1129_DATA + DDRSS_PHY_1130_DATA + DDRSS_PHY_1131_DATA + DDRSS_PHY_1132_DATA + DDRSS_PHY_1133_DATA + DDRSS_PHY_1134_DATA + DDRSS_PHY_1135_DATA + DDRSS_PHY_1136_DATA + DDRSS_PHY_1137_DATA + DDRSS_PHY_1138_DATA + DDRSS_PHY_1139_DATA + DDRSS_PHY_1140_DATA + DDRSS_PHY_1141_DATA + DDRSS_PHY_1142_DATA + DDRSS_PHY_1143_DATA + DDRSS_PHY_1144_DATA + DDRSS_PHY_1145_DATA + DDRSS_PHY_1146_DATA + DDRSS_PHY_1147_DATA + DDRSS_PHY_1148_DATA + DDRSS_PHY_1149_DATA + DDRSS_PHY_1150_DATA + DDRSS_PHY_1151_DATA + DDRSS_PHY_1152_DATA + DDRSS_PHY_1153_DATA + DDRSS_PHY_1154_DATA + DDRSS_PHY_1155_DATA + DDRSS_PHY_1156_DATA + DDRSS_PHY_1157_DATA + DDRSS_PHY_1158_DATA + DDRSS_PHY_1159_DATA + DDRSS_PHY_1160_DATA + DDRSS_PHY_1161_DATA + DDRSS_PHY_1162_DATA + DDRSS_PHY_1163_DATA + DDRSS_PHY_1164_DATA + DDRSS_PHY_1165_DATA + DDRSS_PHY_1166_DATA + DDRSS_PHY_1167_DATA + DDRSS_PHY_1168_DATA + DDRSS_PHY_1169_DATA + DDRSS_PHY_1170_DATA + DDRSS_PHY_1171_DATA + DDRSS_PHY_1172_DATA + DDRSS_PHY_1173_DATA + DDRSS_PHY_1174_DATA + DDRSS_PHY_1175_DATA + DDRSS_PHY_1176_DATA + DDRSS_PHY_1177_DATA + DDRSS_PHY_1178_DATA + DDRSS_PHY_1179_DATA + DDRSS_PHY_1180_DATA + DDRSS_PHY_1181_DATA + DDRSS_PHY_1182_DATA + DDRSS_PHY_1183_DATA + DDRSS_PHY_1184_DATA + DDRSS_PHY_1185_DATA + DDRSS_PHY_1186_DATA + DDRSS_PHY_1187_DATA + DDRSS_PHY_1188_DATA + DDRSS_PHY_1189_DATA + DDRSS_PHY_1190_DATA + DDRSS_PHY_1191_DATA + DDRSS_PHY_1192_DATA + DDRSS_PHY_1193_DATA + DDRSS_PHY_1194_DATA + DDRSS_PHY_1195_DATA + DDRSS_PHY_1196_DATA + DDRSS_PHY_1197_DATA + DDRSS_PHY_1198_DATA + DDRSS_PHY_1199_DATA + DDRSS_PHY_1200_DATA + DDRSS_PHY_1201_DATA + DDRSS_PHY_1202_DATA + DDRSS_PHY_1203_DATA + DDRSS_PHY_1204_DATA + DDRSS_PHY_1205_DATA + DDRSS_PHY_1206_DATA + DDRSS_PHY_1207_DATA + DDRSS_PHY_1208_DATA + DDRSS_PHY_1209_DATA + DDRSS_PHY_1210_DATA + DDRSS_PHY_1211_DATA + DDRSS_PHY_1212_DATA + DDRSS_PHY_1213_DATA + DDRSS_PHY_1214_DATA + DDRSS_PHY_1215_DATA + DDRSS_PHY_1216_DATA + DDRSS_PHY_1217_DATA + DDRSS_PHY_1218_DATA + DDRSS_PHY_1219_DATA + DDRSS_PHY_1220_DATA + DDRSS_PHY_1221_DATA + DDRSS_PHY_1222_DATA + DDRSS_PHY_1223_DATA + DDRSS_PHY_1224_DATA + DDRSS_PHY_1225_DATA + DDRSS_PHY_1226_DATA + DDRSS_PHY_1227_DATA + DDRSS_PHY_1228_DATA + DDRSS_PHY_1229_DATA + DDRSS_PHY_1230_DATA + DDRSS_PHY_1231_DATA + DDRSS_PHY_1232_DATA + DDRSS_PHY_1233_DATA + DDRSS_PHY_1234_DATA + DDRSS_PHY_1235_DATA + DDRSS_PHY_1236_DATA + DDRSS_PHY_1237_DATA + DDRSS_PHY_1238_DATA + DDRSS_PHY_1239_DATA + DDRSS_PHY_1240_DATA + DDRSS_PHY_1241_DATA + DDRSS_PHY_1242_DATA + DDRSS_PHY_1243_DATA + DDRSS_PHY_1244_DATA + DDRSS_PHY_1245_DATA + DDRSS_PHY_1246_DATA + DDRSS_PHY_1247_DATA + DDRSS_PHY_1248_DATA + DDRSS_PHY_1249_DATA + DDRSS_PHY_1250_DATA + DDRSS_PHY_1251_DATA + DDRSS_PHY_1252_DATA + DDRSS_PHY_1253_DATA + DDRSS_PHY_1254_DATA + DDRSS_PHY_1255_DATA + DDRSS_PHY_1256_DATA + DDRSS_PHY_1257_DATA + DDRSS_PHY_1258_DATA + DDRSS_PHY_1259_DATA + DDRSS_PHY_1260_DATA + DDRSS_PHY_1261_DATA + DDRSS_PHY_1262_DATA + DDRSS_PHY_1263_DATA + DDRSS_PHY_1264_DATA + DDRSS_PHY_1265_DATA + DDRSS_PHY_1266_DATA + DDRSS_PHY_1267_DATA + DDRSS_PHY_1268_DATA + DDRSS_PHY_1269_DATA + DDRSS_PHY_1270_DATA + DDRSS_PHY_1271_DATA + DDRSS_PHY_1272_DATA + DDRSS_PHY_1273_DATA + DDRSS_PHY_1274_DATA + DDRSS_PHY_1275_DATA + DDRSS_PHY_1276_DATA + DDRSS_PHY_1277_DATA + DDRSS_PHY_1278_DATA + DDRSS_PHY_1279_DATA + DDRSS_PHY_1280_DATA + DDRSS_PHY_1281_DATA + DDRSS_PHY_1282_DATA + DDRSS_PHY_1283_DATA + DDRSS_PHY_1284_DATA + DDRSS_PHY_1285_DATA + DDRSS_PHY_1286_DATA + DDRSS_PHY_1287_DATA + DDRSS_PHY_1288_DATA + DDRSS_PHY_1289_DATA + DDRSS_PHY_1290_DATA + DDRSS_PHY_1291_DATA + DDRSS_PHY_1292_DATA + DDRSS_PHY_1293_DATA + DDRSS_PHY_1294_DATA + DDRSS_PHY_1295_DATA + DDRSS_PHY_1296_DATA + DDRSS_PHY_1297_DATA + DDRSS_PHY_1298_DATA + DDRSS_PHY_1299_DATA + DDRSS_PHY_1300_DATA + DDRSS_PHY_1301_DATA + DDRSS_PHY_1302_DATA + DDRSS_PHY_1303_DATA + DDRSS_PHY_1304_DATA + DDRSS_PHY_1305_DATA + DDRSS_PHY_1306_DATA + DDRSS_PHY_1307_DATA + DDRSS_PHY_1308_DATA + DDRSS_PHY_1309_DATA + DDRSS_PHY_1310_DATA + DDRSS_PHY_1311_DATA + DDRSS_PHY_1312_DATA + DDRSS_PHY_1313_DATA + DDRSS_PHY_1314_DATA + DDRSS_PHY_1315_DATA + DDRSS_PHY_1316_DATA + DDRSS_PHY_1317_DATA + DDRSS_PHY_1318_DATA + DDRSS_PHY_1319_DATA + DDRSS_PHY_1320_DATA + DDRSS_PHY_1321_DATA + DDRSS_PHY_1322_DATA + DDRSS_PHY_1323_DATA + DDRSS_PHY_1324_DATA + DDRSS_PHY_1325_DATA + DDRSS_PHY_1326_DATA + DDRSS_PHY_1327_DATA + DDRSS_PHY_1328_DATA + DDRSS_PHY_1329_DATA + DDRSS_PHY_1330_DATA + DDRSS_PHY_1331_DATA + DDRSS_PHY_1332_DATA + DDRSS_PHY_1333_DATA + DDRSS_PHY_1334_DATA + DDRSS_PHY_1335_DATA + DDRSS_PHY_1336_DATA + DDRSS_PHY_1337_DATA + DDRSS_PHY_1338_DATA + DDRSS_PHY_1339_DATA + DDRSS_PHY_1340_DATA + DDRSS_PHY_1341_DATA + DDRSS_PHY_1342_DATA + DDRSS_PHY_1343_DATA + DDRSS_PHY_1344_DATA + DDRSS_PHY_1345_DATA + DDRSS_PHY_1346_DATA + DDRSS_PHY_1347_DATA + DDRSS_PHY_1348_DATA + DDRSS_PHY_1349_DATA + DDRSS_PHY_1350_DATA + DDRSS_PHY_1351_DATA + DDRSS_PHY_1352_DATA + DDRSS_PHY_1353_DATA + DDRSS_PHY_1354_DATA + DDRSS_PHY_1355_DATA + DDRSS_PHY_1356_DATA + DDRSS_PHY_1357_DATA + DDRSS_PHY_1358_DATA + DDRSS_PHY_1359_DATA + DDRSS_PHY_1360_DATA + DDRSS_PHY_1361_DATA + DDRSS_PHY_1362_DATA + DDRSS_PHY_1363_DATA + DDRSS_PHY_1364_DATA + DDRSS_PHY_1365_DATA + DDRSS_PHY_1366_DATA + DDRSS_PHY_1367_DATA + DDRSS_PHY_1368_DATA + DDRSS_PHY_1369_DATA + DDRSS_PHY_1370_DATA + DDRSS_PHY_1371_DATA + DDRSS_PHY_1372_DATA + DDRSS_PHY_1373_DATA + DDRSS_PHY_1374_DATA + DDRSS_PHY_1375_DATA + DDRSS_PHY_1376_DATA + DDRSS_PHY_1377_DATA + DDRSS_PHY_1378_DATA + DDRSS_PHY_1379_DATA + DDRSS_PHY_1380_DATA + DDRSS_PHY_1381_DATA + DDRSS_PHY_1382_DATA + DDRSS_PHY_1383_DATA + DDRSS_PHY_1384_DATA + DDRSS_PHY_1385_DATA + DDRSS_PHY_1386_DATA + DDRSS_PHY_1387_DATA + DDRSS_PHY_1388_DATA + DDRSS_PHY_1389_DATA + DDRSS_PHY_1390_DATA + DDRSS_PHY_1391_DATA + DDRSS_PHY_1392_DATA + DDRSS_PHY_1393_DATA + DDRSS_PHY_1394_DATA + DDRSS_PHY_1395_DATA + DDRSS_PHY_1396_DATA + DDRSS_PHY_1397_DATA + DDRSS_PHY_1398_DATA + DDRSS_PHY_1399_DATA + DDRSS_PHY_1400_DATA + DDRSS_PHY_1401_DATA + DDRSS_PHY_1402_DATA + DDRSS_PHY_1403_DATA + DDRSS_PHY_1404_DATA + DDRSS_PHY_1405_DATA + DDRSS_PHY_1406_DATA + DDRSS_PHY_1407_DATA + DDRSS_PHY_1408_DATA + DDRSS_PHY_1409_DATA + DDRSS_PHY_1410_DATA + DDRSS_PHY_1411_DATA + DDRSS_PHY_1412_DATA + DDRSS_PHY_1413_DATA + DDRSS_PHY_1414_DATA + DDRSS_PHY_1415_DATA + DDRSS_PHY_1416_DATA + DDRSS_PHY_1417_DATA + DDRSS_PHY_1418_DATA + DDRSS_PHY_1419_DATA + DDRSS_PHY_1420_DATA + DDRSS_PHY_1421_DATA + DDRSS_PHY_1422_DATA + DDRSS_PHY_1423_DATA + DDRSS_PHY_1424_DATA + DDRSS_PHY_1425_DATA + DDRSS_PHY_1426_DATA + DDRSS_PHY_1427_DATA + DDRSS_PHY_1428_DATA + DDRSS_PHY_1429_DATA + DDRSS_PHY_1430_DATA + DDRSS_PHY_1431_DATA + DDRSS_PHY_1432_DATA + DDRSS_PHY_1433_DATA + DDRSS_PHY_1434_DATA + DDRSS_PHY_1435_DATA + DDRSS_PHY_1436_DATA + DDRSS_PHY_1437_DATA + DDRSS_PHY_1438_DATA + DDRSS_PHY_1439_DATA + DDRSS_PHY_1440_DATA + DDRSS_PHY_1441_DATA + DDRSS_PHY_1442_DATA + DDRSS_PHY_1443_DATA + DDRSS_PHY_1444_DATA + DDRSS_PHY_1445_DATA + DDRSS_PHY_1446_DATA + DDRSS_PHY_1447_DATA + DDRSS_PHY_1448_DATA + DDRSS_PHY_1449_DATA + DDRSS_PHY_1450_DATA + DDRSS_PHY_1451_DATA + DDRSS_PHY_1452_DATA + DDRSS_PHY_1453_DATA + DDRSS_PHY_1454_DATA + DDRSS_PHY_1455_DATA + DDRSS_PHY_1456_DATA + DDRSS_PHY_1457_DATA + DDRSS_PHY_1458_DATA + DDRSS_PHY_1459_DATA + DDRSS_PHY_1460_DATA + DDRSS_PHY_1461_DATA + DDRSS_PHY_1462_DATA + DDRSS_PHY_1463_DATA + DDRSS_PHY_1464_DATA + DDRSS_PHY_1465_DATA + DDRSS_PHY_1466_DATA + DDRSS_PHY_1467_DATA + DDRSS_PHY_1468_DATA + DDRSS_PHY_1469_DATA + DDRSS_PHY_1470_DATA + DDRSS_PHY_1471_DATA + DDRSS_PHY_1472_DATA + DDRSS_PHY_1473_DATA + DDRSS_PHY_1474_DATA + DDRSS_PHY_1475_DATA + DDRSS_PHY_1476_DATA + DDRSS_PHY_1477_DATA + DDRSS_PHY_1478_DATA + DDRSS_PHY_1479_DATA + DDRSS_PHY_1480_DATA + DDRSS_PHY_1481_DATA + DDRSS_PHY_1482_DATA + DDRSS_PHY_1483_DATA + DDRSS_PHY_1484_DATA + DDRSS_PHY_1485_DATA + DDRSS_PHY_1486_DATA + DDRSS_PHY_1487_DATA + DDRSS_PHY_1488_DATA + DDRSS_PHY_1489_DATA + DDRSS_PHY_1490_DATA + DDRSS_PHY_1491_DATA + DDRSS_PHY_1492_DATA + DDRSS_PHY_1493_DATA + DDRSS_PHY_1494_DATA + DDRSS_PHY_1495_DATA + DDRSS_PHY_1496_DATA + DDRSS_PHY_1497_DATA + DDRSS_PHY_1498_DATA + DDRSS_PHY_1499_DATA + DDRSS_PHY_1500_DATA + DDRSS_PHY_1501_DATA + DDRSS_PHY_1502_DATA + DDRSS_PHY_1503_DATA + DDRSS_PHY_1504_DATA + DDRSS_PHY_1505_DATA + DDRSS_PHY_1506_DATA + DDRSS_PHY_1507_DATA + DDRSS_PHY_1508_DATA + DDRSS_PHY_1509_DATA + DDRSS_PHY_1510_DATA + DDRSS_PHY_1511_DATA + DDRSS_PHY_1512_DATA + DDRSS_PHY_1513_DATA + DDRSS_PHY_1514_DATA + DDRSS_PHY_1515_DATA + DDRSS_PHY_1516_DATA + DDRSS_PHY_1517_DATA + DDRSS_PHY_1518_DATA + DDRSS_PHY_1519_DATA + DDRSS_PHY_1520_DATA + DDRSS_PHY_1521_DATA + DDRSS_PHY_1522_DATA + DDRSS_PHY_1523_DATA + DDRSS_PHY_1524_DATA + DDRSS_PHY_1525_DATA + DDRSS_PHY_1526_DATA + DDRSS_PHY_1527_DATA + DDRSS_PHY_1528_DATA + DDRSS_PHY_1529_DATA + DDRSS_PHY_1530_DATA + DDRSS_PHY_1531_DATA + DDRSS_PHY_1532_DATA + DDRSS_PHY_1533_DATA + DDRSS_PHY_1534_DATA + DDRSS_PHY_1535_DATA + DDRSS_PHY_1536_DATA + DDRSS_PHY_1537_DATA + DDRSS_PHY_1538_DATA + DDRSS_PHY_1539_DATA + DDRSS_PHY_1540_DATA + DDRSS_PHY_1541_DATA + DDRSS_PHY_1542_DATA + DDRSS_PHY_1543_DATA + DDRSS_PHY_1544_DATA + DDRSS_PHY_1545_DATA + DDRSS_PHY_1546_DATA + DDRSS_PHY_1547_DATA + DDRSS_PHY_1548_DATA + DDRSS_PHY_1549_DATA + DDRSS_PHY_1550_DATA + DDRSS_PHY_1551_DATA + DDRSS_PHY_1552_DATA + DDRSS_PHY_1553_DATA + DDRSS_PHY_1554_DATA + DDRSS_PHY_1555_DATA + DDRSS_PHY_1556_DATA + DDRSS_PHY_1557_DATA + DDRSS_PHY_1558_DATA + DDRSS_PHY_1559_DATA + DDRSS_PHY_1560_DATA + DDRSS_PHY_1561_DATA + DDRSS_PHY_1562_DATA + DDRSS_PHY_1563_DATA + DDRSS_PHY_1564_DATA + DDRSS_PHY_1565_DATA + DDRSS_PHY_1566_DATA + DDRSS_PHY_1567_DATA + DDRSS_PHY_1568_DATA + DDRSS_PHY_1569_DATA + DDRSS_PHY_1570_DATA + DDRSS_PHY_1571_DATA + DDRSS_PHY_1572_DATA + DDRSS_PHY_1573_DATA + DDRSS_PHY_1574_DATA + DDRSS_PHY_1575_DATA + DDRSS_PHY_1576_DATA + DDRSS_PHY_1577_DATA + DDRSS_PHY_1578_DATA + DDRSS_PHY_1579_DATA + DDRSS_PHY_1580_DATA + DDRSS_PHY_1581_DATA + DDRSS_PHY_1582_DATA + DDRSS_PHY_1583_DATA + DDRSS_PHY_1584_DATA + DDRSS_PHY_1585_DATA + DDRSS_PHY_1586_DATA + DDRSS_PHY_1587_DATA + DDRSS_PHY_1588_DATA + DDRSS_PHY_1589_DATA + DDRSS_PHY_1590_DATA + DDRSS_PHY_1591_DATA + DDRSS_PHY_1592_DATA + DDRSS_PHY_1593_DATA + DDRSS_PHY_1594_DATA + DDRSS_PHY_1595_DATA + DDRSS_PHY_1596_DATA + DDRSS_PHY_1597_DATA + DDRSS_PHY_1598_DATA + DDRSS_PHY_1599_DATA + DDRSS_PHY_1600_DATA + DDRSS_PHY_1601_DATA + DDRSS_PHY_1602_DATA + DDRSS_PHY_1603_DATA + DDRSS_PHY_1604_DATA + DDRSS_PHY_1605_DATA + DDRSS_PHY_1606_DATA + DDRSS_PHY_1607_DATA + DDRSS_PHY_1608_DATA + DDRSS_PHY_1609_DATA + DDRSS_PHY_1610_DATA + DDRSS_PHY_1611_DATA + DDRSS_PHY_1612_DATA + DDRSS_PHY_1613_DATA + DDRSS_PHY_1614_DATA + DDRSS_PHY_1615_DATA + DDRSS_PHY_1616_DATA + DDRSS_PHY_1617_DATA + DDRSS_PHY_1618_DATA + DDRSS_PHY_1619_DATA + DDRSS_PHY_1620_DATA + DDRSS_PHY_1621_DATA + DDRSS_PHY_1622_DATA + DDRSS_PHY_1623_DATA + DDRSS_PHY_1624_DATA + DDRSS_PHY_1625_DATA + DDRSS_PHY_1626_DATA + DDRSS_PHY_1627_DATA + DDRSS_PHY_1628_DATA + DDRSS_PHY_1629_DATA + DDRSS_PHY_1630_DATA + DDRSS_PHY_1631_DATA + DDRSS_PHY_1632_DATA + DDRSS_PHY_1633_DATA + DDRSS_PHY_1634_DATA + DDRSS_PHY_1635_DATA + DDRSS_PHY_1636_DATA + DDRSS_PHY_1637_DATA + DDRSS_PHY_1638_DATA + DDRSS_PHY_1639_DATA + DDRSS_PHY_1640_DATA + DDRSS_PHY_1641_DATA + DDRSS_PHY_1642_DATA + DDRSS_PHY_1643_DATA + DDRSS_PHY_1644_DATA + DDRSS_PHY_1645_DATA + DDRSS_PHY_1646_DATA + DDRSS_PHY_1647_DATA + DDRSS_PHY_1648_DATA + DDRSS_PHY_1649_DATA + DDRSS_PHY_1650_DATA + DDRSS_PHY_1651_DATA + DDRSS_PHY_1652_DATA + DDRSS_PHY_1653_DATA + DDRSS_PHY_1654_DATA + DDRSS_PHY_1655_DATA + DDRSS_PHY_1656_DATA + DDRSS_PHY_1657_DATA + DDRSS_PHY_1658_DATA + DDRSS_PHY_1659_DATA + DDRSS_PHY_1660_DATA + DDRSS_PHY_1661_DATA + DDRSS_PHY_1662_DATA + DDRSS_PHY_1663_DATA + DDRSS_PHY_1664_DATA + DDRSS_PHY_1665_DATA + DDRSS_PHY_1666_DATA + DDRSS_PHY_1667_DATA + DDRSS_PHY_1668_DATA + DDRSS_PHY_1669_DATA + DDRSS_PHY_1670_DATA + DDRSS_PHY_1671_DATA + DDRSS_PHY_1672_DATA + DDRSS_PHY_1673_DATA + DDRSS_PHY_1674_DATA + DDRSS_PHY_1675_DATA + DDRSS_PHY_1676_DATA + DDRSS_PHY_1677_DATA + DDRSS_PHY_1678_DATA + DDRSS_PHY_1679_DATA + DDRSS_PHY_1680_DATA + DDRSS_PHY_1681_DATA + DDRSS_PHY_1682_DATA + DDRSS_PHY_1683_DATA + DDRSS_PHY_1684_DATA + DDRSS_PHY_1685_DATA + DDRSS_PHY_1686_DATA + DDRSS_PHY_1687_DATA + DDRSS_PHY_1688_DATA + DDRSS_PHY_1689_DATA + DDRSS_PHY_1690_DATA + DDRSS_PHY_1691_DATA + DDRSS_PHY_1692_DATA + DDRSS_PHY_1693_DATA + DDRSS_PHY_1694_DATA + DDRSS_PHY_1695_DATA + DDRSS_PHY_1696_DATA + DDRSS_PHY_1697_DATA + DDRSS_PHY_1698_DATA + DDRSS_PHY_1699_DATA + DDRSS_PHY_1700_DATA + DDRSS_PHY_1701_DATA + DDRSS_PHY_1702_DATA + DDRSS_PHY_1703_DATA + DDRSS_PHY_1704_DATA + DDRSS_PHY_1705_DATA + DDRSS_PHY_1706_DATA + DDRSS_PHY_1707_DATA + DDRSS_PHY_1708_DATA + DDRSS_PHY_1709_DATA + DDRSS_PHY_1710_DATA + DDRSS_PHY_1711_DATA + DDRSS_PHY_1712_DATA + DDRSS_PHY_1713_DATA + DDRSS_PHY_1714_DATA + DDRSS_PHY_1715_DATA + DDRSS_PHY_1716_DATA + DDRSS_PHY_1717_DATA + DDRSS_PHY_1718_DATA + DDRSS_PHY_1719_DATA + DDRSS_PHY_1720_DATA + DDRSS_PHY_1721_DATA + DDRSS_PHY_1722_DATA + DDRSS_PHY_1723_DATA + DDRSS_PHY_1724_DATA + DDRSS_PHY_1725_DATA + DDRSS_PHY_1726_DATA + DDRSS_PHY_1727_DATA + DDRSS_PHY_1728_DATA + DDRSS_PHY_1729_DATA + DDRSS_PHY_1730_DATA + DDRSS_PHY_1731_DATA + DDRSS_PHY_1732_DATA + DDRSS_PHY_1733_DATA + DDRSS_PHY_1734_DATA + DDRSS_PHY_1735_DATA + DDRSS_PHY_1736_DATA + DDRSS_PHY_1737_DATA + DDRSS_PHY_1738_DATA + DDRSS_PHY_1739_DATA + DDRSS_PHY_1740_DATA + DDRSS_PHY_1741_DATA + DDRSS_PHY_1742_DATA + DDRSS_PHY_1743_DATA + DDRSS_PHY_1744_DATA + DDRSS_PHY_1745_DATA + DDRSS_PHY_1746_DATA + DDRSS_PHY_1747_DATA + DDRSS_PHY_1748_DATA + DDRSS_PHY_1749_DATA + DDRSS_PHY_1750_DATA + DDRSS_PHY_1751_DATA + DDRSS_PHY_1752_DATA + DDRSS_PHY_1753_DATA + DDRSS_PHY_1754_DATA + DDRSS_PHY_1755_DATA + DDRSS_PHY_1756_DATA + DDRSS_PHY_1757_DATA + DDRSS_PHY_1758_DATA + DDRSS_PHY_1759_DATA + DDRSS_PHY_1760_DATA + DDRSS_PHY_1761_DATA + DDRSS_PHY_1762_DATA + DDRSS_PHY_1763_DATA + DDRSS_PHY_1764_DATA + DDRSS_PHY_1765_DATA + DDRSS_PHY_1766_DATA + DDRSS_PHY_1767_DATA + DDRSS_PHY_1768_DATA + DDRSS_PHY_1769_DATA + DDRSS_PHY_1770_DATA + DDRSS_PHY_1771_DATA + DDRSS_PHY_1772_DATA + DDRSS_PHY_1773_DATA + DDRSS_PHY_1774_DATA + DDRSS_PHY_1775_DATA + DDRSS_PHY_1776_DATA + DDRSS_PHY_1777_DATA + DDRSS_PHY_1778_DATA + DDRSS_PHY_1779_DATA + DDRSS_PHY_1780_DATA + DDRSS_PHY_1781_DATA + DDRSS_PHY_1782_DATA + DDRSS_PHY_1783_DATA + DDRSS_PHY_1784_DATA + DDRSS_PHY_1785_DATA + DDRSS_PHY_1786_DATA + DDRSS_PHY_1787_DATA + DDRSS_PHY_1788_DATA + DDRSS_PHY_1789_DATA + DDRSS_PHY_1790_DATA + DDRSS_PHY_1791_DATA + DDRSS_PHY_1792_DATA + DDRSS_PHY_1793_DATA + DDRSS_PHY_1794_DATA + DDRSS_PHY_1795_DATA + DDRSS_PHY_1796_DATA + DDRSS_PHY_1797_DATA + DDRSS_PHY_1798_DATA + DDRSS_PHY_1799_DATA + DDRSS_PHY_1800_DATA + DDRSS_PHY_1801_DATA + DDRSS_PHY_1802_DATA + DDRSS_PHY_1803_DATA + DDRSS_PHY_1804_DATA + DDRSS_PHY_1805_DATA + DDRSS_PHY_1806_DATA + DDRSS_PHY_1807_DATA + DDRSS_PHY_1808_DATA + DDRSS_PHY_1809_DATA + DDRSS_PHY_1810_DATA + DDRSS_PHY_1811_DATA + DDRSS_PHY_1812_DATA + DDRSS_PHY_1813_DATA + DDRSS_PHY_1814_DATA + DDRSS_PHY_1815_DATA + DDRSS_PHY_1816_DATA + DDRSS_PHY_1817_DATA + DDRSS_PHY_1818_DATA + DDRSS_PHY_1819_DATA + DDRSS_PHY_1820_DATA + DDRSS_PHY_1821_DATA + DDRSS_PHY_1822_DATA + DDRSS_PHY_1823_DATA + DDRSS_PHY_1824_DATA + DDRSS_PHY_1825_DATA + DDRSS_PHY_1826_DATA + DDRSS_PHY_1827_DATA + DDRSS_PHY_1828_DATA + DDRSS_PHY_1829_DATA + DDRSS_PHY_1830_DATA + DDRSS_PHY_1831_DATA + DDRSS_PHY_1832_DATA + DDRSS_PHY_1833_DATA + DDRSS_PHY_1834_DATA + DDRSS_PHY_1835_DATA + DDRSS_PHY_1836_DATA + DDRSS_PHY_1837_DATA + DDRSS_PHY_1838_DATA + DDRSS_PHY_1839_DATA + DDRSS_PHY_1840_DATA + DDRSS_PHY_1841_DATA + DDRSS_PHY_1842_DATA + DDRSS_PHY_1843_DATA + DDRSS_PHY_1844_DATA + DDRSS_PHY_1845_DATA + DDRSS_PHY_1846_DATA + DDRSS_PHY_1847_DATA + DDRSS_PHY_1848_DATA + DDRSS_PHY_1849_DATA + DDRSS_PHY_1850_DATA + DDRSS_PHY_1851_DATA + DDRSS_PHY_1852_DATA + DDRSS_PHY_1853_DATA + DDRSS_PHY_1854_DATA + DDRSS_PHY_1855_DATA + DDRSS_PHY_1856_DATA + DDRSS_PHY_1857_DATA + DDRSS_PHY_1858_DATA + DDRSS_PHY_1859_DATA + DDRSS_PHY_1860_DATA + DDRSS_PHY_1861_DATA + DDRSS_PHY_1862_DATA + DDRSS_PHY_1863_DATA + DDRSS_PHY_1864_DATA + DDRSS_PHY_1865_DATA + DDRSS_PHY_1866_DATA + DDRSS_PHY_1867_DATA + DDRSS_PHY_1868_DATA + DDRSS_PHY_1869_DATA + DDRSS_PHY_1870_DATA + DDRSS_PHY_1871_DATA + DDRSS_PHY_1872_DATA + DDRSS_PHY_1873_DATA + DDRSS_PHY_1874_DATA + DDRSS_PHY_1875_DATA + DDRSS_PHY_1876_DATA + DDRSS_PHY_1877_DATA + DDRSS_PHY_1878_DATA + DDRSS_PHY_1879_DATA + DDRSS_PHY_1880_DATA + DDRSS_PHY_1881_DATA + DDRSS_PHY_1882_DATA + DDRSS_PHY_1883_DATA + DDRSS_PHY_1884_DATA + DDRSS_PHY_1885_DATA + DDRSS_PHY_1886_DATA + DDRSS_PHY_1887_DATA + DDRSS_PHY_1888_DATA + DDRSS_PHY_1889_DATA + DDRSS_PHY_1890_DATA + DDRSS_PHY_1891_DATA + DDRSS_PHY_1892_DATA + DDRSS_PHY_1893_DATA + DDRSS_PHY_1894_DATA + DDRSS_PHY_1895_DATA + DDRSS_PHY_1896_DATA + DDRSS_PHY_1897_DATA + DDRSS_PHY_1898_DATA + DDRSS_PHY_1899_DATA + DDRSS_PHY_1900_DATA + DDRSS_PHY_1901_DATA + DDRSS_PHY_1902_DATA + DDRSS_PHY_1903_DATA + DDRSS_PHY_1904_DATA + DDRSS_PHY_1905_DATA + DDRSS_PHY_1906_DATA + DDRSS_PHY_1907_DATA + DDRSS_PHY_1908_DATA + DDRSS_PHY_1909_DATA + DDRSS_PHY_1910_DATA + DDRSS_PHY_1911_DATA + DDRSS_PHY_1912_DATA + DDRSS_PHY_1913_DATA + DDRSS_PHY_1914_DATA + DDRSS_PHY_1915_DATA + DDRSS_PHY_1916_DATA + DDRSS_PHY_1917_DATA + DDRSS_PHY_1918_DATA + DDRSS_PHY_1919_DATA + DDRSS_PHY_1920_DATA + DDRSS_PHY_1921_DATA + DDRSS_PHY_1922_DATA + DDRSS_PHY_1923_DATA + >; + }; +}; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts new file mode 100644 index 0000000000..58b7c8ad05 --- /dev/null +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A7 SK dts file for R5 SPL + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62a7-sk.dts" +#include "k3-am62a-ddr-1866mhz-32bit.dtsi" +#include "k3-am62a-ddr.dtsi" + +#include "k3-am62a7-sk-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */ + u-boot,dm-spl; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + u-boot,dm-spl; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + u-boot,dm-spl; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x0 0x44860000 0x0 0x20000>, + <0x0 0x43600000 0x0 0x10000>; + reg-names = "rt", "scfg", "target_data"; + u-boot,dm-spl; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + u-boot,dm-spl; + }; +}; + +&mcu_pmx0 { + status = "okay"; + u-boot,dm-spl; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ + >; + u-boot,dm-spl; + }; +}; + +&main_pmx0 { + u-boot,dm-spl; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + u-boot,dm-spl; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "okay"; + u-boot,dm-spl; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "okay"; + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi new file mode 100644 index 0000000000..7fc749ed70 --- /dev/null +++ b/arch/arm/dts/k3-am62a7-sk-u-boot.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM62A EVM dts file for SPLs + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/ { + chosen { + stdout-path = "serial2:115200n8"; + tick-timer = &timer1; + }; + + memory@80000000 { + u-boot,dm-spl; + }; +}; + +&cbass_main{ + u-boot,dm-spl; + + timer1: timer@2400000 { + compatible = "ti,omap5430-timer"; + reg = <0x00 0x2400000 0x00 0x80>; + ti,timer-alwon; + clock-frequency = <25000000>; + u-boot,dm-spl; + }; +}; + +&dmss { + u-boot,dm-spl; +}; + +&secure_proxy_main { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; +}; + +&k3_pds { + u-boot,dm-spl; +}; + +&k3_clks { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&wkup_conf { + u-boot,dm-spl; +}; + +&chipid { + u-boot,dm-spl; +}; + +&main_pmx0 { + u-boot,dm-spl; +}; + +&main_uart0 { + u-boot,dm-spl; +}; + +&main_uart0_pins_default { + u-boot,dm-spl; +}; + +&main_uart1 { + u-boot,dm-spl; +}; + +&cbass_mcu { + u-boot,dm-spl; +}; + +&cbass_wakeup { + u-boot,dm-spl; +}; + +&mcu_pmx0 { + u-boot,dm-spl; +}; + +&wkup_uart0 { + u-boot,dm-spl; +}; + +&main_gpio0 { + u-boot,dm-spl; +}; + +&main_i2c0 { + u-boot,dm-spl; +}; + +&main_i2c0_pins_default { + u-boot,dm-spl; +}; + +&main_i2c1 { + u-boot,dm-spl; +}; + +&main_i2c1_pins_default { + u-boot,dm-spl; +}; + +&exp1 { + u-boot,dm-spl; +}; + +&sdhci1 { + u-boot,dm-spl; +}; + +&main_mmc1_pins_default { + u-boot,dm-spl; +}; + +&k3_reset { + u-boot,dm-spl; +}; + +&dmsc { + u-boot,dm-spl; + k3_sysreset: sysreset-controller { + compatible = "ti,sci-sysreset"; + u-boot,dm-spl; + }; +}; + +&vdd_mmc1 { + u-boot,dm-spl; +}; From f54febe1b126b5ebede3d9784e07c10b9da299a1 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:53 -0500 Subject: [PATCH 140/424] ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof Reviewed-by: Tom Rini --- drivers/ram/Kconfig | 1 + drivers/ram/k3-ddrss/k3-ddrss.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index bf279b79f6..e085119963 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,6 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 config K3_J721E_DDRSS bool "Enable J721E DDRSS support" diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index e8b7aec9e0..7e445d2b73 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -706,6 +706,7 @@ static const struct k3_ddrss_data j721s2_data = { }; static const struct udevice_id k3_ddrss_ids[] = { + {.compatible = "ti,am62a-ddrss", .data = (ulong)&k3_data, }, {.compatible = "ti,am64-ddrss", .data = (ulong)&k3_data, }, {.compatible = "ti,j721e-ddrss", .data = (ulong)&k3_data, }, {.compatible = "ti,j721s2-ddrss", .data = (ulong)&j721s2_data, }, From e38025c8b54728c7e41fee33586cd4eca31a4166 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:54 -0500 Subject: [PATCH 141/424] soc: ti: k3-socinfo: add am62a SoC entry Add identification support for TI's am62ax family of SoCs Signed-off-by: Bryan Brattlof Reviewed-by: Tom Rini --- drivers/soc/soc_ti_k3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index b1e7c4ae5f..8af0ac7051 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -16,6 +16,7 @@ #define AM64X 0xbb38 #define J721S2 0xbb75 #define AM62X 0xbb7e +#define AM62AX 0xbb8d #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) @@ -53,6 +54,9 @@ static const char *get_family_string(u32 idreg) case AM62X: family = "AM62X"; break; + case AM62AX: + family = "AM62AX"; + break; default: family = "Unknown Silicon"; }; From b511b371ad76c592fac49f8f780bd42310479d1e Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:55 -0500 Subject: [PATCH 142/424] arm: mach-k3: introduce basic files to support the am62a Introduce the mach-k3 files needed to properly boot TI's am62a SoC family of devices Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/Kconfig | 14 +- arch/arm/mach-k3/Makefile | 2 + arch/arm/mach-k3/am62a7_init.c | 250 ++++++++++++++++++ arch/arm/mach-k3/arm64-mmu.c | 6 +- .../arm/mach-k3/include/mach/am62a_hardware.h | 74 ++++++ arch/arm/mach-k3/include/mach/am62a_spl.h | 49 ++++ arch/arm/mach-k3/include/mach/hardware.h | 4 + arch/arm/mach-k3/include/mach/spl.h | 4 + 8 files changed, 396 insertions(+), 7 deletions(-) create mode 100644 arch/arm/mach-k3/am62a7_init.c create mode 100644 arch/arm/mach-k3/include/mach/am62a_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am62a_spl.h diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 171a7f2f25..87da6b49ee 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -19,6 +19,9 @@ config SOC_K3_AM642 config SOC_K3_AM625 bool "TI's K3 based AM625 SoC Family Support" +config SOC_K3_AM62A7 + bool "TI's K3 based AM62A7 SoC Family Support" + endchoice config SYS_SOC @@ -29,7 +32,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE default 0x80000 if SOC_K3_AM654 default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 default 0x1c0000 if SOC_K3_AM642 - default 0x3c000 if SOC_K3_AM625 + default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7 help Describes the total size of the MCU or OCMC MSRAM present on the SoC in use. This doesn't specify the total size of SPL as @@ -41,7 +44,7 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE default 0x58000 if SOC_K3_AM654 default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 default 0x180000 if SOC_K3_AM642 - default 0x38000 if SOC_K3_AM625 + default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7 help Describes the maximum size of the image that ROM can download from any boot media. @@ -66,7 +69,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX default 0x41cffbfc if SOC_K3_J721E default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 - default 0x43c3f290 if SOC_K3_AM625 + default 0x43c3f290 if SOC_K3_AM625 || SOC_K3_AM62A7 help Address at which ROM stores the value which determines if SPL is booted up by primary boot media or secondary boot media. @@ -135,7 +138,7 @@ config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART config K3_SYSFW_IMAGE_SIZE_MAX int "Amount of memory dynamically allocated for loading SYSFW blob" depends on K3_LOAD_SYSFW - default 163840 if SOC_K3_AM625 + default 163840 if SOC_K3_AM625 || SOC_K3_AM62A7 default 278000 help Amount of memory (in bytes) reserved through dynamic allocation at @@ -167,7 +170,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -185,6 +188,7 @@ config K3_X509_SWRV source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/am62x/Kconfig" +source "board/ti/am62ax/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" source "board/ti/j721s2/Kconfig" diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 6ac2b61c3d..b5bc236781 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/ obj-$(CONFIG_SOC_K3_J721S2) += j721s2/ obj-$(CONFIG_SOC_K3_AM625) += am62x/ +obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_ARM64) += cache.o @@ -15,6 +16,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_SOC_K3_AM625) += am625_init.o +obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o endif obj-y += common.o security.o diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c new file mode 100644 index 0000000000..e9569f0d26 --- /dev/null +++ b/arch/arm/mach-k3/am62a7_init.c @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62A7: SoC specific initialization + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include "common.h" +#include +#include +#include + +/* + * This uninitialized global variable would normal end up in the .bss section, + * but the .bss is cleared between writing and reading this variable, so move + * it to the .data section. + */ +u32 bootindex __section(".data"); +static struct rom_extended_boot_data bootdata __section(".data"); + +static void store_boot_info_from_rom(void) +{ + bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); + memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO, + sizeof(struct rom_extended_boot_data)); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 5); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 4); + mmr_unlock(CTRL_MMR0_BASE, 5); + mmr_unlock(CTRL_MMR0_BASE, 6); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 3); + mmr_unlock(MCU_CTRL_MMR0_BASE, 4); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock PADCFG_CTRL_MMR padconf registers */ + mmr_unlock(PADCFG_MMR0_BASE, 1); + mmr_unlock(PADCFG_MMR1_BASE, 1); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#if defined(CONFIG_CPU_V7R) + setup_k3_mpu_regions(); +#endif + + /* + * Cannot delay this further as there is a chance that + * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. + */ + store_boot_info_from_rom(); + + ctrl_mmr_unlock(); + + /* Init DM early */ + spl_early_init(); + + /* + * Process pinctrl for the serial0 and serial3, aka WKUP_UART0 and + * MAIN_UART1 modules and continue regardless of the result of pinctrl. + * Do this without probing the device, but instead by searching the + * device that would request the given sequence number if probed. The + * UARTs will be used by the DM firmware and TIFS firmware images + * respectively and the firmware depend on SPL to initialize the pin + * settings. + */ + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + if (!ret) + pinctrl_select_state(dev, "default"); + +#ifdef CONFIG_K3_EARLY_CONS + /* + * Allow establishing an early console as required for example when + * doing a UART-based boot. Note that this console may not "survive" + * through a SYSFW PM-init step and will need a re-init in some way + * due to changing module clock frequencies. + */ + early_console_init(); +#endif + +#if defined(CONFIG_K3_LOAD_SYSFW) + /* + * Configure and start up system controller firmware. Provide + * the U-Boot console init function to the SYSFW post-PM configuration + * callback hook, effectively switching on (or over) the console + * output. + */ + ret = is_rom_loaded_sysfw(&bootdata); + if (!ret) + panic("ROM has not loaded TIFS firmware\n"); + + k3_sysfw_loader(true, NULL, NULL); +#endif + + /* + * Force probe of clk_k3 driver here to ensure basic default clock + * configuration is always done. + */ + if (IS_ENABLED(CONFIG_SPL_CLK_K3)) { + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(ti_clk), + &dev); + if (ret) + printf("Failed to initialize clk-k3!\n"); + } + + preloader_console_init(); + + /* Output System Firmware version info */ + k3_sysfw_print_ver(); + +#if defined(CONFIG_K3_AM62A_DDRSS) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("DRAM init failed: %d\n", ret); +#endif + + printf("am62a_init: %s done\n", __func__); +} + +static u32 __get_backup_bootmedia(u32 devstat) +{ + u32 bkup_bootmode = (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT; + u32 bkup_bootmode_cfg = + (devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT; + + switch (bkup_bootmode) { + case BACKUP_BOOT_DEVICE_UART: + return BOOT_DEVICE_UART; + + case BACKUP_BOOT_DEVICE_USB: + return BOOT_DEVICE_USB; + + case BACKUP_BOOT_DEVICE_ETHERNET: + return BOOT_DEVICE_ETHERNET; + + case BACKUP_BOOT_DEVICE_MMC: + if (bkup_bootmode_cfg) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BACKUP_BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BACKUP_BOOT_DEVICE_I2C: + return BOOT_DEVICE_I2C; + + case BACKUP_BOOT_DEVICE_DFU: + if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + }; + + return BOOT_DEVICE_RAM; +} + +static u32 __get_primary_bootmedia(u32 devstat) +{ + u32 bootmode = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; + u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> + MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + + switch (bootmode) { + case BOOT_DEVICE_OSPI: + fallthrough; + case BOOT_DEVICE_QSPI: + fallthrough; + case BOOT_DEVICE_XSPI: + fallthrough; + case BOOT_DEVICE_SPI: + return BOOT_DEVICE_SPI; + + case BOOT_DEVICE_ETHERNET_RGMII: + fallthrough; + case BOOT_DEVICE_ETHERNET_RMII: + return BOOT_DEVICE_ETHERNET; + + case BOOT_DEVICE_EMMC: + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_SPI_NAND: + return BOOT_DEVICE_SPINAND; + + case BOOT_DEVICE_MMC: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >> + MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT) + return BOOT_DEVICE_MMC2; + return BOOT_DEVICE_MMC1; + + case BOOT_DEVICE_DFU: + if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >> + MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT) + return BOOT_DEVICE_USB; + return BOOT_DEVICE_DFU; + + case BOOT_DEVICE_NOBOOT: + return BOOT_DEVICE_RAM; + } + + return bootmode; +} + +u32 spl_boot_device(void) +{ + u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); + u32 bootmedia; + + if (bootindex == K3_PRIMARY_BOOTMODE) + bootmedia = __get_primary_bootmedia(devstat); + else + bootmedia = __get_backup_bootmedia(devstat); + + printf("am62a_init: %s: devstat = 0x%x bootmedia = 0x%x bootindex = %d\n", + __func__, devstat, bootmedia, bootindex); + return bootmedia; +} diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index b4d7ab1f16..88687c2d09 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -222,7 +222,9 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ -#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) +#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ + defined(CONFIG_SOC_K3_AM62A7) + /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) @@ -261,4 +263,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 */ +#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ diff --git a/arch/arm/mach-k3/include/mach/am62a_hardware.h b/arch/arm/mach-k3/include/mach/am62a_hardware.h new file mode 100644 index 0000000000..52b0d9b3cb --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_hardware.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: AM62A SoC definitions, structures etc. + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __ASM_ARCH_AM62A_HARDWARE_H +#define __ASM_ARCH_AM62A_HARDWARE_H + +#include +#ifndef __ASSEMBLY__ +#include +#endif + +#define PADCFG_MMR0_BASE 0x04080000 +#define PADCFG_MMR1_BASE 0x000f0000 +#define CTRL_MMR0_BASE 0x00100000 +#define MCU_CTRL_MMR0_BASE 0x04500000 +#define WKUP_CTRL_MMR0_BASE 0x43000000 + +#define CTRLMMR_MAIN_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(6, 3) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK GENMASK(9, 7) +#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK GENMASK(12, 10) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10 +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK BIT(13) +#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13 + +/* Primary Bootmode MMC Config macros */ +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x4 +#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK 0x1 +#define MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_SHIFT 0 + +/* Primary Bootmode USB Config macros */ +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02 + +/* Backup Bootmode USB Config macros */ +#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism + * shared register definitions. The same registers are also used for + * PADCFG_MMR lock/kick-mechanism. + */ +#define CTRLMMR_LOCK_KICK0 0x1008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK1 0x100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#define MCU_CTRL_LFXOSC_CTRL (MCU_CTRL_MMR0_BASE + 0x8038) +#define MCU_CTRL_LFXOSC_TRIM (MCU_CTRL_MMR0_BASE + 0x803c) +#define MCU_CTRL_LFXOSC_32K_DISABLE_VAL BIT(7) + +#define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL (MCU_CTRL_MMR0_BASE + 0x8058) +#define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL (0x3) + +#define ROM_ENTENDED_BOOT_DATA_INFO 0x43c3f1e0 + +/* Use Last 2K as Scratch pad */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x70000001 + +#endif /* __ASM_ARCH_AM62A_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/am62a_spl.h b/arch/arm/mach-k3/include/mach/am62a_spl.h new file mode 100644 index 0000000000..dd0f57714f --- /dev/null +++ b/arch/arm/mach-k3/include/mach/am62a_spl.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef _ASM_ARCH_AM62A_SPL_H_ +#define _ASM_ARCH_AM62A_SPL_H_ + +/* Primary BootMode devices */ +#define BOOT_DEVICE_SPI_NAND 0x00 +#define BOOT_DEVICE_RAM 0xFF +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 +#define BOOT_DEVICE_ETHERNET_RGMII 0x04 +#define BOOT_DEVICE_ETHERNET_RMII 0x05 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_MMC 0x08 +#define BOOT_DEVICE_EMMC 0x09 + +#define BOOT_DEVICE_USB 0x2A +#define BOOT_DEVICE_DFU 0x0A +#define BOOT_DEVICE_GPMC_NAND 0x0B +#define BOOT_DEVICE_GPMC_NOR 0x0C +#define BOOT_DEVICE_XSPI 0x0E +#define BOOT_DEVICE_NOBOOT 0x0F + +/* U-Boot used aliases */ +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_SPINAND 0x10 +#define BOOT_DEVICE_MMC2 0x08 +#define BOOT_DEVICE_MMC1 0x09 +/* Invalid */ +#define BOOT_DEVICE_MMC2_2 0x1F + +/* Backup BootMode devices */ +#define BACKUP_BOOT_DEVICE_DFU 0x01 +#define BACKUP_BOOT_DEVICE_UART 0x03 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x04 +#define BACKUP_BOOT_DEVICE_MMC 0x05 +#define BACKUP_BOOT_DEVICE_SPI 0x06 +#define BACKUP_BOOT_DEVICE_I2C 0x07 +#define BACKUP_BOOT_DEVICE_USB 0x09 + +#define K3_PRIMARY_BOOTMODE 0x0 + +#endif /* _ASM_ARCH_AM62A_SPL_H_ */ diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index d6d2cf6dc2..2c60ef8543 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -26,6 +26,10 @@ #include "am62_hardware.h" #endif +#ifdef CONFIG_SOC_K3_AM62A7 +#include "am62a_hardware.h" +#endif + /* Assuming these addresses and definitions stay common across K3 devices */ #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14) #define JTAG_ID_VARIANT_SHIFT 28 diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index c9a324a5f0..356cd89210 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -26,4 +26,8 @@ #include "am62_spl.h" #endif +#ifdef CONFIG_SOC_K3_AM62A7 +#include "am62a_spl.h" +#endif + #endif /* _ASM_ARCH_SPL_H_ */ From b6cbcd61556e0d9de4c389071e3a826e577b9f43 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:56 -0500 Subject: [PATCH 143/424] arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/am62ax/Makefile | 6 + arch/arm/mach-k3/am62ax/clk-data.c | 317 +++++++++++++++++++++++++ arch/arm/mach-k3/am62ax/dev-data.c | 73 ++++++ drivers/clk/ti/clk-k3.c | 6 + drivers/power/domain/ti-power-domain.c | 6 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 7 files changed, 410 insertions(+) create mode 100644 arch/arm/mach-k3/am62ax/Makefile create mode 100644 arch/arm/mach-k3/am62ax/clk-data.c create mode 100644 arch/arm/mach-k3/am62ax/dev-data.c diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile new file mode 100644 index 0000000000..c58e52df1f --- /dev/null +++ b/arch/arm/mach-k3/am62ax/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/am62ax/clk-data.c b/arch/arm/mach-k3/am62ax/clk-data.c new file mode 100644 index 0000000000..d950b35e0b --- /dev/null +++ b/arch/arm/mach-k3/am62ax/clk-data.c @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific clock platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + NULL, + NULL, + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + NULL, +}; + +static const char * const clk_32k_rc_sel_out0_parents[] = { + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_hfosc0_clkout", + "gluelogic_rcosc_clk_1p0v_97p65k", + "gluelogic_lfosc0_clkout", +}; + +static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = { + "board_0_mmc0_clklb_out", + "board_0_mmc0_clk_out", +}; + +static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = { + "board_0_mmc1_clklb_out", + "board_0_mmc1_clk_out", +}; + +static const char * const main_ospi_loopback_clk_sel_out0_parents[] = { + "board_0_ospi0_dqs_out", + "board_0_ospi0_lbclko_out", +}; + +static const char * const main_usb0_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const main_usb1_refclk_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "postdiv4_16ff_main_0_hsdivout8_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = { + "gluelogic_hfosc0_clkout", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const clkout0_ctrl_out0_parents[] = { + "hsdiv4_16fft_main_2_hsdivout1_clk", + "hsdiv4_16fft_main_2_hsdivout1_clk", +}; + +static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { + "postdiv4_16ff_main_0_hsdivout5_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", +}; + +static const char * const main_gtcclk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const char * const main_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout1_clk", + "postdiv1_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_clkout_sel_out0_parents[] = { + NULL, + "gluelogic_lfosc0_clkout", + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "postdiv4_16ff_main_2_hsdivout9_clk", + "clk_32k_rc_sel_out0", + "gluelogic_rcosc_clkout", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clkout_sel_io_out0_parents[] = { + "wkup_clkout_sel_out0", + "gluelogic_hfosc0_clkout", +}; + +static const char * const wkup_clksel_out0_parents[] = { + "hsdiv2_16fft_main_15_hsdivout0_clk", + "hsdiv4_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const main_usart0_fclk_sel_out0_parents[] = { + "usart_programmable_clock_divider_out0", + "hsdiv4_16fft_main_1_hsdivout1_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0), + CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0), + CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0), + CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0), + CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0), + CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0), + CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0), + CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0), + CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0), + CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0), + CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0), + CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0), + CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0), + CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), + CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0), + CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), + CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), + CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), + CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000), + CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0), + CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0), + CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0), + CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0), + CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0), + CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0), + CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 5, "board_0_ext_refclk1_out"), + DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"), + DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"), + DEV_CLK(16, 9, "board_0_ext_refclk1_out"), + DEV_CLK(16, 10, "gluelogic_rcosc_clkout"), + DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"), + DEV_CLK(57, 1, "board_0_mmc0_clklb_out"), + DEV_CLK(57, 2, "board_0_mmc0_clk_out"), + DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"), + DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), + DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), + DEV_CLK(58, 2, "board_0_mmc1_clk_out"), + DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"), + DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"), + DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(61, 0, "main_gtcclk_sel_out0"), + DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(61, 6, "board_0_ext_refclk1_out"), + DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 9, "wkup_clksel_out0"), + DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(75, 0, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"), + DEV_CLK(75, 3, "board_0_ospi0_dqs_out"), + DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"), + DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"), + DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"), + DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(95, 0, "gluelogic_rcosc_clkout"), + DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"), + DEV_CLK(95, 2, "wkup_clksel_out0"), + DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(102, 1, "board_0_i2c0_scl_out"), + DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"), + DEV_CLK(107, 0, "wkup_clksel_out0"), + DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"), + DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"), + DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"), + DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"), + DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"), + DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 20, "clkout0_ctrl_out0"), + DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(157, 25, "board_0_ddr0_ck0_out"), + DEV_CLK(157, 40, "mshsi2c_main_0_porscl"), + DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"), + DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"), + DEV_CLK(157, 160, "wkup_clkout_sel_out0"), + DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"), + DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(161, 10, "board_0_tck_out"), + DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"), + DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"), + DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"), + DEV_CLK(162, 10, "board_0_tck_out"), + DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(170, 2, "board_0_tck_out"), + DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), +}; + +const struct ti_k3_clk_platdata am62ax_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 80, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 104, +}; diff --git a/arch/arm/mach-k3/am62ax/dev-data.c b/arch/arm/mach-k3/am62ax/dev-data.c new file mode 100644 index 0000000000..74739c6385 --- /dev/null +++ b/arch/arm/mach-k3/am62ax/dev-data.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * AM62AX specific device platform data + * + * This file is auto generated. Please do not hand edit and report any issues + * to Bryan Brattlof . + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x04000000), + [1] = PSC(1, 0x00400000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[1], NULL), + [1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]), + [2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]), + [3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]), + [2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]), + [3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]), + [9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]), + [10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]), + [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]), + [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]), + [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(16, &soc_lpsc_list[0]), + PSC_DEV(77, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(95, &soc_lpsc_list[0]), + PSC_DEV(107, &soc_lpsc_list[0]), + PSC_DEV(178, &soc_lpsc_list[1]), + PSC_DEV(179, &soc_lpsc_list[2]), + PSC_DEV(57, &soc_lpsc_list[3]), + PSC_DEV(58, &soc_lpsc_list[4]), + PSC_DEV(161, &soc_lpsc_list[5]), + PSC_DEV(162, &soc_lpsc_list[6]), + PSC_DEV(75, &soc_lpsc_list[7]), + PSC_DEV(102, &soc_lpsc_list[8]), + PSC_DEV(146, &soc_lpsc_list[8]), + PSC_DEV(166, &soc_lpsc_list[9]), + PSC_DEV(135, &soc_lpsc_list[10]), + PSC_DEV(170, &soc_lpsc_list[11]), + PSC_DEV(177, &soc_lpsc_list[12]), + PSC_DEV(55, &soc_lpsc_list[13]), +}; + +const struct ti_k3_pd_platdata am62ax_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 4, + .num_lpsc = 14, + .num_devs = 19, +}; diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c index 0dd65934b3..ba925fa3c4 100644 --- a/drivers/clk/ti/clk-k3.c +++ b/drivers/clk/ti/clk-k3.c @@ -79,6 +79,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = { .family = "AM62X", .data = &am62x_clk_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_AM62A7 + { + .family = "AM62AX", + .data = &am62ax_clk_platdata, + }, #endif { /* sentinel */ } }; diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c index a7f64d04f5..9e7151307c 100644 --- a/drivers/power/domain/ti-power-domain.c +++ b/drivers/power/domain/ti-power-domain.c @@ -92,6 +92,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = { .family = "AM62X", .data = &am62x_pd_platdata, }, +#endif +#ifdef CONFIG_SOC_K3_AM62A7 + { + .family = "AM62AX", + .data = &am62ax_pd_platdata, + }, #endif { /* sentinel */ } }; diff --git a/include/k3-clk.h b/include/k3-clk.h index 371f077c44..49ba53d20f 100644 --- a/include/k3-clk.h +++ b/include/k3-clk.h @@ -175,6 +175,7 @@ extern const struct ti_k3_clk_platdata j721e_clk_platdata; extern const struct ti_k3_clk_platdata j7200_clk_platdata; extern const struct ti_k3_clk_platdata j721s2_clk_platdata; extern const struct ti_k3_clk_platdata am62x_clk_platdata; +extern const struct ti_k3_clk_platdata am62ax_clk_platdata; struct clk *clk_register_ti_pll(const char *name, const char *parent_name, void __iomem *reg); diff --git a/include/k3-dev.h b/include/k3-dev.h index 87e873b9ce..d288ae3be7 100644 --- a/include/k3-dev.h +++ b/include/k3-dev.h @@ -79,6 +79,7 @@ extern const struct ti_k3_pd_platdata j721e_pd_platdata; extern const struct ti_k3_pd_platdata j7200_pd_platdata; extern const struct ti_k3_pd_platdata j721s2_pd_platdata; extern const struct ti_k3_pd_platdata am62x_pd_platdata; +extern const struct ti_k3_pd_platdata am62ax_pd_platdata; u8 ti_pd_state(struct ti_pd *pd); u8 lpsc_get_state(struct ti_lpsc *lpsc); From d90c8bc441e2f0331fa2365ad07927bbbef725b3 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:57 -0500 Subject: [PATCH 144/424] board: ti: introduce the basic files needed to support the am62a Introduce the bare minimum SD and UART support for the am62a sk. Signed-off-by: Bryan Brattlof Reviewed-by: Tom Rini --- board/ti/am62ax/Kconfig | 52 +++++++++++++++++++++++++++ board/ti/am62ax/MAINTAINERS | 9 +++++ board/ti/am62ax/Makefile | 7 ++++ board/ti/am62ax/evm.c | 31 ++++++++++++++++ drivers/firmware/ti_sci_static_data.h | 4 +-- 5 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 board/ti/am62ax/Kconfig create mode 100644 board/ti/am62ax/MAINTAINERS create mode 100644 board/ti/am62ax/Makefile create mode 100644 board/ti/am62ax/evm.c diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig new file mode 100644 index 0000000000..2c18cd49b5 --- /dev/null +++ b/board/ti/am62ax/Kconfig @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# + +choice + prompt "TI K3 AM62Ax based boards" + optional + +config TARGET_AM62A7_A53_EVM + bool "TI K3 based AM62A7 EVM running on A53" + select ARM64 + select SOC_K3_AM62A7 + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM62A7_R5_EVM + bool "TI K3 based AM62A7 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select SOC_K3_AM62A7 + select RAM + select SPL_RAM + select K3_DDRSS + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + +endchoice + +if TARGET_AM62A7_R5_EVM || TARGET_AM62A7_A53_EVM + +config SYS_BOARD + default "am62ax" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am62ax_evm" + +source "board/ti/common/Kconfig" + +endif + +if TARGET_AM62A7_R5_EVM + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +endif diff --git a/board/ti/am62ax/MAINTAINERS b/board/ti/am62ax/MAINTAINERS new file mode 100644 index 0000000000..590f683584 --- /dev/null +++ b/board/ti/am62ax/MAINTAINERS @@ -0,0 +1,9 @@ +AM62Ax BOARD +M: Vignesh Raghavendra +M: Bryan Brattlof +M: Tom Rini +S: Maintained +F: board/ti/am62ax/ +F: include/configs/am62a7_evm.h +F: configs/am62ax_evm_r5_defconfig +F: configs/am62ax_evm_a53_defconfig diff --git a/board/ti/am62ax/Makefile b/board/ti/am62ax/Makefile new file mode 100644 index 0000000000..4e8e7aa230 --- /dev/null +++ b/board/ti/am62ax/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evm.o diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c new file mode 100644 index 0000000000..beef3f2f3d --- /dev/null +++ b/board/ti/am62ax/evm.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Board specific initialization for AM62Ax platforms + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h index 5ae0556a9a..1a461fab61 100644 --- a/drivers/firmware/ti_sci_static_data.h +++ b/drivers/firmware/ti_sci_static_data.h @@ -84,7 +84,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }; #endif /* CONFIG_SOC_K3_J721S2 */ -#if IS_ENABLED(CONFIG_SOC_K3_AM625) +#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) static struct ti_sci_resource_static_data rm_static_data[] = { /* BC channels */ { @@ -95,7 +95,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = { }, { }, }; -#endif /* CONFIG_SOC_K3_AM625 */ +#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ #else static struct ti_sci_resource_static_data rm_static_data[] = { From 719bd650c30e86d43c9a6c1e289e82db802b0d3c Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Thu, 3 Nov 2022 19:13:58 -0500 Subject: [PATCH 145/424] configs: introduce configs for the am62a Introduce the minimum configs, only SD-MMC and UART boot related settings, to serve as a good starting point for the am62a as we add more functionality. Signed-off-by: Bryan Brattlof [trini: Disable CONFIG_NET as it's not used, in both platforms] Signed-off-by: Tom Rini --- configs/am62ax_evm_a53_defconfig | 77 ++++++++++++++++++++++ configs/am62ax_evm_r5_defconfig | 106 +++++++++++++++++++++++++++++++ include/configs/am62ax_evm.h | 68 ++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 configs/am62ax_evm_a53_defconfig create mode 100644 configs/am62ax_evm_r5_defconfig create mode 100644 include/configs/am62ax_evm.h diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig new file mode 100644 index 0000000000..0c2cf945c6 --- /dev/null +++ b/configs/am62ax_evm_a53_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM62A7=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e780000 +CONFIG_TARGET_AM62A7_A53_EVM=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-sk" +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a00000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_CMD_MMC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +# CONFIG_NET is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_TI_SCI_PROTOCOL=y +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig new file mode 100644 index 0000000000..59d5f4f80e --- /dev/null +++ b/configs/am62ax_evm_r5_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62A7=y +CONFIG_TARGET_AM62A7_R5_EVM=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-sk" +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c37800 +CONFIG_SPL_BSS_MAX_SIZE=0x5000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_SPL_MALLOC=y +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_SPL_THERMAL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +# CONFIG_NET is not set +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +# CONFIG_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h new file mode 100644 index 0000000000..5406c39350 --- /dev/null +++ b/include/configs/am62ax_evm.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration header file for K3 AM62Ax SoC family + * + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __CONFIG_AM62AX_EVM_H +#define __CONFIG_AM62AX_EVM_H + +#include +#include +#include +#include + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE1 0x880000000 + +#define PARTS_DEFAULT \ + /* Linux partitions */ \ + "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \ + +/* U-Boot general configuration */ +#define EXTRA_ENV_AM62A7_BOARD_SETTINGS \ + "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "findfdt=" \ + "setenv name_fdt ${default_device_tree};" \ + "setenv fdtfile ${name_fdt}\0" \ + "name_kern=Image\0" \ + "console=ttyS2,115200n8\0" \ + "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \ + "${mtdparts}\0" \ + "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" + +/* U-Boot MMC-specific configuration */ +#define EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \ + "boot=mmc\0" \ + "mmcdev=1\0" \ + "bootpart=1:2\0" \ + "bootdir=/boot\0" \ + "rd_spec=-\0" \ + "init_mmc=run args_all args_mmc\0" \ + "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ + "get_overlay_mmc=" \ + "fdt address ${fdtaddr};" \ + "fdt resize 0x100000;" \ + "for overlay in $name_overlays;" \ + "do;" \ + "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \ + "fdt apply ${dtboaddr};" \ + "done;\0" \ + "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ + "${bootdir}/${name_kern}\0" \ + "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ + "${bootdir}/${name_fit}\0" \ + "partitions=" PARTS_DEFAULT + +/* Incorporate settings into the U-Boot environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV \ + DEFAULT_MMC_TI_ARGS \ + EXTRA_ENV_AM62A7_BOARD_SETTINGS \ + EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \ + +/* Now for the remaining common defines */ +#include + +#endif /* __CONFIG_AM62A7_EVM_H */ From 8bd8a5d02272028ad6ddc2c596fe97175a729e79 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 27 Oct 2022 20:23:09 +0530 Subject: [PATCH 146/424] arm: dts: k3-am62x: sync dt with linux kernel Sync the DT Files with linux kernel (tag v6.0.3) Signed-off-by: Dhruva Gole --- arch/arm/dts/k3-am62-main.dtsi | 54 +++++ arch/arm/dts/k3-am62-mcu.dtsi | 28 +++ arch/arm/dts/k3-am62.dtsi | 1 + arch/arm/dts/k3-am625-sk.dts | 354 +++++++++++++++++++++++++++++++++ 4 files changed, 437 insertions(+) diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi index 4b6ba98dd0..4a42f1b2e3 100644 --- a/arch/arm/dts/k3-am62-main.dtsi +++ b/arch/arm/dts/k3-am62-main.dtsi @@ -165,6 +165,19 @@ }; }; + crypto: crypto@40900000 { + compatible = "ti,am62-sa3ul"; + reg = <0x00 0x40900000 0x00 0x1200>; + power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; + + dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, + <&main_pktdma 0x7507 0>; + dma-names = "tx", "rx1", "rx2"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; @@ -530,4 +543,45 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi index d103824c96..f56c803560 100644 --- a/arch/arm/dts/k3-am62-mcu.dtsi +++ b/arch/arm/dts/k3-am62-mcu.dtsi @@ -53,4 +53,32 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; }; diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi index bc2997b185..37fcbe7a3c 100644 --- a/arch/arm/dts/k3-am62.dtsi +++ b/arch/arm/dts/k3-am62.dtsi @@ -66,6 +66,7 @@ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ diff --git a/arch/arm/dts/k3-am625-sk.dts b/arch/arm/dts/k3-am625-sk.dts index 76b06ea239..af5617ff44 100644 --- a/arch/arm/dts/k3-am625-sk.dts +++ b/arch/arm/dts/k3-am625-sk.dts @@ -18,7 +18,12 @@ aliases { serial2 = &main_uart0; + mmc0 = &sdhci0; mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; chosen { @@ -38,6 +43,15 @@ #size-cells = <2>; ranges; + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -56,6 +70,79 @@ no-map; }; }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; }; &main_pmx0 { @@ -66,6 +153,42 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ @@ -77,6 +200,81 @@ AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ >; }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; }; &wkup_uart0 { @@ -128,10 +326,41 @@ &main_i2c0 { status = "disabled"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; }; &main_i2c1 { status = "disabled"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; }; &main_i2c2 { @@ -142,9 +371,134 @@ status = "disabled"; }; +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; }; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default + &main_rgmii1_pins_default + &main_rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ecap0 { + status = "disabled"; +}; + +&ecap1 { + status = "disabled"; +}; + +&ecap2 { + status = "disabled"; +}; + +&main_mcan0 { + status = "disabled"; +}; From 8994ac365a107ba443ff238719ffb5497a67b347 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 27 Oct 2022 20:23:10 +0530 Subject: [PATCH 147/424] arm: dts: Add OSPI support for AM62-SK Add OSPI Support such that this device can boot up using OSPI Flash. Also can use the flash for other purposes if required from uboot. Signed-off-by: Dhruva Gole --- arch/arm/dts/k3-am625-r5-sk.dts | 5 +++++ arch/arm/dts/k3-am625-sk-u-boot.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 6d696e720d..d39b334ed0 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -155,3 +155,8 @@ status = "okay"; u-boot,dm-spl; }; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi b/arch/arm/dts/k3-am625-sk-u-boot.dtsi index 159fa36bbe..92788bae3e 100644 --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi @@ -102,3 +102,27 @@ &main_mmc1_pins_default { u-boot,dm-spl; }; + +&fss { + u-boot,dm-spl; +}; + +&ospi0_pins_default { + u-boot,dm-spl; +}; + +&ospi0 { + u-boot,dm-spl; + + flash@0 { + u-boot,dm-spl; + + partitions { + u-boot,dm-spl; + + partition@3fc0000 { + u-boot,dm-spl; + }; + }; + }; +}; From 04150400c96785763d17bfee1c01e210cc60f642 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 27 Oct 2022 20:23:11 +0530 Subject: [PATCH 148/424] configs: enable OSPI related configs in AM62x Add am62x_evm_r5_defconfig for OSPI Flash support in R5 SPL and am62x_evm_a53_defconfig for A53 SPL and U-Boot support. These configs enable OSPI Flash boot functionality in the board as well as the usage of OSPI Flash from U-Boot. Signed-off-by: Dhruva Gole --- configs/am62x_evm_a53_defconfig | 19 +++++++++++++++++++ configs/am62x_evm_r5_defconfig | 22 ++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig index ff258bcbc1..e6ffd16692 100644 --- a/configs/am62x_evm_a53_defconfig +++ b/configs/am62x_evm_a53_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000 @@ -31,7 +32,14 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_MMC=y @@ -56,6 +64,14 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ADMA=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x3 +CONFIG_SF_DEFAULT_SPEED=25000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HS512T=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_SINGLE=y @@ -69,6 +85,9 @@ CONFIG_DM_SERIAL=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_TI_SCI=y diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig index 20172557ef..f95bc5f222 100644 --- a/configs/am62x_evm_r5_defconfig +++ b/configs/am62x_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x08000000 CONFIG_SYS_MALLOC_F_LEN=0x9000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y @@ -17,6 +18,10 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_SPL_SIZE_LIMIT=0x40000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7000ffff CONFIG_SPL_LOAD_FIT=y @@ -37,12 +42,17 @@ CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_RESET=y +CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y @@ -91,6 +101,16 @@ CONFIG_DM_RESET=y CONFIG_RESET_TI_SCI=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SPI=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HS512T=y CONFIG_SOC_DEVICE=y CONFIG_SOC_DEVICE_TI_K3=y CONFIG_SOC_TI=y @@ -99,3 +119,5 @@ CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x680000 From 1eaffe39583a784390d579c3ca9e06b58164f4d0 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 20 Oct 2022 12:12:19 -0500 Subject: [PATCH 149/424] arm: mach-omap2: Move common image process functions out of board files The functions board_fit_image_post_process() and board_tee_image_process() are not actually board specific (despite their names). Any board using the OMAP2 family can use these functions. Move them to boot-common.c. Signed-off-by: Andrew Davis Reviewed-by: Tom Rini --- arch/arm/mach-omap2/boot-common.c | 16 ++++++++++++++++ board/ti/am335x/board.c | 9 --------- board/ti/am43xx/board.c | 17 ----------------- board/ti/am57xx/board.c | 17 ----------------- board/ti/dra7xx/evm.c | 17 ----------------- 5 files changed, 16 insertions(+), 60 deletions(-) diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index c463c96c74..f955d49471 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -331,3 +333,17 @@ void arch_preboot_os(void) ahci_reset((void __iomem *)DWC_AHSATA_BASE); } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(const void *fit, int node, void **p_image, + size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} + +static void tee_image_process(ulong tee_image, size_t tee_size) +{ + secure_tee_install((u32)tee_image); +} +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, tee_image_process); +#endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 9e58281611..ecb9fa02de 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include #include @@ -983,14 +982,6 @@ int board_fit_config_name_match(const char *name) } #endif -#ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(const void *fit, int node, void **p_image, - size_t *p_size) -{ - secure_boot_verify_image(p_image, p_size); -} -#endif - #if !CONFIG_IS_ENABLED(OF_CONTROL) static const struct omap_hsmmc_plat am335x_mmc0_plat = { .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index d0b7a14e0e..87e552a470 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include @@ -20,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -867,18 +865,3 @@ int embedded_dtb_select(void) return 0; } #endif - -#ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(const void *fit, int node, void **p_image, - size_t *p_size) -{ - secure_boot_verify_image(p_image, p_size); -} - -void board_tee_image_process(ulong tee_image, size_t tee_size) -{ - secure_tee_install((u32)tee_image); -} - -U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); -#endif diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 652c40f55c..0e57ee566b 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -22,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -1197,18 +1195,3 @@ static int board_bootmode_has_emmc(void) return 0; } #endif - -#ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(const void *fit, int node, void **p_image, - size_t *p_size) -{ - secure_boot_verify_image(p_image, p_size); -} - -void board_tee_image_process(ulong tee_image, size_t tee_size) -{ - secure_tee_install((u32)tee_image); -} - -U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); -#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 1c00e253ff..9cb7e21a9f 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -26,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -1063,18 +1061,3 @@ int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) return 0; } #endif - -#ifdef CONFIG_TI_SECURE_DEVICE -void board_fit_image_post_process(const void *fit, int node, void **p_image, - size_t *p_size) -{ - secure_boot_verify_image(p_image, p_size); -} - -void board_tee_image_process(ulong tee_image, size_t tee_size) -{ - secure_tee_install((u32)tee_image); -} - -U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); -#endif From 4c56d75117341103388f001818a0a1f8f6c449f1 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 20 Oct 2022 16:51:09 +0100 Subject: [PATCH 150/424] drivers: pci: pcie_dw_common: add upper-limit to iATU The 4.6 spec added an upper 32bits to the ATU limit, and since this driver is already assuming the unrolled feature added in the 4.8 specification this really should be set. This is causing a bug with testing against the QEMU model as it defaults the viewports to fully open and not setting this causes the config viewport to become most of memory (obviously stopping the emulated system working correctly) Signed-off-by: Ben Dooks --- drivers/pci/pcie_dw_common.c | 2 ++ drivers/pci/pcie_dw_common.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index e66fb1490a..9f8b016d11 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -73,6 +73,8 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index, upper_32_bits(cpu_addr)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, + upper_32_bits(cpu_addr + size - 1)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, lower_32_bits(pci_addr)); dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h index 6b701645af..e0f7796f2a 100644 --- a/drivers/pci/pcie_dw_common.h +++ b/drivers/pci/pcie_dw_common.h @@ -32,6 +32,7 @@ #define PCIE_ATU_UNR_LIMIT 0x10 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) From f723c2778cf883c5714aa942b4500846dc09f8f3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 28 Oct 2022 11:01:18 +0200 Subject: [PATCH 151/424] cmd: pxe: reorder kernel treatment in label_boot Reorder kernel treatment in label_boot at the beginning of the function. This patch doesn't change the pxe command behavior, it is only a preliminary step for next patch, build kernel_addr before parsing the label initrd and fdt to build the next bootm arguments. Signed-off-by: Patrick Delaunay Reviewed-by: Neil Armstrong --- boot/pxe_utils.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 8133006875..fc453bd539 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -521,6 +521,27 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) return 1; } + if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r", + NULL) < 0) { + printf("Skipping %s for failure retrieving kernel\n", + label->name); + return 1; + } + + kernel_addr = env_get("kernel_addr_r"); + /* for FIT, append the configuration identifier */ + if (label->config) { + int len = strlen(kernel_addr) + strlen(label->config) + 1; + + fit_addr = malloc(len); + if (!fit_addr) { + printf("malloc fail (FIT address)\n"); + return 1; + } + snprintf(fit_addr, len, "%s%s", kernel_addr, label->config); + kernel_addr = fit_addr; + } + if (label->initrd) { ulong size; @@ -528,21 +549,14 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) &size) < 0) { printf("Skipping %s for failure retrieving initrd\n", label->name); - return 1; + goto cleanup; } initrd_addr_str = env_get("ramdisk_addr_r"); size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx", initrd_addr_str, size); if (size >= sizeof(initrd_str)) - return 1; - } - - if (get_relfile_envaddr(ctx, label->kernel, "kernel_addr_r", - NULL) < 0) { - printf("Skipping %s for failure retrieving kernel\n", - label->name); - return 1; + goto cleanup; } if (label->ipappend & 0x1) { @@ -572,7 +586,7 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) strlen(label->append ?: ""), strlen(ip_str), strlen(mac_str), sizeof(bootargs)); - return 1; + goto cleanup; } if (label->append) @@ -587,21 +601,6 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) printf("append: %s\n", finalbootargs); } - kernel_addr = env_get("kernel_addr_r"); - - /* for FIT, append the configuration identifier */ - if (label->config) { - int len = strlen(kernel_addr) + strlen(label->config) + 1; - - fit_addr = malloc(len); - if (!fit_addr) { - printf("malloc fail (FIT address)\n"); - return 1; - } - snprintf(fit_addr, len, "%s%s", kernel_addr, label->config); - kernel_addr = fit_addr; - } - /* * fdt usage is optional: * It handles the following scenarios. From a5dacef7380e4414e7fe5831298e31122d24b18d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 28 Oct 2022 11:01:19 +0200 Subject: [PATCH 152/424] cmd: pxe: support INITRD and FDT selection with FIT Since the commit d5ba6188dfbf ("cmd: pxe_utils: Check fdtcontroladdr in label_boot") the FDT or the FDTDIR label is required in extlinux.conf and the fallback done by bootm command when only the device tree present in this command parameters is no more performed when FIT is used for kernel. When the label FDT or FDTDIR are absent or if the device tree file is absent, the PXE command in U-Boot uses the default U-Boot device tree selected by fdtcontroladdr = gd->fdt_blob, it is the "Scenario 3". With this scenario the bootm FIP fallback is no more possible with the extlinux.conf when only "kernel" label is present and is a FIP: kernel #[##[##[##[# Reviewed-by: Neil Armstrong --- boot/pxe_utils.c | 17 ++++++++++++++--- doc/README.pxe | 8 ++++++++ include/pxe_utils.h | 2 ++ 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index fc453bd539..b59e959f71 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -258,6 +258,7 @@ static struct pxe_label *label_create(void) static void label_destroy(struct pxe_label *label) { free(label->name); + free(label->kernel_label); free(label->kernel); free(label->config); free(label->append); @@ -542,9 +543,11 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) kernel_addr = fit_addr; } - if (label->initrd) { + /* For FIT, the label can be identical to kernel one */ + if (label->initrd && !strcmp(label->kernel_label, label->initrd)) { + initrd_addr_str = kernel_addr; + } else if (label->initrd) { ulong size; - if (get_relfile_envaddr(ctx, label->initrd, "ramdisk_addr_r", &size) < 0) { printf("Skipping %s for failure retrieving initrd\n", @@ -622,8 +625,11 @@ static int label_boot(struct pxe_context *ctx, struct pxe_label *label) */ bootm_argv[3] = env_get("fdt_addr_r"); + /* For FIT, the label can be identical to kernel one */ + if (label->fdt && !strcmp(label->kernel_label, label->fdt)) { + bootm_argv[3] = kernel_addr; /* if fdt label is defined then get fdt from server */ - if (bootm_argv[3]) { + } else if (bootm_argv[3]) { char *fdtfile = NULL; char *fdtfilefree = NULL; @@ -1164,6 +1170,11 @@ static int parse_label_kernel(char **c, struct pxe_label *label) if (err < 0) return err; + /* copy the kernel label to compare with FDT / INITRD when FIT is used */ + label->kernel_label = strdup(label->kernel); + if (!label->kernel_label) + return -ENOMEM; + s = strstr(label->kernel, "#"); if (!s) return 1; diff --git a/doc/README.pxe b/doc/README.pxe index d14d2bdcc9..172201093d 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -179,11 +179,19 @@ initrd - if this label is chosen, use tftp to retrieve the initrd at . it will be stored at the address indicated in the initrd_addr_r environment variable, and that address will be passed to bootm. + For FIT image, the initrd can be provided with the same value than + kernel, including configuration: + #[# - if this label is chosen, use tftp to retrieve the fdt blob at . it will be stored at the address indicated in the fdt_addr_r environment variable, and that address will be passed to bootm. + For FIT image, the device tree can be provided with the same value + than kernel, including configuration: + #[# - if this label is chosen, use tftp to retrieve the fdt blob at . it will be stored at the address indicated in diff --git a/include/pxe_utils.h b/include/pxe_utils.h index 4a73b2aace..1e5e8424f5 100644 --- a/include/pxe_utils.h +++ b/include/pxe_utils.h @@ -28,6 +28,7 @@ * Create these with the 'label_create' function given below. * * name - the name of the menu as given on the 'menu label' line. + * kernel_label - the kernel label, including FIT config if present. * kernel - the path to the kernel file to use for this label. * append - kernel command line to use when booting this label * initrd - path to the initrd to use for this label. @@ -40,6 +41,7 @@ struct pxe_label { char num[4]; char *name; char *menu; + char *kernel_label; char *kernel; char *config; char *append; From 51c5c28af59c19407d6602336ac7374dd1432c49 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Fri, 28 Oct 2022 11:01:20 +0200 Subject: [PATCH 153/424] cmd: pxe: use strdup to copy config Replace malloc and strcpy by strdup in function parse_label_kernel. Signed-off-by: Patrick Delaunay Reviewed-by: Neil Armstrong --- boot/pxe_utils.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index b59e959f71..c613818d0b 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -1179,11 +1179,10 @@ static int parse_label_kernel(char **c, struct pxe_label *label) if (!s) return 1; - label->config = malloc(strlen(s) + 1); + label->config = strdup(s); if (!label->config) return -ENOMEM; - strcpy(label->config, s); *s = 0; return 1; From 739e8361f3fe78038251216df6096a32bc2d5839 Mon Sep 17 00:00:00 2001 From: Manuel Traut Date: Fri, 18 Nov 2022 09:00:27 +0100 Subject: [PATCH 154/424] distro/pxeboot: Handle prompt variable Regarding the documentation found here: https://github.com/u-boot/u-boot/blob/master/common/menu.c#L347 If both timeout and prompt is set to 0 the default entry shall be booted immediately. However the current behaviour is that the prompt is shown (tested with distroboot) until the user selects an entry (no timeout). This change implements a behaviour as documented. It was tested with distroboot. Signed-off-by: Manuel Traut Reviewed-by: Simon Glass Reviewed-by: Simon Glass --- boot/pxe_utils.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index c613818d0b..2724313817 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -1368,7 +1368,10 @@ static int parse_pxefile_top(struct pxe_context *ctx, char *p, unsigned long bas break; case T_PROMPT: - eol_or_eof(&p); + err = parse_integer(&p, &cfg->prompt); + // Do not fail if prompt configuration is undefined + if (err < 0) + eol_or_eof(&p); break; case T_EOL: From 3419416a3a21bb95249052866c9a0d17e80dfb93 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Sat, 26 Nov 2022 23:30:09 +0100 Subject: [PATCH 155/424] omap4: make musb probeable by simple bus Like other peripherals important for booting, do not rely on ti-sysc compatibility alone Signed-off-by: Andreas Kemnade --- arch/arm/dts/omap4-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/omap4-u-boot.dtsi b/arch/arm/dts/omap4-u-boot.dtsi index 4a6bafd6ed..d476bfbc50 100644 --- a/arch/arm/dts/omap4-u-boot.dtsi +++ b/arch/arm/dts/omap4-u-boot.dtsi @@ -17,6 +17,14 @@ compatible = "simple-bus"; }; }; + + segment@80000 { + /* USB OTG */ + target-module@2b000 { + compatible = "simple-bus"; + }; + }; + }; &l4_per { From 5e6becefb0060d83590c4c386423f0e259974007 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Mon, 28 Nov 2022 10:32:43 +0800 Subject: [PATCH 156/424] ARM: config: enable function for nuvoton npcm845 bmc Signed-off-by: Jim Liu --- configs/arbel_evb_defconfig | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 447b97ef4a..aa857661d9 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x240000 CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0x1C0000 +CONFIG_ENV_OFFSET=0x3C0000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="nuvoton-npcm845-evb" @@ -13,7 +13,7 @@ CONFIG_SYS_PROMPT="U-Boot>" CONFIG_ARCH_NPCM8XX=y CONFIG_TARGET_ARBEL_EVB=y CONFIG_SYS_LOAD_ADDR=0x10000000 -CONFIG_ENV_ADDR=0x801C0000 +CONFIG_ENV_ADDR=0x803C0000 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTCOMMAND=y @@ -22,6 +22,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_BOOTM_LEN=0x1400000 CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -35,17 +37,25 @@ CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_NPCM_GPIO=y +CONFIG_DM_I2C=y # CONFIG_INPUT is not set +CONFIG_NPCM_HOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_NPCM=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_BROADCOM=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PHY_NPCM_USB=y CONFIG_PINCTRL=y CONFIG_PINCONF=y +CONFIG_PINCTRL_NPCM8XX=y CONFIG_DM_RESET=y CONFIG_RESET_SYSCON=y CONFIG_DM_SERIAL=y @@ -53,12 +63,15 @@ CONFIG_NPCM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_NPCM_FIU_SPI=y +CONFIG_NPCM_PSPI=y CONFIG_TIMER=y CONFIG_NPCM_TIMER=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_NPCM=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_OHCI_NPCM=y CONFIG_USB_STORAGE=y # CONFIG_EFI_LOADER is not set From 74bf4899b5fbb6eec43745bae4c9bda8784e3644 Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Mon, 28 Nov 2022 10:32:44 +0800 Subject: [PATCH 157/424] ARM: dts: npcm8xx: add npcm845 function node 1. add usb phy 2. add ehci ohci sdhci 3. add pinctrl node 4. add fiu node Signed-off-by: Jim Liu --- arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 92 + arch/arm/dts/nuvoton-npcm845-evb.dts | 129 ++ arch/arm/dts/nuvoton-npcm845-pincfg.dtsi | 2007 ++++++++++++++++++++++ arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 832 ++++++++- 4 files changed, 3052 insertions(+), 8 deletions(-) create mode 100644 arch/arm/dts/nuvoton-npcm845-pincfg.dtsi diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index aa7aac8c37..4538345dda 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -60,6 +61,70 @@ reg = <0x0 0xf0801000 0x0 0x1000>; }; + sdhci0: sdhci@f0842000 { + compatible = "nuvoton,npcm845-sdhci"; + reg = <0x0 0xf0842000 0x0 0x100>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_AHB>; + clock-names = "clk_mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc8_pins + &mmc_pins>; + status = "disabled"; + }; + + fiu0: spi@fb000000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfb000000 0x0 0x1000>, + <0x0 0x80000000 0x0 0x10000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPI0>; + clock-names = "clk_ahb"; + status = "disabled"; + }; + + fiu1: spi@fb002000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfb002000 0x0 0x1000>, + <0x0 0x90000000 0x0 0x4000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPI1>; + clock-names = "clk_spi1"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "disabled"; + }; + + fiu3: spi@c0000000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xc0000000 0x0 0x1000>, + <0x0 0xA0000000 0x0 0x20000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPI3>; + clock-names = "clk_spi3"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + status = "disabled"; + }; + + fiux: spi@fb001000 { + compatible = "nuvoton,npcm845-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xfb001000 0x0 0x1000>, + <0x0 0xf8000000 0x0 0x2000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM8XX_CLK_SPIX>; + clock-names = "clk_ahb"; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>; @@ -68,6 +133,19 @@ ranges = <0x0 0x0 0xf0000000 0x00300000>, <0xfff00000 0x0 0xfff00000 0x00016000>; + spi1: spi@201000 { + compatible = "nuvoton,npcm845-pspi"; + reg = <0x201000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_APB5>; + clock-names = "clk_apb5"; + status = "disabled"; + }; + timer0: timer@8000 { compatible = "nuvoton,npcm845-timer"; interrupts = ; @@ -165,6 +243,20 @@ clocks = <&clk NPCM8XX_CLK_REFCLK>; syscon = <&gcr>; }; + + i2c0: i2c@80000 { + compatible = "nuvoton,npcm845-i2c"; + reg = <0x80000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM8XX_CLK_APB2>; + clock-frequency = <100000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + syscon = <&gcr>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts index a5ab2bc0f8..53f4c6aeca 100644 --- a/arch/arm/dts/nuvoton-npcm845-evb.dts +++ b/arch/arm/dts/nuvoton-npcm845-evb.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "nuvoton-npcm845.dtsi" +#include "nuvoton-npcm845-pincfg.dtsi" / { model = "Nuvoton npcm845 Development Board (Device Tree)"; @@ -10,6 +11,15 @@ aliases { serial0 = &serial0; + i2c0 = &i2c0; + spi0 = &fiu0; + spi1 = &fiu1; + spi3 = &fiu3; + spi4 = &fiux; + spi5 = &spi1; + usb0 = &udc0; + usb1 = &ehci1; + usb2 = &ehci2; }; chosen { @@ -19,6 +29,31 @@ memory { reg = <0x0 0x0 0x0 0x40000000>; }; + + vsbr2: vsbr2 { + compatible = "regulator-npcm845"; + regulator-name = "vr2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vsbv8: vsbv8 { + compatible = "regulator-npcm845"; + regulator-name = "v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vsbv5: vsbv5 { + compatible = "regulator-npcm845"; + regulator-name = "v5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; &serial0 { @@ -28,3 +63,97 @@ &watchdog1 { status = "okay"; }; + +&fiu0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + spi_flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&fiu1 { + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + vqspi-supply = <&vsbv5>; + vqspi-microvolt = <3300000>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + }; +}; + +&fiux { + nuvoton,spix-mode; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usbphy3 { + status = "okay"; +}; + +&udc0 { + status = "okay"; + phys = <&usbphy1 0>; +}; + +&sdhci0 { + bus-width = <0x8>; + status = "okay"; +}; + +&ehci1 { + status = "okay"; + phys = <&usbphy2 3>; +}; + +&ehci2 { + status = "okay"; + phys = <&usbphy3 4>; +}; + +&i2c0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + &gspi_pins + &vgadig_pins + &spix_pins + &r1_pins + &r1en_pins + &r1oen_pins + >; +}; \ No newline at end of file diff --git a/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi b/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi new file mode 100644 index 0000000000..65de96b1f5 --- /dev/null +++ b/arch/arm/dts/nuvoton-npcm845-pincfg.dtsi @@ -0,0 +1,2007 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0o_pins: gpio0o-pins { + pins = "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"; + bias-disable; + output-high; + }; + gpio1_pins: gpio1-pins { + pins = "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"; + bias-disable; + input-enable; + }; + gpio2_pins: gpio2-pins { + pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"; + bias-disable; + input-enable; + }; + gpio2o_pins: gpio2o-pins { + pins = "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"; + bias-disable; + output_high; + }; + gpio3_pins: gpio3-pins { + pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"; + bias-disable; + input-enable; + }; + gpio3o_pins: gpio3o-pins { + pins = "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"; + bias-disable; + output-high; + }; + gpio4_pins: gpio4-pins { + pins = "GPIO4/IOX2_DI/SMB1D_SDA"; + bias-disable; + input-enable; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2_LD/SMB1D_SCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2_CK/SMB2D_SDA"; + bias-disable; + input-enable; + }; + gpio6o_pins: gpio6o-pins { + pins = "GPIO6/IOX2_CK/SMB2D_SDA"; + bias-disable; + output-high; + }; + gpio6ol_pins: gpio6ol-pins { + pins = "GPIO6/IOX2_CK/SMB2D_SDA"; + bias-disable; + output-low; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2_D0/SMB2D_SCL"; + bias-disable; + input-enable; + }; + gpio7o_pins: gpio7o-pins { + pins = "GPIO7/IOX2_D0/SMB2D_SCL"; + bias-disable; + output-high; + }; + gpio7ol_pins: gpio7ol-pins { + pins = "GPIO7/IOX2_D0/SMB2D_SCL"; + bias-disable; + output-low; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1/TP_GPIO0"; + bias-disable; + input-enable; + }; + gpio8ol_pins: gpio8ol-pins { + pins = "GPIO8/LKGPO1/TP_GPIO0"; + bias-disable; + output-low; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2/TP_GPIO1"; + bias-disable; + input-enable; + }; + gpio9o_pins: gpio9o-pins { + pins = "GPIO9/LKGPO2/TP_GPIO1"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2/TP_GPIO1"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"; + bias-disable; + input-enable; + }; + gpio10ol_pins: gpio10ol-pins { + pins = "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"; + bias-disable; + output-low; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"; + bias-disable; + input-enable; + }; + gpio11o_pins: gpio11o-pins { + pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"; + bias-disable; + output-high; + }; + gpio11ol_pins: gpio11ol-pins { + pins = "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"; + bias-disable; + output-low; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPI_CK/SMB5B_SCL"; + bias-disable; + input-enable; + }; + gpio12o_pins: gpio12o-pins { + pins = "GPIO12/GSPI_CK/SMB5B_SCL"; + bias-disable; + output-high; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPI_CK/SMB5B_SCL"; + bias-disable; + output-low; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPI_DO/SMB5B_SDA"; + bias-disable; + input-enable; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPI_DO/SMB5B_SDA"; + bias-disable; + output-low; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPI_DI/SMB5C_SCL"; + bias-disable; + input-enable; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPI_DI/SMB5C_SCL"; + bias-disable; + output-low; + }; + gpio15_pins: gpio15-pins { + pins = "GPIO15/GSPI_CS/SMB5C_SDA"; + bias-disable; + input-enable; + }; + gpio15o_pins: gpio15o-pins { + pins = "GPIO15/GSPI_CS/SMB5C_SDA"; + bias-disable; + output-high; + }; + gpio16_pins: gpio16-pins { + pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"; + bias-disable; + input-enable; + }; + gpio16o_pins: gpio16o-pins { + pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"; + bias-disable; + output-high; + }; + gpio16ol_pins: gpio16ol-pins { + pins = "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"; + bias-disable; + output-low; + }; + gpio17_pins: gpio17-pins { + pins = "GPIO17/PSPI_DI/CP1_GPIO5"; + bias-disable; + input-enable; + }; + gpio17o_pins: gpio17o-pins { + pins = "GPIO17/PSPI_DI/CP1_GPIO5"; + bias-disable; + output-high; + }; + gpio17ol_pins: gpio17ol-pins { + pins = "GPIO17/PSPI_DI/CP1_GPIO5"; + bias-disable; + output-low; + }; + gpio18_pins: gpio18-pins { + pins = "GPIO18/PSPI_D0/SMB4B_SDA"; + bias-disable; + input-enable; + }; + gpio18ol_pins: gpio18ol-pins { + pins = "GPIO18/PSPI_D0/SMB4B_SDA"; + bias-disable; + output-low; + }; + gpio19_pins: gpio19-pins { + pins = "GPIO19/PSPI_CK/SMB4B_SCL"; + bias-disable; + input-enable; + }; + gpio19ol_pins: gpio19ol-pins { + pins = "GPIO19/PSPI_CK/SMB4B_SCL"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"; + bias-disable; + input-enable; + }; + gpio20o_pins: gpio20o-pins { + pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"; + bias-disable; + output-high; + }; + gpio20ol_pins: gpio20ol-pins { + pins = "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"; + bias-disable; + output-low; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"; + bias-disable; + input-enable; + }; + gpio21ol_pins: gpio21ol-pins { + pins = "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"; + bias-disable; + output-low; + }; + gpio22_pins: gpio22-pins { + pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"; + bias-disable; + input-enable; + }; + gpio22ol_pins: gpio22ol-pins { + pins = "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"; + bias-disable; + output-low; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"; + bias-disable; + input-enable; + }; + gpio23ol_pins: gpio23ol-pins { + pins = "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"; + bias-disable; + output-low; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"; + bias-disable; + input-enable; + }; + gpio24o_pins: gpio24o-pins { + pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"; + bias-disable; + output-high; + }; + gpio24ol_pins: gpio24ol-pins { + pins = "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"; + bias-disable; + output-low; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"; + bias-disable; + input-enable; + }; + gpio25o_pins: gpio25o-pins { + pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"; + bias-disable; + output-high; + }; + gpio25ol_pins: gpio25ol-pins { + pins = "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"; + bias-disable; + output-low; + }; + gpio26_pins: gpio26-pins { + pins = "GPIO26/SMB5_SDA"; + bias-disable; + input-enable; + }; + gpio27_pins: gpio27-pins { + pins = "GPIO27/SMB5_SCL"; + bias-disable; + input-enable; + }; + gpio32_pins: gpio32-pins { + pins = "GPIO32/SMB14_SCL/SPI0_nCS1"; + bias-disable; + input-enable; + }; + gpio32o_pins: gpio32o-pins { + pins = "GPIO32/SMB14_SCL/SPI0_nCS1"; + bias-disable; + output-high; + }; + gpio32ol_pins: gpio32ol-pins { + pins = "GPIO32/SMB14_SCL/SPI0_nCS1"; + bias-disable; + output-low; + }; + gpio37_pins: gpio37-pins { + pins = "GPIO37/SMB3C_SDA/SMB23_SDA"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3C_SDA/SMB23_SDA"; + bias-disable; + output-high; + }; + gpio37ol_pins: gpio37ol-pins { + pins = "GPIO37/SMB3C_SDA/SMB23_SDA"; + bias-disable; + output-low; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3C_SCL/SMB23_SCL"; + bias-disable; + input-enable; + }; + gpio38o_pins: gpio38o-pins { + pins = "GPIO38/SMB3C_SCL/SMB23_SCL"; + bias-disable; + output-high; + }; + gpio38ol_pins: gpio38ol-pins { + pins = "GPIO38/SMB3C_SCL/SMB23_SCL"; + bias-disable; + output-low; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3B_SDA/SMB22_SDA"; + bias-disable; + input-enable; + }; + gpio39o_pins: gpio39o-pins { + pins = "GPIO39/SMB3B_SDA/SMB22_SDA"; + bias-disable; + output-high; + }; + gpio39ol_pins: gpio39ol-pins { + pins = "GPIO39/SMB3B_SDA/SMB22_SDA"; + bias-disable; + output-low; + }; + gpio40_pins: gpio40-pins { + pins = "GPIO40/SMB3B_SCL/SMB22_SCL"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3B_SCL/SMB22_SCL"; + bias-disable; + output-high; + }; + gpio40ol_pins: gpio40ol-pins { + pins = "GPIO40/SMB3B_SCL/SMB22_SCL"; + bias-disable; + output-low; + }; + gpio41_pins: gpio41-pins { + pins = "GPIO41/BU0_RXD/CP1U_RXD"; + input-enable; + }; + gpio42_pins: gpio42-pins { + pins = "GPIO42/BU0_TXD/CP1U_TXD"; + bias-disable; + input-enable; + }; + gpio43_pins: gpio43-pins { + pins = "GPIO43/SI1_RXD/BU1_RXD"; + bias-disable; + input-enable; + }; + gpio44_pins: gpio44-pins { + pins = "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"; + bias-disable; + input-enable; + }; + gpio45_pins: gpio45-pins { + pins = "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"; + bias-disable; + input-enable; + }; + gpio46_pins: gpio46-pins { + pins = "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"; + bias-disable; + input-enable; + }; + gpio47_pins: gpio47-pins { + pins = "GPIO47/SI1n_RI1"; + bias-disable; + input-enable; + }; + gpio48_pins: gpio48-pins { + pins = "GPIO48/SI2_TXD/BU0_TXD/STRAP5"; + bias-disable; + input-enable; + }; + gpio49_pins: gpio49-pins { + pins = "GPIO49/SI2_RXD/BU0_RXD"; + bias-disable; + input-enable; + }; + gpio50_pins: gpio50-pins { + pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"; + bias-disable; + input-enable; + }; + gpio50ol_pins: gpio50ol-pins { + pins = "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"; + bias-disable; + output-low; + }; + gpio51_pins: gpio51-pins { + pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"; + bias-disable; + input-enable; + }; + gpio51o_pins: gpio51o-pins { + pins = "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"; + bias-disable; + output-high; + }; + gpio52_pins: gpio52-pins { + pins = "GPIO52/SI2_nDCD/BU5_RXD"; + bias-disable; + input-enable; + }; + gpio52ol_pins: gpio52ol-pins { + pins = "GPIO52/SI2_nDCD/BU5_RXD"; + bias-disable; + output-low; + }; + gpio53_pins: gpio53-pins { + pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"; + bias-disable; + input-enable; + }; + gpio53o_pins: gpio53o-pins { + pins = "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"; + bias-disable; + output-high; + }; + gpio54_pins: gpio54-pins { + pins = "GPIO54/SI2_nDSR/BU4_TXD"; + bias-disable; + input-enable; + }; + gpio54ol_pins: gpio54ol-pins { + pins = "GPIO54/SI2_nDSR/BU4_TXD"; + bias-disable; + output-low; + }; + gpio55_pins: gpio55-pins { + pins = "GPIO55/SI2_RI2/BU4_RXD"; + bias-disable; + input-enable; + }; + gpio55ol_pins: gpio55ol-pins { + pins = "GPIO55/SI2_RI2/BU4_RXD"; + bias-disable; + output-low; + }; + gpio56_pins: gpio56-pins { + pins = "GPIO56/R1_RXERR/R1_OEN"; + bias-disable; + input-enable; + }; + gpio57_pins: gpio57-pins { + pins = "GPIO57/R1_MDC/TP_GPIO4"; + bias-disable; + input-enable; + }; + gpio57ol_pins: gpio57ol-pins { + pins = "GPIO57/R1_MDC/TP_GPIO4"; + bias-disable; + output-low; + }; + gpio58_pins: gpio58-pins { + pins = "GPIO58/R1_MDIO/TP_GPIO5"; + bias-disable; + input-enable; + }; + gpio58ol_pins: gpio58ol-pins { + pins = "GPIO58/R1_MDIO/TP_GPIO5"; + bias-disable; + output-low; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"; + bias-disable; + input-enable; + }; + gpio59o_pins: gpio59o-pins { + pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"; + bias-disable; + output-high; + }; + gpio59ol_pins: gpio59ol-pins { + pins = "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"; + bias-disable; + output-low; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"; + bias-disable; + input-enable; + }; + gpio60o_pins: gpio60o-pins { + pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"; + bias-disable; + output-high; + }; + gpio60ol_pins: gpio60ol-pins { + pins = "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"; + bias-disable; + output-low; + }; + gpio61_pins: gpio61-pins { + pins = "GPIO61/SI1_nDTR_BOUT"; + bias-disable; + input-enable; + }; + gpio61o_pins: gpio61o-pins { + pins = "GPIO61/SI1_nDTR_BOUT"; + bias-disable; + output-high; + }; + gpio62_pins: gpio62-pins { + pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"; + bias-disable; + input-enable; + }; + gpio62o_pins: gpio62o-pins { + pins = "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"; + bias-disable; + output-high; + }; + gpio63_pins: gpio63-pins { + pins = "GPIO63/BU1_TXD1/SI1_TXD"; + bias-disable; + input-enable; + }; + gpio63o_pins: gpio63o-pins { + pins = "GPIO63/BU1_TXD1/SI1_TXD"; + bias-disable; + output-high; + }; + gpio64_pins: gpio64-pins { + pins = "GPIO64/FANIN0"; + bias-disable; + input-enable; + }; + gpio64o_pins: gpio64o-pins { + pins = "GPIO64/FANIN0"; + bias-disable; + output-high; + }; + gpio65_pins: gpio65-pins { + pins = "GPIO65/FANIN1"; + bias-disable; + input-enable; + }; + gpio66_pins: gpio66-pins { + pins = "GPIO66/FANIN2"; + bias-disable; + input-enable; + }; + gpio67_pins: gpio67-pins { + pins = "GPIO67/FANIN3"; + bias-disable; + input-enable; + }; + gpio68_pins: gpio68-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + input-enable; + }; + gpio68o_pins: gpio68o-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + output-high; + }; + gpio69_pins: gpio69-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + input-enable; + }; + gpio69o_pins: gpio69o-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + output-high; + }; + gpio69ol_pins: gpio69ol-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + output-low; + }; + gpio70_pins: gpio70-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + input-enable; + }; + gpio70o_pins: gpio70o-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + output-high; + }; + gpio71_pins: gpio71-pins { + pins = "GPIO71/FANIN7"; + bias-disable; + input-enable; + }; + gpio72_pins: gpio72-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + input-enable; + }; + gpio72ol_pins: gpio72ol-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + output-low; + }; + gpio73_pins: gpio73-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + input-enable; + }; + gpio73ol_pins: gpio73ol-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + output-low; + }; + gpio74_pins: gpio74-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + input-enable; + }; + gpio74ol_pins: gpio74ol-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + output-low; + }; + gpio75_pins: gpio75-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + input-enable; + }; + gpio75ol_pins: gpio75ol-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + output-low; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio76ol_pins: gpio76ol-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + output-low; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio77ol_pins: gpio77ol-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + output-low; + }; + gpio78_pins: gpio78-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + input-enable; + }; + gpio78ol_pins: gpio78ol-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-low; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio79ol_pins: gpio79ol-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + output-low; + }; + gpio80_pins: gpio80-pins { + pins = "GPIO80/PWM0"; + bias-disable; + input-enable; + }; + gpio81_pins: gpio81-pins { + pins = "GPIO81/PWM1"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2_TXD0"; + bias-disable; + input-enable; + }; + gpio84o_pins: gpio84ol-pins { + pins = "GPIO84/R2_TXD0"; + bias-disable; + output-high; + }; + gpio85_pins: gpio85-pins { + pins = "GPIO85/R2_TXD1"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2_TXD1"; + bias-disable; + output-high; + }; + gpio86_pins: gpio86-pins { + pins = "GPIO86/R2_TXEN"; + bias-disable; + input-enable; + }; + gpio86o_pins: gpio86o-pins { + pins = "GPIO86/R2_TXEN"; + bias-disable; + output-high; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2_RXD0"; + bias-disable; + input-enable; + }; + gpio87o_pins: gpio87o-pins { + pins = "GPIO87/R2_RXD0"; + bias-disable; + output-high; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2_RXD1"; + bias-disable; + input-enable; + }; + gpio88ol_pins: gpio88ol-pins { + pins = "GPIO88/R2_RXD1"; + bias-disable; + output-low; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2_CRSDV"; + bias-disable; + input-enable; + }; + gpio89ol_pins: gpio89ol-pins { + pins = "GPIO89/R2_CRSDV"; + bias-disable; + output-low; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2_RXERR/R2_OEN"; + bias-disable; + input-enable; + }; + gpio90o_pins: gpio90o0-pins { + pins = "GPIO90/R2_RXERR/R2_OEN"; + bias-disable; + output-high; + }; + gpio90ol_pins: gpio90ol-pins { + pins = "GPIO90/R2_RXERR/R2_OEN"; + bias-disable; + output-low; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"; + bias-disable; + input-enable; + }; + gpio91o_pins: gpio91o-pins { + pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"; + bias-disable; + output-high; + }; + gpio91ol_pins: gpio91ol-pins { + pins = "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"; + bias-disable; + output-low; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + input-enable; + }; + gpio92o_pins: gpio92o-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + output-high; + }; + gpio92ol_pins: gpio92ol-pins { + pins = "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"; + bias-disable; + output-low; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5D_SCL"; + bias-disable; + input-enable; + }; + gpio93o_pins: gpio93o-pins { + pins = "GPIO93/GA20/SMB5D_SCL"; + bias-disable; + output-high; + }; + gpio93ol_pins: gpio93ol-pins { + pins = "GPIO93/GA20/SMB5D_SCL"; + bias-disable; + output-low; + }; + gpio94_pins: gpio94-pins { + pins = "GPIO94/nKBRST/SMB5D_SDA"; + bias-disable; + input-enable; + }; + gpio94o_pins: gpio94o-pins { + pins = "GPIO94/nKBRST/SMB5D_SDA"; + bias-disable; + output-high; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nESPIRST/LPC_nLRESET"; + bias-disable; + input-enable; + }; + gpio96_pins: gpio96-pins { + pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"; + bias-disable; + input-enable; + }; + gpio96ol_pins: gpio96ol-pins { + pins = "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"; + bias-disable; + output-low; + }; + gpio97_pins: gpio97-pins { + pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"; + bias-disable; + input-enable; + }; + gpio97ol_pins: gpio97ol-pins { + pins = "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"; + bias-disable; + output-low; + }; + gpio98_pins: gpio98-pins { + pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"; + bias-disable; + input-enable; + }; + gpio98o_pins: gpio98o-pins { + pins = "GPIO98/RG1TXD2"; + bias-disable; + output-high; + }; + gpio98ol_pins: gpio98ol-pins { + pins = "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"; + bias-disable; + output-low; + }; + gpio99_pins: gpio99-pins { + pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"; + bias-disable; + input-enable; + }; + gpio99o_pins: gpio99o-pins { + pins = "GPIO99/RG1TXD3"; + bias-disable; + output-high; + }; + gpio99ol_pins: gpio99ol-pins { + pins = "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"; + bias-disable; + output-low; + }; + gpio100_pins: gpio100-pins { + pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"; + bias-disable; + input-enable; + }; + gpio100ol_pins: gpio100ol-pins { + pins = "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"; + bias-disable; + output-low; + }; + gpio101_pins: gpio101-pins { + pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"; + bias-disable; + input-enable; + }; + gpio101ol_pins: gpio101ol-pins { + pins = "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"; + bias-disable; + output-low; + }; + gpio102_pins: gpio102-pins { + pins = "GPIO102/HSYNC"; + bias-disable; + input-enable; + }; + gpio102ol_pins: gpio102ol-pins { + pins = "GPIO102/HSYNC"; + bias-disable; + output-low; + }; + gpio103_pins: gpio103-pins { + pins = "GPIO103/VSYNC"; + bias-disable; + input-enable; + }; + gpio103ol_pins: gpio103ol-pins { + pins = "GPIO103/VSYNC"; + bias-disable; + output-low; + }; + gpio104_pins: gpio104-pins { + pins = "GPIO104/DDC_SCL"; + bias-disable; + input-enable; + }; + gpio104ol_pins: gpio104ol-pins { + pins = "GPIO104/DDC_SCL"; + bias-disable; + output-low; + }; + gpio105_pins: gpio105-pins { + pins = "GPIO105/DDC_SDA"; + bias-disable; + input-enable; + }; + gpio105ol_pins: gpio105ol-pins { + pins = "GPIO105/DDC_SDA"; + bias-disable; + output-low; + }; + gpio106_pins: gpio106-pins { + pins = "GPIO106/I3C5_SCL"; + bias-disable; + input-enable; + }; + gpio106ol_pins: gpio106ol-pins { + pins = "GPIO106/I3C5_SCL"; + bias-disable; + output-low; + }; + gpio107_pins: gpio107-pins { + pins = "GPIO107/I3C5_SDA"; + bias-disable; + input-enable; + }; + gpio107ol_pins: gpio107ol-pins { + pins = "GPIO107/I3C5_SDA"; + bias-disable; + output-low; + }; + gpio108_pins: gpio108-pins { + pins = "GPIO108/SG1_MDC"; + bias-disable; + input-enable; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/SG1_MDC"; + bias-disable; + output-low; + }; + gpio109_pins: gpio109-pins { + pins = "GPIO109/SG1_MDIO"; + bias-disable; + input-enable; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/SG1_MDIO"; + bias-disable; + output-low; + }; + gpio110_pins: gpio110-pins { + pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"; + bias-disable; + input-enable; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"; + bias-disable; + output-low; + }; + gpio111_pins: gpio111-pins { + pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"; + bias-disable; + input-enable; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"; + bias-disable; + output-low; + }; + gpio112_pins: gpio112-pins { + pins = "GPIO112/RG2_TXD2/DDRV2"; + bias-disable; + input-enable; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2_TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113_pins: gpio113-pins { + pins = "GPIO113/RG2_TXD3/DDRV3"; + bias-disable; + input-enable; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2_TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio118_pins: gpio118-pins { + pins = "GPIO118/SMB2_SCL"; + bias-disable; + input-enable; + }; + gpio119_pins: gpio119-pins { + pins = "GPIO119/SMB2_SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2C_SDA"; + bias-disable; + input-enable; + }; + gpio120ol_pins: gpio120ol-pins { + pins = "GPIO120/SMB2C_SDA"; + bias-disable; + output-low; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2C_SCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2B_SDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2B_SCL"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2B_SCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1C_SDA/CP1_GPIO3"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1C_SCL/CP1_GPIO2"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1B_SDA/CP1_GPIO1"; + bias-disable; + input-enable; + }; + gpio127_pins: gpio127-pins { + pins = "GPIO127/SMB1B_SCL/CP1_GPIO0"; + bias-disable; + input-enable; + }; + gpio128o_pins: gpio128o-pins { + pins = "GPIO128/SMB824_SCL"; + bias-disable; + output-high; + }; + gpio130_pins: gpio130-pins { + pins = "GPIO130/SMB925_SCL"; + bias-disable; + input-enable; + }; + gpio131_pins: gpio131-pins { + pins = "GPIO131/SMB925_SDA"; + bias-disable; + input-enable; + }; + gpio132_pins: gpio132-pins { + pins = "GPIO132/SMB1026_SCL"; + bias-disable; + input-enable; + }; + gpio133_pins: gpio133-pins { + pins = "GPIO133/SMB1026_SDA"; + bias-disable; + input-enable; + }; + gpio134_pins: gpio134-pins { + pins = "GPIO134/SMB11_SCL"; + bias-disable; + input-enable; + }; + gpio135_pins: gpio135-pins { + pins = "GPIO135/SMB11_SDA"; + bias-disable; + input-enable; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/JM1_TCK"; + bias-disable; + input-enable; + }; + gpio136o_pins: gpio136o-pins { + pins = "GPIO136/JM1_TCK"; + bias-disable; + output-high; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/JM1_TDO"; + bias-disable; + input-enable; + }; + gpio137o_pins: gpio137o-pins { + pins = "GPIO137/JM1_TDO"; + bias-disable; + output-high; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/JM1_TMS"; + bias-disable; + input-enable; + }; + gpio138o_pins: gpio138o-pins { + pins = "GPIO138/JM1_TMS"; + bias-disable; + output-high; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/JM1_TDI"; + bias-disable; + input-enable; + }; + gpio139o_pins: gpio139o-pins { + pins = "GPIO139/JM1_TDI"; + bias-disable; + output-high; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/JM1_nTRST"; + bias-disable; + input-enable; + }; + gpio140o_pins: gpio140o-pins { + pins = "GPIO140/JM1_nTRST"; + bias-disable; + output-high; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SMB7B_SCL"; + bias-disable; + input-enable; + }; + gpio141o_pins: gpio141o-pins { + pins = "GPIO141/SMB7B_SCL"; + bias-disable; + output-high; + }; + gpio141ol_pins: gpio141ol-pins { + pins = "GPIO141/SMB7B_SCL"; + bias-disable; + output-low; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL"; + bias-disable; + input-enable; + }; + gpio142o_pins: gpio142o-pins { + pins = "GPIO142/SMB7D_SCL/TPSMB1_SCL"; + bias-disable; + output-high; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA"; + bias-disable; + input-enable; + }; + gpio143o_pins: gpio143o-pins { + pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA"; + bias-disable; + output-high; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SMB7D_SDA/TPSMB1_SDA"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMC_DT4"; + bias-disable; + input-enable; + }; + gpio148o_pins: gpio148o-pins { + pins = "GPIO148/MMC_DT4"; + bias-disable; + output-high; + }; + gpio148ol_pins: gpio148ol_pins { + pins = "GPIO148/MMC_DT4"; + bias-disable; + output-low; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMC_DT5"; + bias-disable; + input-enable; + }; + gpio149o_pins: gpio149o-pins { + pins = "GPIO149/MMC_DT5"; + bias-disable; + output-high; + }; + gpio149ol_pins: gpio149ol-pins { + pins = "GPIO149/MMC_DT5"; + bias-disable; + output-low; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMC_DT6"; + bias-disable; + input-enable; + }; + gpio150o_pins: gpio150o-pins { + pins = "GPIO150/MMC_DT6"; + bias-disable; + output-high; + }; + gpio150ol_pins: gpio150ol-pins { + pins = "GPIO150/MMC_DT6"; + bias-disable; + output-low; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMC_DT7"; + bias-disable; + input-enable; + }; + gpio151o_pins: gpio151o-pins { + pins = "GPIO151/MMC_DT7"; + bias-disable; + output-high; + }; + gpio151ol_pins: gpio151ol-pins { + pins = "GPIO151/MMC_DT7"; + bias-disable; + output-low; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMC_CLK"; + bias-disable; + input-enable; + }; + gpio152o_pins: gpio152o-pins { + pins = "GPIO152/MMC_CLK"; + bias-disable; + output-high; + }; + gpio152ol_pins: gpio152ol-pins { + pins = "GPIO152/MMC_CLK"; + bias-disable; + output-low; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMC_WP"; + bias-disable; + input-enable; + }; + gpio153ol_pins: gpio153ol-pins { + pins = "GPIO153/MMC_WP"; + bias-disable; + output-low; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMC_CMD"; + bias-disable; + input-enable; + }; + gpio154ol_pins: gpio154ol-pins { + pins = "GPIO154/MMC_CMD"; + bias-disable; + output-low; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/MMC_nCD/MMC_nRSTLK"; + bias-disable; + input-enable; + }; + gpio155ol_pins: gpio155ol-pins { + pins = "GPIO155/MMC_nCD/MMC_nRSTLK"; + bias-disable; + output-low; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMC_DT0"; + bias-disable; + input-enable; + }; + gpio156ol_pins: gpio156ol-pins { + pins = "GPIO156/MMC_DT0"; + bias-disable; + output-low; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMC_DT1"; + bias-disable; + input-enable; + }; + gpio157o_pins: gpio157o-pins { + pins = "GPIO157/MMC_DT1"; + bias-disable; + output-high; + }; + gpio157ol_pins: gpio157ol-pins { + pins = "GPIO157/MMC_DT1"; + bias-disable; + output-low; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMC_DT2"; + bias-disable; + input-enable; + }; + gpio158o_pins: gpio158o-pins { + pins = "GPIO158/MMC_DT2"; + bias-disable; + output-high; + }; + gpio158ol_pins: gpio158ol-pins { + pins = "GPIO158/MMC_DT2"; + bias-disable; + output-low; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + input-enable; + }; + gpio159o_pins: gpio159o-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + output-high; + }; + gpio159ol_pins: gpio159ol-pins { + pins = "GPIO159/MMC_DT3"; + bias-disable; + output-low; + }; + gpio160_pins: gpio160-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"; + bias-disable; + output-high; + }; + gpio160ol_pins: gpio160ol-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"; + bias-disable; + output-low; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/ESPI_nCS/LPC_nLFRAME"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/LPC_nCLKRUN"; + bias-disable; + input-enable; + }; + gpio162o_pins: gpio162o-pins { + pins = "GPIO162/LPC_nCLKRUN"; + bias-disable; + output-high; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/ESPI_CK/LPC_LCLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/ESPI_IO0/LPC_LAD0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/ESPI_IO1/LPC_LAD1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/ESPI_IO2/LPC_LAD2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/ESPI_IO3/LPC_LAD3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/ESPI_nALERT/SERIRQ"; + bias-disable; + input-enable; + drive-open-drain; + }; + gpio168ol_pins: gpio168ol-pins { + pins = "GPIO168/ESPI_nALERT/SERIRQ"; + bias-disable; + output-low; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME/SMB21_SCL"; + bias-disable; + input-enable; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME/SMB21_SCL"; + bias-disable; + output-high; + }; + gpio169ol_pins: gpio169ol-pins { + pins = "GPIO169/nSCIPME/SMB21_SCL"; + bias-disable; + output-low; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI/SMB21_SDA"; + bias-disable; + input-enable; + }; + gpio170ol_pins: gpio170ol-pins { + pins = "GPIO170/nSMI/SMB21_SDA"; + bias-disable; + output-low; + }; + gpio173o_pins: gpio173o-pins { + pins = "GPIO173/SMB7_SCL"; + bias-disable; + output-high; + }; + gpio173ol_pins: gpio173ol-pins { + pins = "GPIO173/SMB7_SCL"; + bias-disable; + output-low; + }; + gpio174_pins: gpio174-pins { + pins = "GPIO174/SMB7_SDA"; + bias-disable; + input-enable; + }; + gpio175_pins: gpio175-pins { + pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK"; + bias-disable; + input-enable; + }; + gpio175o_pins: gpio175o-pins { + pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK"; + bias-disable; + output-high; + }; + gpio175ol_pins: gpio175ol-pins { + pins = "GPIO175/SPI1_CK/FANIN19/FM1_CK"; + bias-disable; + output-low; + }; + gpio176_pins: gpio176-pins { + pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"; + bias-disable; + input-enable; + }; + gpio176o_pins: gpio176o-pins { + pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"; + bias-disable; + output-high; + }; + gpio176ol_pins: gpio176ol-pins { + pins = "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"; + bias-disable; + output-low; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"; + bias-disable; + input-enable; + }; + gpio177o_pins: gpio177o-pins { + pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-high; + }; + gpio177ol_pins: gpio177ol-pins { + pins = "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-low; + }; + gpio187_pins: gpio187-pins { + pins = "GPIO187/SPI3_nCS1_SMB14_SDA"; + bias-disable; + input-enable; + }; + gpio187o_pins: gpio187o-pins { + pins = "GPIO187/SPI3_nCS1_SMB14_SDA"; + bias-disable; + output-high; + }; + gpio187ol_pins: gpio187ol-pins { + pins = "GPIO187/SPI3_nCS1_SMB14_SDA"; + bias-disable; + output-low; + }; + gpio188_pins: gpio188-pins { + pins = "GPIO188/SPI3_D2/SPI3_nCS2"; + bias-disable; + input-enable; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3_D2/SPI3_nCS2"; + bias-disable; + output-high; + }; + gpio189o_pins: gpio189o-pins { + pins = "GPIO189/SPI3_D3/SPI3_nCS3"; + bias-disable; + output-high; + }; + gpio190_pins: gpio190-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + input-enable; + }; + gpio190o_pins: gpio190o-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-high; + }; + gpio190ol_pins: gpio190ol-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-low; + }; + gpio191o_pins: gpio191o-pins { + pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-high; + }; + gpio191ol_pins: gpio191ol-pins { + pins = "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"; + bias-disable; + output-low; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"; + bias-disable; + input-enable; + }; + gpio192o_pins: gpio192o-pins { + pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"; + bias-disable; + output-high; + }; + gpio192ol_pins: gpio192ol-pins { + pins = "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"; + bias-disable; + output-low; + }; + gpio194_pins: gpio194-pins { + pins = "GPIO194/SMB0B_SCL/FM0_CK"; + bias-disable; + input-enable; + }; + gpio194o_pins: gpio194o-pins { + pins = "GPIO194/SMB0B_SCL/FM0_CK"; + bias-disable; + output-high; + }; + gpio195_pins: gpio195-pins { + pins = "GPIO195/SMB0B_SDA/FM0_D0"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0C_SCL/FM0_D1"; + bias-disable; + input-enable; + }; + gpio196o_pins: gpio196o-pins { + pins = "GPIO196/SMB0C_SCL/FM0_D1"; + bias-disable; + output-high; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN/FM0_D3"; + bias-disable; + input-enable; + }; + gpio197o_pins: gpio197o-pins { + pins = "GPIO197/SMB0DEN/FM0_D3"; + bias-disable; + output-high; + }; + gpio197ol_pins: gpio197ol-pins { + pins = "GPIO197/SMB0DEN/FM0_D3"; + bias-disable; + output-low; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0D_SDA/FM0_D2"; + bias-disable; + output-high; + }; + gpio198ol_pins: gpio198ol-pins { + pins = "GPIO198/SMB0D_SDA/FM0_D2"; + bias-disable; + output-low; + }; + gpio199_pins: gpio199-pins { + pins = "GPIO199/SMB0D_SCL/FM0_CSO"; + bias-disable; + input-enable; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2_CK"; + input-enable; + bias-disable; + }; + gpio200ol_pins: gpio200ol-pins { + pins = "GPIO200/R2_CK"; + bias-disable; + output-low; + }; + gpio201ol_pins: gpio201ol-pins { + pins = "GPIO201/R1_CK"; + bias-disable; + output-low; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0C_SDA/FM0_CSI"; + bias-disable; + input-enable; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"; + bias-disable; + output-high; + }; + gpio203ol_pins: gpio203ol-pins { + pins = "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"; + bias-disable; + output-low; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2_TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio208o_pins: gpio208o-pins { + pins = "GPIO208/RG2_TXC/DVCK"; + bias-disable; + output-high; + }; + gpio208ol_pins: gpio208ol-pins { + pins = "GPIO208/RG2_TXC/DVCK"; + bias-disable; + output-low; + }; + gpio209_pins: gpio209-pins { + pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"; + bias-disable; + output-low; + }; + gpio210_pins: gpio210-pins { + pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"; + bias-disable; + input-enable; + }; + gpio210o_pins: gpio210o-pins { + pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"; + bias-disable; + output-high; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"; + bias-disable; + output-low; + }; + gpio211_pins: gpio211-pins { + pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"; + bias-disable; + input-enable; + }; + gpio211o_pins: gpio211o-pins { + pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"; + bias-disable; + output-high; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"; + bias-disable; + output-low; + }; + gpio212_pins: gpio212-pins { + pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"; + bias-disable; + input-enable; + }; + gpio212o_pins: gpio212o-pins { + pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"; + bias-disable; + output-high; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"; + bias-disable; + output-low; + }; + gpio213_pins: gpio213-pins { + pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN"; + bias-disable; + input-enable; + }; + gpio213o_pins: gpio213o-pins { + pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN"; + bias-disable; + output-high; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2_RXD3/DDRV8/R3_OEN"; + bias-disable; + output-low; + }; + gpio214_pins: gpio214-pins { + pins = "GPIO214/RG2_RXC/DDRV9/R3_CK"; + bias-disable; + input-enable; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2_RXC/DDRV9/R3_CK"; + bias-disable; + output-low; + }; + gpio215_pins: gpio215-pins { + pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"; + bias-disable; + input-enable; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"; + bias-disable; + output-low; + }; + gpio216_pins: gpio216-pins { + pins = "GPIO216/RG2_MDC/DDRV11"; + bias-disable; + input-enable; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2_MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217_pins: gpio217-pins { + pins = "GPIO217/RG2_MDIO/DVHSYNC"; + bias-disable; + input-enable; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2_MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio218_pins: gpio218-pins { + pins = "GPIO218/nWDO1/SMB16_SCL"; + bias-disable; + input-enable; + }; + gpio218ol_pins: gpio218ol-pins { + pins = "GPIO218/nWDO1/SMB16_SCL"; + bias-disable; + output-low; + }; + gpio219_pins: gpio219-pins { + pins = "GPIO219/nWDO2/SMB16_SDA"; + bias-disable; + input-enable; + }; + gpio219ol_pins: gpio219ol-pins { + pins = "GPIO219/nWDO2/SMB16_SDA"; + bias-disable; + output-low; + }; + gpio220ol_pins: gpio220ol-pins { + pins = "GPIO220/SMB12_SCL/PWM8"; + bias-disable; + output-low; + }; + gpio221o_pins: gpio221o-pins { + pins = "GPIO221/SMB12_SDA/PWM9"; + bias-disable; + output-high; + }; + gpio222_pins: gpio222-pins { + pins = "GPIO222/SMB13_SCL"; + bias-disable; + input-enable; + }; + gpio222o_pins: gpio222o-pins { + pins = "GPIO222/SMB13_SCL"; + bias-disable; + output-high; + }; + gpio223_pins: gpio223-pins { + pins = "GPIO223/SMB13_SDA"; + bias-disable; + input-enable; + }; + gpio223ol_pins: gpio223ol-pins { + pins = "GPIO223/SMB13_SDA"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIX_CK/FM2_CK"; + bias-disable; + input-enable; + }; + gpio224o_pins: gpio224o-pins { + pins = "GPIO224/SPIX_CK/FM2_CK"; + bias-disable; + output-high; + }; + gpio224ol_pins: gpio224ol-pins { + pins = "GPIO224/SPIX_CK/FM2_CK"; + bias-disable; + output-low; + }; + gpio225_pins: gpio225-pins { + pins = "GPO225/SPIX_D0/FM2_D0/STRAP1"; + bias-disable; + input-enable; + }; + gpio225o_pins: gpio225o-pins { + pins = "GPO225/SPIX_D0/FM2_D0/STRAP1"; + bias-disable; + output-high; + }; + gpio226_pins: gpio226-pins { + pins = "GPO226/SPIX_D1/FM2_D1/STRAP2"; + bias-disable; + input-enable; + }; + gpio226o_pins: gpio226o-pins { + pins = "GPO226/SPIX_D1/FM2_D1/STRAP2"; + bias-disable; + output-high; + }; + gpio227_pins: gpio227-pins { + pins = "GPIO227/SPIX_nCS0/FM2_CSI"; + bias-disable; + input-enable; + }; + gpio227o_pins: gpio227o-pins { + pins = "GPIO227/SPIX_nCS0/FM2_CSI"; + bias-disable; + output-high; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/SPIX_nCS0/FM2_CSI"; + bias-disable; + output-low; + }; + gpio228_pins: gpio228-pins { + pins = "GPIO228/SPIX_nCS1/FM2_CSO"; + bias-disable; + input-enable; + }; + gpio228ol_pins: gpio228ol-pins { + pins = "GPIO228/SPIX_nCS1/FM2_CSO"; + bias-disable; + output-low; + }; + gpio229_pins: gpio229-pins { + pins = "GPO229/SPIX_D2/FM2_D2/STRAP3"; + bias-disable; + input-enable; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIX_D2/FM2_D2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPO230/SPIX_D3/FM2_D3/STRAP6"; + bias-disable; + input-enable; + }; + gpio230o_pins: gpio230o-pins { + pins = "GPO230/SPIX_D3/FM2_D3/STRAP6"; + bias-disable; + output-high; + }; + gpio230ol_pins: gpio230ol-pins { + pins = "GPO230/SPIX_D3/FM2_D3/STRAP6"; + bias-disable; + output-low; + }; + gpio231_pins: gpio231-pins { + pins = "GPIO231/EP_nCLKREQ"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/EP_nCLKREQ"; + bias-disable; + output-high; + }; + }; +}; diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index f5f1ce669b..d21e5042a6 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -59,6 +59,174 @@ clocks = <&clk_refclk>; }; + ehci1: usb@f0828100 { + compatible = "nuvoton,npcm845-ehci"; + reg = <0x0 0xf0828100 0x0 0x1000>; + interrupts = ; + resets = <&rstc2 NPCM8XX_RESET_USBH1>; + status = "disabled"; + }; + + ehci2: usb@f082a100 { + compatible = "nuvoton,npcm845-ehci"; + reg = <0x0 0xf082a100 0x0 0x1000>; + interrupts = ; + resets = <&rstc4 NPCM8XX_RESET_USBH2>; + status = "disabled"; + }; + + ohci1: usb@f0829000 { + compatible = "nuvoton,npcm845-ohci"; + reg = <0x0 0xF0829000 0x0 0x1000>; + resets = <&rstc2 NPCM8XX_RESET_USBH1>; + status = "disabled"; + }; + + ohci2: usb@f082b000 { + compatible = "nuvoton,npcm845-ohci"; + reg = <0x0 0xF082B000 0x0 0x1000>; + resets = <&rstc4 NPCM8XX_RESET_USBH2>; + status = "disabled"; + }; + + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + syscon = <&gcr>; + usbphy1: usbphy@1 { + compatible = "nuvoton,npcm845-usb-phy"; + #phy-cells = <1>; + reg = <1>; + resets = <&rstc3 NPCM8XX_RESET_USBPHY1>; + status = "disabled"; + }; + usbphy2: usbphy@2 { + compatible = "nuvoton,npcm845-usb-phy"; + #phy-cells = <1>; + reg = <2>; + resets = <&rstc3 NPCM8XX_RESET_USBPHY2>; + status = "disabled"; + }; + usbphy3: usbphy@3 { + compatible = "nuvoton,npcm845-usb-phy"; + #phy-cells = <1>; + reg = <3>; + resets = <&rstc3 NPCM8XX_RESET_USBPHY3>; + status = "disabled"; + }; + }; + + udc0:udc@f0830100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0830100 0x0 0x100 + 0x0 0xfffb0000 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC0>; + status = "disable"; + }; + + udc1:udc@f0831100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0831100 0x0 0x100 + 0x0 0xfffb0800 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC1>; + status = "disable"; + }; + + udc2:udc@f0832100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0832100 0x0 0x100 + 0x0 0xfffb1000 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC2>; + status = "disable"; + }; + + udc3:udc@f0833100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0833100 0x0 0x100 + 0x0 0xfffb1800 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC3>; + status = "disable"; + }; + + udc4:udc@f0834100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0834100 0x0 0x100 + 0x0 0xfffb2000 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC4>; + status = "disable"; + }; + + udc5:udc@f0835100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0835100 0x0 0x100 + 0x0 0xfffb2800 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC5>; + status = "disable"; + }; + + udc6:udc@f0836100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0836100 0x0 0x100 + 0x0 0xfffb3000 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc1 NPCM8XX_RESET_UDC6>; + status = "disable"; + }; + + udc7:udc@f0837100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0837100 0x0 0x100 + 0x0 0xfffb3800 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC7>; + status = "disable"; + }; + + udc8:udc@f0838100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0838100 0x0 0x100 + 0x0 0xfffb4000 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC8>; + status = "disable"; + }; + + udc9:udc@f0839100 { + compatible = "nuvoton,npcm845-udc"; + reg = <0x0 0xf0839100 0x0 0x100 + 0x0 0xfffb4800 0x0 0x800>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + resets = <&rstc3 NPCM8XX_RESET_UDC9>; + status = "disable"; + }; + apb { serial0: serial@0 { compatible = "nuvoton,npcm845-uart"; @@ -69,7 +237,7 @@ }; gpio0: gpio0@10000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x10000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -77,7 +245,7 @@ }; gpio1: gpio1@11000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x11000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -85,7 +253,7 @@ }; gpio2: gpio2@12000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x12000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -93,7 +261,7 @@ }; gpio3: gpio3@13000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x13000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -101,7 +269,7 @@ }; gpio4: gpio4@14000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x14000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -109,7 +277,7 @@ }; gpio5: gpio5@15000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x15000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -117,7 +285,7 @@ }; gpio6: gpio6@16000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x16000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -125,7 +293,7 @@ }; gpio7: gpio7@17000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio"; reg = <0x17000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -133,4 +301,652 @@ }; }; }; + pinctrl: pinctrl@f0800000 { + compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd"; + reg = <0x0 0xf0010000 0x0 0x8000>; + syscon-gcr = <&gcr>; + syscon-rst = <&rstc>; + status = "okay"; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi_pins: pspi-pins { + groups = "pspi"; + function = "pspi"; + }; + vgadig_pins: vgadig-pins { + groups = "vgadig"; + function = "vgadig"; + }; + jm1_pins: jm1-pins { + groups = "jm1"; + function = "jm1"; + }; + jm2_pins: jm2-pins { + groups = "jm2"; + function = "jm2"; + }; + smb4b_pins: smb4b-pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-pins { + groups = "smb15"; + function = "smb15"; + }; + smb16_pins: smb16-pins { + groups = "smb16"; + function = "smb16"; + }; + smb17_pins: smb17-pins { + groups = "smb17"; + function = "smb17"; + }; + smb18_pins: smb18-pins { + groups = "smb18"; + function = "smb18"; + }; + smb19_pins: smb19-pins { + groups = "smb19"; + function = "smb19"; + }; + smb20_pins: smb20-pins { + groups = "smb20"; + function = "smb20"; + }; + smb21_pins: smb21-pins { + groups = "smb21"; + function = "smb21"; + }; + smb22_pins: smb22-pins { + groups = "smb22"; + function = "smb22"; + }; + smb23_pins: smb23-pins { + groups = "smb23"; + function = "smb23"; + }; + smb4d_pins: smb4d-pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0cs2_pins: spi0cs2-pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3-pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c-pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-pins { + groups = "smb3b"; + function = "smb3b"; + }; + hsi1a_pins: hsi1a-pins { + groups = "hsi1a"; + function = "hsi1a"; + }; + hsi1b_pins: hsi1b-pins { + groups = "hsi1b"; + function = "hsi1b"; + }; + hsi1c_pins: hsi1c-pins { + groups = "hsi1c"; + function = "hsi1c"; + }; + hsi2a_pins: hsi2a-pins { + groups = "hsi2a"; + function = "hsi2a"; + }; + hsi2b_pins: hsi2b-pins { + groups = "hsi2b"; + function = "hsi2b"; + }; + hsi2c_pins: hsi2c-pins { + groups = "hsi2c"; + function = "hsi2c"; + }; + bmcuart0a_pins: bmcuart0a-pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + bmcuart0b_pins: bmcuart0b-pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + bmcuart1_pins: bmcuart1-pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + bu4_pins: bu4-pins { + groups = "bu4"; + function = "bu4"; + }; + bu5_pins: bu5-pins { + groups = "bu5"; + function = "bu5"; + }; + bu6_pins: bu6-pins { + groups = "bu6"; + function = "bu6"; + }; + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + r1oen_pins: r1oen-pins { + groups = "r1oen"; + function = "r1oen"; + }; + r1en_pins: r1en-pins { + groups = "r1en"; + function = "r1en"; + }; + r2oen_pins: r2oen-pins { + groups = "r2oen"; + function = "r2oen"; + }; + r2en_pins: r2en-pins { + groups = "r2en"; + function = "r2en"; + }; + rmii3_pins: rmii3_pins { + groups = "rmii3"; + function = "rmii3"; + }; + r3oen_pins: r3oen-pins { + groups = "r3oen"; + function = "r3oen"; + }; + r3en_pins: r3en-pins { + groups = "r3en"; + function = "r3en"; + }; + smb3d_pins: smb3d-pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + r3rxer_pins: r3rxer_pins { + groups = "r3rxer"; + function = "r3rxer"; + }; + ga20kbc_pins: ga20kbc-pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1-pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio-pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2-pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-pins { + groups = "ddr"; + function = "ddr"; + }; + i3c0_pins: i3c0-pins { + groups = "i3c0"; + function = "i3c0"; + }; + i3c1_pins: i3c1-pins { + groups = "i3c1"; + function = "i3c1"; + }; + i3c2_pins: i3c2-pins { + groups = "i3c2"; + function = "i3c2"; + }; + i3c3_pins: i3c3-pins { + groups = "i3c3"; + function = "i3c3"; + }; + i3c4_pins: i3c4-pins { + groups = "i3c4"; + function = "i3c4"; + }; + i3c5_pins: i3c5-pins { + groups = "i3c5"; + function = "i3c5"; + }; + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + pwm8_pins: pwm8-pins { + groups = "pwm8"; + function = "pwm8"; + }; + pwm9_pins: pwm9-pins { + groups = "pwm9"; + function = "pwm9"; + }; + pwm10_pins: pwm10-pins { + groups = "pwm10"; + function = "pwm10"; + }; + pwm11_pins: pwm11-pins { + groups = "pwm11"; + function = "pwm11"; + }; + mmc8_pins: mmc8-pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-pins { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme-pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci-pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6-pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7-pins { + groups = "smb7"; + function = "smb7"; + }; + spi1_pins: spi1-pins { + groups = "spi1"; + function = "spi1"; + }; + spi1d23_pins: spi1d23-pins { + groups = "spi1d23"; + function = "spi1d23"; + }; + faninx_pins: faninx-pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b-pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-pins { + groups = "smb0d"; + function = "smb0d"; + }; + rg2mdio_pins: rg2mdio-pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + rg2refck_pins: rg2refck-pins { + groups = "rg2refck"; + function = "rg2refck"; + }; + wdog1_pins: wdog1-pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-pins { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-pins { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-pins { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-pins { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-pins { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-pins { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-pins { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-pins { + groups = "hgpio7"; + function = "hgpio7"; + }; + jtag2_pins: jtag2-pins { + groups = "jtag2"; + function = "jtag2"; + }; + }; }; From 8debdf1417f8bf94ded3b39fa55b0535b9aaf66d Mon Sep 17 00:00:00 2001 From: Jim Liu Date: Mon, 28 Nov 2022 10:34:47 +0800 Subject: [PATCH 158/424] ARM: dts: npcm7xx: add npcm750 gpio node compatible name Add npcm750 gpio node compatible name Signed-off-by: Jim Liu --- arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi index c547e433e7..d54064091e 100644 --- a/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm7xx-u-boot.dtsi @@ -220,7 +220,7 @@ clocks = <&clk NPCM7XX_CLK_APB1>; }; gpio_0: gpio0@10000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x10000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -228,7 +228,7 @@ }; gpio_1: gpio1@11000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x11000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -236,14 +236,14 @@ }; gpio_2: gpio2@12000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x12000 0xB0>; #gpio-cells = <2>; gpio-controller; gpio-bank-name = "gpio2"; }; gpio_3: gpio3@13000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x13000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -251,7 +251,7 @@ }; gpio_4: gpio4@14000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x14000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -259,7 +259,7 @@ }; gpio_5: gpio5@15000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x15000 0xB0>; #gpio-cells = <2>; gpio-controller; @@ -267,14 +267,14 @@ }; gpio_6: gpio6@16000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x16000 0xB0>; #gpio-cells = <2>; gpio-controller; gpio-bank-name = "gpio6"; }; gpio_7: gpio7@17000 { - compatible = "nuvoton,npcm-gpio"; + compatible = "nuvoton,npcm-gpio", "nuvoton,npcm750-gpio"; reg = <0x17000 0xB0>; #gpio-cells = <2>; gpio-controller; From 178cbadb52f0c2809de6ded0f7b42fa7bb4e0e78 Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Tue, 29 Nov 2022 19:37:59 +0000 Subject: [PATCH 159/424] configs: set CONFIG_LMB_MAX_REGIONS=64 for all mt798[16] boards With recently added wireless offloading features in Linux [1] the number of reserved memory regions with MediaTek SoCs supporting offloading wireless-to-Ethernet traffic grew beyond the default (8) which breaks booting Linux: ERROR: Failed to allocate 0xa6ac bytes below 0xc0000000. device tree - allocation error FDT creation failed! resetting ... Raise CONFIG_LMB_MAX_REGIONS to 64 like it is already done for other SoCs which require a larger number of reserved memory regions, eg. exynos78x0 based a3y17lte, a5y17lte and a7y17lte or dragonboard845c. [1]: https://lore.kernel.org/netdev/e3489a697b404bd47447190cd2e5adf090ae61c2.1667687249.git.lorenzo@kernel.org/ https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=eed4f1ddad8c5ad7596b229caec8bd7b477b81ee Signed-off-by: Daniel Golle --- configs/mt7981_emmc_rfb_defconfig | 1 + configs/mt7981_rfb_defconfig | 1 + configs/mt7981_sd_rfb_defconfig | 1 + configs/mt7986_rfb_defconfig | 1 + configs/mt7986a_bpir3_emmc_defconfig | 1 + configs/mt7986a_bpir3_sd_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig index 4832a22643..b3b37b6e5e 100644 --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig @@ -62,3 +62,4 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set +CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index c397527887..b7ffb4dfa7 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -64,3 +64,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MTK_SPIM=y CONFIG_HEXDUMP=y +CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig index 17592dc22b..85be9bbc50 100644 --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig @@ -62,3 +62,4 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set +CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 1363f9dc6d..ac91c93efb 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -64,3 +64,4 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MTK_SPIM=y CONFIG_HEXDUMP=y +CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index 354159df9b..2d4876f299 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -62,3 +62,4 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set +CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index db7ef98d80..08edfe7ac4 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -62,3 +62,4 @@ CONFIG_MTK_SERIAL=y CONFIG_FAT_WRITE=y CONFIG_HEXDUMP=y # CONFIG_EFI_LOADER is not set +CONFIG_LMB_MAX_REGIONS=64 From 1e1c51f8ace8717f972ccad37616e3b6488e92ad Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 7 Dec 2022 15:49:43 -0500 Subject: [PATCH 160/424] Makefile: link with --no-warn-rwx-segments We borrow from the Linux Kernel 0d362be5b142 ("Makefile: link with -z noexecstack --no-warn-rwx-segments") here to disable the RWX segment linking warnings. We do not also bring in -z noexecstack as that requires auditing and using ".note.GNU-stack" on assembly functions which do need this feature. Further, we now introduce KBUILD_EFILDFLAGS so that we can also pass --no-warn-rwx-segments when linking EFI applications, and those do explicitly pass -z execstack. Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Signed-off-by: Tom Rini Reviewed-by: Nick Desaulniers Reviewed-by: Ilias Apalodimas --- Makefile | 2 ++ scripts/Makefile.lib | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 9ec2e12a06..9d84f96481 100644 --- a/Makefile +++ b/Makefile @@ -806,6 +806,8 @@ KBUILD_CPPFLAGS += $(KCPPFLAGS) KBUILD_AFLAGS += $(KAFLAGS) KBUILD_CFLAGS += $(KCFLAGS) +KBUILD_LDFLAGS += $(call ld-option,--no-warn-rwx-segments) + KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g) # Use UBOOTINCLUDE when you must reference the include/ directory. diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 8e13bf2b98..ac45a88478 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -425,9 +425,11 @@ cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j \ $(obj)/%.efi: $(obj)/%_efi.so $(call cmd,efi_objcopy) +KBUILD_EFILDFLAGS = -nostdlib -zexecstack -znocombreloc -znorelro +KBUILD_EFILDFLAGS += $(call ld-option,--no-warn-rwx-segments) quiet_cmd_efi_ld = LD $@ -cmd_efi_ld = $(LD) -nostdlib -zexecstack -znocombreloc -T $(EFI_LDS_PATH) \ - -shared -Bsymbolic -znorelro -s $^ -o $@ +cmd_efi_ld = $(LD) $(KBUILD_EFILDFLAGS) -T $(EFI_LDS_PATH) \ + -shared -Bsymbolic -s $^ -o $@ EFI_LDS_PATH = $(srctree)/arch/$(ARCH)/lib/$(EFI_LDS) From 828d7e6022f2ae827aa278fc6bc15efee0d0a6b6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:40 +0100 Subject: [PATCH 161/424] configs: am333x_guardian: move MTDIDS_DEFAULT in defconfif Replace MTDIDS_DEFAULT in config include file by CONFIG_MTDIDS_DEFAULT in defonfig to complete the Kconfig migration Signed-off-by: Patrick Delaunay --- configs/am335x_guardian_defconfig | 1 + include/configs/am335x_guardian.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index fef4fd1551..0feac53c35 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -64,6 +64,7 @@ CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_CMD_BMP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),1m(u-boot-2),1m(u-boot-2.backup1),256k(u-boot-env),256k(u-boot-env.backup1),256k(splash-screen),-(UBI)" CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index 7c5e7ce475..a5b83b0c25 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -115,7 +115,6 @@ } #define CFG_SYS_NAND_ECCSIZE 512 #define CFG_SYS_NAND_ECCBYTES 26 -#define MTDIDS_DEFAULT "nand0=nand.0" #endif /* CONFIG_MTD_RAW_NAND */ From bde4a407ea89704e5d2dd6d77140a4d2616c171d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:41 +0100 Subject: [PATCH 162/424] configs: x530: move MTDPART/MTDIDS_DEFAULT in defconfig Replace MTDIDS_DEFAULT and MTDPARTS_DEFAULT in the config include file by CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration. Signed-off-by: Patrick Delaunay --- configs/x530_defconfig | 2 ++ include/configs/x530.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/x530_defconfig b/configs/x530_defconfig index 2f8be2fcd7..70c08adcde 100644 --- a/configs/x530_defconfig +++ b/configs/x530_defconfig @@ -57,6 +57,8 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" CONFIG_CMD_UBI=y CONFIG_ENV_OVERWRITE=y CONFIG_ARP_TIMEOUT=200 diff --git a/include/configs/x530.h b/include/configs/x530.h index dee87cb773..c213dc6074 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -32,8 +32,6 @@ /* SPI NOR flash default params, used by sf commands */ -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" #define MTDPARTS_MTDOOPS "errlog" /* Partition support */ From 91b9551fb3c877f5c35324f31736787b4c7228cd Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:42 +0100 Subject: [PATCH 163/424] configs: SBx81LIFXCAT: move MTDPART_DEFAULT in defconfig Replace MTDPARTS_DEFAULT in the config include file by CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration. Signed-off-by: Patrick Delaunay --- configs/SBx81LIFXCAT_defconfig | 1 + include/configs/SBx81LIFXCAT.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 125871301e..80dbbb11c9 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -35,6 +35,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y # CONFIG_CMD_LED is not set +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 9a9663b34b..23d37394e0 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -21,7 +21,6 @@ * for your console driver. */ -#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" /* From 72e79f998e79626a551d22c637abf4c5786e8046 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:43 +0100 Subject: [PATCH 164/424] configs: SBx81LIFKW: move MTDPART_DEFAULT in defconfig Replace MTDPARTS_DEFAULT in the config include file by CONFIG_MTDPARTS_DEFAULT in defconfig to complete the Kconfig migration. Signed-off-by: Patrick Delaunay --- configs/SBx81LIFKW_defconfig | 1 + include/configs/SBx81LIFKW.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index fa7c35b9ef..e53f2489c5 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTP_NTPSERVER=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_SNTP=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index bad34d9771..d5c9c05767 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -21,7 +21,6 @@ * for your console driver. */ -#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" #define MTDPARTS_MTDOOPS "errlog" /* From 8b83d54f9e40cdd25b41404ce96066f5e3b4a41f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 7 Dec 2022 09:26:44 +0100 Subject: [PATCH 165/424] configs: remove support of MTDIDS_DEFAULT/MTDPARTS_DEFAULT Complete the migration of MTDPARTS_DEFAULT / MTDIDS_DEFAULT in Kconfig; this patch removes the support of MTDIDS_DEFAULT / MTDPARTS_DEFAULT in the configuration files (include/configs/*.h). Signed-off-by: Patrick Delaunay --- cmd/mtdparts.c | 5 +---- drivers/mtd/mtd_uboot.c | 4 ---- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index bab75a262f..0984158f41 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -111,20 +111,17 @@ DECLARE_GLOBAL_DATA_PTR; #define MTD_WRITEABLE_CMD 1 /* default values for mtdids and mtdparts variables */ -#if !defined(MTDIDS_DEFAULT) #ifdef CONFIG_MTDIDS_DEFAULT #define MTDIDS_DEFAULT CONFIG_MTDIDS_DEFAULT #else #define MTDIDS_DEFAULT NULL #endif -#endif -#if !defined(MTDPARTS_DEFAULT) #ifdef CONFIG_MTDPARTS_DEFAULT #define MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT #else #define MTDPARTS_DEFAULT NULL #endif -#endif + #if defined(CONFIG_SYS_MTDPARTS_RUNTIME) extern void board_mtdparts_default(const char **mtdids, const char **mtdparts); #endif diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c index dd0b0242f9..14ce726b10 100644 --- a/drivers/mtd/mtd_uboot.c +++ b/drivers/mtd/mtd_uboot.c @@ -30,8 +30,6 @@ static const char *get_mtdids(void) #if defined(CONFIG_SYS_MTDPARTS_RUNTIME) board_mtdparts_default(&mtdids, &mtdparts); -#elif defined(MTDIDS_DEFAULT) - mtdids = MTDIDS_DEFAULT; #elif defined(CONFIG_MTDIDS_DEFAULT) mtdids = CONFIG_MTDIDS_DEFAULT; #endif @@ -147,8 +145,6 @@ static const char *get_mtdparts(void) #if defined(CONFIG_SYS_MTDPARTS_RUNTIME) board_mtdparts_default(&mtdids, &mtdparts); -#elif defined(MTDPARTS_DEFAULT) - mtdparts = MTDPARTS_DEFAULT; #elif defined(CONFIG_MTDPARTS_DEFAULT) mtdparts = CONFIG_MTDPARTS_DEFAULT; #endif From 553d7607c681806a40550696d56e15dcd9a2b0e6 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:37 +0100 Subject: [PATCH 166/424] board/km: move ls102xa boards to environment text files Create a common.env which we can use later on also for other boards. Signed-off-by: Holger Brunck --- .../keymile/pg-wcom-ls102xa/pg-wcom-expu1.env | 3 + .../keymile/pg-wcom-ls102xa/pg-wcom-seli8.env | 3 + configs/pg_wcom_expu1_defconfig | 2 +- configs/pg_wcom_expu1_update_defconfig | 2 +- configs/pg_wcom_seli8_defconfig | 2 +- configs/pg_wcom_seli8_update_defconfig | 2 +- include/configs/km/pg-wcom-ls102xa.h | 65 ------------------ include/configs/pg-wcom-expu1.h | 4 -- include/configs/pg-wcom-seli8.h | 5 -- include/environment/pg-wcom/common.env | 68 +++++++++++++++++++ include/environment/pg-wcom/ls102xa.env | 29 ++++++++ 11 files changed, 107 insertions(+), 78 deletions(-) create mode 100644 board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env create mode 100644 board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env create mode 100644 include/environment/pg-wcom/common.env create mode 100644 include/environment/pg-wcom/ls102xa.env diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env new file mode 100644 index 0000000000..d960de6bfe --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-expu1.env @@ -0,0 +1,3 @@ +#include + +hostname=EXPU1 diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env new file mode 100644 index 0000000000..4031f8bee9 --- /dev/null +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-seli8.env @@ -0,0 +1,3 @@ +#include + +hostname=SELI8 diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index d21e180d1f..b57e588f4e 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -20,7 +20,6 @@ CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -64,6 +63,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 54773b0633..9029e7babc 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -19,7 +19,6 @@ CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -62,6 +61,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 8311b3a3a0..aa74e1746a 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -20,7 +20,6 @@ CONFIG_ENV_ADDR=0x60060000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -64,6 +63,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index d6f4a05479..2b18a88d44 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -19,7 +19,6 @@ CONFIG_ENV_ADDR=0x60220000 CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_COMMON_ETH_INIT=y CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED=y @@ -62,6 +61,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index dfa81c037f..7fe2ece840 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -6,9 +6,6 @@ #ifndef __CONFIG_PG_WCOM_LS102XA_H #define __CONFIG_PG_WCOM_LS102XA_H -/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" - #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE @@ -168,68 +165,6 @@ #define HWCONFIG_BUFFER_SIZE 256 -/* - * Environment - */ - -#define CONFIG_ENV_TOTAL_SIZE 0x40000 -#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */ - -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV -#endif - -#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" -#endif - -#define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize}\0" \ - "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "" - -#define CONFIG_KM_NEW_ENV \ - "newenv=protect off " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "erase " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "protect on " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" - -#define CONFIG_HW_ENV_SETTINGS \ - "hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi," \ - "can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6," \ - "asrc,spdif,lpuart1,ftm1\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_NEW_ENV \ - CONFIG_KM_DEF_ENV \ - CONFIG_HW_ENV_SETTINGS \ - "EEprom_ivm=pca9547:70:9\0" \ - "ethrotate=no\0" \ - "" - #define CFG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ #endif diff --git a/include/configs/pg-wcom-expu1.h b/include/configs/pg-wcom-expu1.h index 1b72739d14..2c38cffa8a 100644 --- a/include/configs/pg-wcom-expu1.h +++ b/include/configs/pg-wcom-expu1.h @@ -7,10 +7,6 @@ #define __CONFIG_PG_WCOM_EXPU1_H #define WCOM_EXPU1 -#define CONFIG_HOSTNAME "EXPU1" - -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" /* CLIPS FPGA Definitions */ #define CFG_SYS_CSPR3_EXT (0x00) diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h index e4bcae5bb5..9474d3bd7b 100644 --- a/include/configs/pg-wcom-seli8.h +++ b/include/configs/pg-wcom-seli8.h @@ -6,11 +6,6 @@ #ifndef __CONFIG_PG_WCOM_SELI8_H #define __CONFIG_PG_WCOM_SELI8_H -#define CONFIG_HOSTNAME "SELI8" - -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - /* PAXK FPGA Definitions */ #define CFG_SYS_CSPR3_EXT (0x00) #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ diff --git a/include/environment/pg-wcom/common.env b/include/environment/pg-wcom/common.env new file mode 100644 index 0000000000..4b660cebd6 --- /dev/null +++ b/include/environment/pg-wcom/common.env @@ -0,0 +1,68 @@ + +#ifndef WCOM_UBI_PARTITION_APP +/* one flash chip only called boot */ +# define WCOM_UBI_LINUX_MTD ubi.mtd=ubi0 +ubiattach=ubi part ubi0 +#else /* WCOM_UBI_PARTITION_APP */ +/* two flash chips called boot and app */ +# define WCOM_UBI_LINUX_MTD ubi.mtd=ubi0 ubi.mtd=ubi1 +ubiattach=if test ${boot_bank} -eq 0; + then; + ubi part ubi0; + else; + ubi part ubi1; + fi +#endif /* WCOMC_UBI_PARTITION_APP */ + +actual_bank=0 + +add_default=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off: + console=ttyS0,${baudrate} mem=${kernelmem} init=${init} + phram.phram=phvar,${varaddr},CONFIG_KM_PHRAM + WCOM_UBI_LINUX_MTD + +addpanic=setenv bootargs ${bootargs} panic=1 panic_on_oops=1 +altbootcmd=run bootcmd +backup_bank=0 +boot=bootm ${load_addr_r} - ${fdt_addr_r} + +bootcmd=km_checkbidhwk && + setenv bootcmd 'if km_checktestboot; + then; + setenv boot_bank ${test_bank}; + else; + setenv boot_bank ${actual_bank}; + fi; + run ${subbootcmds}; reset' && + setenv altbootcmd 'setenv boot_bank ${backup_bank}; + run ${subbootcmds}; + reset' && + saveenv && + saveenv && + boot + +cramfsaddr=CONFIG_KM_CRAMFS_ADDR +cramfsloadfdt=cramfsload ${fdt_addr_r} fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb +cramfsloadkernel=cramfsload ${load_addr_r} ${uimage} + +develop=tftp ${load_addr_r} scripts/develop-${arch}.txt && + env import -t ${load_addr_r} ${filesize} && + run setup_debug_env + +env_version=1 +fdt_addr_r=CONFIG_KM_FDT_ADDR +flashargs=setenv bootargs root=mtdblock:rootfs${boot_bank} rootfstype=squashfs ro +init=/sbin/init-overlay.sh +load=tftpboot ${load_addr_r} ${hostname}/u-boot.bin +load_addr_r=CONFIG_KM_KERNEL_ADDR +pnvramsize=CONFIG_KM_PNVRAM + +ramfs=tftp ${load_addr_r} scripts/ramfs-${arch}.txt && + env import -t ${load_addr_r} ${filesize} && + run setup_debug_env + +release=run newenv; reset +subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt set_fdthigh + cramfsloadkernel flashargs add_default addpanic boot +testbootcmd=setenv boot_bank ${test_bank}; run ${subbootcmds}; reset +ubicopy=ubi read ${cramfsaddr} bootfs${boot_bank} diff --git a/include/environment/pg-wcom/ls102xa.env b/include/environment/pg-wcom/ls102xa.env new file mode 100644 index 0000000000..5b5bda95e2 --- /dev/null +++ b/include/environment/pg-wcom/ls102xa.env @@ -0,0 +1,29 @@ +#define WCOM_UBI_PARTITION_APP + +#include + +EEprom_ivm=pca9547:70:9 +boot=bootm $load_addr_r - $fdt_addr_r +checkfdt=true +cramfsloadfdt=cramfsload $fdt_addr_r fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb +ethrotate=no +hwconfig=devdis:esdhc,usb3,usb2,sata,sec,dcu,duart2,qspi,can1,can2_4,ftm2_8,i2c2_3,sai1_4,lpuart2_6,asrc,spdif,lpuart1,ftm1 +netdev=eth2 + +newenv=protect off CONFIG_ENV_ADDR_REDUND +0x40000 && + erase CONFIG_ENV_ADDR_REDUND +0x40000 && + protect on CONFIG_ENV_ADDR_REDUND +0x40000 + +set_fdthigh=true + +update=protect off CONFIG_SYS_MONITOR_BASE +${filesize} && + erase CONFIG_SYS_MONITOR_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_MONITOR_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +${filesize} + +update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} && + erase CONFIG_SYS_FLASH_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_FLASH_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +0x100000 + +uimage=uImage From 0cc0c098c8fbbf61378081df9681e660829c48eb Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:38 +0100 Subject: [PATCH 167/424] km/powerpc: migrate to env.txt file Use already present common.env file and add a powerpc specific env so that we can move all the environment defines to text files. Signed-off-by: Holger Brunck --- board/keymile/km83xx/km83xx.env | 21 +++++++++++ configs/kmcoge5ne_defconfig | 2 +- configs/kmeter1_defconfig | 2 +- configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + include/configs/km/km-mpc83xx.h | 24 ------------- include/configs/km/km-powerpc.h | 46 ------------------------- include/configs/kmcoge5ne.h | 6 ---- include/configs/kmeter1.h | 4 --- include/configs/kmopti2.h | 7 ---- include/configs/kmsupx5.h | 7 ---- include/configs/kmtepr2.h | 7 ---- include/configs/tuge1.h | 7 ---- include/configs/tuxx1.h | 7 ---- include/environment/pg-wcom/powerpc.env | 14 ++++++++ 18 files changed, 42 insertions(+), 117 deletions(-) create mode 100644 board/keymile/km83xx/km83xx.env delete mode 100644 include/configs/km/km-powerpc.h create mode 100644 include/environment/pg-wcom/powerpc.env diff --git a/board/keymile/km83xx/km83xx.env b/board/keymile/km83xx/km83xx.env new file mode 100644 index 0000000000..ed2487c028 --- /dev/null +++ b/board/keymile/km83xx/km83xx.env @@ -0,0 +1,21 @@ +#if CONFIG_TARGET_KMCOGE5NE +#define WCOM_UBI_PARTITION_APP +hostname=kmcoge5ne +netdev=eth1 +uimage=ecc_bch_uImage +#elif CONFIG_TARGET_KMETER1 +hostname=kmeter1 +netdev=eth2 +uimage=uImage +#else +hostname=kmeter1 +netdev=eth0 +uimage=uImage +#endif + +#include +#include + +#if CONFIG_TARGET_KMCOGE5NE +add_default+= eccmode=bch +#endif diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 013277c9bf..6bfcee9ed2 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -159,7 +159,6 @@ CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y CONFIG_83XX_PCICLK=0x3ef1480 -CONFIG_KM_DEF_NETDEV="eth1" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -197,6 +196,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot,nand0=app" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);app:-(ubi1);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 66ec936cce..b0af9e051b 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -129,7 +129,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -166,6 +165,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 3ba334c240..9a1e7cbde3 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -178,6 +178,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 4a02e5e88f..d981e51223 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -157,6 +157,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 55158864ea..18a464c0ae 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -177,6 +177,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 894a79df59..dbd832c9b7 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -157,6 +157,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 6e66e6ce30..1b034a21a7 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -179,6 +179,7 @@ CONFIG_MTDIDS_DEFAULT="nor0=boot" CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi0);" CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set +CONFIG_ENV_SOURCE_FILE="km83xx" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 840a4d5401..7f1839f463 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -67,30 +67,6 @@ */ #define CFG_SYS_BOOTMAPSZ (8 << 20) -/* - * Environment - */ - -/* - * Environment Configuration - */ -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ - "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ - "unlock=yes\0" \ - "" - /* * QE UEC ethernet configuration */ diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h deleted file mode 100644 index 424caa0df9..0000000000 --- a/include/configs/km/km-powerpc.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KEYMILE_POWERPC_H -#define __CONFIG_KEYMILE_POWERPC_H - -/* Do boardspecific init for all boards */ - -/* Increase max size of compressed kernel */ - -/****************************************************************************** - * (PRAM usage) - * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM - * ... |<------------------- pram -------------------------->| - * ... ------------------------------------------------------- - * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose - * @CONFIG_KM_PHRAM: address for /var - * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) - */ - -/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable - * is not valid yet, which is the case for when u-boot copies itself to RAM */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" - -#define CONFIG_KM_DEF_ENV_CPU \ - "u-boot="CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=" \ - "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ - "erase " __stringify(BOOTFLASH_START) " +${filesize} && "\ - "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ - " ${filesize} && " \ - "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "bootm_mapsize=" __stringify(CONFIG_SYS_BOOTM_LEN) "\0" \ - "" - -#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 6b30fb4b61..e0f94aead7 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -8,16 +8,10 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_HOSTNAME "kmcoge5ne" #define NAND_MAX_CHIPS 1 #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 910fc1b2cb..6f67e5a98a 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -8,11 +8,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_HOSTNAME "kmeter1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc8360.h" diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 5050c70303..d6a3844bcc 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "kmopti2" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index e3de6c61e7..d6a3844bcc 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "kmsupx5" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index a4ceb1c50d..d6a3844bcc 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "kmtepr2" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index d43ccbe8dd..d6a3844bcc 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "tuge1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index 7eed31c35f..d6a3844bcc 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -20,14 +20,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* - * High Level Configuration Options - */ -#define CONFIG_HOSTNAME "tuxx1" - /* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h" diff --git a/include/environment/pg-wcom/powerpc.env b/include/environment/pg-wcom/powerpc.env new file mode 100644 index 0000000000..a57fd93092 --- /dev/null +++ b/include/environment/pg-wcom/powerpc.env @@ -0,0 +1,14 @@ +arch=ppc_82xx +bootm_mapsize=CONFIG_SYS_BOOTM_LEN +checkfdt=true +set_fdthigh=true + +update=protect off BOOTFLASH_START +${filesize} && + erase BOOTFLASH_START +${filesize} && + cp.b ${load_addr_r} BOOTFLASH_START ${filesize} && + protect on BOOTFLASH_START +${filesize} + +newenv=prot off CONFIG_ENV_ADDR +0x40000 && + era CONFIG_ENV_ADDR +0x40000 + +unlock=yes From 6f7c936fbdd40071716730d07083c7f596700478 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:39 +0100 Subject: [PATCH 168/424] board/km/cent2: migrate to environment text file Use like the other boards a text file for the environment. As this is the last user of keymile-common.h we can now remove this file completely. Signed-off-by: Holger Brunck --- board/keymile/Kconfig | 12 -- board/keymile/kmcent2/kmcent2.c | 2 +- board/keymile/kmcent2/kmcent2.env | 37 ++++++ configs/kmcent2_defconfig | 2 +- include/configs/km/keymile-common.h | 174 ---------------------------- include/configs/kmcent2.h | 74 ------------ scripts/config_whitelist.txt | 15 --- 7 files changed, 39 insertions(+), 277 deletions(-) create mode 100644 board/keymile/kmcent2/kmcent2.env delete mode 100644 include/configs/km/keymile-common.h diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index b8f0578a28..46d0897108 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -77,18 +77,6 @@ config SYS_CLIPS_BASE help IFC Base Address for CLIPS FPGA. -config KM_CONSOLE_TTY - string "KM Console" - default "ttyS0" - help - TTY console to use on board. - -config KM_DEF_NETDEV - string "Default Netdevice" - default "eth0" - help - Default netdevice for debug interface - config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" default y if ARCH_KIRKWOOD || MPC83xx diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 9f68c215f3..ed552c57b5 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -34,7 +34,7 @@ static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int checkboard(void) { - printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME); + printf("Board: Hitachi Power Grids kmcent2\n"); return 0; } diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env new file mode 100644 index 0000000000..7c8f8306c5 --- /dev/null +++ b/board/keymile/kmcent2/kmcent2.env @@ -0,0 +1,37 @@ +#include + +EEprom_ivm=pca9547:70:9 +arch=ppc_82xx +boot=bootm ${load_addr_r} - ${fdt_addr_r} +checkfdt=true +cramfsloadfdt=cramfsload ${fdt_addr_r} fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb +fpgacfg=true +hostname=kmcent2 +hwconfig=fsl_ddr:ctlr_intlv=cacheline +netdev=eth2 + +newenv=protect off ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && + erase ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && + protect on ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE + +set_fdthigh=true +uimage=uImage + +update=protect off CONFIG_SYS_MONITOR_BASE +${filesize} && + erase CONFIG_SYS_MONITOR_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_MONITOR_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +${filesize} + update-nor=protect off CONFIG_SYS_FLASH_BASE +${filesize} && + erase CONFIG_SYS_FLASH_BASE +${filesize} && + cp.b ${load_addr_r} CONFIG_SYS_FLASH_BASE ${filesize} && + protect on CONFIG_SYS_MONITOR_BASE +CONFIG_SYS_MONITOR_LEN + +usb_phy_type=utmi +usb_dr_mode=host + +/* + * The Linux fsl_fman driver needs to be able to process frames with more + * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot + * parameters + */ +add_default+= fsl_dpaa_fman.fsl_fm_max_frm=1558 diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 41b26287d5..2abda78893 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_CACHE_STASHING=y # CONFIG_DEEP_SLEEP is not set CONFIG_PCIE1=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 -CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_IVM_BUS=2 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y @@ -54,6 +53,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:128k(RCW),128k(fman),128k(QE),12 CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_OF_CONTROL=y +CONFIG_ENV_SOURCE_FILE="kmcent2" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h deleted file mode 100644 index cc5ec219b8..0000000000 --- a/include/configs/km/keymile-common.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KEYMILE_H -#define __CONFIG_KEYMILE_H - -#include - -/* - * Miscellaneous configurable options - */ - -#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS -#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ - "actual_bank=0\0" -#endif - -#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ - -#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS -#define CONFIG_KM_UBI_PART_BOOT_OPTS "" -#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ - -#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP -/* one flash chip only called boot */ -/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ -# define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ - CONFIG_KM_UBI_PART_BOOT_OPTS -# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ - "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" -#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ -/* two flash chips called boot and app */ -/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ -/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ -# define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ - CONFIG_KM_UBI_PART_BOOT_OPTS " " \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP -# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ - "ubiattach=if test ${boot_bank} -eq 0; then; " \ - "ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; " \ - "ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0" -#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */ - -#ifdef CONFIG_NAND_ECC_BCH -#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0" -#define CONFIG_KM_ECC_MODE " eccmode=bch" -#else -#define CONFIG_KM_UIMAGE_NAME "uImage\0" -#define CONFIG_KM_ECC_MODE -#endif - -/* - * boottargets - * - set 'subbootcmds' - * - set 'bootcmd' and 'altbootcmd' - * available targets: - * - 'release': for a standalone system kernel/rootfs from flash - */ -#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt " \ - "set_fdthigh cramfsloadkernel flashargs add_default " \ - "addpanic boot\0" \ - "develop=" \ - "tftp ${load_addr_r} scripts/develop-${arch}.txt && " \ - "env import -t ${load_addr_r} ${filesize} && " \ - "run setup_debug_env\0" \ - "ramfs=" \ - "tftp ${load_addr_r} scripts/ramfs-${arch}.txt && " \ - "env import -t ${load_addr_r} ${filesize} && " \ - "run setup_debug_env\0" \ - "" - -/* - * bootargs - * - modify 'bootargs' - * - * - 'add_default': default bootargs common for all arm/ppc boards - * - 'addpanic': add kernel panic options - * - 'flashargs': defaults arguments for flash base boot - * - */ -#define CONFIG_KM_DEF_ENV_BOOTARGS \ - "add_default=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off:" \ - " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ - " mem=${kernelmem} init=${init}" \ - CONFIG_KM_ECC_MODE \ - " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\ - " " CONFIG_KM_UBI_LINUX_MTD " " \ - CONFIG_KM_DEF_BOOT_ARGS_CPU \ - "\0" \ - "addpanic=" \ - "setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \ - "flashargs=" \ - "setenv bootargs " \ - "root=mtdblock:rootfs${boot_bank} " \ - "rootfstype=squashfs ro\0" \ - "" - -/* - * flash_boot - * - commands for booting from flash - * - * - 'cramfsloadkernel': copy kernel from a cramfs to ram - * - 'ubiattach': attach ubi partition - * - 'ubicopy': copy ubi volume to ram - * - volume names: bootfs0, bootfs1, bootfs2, ... - * - * processor specific settings - * - 'cramfsloadfdt': copy fdt from a cramfs to ram - */ -#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ - "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \ - "cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0" \ - "ubicopy=ubi read ${cramfsaddr} bootfs${boot_bank}\0" \ - "uimage=" CONFIG_KM_UIMAGE_NAME \ - CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI - -/* - * constants - * - KM specific constants and commands - * - * - 'default': setup default environment - */ -#define CONFIG_KM_DEF_ENV_CONSTANTS \ - "backup_bank=0\0" \ - "release=run newenv; reset\0" \ - "pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0" \ - "testbootcmd=setenv boot_bank ${test_bank}; " \ - "run ${subbootcmds}; reset\0" \ - "env_version=1\0" \ - "" - -#ifndef CONFIG_KM_DEF_ENV -#define CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ENV_BOOTPARAMS \ - "netdev=" __stringify(CONFIG_KM_DEF_NETDEV) "\0" \ - CONFIG_KM_DEF_ENV_CPU \ - CONFIG_KM_DEF_ENV_BOOTTARGETS \ - CONFIG_KM_DEF_ENV_BOOTARGS \ - CONFIG_KM_DEF_ENV_FLASH_BOOT \ - CONFIG_KM_DEF_ENV_CONSTANTS \ - "altbootcmd=run bootcmd\0" \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=km_checkbidhwk && " \ - "setenv bootcmd \'if km_checktestboot; then; " \ - "setenv boot_bank ${test_bank}; else; " \ - "setenv boot_bank ${actual_bank}; fi;" \ - "run ${subbootcmds}; reset\' && " \ - "setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \ - "run ${subbootcmds}; reset\' && " \ - "saveenv && saveenv && boot\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "init=/sbin/init-overlay.sh\0" \ - "load_addr_r=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "load=tftpboot ${load_addr_r} ${u-boot}\0" \ - "" -#endif /* CONFIG_KM_DEF_ENV */ - -#endif /* __CONFIG_KEYMILE_H */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 527f0383bc..532370e918 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -8,18 +8,6 @@ #ifndef __KMCENT2_H #define __KMCENT2_H -#define CONFIG_HOSTNAME "kmcent2" -#define KM_BOARD_NAME CONFIG_HOSTNAME - -/* - * The Linux fsl_fman driver needs to be able to process frames with more - * than just the VLAN tag (i.e. eDSA tag). It is passed as a kernel boot - * parameters - */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "fsl_dpaa_fman.fsl_fm_max_frm=1558" - -#include "km/keymile-common.h" - /* Application IFC chip selects */ #define SYS_LAWAPP_BASE 0xc0000000 #define SYS_LAWAPP_BASE_PHYS (0xf00000000ull | SYS_LAWAPP_BASE) @@ -387,66 +375,4 @@ int get_scl(void); */ #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -/* - * Environment Configuration - */ -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV -#endif - -#define __USB_PHY_TYPE utmi - -#define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize}\0" \ - "update-nor=protect off " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "erase " __stringify(CFG_SYS_FLASH_BASE) \ - " +${filesize} && " \ - "cp.b ${load_addr_r} " \ - __stringify(CFG_SYS_FLASH_BASE) " ${filesize} && " \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +" __stringify(CONFIG_SYS_MONITOR_LEN) "\0" \ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "fpgacfg=true\0" \ - "" - -#define CONFIG_HW_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ - "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "usb_dr_mode=host\0" - -#define CONFIG_KM_NEW_ENV \ - "newenv=protect off " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "erase " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ - "protect on " __stringify(ENV_DEL_ADDR) \ - " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" - -/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - CONFIG_KM_NEW_ENV \ - CONFIG_HW_ENV_SETTINGS \ - "EEprom_ivm=pca9547:70:9\0" \ - "" - #endif /* __KMCENT2_H */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 12c23a5dfd..f829a7927d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -70,23 +70,8 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KM_DEF_ARCH -CONFIG_KM_DEF_BOOT_ARGS_CPU -CONFIG_KM_DEF_ENV -CONFIG_KM_DEF_ENV_BOOTARGS -CONFIG_KM_DEF_ENV_BOOTPARAMS CONFIG_KM_DEF_ENV_BOOTTARGETS -CONFIG_KM_DEF_ENV_CONSTANTS -CONFIG_KM_DEF_ENV_CPU -CONFIG_KM_DEF_ENV_FLASH_BOOT -CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI -CONFIG_KM_ECC_MODE CONFIG_KM_NEW_ENV -CONFIG_KM_UBI_LINUX_MTD -CONFIG_KM_UBI_PARTITION_NAME_APP -CONFIG_KM_UBI_PARTITION_NAME_BOOT -CONFIG_KM_UBI_PART_BOOT_OPTS -CONFIG_KM_UIMAGE_NAME CONFIG_KSNET_CPSW_NUM_PORTS CONFIG_KSNET_MAC_ID_BASE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE From 3bcf9c08a3de030438fcb91b27bf38e3235aafc5 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:40 +0100 Subject: [PATCH 169/424] board/km/secu: migrate to use environment text files Instead of having these defines in a header file, move them to a simple text file. Signed-off-by: Holger Brunck --- board/keymile/secu1/socfpga_secu.env | 50 ++++++++++++++++++++++++ configs/socfpga_secu1_defconfig | 4 +- include/configs/socfpga_arria5_secu1.h | 53 -------------------------- scripts/config_whitelist.txt | 2 - 4 files changed, 52 insertions(+), 57 deletions(-) create mode 100644 board/keymile/secu1/socfpga_secu.env diff --git a/board/keymile/secu1/socfpga_secu.env b/board/keymile/secu1/socfpga_secu.env new file mode 100644 index 0000000000..147c4170ef --- /dev/null +++ b/board/keymile/secu1/socfpga_secu.env @@ -0,0 +1,50 @@ +altbootcmd=run bootcmd; +bootlimit=6 +bootnum=1 +bootretry=CONFIG_BOOT_RETRY_TIME + +develop=tftp 0x200000 scripts/develop-secu.txt && + env import -t 0x200000 ${filesize} && + saveenv && + reset + +fdt_addr=CONFIG_KM_FDT_ADDR +load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp +loadaddr=CONFIG_KM_KERNEL_ADDR +newenv=nand erase 0x100000 0x40000 +release=run newenv; reset +socfpga_legacy_reset_compat=1 +update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize} + +userload=ubi part nand.ubi && + ubi check rootfs$bootnum && + ubi read $fdt_addr dtb$bootnum && + ubi read $loadaddr kernel$bootnum + +userboot=setenv bootargs console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id="idq,regbank" + ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid ro + rootfstype=squashfs init=sbin/preinit; + bootz ${loadaddr} - ${fdt_addr} + +verify=y + +/* + * FPGA Remote Update related environment + * + * Note that since those commands access the FPGA, the HPS-to-FPGA bridges + * MUST have been previously enabled (for example with 'bridge enable'). + */ +rmtu_page=0xFF29000C +rmtu_reconfig=0xFF290018 +fpga_safebase=0x0 +fpga_userbase=0x2000000 + +_fpga_loaduser=echo "Loading FPGA USER image..." && + mw ${rmtu_page} ${fpga_userbase} && + mw ${rmtu_reconfig} 1 + +_fpga_loadsafe=echo "Loading FPGA SAFE image..." && + mw ${rmtu_page} ${fpga_safebase} && + mw ${rmtu_reconfig} 1 + + diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 7a805df5a3..6e4fe588a1 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -3,7 +3,7 @@ CONFIG_SYS_L2_PL310=y CONFIG_ARCH_SOCFPGA=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x800 -CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_secu1" @@ -24,7 +24,6 @@ CONFIG_BOOT_RETRY=y CONFIG_BOOT_RETRY_TIME=45 CONFIG_RESET_TO_RETRY=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 ubi.fm_autoconvert=1 uio_pdrv_genirq.of_id=\"idq,regbank\"" CONFIG_BOOTCOMMAND="setenv bootcmd 'bridge enable; if test ${bootnum} = 'b'; then run _fpga_loadsafe; else if test ${bootcount} -eq 4; then echo 'Switching copy...'; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; run _fpga_loaduser; fi;echo 'Booting bank $bootnum' && run userload && run userboot;' && setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && saveenv && saveenv && boot;" CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_secu1.dtb" CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -65,6 +64,7 @@ CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set +CONFIG_ENV_SOURCE_FILE="socfpga_secu" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/include/configs/socfpga_arria5_secu1.h b/include/configs/socfpga_arria5_secu1.h index 29b4b22b39..55168c2fb8 100644 --- a/include/configs/socfpga_arria5_secu1.h +++ b/include/configs/socfpga_arria5_secu1.h @@ -7,7 +7,6 @@ #define __CONFIG_SOCFPGA_SECU1_H__ #include -#include /* Eternal oscillator */ #define CFG_SYS_TIMER_RATE 40000000 @@ -23,58 +22,6 @@ */ #define CFG_SYS_I2C_RTC_ADDR 0x68 -/* Environment settings */ - -/* - * FPGA Remote Update related environment - * - * Note that since those commands access the FPGA, the HPS-to-FPGA - * bridges MUST have been previously enabled (for example - * with 'bridge enable'). - */ -#define FPGA_RMTU_ENV \ - "rmtu_page=0xFF29000C\0" \ - "rmtu_reconfig=0xFF290018\0" \ - "fpga_safebase=0x0\0" \ - "fpga_userbase=0x2000000\0" \ - "_fpga_loaduser=echo Loading FPGA USER image..." \ - " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \ - "_fpga_loadsafe=echo Loading FPGA SAFE image..." \ - " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \ - -#define CONFIG_KM_NEW_ENV \ - "newenv=" \ - "nand erase 0x100000 0x40000\0" - -#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "release=" \ - "run newenv; reset\0" \ - "develop=" \ - "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - FPGA_RMTU_ENV \ - CONFIG_KM_DEF_ENV_BOOTTARGETS \ - CONFIG_KM_NEW_ENV \ - "socfpga_legacy_reset_compat=1\0" \ - "altbootcmd=run bootcmd;\0" \ - "bootlimit=6\0" \ - "bootnum=1\0" \ - "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \ - "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \ - "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \ - "userload=ubi part nand.ubi &&" \ - "ubi check rootfs$bootnum &&" \ - "ubi read $fdt_addr dtb$bootnum &&" \ - "ubi read $loadaddr kernel$bootnum\0" \ - "userboot=setenv bootargs " CONFIG_BOOTARGS \ - " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \ - " ro rootfstype=squashfs init=sbin/preinit;" \ - "bootz ${loadaddr} - ${fdt_addr}\0" \ - "verify=y\0" - /* The rest of the configuration is shared */ #include diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f829a7927d..a863665b2f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -70,8 +70,6 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KM_DEF_ENV_BOOTTARGETS -CONFIG_KM_NEW_ENV CONFIG_KSNET_CPSW_NUM_PORTS CONFIG_KSNET_MAC_ID_BASE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE From 400d1a7c9427c14fe06ff913f63cf13b49f7f89f Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:41 +0100 Subject: [PATCH 170/424] board/km: remove obsolete ARCH_KIRKWOOD We already removed the support for these boards. Signed-off-by: Holger Brunck --- board/keymile/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 46d0897108..cd8a06e278 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -34,7 +34,6 @@ config KM_PHRAM config KM_RESERVED_PRAM hex "Reserved RAM" - default 0x801000 if ARCH_KIRKWOOD default 0x0 if MPC83xx default 0x1000 if MPC85xx || ARCH_LS1021A depends on !ARCH_SOCFPGA @@ -79,7 +78,7 @@ config SYS_CLIPS_BASE config KM_COMMON_ETH_INIT bool "Common Ethernet Initialization" - default y if ARCH_KIRKWOOD || MPC83xx + default y if MPC83xx default n if MPC85xx || ARCH_SOCFPGA || ARCH_LS1021A help Use the Ethernet initialization implemented in common code that @@ -101,7 +100,7 @@ config KM_MVEXTSW_ADDR config KM_IVM_BUS int "IVM I2C Bus" default 0 if ARCH_SOCFPGA - default 1 if ARCH_KIRKWOOD || MPC85xx || ARCH_LS1021A + default 1 if MPC85xx || ARCH_LS1021A default 2 if MPC83xx help Identifier number of I2C bus, where the inventory EEPROM is connected to. From 31464f9455ca16b6dd98e5469213c33d78fc0137 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:42 +0100 Subject: [PATCH 171/424] km/ppc: migrate all mpc83xx to DM_I2C Enable DM_I2C and I2C mux to get rid of the usage of the legacy i2c driver. Signed-off-by: Holger Brunck --- board/keymile/Kconfig | 3 +- board/keymile/km83xx/Makefile | 2 +- board/keymile/km83xx/km83xx_i2c.c | 73 ------------------------------- configs/kmcoge5ne_defconfig | 9 ++-- configs/kmeter1_defconfig | 9 ++-- configs/kmopti2_defconfig | 9 ++-- configs/kmsupx5_defconfig | 9 ++-- configs/kmtepr2_defconfig | 9 ++-- configs/tuge1_defconfig | 9 ++-- configs/tuxx1_defconfig | 9 ++-- include/configs/km/km-mpc83xx.h | 8 ---- 11 files changed, 23 insertions(+), 126 deletions(-) delete mode 100644 board/keymile/km83xx/km83xx_i2c.c diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index cd8a06e278..e5d7c80a86 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -100,8 +100,7 @@ config KM_MVEXTSW_ADDR config KM_IVM_BUS int "IVM I2C Bus" default 0 if ARCH_SOCFPGA - default 1 if MPC85xx || ARCH_LS1021A - default 2 if MPC83xx + default 1 if PPC || ARCH_LS1021A help Identifier number of I2C bus, where the inventory EEPROM is connected to. diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile index 0aef654987..bdb358e2d2 100644 --- a/board/keymile/km83xx/Makefile +++ b/board/keymile/km83xx/Makefile @@ -3,4 +3,4 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o +obj-y += km83xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c deleted file mode 100644 index b80672d1b4..0000000000 --- a/board/keymile/km83xx/km83xx_i2c.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - */ - -#include -#include -#include -#include -#include -#include "../common/common.h" - -static void i2c_write_start_seq(void) -{ - struct fsl_i2c_base *base; - base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + - CONFIG_SYS_FSL_I2C_OFFSET); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN)); -} - -int i2c_make_abort(void) -{ - struct fsl_i2c_base *base; - base = (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + - CONFIG_SYS_FSL_I2C_OFFSET); - uchar last; - int nbr_read = 0; - int i = 0; - int ret = 0; - - /* wait after each operation to finsh with a delay */ - out_8(&base->cr, (I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN | I2C_CR_MSTA)); - udelay(DELAY_ABORT_SEQ); - in_8(&base->dr); - udelay(DELAY_ABORT_SEQ); - last = in_8(&base->dr); - nbr_read++; - - /* - * do read until the last bit is 1, but stop if the full eeprom is - * read. - */ - while (((last & 0x01) != 0x01) && - (nbr_read < CONFIG_SYS_IVM_EEPROM_MAX_LEN)) { - udelay(DELAY_ABORT_SEQ); - last = in_8(&base->dr); - nbr_read++; - } - if ((last & 0x01) != 0x01) - ret = -2; - if ((last != 0xff) || (nbr_read > 1)) - printf("[INFO] i2c abort after %d bytes (0x%02x)\n", - nbr_read, last); - udelay(DELAY_ABORT_SEQ); - out_8(&base->cr, (I2C_CR_MEN)); - udelay(DELAY_ABORT_SEQ); - /* clear status reg */ - out_8(&base->sr, 0); - - for (i = 0; i < 5; i++) - i2c_write_start_seq(); - if (ret != 0) - printf("[ERROR] i2c abort failed after %d bytes (0x%02x)\n", - nbr_read, last); - - return ret; -} diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 6bfcee9ed2..9609f58fb4 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -219,13 +219,10 @@ CONFIG_SYS_OR3_PRELIM=0xF0000E25 CONFIG_SYS_BR4_PRELIM_BOOL=y CONFIG_SYS_BR4_PRELIM=0xB0000801 CONFIG_SYS_OR4_PRELIM=0xF0000E25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index b0af9e051b..bd3d6315b1 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -185,13 +185,10 @@ CONFIG_SYS_OR1_PRELIM=0xFC000E25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xA0000801 CONFIG_SYS_OR3_PRELIM=0xF0000E25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 9a1e7cbde3..de6d99e91e 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -200,13 +200,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xB0001001 CONFIG_SYS_OR3_PRELIM=0xF0000040 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index d981e51223..a231510a76 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -177,13 +177,10 @@ CONFIG_SYS_OR1_PRELIM=0xF8000E25 CONFIG_SYS_BR2_PRELIM_BOOL=y CONFIG_SYS_BR2_PRELIM=0xA0000801 CONFIG_SYS_OR2_PRELIM=0xF0000C25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 18a464c0ae..e6beb62f86 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -199,13 +199,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xB0001001 CONFIG_SYS_OR3_PRELIM=0xF0000040 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index dbd832c9b7..83120759b1 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -177,13 +177,10 @@ CONFIG_SYS_OR1_PRELIM=0xF8000E25 CONFIG_SYS_BR2_PRELIM_BOOL=y CONFIG_SYS_BR2_PRELIM=0xA0000801 CONFIG_SYS_OR2_PRELIM=0xF0000C25 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 1b034a21a7..ee1640608d 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -201,13 +201,10 @@ CONFIG_SYS_OR2_PRELIM=0xF0000C25 CONFIG_SYS_BR3_PRELIM_BOOL=y CONFIG_SYS_BR3_PRELIM=0xB0000801 CONFIG_SYS_OR3_PRELIM=0xF0000E24 -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y -CONFIG_SYS_FSL_I2C_OFFSET=0x3000 -CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y -CONFIG_SYS_FSL_I2C2_OFFSET=0x3100 -CONFIG_SYS_I2C_SLAVE=0x7F -CONFIG_SYS_I2C_SPEED=200000 +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 7f1839f463..1f03f95ace 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -48,14 +48,6 @@ #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } -/* I2C */ -#define CFG_SYS_NUM_I2C_BUSES 4 -#define CFG_SYS_I2C_MAX_HOPS 1 -#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - #if defined(CONFIG_CMD_NAND) #define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE #endif From aeb13924f4579bd200d538fcb82628101822a833 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Dec 2022 18:22:43 +0100 Subject: [PATCH 172/424] km/mpc8360: remove unused CONFIG_SYS_PAXE defines These are unused defines and can be dropped. Signed-off-by: Holger Brunck --- include/configs/km/km-mpc8360.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index 5c9f912383..04d3d352ee 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -66,9 +66,3 @@ #define CFG_SYS_DDR_TIMING_3 0x00000000 -/* EEprom support */ - -/* - * PAXE on the local bus CS3 - */ -#define CFG_SYS_PAXE_BASE 0xA0000000 From f2d6c888f471837c565719097ca96f8f2b9dd215 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 25 Nov 2022 09:54:51 +0200 Subject: [PATCH 173/424] dt-bindings: mfd: add at91-usart.h from Linux Copy include file dt-bindings/mfd/at91-usart.h from Linux Signed-off-by: Eugen Hristev Reviewed-by: Claudiu Beznea --- include/dt-bindings/mfd/at91-usart.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 include/dt-bindings/mfd/at91-usart.h diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h new file mode 100644 index 0000000000..2de5bc312e --- /dev/null +++ b/include/dt-bindings/mfd/at91-usart.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides macros for AT91 USART DT bindings. + * + * Copyright (C) 2018 Microchip Technology + * + * Author: Radu Pirea + * + */ + +#ifndef __DT_BINDINGS_AT91_USART_H__ +#define __DT_BINDINGS_AT91_USART_H__ + +#define AT91_USART_MODE_SERIAL 0 +#define AT91_USART_MODE_SPI 1 + +#endif /* __DT_BINDINGS_AT91_USART_H__ */ From 9859b9a7224b9a2b51d2d6168bbd0164f4885a0e Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 25 Nov 2022 09:54:52 +0200 Subject: [PATCH 174/424] sysreset: at91: add compatible with microchip, sama7g5-rstc As documented in bindings doc in kernel 6.0: https://elixir.bootlin.com/linux/v6.0/source/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml Signed-off-by: Eugen Hristev Reviewed-by: Claudiu Beznea --- drivers/sysreset/sysreset_at91.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c index 24b87ee987..6119a29927 100644 --- a/drivers/sysreset/sysreset_at91.c +++ b/drivers/sysreset/sysreset_at91.c @@ -59,6 +59,7 @@ static struct sysreset_ops at91_sysreset = { static const struct udevice_id a91_sysreset_ids[] = { { .compatible = "atmel,sama5d3-rstc" }, { .compatible = "microchip,sam9x60-rstc" }, + { .compatible = "microchip,sama7g5-rstc" }, { } }; From 4df35b38d12c0c5630efe373870b5f557262af57 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 25 Nov 2022 09:54:53 +0200 Subject: [PATCH 175/424] ARM: dts: at91: sama7g5/sama7g5ek: align DT with kernel 6.1 Align the DT with current Linux 6.1 tree, wherever possible. Signed-off-by: Eugen Hristev Reviewed-by: Claudiu Beznea --- arch/arm/dts/at91-sama7g5ek.dts | 23 +++++++++++------------ arch/arm/dts/sama7g5.dtsi | 27 ++++++++++++++++----------- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts index aed84f15a1..9b247fcaf6 100644 --- a/arch/arm/dts/at91-sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -45,13 +45,13 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; - bp1 { + button { label = "PB_USER"; gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>; linux,code = ; @@ -244,8 +244,8 @@ regulators { vdd_3v3: VDD_IO { regulator-name = "VDD_IO"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -264,8 +264,8 @@ vddioddr: VDD_DDR { regulator-name = "VDD_DDR"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1450000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -285,8 +285,8 @@ vddcore: VDD_CORE { regulator-name = "VDD_CORE"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-always-on; @@ -306,7 +306,7 @@ vddcpu: VDD_OTHER { regulator-name = "VDD_OTHER"; regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1850000>; + regulator-max-microvolt = <1250000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; regulator-ramp-delay = <3125>; @@ -326,8 +326,8 @@ vldo1: LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3700000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-always-on; regulator-state-standby { @@ -707,7 +707,6 @@ ck_cd_rstn_vddsel { pinmux = , , - , ; slew-rate = <0>; bias-pull-up; diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi index d38090d7dd..6388a60e53 100644 --- a/arch/arm/dts/sama7g5.dtsi +++ b/arch/arm/dts/sama7g5.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include / { model = "Microchip SAMA7G5 family SoC"; @@ -195,11 +196,11 @@ , , ; - clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; }; pmc: pmc@e0018000 { @@ -211,6 +212,13 @@ clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; }; + reset_controller: reset-controller@e001d000 { + compatible = "microchip,sama7g5-rstc"; + reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + shdwc: shdwc@e001d010 { compatible = "microchip,sama7g5-shdwc", "syscon"; reg = <0xe001d010 0x10>; @@ -229,13 +237,6 @@ clocks = <&clk32k 0>; }; - reset_controller: rstc@e001d000 { - compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc"; - reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; - #reset-cells = <1>; - clocks = <&clk32k 0>; - }; - clk32k: clock-controller@e001d050 { compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d050 0x4>; @@ -620,6 +621,7 @@ uart0: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = ; interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "usart"; @@ -668,6 +670,7 @@ uart3: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = ; interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "usart"; @@ -711,6 +714,7 @@ uart4: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = ; interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "usart"; @@ -736,6 +740,7 @@ uart7: serial@200 { compatible = "atmel,at91sam9260-usart"; reg = <0x200 0x200>; + atmel,usart-mode = ; interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; clock-names = "usart"; @@ -884,9 +889,9 @@ #address-cells = <1>; #size-cells = <0>; atmel,fifo-size = <32>; - dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, - <&dma0 AT91_XDMAC_DT_PERID(28)>; - dma-names = "rx", "tx"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>, + <&dma0 AT91_XDMAC_DT_PERID(27)>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From a60c5a986eedd5920cd2c2ba79ecece85dbb87b5 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Fri, 2 Dec 2022 09:47:19 +0200 Subject: [PATCH 176/424] ARM: mach-at91: add support for sama7g5 chip id and extended id definition Add SAMA7G5 series chip id definitions to align with linux SoC driver. Add support for SAMA7G5 System-In-Package (SIP): SAMA7G54D1G, SAMA7G54D2G, SAMA7G54D4G. Signed-off-by: Mihai Sain --- arch/arm/mach-at91/armv7/sama7g5_devices.c | 26 +++++++++++++++++++- arch/arm/mach-at91/include/mach/sama7g5.h | 28 ++++++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c index 0b702c7fb7..6f2c1fc914 100644 --- a/arch/arm/mach-at91/armv7/sama7g5_devices.c +++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c @@ -4,7 +4,31 @@ * Eugen Hristev */ +#include + char *get_cpu_name(void) { - return "SAMA7G5"; + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama7g5()) + switch (extension_id) { + case ARCH_EXID_SAMA7G51: + return "SAMA7G51"; + case ARCH_EXID_SAMA7G52: + return "SAMA7G52"; + case ARCH_EXID_SAMA7G53: + return "SAMA7G53"; + case ARCH_EXID_SAMA7G54: + return "SAMA7G54"; + case ARCH_EXID_SAMA7G54_D1G: + return "SAMA7G54 1Gb DDR3L SiP"; + case ARCH_EXID_SAMA7G54_D2G: + return "SAMA7G54 2Gb DDR3L SiP"; + case ARCH_EXID_SAMA7G54_D4G: + return "SAMA7G54 4Gb DDR3L SiP"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type"; } diff --git a/arch/arm/mach-at91/include/mach/sama7g5.h b/arch/arm/mach-at91/include/mach/sama7g5.h index ae43e8700b..621a26f6eb 100644 --- a/arch/arm/mach-at91/include/mach/sama7g5.h +++ b/arch/arm/mach-at91/include/mach/sama7g5.h @@ -67,7 +67,35 @@ #define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 +/* SAMA7G5 series chip id definitions */ +#define ARCH_ID_SAMA7G5 0x80162100 +#define ARCH_EXID_SAMA7G51 0x00000003 +#define ARCH_EXID_SAMA7G52 0x00000002 +#define ARCH_EXID_SAMA7G53 0x00000001 +#define ARCH_EXID_SAMA7G54 0x00000000 +#define ARCH_EXID_SAMA7G54_D1G 0x00000018 +#define ARCH_EXID_SAMA7G54_D2G 0x00000020 +#define ARCH_EXID_SAMA7G54_D4G 0x00000028 + +#define cpu_is_sama7g5() (get_chip_id() == ARCH_ID_SAMA7G5) +#define cpu_is_sama7g51() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G51)) +#define cpu_is_sama7g52() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G52)) +#define cpu_is_sama7g53() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G53)) +#define cpu_is_sama7g54() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54)) +#define cpu_is_sama7g54d1g() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D1G)) +#define cpu_is_sama7g54d2g() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D2G)) +#define cpu_is_sama7g54d4g() (cpu_is_sama7g5() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D4G)) + #ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); char *get_cpu_name(void); #endif From 8374617637c5c26438ebea6a399aba69ba00054a Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 12 Dec 2022 11:59:16 +0200 Subject: [PATCH 177/424] ARM: dts: at91: sama5d2: fix wrong interrupt-cells property The PMC node is not an interrupt provider, so it must not have interrupt-cells. This fixes the warning (on newer DTC): arch/arm/dts/sama5d2.dtsi:82.22-602.6: Warning (interrupt_provider): /ahb/apb/pmc@f0014000: '#interrupt-cells' found, but node is not an interrupt provider Fixes: 2c4b2dd289 ("ARM: at91/dt: Add device tree for SAMA5D2 Xplained") Signed-off-by: Eugen Hristev Reviewed-by: Claudiu Beznea --- arch/arm/dts/sama5d2.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 790b746ed1..187c2ff2fb 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -84,7 +84,6 @@ reg = <0xf0014000 0x160>; #address-cells = <1>; #size-cells = <0>; - #interrupt-cells = <1>; u-boot,dm-pre-reloc; main: mainck { From 7d212af2b1cf19c643368668fafd2525fda26277 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:11 -0500 Subject: [PATCH 178/424] usb: Update USB_STORAGE dependencies As it's no longer possible to have !DM_USB set, we can remove these dependencies. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- common/spl/Kconfig | 2 +- drivers/usb/Kconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 1657c2ca96..f0f7acead7 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1347,7 +1347,7 @@ config SPL_USB_HOST config SPL_USB_STORAGE bool "Support loading from USB" - depends on SPL_USB_HOST && !(BLK && !DM_USB) + depends on SPL_USB_HOST help Enable support for USB devices in SPL. This allows use of USB devices such as hard drives and flash drivers for loading U-Boot. diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 3afb45d5cc..8efd461457 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -93,7 +93,6 @@ comment "USB peripherals" config USB_STORAGE bool "USB Mass Storage support" - depends on !(BLK && !DM_USB) ---help--- Say Y here if you want to connect USB mass storage devices to your board's USB port. From 4475d017c57f93dca61c08563b3ff4202d38a127 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:12 -0500 Subject: [PATCH 179/424] arm: exynos5: Migrate USB_BOOTING to Kconfig This symbol is enabled for all exynos5 platforms, move to Kconfig and select it. Cc: Jaehoon Chung Cc: Minkyu Kang Signed-off-by: Tom Rini --- arch/arm/mach-exynos/Kconfig | 4 ++++ include/configs/exynos5-common.h | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 29e35e443c..383af83066 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -4,6 +4,9 @@ config BOARD_COMMON def_bool y depends on !TARGET_SMDKV310 && !TARGET_ARNDALE +config USB_BOOTING + bool + choice prompt "EXYNOS architecture type select" optional @@ -24,6 +27,7 @@ config ARCH_EXYNOS5 select BOARD_EARLY_INIT_F select CPU_V7A select SHA_HW_ACCEL + select USB_BOOTING imply CMD_HASH imply CRC32_VERIFY imply HASH_VERIFY diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index dd322c2b3a..9b5c329bda 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -58,7 +58,6 @@ /* USB */ /* USB boot mode */ -#define CONFIG_USB_BOOTING #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 From b41eb5a27e8cf6d32e68ea70ab0b5226329db154 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:13 -0500 Subject: [PATCH 180/424] p1_p2_rdb: Remove unused environment sections The CONFIG_USB_FAT_BOOT, CONFIG_USB_EXT2_BOOT and CONFIG_NORBOOT defines are not referenced anywhere, so remove them. Signed-off-by: Tom Rini --- include/configs/p1_p2_rdb_pc.h | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 49c5aef305..f86b96b214 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -441,29 +441,4 @@ RST_PCIE_CMD(pciboot) \ RST_DEF_CMD(defboot) \ "" -#define CONFIG_USB_FAT_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"fatload usb 0:2 $loadaddr $bootfile;" \ -"fatload usb 0:2 $fdtaddr $fdtfile;" \ -"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_USB_EXT2_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"ext2load usb 0:4 $loadaddr $bootfile;" \ -"ext2load usb 0:4 $fdtaddr $fdtfile;" \ -"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NORBOOT \ -"setenv bootargs root=/dev/$jffs2nor rw " \ -"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ -"bootm $norbootaddr - $norfdtaddr" - #endif /* __CONFIG_H */ From 5732cf24ddfe010cd18de2233b9f175fa11f004f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:14 -0500 Subject: [PATCH 181/424] x530: Remove unused symbols The symbols CONFIG_UBI_PART and CONFIG_UBIFS_VOLUME are not referenced anywhere, drop them. Signed-off-by: Tom Rini --- include/configs/x530.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/x530.h b/include/configs/x530.h index c213dc6074..4cf41f52fd 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -51,7 +51,4 @@ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" -#define CONFIG_UBI_PART user -#define CONFIG_UBIFS_VOLUME user - #endif /* _CONFIG_X530_H */ From 5125e136a9a667ace526fbb968500ff39011e6b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:15 -0500 Subject: [PATCH 182/424] arm: trats2: Set mmcdev directly Only this platform sets mmcdev via CONFIG_MMC_DEFAULT_DEV so we hard-code that default directly. Signed-off-by: Tom Rini --- include/configs/exynos4-common.h | 3 --- include/configs/s5p_goni.h | 3 --- include/configs/trats2.h | 2 +- 3 files changed, 1 insertion(+), 7 deletions(-) diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 81f450cde6..bf965e5ced 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -10,9 +10,6 @@ #include "exynos-common.h" -/* SD/MMC configuration */ -#define CONFIG_MMC_DEFAULT_DEV 0 - #define DFU_DEFAULT_POLL_TIMEOUT 300 /* USB Samsung's IDs */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index fdade1ee66..97f5dd0e47 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -119,9 +119,6 @@ #define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */ #define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */ -/* FLASH and environment organization */ -#define CONFIG_MMC_DEFAULT_DEV 0 - #define CFG_SYS_ONENAND_BASE 0xB0000000 #endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 0aa331e393..4d39b4005b 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -81,7 +81,7 @@ "${kernelname}\0" \ "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ "${fdtfile}\0" \ - "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ + "mmcdev=0\0" \ "mmcbootpart=2\0" \ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ From 2440b5bb523b004af43a1090e1a4134231702416 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:16 -0500 Subject: [PATCH 183/424] Convert CONFIG_HSMMC2_8BIT to Kconfig This converts the following to Kconfig: CONFIG_HSMMC2_8BIT Signed-off-by: Tom Rini --- configs/am335x_shc_defconfig | 1 + configs/am335x_shc_ict_defconfig | 1 + configs/am335x_shc_netboot_defconfig | 1 + configs/am335x_shc_sdboot_defconfig | 1 + configs/am57xx_evm_defconfig | 1 + configs/am57xx_hs_evm_defconfig | 1 + configs/am57xx_hs_evm_usb_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/dra7xx_evm_defconfig | 1 + configs/dra7xx_hs_evm_defconfig | 1 + configs/dra7xx_hs_evm_usb_defconfig | 1 + configs/omap5_uevm_defconfig | 1 + drivers/mmc/Kconfig | 5 +++++ include/configs/am335x_shc.h | 2 -- include/configs/am57xx_evm.h | 3 --- include/configs/cm_t43.h | 2 -- include/configs/dra7xx_evm.h | 3 --- include/configs/omap5_uevm.h | 3 --- 18 files changed, 17 insertions(+), 13 deletions(-) diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 9d81f8d0ad..5a6db3ce6a 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index de83139d15..aa55a7a61e 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -70,6 +70,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index e1dfd6a9bd..cb73b104d2 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -73,6 +73,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 74f0834466..f28e6e6b16 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_SLAVE=0x1 CONFIG_SYS_I2C_SPEED=400000 CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_SMSC=y CONFIG_MII=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 054e9747a8..03f799506e 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -92,6 +92,7 @@ CONFIG_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 02a2543a3f..86bcfe85ae 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -89,6 +89,7 @@ CONFIG_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 84eca42aac..eedbfd0d86 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -88,6 +88,7 @@ CONFIG_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 867ca30320..6eda33ebbc 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -76,6 +76,7 @@ CONFIG_SYS_RX_ETH_BUFFER=64 CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index d91cf3e130..41df92f3d2 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -101,6 +101,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 195bc0e4ee..7392b73085 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -96,6 +96,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 99cdbbc02f..1bda6db7a3 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -92,6 +92,7 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=76800000 diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 91878c11ed..9d5c515a44 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -52,6 +52,7 @@ CONFIG_SYS_I2C_LEGACY=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y +CONFIG_HSMMC2_8BIT=y CONFIG_PALMAS_POWER=y CONFIG_SCSI=y CONFIG_SCSI_AHCI_PLAT=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index bf4d994ff6..698c91c57f 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -385,6 +385,11 @@ config MMC_OMAP36XX_PINS If unsure, say N. +config HSMMC2_8BIT + bool "Enable 8-bit interface for eMMC (interface #2)" + depends on MMC_OMAP_HS && (OMAP44XX || OMAP54XX || DRA7XX || AM33XX || \ + AM43XX || ARCH_KEYSTONE) + config SH_SDHI bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support" depends on ARCH_RMOBILE diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 452887d699..70645edcb1 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -20,8 +20,6 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_HSMMC2_8BIT - #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index dacfd41cce..ba91f2b054 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -35,9 +35,6 @@ #include -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - /* CPSW Ethernet */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index fcc17fc6b7..8a18d6f97a 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -36,8 +36,6 @@ * we don't need to do it twice. */ -#define CONFIG_HSMMC2_8BIT - #include #define V_OSCK 24000000 /* Clock output from T2 */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index ac3fcacc68..b8f518612e 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -48,9 +48,6 @@ #include -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - /* * Default to using SPI for environment, etc. * 0x000000 - 0x040000 : QSPI.SPL (256KiB) diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d7fa2d4391..39d0b40313 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -32,9 +32,6 @@ /* MMC ENV related defines */ -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - /* Required support for the TCA642X GPIO we have on the uEVM */ #define CFG_SYS_I2C_TCA642X_BUS_NUM 4 #define CFG_SYS_I2C_TCA642X_ADDR 0x22 From 6bd2372094ab4827547ec0d3e5a258b72810cafd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:17 -0500 Subject: [PATCH 184/424] env: Rework ENV_IS_EMBEDDED and related logic slightly - Drop CONFIG_BUILD_ENVCRC as this is never set directly but instead means ENV_IS_EMBEDDED, so reference that in code and rename the Makefile usage to BUILD_ENVCRC. - Remove extra-$(CONFIG_ENV_IS_EMBEDDED) line as it could never be true, and likely why there is an extra- line for CONFIG_ENV_IS_IN_FLASH (the only use case today of embedded environments). - With these slight changes we can then see that using the calculated symbol of ENV_IS_EMBEDDED is the right thing to use in any code which needs to know this situation and can remove CONFIG_ENV_IS_EMBEDDED entirely. Signed-off-by: Tom Rini --- README | 5 ----- env/Makefile | 1 - env/embedded.c | 2 +- include/env_internal.h | 23 +---------------------- tools/Makefile | 5 ++--- tools/envcrc.c | 10 +++------- 6 files changed, 7 insertions(+), 39 deletions(-) diff --git a/README b/README index 103562bbbe..3fef1d2afa 100644 --- a/README +++ b/README @@ -1542,11 +1542,6 @@ The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: -- CONFIG_BUILD_ENVCRC: - - Builds up envcrc with the target environment so that external utils - may easily extract it and embed it in final U-Boot images. - BE CAREFUL! The first access to the environment happens quite early in U-Boot initialization (when we try to get the setting of for the console baudrate). You *MUST* have mapped your NVRAM area then, or diff --git a/env/Makefile b/env/Makefile index c4ad654328..bb6e24b396 100644 --- a/env/Makefile +++ b/env/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o ifndef CONFIG_SPL_BUILD obj-y += callback.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o -extra-$(CONFIG_ENV_IS_EMBEDDED) += embedded.o obj-$(CONFIG_ENV_IS_IN_EEPROM) += embedded.o extra-$(CONFIG_ENV_IS_IN_FLASH) += embedded.o obj-$(CONFIG_ENV_IS_IN_NVRAM) += embedded.o diff --git a/env/embedded.c b/env/embedded.c index 27fb45bf8c..7cbe54c56e 100644 --- a/env/embedded.c +++ b/env/embedded.c @@ -27,7 +27,7 @@ * Generate embedded environment table * inside U-Boot image, if needed. */ -#if defined(ENV_IS_EMBEDDED) || defined(CONFIG_BUILD_ENVCRC) +#if defined(ENV_IS_EMBEDDED) /* * Put the environment in the .text section when we are building * U-Boot proper. The host based program "tools/envcrc" does not need diff --git a/include/env_internal.h b/include/env_internal.h index f30fd6159d..aee6b3e48f 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -41,10 +41,6 @@ (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) # define ENV_IS_EMBEDDED # endif -# ifdef CONFIG_ENV_IS_EMBEDDED -# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config" -# error "it is calculated automatically for you" -# endif #endif /* CONFIG_ENV_IS_IN_FLASH */ #if defined(CONFIG_ENV_IS_IN_NAND) @@ -57,23 +53,6 @@ extern unsigned long nand_env_oob_offset; # endif /* CONFIG_ENV_OFFSET_OOB */ #endif /* CONFIG_ENV_IS_IN_NAND */ -/* - * For the flash types where embedded env is supported, but it cannot be - * calculated automatically (i.e. NAND), take the board opt-in. - */ -#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED) -# define ENV_IS_EMBEDDED -#endif - -/* The build system likes to know if the env is embedded */ -#ifdef DO_DEPS_ONLY -# ifdef ENV_IS_EMBEDDED -# ifndef CONFIG_ENV_IS_EMBEDDED -# define CONFIG_ENV_IS_EMBEDDED -# endif -# endif -#endif - #include "compiler.h" #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT @@ -88,7 +67,7 @@ extern unsigned long nand_env_oob_offset; * If the environment is in RAM, allocate extra space for it in the malloc * region. */ -#if defined(CONFIG_ENV_IS_EMBEDDED) +#if defined(ENV_IS_EMBEDDED) #define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN #elif (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE < CONFIG_SYS_MONITOR_BASE) || \ (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) || \ diff --git a/tools/Makefile b/tools/Makefile index 80bc62befc..edfa40903d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -36,21 +36,20 @@ endif subdir-$(HOST_TOOLS_ALL) += gdb # Merge all the different vars for envcrc into one -ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y -CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y) +BUILD_ENVCRC ?= $(ENVCRC-y) hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo HOSTCFLAGS_bmp_logo.o := -pedantic -hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc +hostprogs-$(BUILD_ENVCRC) += envcrc envcrc-objs := envcrc.o lib/crc32.o env/embedded.o lib/sha1.o hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr diff --git a/tools/envcrc.c b/tools/envcrc.c index a021c785ae..550f31038b 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -40,10 +40,6 @@ # endif #endif /* CONFIG_ENV_IS_IN_FLASH */ -#if defined(ENV_IS_EMBEDDED) && !defined(CONFIG_BUILD_ENVCRC) -# define CONFIG_BUILD_ENVCRC -#endif - #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else @@ -53,17 +49,17 @@ #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) -#ifdef CONFIG_BUILD_ENVCRC +#ifdef ENV_IS_EMBEDDED # include extern unsigned int env_size; extern env_t embedded_environment; -#endif /* CONFIG_BUILD_ENVCRC */ +#endif /* ENV_IS_EMBEDDED */ extern uint32_t crc32(uint32_t, const unsigned char *, unsigned int); int main (int argc, char **argv) { -#ifdef CONFIG_BUILD_ENVCRC +#ifdef ENV_IS_EMBEDDED unsigned char pad = 0x00; uint32_t crc; unsigned char *envptr = (unsigned char *)&embedded_environment, From 9b0240f8c6a1caa42da73835090fcb6db60f3d23 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:18 -0500 Subject: [PATCH 185/424] Convert CONFIG_DM9000_BYTE_SWAPPED et al to Kconfig This converts the following to Kconfig: CONFIG_DM9000_BYTE_SWAPPED CONFIG_DM9000_NO_SROM CONFIG_DM9000_USE_16BIT CONFIG_DM9000_DEBUG CONFIG_MXC_GPT_HCLK CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC Signed-off-by: Tom Rini --- arch/arm/Kconfig | 2 ++ arch/arm/mach-imx/Kconfig | 3 +++ board/davinci/da8xxevm/Kconfig | 3 +++ board/timll/devkit8000/devkit8000.c | 7 +++---- configs/M5253DEMO_defconfig | 1 + configs/at91sam9261ek_dataflash_cs0_defconfig | 2 ++ configs/at91sam9261ek_dataflash_cs3_defconfig | 2 ++ configs/at91sam9261ek_nandflash_defconfig | 2 ++ configs/devkit8000_defconfig | 2 ++ drivers/net/Kconfig | 12 ++++++++++++ include/configs/M5253DEMO.h | 6 ------ include/configs/at91sam9261ek.h | 7 ------- include/configs/brppt2.h | 2 -- include/configs/ci20.h | 7 ------- include/configs/devkit8000.h | 11 ----------- include/configs/mx6_common.h | 1 - include/configs/mx7_common.h | 1 - include/configs/omapl138_lcdk.h | 1 - 18 files changed, 32 insertions(+), 40 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d3b11b8495..8381e09e10 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -915,6 +915,7 @@ config ARCH_MX7 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX + select MXC_GPT_HCLK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -928,6 +929,7 @@ config ARCH_MX6 select CPU_V7A select GPIO_EXTRA_HEADER select MACH_IMX + select MXC_GPT_HCLK select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ee5f1996a8..3266545c26 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -18,6 +18,9 @@ config SYSCOUNTER_TIMER config GPT_TIMER bool +config MXC_GPT_HCLK + bool + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index c5499a63fd..34055f6975 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -37,6 +37,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "omapl138_lcdk" +config NAND_6BYTES_OOB_FREE_10BYTES_ECC + def_bool y + endif source "board/ti/common/Kconfig" diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 0808ca1a54..06009d8ad5 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -76,10 +76,11 @@ int board_init(void) } /* Configure GPMC registers for DM9000 */ +#define DM9000_BASE 0x2c000000 static void gpmc_dm9000_config(void) { enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], - CONFIG_DM9000_BASE, GPMC_SIZE_16M); + DM9000_BASE, GPMC_SIZE_16M); } /* @@ -100,9 +101,7 @@ int misc_init_r(void) #endif #ifdef CONFIG_DRIVER_DM9000 - /* Configure GPMC registers for DM9000 */ - enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], - CONFIG_DM9000_BASE, GPMC_SIZE_16M); + gpmc_dm9000_config(); /* Use OMAP DIE_ID as MAC address */ if (!eth_env_get_enetaddr("ethaddr", enetaddr)) { diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 581023f967..2684ce05f2 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -44,4 +44,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_MAX_FLASH_SECT=2048 CONFIG_USE_SYS_MAX_FLASH_BANKS=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_BYTE_SWAPPED=y CONFIG_MCFUART=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index c6c83b8da3..a398e6d97a 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index 1c16d26c82..1b464ff292 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -54,6 +54,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 8dbcb27f95..f232624942 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -52,6 +52,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_DATAFLASH=y CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_PINCTRL=y CONFIG_PINCTRL_AT91=y CONFIG_DM_SERIAL=y diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 8347b67681..6fd4410df5 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -84,4 +84,6 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 CONFIG_DRIVER_DM9000=y +CONFIG_DM9000_NO_SROM=y +CONFIG_DM9000_USE_16BIT=y CONFIG_JFFS2_NAND=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 4e5da5ab72..0607f959da 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -198,6 +198,18 @@ config DRIVER_DM9000 help The Davicom DM9000 parallel bus external ethernet interface chip. +config DM9000_BYTE_SWAPPED + bool "Byte swapped access for DM9000" + depends on DRIVER_DM9000 + +config DM9000_NO_SROM + bool "No SROM on DM9000" + depends on DRIVER_DM9000 + +config DM9000_USE_16BIT + bool "Use 16bit access in DM9000" + depends on DRIVER_DM9000 + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" select PHYLIB diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 7e37c6d119..ad55938348 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -20,12 +20,6 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CFG_SYS_CS1_BASE | 0x300) -# define DM9000_IO CONFIG_DM9000_BASE -# define DM9000_DATA (CONFIG_DM9000_BASE + 4) -# undef CONFIG_DM9000_DEBUG -# define CONFIG_DM9000_BYTE_SWAPPED - # define CONFIG_OVERWRITE_ETHADDR_ONCE # define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 56247e390b..39f6ff8a72 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -34,13 +34,6 @@ #endif -/* Ethernet */ -#define CONFIG_DM9000_BASE 0x30000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_DM9000_USE_16BIT -#define CONFIG_DM9000_NO_SROM - /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index d35c7c4a59..80104b2d31 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -16,8 +16,6 @@ #define CFG_SYS_PL310_BASE L2_PL310_BASE #endif /* !CONFIG_SYS_L2CACHE_OFF */ -#define CONFIG_MXC_GPT_HCLK - /* MMC */ /* Boot */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 3329c24fa6..446d5c4f3d 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -17,11 +17,4 @@ /* NS16550-ish UARTs */ #define CFG_SYS_NS16550_CLK 48000000 -/* Ethernet: davicom DM9000 */ -#define CONFIG_DM9000_BASE 0xb6000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* Miscellaneous configuration options */ - #endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 46410595c2..e3621fd6f9 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -16,17 +16,6 @@ #include -/* Hardware drivers */ -/* DM9000 */ -#define CONFIG_DM9000_BASE 0x2c000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) -#define CONFIG_DM9000_USE_16BIT 1 -#define CONFIG_DM9000_NO_SROM 1 -#undef CONFIG_DM9000_DEBUG - -/* TWL4030 */ - /* BOOTP/DHCP options */ #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 245530aa64..dd8cabc2e9 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -16,7 +16,6 @@ #endif #endif -#define CONFIG_MXC_GPT_HCLK #include #include diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index d5af699010..6e14b4fbf0 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -14,7 +14,6 @@ #include /* Timer settings */ -#define CONFIG_MXC_GPT_HCLK #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ /* Miscellaneous configurable options */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 788a111386..f19211fe64 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -109,7 +109,6 @@ #define CFG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE #define CFG_SYS_NAND_MASK_CLE 0x10 #define CFG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CFG_SYS_NAND_U_BOOT_SIZE SZ_512K #define CFG_SYS_NAND_U_BOOT_DST 0xc1080000 #define CFG_SYS_NAND_U_BOOT_START CFG_SYS_NAND_U_BOOT_DST From 21491883d2af674f698a94699a5a8b7356d02adf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:19 -0500 Subject: [PATCH 186/424] fec_mxc: Remove CONFIG_FEC_FIXED_SPEED support This option is only used on one platform currently. However, with PHYLIB enabled, which this platform also does, this option is not checked and the functional use case is handled. Remove this code. Signed-off-by: Tom Rini --- doc/README.fec_mxc | 6 ------ drivers/net/fec_mxc.c | 4 ---- include/configs/brppt2.h | 3 --- 3 files changed, 13 deletions(-) diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index d17dfb676f..4e890d348f 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -22,12 +22,6 @@ CONFIG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. -CONFIG_FEC_FIXED_SPEED - Optional, selects a fixed speed on the MAC interface without asking some - phy. This is usefull if there is a direct MAC <-> MAC connection, for - example if the CPU is connected directly via the RGMII interface to a - ethernet-switch. - Reading the ethaddr from the SoC eFuses: if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the ethaddr variable, then its value gets read from the corresponding eFuses in diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index a61a1fc757..9cb235ad5e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -268,7 +268,6 @@ static int miiphy_restart_aneg(struct eth_device *dev) return ret; } -#ifndef CONFIG_FEC_FIXED_SPEED static int miiphy_wait_aneg(struct eth_device *dev) { uint32_t start; @@ -294,7 +293,6 @@ static int miiphy_wait_aneg(struct eth_device *dev) return 0; } -#endif /* CONFIG_FEC_FIXED_SPEED */ #endif static int fec_rx_task_enable(struct fec_priv *fec) @@ -536,8 +534,6 @@ static int fec_open(struct udevice *dev) } speed = fec->phydev->speed; } -#elif CONFIG_FEC_FIXED_SPEED - speed = CONFIG_FEC_FIXED_SPEED; #else miiphy_wait_aneg(edev); speed = miiphy_speed(edev->name, fec->phy_id); diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 80104b2d31..984602c2cf 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -78,9 +78,6 @@ BUR_COMMON_ENV \ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* Ethernet */ -#define CONFIG_FEC_FIXED_SPEED _1000BASET - /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) From 98fbad631f9973eb763d83571ec8dde00a94a76c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:20 -0500 Subject: [PATCH 187/424] Convert CONFIG_FLASH_SHOW_PROGRESS to Kconfig This converts the following to Kconfig: CONFIG_FLASH_SHOW_PROGRESS Signed-off-by: Tom Rini --- README | 5 ----- configs/3c120_defconfig | 1 + configs/M5208EVBE_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5249EVB_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/M5282EVB_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/MCR3000_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + configs/ae350_rv64_xip_defconfig | 1 + configs/amcore_defconfig | 1 + configs/astro_mcf5373l_defconfig | 1 + configs/at91sam9263ek_norflash_boot_defconfig | 1 + configs/at91sam9263ek_norflash_defconfig | 1 + configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston32r6_defconfig | 1 + configs/boston32r6el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + configs/boston64r6_defconfig | 1 + configs/boston64r6el_defconfig | 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_wap5813n_ram_defconfig | 1 + configs/da850evm_direct_nor_defconfig | 1 + configs/devkit3250_defconfig | 1 + configs/gazerbeam_defconfig | 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/integratorap_cm720t_defconfig | 1 + configs/integratorap_cm920t_defconfig | 1 + configs/integratorap_cm926ejs_defconfig | 1 + configs/integratorap_cm946es_defconfig | 1 + configs/integratorcp_cm1136_defconfig | 1 + configs/integratorcp_cm920t_defconfig | 1 + configs/integratorcp_cm926ejs_defconfig | 1 + configs/integratorcp_cm946es_defconfig | 1 + configs/j7200_evm_a72_defconfig | 1 + configs/j7200_evm_r5_defconfig | 1 + configs/j7200_hs_evm_a72_defconfig | 1 + configs/j7200_hs_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721e_hs_evm_a72_defconfig | 1 + configs/j721e_hs_evm_r5_defconfig | 1 + configs/j721s2_evm_a72_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j721s2_hs_evm_a72_defconfig | 1 + configs/j721s2_hs_evm_r5_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + configs/octeon_ebb7304_defconfig | 1 + configs/omap35_logic_somlv_defconfig | 1 + configs/omap3_logic_somlv_defconfig | 1 + configs/pm9261_defconfig | 1 + configs/pm9263_defconfig | 1 + configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + configs/qemu_arm64_defconfig | 1 + configs/qemu_arm_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d3xek_nandflash_defconfig | 1 + configs/sama5d3xek_spiflash_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/socrates_defconfig | 1 + configs/synquacer_developerbox_defconfig | 1 + configs/total_compute_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/vexpress_aemv8a_juno_defconfig | 1 + configs/vexpress_aemv8a_semi_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xtfpga_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + drivers/mtd/Kconfig | 9 +++++++++ drivers/mtd/cfi_flash.c | 4 ++-- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 2 -- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 2 -- include/configs/blanche.h | 1 - include/configs/draak.h | 1 - include/configs/eb_cpu5282.h | 1 - include/configs/ebisu.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 2 -- include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 2 -- include/configs/ls1043a_common.h | 4 ---- include/configs/ls1046aqds.h | 4 ---- include/configs/ls1088aqds.h | 2 -- include/configs/ls1088ardb.h | 2 -- include/configs/ls2080aqds.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/p1_p2_rdb_pc.h | 1 - include/configs/salvator-x.h | 1 - include/configs/ulcb.h | 1 - include/configs/zynq-common.h | 3 --- 132 files changed, 116 insertions(+), 51 deletions(-) diff --git a/README b/README index 3fef1d2afa..0583520742 100644 --- a/README +++ b/README @@ -1481,11 +1481,6 @@ Configuration Settings: s29ws-n MirrorBit flash has non-standard addresses for buffered write commands. -- CONFIG_FLASH_SHOW_PROGRESS - If defined (must be an integer), print out countdown - digits and dots. Recommended value: 45 (9..1) for 80 - column displays, 15 (3..1) for 40 column displays. - - CONFIG_FLASH_VERIFY If defined, the content of the flash (destination) is compared against the source after the write operation. An error message diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 3d62512ff9..8c421f099b 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -39,6 +39,7 @@ CONFIG_MISC=y CONFIG_ALTERA_SYSID=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 680c2d4367..20250c02a1 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=254 diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index c0087aa67f..38c5076d5f 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index b099e98606..cb5bcb7221 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index b192839766..de7f14165b 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -27,6 +27,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CHECKSUM=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index a321b1c5c2..f2d70a4e26 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_OR7_PRELIM=0xFFC0007C CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index e7e799b7bd..01961e5ae2 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=11 CONFIG_MCFFEC=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 5521cced6d..0ef2e7b4ff 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -32,6 +32,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_CHECKSUM=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 32d1958088..8158cd4e84 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 9f0b419639..6fede625fb 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -39,6 +39,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 05388796fb..fe70245497 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -40,6 +40,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 90d8321648..b074cf520f 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -40,6 +40,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index d8d6417d21..7d54807e64 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -83,6 +83,7 @@ CONFIG_SYS_OR7_PRELIM=0xFFFF810A CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=35 CONFIG_MTD_RAW_NAND=y diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 1a571cf6bc..40fc1d1da4 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -197,6 +197,7 @@ CONFIG_SYS_I2C_SPEED=400000 CONFIG_FSL_ESDHC=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 517fd785dd..c6f5d87bb9 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -68,6 +68,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 5c83e808d5..b6ebac3980 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index b354237db3..d272ede8d4 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index d876602fa0..e5c8358e54 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -34,6 +34,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 1c0b534537..a66db65621 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -40,6 +40,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index dc584a6fd4..606962c0a7 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -41,6 +41,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index ec6299495d..069a9d3982 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 65b3fc646f..c373b99b95 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -34,6 +34,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 4c3e1beb00..f235db7990 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -40,6 +40,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 3c6408a12a..4cbfd52fb1 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -41,6 +41,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index f4deee6871..4fed2ead1d 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_FTSDC010_SDIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_CFI_FLASH_STATUS_POLL=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index b8e8bc41b6..cebb79f733 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -34,6 +34,7 @@ CONFIG_ENV_IS_IN_FLASH=y # CONFIG_NET is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=1024 diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 9e5665a12b..a1a25622c7 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=80000 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index e7d32f0991..d5db004481 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -50,6 +50,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 794cf0e38d..d82cd21472 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -51,6 +51,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index d80152be0f..708a3a39d8 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -42,6 +42,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 8624853eba..41769be634 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 464b255920..12abbb8998 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index 67abbb9f7f..89d14b61fb 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -44,6 +44,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 253d232374..80031666f9 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index 190c993725..ad79c4e585 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -44,6 +44,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index f6e246e07f..581ddfa5b3 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -43,6 +43,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 82e01bb21f..9a5655fb02 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -44,6 +44,7 @@ CONFIG_CLK=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 594bddea6e..f3f09e593f 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index 69a958d879..a8ce3000d8 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 9332c8cb3f..137f9ec4f5 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -65,6 +65,7 @@ CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 66300698a9..cd5ddc4ad3 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -65,6 +65,7 @@ CONFIG_SYS_I2C_LPC32XX=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=71 diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index d2946971b4..a852b96d4e 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -192,6 +192,7 @@ CONFIG_IHS_FPGA=y CONFIG_FSL_ESDHC=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 9fbec97d51..fdff11e16f 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index e2709ec521..444953db91 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index e8baca158b..6eb912c1a1 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index 04032c8b94..023b84200e 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index 3d910d3d48..fab7274068 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -30,6 +30,7 @@ CONFIG_SYS_RX_ETH_BUFFER=8 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index ea1f858135..7417b53e86 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 19c72c759e..36b71fc401 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index e0ba5720f3..947d21ef35 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index e4e960e72a..630fe0d813 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTFILE="uImage" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index e7cdd84ecb..053f29b11f 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -138,6 +138,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 87101cbf53..dc6c1b6935 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -112,6 +112,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j7200_hs_evm_a72_defconfig b/configs/j7200_hs_evm_a72_defconfig index b9598ca1fe..782a42b746 100644 --- a/configs/j7200_hs_evm_a72_defconfig +++ b/configs/j7200_hs_evm_a72_defconfig @@ -139,6 +139,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j7200_hs_evm_r5_defconfig b/configs/j7200_hs_evm_r5_defconfig index 608778ade8..73979f4cc3 100644 --- a/configs/j7200_hs_evm_r5_defconfig +++ b/configs/j7200_hs_evm_r5_defconfig @@ -112,6 +112,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 48a2444694..5efaff26d2 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -140,6 +140,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index d6da4c6ae2..9d333e4905 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -120,6 +120,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index a1cc7da0bf..ec66b18740 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -141,6 +141,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index eb9df36553..e496ec85af 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -120,6 +120,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 2b2f80c4aa..99a0eee12d 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -139,6 +139,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 2de5d87bdb..cd25016998 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -118,6 +118,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_hs_evm_a72_defconfig b/configs/j721s2_hs_evm_a72_defconfig index 3e0ec40fb2..9fc90737da 100644 --- a/configs/j721s2_hs_evm_a72_defconfig +++ b/configs/j721s2_hs_evm_a72_defconfig @@ -140,6 +140,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/j721s2_hs_evm_r5_defconfig b/configs/j721s2_hs_evm_r5_defconfig index bc8672f709..d9988fc17f 100644 --- a/configs/j721s2_hs_evm_r5_defconfig +++ b/configs/j721s2_hs_evm_r5_defconfig @@ -118,6 +118,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 2abda78893..bd4943006c 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -74,6 +74,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 9609f58fb4..4ea7da8d32 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -227,6 +227,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index bd3d6315b1..96298ed0c3 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -193,6 +193,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index de6d99e91e..db717e4a15 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -208,6 +208,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index a231510a76..69de685baf 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -185,6 +185,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index e6beb62f86..92f2b0adec 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -207,6 +207,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig index b635c651aa..03de161684 100644 --- a/configs/malta64_defconfig +++ b/configs/malta64_defconfig @@ -37,6 +37,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig index 243213cb81..3ea9fa9857 100644 --- a/configs/malta64el_defconfig +++ b/configs/malta64el_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/malta_defconfig b/configs/malta_defconfig index ed41e298f4..317b422a6b 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -36,6 +36,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 63e5fcb6a5..3e4d2beda2 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -38,6 +38,7 @@ CONFIG_SYS_ATA_REG_OFFSET=0 CONFIG_SYS_ATA_IDE0_OFFSET=0x01f0 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=128 diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 2566bdef16..5f8a287373 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -63,6 +63,7 @@ CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 43ffc3c6bc..651eef5d06 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -61,6 +61,7 @@ CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index f1b9cb461b..186521aac6 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -64,6 +64,7 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index b966b1d24f..a642a64d5c 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -50,6 +50,7 @@ CONFIG_MMC_OCTEONTX=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 471e0556fa..fb9430b454 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -74,6 +74,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index e18cbaa5c1..37708516f1 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -75,6 +75,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index d43043427a..d30d07bcbf 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -45,6 +45,7 @@ CONFIG_AT91_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig index 2e42ba0803..11ec775b38 100644 --- a/configs/pm9263_defconfig +++ b/configs/pm9263_defconfig @@ -49,6 +49,7 @@ CONFIG_AT91_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 40ba25297f..425bb37c98 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -20,4 +20,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index eb9bf9b918..eeb90360cd 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -21,4 +21,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 756e7f35f6..04447e5ed3 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -25,5 +25,6 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 # CONFIG_BINMAN_FDT is not set diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index d5eae95c80..7430fa075d 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -20,4 +20,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 1cb06b4b2c..03ef58ba47 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -23,4 +23,5 @@ CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 68b16f0a2c..840e0ff151 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -24,5 +24,6 @@ CONFIG_SYS_BOOTM_LEN=0x4000000 # CONFIG_CMD_MII is not set CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_MAX_FLASH_BANKS=2 # CONFIG_BINMAN_FDT is not set diff --git a/configs/qemu_arm64_defconfig b/configs/qemu_arm64_defconfig index 4123338b8d..9335233152 100644 --- a/configs/qemu_arm64_defconfig +++ b/configs/qemu_arm64_defconfig @@ -45,6 +45,7 @@ CONFIG_DFU_RAM=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/qemu_arm_defconfig b/configs/qemu_arm_defconfig index f6c6c28764..6373185f29 100644 --- a/configs/qemu_arm_defconfig +++ b/configs/qemu_arm_defconfig @@ -47,6 +47,7 @@ CONFIG_DFU_RAM=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index 4217175345..0653089eca 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -44,6 +44,7 @@ CONFIG_IDE_RESET=y CONFIG_CLK=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_E1000=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index b3108fa64a..ba2e7dd76d 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -81,6 +81,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=131 diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index f06c21fdf1..3afb2aaffb 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -80,6 +80,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=131 diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 2045146fb8..8d71ba7d4f 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -82,6 +82,7 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=131 diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 5cf020a3eb..6140424670 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -53,6 +53,7 @@ CONFIG_LED_BCM6358=y CONFIG_LED_GPIO=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index f45f570764..4cc50d3558 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -77,6 +77,7 @@ CONFIG_SYS_I2C_FSL=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_FLASH_QUIET_TEST=y CONFIG_SYS_MAX_FLASH_SECT=256 diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index f69b873a36..a6fc65baee 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -60,6 +60,7 @@ CONFIG_MMC_SDHCI_F_SDH30=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index 807e9ebd86..04d27058f3 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -53,6 +53,7 @@ CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 83120759b1..0c3381461e 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -185,6 +185,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index ee1640608d..4f192ad262 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -209,6 +209,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index 73b7363b68..47841e8b6c 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 0b566b8005..4b22d49b29 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_UBI=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_SYS_FLASH_CFI_WIDTH_32BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 70ce13eccc..83e15ddbe1 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_MMC_MAX_BLK_COUNT=127 CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_EMPTY_INFO=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index a4c555dac5..5068565769 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -109,6 +109,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=10 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index c58514669d..f5eeea426b 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -39,6 +39,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y +CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index f1c648a8f9..c194e89b7e 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -75,6 +75,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_SHOW_PROGRESS=10 CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index d8e2dec0a8..04ae45665e 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -77,6 +77,15 @@ config SYS_FLASH_CFI_WIDTH help This must be kept in sync with the table in include/flash.h +config FLASH_SHOW_PROGRESS + int "Print out a countdown durinng writes" + depends on FLASH_CFI_DRIVER + default 45 + help + If set to a non-zero value, print out countdown digits and dots. + Recommended value: 45 (9..1) for 80 column displays, 15 (3..1) for 40 + column displays. + config CFI_FLASH bool "Enable Driver Model for CFI Flash driver" depends on DM_MTD diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index c1cdd2cbc3..f378f6fb61 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1292,7 +1292,7 @@ void flash_print_info(flash_info_t *info) * effect updates to digit and dots. Repeated code is nasty too, so * we define it once here. */ -#ifdef CONFIG_FLASH_SHOW_PROGRESS +#if CONFIG_FLASH_SHOW_PROGRESS #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ if (flash_verbose) { \ dots -= dots_sub; \ @@ -1325,7 +1325,7 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE int buffered_size; #endif -#ifdef CONFIG_FLASH_SHOW_PROGRESS +#if CONFIG_FLASH_SHOW_PROGRESS int digit = CONFIG_FLASH_SHOW_PROGRESS; int scale = 0; int dots = 0; diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 4418d51695..f79c62adba 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -161,7 +161,6 @@ extern unsigned long get_sdram_size(void); #define CFG_SYS_NOR_FTIM3 0x0 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* CFI for NOR Flash */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8b901ca47a..707157e4a9 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -101,8 +101,6 @@ #define PIXIS_LBMAP_SHIFT 4 #define PIXIS_LBMAP_ALTBANK 0x40 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CFG_SYS_NAND_BASE 0xffa00000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 623d4cf556..b590f12739 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -158,8 +158,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} #ifdef CONFIG_TARGET_T1024RDB diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index b6938056bb..9d805f446b 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -126,8 +126,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} /* CPLD on IFC */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a93e05dd4d..804b7ec4c1 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -119,8 +119,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index cf65a0da18..d8213b4662 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -114,8 +114,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS } /* CPLD on IFC */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b51762264a..958933689d 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -184,8 +184,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0x0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \ + 0x8000000, CFG_SYS_FLASH_BASE_PHYS} diff --git a/include/configs/blanche.h b/include/configs/blanche.h index cb28ae28dd..fe09997e17 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -25,7 +25,6 @@ #if !defined(CONFIG_MTD_NOR_FLASH) #define CONFIG_SH_QSPI_BASE 0xE6B10000 #else -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BASE 0x00000000 #define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ #define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } diff --git a/include/configs/draak.h b/include/configs/draak.h index 8140bc469c..946f1d9646 100644 --- a/include/configs/draak.h +++ b/include/configs/draak.h @@ -13,7 +13,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 21eab9b3a4..717f49ca29 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -84,7 +84,6 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE #define CFG_SYS_INT_FLASH_BASE 0xF0000000 diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index d1882a9646..ad5944230a 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -15,7 +15,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 7fe2ece840..8d5b24d827 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -58,8 +58,6 @@ FTIM2_NOR_TWP(0xb)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d6681e8598..e49588489c 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -60,7 +60,6 @@ FTIM2_NOR_TWP(0x1c)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_WRITE_SWAPPED_DATA #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS, \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3c4c207edd..b07978a999 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -92,8 +92,6 @@ FTIM2_NOR_TWPH(0x0e)) #define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE_PHYS } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index a3fa92d1ff..e54e903a8a 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -90,10 +90,6 @@ #define CFG_SYS_FLASH_BASE 0x60000000 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#endif #endif #endif diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 553ae841ca..e9b8ad0c0b 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -41,10 +41,6 @@ #define CFG_SYS_FLASH_BASE 0x60000000 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#endif #endif /* LPUART */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index a35045d640..dc9cded49f 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -62,8 +62,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ CFG_SYS_FLASH_BASE + 0x40000000} #endif diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 7bc4fc6a66..e2444cd8eb 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -47,8 +47,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE } #endif #endif diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 924d4057d9..4e6d40afbf 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -64,8 +64,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ CFG_SYS_FLASH_BASE + 0x40000000} #endif diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index c50b603068..8f36958f71 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -61,8 +61,6 @@ #define CFG_SYS_IFC_CCR 0x01000000 #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\ CFG_SYS_FLASH_BASE + 0x40000000} #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f86b96b214..eb2c5a2d83 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -199,7 +199,6 @@ #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 2e422cd241..8dc6702de4 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -13,7 +13,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index ab199bc726..6e03375c6c 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -13,7 +13,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CFG_SYS_FLASH_BANKS_LIST { 0x08000000 } #define CFG_SYS_WRITE_SWAPPED_DATA diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index b8c142fed3..37b5428907 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -35,9 +35,6 @@ /* Ethernet driver */ /* NOR */ -#ifdef CONFIG_MTD_NOR_FLASH -# define CONFIG_FLASH_SHOW_PROGRESS 10 -#endif #ifdef CONFIG_USB_EHCI_ZYNQ # define DFU_DEFAULT_POLL_TIMEOUT 300 From 3a581af21af0bceb7e47650a19e3ddd3de87148a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:21 -0500 Subject: [PATCH 188/424] Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig This converts the following to Kconfig: CONFIG_FLASH_SPANSION_S29WS_N CONFIG_FLASH_VERIFY CONFIG_FSL_FM_10GEC_REGULAR_NOTATION CONFIG_FSL_ISBC_KEY_EXT CONFIG_FSL_TRUST_ARCH_v1 CONFIG_FSL_SDHC_V2_3 CONFIG_MAX_DSP_CPUS CONFIG_MIU_2BIT_INTERLEAVED CONFIG_SERIAL_BOOT CONFIG_SPI_BOOTING CONFIG_X86EMU_RAW_IO Signed-off-by: Tom Rini --- README | 13 ------------- arch/Kconfig.nxp | 17 +++++++++++++++++ arch/arm/include/asm/fsl_secure_boot.h | 15 --------------- arch/arm/mach-exynos/Kconfig | 4 ++++ arch/powerpc/cpu/mpc85xx/Kconfig | 5 +++++ arch/powerpc/include/asm/config_mpc85xx.h | 7 ------- arch/powerpc/include/asm/fsl_secure_boot.h | 18 ------------------ board/freescale/common/fsl_validate.c | 18 +++++++++--------- board/google/Kconfig | 4 ++++ board/samsung/smdkv310/Kconfig | 3 +++ board/sysam/stmark2/Kconfig | 4 ++++ configs/M53017EVB_defconfig | 1 + configs/mccmon6_nor_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + doc/README.fsl-dpaa | 10 ---------- drivers/mmc/Kconfig | 5 +++++ drivers/mtd/Kconfig | 19 +++++++++++++++++++ drivers/net/Kconfig | 13 +++++++++++++ include/configs/M53017EVB.h | 1 - include/configs/conga-qeval20-qa3-e3845.h | 1 - include/configs/dfi-bt700.h | 1 - include/configs/exynos5-dt-common.h | 1 - include/configs/mccmon6.h | 1 - include/configs/minnowmax.h | 1 - include/configs/smdkv310.h | 3 --- include/configs/som-db5800-som-6867.h | 1 - include/configs/stmark2.h | 4 ---- include/configs/theadorable-x86-common.h | 1 - include/configs/x86-chromebook.h | 1 - 29 files changed, 86 insertions(+), 88 deletions(-) delete mode 100644 doc/README.fsl-dpaa diff --git a/README b/README index 0583520742..b833aca2e5 100644 --- a/README +++ b/README @@ -1477,19 +1477,6 @@ Configuration Settings: - CONFIG_SYS_FLASH_USE_BUFFER_WRITE Use buffered writes to flash. -- CONFIG_FLASH_SPANSION_S29WS_N - s29ws-n MirrorBit flash has non-standard addresses for buffered - write commands. - -- CONFIG_FLASH_VERIFY - If defined, the content of the flash (destination) is compared - against the source after the write operation. An error message - will be printed when the contents are not identical. - Please note that this option is useless in nearly all cases, - since such flash programming errors usually are detected earlier - while unprotecting/erasing/programming. Please only enable - this option if you really know what you are doing. - - CONFIG_ENV_FLAGS_LIST_DEFAULT - CONFIG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 805fe934a1..ad61dabb31 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -1,5 +1,10 @@ +config FSL_TRUST_ARCH_v1 + bool + config NXP_ESBC bool "NXP ESBC (secure boot) functionality" + select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \ + ARCH_P5040 || ARCH_P2041 help Enable Freescale Secure Boot feature. Normally selected by defconfig. If unsure, do not change. @@ -10,6 +15,7 @@ menu "Chain of trust / secure boot options" config CHAIN_OF_TRUST select FSL_CAAM select ARCH_MISC_INIT + select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT select FSL_SEC_MON select SPL_BOARD_INIT if (ARM && SPL) select SPL_HASH if (ARM && SPL) @@ -41,6 +47,17 @@ config ESBC_ADDR_64BIT help For Layerscape based platforms, ESBC image Address in Header is 64bit. +config FSL_ISBC_KEY_EXT + bool + help + The key used for verification of next level images is picked up from + an Extension Table which has been verified by the ISBC (Internal + Secure boot Code) in boot ROM of the SoC. The feature is only + applicable in case of NOR boot and is not applicable in case of + RAMBOOT (NAND, SD, SPI). For Layerscape, this feature is available + for all device if IE Table is copied to XIP memory Also, for + Layerscape, ISBC doesn't verify this table. + config SYS_FSL_SFP_BE def_bool y depends on PPC || FSL_LSCH2 || ARCH_LS1021A diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index a4f4961fc8..6a9d198cb8 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -9,21 +9,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST #ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_SYS_RAMBOOT -/* The key used for verification of next level images - * is picked up from an Extension Table which has - * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC. - * The feature is only applicable in case of NOR boot and is - * not applicable in case of RAMBOOT (NAND, SD, SPI). - * For LS, this feature is available for all device if IE Table - * is copied to XIP memory - * Also, for LS, ISBC doesn't verify this table. - */ -#define CONFIG_FSL_ISBC_KEY_EXT - -#endif - #ifdef CONFIG_FSL_LS_PPA /* Define the key hash here if SRK used for signing PPA image is * different from SRK hash put in SFP used for U-Boot. diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 383af83066..8f3aee052c 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -4,6 +4,9 @@ config BOARD_COMMON def_bool y depends on !TARGET_SMDKV310 && !TARGET_ARNDALE +config SPI_BOOTING + bool + config USB_BOOTING bool @@ -27,6 +30,7 @@ config ARCH_EXYNOS5 select BOARD_EARLY_INIT_F select CPU_V7A select SHA_HW_ACCEL + select SPI_BOOTING if EXYNOS5_DT select USB_BOOTING imply CMD_HASH imply CRC32_VERIFY diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index f2361560e9..721dafc5ab 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1324,6 +1324,11 @@ config SYS_ULB_CLK config SYS_ETVPE_CLK int default 1 + +config MAX_DSP_CPUS + int + default 12 if ARCH_B4860 + default 2 if ARCH_B4420 endif config SYS_L2_SIZE_256KB diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1b5b4947f1..edaf8baaae 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -23,7 +23,6 @@ #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 #elif defined(CONFIG_ARCH_P1010) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #elif defined(CONFIG_ARCH_P1021) @@ -93,11 +92,9 @@ #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_T4240) @@ -136,7 +133,6 @@ #define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 -#define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CFG_SYS_NUM_FM1_DTSEC 6 @@ -145,7 +141,6 @@ #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else -#define CONFIG_MAX_DSP_CPUS 2 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CFG_SYS_NUM_FM1_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 0 @@ -173,7 +168,6 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 @@ -204,7 +198,6 @@ #elif defined(CONFIG_ARCH_C29X) -#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index e8b2680206..09f37ec3e4 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -35,24 +35,6 @@ #define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif - -#if defined(CONFIG_ARCH_P3041) || \ - defined(CONFIG_ARCH_P4080) || \ - defined(CONFIG_ARCH_P5040) || \ - defined(CONFIG_ARCH_P2041) - #define CONFIG_FSL_TRUST_ARCH_v1 -#endif - -#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT) -/* The key used for verification of next level images - * is picked up from an Extension Table which has - * been verified by the ISBC (Internal Secure boot Code) - * in boot ROM of the SoC. - * The feature is only applicable in case of NOR boot and is - * not applicable in case of RAMBOOT (NAND, SD, SPI). - */ -#define CONFIG_FSL_ISBC_KEY_EXT -#endif #endif /* #ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_CHAIN_OF_TRUST diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 285ed9afcc..bfe6357b0d 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -29,7 +29,7 @@ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES)) -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) /* Global data structure */ static struct fsl_secboot_glb glb; #endif @@ -63,7 +63,7 @@ self: goto self; } -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) static u32 check_ie(struct fsl_secboot_img_priv *img) { if (img->hdr.ie_flag & IE_FLAG_MASK) @@ -188,7 +188,7 @@ static u32 check_srk(struct fsl_secboot_img_priv *img) { #ifdef CONFIG_ESBC_HDR_LS /* In LS, No SRK Flag as SRK is always present if IE not present*/ -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) return !check_ie(img); #endif return 1; @@ -278,7 +278,7 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) } #endif /* CONFIG_ESBC_HDR_LS */ -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) static void install_ie_tbl(uintptr_t ie_tbl_addr, struct fsl_secboot_img_priv *img) @@ -434,7 +434,7 @@ void fsl_secboot_handle_error(int error) case ERROR_ESBC_CLIENT_HEADER_INVALID_KEY_NUM: case ERROR_ESBC_CLIENT_HEADER_INV_SRK_ENTRY_KEYLEN: #endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) /*@fallthrough@*/ case ERROR_ESBC_CLIENT_HEADER_IE_KEY_REVOKED: case ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY: @@ -571,7 +571,7 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) key_hash = 1; } #endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (!key_hash && check_ie(img)) key_hash = 1; #endif @@ -705,7 +705,7 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) } #endif -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (!key_found && check_ie(img)) { ret = read_validate_ie_tbl(img); if (ret != 0) @@ -851,7 +851,7 @@ static int secboot_init(struct fsl_secboot_img_priv **img_ptr) return -ENOMEM; memset(img, 0, sizeof(struct fsl_secboot_img_priv)); -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (glb.ie_addr) img->ie_addr = glb.ie_addr; #endif @@ -952,7 +952,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, else ret = memcmp(srk_hash, img->img_key_hash, SHA256_BYTES); -#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#if CONFIG_IS_ENABLED(FSL_ISBC_KEY_EXT) if (!hash_cmd && check_ie(img)) ret = 0; #endif diff --git a/board/google/Kconfig b/board/google/Kconfig index c57e518c33..0474b4e693 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -6,6 +6,10 @@ if VENDOR_GOOGLE config BIOSEMU bool + select X86EMU_RAW_IO + +config X86EMU_RAW_IO + bool choice prompt "Mainboard model" diff --git a/board/samsung/smdkv310/Kconfig b/board/samsung/smdkv310/Kconfig index a6fd657697..cf5ac17074 100644 --- a/board/samsung/smdkv310/Kconfig +++ b/board/samsung/smdkv310/Kconfig @@ -1,5 +1,8 @@ if TARGET_SMDKV310 +config MIU_2BIT_INTERLEAVED + def_bool y + config SYS_BOARD default "smdkv310" diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig index 49d02744a9..b2595059c6 100644 --- a/board/sysam/stmark2/Kconfig +++ b/board/sysam/stmark2/Kconfig @@ -6,6 +6,10 @@ config CF_SBF config EXTRA_CLOCK def_bool y +config SERIAL_BOOT + def_bool y + depends on CF_SBF + config SYS_INPUT_CLKSRC hex default 30000000 diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 8158cd4e84..b6783ab95b 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -41,6 +41,7 @@ CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y CONFIG_FLASH_SHOW_PROGRESS=0 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_SPANSION_S29WS_N=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=137 diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 5f8a287373..1e6cec0121 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -69,6 +69,7 @@ CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_FLASH_VERIFY=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 651eef5d06..20b6e03bdf 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_FLASH_EMPTY_INFO=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_FLASH_VERIFY=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=25000000 CONFIG_SPI_FLASH_SPANSION=y diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa deleted file mode 100644 index 3ef5eeb32e..0000000000 --- a/doc/README.fsl-dpaa +++ /dev/null @@ -1,10 +0,0 @@ -This file documents Freescale DPAA-specific options. - -FMan (Frame Manager) - - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION - on SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 - on SoCs T1024, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC1, 10GEC2->MAC2 - so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on - which 10GEC enumeration is consistent with MAC enumeration. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 698c91c57f..5a5a31c75a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -825,8 +825,13 @@ config MMC_MTK endif +config FSL_SDHC_V2_3 + bool + config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" + select FSL_SDHC_V2_3 if ARCH_P1010 || ARCH_BSC9131 || ARCH_BSC9132 \ + || ARCH_C29X help This selects support for the eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 04ae45665e..af45ef00da 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -119,6 +119,13 @@ config SYS_FLASH_EMPTY_INFO bool "Enable displaying empty sectors in flash info" depends on FLASH_CFI_DRIVER +config FLASH_SPANSION_S29WS_N + bool "Non-standard s29ws-n MirrorBit flash" + depends on FLASH_CFI_DRIVER + help + Enable this if the s29ws-n MirrorBit flash has non-standard addresses + for buffered write commands. + config FLASH_CFI_MTD bool "Enable CFI MTD driver" depends on FLASH_CFI_DRIVER @@ -156,6 +163,18 @@ config SYS_FLASH_CHECKSUM If the variable flashchecksum is set in the environment, perform a CRC of the flash and print the value to console. +config FLASH_VERIFY + bool "Compare writes to NOR flash with source location" + depends on MTD_NOR_FLASH + help + If enabled, the content of the flash (destination) is compared + against the source after the write operation. An error message will + be printed when the contents are not identical. Please note that + this option is useless in nearly all cases, since such flash + programming errors usually are detected earlier while + unprotecting/erasing/programming. Please only enable this option if + you really know what you are doing. + config ALTERA_QSPI bool "Altera Generic Quad SPI Controller" depends on DM_MTD diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0607f959da..53fb69f526 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -372,6 +372,7 @@ config FMAN_ENET select SYS_FMAN_V3 if ARCH_B4420 || ARCH_B4860 || ARCH_LS1043A || \ ARCH_LS1046A || ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || \ ARCH_T2080 || ARCH_T4240 + select FSL_FM_10GEC_REGULAR_NOTATION if ARCH_T1024 help This driver support the Freescale FMan Ethernet controller @@ -391,6 +392,18 @@ config SYS_FMAN_V3 help SoC has FMan v3 with mEMAC +config FSL_FM_10GEC_REGULAR_NOTATION + bool + help + On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and + MAC as below: + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + While on SoCs T1024, etc, the notation between 10GEC and MAC as below: + 10GEC1->MAC1, 10GEC2->MAC2 + so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the + new SoCs on which 10GEC enumeration is consistent with MAC + enumeration. + config FTMAC100 bool "Ftmac100 Ethernet Support" help diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 42b74aeb9b..439ed93a23 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -93,7 +93,6 @@ * FLASH organization */ #ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_FLASH_SPANSION_S29WS_N 1 # define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ #endif diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 823d37fc38..e9b85b4e1c 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -17,7 +17,6 @@ "stderr=serial\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 52f2d50118..154c4f4f13 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -21,7 +21,6 @@ "stderr=serial\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index c9e0c13172..8f2dac61cb 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -17,6 +17,5 @@ #define CFG_SYS_SPI_BASE 0x12D30000 #define FLASH_SIZE (4 << 20) -#define CONFIG_SPI_BOOTING #endif diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 7c401a2cfd..a7f5507692 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -25,7 +25,6 @@ /* NOR 16-bit mode */ #define CFG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_FLASH_VERIFY /* NOR Flash MTD */ #define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 50c52f8839..6c15c72efd 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -18,6 +18,5 @@ "usb_pgood_delay=40\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index af0c8200fc..601c16ea45 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -34,9 +34,6 @@ /* FLASH and environment organization */ -/* MIU (Memory Interleaving Unit) */ -#define CONFIG_MIU_2BIT_INTERLEAVED - #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index ee038d83bc..f097092136 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -17,6 +17,5 @@ "stderr=serial,vidconsole\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #endif /* __CONFIG_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index faff8d6ed6..f81cef0a2c 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -63,10 +63,6 @@ #define CFG_SYS_DRAM_TEST -#if defined(CONFIG_CF_SBF) -#define CONFIG_SERIAL_BOOT -#endif - /* Reserve 256 kB for Monitor */ /* diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index af0a095dfc..b57b1beaaf 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -16,7 +16,6 @@ "stderr=serial\0" #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO /* Environment settings */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index ec87eddd4c..9df3bfd527 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -11,7 +11,6 @@ #define CONFIG_X86_REFCODE_RUN_ADDR 0 #define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ From 5388aa28511c75be387f6bfe868e03fa7505792a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:22 -0500 Subject: [PATCH 189/424] Convert CONFIG_FSL_ESDHC_PIN_MUX to Kconfig This converts the following to Kconfig: CONFIG_FSL_ESDHC_PIN_MUX Signed-off-by: Tom Rini --- configs/MPC837XERDB_defconfig | 1 + drivers/mmc/Kconfig | 4 ++++ drivers/mmc/fsl_esdhc_imx.c | 2 +- include/configs/MPC837XERDB.h | 1 - 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 40fc1d1da4..a227ca86de 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -195,6 +195,7 @@ CONFIG_SYS_FSL_I2C_OFFSET=0x3000 CONFIG_SYS_I2C_SLAVE=0x7F CONFIG_SYS_I2C_SPEED=400000 CONFIG_FSL_ESDHC=y +CONFIG_FSL_ESDHC_PIN_MUX=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_FLASH_SHOW_PROGRESS=0 diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 5a5a31c75a..878f867c62 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -891,6 +891,10 @@ config FSL_USDHC help This enables the Ultra Secured Digital Host Controller enhancements +config FSL_ESDHC_PIN_MUX + bool "Perform esdhc device-tree fixup" + depends on (FSL_ESDHC || FSL_ESDHC_IMX) && OF_LIBFDT + endmenu config SYS_FSL_ERRATUM_ESDHC111 diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 5ee3ce7823..66caf683f7 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1360,7 +1360,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) #if CONFIG_IS_ENABLED(OF_LIBFDT) __weak int esdhc_status_fixup(void *blob, const char *compat) { - if (IS_ENABLED(FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { + if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) { do_fixup_by_compat(blob, compat, "status", "disabled", sizeof("disabled"), 1); return 1; diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f312ffb37e..dbfcdfb738 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -177,7 +177,6 @@ #define CFG_SYS_PCIE2_IO_PHYS 0xD8000000 #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR #endif From ade03b55c4f2306785314080736d1af8d035609f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:23 -0500 Subject: [PATCH 190/424] env: nvram: Drop CONFIG_SYS_NVRAM_ACCESS_ROUTINE This option is unused anywhere and likely untested for quite a long while. Drop this support code. Signed-off-by: Tom Rini --- env/nvram.c | 42 ++---------------------------------------- 1 file changed, 2 insertions(+), 40 deletions(-) diff --git a/env/nvram.c b/env/nvram.c index fb265235af..229c34f536 100644 --- a/env/nvram.c +++ b/env/nvram.c @@ -7,22 +7,6 @@ * Andreas Heppel */ -/* - * 09-18-2001 Andreas Heppel, Sysgo RTS GmbH - * - * It might not be possible in all cases to use 'memcpy()' to copy - * the environment to NVRAM, as the NVRAM might not be mapped into - * the memory space. (I.e. this is the case for the BAB750). In those - * cases it might be possible to access the NVRAM using a different - * method. For example, the RTC on the BAB750 is accessible in IO - * space using its address and data registers. To enable usage of - * NVRAM in those cases I invented the functions 'nvram_read()' and - * 'nvram_write()', which will be activated upon the configuration - * #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE. Note, that those functions are - * strongly dependent on the used HW, and must be redefined for each - * board that wants to use them. - */ - #include #include #include @@ -35,22 +19,14 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE -extern void *nvram_read(void *dest, const long src, size_t count); -extern void nvram_write(long dest, const void *src, size_t count); -#else static env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; -#endif static int env_nvram_load(void) { char buf[CONFIG_ENV_SIZE]; -#if defined(CONFIG_SYS_NVRAM_ACCESS_ROUTINE) - nvram_read(buf, CONFIG_ENV_ADDR, CONFIG_ENV_SIZE); -#else memcpy(buf, (void *)CONFIG_ENV_ADDR, CONFIG_ENV_SIZE); -#endif + return env_import(buf, 1, H_EXTERNAL); } @@ -63,12 +39,9 @@ static int env_nvram_save(void) if (rcode) return rcode; -#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE - nvram_write(CONFIG_ENV_ADDR, &env_new, CONFIG_ENV_SIZE); -#else if (memcpy((char *)CONFIG_ENV_ADDR, &env_new, CONFIG_ENV_SIZE) == NULL) rcode = 1; -#endif + return rcode; } @@ -79,19 +52,8 @@ static int env_nvram_save(void) */ static int env_nvram_init(void) { -#if defined(CONFIG_SYS_NVRAM_ACCESS_ROUTINE) - ulong crc; - uchar data[ENV_SIZE]; - - nvram_read(&crc, CONFIG_ENV_ADDR, sizeof(ulong)); - nvram_read(data, CONFIG_ENV_ADDR + sizeof(ulong), ENV_SIZE); - - if (crc32(0, data, ENV_SIZE) == crc) { - gd->env_addr = (ulong)CONFIG_ENV_ADDR + sizeof(long); -#else if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { gd->env_addr = (ulong)&env_ptr->data; -#endif gd->env_valid = ENV_VALID; } else { gd->env_valid = ENV_INVALID; From f3b516852e0ba16f491266218430264789c71f3a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:24 -0500 Subject: [PATCH 191/424] CONFIG_SYS_MPC8xxx_GUTS_ADDR: Migrate to CFG_SYS Due to whitespace, CONFIG_SYS_MPC8xxx_GUTS_ADDR wasn't migrated to CFG_SYS previously. Do this now. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc8xxx/srio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index dc1bc0db42..c0b4a1217d 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -33,17 +33,17 @@ #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 #endif #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR + #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC85xx) #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR + #define CFG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC86xx) #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \ + #define CFG_SYS_MPC8xxx_GUTS_ADDR \ (&((immap_t *)CONFIG_SYS_IMMR)->im_gur) #else #error "No defines for DEVDISR_SRIO" @@ -230,7 +230,7 @@ host_ok: void srio_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC8xxx_GUTS_ADDR; int srio1_used = 0, srio2_used = 0; u32 *devdisr; From b95de034c51bfeabde26e8ca6a11f25e91f2405b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:25 -0500 Subject: [PATCH 192/424] meson64: Fix missing CFG_SYS_BAUDRATE_TABLE migration CONFIG_SYS_BAUDRATE_TABLE has already been migrated to CFG_SYS but this instance was missed, correct. Signed-off-by: Tom Rini --- include/configs/meson64.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 6331b7615d..a22f7a81b0 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -18,7 +18,7 @@ /* Serial drivers */ /* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ +#define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, \ 230400, 250000, 460800, 500000, 1000000, 2000000, 4000000, \ 8000000 } From 3f7a4965319920d0d029318399bbc0fe51ab0c08 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:26 -0500 Subject: [PATCH 193/424] Convert CONFIG_POWER_PCA9450 to Kconfig This converts the following to Kconfig: CONFIG_POWER_PCA9450 Signed-off-by: Tom Rini --- configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + configs/verdin-imx8mp_defconfig | 1 + drivers/power/pmic/Kconfig | 3 +++ include/configs/imx8mp_evk.h | 8 -------- include/configs/imx8mp_icore_mx8mp.h | 7 ------- include/configs/phycore_imx8mp.h | 6 ------ include/configs/verdin-imx8mp.h | 3 --- 9 files changed, 7 insertions(+), 24 deletions(-) diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index f679fbe251..e3588473d5 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -99,6 +99,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 91ec39d023..10802eb961 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -99,6 +99,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 248631b7a8..82e4f1ed97 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -107,6 +107,7 @@ CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_SPL_POWER_LEGACY=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index bae8179bfd..153c7c1519 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -143,6 +143,7 @@ CONFIG_SPL_POWER_LEGACY=y CONFIG_POWER_DOMAIN=y CONFIG_IMX8M_POWER_DOMAIN=y CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y +CONFIG_POWER_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index d94048db5f..176fb07c65 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -416,6 +416,9 @@ config POWER_HI6553 config POWER_LTC3676 bool "Enable legacy driver for LTC3676 PMIC" +config POWER_PCA9450 + bool "Enable legacy driver for PCA9450 PMIC" + config POWER_PFUZE100 bool "Enable legacy driver for PFUZE100 PMIC" diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 738677ff37..137bd3b095 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -12,14 +12,6 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ - - -#define CONFIG_POWER_PCA9450 - -#endif - #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index d67bad8971..b261a81e44 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -13,13 +13,6 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ - -#define CONFIG_POWER_PCA9450 - -#endif - #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 1 diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 11a833bb12..7a38382034 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,12 +13,6 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#ifdef CONFIG_SPL_BUILD - -#define CONFIG_POWER_PCA9450 - -#endif - #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 88839a6e56..22dc364223 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -19,9 +19,6 @@ #define CONFIG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PCA9450 - -#define CONFIG_SYS_I2C #endif /* CONFIG_SPL_BUILD */ #define MEM_LAYOUT_ENV_SETTINGS \ From 54f80dd2908af0b851816cf062edf2d454948397 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:27 -0500 Subject: [PATCH 194/424] Convert CONFIG_HOSTNAME et al to Kconfig This converts the following to Kconfig: CONFIG_GATEWAYIP CONFIG_HOSTNAME CONFIG_IPADDR CONFIG_NETMASK CONFIG_ROOTPATH CONFIG_SERVERIP CONFIG_UBOOTPATH To do this, we introduce a CONFIG_USE_ form of each of the above and change include/env_default.h to test for that to be set before setting a value. Further, we don't want to stringify the IP address related values as they are now properly strings via Kconfig. Signed-off-by: Tom Rini --- README | 32 ------------ arch/powerpc/Kconfig | 12 +++++ configs/M5208EVBE_defconfig | 10 ++++ configs/M5235EVB_Flash32_defconfig | 10 ++++ configs/M5235EVB_defconfig | 10 ++++ configs/M5253DEMO_defconfig | 2 + configs/M5272C3_defconfig | 10 ++++ configs/M5282EVB_defconfig | 10 ++++ configs/M53017EVB_defconfig | 10 ++++ configs/M5329AFEE_defconfig | 10 ++++ configs/M5329BFEE_defconfig | 10 ++++ configs/M5373EVB_defconfig | 10 ++++ configs/MCR3000_defconfig | 6 +++ configs/MPC837XERDB_defconfig | 5 ++ configs/MPC8548CDS_36BIT_defconfig | 13 +++++ configs/MPC8548CDS_defconfig | 13 +++++ configs/MPC8548CDS_legacy_defconfig | 13 +++++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig | 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig | 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 ++ configs/P1020RDB-PC_36BIT_defconfig | 3 ++ configs/P1020RDB-PC_NAND_defconfig | 3 ++ configs/P1020RDB-PC_SDCARD_defconfig | 3 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 3 ++ configs/P1020RDB-PC_defconfig | 3 ++ configs/P1020RDB-PD_NAND_defconfig | 3 ++ configs/P1020RDB-PD_SDCARD_defconfig | 3 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 3 ++ configs/P1020RDB-PD_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 ++ configs/P2020RDB-PC_36BIT_defconfig | 3 ++ configs/P2020RDB-PC_NAND_defconfig | 3 ++ configs/P2020RDB-PC_SDCARD_defconfig | 3 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 3 ++ configs/P2020RDB-PC_defconfig | 3 ++ configs/P2041RDB_NAND_defconfig | 2 + configs/P2041RDB_SDCARD_defconfig | 2 + configs/P2041RDB_SPIFLASH_defconfig | 2 + configs/P2041RDB_defconfig | 2 + configs/T1024RDB_NAND_defconfig | 2 + configs/T1024RDB_SDCARD_defconfig | 2 + configs/T1024RDB_SPIFLASH_defconfig | 2 + configs/T1024RDB_defconfig | 2 + configs/T1042D4RDB_NAND_defconfig | 2 + configs/T1042D4RDB_SDCARD_defconfig | 2 + configs/T1042D4RDB_SPIFLASH_defconfig | 2 + configs/T1042D4RDB_defconfig | 2 + configs/T2080QDS_NAND_defconfig | 2 + configs/T2080QDS_SDCARD_defconfig | 2 + configs/T2080QDS_SECURE_BOOT_defconfig | 2 + configs/T2080QDS_SPIFLASH_defconfig | 2 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 + configs/T2080QDS_defconfig | 2 + configs/T2080RDB_NAND_defconfig | 2 + configs/T2080RDB_SDCARD_defconfig | 2 + configs/T2080RDB_SPIFLASH_defconfig | 2 + configs/T2080RDB_defconfig | 2 + configs/T2080RDB_revD_NAND_defconfig | 2 + configs/T2080RDB_revD_SDCARD_defconfig | 2 + configs/T2080RDB_revD_SPIFLASH_defconfig | 2 + configs/T2080RDB_revD_defconfig | 2 + configs/T4240RDB_SDCARD_defconfig | 2 + configs/T4240RDB_defconfig | 2 + configs/amcore_defconfig | 2 + configs/apalis-imx8_defconfig | 6 +++ configs/apalis-tk1_defconfig | 6 +++ configs/apalis_imx6_defconfig | 6 +++ configs/aristainetos2c_defconfig | 2 + configs/aristainetos2ccslb_defconfig | 2 + configs/bayleybay_defconfig | 1 + configs/bcm_ns3_defconfig | 2 + configs/cherryhill_defconfig | 1 + configs/chromebook_coral_defconfig | 1 + configs/chromebook_link64_defconfig | 1 + configs/chromebook_link_defconfig | 1 + configs/chromebook_samus_defconfig | 1 + configs/chromebox_panther_defconfig | 1 + configs/cobra5272_defconfig | 4 ++ configs/colibri-imx6ull-emmc_defconfig | 6 +++ configs/colibri-imx6ull_defconfig | 6 +++ configs/colibri-imx8x_defconfig | 6 +++ configs/colibri_imx6_defconfig | 6 +++ configs/colibri_imx7_defconfig | 6 +++ configs/colibri_imx7_emmc_defconfig | 6 +++ configs/colibri_vf_defconfig | 6 +++ ...-qeval20-qa3-e3845-internal-uart_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/controlcenterdc_defconfig | 3 ++ configs/coreboot64_defconfig | 1 + configs/coreboot_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/crownbay_defconfig | 1 + configs/dfi-bt700-q7x-151_defconfig | 1 + configs/draco_defconfig | 2 + configs/efi-x86_app32_defconfig | 1 + configs/efi-x86_app64_defconfig | 1 + configs/efi-x86_payload32_defconfig | 1 + configs/efi-x86_payload64_defconfig | 1 + configs/etamin_defconfig | 2 + configs/galileo_defconfig | 1 + configs/gazerbeam_defconfig | 3 ++ configs/gwventana_emmc_defconfig | 4 ++ configs/gwventana_gw5904_defconfig | 4 ++ configs/gwventana_nand_defconfig | 4 ++ configs/imx28_xea_defconfig | 2 + configs/imx28_xea_sb_defconfig | 2 + configs/integratorcp_cm1136_defconfig | 4 ++ configs/integratorcp_cm920t_defconfig | 4 ++ configs/integratorcp_cm926ejs_defconfig | 4 ++ configs/integratorcp_cm946es_defconfig | 4 ++ configs/kontron-sl-mx6ul_defconfig | 2 + configs/kontron-sl-mx8mm_defconfig | 2 + configs/m53menlo_defconfig | 2 + configs/microblaze-generic_defconfig | 2 + configs/minnowmax_defconfig | 1 + configs/mt7622_rfb_defconfig | 4 ++ configs/mt7623a_unielec_u7623_02_defconfig | 4 ++ configs/mt7623n_bpir2_defconfig | 4 ++ configs/mt7629_rfb_defconfig | 4 ++ configs/mvebu_ac5_rd_defconfig | 10 ++++ configs/novena_defconfig | 2 + configs/opos6uldev_defconfig | 2 + configs/pg_wcom_expu1_defconfig | 2 + configs/pg_wcom_expu1_update_defconfig | 2 + configs/pg_wcom_seli8_defconfig | 2 + configs/pg_wcom_seli8_update_defconfig | 2 + configs/poleg_evb_defconfig | 6 +++ configs/pxm2_defconfig | 2 + configs/qemu-ppce500_defconfig | 2 + configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig | 1 + configs/rastaban_defconfig | 2 + configs/rut_defconfig | 2 + configs/seeed_npi_imx6ull_defconfig | 2 + configs/slimbootloader_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 2 + configs/som-db5800-som-6867_defconfig | 1 + ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 2 + ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig | 2 + ...-microgea-stm32mp1-microdev2-of7_defconfig | 2 + ...mp15-microgea-stm32mp1-microdev2_defconfig | 2 + configs/stm32mp15_basic_defconfig | 2 + configs/stm32mp15_defconfig | 2 + configs/stm32mp15_dhcom_basic_defconfig | 2 + configs/stm32mp15_dhcor_basic_defconfig | 2 + configs/stm32mp15_trusted_defconfig | 2 + configs/stmark2_defconfig | 2 + ...able-x86-conga-qa3-e3845-pcie-x4_defconfig | 1 + .../theadorable-x86-conga-qa3-e3845_defconfig | 1 + configs/theadorable-x86-dfi-bt700_defconfig | 1 + configs/thuban_defconfig | 2 + configs/uniphier_ld4_sld8_defconfig | 10 ++++ configs/uniphier_v7_defconfig | 10 ++++ configs/uniphier_v8_defconfig | 10 ++++ configs/usbarmory_defconfig | 2 + env/Kconfig | 10 ++++ include/configs/M5208EVBE.h | 8 --- include/configs/M5235EVB.h | 7 --- include/configs/M5253DEMO.h | 2 - include/configs/M5272C3.h | 8 --- include/configs/M5282EVB.h | 8 --- include/configs/M53017EVB.h | 8 --- include/configs/M5329EVB.h | 8 --- include/configs/M5373EVB.h | 8 --- include/configs/MCR3000.h | 4 -- include/configs/MPC837XERDB.h | 4 -- include/configs/MPC8548CDS.h | 12 +---- include/configs/P1010RDB.h | 5 +- include/configs/P2041RDB.h | 4 +- include/configs/T102xRDB.h | 4 +- include/configs/T104xRDB.h | 4 +- include/configs/T208xQDS.h | 4 +- include/configs/T208xRDB.h | 4 +- include/configs/T4240RDB.h | 4 +- include/configs/amcore.h | 2 - include/configs/apalis-imx8.h | 3 -- include/configs/apalis-tk1.h | 6 --- include/configs/apalis_imx6.h | 6 --- include/configs/aristainetos2.h | 2 - include/configs/bcm_ns3.h | 2 - include/configs/cobra5272.h | 3 -- include/configs/colibri-imx6ull.h | 4 -- include/configs/colibri-imx8x.h | 4 -- include/configs/colibri_imx6.h | 6 --- include/configs/colibri_imx7.h | 4 -- include/configs/colibri_vf.h | 4 -- include/configs/controlcenterdc.h | 3 -- include/configs/gazerbeam.h | 4 -- include/configs/gw_ventana.h | 2 - include/configs/integratorcp.h | 3 -- include/configs/kontron-sl-mx6ul.h | 1 - include/configs/kontron-sl-mx8mm.h | 1 - include/configs/m53menlo.h | 1 - include/configs/microblaze-generic.h | 2 - include/configs/mt7622.h | 2 - include/configs/mt7623.h | 2 - include/configs/mt7629.h | 2 - include/configs/mvebu_alleycat-5.h | 5 -- include/configs/novena.h | 1 - include/configs/npi_imx6ull.h | 2 - include/configs/opos6uldev.h | 2 - include/configs/p1_p2_rdb_pc.h | 5 +- include/configs/poleg.h | 3 -- include/configs/qemu-ppce500.h | 2 - include/configs/siemens-am33x-common.h | 2 - include/configs/socfpga_vining_fpga.h | 1 - include/configs/stm32mp15_common.h | 3 -- include/configs/stmark2.h | 2 - include/configs/uniphier.h | 6 --- include/configs/usbarmory.h | 1 - include/configs/x86-common.h | 2 - include/configs/xea.h | 1 - include/env_default.h | 22 ++++---- net/Kconfig | 52 +++++++++++++++++++ 232 files changed, 643 insertions(+), 247 deletions(-) diff --git a/README b/README index b833aca2e5..c0f55b2586 100644 --- a/README +++ b/README @@ -734,38 +734,6 @@ The following options need to be configured: Some PHY like Intel LXT971A need extra delay after command issued before MII status register can be read -- IP address: - CONFIG_IPADDR - - Define a default value for the IP address to use for - the default Ethernet interface, in case this is not - determined through e.g. bootp. - (Environment variable "ipaddr") - -- Server IP address: - CONFIG_SERVERIP - - Defines a default value for the IP address of a TFTP - server to contact when using the "tftboot" command. - (Environment variable "serverip") - -- Gateway IP address: - CONFIG_GATEWAYIP - - Defines a default value for the IP address of the - default router where packets to other networks are - sent to. - (Environment variable "gatewayip") - -- Subnet mask: - CONFIG_NETMASK - - Defines a default value for the subnet mask (or - routing prefix) which is used to determine if an IP - address belongs to the local subnet or needs to be - forwarded through a router. - (Environment variable "netmask") - - BOOTP Recovery Mode: CONFIG_BOOTP_RANDOM_DELAY diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 0fc4ceda00..e0801c2594 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -68,4 +68,16 @@ source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" source "arch/powerpc/lib/Kconfig" +config USE_UBOOTPATH + bool "Set a default 'uboot' value in the environment" + help + Many default environment scripts will check the "uboot" variable + to determine the name of the file to load via tftp that will then + be written to flash. + +config UBOOTPATH + string "Value of the default 'uboot' value in the environment" + depends on USE_UBOOTPATH + default "u-boot.bin" + endmenu diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 20250c02a1..263e57f46a 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -26,8 +26,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5208EVBe" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 38c5076d5f..88c1116211 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -34,7 +34,17 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="u-boot.bin" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5235EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index cb5bcb7221..255f3b9d2f 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -34,7 +34,17 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="u-boot.bin" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5235EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 2684ce05f2..4de6290b7d 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -26,6 +26,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5253DEMO" # CONFIG_BLOCK_CACHE is not set CONFIG_SYS_IDE_MAXBUS=1 CONFIG_SYS_ATA_STRIDE=4 diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index f2d70a4e26..324daa016e 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -27,7 +27,17 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5272C3" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFFE00201 diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 0ef2e7b4ff..7988d25003 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -27,7 +27,17 @@ CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5282EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index b6783ab95b..d7c07aa2ea 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -28,8 +28,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M53017" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 6fede625fb..989af925f7 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -27,8 +27,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5329EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index fe70245497..7be2a27ba2 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -28,8 +28,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5329EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index b074cf520f..4b278a5b1c 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -28,8 +28,18 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_DATE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="M5373EVB" CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_UDP_CHECKSUM=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.162.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.162.1.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.162.1.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_FSL=y diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index 7d54807e64..3e16ffc2ef 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -55,6 +55,12 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.0.3" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.0.0.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.0.1" CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0x4000801 CONFIG_SYS_OR0_PRELIM=0xFFC00926 diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index a227ca86de..7287ca6b24 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -148,6 +148,7 @@ CONFIG_SPCR_TSECEP_3=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_CLKDIV_8=y CONFIG_FSL_SERDES=y +CONFIG_USE_UBOOTPATH=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y @@ -178,6 +179,10 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="TSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="mpc837x_rdb" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" CONFIG_FSL_SATA=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_SYS_BR0_PRELIM_BOOL=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index c6f5d87bb9..241cb80fde 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -14,6 +14,8 @@ CONFIG_SRIO1=y CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_USE_UBOOTPATH=y +CONFIG_UBOOTPATH="8548cds/u-boot.bin" CONFIG_PCIE1=y CONFIG_PHYS_64BIT=y CONFIG_SYS_MONITOR_LEN=524288 @@ -45,6 +47,17 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.253" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index b6ebac3980..5af056bd4f 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -14,6 +14,8 @@ CONFIG_SRIO1=y CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_USE_UBOOTPATH=y +CONFIG_UBOOTPATH="8548cds/u-boot.bin" CONFIG_PCIE1=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y @@ -44,6 +46,17 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.253" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index d272ede8d4..34d1938129 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -15,6 +15,8 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y +CONFIG_USE_UBOOTPATH=y +CONFIG_UBOOTPATH="8548cds/u-boot.bin" CONFIG_PCIE1=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y @@ -44,6 +46,17 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="8548cds/uImage.uboot" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.1.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.253" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfsroot" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_SPD_EEPROM=y CONFIG_CHIP_SELECTS_PER_CTRL=2 CONFIG_DDR_ECC=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index b32837c778..3fb993e201 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -81,6 +82,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 575d5bffcb..dc6dd717df 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -49,6 +50,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 21c752d974..bc29526f63 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -71,6 +72,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index a514d4ba36..5c42d5ee36 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -73,6 +74,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index db71e9bce4..b6e68d2788 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -80,6 +81,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 291c4a4038..fe24faa175 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -48,6 +49,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 8237da39c2..110a9b4ad3 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -70,6 +71,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 9cb53d64e2..fcd60f7a4e 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -72,6 +73,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 9574697108..76919c3881 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -82,6 +83,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7b3919dc16..b297258694 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -50,6 +51,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 3ad137dbd5..df80488cff 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -72,6 +73,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index cde657ce00..d27ea17a0b 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -74,6 +75,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 1faeab2c3b..88de4f9b92 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -81,6 +82,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 190d02fa50..2e86aec595 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -49,6 +50,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 5e32768c28..d5bbd6dca5 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -71,6 +72,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index bce763c73b..66efe739e9 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -73,6 +74,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index b9d52a755d..0f082f6e6e 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -81,6 +82,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index f86bc553da..88e10af29a 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -72,6 +73,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 0b9e108ba5..729e93eae2 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -74,6 +75,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 9f68ede4be..2860c286d7 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -51,6 +52,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 3dd2475643..0958a0a94b 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -80,6 +81,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index bd64dcc9ef..81bb26cb8f 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -71,6 +72,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 140d271a19..481009f307 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -73,6 +74,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 3f653895ab..49207eb65a 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -50,6 +51,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index abe064c04e..7e22b4e34c 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -83,6 +84,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 78a54dd461..62b25f0398 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -74,6 +75,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index a8bdb5a220..f5864dea4d 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -76,6 +77,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 7a533ed41d..ca04007288 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -53,6 +54,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3abb9d7f75..2420217b89 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -85,6 +86,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 551b5fca8e..22b0023ec6 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -76,6 +77,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 493e2c94c1..8c95203a4a 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -78,6 +79,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index fc82fa8ab9..b87c965d50 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y @@ -55,6 +56,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index b6ae81dd42..1d33cf6750 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -84,6 +85,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index cfbb3c274e..8d44e5b425 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -75,6 +76,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 36c6c7e26e..9155768c15 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -77,6 +78,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 691df7cc21..4f3be9eb24 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_SYS_MONITOR_LEN=786432 @@ -54,6 +55,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eTSEC1" +CONFIG_USE_HOSTNAME=y +CONFIG_USE_ROOTPATH=y CONFIG_LBA48=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_SYS_SPD_BUS_NUM=1 diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index f495205f5b..bf3365a480 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -15,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 23a7b66fbc..69f30d427f 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 7dfbde0469..c2dc0f21ee 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -62,6 +63,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index aea0b89f97..306432e41b 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -57,6 +58,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index e51db83263..bedea018dd 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -87,6 +88,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5472cccff8..f06bb02a27 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -18,6 +18,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -86,6 +87,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 0dd725128c..4f91dce109 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -20,6 +20,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -89,6 +90,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 8a2096c56d..c9d771e44b 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -12,6 +12,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -61,6 +62,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DDR_ECC=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index cc6a80447c..a55797eb9e 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -80,6 +81,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index cb270adc37..2f5a1a329d 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -79,6 +80,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 79530eac8f..afce81b107 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -82,6 +83,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index a671ae3d87..29b240fc14 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -54,6 +55,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC4" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_CAAM=y CONFIG_DDR_CLK_FREQ=66666666 CONFIG_CHIP_SELECTS_PER_CTRL=2 diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 637842cda2..ca960d368b 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -89,6 +90,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 35ab9931e7..eba73ee989 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -21,6 +21,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -88,6 +89,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 93b02a5e99..ae98a3586b 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -13,6 +13,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_NXP_ESBC=y CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000 CONFIG_PCIE1=y @@ -63,6 +64,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_DYNAMIC_DDR_CLK_FREQ=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7d25bbbb0b..76a1e58300 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -23,6 +23,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -91,6 +92,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 2846f63d47..fe440a469f 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -15,6 +15,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SRIO_PCIE_BOOT_SLAVE=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index a7dc88c0bf..f4f90d5ab2 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -15,6 +15,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -63,6 +64,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index a881488dbe..18baf56812 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -85,6 +86,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 562a79955c..df98e33f97 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -84,6 +85,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 00018033a3..efa48af3bf 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -19,6 +19,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -87,6 +88,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 0cb359de94..8e07b2a09c 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -59,6 +60,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index cbe1bb4e3f..69bebfacb0 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -86,6 +87,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 80a2c003e6..179fc63705 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -85,6 +86,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 99bee8e5ea..1d8a6b5f41 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -88,6 +89,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index aa6a053209..a1332a99b4 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -12,6 +12,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_T2080RDB_REV_D=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -60,6 +61,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC3" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index b445b6bde1..d906035a2b 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -17,6 +17,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -78,6 +79,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index a807ac8347..d2b270dd44 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -11,6 +11,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y CONFIG_SYS_CACHE_STASHING=y +CONFIG_USE_UBOOTPATH=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y @@ -53,6 +54,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FM1@DTSEC1" +CONFIG_USE_ROOTPATH=y CONFIG_FSL_SATA_V2=y CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_FSL_CAAM=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index cebb79f733..6775379428 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_CMD_DIAG=y CONFIG_ENV_IS_IN_FLASH=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="AMCORE" # CONFIG_NET is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 6226d50c8a..395202bc29 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -48,6 +48,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_MXC_GPIO=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 70ef62a778..54b781b9c9 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -54,6 +54,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_SPL_DM=y CONFIG_SYS_I2C_TEGRA=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 68655cf15b..28fc03d85a 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -79,6 +79,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 4c7ded9d22..d7ac130179 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -68,6 +68,8 @@ CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="aristainetos2" CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index a23c77af89..562eb10453 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -68,6 +68,8 @@ CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="aristainetos2" CONFIG_VERSION_VARIABLE=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 503cee91a2..14d435076d 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig index 4928a203d0..956e797e43 100644 --- a/configs/bcm_ns3_defconfig +++ b/configs/bcm_ns3_defconfig @@ -41,6 +41,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y # CONFIG_DOS_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="NS3" CONFIG_CLK=y CONFIG_CLK_CCF=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 321121e3f7..83d5712e61 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -43,6 +43,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index a38b3b78c0..401506e219 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -84,6 +84,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 570c4e82a4..64ebef4b50 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -67,6 +67,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index 43cf53045b..3098857d6e 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index aa3d6f2b9d..b933a2352e 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index e83f2dfe7f..96c739cbfb 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 2fdb882dc4..377781f0bc 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -25,6 +25,10 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_PING=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.100.2" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.100.1" CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_BR0_PRELIM_BOOL=y CONFIG_SYS_BR0_PRELIM=0xFFE00201 diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index c0248dca95..b4de88aead 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -54,6 +54,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index d16b66df7c..f2a0d79ccc 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -63,6 +63,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index 6896236045..e4c418958b 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -47,6 +47,12 @@ CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_TFTP_TSIZE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_CLK_IMX8=y CONFIG_CPU=y CONFIG_FXL6408_GPIO=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index aa24dea1f0..bad7b8a54e 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -79,6 +79,12 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 4428b55503..7e24dcd400 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -61,6 +61,12 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index bc9abc82d5..fe785d7e31 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -52,6 +52,12 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_BLOCKSIZE=16352 +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 3352b8e923..2642e8975b 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -66,6 +66,12 @@ CONFIG_ENV_RANGE=0x80000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.10.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.10.1" CONFIG_DFU_NAND=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 CONFIG_VYBRID_GPIO=y diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig index 15b7f27ae6..3a84190bbf 100644 --- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig +++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig @@ -60,6 +60,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 8a1defd043..bb8b9ef312 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig index e8fb032bba..ffa48fcb93 100644 --- a/configs/controlcenterdc_defconfig +++ b/configs/controlcenterdc_defconfig @@ -66,8 +66,11 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="ccdc.img" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="ccdc" CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 +CONFIG_USE_ROOTPATH=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_SCSI_AHCI=y CONFIG_DM_PCA953X=y diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index e4da59bae9..ec672e59e8 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig index e297494663..4db7289916 100644 --- a/configs/coreboot_defconfig +++ b/configs/coreboot_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 8b47f2d89f..8e53eec74e 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index 038cbbe5b9..69ad017f98 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig index 63b8c8f92d..bd8b2e1155 100644 --- a/configs/dfi-bt700-q7x-151_defconfig +++ b/configs/dfi-bt700-q7x-151_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index cc1fb489eb..8d1c6fd44a 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -84,6 +84,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index 4ae74dbd2e..905f375a3e 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -36,6 +36,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_REGEX is not set diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index 3f1e80120c..605d49ff8c 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -36,6 +36,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_REGEX is not set diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig index 8d1fc22eb9..a5c629b46f 100644 --- a/configs/efi-x86_payload32_defconfig +++ b/configs/efi-x86_payload32_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 89e6d1febc..5cde04a5ac 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index ee731f3c0a..d42eda2055 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -85,6 +85,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 141467bbe3..0d2ebdab92 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -46,6 +46,7 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index a852b96d4e..9d09d9c37f 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -162,6 +162,9 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xFE090000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="gazerbeam" +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_AXI=y CONFIG_IHS_AXI=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index f999b44775..5308a8e3e9 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -97,6 +97,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.146" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 4c6291f0c5..37fc1e5143 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -97,6 +97,10 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.146" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 4e062e477e..f33625b2ca 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -100,6 +100,10 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.146" CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index 48be3c5f4a..b29c62fc59 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -83,6 +83,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="xea" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_DEVRES=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index 26227341d9..b7edd3bae4 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -63,6 +63,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="xea" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_DEVRES=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index 7417b53e86..6d9d0e8999 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 36b71fc401..2d40a5f937 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index 947d21ef35..4505123d4f 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index 630fe0d813..bbdf86baeb 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -31,6 +31,10 @@ CONFIG_CMD_ARMFLASH=y # CONFIG_CMD_SETEXPR is not set CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.104" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.100" # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 7391e59764..02b963e7c3 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -66,6 +66,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="kontron-mx6ul" CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y CONFIG_DM_I2C=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 62fd984deb..4b54813415 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -77,6 +77,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="kontron-mx8mm" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index e332de2aa9..b70d10433d 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -75,6 +75,8 @@ CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="boot/fitImage" CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC0" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="m53menlo" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041 diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 186521aac6..be34941805 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_JFFS2=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="microblaze-generic" CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index e8ef832f89..679b6e3de5 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -59,6 +59,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 3f18addd5a..c09c2221a5 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -26,6 +26,10 @@ CONFIG_CMD_SMC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.3" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index c56b4bb82f..8dd65d57e3 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -35,6 +35,10 @@ CONFIG_CMD_READ=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index e36943b0fc..cafac4278b 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -36,6 +36,10 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index d7669d5577..76fd135d93 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -57,6 +57,10 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.1.1" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.2" CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig index 9235a398c5..a27202eb23 100644 --- a/configs/mvebu_ac5_rd_defconfig +++ b/configs/mvebu_ac5_rd_defconfig @@ -43,6 +43,16 @@ CONFIG_CMD_UBI=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="0.0.0.0" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="0.0.0.0" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/srv/nfs/" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="0.0.0.0" CONFIG_CLK=y CONFIG_CLK_MVEBU=y CONFIG_DM_PCA953X=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 3999ae1c82..cc74abfcd7 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -59,6 +59,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="novena" CONFIG_VERSION_VARIABLE=y CONFIG_NETCONSOLE=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index cdb246fc64..867b89d3fe 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -77,6 +77,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/tftpboot/opos6ul-root" CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index b57e588f4e..b7c0b0d1e8 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -70,6 +70,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 9029e7babc..a5193cb463 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -68,6 +68,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index aa74e1746a..1b9e0b6c91 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -70,6 +70,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 2b18a88d44..c193f7bb40 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -68,6 +68,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y diff --git a/configs/poleg_evb_defconfig b/configs/poleg_evb_defconfig index 914fc39a7e..b7e39eb31f 100644 --- a/configs/poleg_evb_defconfig +++ b/configs/poleg_evb_defconfig @@ -28,6 +28,12 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_UUID=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.0.2" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.0.1" CONFIG_CLK=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 6b361f8211..e655b18f02 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -82,6 +82,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index cdad1b0995..a19d555f7d 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -8,6 +8,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_QEMU_PPCE500=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_USE_UBOOTPATH=y CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -39,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_ROOTPATH=y CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_LBA48=y CONFIG_CHIP_SELECTS_PER_CTRL=0 diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 0f4811e5d7..9f1cb2675d 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -58,6 +58,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SYS_IDE_MAXDEVICE=4 diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index a8222122fc..04528ad7cd 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SYS_IDE_MAXDEVICE=4 diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 861f0f59bc..fe09c34d5b 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -84,6 +84,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 30c5d4a5ad..6c3ba4cc72 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -83,6 +83,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index 34d23fdb84..abcd63c7ec 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -49,6 +49,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig index f5d16f64d7..dbfed814de 100644 --- a/configs/slimbootloader_defconfig +++ b/configs/slimbootloader_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y # CONFIG_ACPIGEN is not set diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index cdad36bbfd..6d859b3274 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -63,6 +63,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="socfpga_vining_fpga" CONFIG_VERSION_VARIABLE=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig index a75ec667d5..c4752a2b0a 100644 --- a/configs/som-db5800-som-6867_defconfig +++ b/configs/som-db5800-som-6867_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index df90e64cbb..41074d50ff 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index a242f1b158..c9dbd485bc 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index 5f1fc90113..6f8293c7ee 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 65d9b5a729..a12a150f3b 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -58,6 +58,8 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_DM_HWSPINLOCK=y CONFIG_HWSPINLOCK_STM32=y CONFIG_DM_I2C=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 86ebbef0a6..2d4b7cbc7b 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -94,6 +94,8 @@ CONFIG_SYS_MMC_ENV_DEV=-1 # CONFIG_SPL_ENV_IS_NOWHERE is not set # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index caa79e6883..22cf538b41 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -66,6 +66,8 @@ CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 26c2e73aa0..7db562c542 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -106,6 +106,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index f76e13eafd..c94f03569f 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -103,6 +103,8 @@ CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 3309c2e792..e00c00f374 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -67,6 +67,8 @@ CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_TFTP_TSIZE=y +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.1.1" CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 5ee2edcf5e..ae7a9cf6da 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -37,6 +37,8 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-flash.0:1m(u-boot),7m(kernel),-(rootfs)" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_CS=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="stmark2" # CONFIG_NET is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index 205ac87748..74c4a4967d 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -56,6 +56,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index b6d59215e7..194b0519ea 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -55,6 +55,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index fea35cd915..39c8a87fbe 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" CONFIG_TFTP_TSIZE=y +CONFIG_USE_ROOTPATH=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_LBA48=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index aef524052b..a9e37170f4 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -84,6 +84,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/opt/eldk" CONFIG_SPL_DM=y # CONFIG_SPL_BLK is not set CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 5665cf3879..b361e3f403 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -50,6 +50,16 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.11.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.11.10" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfs/root/path" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.11.1" CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index e3087a9109..765d42a3e6 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -51,6 +51,16 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.11.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.11.10" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfs/root/path" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.11.1" CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index 1b0e0d0da7..6a0e2666cf 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -38,6 +38,16 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="Image" CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_USE_GATEWAYIP=y +CONFIG_GATEWAYIP="192.168.11.1" +CONFIG_USE_IPADDR=y +CONFIG_IPADDR="192.168.11.10" +CONFIG_USE_NETMASK=y +CONFIG_NETMASK="255.255.255.0" +CONFIG_USE_ROOTPATH=y +CONFIG_ROOTPATH="/nfs/root/path" +CONFIG_USE_SERVERIP=y +CONFIG_SERVERIP="192.168.11.1" CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig index ed2bcc69fc..66c969f95e 100644 --- a/configs/usbarmory_defconfig +++ b/configs/usbarmory_defconfig @@ -27,6 +27,8 @@ CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="usbarmory" CONFIG_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MXC=y CONFIG_FSL_IIM=y diff --git a/env/Kconfig b/env/Kconfig index 4e506ae262..c13a5b0d46 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -866,6 +866,16 @@ config ETHPRIME help The value to set the "ethprime" variable to. +config USE_HOSTNAME + bool "Set a default 'hostname' value in the environment" + default y if X86 + +config HOSTNAME + string "Value of the default 'hostname' value in the environment" + depends on USE_HOSTNAME + default "x86" if X86 + default "unknown" + config VERSION_VARIABLE bool "Add a 'ver' environment variable with the U-Boot version" help diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index b360238b33..e14650fe0d 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,14 +17,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5208EVBe" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index ed45eccb62..220524bfae 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -26,14 +26,7 @@ #define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ -#define CONFIG_HOSTNAME "M5235EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index ad55938348..65a7aa0408 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -36,8 +36,6 @@ "" #endif -#define CONFIG_HOSTNAME "M5253DEMO" - /* I2C */ #define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C)) #define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index a9339e5052..c58d19c810 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -29,14 +29,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5272C3" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index bde9e770e5..e23439fd78 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -29,14 +29,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5282EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 439ed93a23..ac2bd0b224 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -30,14 +30,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M53017" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 72f0c63a1e..a86a117fd8 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,14 +22,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5329EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 4e8b54e01f..b2ad03cc3c 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,14 +24,6 @@ /* I2C */ -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5373EVB" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 232cf9e998..f8368823aa 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -52,10 +52,6 @@ "${ofl_args}; " \ "bootm ${loadaddr} - 0xf00000\0" -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_NETMASK 255.0.0.0 - /* Miscellaneous configurable options */ /* Definitions for initial stack pointer and data area (in DPRAM) */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index dbfcdfb738..7dff3cc691 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -197,10 +197,6 @@ #define CONFIG_NETDEV "eth1" -#define CONFIG_HOSTNAME "mpc837x_rdb" -#define CONFIG_ROOTPATH "/nfsroot" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_FDTFILE "mpc8379_rdb.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 34b876f829..1f1eacdb69 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -298,20 +298,10 @@ * Environment Configuration */ -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ "protect off " __stringify(CONFIG_TEXT_BASE) \ " +$filesize; " \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f79c62adba..d83563d618 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -380,13 +380,10 @@ extern unsigned long get_sdram_size(void); * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "loadaddr=1000000\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 707157e4a9..0f0cdb3a68 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -306,8 +306,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin #define __USB_PHY_TYPE utmi @@ -315,7 +313,7 @@ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b590f12739..e815d9f81a 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -421,8 +421,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define __USB_PHY_TYPE utmi #ifdef CONFIG_ARCH_T1024 @@ -441,7 +439,7 @@ ARCH_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ "netdev=eth0\0" \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 9d805f446b..6fe0bd6828 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -411,8 +411,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" @@ -434,7 +432,7 @@ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 804b7ec4c1..79b3d7af4e 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -419,8 +419,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define __USB_PHY_TYPE utmi @@ -430,7 +428,7 @@ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index d8213b4662..2a32fe37aa 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -385,8 +385,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ #define __USB_PHY_TYPE utmi @@ -396,7 +394,7 @@ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 958933689d..d8c4de5b3d 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -138,8 +138,6 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ #define HVBOOT \ "setenv bootargs config-addr=0x60000000; " \ @@ -386,7 +384,7 @@ "bank_intlv=auto;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index ee0be972d2..ca29346fe6 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -8,8 +8,6 @@ #ifndef __AMCORE_CONFIG_H #define __AMCORE_CONFIG_H -#define CONFIG_HOSTNAME "AMCORE" - #define CFG_SYS_UART_PORT 0 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index cf23837863..aa3dcf4a88 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -14,9 +14,6 @@ #define USDHC2_BASE_ADDR 0x5b020000 /* Networking */ -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x84000000\0" \ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index f0a02ae179..1d478078b2 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -33,12 +33,6 @@ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - #define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ "boot part 0 1 mmcpart 0; " \ "rootfs part 0 2 mmcpart 0; " \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index a3c86545f0..25a84458f5 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -35,12 +35,6 @@ /* Command definition */ -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 6faf544d21..8541354571 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -11,8 +11,6 @@ #ifndef __ARISTAINETOS2_CONFIG_H #define __ARISTAINETOS2_CONFIG_H -#define CONFIG_HOSTNAME "aristainetos2" - #if (CONFIG_SYS_BOARD_VERSION == 5) #define CONSOLE_DEV "ttymxc1" #elif (CONFIG_SYS_BOARD_VERSION == 6) diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index b5469880fe..fc176dc201 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -9,8 +9,6 @@ #include -#define CONFIG_HOSTNAME "NS3" - /* Physical Memory Map */ #define V2M_BASE 0x80000000 #define PHYS_SDRAM_1 V2M_BASE diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 6d6e2fc696..8c83c3ac06 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -91,9 +91,6 @@ enter a valid image address in flash */ /* User network settings */ -#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ -#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ - #endif /*---*/ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index c0c3b4e035..2f09a264cb 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -20,10 +20,6 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 1 -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #if defined(CONFIG_TARGET_COLIBRI_IMX6ULL_EMMC) #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 6002d8d5c9..215c633a4c 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -14,10 +14,6 @@ #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000 -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #define MEM_LAYOUT_ENV_SETTINGS \ "fdt_addr_r=0x83000000\0" \ "kernel_addr_r=0x81000000\0" \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 60a3862a4d..19daad21cb 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -30,12 +30,6 @@ /* Command definition */ -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 32a79b0255..48c3f01547 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -21,10 +21,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #if defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) #define UBOOT_UPDATE \ "uboot_hwpart=1\0" \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index fa778ec9e2..8a790400b4 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -16,10 +16,6 @@ /* NAND support */ -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - #define CONFIG_FDTADDR 0x84000000 #define MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 5da2778b67..119a834fe7 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -21,9 +21,6 @@ * Environment Configuration */ -#define CONFIG_HOSTNAME "ccdc" -#define CONFIG_ROOTPATH "/opt/nfsroot" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 36dcee87c5..671b75e698 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -55,10 +55,6 @@ * Environment Configuration */ -/* TODO: Turn into string option and migrate to Kconfig */ -#define CONFIG_HOSTNAME "gazerbeam" -#define CONFIG_ROOTPATH "/opt/nfsroot" - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 4d0a78c626..298a8f5aa2 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -57,7 +57,5 @@ /* Persistent Environment Config */ /* Environment */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.146 #endif /* __CONFIG_H */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 25bb41ebc4..596e4ff8c3 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -19,9 +19,6 @@ /* Integrator CP-specific configuration */ #define CFG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ -#define CONFIG_SERVERIP 192.168.1.100 -#define CONFIG_IPADDR 192.168.1.104 - /* * Miscellaneous configurable options */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 6fcacdb0c6..7c5f673c0f 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -23,7 +23,6 @@ /* Board and environment settings */ #define CONFIG_MXC_UART_BASE UART4_BASE -#define CONFIG_HOSTNAME "kontron-mx6ul" #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 80a3230460..beb1926c12 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -23,7 +23,6 @@ #define CFG_SYS_INIT_RAM_SIZE 0x200000 /* Board and environment settings */ -#define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 66591390d9..189b2113f7 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -84,7 +84,6 @@ /* * Extra Environments */ -#define CONFIG_HOSTNAME "m53menlo" #define CONFIG_EXTRA_ENV_SETTINGS \ "consdev=ttymxc0\0" \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index edd2466caa..b8b08974c7 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -16,8 +16,6 @@ # define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -#define CONFIG_HOSTNAME "microblaze-generic" - /* architecture dependent code */ #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index 8c297266d8..6541512953 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -18,7 +18,5 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.3 #endif diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 39a7ba7663..93161bd24f 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -33,8 +33,6 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" /* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index bfa44aacc7..99b09ad41e 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -28,7 +28,5 @@ #define CFG_SYS_SDRAM_BASE 0x40000000 /* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 #endif diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 5c9620371e..3ad3aefa75 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -15,11 +15,6 @@ 115200, 230400, 460800, 921600 } /* Default Env vars */ -#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */ -#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */ -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 0.0.0.0 -#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ diff --git a/include/configs/novena.h b/include/configs/novena.h index 4e46dfc526..6e4bdce1c0 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -25,7 +25,6 @@ */ /* Booting Linux */ -#define CONFIG_HOSTNAME "novena" /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 09c4ddb664..2eebd0c9a4 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -18,8 +18,6 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_NETMASK 255.255.255.0 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index e42a736136..5c44b9dcb2 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -27,6 +27,4 @@ /* LCD */ #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#define CONFIG_ROOTPATH "/tftpboot/opos6ul-root" - #endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index eb2c5a2d83..ee25990b03 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -396,15 +396,12 @@ /* * Environment Configuration */ -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #include "p1_p2_bootsrc.h" #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ +"uboot=" CONFIG_UBOOTPATH "\0" \ "loadaddr=1000000\0" \ "bootfile=uImage\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 518d7a3639..075729e5d3 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -14,9 +14,6 @@ #define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_IPADDR 192.168.0.2 -#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 30a9eae852..d056189958 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -58,7 +58,5 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * Environment Configuration */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ #endif /* __QEMU_PPCE500_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5a001716fb..1b1787a3d3 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -17,8 +17,6 @@ /* commands to include */ -#define CONFIG_ROOTPATH "/opt/eldk" - /* Clock Defines */ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 70d9f3607a..d88b07bc15 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -13,7 +13,6 @@ /* Booting Linux */ /* Extra Environment */ -#define CONFIG_HOSTNAME "socfpga_vining_fpga" /* * Active LOW GPIO buttons: diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index c9cfadd9ce..9715dfad1c 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -24,9 +24,6 @@ /* NAND support */ /* Ethernet need */ -#ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SERVERIP 192.168.1.1 -#endif #define STM32MP_FIP_IMAGE_GUID \ EFI_GUID(0x19d5df83, 0x11b0, 0x457b, 0xbe, 0x2c, \ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index f81cef0a2c..ce941d832a 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -8,8 +8,6 @@ #ifndef __STMARK2_CONFIG_H #define __STMARK2_CONFIG_H -#define CONFIG_HOSTNAME "stmark2" - #define CFG_SYS_UART_PORT 0 #define LDS_BOARD_TEXT \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 8cd81f1cdd..7fee64029d 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -46,10 +46,6 @@ /* * Network Configuration */ -#define CONFIG_SERVERIP 192.168.11.1 -#define CONFIG_IPADDR 192.168.11.10 -#define CONFIG_GATEWAYIP 192.168.11.1 -#define CONFIG_NETMASK 255.255.255.0 #if defined(CONFIG_ARM64) /* ARM Trusted Firmware */ @@ -62,8 +58,6 @@ "third_image=u-boot.bin\0" #endif -#define CONFIG_ROOTPATH "/nfs/root/path" - #ifdef CONFIG_FIT #define KERNEL_ADDR_R_OFFSET "0x05100000" #define LINUXBOOT_ENV_SETTINGS \ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index a2bc3cd23a..7f79c6342f 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -28,7 +28,6 @@ #define CONFIG_MXC_USB_FLAGS 0 /* Linux boot */ -#define CONFIG_HOSTNAME "usbarmory" #define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 3e17b53dde..9bf2462010 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -41,8 +41,6 @@ */ /* Default environment */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_HOSTNAME "x86" #define CONFIG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) #define CONFIG_OTHBOOTARGS "othbootargs=\0" diff --git a/include/configs/xea.h b/include/configs/xea.h index b432ab2dc8..a3dc0c74eb 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -26,7 +26,6 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environment */ -#define CONFIG_HOSTNAME "xea" #define CONFIG_EXTRA_ENV_SETTINGS \ "bootmode=update\0" \ diff --git a/include/env_default.h b/include/env_default.h index 7c9c00a969..3b7685ee26 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -53,11 +53,11 @@ const char default_environment[] = { #ifdef CONFIG_ETHPRIME "ethprime=" CONFIG_ETHPRIME "\0" #endif -#ifdef CONFIG_IPADDR - "ipaddr=" __stringify(CONFIG_IPADDR) "\0" +#ifdef CONFIG_USE_IPADDR + "ipaddr=" CONFIG_IPADDR "\0" #endif -#ifdef CONFIG_SERVERIP - "serverip=" __stringify(CONFIG_SERVERIP) "\0" +#ifdef CONFIG_USE_SERVERIP + "serverip=" CONFIG_SERVERIP "\0" #endif #ifdef CONFIG_SYS_DISABLE_AUTOLOAD "autoload=0\0" @@ -65,17 +65,17 @@ const char default_environment[] = { #ifdef CONFIG_PREBOOT_DEFINED "preboot=" CONFIG_PREBOOT "\0" #endif -#ifdef CONFIG_ROOTPATH +#ifdef CONFIG_USE_ROOTPATH "rootpath=" CONFIG_ROOTPATH "\0" #endif -#ifdef CONFIG_GATEWAYIP - "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0" +#ifdef CONFIG_USE_GATEWAYIP + "gatewayip=" CONFIG_GATEWAYIP "\0" #endif -#ifdef CONFIG_NETMASK - "netmask=" __stringify(CONFIG_NETMASK) "\0" +#ifdef CONFIG_USE_NETMASK + "netmask=" CONFIG_NETMASK "\0" #endif -#ifdef CONFIG_HOSTNAME - "hostname=" CONFIG_HOSTNAME "\0" +#ifdef CONFIG_USE_HOSTNAME + "hostname=" CONFIG_HOSTNAME "\0" #endif #ifdef CONFIG_USE_BOOTFILE "bootfile=" CONFIG_BOOTFILE "\0" diff --git a/net/Kconfig b/net/Kconfig index a1ec3f8542..4215889127 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -174,6 +174,58 @@ config BOOTP_MAX_ROOT_PATH_LEN help Select maximal length of option 17 root path. +config USE_GATEWAYIP + bool "Set a default 'gateway' value in the environment" + help + Defines a default value for the IP address of the default router + where packets to other networks are sent to. (Environment variable + "gatewayip") + +config GATEWAYIP + string "Value of the default 'gateway' value in the environment" + depends on USE_GATEWAYIP + +config USE_IPADDR + bool "Set a default 'ipaddr' value in the environment" + help + Define a default value for the IP address to use for the default + Ethernet interface, in case this is not determined through e.g. + bootp. (Environment variable "ipaddr") + +config IPADDR + string "Value of the default 'ipaddr' value in the environment" + depends on USE_IPADDR + +config USE_NETMASK + bool "Set a default 'netmask' value in the environment" + help + Defines a default value for the subnet mask (or routing prefix) which + is used to determine if an IP address belongs to the local subnet or + needs to be forwarded through a router. (Environment variable "netmask") + +config NETMASK + string "Value of the default 'netmask' value in the environment" + depends on USE_NETMASK + +config USE_ROOTPATH + bool "Set a default 'rootpath' value in the environment" + +config ROOTPATH + string "Value of the default 'rootpath' value in the environment" + depends on USE_ROOTPATH + default "/opt/nfsroot" + +config USE_SERVERIP + bool "Set a default 'serverip' value in the environment" + help + Defines a default value for the IP address of a TFTP server to + contact when using the "tftboot" command. (Environment variable + "serverip") + +config SERVERIP + string "Value of the default 'serverip' value in the environment" + depends on USE_SERVERIP + config PROT_TCP bool "TCP stack" help From b5f7d8816225f869e3fd63d78d017308af0ac224 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:28 -0500 Subject: [PATCH 195/424] arm: samsung: Rename CONFIG_G_DNL_*_NUM variables Following how g_dnl_bind_fixup is used on other platforms, rename the unchanging defines used here to be prefixed with EXYNOS rather than Samsung, and define them here. Cc: Minkyu Kang Cc: Jaehoon Chung Signed-off-by: Tom Rini --- board/samsung/common/gadget.c | 14 ++++++++++---- include/configs/dh_imx6.h | 4 ---- include/configs/exynos4-common.h | 6 ------ include/configs/odroid_xu3.h | 8 -------- include/configs/s5p_goni.h | 7 ------- include/configs/socfpga_common.h | 4 ---- 6 files changed, 10 insertions(+), 33 deletions(-) diff --git a/board/samsung/common/gadget.c b/board/samsung/common/gadget.c index 6d783e61e0..9487f9ec4e 100644 --- a/board/samsung/common/gadget.c +++ b/board/samsung/common/gadget.c @@ -7,14 +7,20 @@ #include #include +#define EXYNOS_G_DNL_THOR_VENDOR_NUM 0x04E8 +#define EXYNOS_G_DNL_THOR_PRODUCT_NUM 0x685D + +#define EXYNOS_G_DNL_UMS_VENDOR_NUM 0x0525 +#define EXYNOS_G_DNL_UMS_PRODUCT_NUM 0xA4A5 + int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { if (!strcmp(name, "usb_dnl_thor")) { - put_unaligned(CONFIG_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); - put_unaligned(CONFIG_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); + put_unaligned(EXYNOS_G_DNL_THOR_VENDOR_NUM, &dev->idVendor); + put_unaligned(EXYNOS_G_DNL_THOR_PRODUCT_NUM, &dev->idProduct); } else if (!strcmp(name, "usb_dnl_ums")) { - put_unaligned(CONFIG_G_DNL_UMS_VENDOR_NUM, &dev->idVendor); - put_unaligned(CONFIG_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); + put_unaligned(EXYNOS_G_DNL_UMS_VENDOR_NUM, &dev->idVendor); + put_unaligned(EXYNOS_G_DNL_UMS_PRODUCT_NUM, &dev->idProduct); } else { put_unaligned(CONFIG_USB_GADGET_VENDOR_NUM, &dev->idVendor); put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct); diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index f9b3d19480..3aed6299ed 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -38,10 +38,6 @@ /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB IDs */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #endif #endif diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index bf965e5ced..e8c182bc2f 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -12,12 +12,6 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 5bbe7aadcb..bf63a4de07 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -20,14 +20,6 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 -/* THOR */ -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_USB_GADGET_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D - -/* UMS */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - #define CONFIG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 97f5dd0e47..da83db1f68 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -24,13 +24,6 @@ /* USB Composite download gadget - g_dnl */ #define DFU_DEFAULT_POLL_TIMEOUT 300 -/* USB Samsung's IDs */ - -#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - /* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ /* partitions definitions */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index bbbdea6664..088cd4d4f7 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -83,10 +83,6 @@ */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) #define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB IDs */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 #endif /* From 495fc3e836df25e24a1b228b78f3e45166fd2f96 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:29 -0500 Subject: [PATCH 196/424] env: eeprom: Remove CONFIG_I2C_ENV_EEPROM_BUS support This functionality is currently unused, and has not been migrated to using DM_I2C, even. Drop this. Signed-off-by: Tom Rini --- env/Kconfig | 7 ------- env/eeprom.c | 59 +++++++--------------------------------------------- 2 files changed, 8 insertions(+), 58 deletions(-) diff --git a/env/Kconfig b/env/Kconfig index c13a5b0d46..c28d9e89f6 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -78,13 +78,6 @@ config ENV_IS_IN_EEPROM still be one byte because the extra address bits are hidden in the chip address. - - CONFIG_I2C_ENV_EEPROM_BUS - if you have an Environment on an EEPROM reached over - I2C muxes, you can define here, how to reach this - EEPROM. For example: - - #define CONFIG_I2C_ENV_EEPROM_BUS 1 - EEPROM which holds the environment, is reached over a pca9547 i2c mux with address 0x70, channel 3. diff --git a/env/eeprom.c b/env/eeprom.c index f8556a4721..7ce7e9972b 100644 --- a/env/eeprom.c +++ b/env/eeprom.c @@ -15,55 +15,12 @@ #include #include #include -#if defined(CONFIG_I2C_ENV_EEPROM_BUS) -#include -#endif #include #include #include /* for BUG_ON */ DECLARE_GLOBAL_DATA_PTR; -static int eeprom_bus_read(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) -{ - int rcode; -#if defined(CONFIG_I2C_ENV_EEPROM_BUS) - int old_bus = i2c_get_bus_num(); - - if (old_bus != CONFIG_I2C_ENV_EEPROM_BUS) - i2c_set_bus_num(CONFIG_I2C_ENV_EEPROM_BUS); -#endif - - rcode = eeprom_read(dev_addr, offset, buffer, cnt); - -#if defined(CONFIG_I2C_ENV_EEPROM_BUS) - i2c_set_bus_num(old_bus); -#endif - - return rcode; -} - -static int eeprom_bus_write(unsigned dev_addr, unsigned offset, - uchar *buffer, unsigned cnt) -{ - int rcode; -#if defined(CONFIG_I2C_ENV_EEPROM_BUS) - int old_bus = i2c_get_bus_num(); - - if (old_bus != CONFIG_I2C_ENV_EEPROM_BUS) - i2c_set_bus_num(CONFIG_I2C_ENV_EEPROM_BUS); -#endif - - rcode = eeprom_write(dev_addr, offset, buffer, cnt); - -#if defined(CONFIG_I2C_ENV_EEPROM_BUS) - i2c_set_bus_num(old_bus); -#endif - - return rcode; -} - static int env_eeprom_load(void) { char buf_env[CONFIG_ENV_SIZE]; @@ -82,11 +39,11 @@ static int env_eeprom_load(void) for (i = 0; i < 2; i++) { /* read CRC */ - eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off_env[i] + offsetof(env_t, crc), (uchar *)&crc[i], sizeof(ulong)); /* read FLAGS */ - eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off_env[i] + offsetof(env_t, flags), (uchar *)&flags[i], sizeof(uchar)); @@ -96,7 +53,7 @@ static int env_eeprom_load(void) while (len > 0) { int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; - eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, rdbuf, n); crc_tmp = crc32(crc_tmp, rdbuf, n); @@ -138,7 +95,7 @@ static int env_eeprom_load(void) eeprom_init(-1); /* prepare for EEPROM read/write */ /* read old CRC */ - eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_ENV_OFFSET + offsetof(env_t, crc), (uchar *)&crc, sizeof(ulong)); @@ -148,7 +105,7 @@ static int env_eeprom_load(void) while (len > 0) { int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; - eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_ENV_OFFSET + off, rdbuf, n); new = crc32(new, rdbuf, n); len -= n; @@ -168,7 +125,7 @@ static int env_eeprom_load(void) off = CONFIG_ENV_OFFSET_REDUND; #endif - eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, (uchar *)buf_env, CONFIG_ENV_SIZE); return env_import(buf_env, 1, H_EXTERNAL); @@ -197,12 +154,12 @@ static int env_eeprom_save(void) env_new.flags = ENV_REDUND_ACTIVE; #endif - rc = eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR, + rc = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, off, (uchar *)&env_new, CONFIG_ENV_SIZE); #ifdef CONFIG_ENV_OFFSET_REDUND if (rc == 0) { - eeprom_bus_write(CONFIG_SYS_I2C_EEPROM_ADDR, + eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, off_red + offsetof(env_t, flags), (uchar *)&flag_obsolete, 1); From 1353b25ec58eba4cd26f4101ebb1b6047838a105 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:30 -0500 Subject: [PATCH 197/424] i2c: Remove CONFIG_I2C_MULTI_BUS This functionality is part of the legacy I2C subsystem and is currently unused anywhere. Remove the remaining references. Signed-off-by: Tom Rini --- README | 10 +-------- cmd/i2c.c | 15 +++++-------- drivers/i2c/mv_i2c.c | 33 ---------------------------- include/configs/display5.h | 3 --- include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/novena.h | 3 --- 6 files changed, 7 insertions(+), 58 deletions(-) diff --git a/README b/README index c0f55b2586..1209633176 100644 --- a/README +++ b/README @@ -984,21 +984,13 @@ The following options need to be configured: CFG_SYS_I2C_NOPROBES This option specifies a list of I2C devices that will be skipped - when the 'i2c probe' command is issued. If CONFIG_I2C_MULTI_BUS - is set, specify a list of bus-device pairs. Otherwise, specify - a 1D array of device addresses + when the 'i2c probe' command is issued. e.g. - #undef CONFIG_I2C_MULTI_BUS #define CFG_SYS_I2C_NOPROBES {0x50,0x68} will skip addresses 0x50 and 0x68 on a board with one I2C bus - #define CONFIG_I2C_MULTI_BUS - #define CFG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} - - will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 - CFG_SYS_RTC_BUS_NUM If defined, then this indicates the I2C bus number for the RTC. diff --git a/cmd/i2c.c b/cmd/i2c.c index da8b4c2555..f204061cf0 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -98,7 +98,7 @@ static uint i2c_mm_last_alen; * pairs. The following macros take care of this */ #if defined(CFG_SYS_I2C_NOPROBES) -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) static struct { uchar bus; @@ -1764,8 +1764,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, * Returns zero on success, CMD_RET_USAGE in case of misuse and negative * on error. */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) || \ - CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) static int do_i2c_bus_num(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -1915,10 +1914,9 @@ static struct cmd_tbl cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(bus, 1, 1, do_i2c_show_bus, "", ""), #endif U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""), -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ - defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""), -#endif /* CONFIG_I2C_MULTI_BUS */ +#endif #if defined(CONFIG_I2C_EDID) U_BOOT_CMD_MKENT(edid, 1, 1, do_edid, "", ""), #endif /* CONFIG_I2C_EDID */ @@ -1992,10 +1990,9 @@ static char i2c_help_text[] = "i2c " /* That's the prefix for the crc32 command below. */ #endif "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n" -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || \ - defined(CONFIG_I2C_MULTI_BUS) || CONFIG_IS_ENABLED(DM_I2C) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || CONFIG_IS_ENABLED(DM_I2C) "i2c dev [dev] - show or set current I2C bus\n" -#endif /* CONFIG_I2C_MULTI_BUS */ +#endif #if defined(CONFIG_I2C_EDID) "i2c edid chip - print EDID configuration information\n" #endif /* CONFIG_I2C_EDID */ diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 8ee17f0a45..5bc9cd7b29 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -374,45 +374,12 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen, static struct mv_i2c *base_glob; -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; -static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; -static unsigned int current_bus; - -int i2c_set_bus_num(unsigned int bus) -{ - if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) { - printf("Bad bus: %d\n", bus); - return -1; - } - - base_glob = (struct mv_i2c *)i2c_regs[bus]; - current_bus = bus; - - if (!bus_initialized[current_bus]) { - bus_initialized[current_bus] = 1; - } - - return 0; -} - -unsigned int i2c_get_bus_num(void) -{ - return current_bus; -} -#endif - /* API Functions */ void i2c_init(int speed, int slaveaddr) { u32 val; -#ifdef CONFIG_I2C_MULTI_BUS - current_bus = 0; - base_glob = (struct mv_i2c *)i2c_regs[current_bus]; -#else base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG; -#endif if (speed > I2C_SPEED_STANDARD_RATE) val = ICR_FM; diff --git a/include/configs/display5.h b/include/configs/display5.h index 7636d2869a..5cbeb9224c 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -36,9 +36,6 @@ #define CONFIG_MXC_UART_BASE UART5_BASE -/* I2C Configs */ -#define CONFIG_I2C_MULTI_BUS - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 8d5b24d827..ffd394691a 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -149,7 +149,6 @@ * I2C */ -#define CONFIG_I2C_MULTI_BUS #define CFG_SYS_I2C_MAX_HOPS 1 #define CFG_SYS_NUM_I2C_BUSES 3 #define I2C_MUX_PCA_ADDR 0x70 diff --git a/include/configs/novena.h b/include/configs/novena.h index 6e4bdce1c0..79e49c74f8 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -33,9 +33,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -/* I2C */ -#define CONFIG_I2C_MULTI_BUS - /* I2C EEPROM */ /* MMC Configs */ From 308520b8f2b11b3427fe8a02171839992bc85da6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:31 -0500 Subject: [PATCH 198/424] global: Remove unused CONFIG symbols This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini --- README | 11 ----------- arch/arm/include/asm/arch-ls102xa/config.h | 1 - arch/arm/mach-mvebu/include/mach/config.h | 9 --------- arch/powerpc/include/asm/config_mpc85xx.h | 1 - arch/xtensa/include/asm/config.h | 1 - board/Marvell/openrd/openrd.c | 2 +- drivers/net/mvgbe.c | 4 ---- drivers/net/mvgbe.h | 7 ------- drivers/ram/mpc83xx_sdram.c | 7 +------ include/configs/MPC837XERDB.h | 8 +++----- include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 9 ++------- include/configs/SBx81LIFKW.h | 9 --------- include/configs/SBx81LIFXCAT.h | 9 --------- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 4 ---- include/configs/T208xQDS.h | 2 -- include/configs/T208xRDB.h | 2 -- include/configs/T4240RDB.h | 3 --- include/configs/alt.h | 3 --- include/configs/ax25-ae350.h | 3 --- include/configs/beaver.h | 4 ---- include/configs/blanche.h | 4 +--- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 3 --- include/configs/colibri_vf.h | 4 ---- include/configs/dalmore.h | 3 --- include/configs/dns325.h | 7 ------- include/configs/dockstar.h | 6 ------ include/configs/dra7xx_evm.h | 1 - include/configs/dreamplug.h | 6 ------ include/configs/ds109.h | 8 -------- include/configs/eb_cpu5282.h | 8 -------- include/configs/efi-x86_app.h | 2 -- include/configs/embestmx6boards.h | 6 +++--- include/configs/ethernut5.h | 1 - include/configs/exynos5-common.h | 2 -- include/configs/exynos5420-common.h | 2 -- include/configs/exynos7420-common.h | 4 ---- include/configs/goflexhome.h | 6 ------ include/configs/guruplug.h | 8 -------- include/configs/ib62x0.h | 8 -------- include/configs/iconnect.h | 10 ---------- include/configs/jetson-tk1.h | 5 ----- include/configs/k2e_evm.h | 1 - include/configs/k2g_evm.h | 1 - include/configs/k2l_evm.h | 1 - include/configs/kmcent2.h | 1 - include/configs/kontron_sl28.h | 1 - include/configs/lacie_kw.h | 7 ------- include/configs/legoev3.h | 1 - include/configs/ls1028a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls1088a_common.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080a_common.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/malta.h | 2 -- include/configs/mt7621.h | 1 - include/configs/mt7629.h | 5 +---- include/configs/mxs.h | 5 ----- include/configs/nas220.h | 12 ------------ include/configs/nsa310s.h | 4 ---- include/configs/nyan-big.h | 3 --- include/configs/openrd.h | 22 ---------------------- include/configs/origen.h | 6 ------ include/configs/p2371-0000.h | 3 --- include/configs/p2371-2180.h | 3 --- include/configs/p2571.h | 3 --- include/configs/p3450-0000.h | 3 --- include/configs/pm9263.h | 5 ----- include/configs/pogo_e02.h | 6 ------ include/configs/pogo_v4.h | 6 ------ include/configs/porter.h | 3 --- include/configs/qemu-ppce500.h | 1 - include/configs/rcar-gen3-common.h | 1 - include/configs/rk3399_common.h | 10 ---------- include/configs/sheevaplug.h | 6 ------ include/configs/silk.h | 3 --- include/configs/smdk5420.h | 2 -- include/configs/smdkv310.h | 3 --- include/configs/socfpga_sr1500.h | 6 ------ include/configs/socrates.h | 4 ---- include/configs/stout.h | 3 --- include/configs/synquacer.h | 1 - include/configs/tec-ng.h | 6 ------ include/configs/venice2.h | 3 --- include/configs/vinco.h | 3 --- include/configs/x86-common.h | 16 ---------------- include/configs/xpress.h | 7 ++----- 99 files changed, 14 insertions(+), 391 deletions(-) diff --git a/README b/README index 1209633176..9e2627863c 100644 --- a/README +++ b/README @@ -373,12 +373,6 @@ The following options need to be configured: such as ARM architectural timer initialization. - Linux Kernel Interface: - CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only] - - When transferring memsize parameter to Linux, some versions - expect it to be in bytes, others in MB. - Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes. - CONFIG_OF_LIBFDT New kernel versions are expecting firmware settings to be @@ -585,11 +579,6 @@ The following options need to be configured: Support for generic parallel port TPM devices. Only one device per system is supported at this time. - CONFIG_TPM_TIS_BASE_ADDRESS - Base address where the generic TPM device is mapped - to. Contemporary x86 systems usually map it at - 0xfed40000. - CONFIG_TPM Define this to enable the TPM support library which provides functional interfaces to some TPM commands. diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 14f86df5ed..4a4d642441 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -70,7 +70,6 @@ /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 2e06f2bdae..96a08104ff 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -30,13 +30,4 @@ /* Needed for SPI NOR booting in SPL */ #define CONFIG_DM_SEQ_ALIAS 1 -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI -#endif -#endif - #endif /* __MVEBU_CONFIG_H */ diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index edaf8baaae..e805991060 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -133,7 +133,6 @@ #define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 -#define CONFIG_NUM_DSP_CPUS 6 #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CFG_SYS_NUM_FM1_DTSEC 6 #define CFG_SYS_NUM_FM1_10GEC 2 diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h index a1096ab196..21b334b938 100644 --- a/arch/xtensa/include/asm/config.h +++ b/arch/xtensa/include/asm/config.h @@ -14,7 +14,6 @@ * restricting used physical memory to the first 128MB. */ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (128 << 20) #endif diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index f44ac3315e..581e2e084d 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -140,7 +140,7 @@ void mv_phy_init(char *name) /* reset the phy */ miiphy_reset(name, devadr); - printf(PHY_NO" Initialized on %s\n", name); + printf("Initialized on %s\n", name); } void reset_phy(void) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 58363fce05..3587ca2124 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -37,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_MVGBE_PORTS -# define CONFIG_MVGBE_PORTS {0, 0} -#endif - #define MV_PHY_ADR_REQUEST 0xee #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) #define MVGBE_PGADR_REG 22 diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h index e3f5ac0639..6514ab67ba 100644 --- a/drivers/net/mvgbe.h +++ b/drivers/net/mvgbe.h @@ -11,13 +11,6 @@ #ifndef __MVGBE_H__ #define __MVGBE_H__ -/* PHY_BASE_ADR is board specific and can be configured */ -#if defined (CONFIG_PHY_BASE_ADR) -#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR -#else -#define PHY_BASE_ADR 0x08 /* default phy base addr */ -#endif - /* Constants */ #define INT_CAUSE_UNMASK_ALL 0x0007ffff #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff diff --git a/drivers/ram/mpc83xx_sdram.c b/drivers/ram/mpc83xx_sdram.c index a53ff93a6b..11676d4fae 100644 --- a/drivers/ram/mpc83xx_sdram.c +++ b/drivers/ram/mpc83xx_sdram.c @@ -118,12 +118,7 @@ int dram_init(void) phys_size_t get_effective_memsize(void) { - if (!IS_ENABLED(CONFIG_VERY_BIG_RAM)) - return gd->ram_size; - - /* Limit stack to what we can reasonable map */ - return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size); + return gd->ram_size; } /** diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 7dff3cc691..7b932eb389 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -195,12 +195,10 @@ * Environment Configuration */ -#define CONFIG_NETDEV "eth1" - -#define CONFIG_FDTFILE "mpc8379_rdb.dtb" +#define FDTFILE "mpc8379_rdb.dtb" #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ + "netdev=eth1\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ "tftpflash=tftp $loadaddr $uboot;" \ "protect off " __stringify(CONFIG_TEXT_BASE) \ @@ -214,7 +212,7 @@ "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \ " $filesize\0" \ "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ + "fdtfile=" FDTFILE "\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ "console=ttyS0\0" \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index d83563d618..02d49c3d34 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -24,7 +24,6 @@ #ifdef CONFIG_SPIFLASH #ifdef CONFIG_NXP_ESBC -#define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #else #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0f0cdb3a68..1a157a7da0 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,7 +12,6 @@ #define __CONFIG_H #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif @@ -46,10 +45,9 @@ /* * Config the L3 Cache as L3 SRAM */ -#define CFG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE #ifdef CONFIG_PHYS_64BIT -#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ - CONFIG_RAMBOOT_TEXT_BASE) +#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE) #else #define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR #endif @@ -62,7 +60,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE @@ -88,7 +85,6 @@ #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FSL_CPLD #define CPLD_BASE 0xffdf0000 /* CPLD registers */ #ifdef CONFIG_PHYS_64BIT #define CPLD_BASE_PHYS 0xfffdf0000ull @@ -131,7 +127,6 @@ #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000} /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index d5c9c05767..19ae639947 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -36,14 +36,5 @@ /* size in bytes reserved for initial data */ #include -/* There is no PHY directly connected so don't ask it for link status */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ -#define CONFIG_PHY_BASE_ADR 0x01 -#endif /* CONFIG_CMD_NET */ #endif /* _CONFIG_SBX81LIFKW_H */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 23d37394e0..bdbf9d4758 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -41,14 +41,5 @@ /* size in bytes reserved for initial data */ #include -/* There is no PHY directly connected so don't ask it for link status */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ -#define CONFIG_PHY_BASE_ADR 0x01 -#endif /* CONFIG_CMD_NET */ #endif /* _CONFIG_SBX81LIFXCAT_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e815d9f81a..4b443c7504 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -112,7 +112,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #if defined(CONFIG_TARGET_T1024RDB) @@ -269,7 +268,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 6fe0bd6828..dfad76e16f 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -86,7 +86,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE @@ -247,7 +246,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 @@ -285,8 +283,6 @@ */ #define CFG_SYS_I2C_RTC_ADDR 0x68 -/*DVI encoder*/ -#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 #endif /* diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 79b3d7af4e..24c1daf998 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -78,7 +78,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ @@ -245,7 +244,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 2a32fe37aa..c825e7fa0c 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -78,7 +78,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE #define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ @@ -210,7 +209,6 @@ #endif /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index d8c4de5b3d..95735f3fcb 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -16,7 +16,6 @@ #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SDCARD -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #else #define RESET_VECTOR_OFFSET 0x27FFC @@ -60,7 +59,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE @@ -71,7 +69,6 @@ #define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE) /* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM #define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/alt.h b/include/configs/alt.h index fe303fda78..f277400169 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -20,9 +20,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index 03e04e6e68..d70f038230 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -49,9 +49,6 @@ */ #define CFG_SYS_FLASH_BANKS_SIZES {0x4000000} -/* max number of sectors on one chip */ -#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) - /* environments */ /* SPI FLASH */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 6b5f650811..7078c2745c 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -20,10 +20,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index fe09997e17..d4e0f677e6 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -22,9 +22,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* FLASH */ -#if !defined(CONFIG_MTD_NOR_FLASH) -#define CONFIG_SH_QSPI_BASE 0xE6B10000 -#else +#if defined(CONFIG_MTD_NOR_FLASH) #define CFG_SYS_FLASH_BASE 0x00000000 #define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ #define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) } diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 35c5a4f122..5cca1e1834 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -24,10 +24,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 55e2d744c4..e3519ed751 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -22,9 +22,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 8a790400b4..e8918df69e 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -14,10 +14,6 @@ #include #include -/* NAND support */ - -#define CONFIG_FDTADDR 0x84000000 - #define MEM_LAYOUT_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "fdt_addr_r=0x82000000\0" \ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 24cf554649..82b2efdfe8 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 015bc78648..1bfb741346 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -16,13 +16,6 @@ /* Remove or override few declarations from mv-common.h */ -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#endif - /* * Enable GPI0 support */ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index 33ae7d654b..a6c1e9c6d0 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -28,10 +28,4 @@ "initrd=/boot/uInitrd\0" \ "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_DOCKSTAR_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index b8f518612e..f8afcc7826 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,7 +13,6 @@ #include -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x80000000 #ifndef CONFIG_QSPI_BOOT diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index fbd83d629c..98322a54f6 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -24,10 +24,4 @@ "x_bootargs=console=ttyS0,115200\0" \ "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index 8553ea0b95..8e7a86e062 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -35,12 +35,4 @@ "ipaddr=192.168.1.5\0" \ "usb0Mode=host\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - #endif /* _CONFIG_DS109_H */ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 717f49ca29..029f13dad3 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -144,13 +144,5 @@ #define CFG_SYS_DDRUA 0x05 #define CFG_SYS_PJPAR 0xFF -/*----------------------------------------------------------------------- - * I2C - */ - -#ifdef CONFIG_CMD_DATE -#define CONFIG_I2C_RTC_ADDR 0x68 -#endif - #endif /* _CONFIG_M5282EVB_H */ /*---------------------------------------------------------------------*/ diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h index 6061a6db0a..17a7851402 100644 --- a/include/configs/efi-x86_app.h +++ b/include/configs/efi-x86_app.h @@ -8,8 +8,6 @@ #include -#undef CONFIG_TPM_TIS_BASE_ADDRESS - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=vidconsole\0" \ "stderr=vidconsole\0" diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 22e0fa5aab..1742b1192f 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -35,11 +35,11 @@ #if defined(CONFIG_ENV_IS_IN_MMC) /* RiOTboard */ -#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" +#define FDTFILE "imx6dl-riotboard.dtb" #define CFG_SYS_FSL_USDHC_NUM 3 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ -#define CONFIG_FDTFILE "imx6q-marsboard.dtb" +#define FDTFILE "imx6q-marsboard.dtb" #define CFG_SYS_FSL_USDHC_NUM 2 #endif @@ -79,7 +79,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - "fdtfile=" CONFIG_FDTFILE "\0" \ + "fdtfile=" FDTFILE "\0" \ "finduuid=part uuid mmc 0:1 uuid\0" \ BOOTENV diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 52eb0be676..3fd58d6bd4 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -49,7 +49,6 @@ /* Ethernet */ #define CONFIG_PHY_ID 0 -#define CONFIG_MACB_SEARCH_PHY /* MMC */ #ifdef CONFIG_CMD_MMC diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 9b5c329bda..8e277ce7ff 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -27,8 +27,6 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_RD_LVL - #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE #define PHYS_SDRAM_2 (CFG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 7a9307ccc3..934a4ef9d1 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_VAR_SIZE_SPL - #define CONFIG_IRAM_TOP 0x02074000 #define CONFIG_PHY_IRAM_BASE 0x02020000 diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index cff910c1bd..e22dd036cc 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -15,10 +15,6 @@ /* select serial console configuration */ -/* IRAM Layout */ -#define CONFIG_IRAM_BASE 0x02100000 -#define CONFIG_IRAM_SIZE 0x58000 -#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) #define CPU_RELEASE_ADDR secondary_boot_addr /* select serial console configuration */ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 66eed9e14f..1c86dcb1f6 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -36,10 +36,4 @@ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index 4954c5ca08..d196c4eda5 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -30,12 +30,4 @@ "fdt=/boot/guruplug-server-plus.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - #endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 05192218d2..76fc4ac8b6 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -24,14 +24,6 @@ "fdt=/boot/ib62x0.dtb\0" \ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" -/* - * Ethernet driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - /* * SATA driver configuration */ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index f2e3608d3a..6d2104b3a1 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -16,14 +16,4 @@ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" -/* - * Ethernet driver configuration - * - * This board has PCIe Wifi card, so allow Ethernet to be disabled - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 11 -#endif /* CONFIG_CMD_NET */ - #endif /* _CONFIG_ICONNECT_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index b846889541..ea4964b13d 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -18,11 +18,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index bbc58be511..174a91c83e 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -39,6 +39,5 @@ /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index bb91751d5d..dc06d5943e 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -53,7 +53,6 @@ /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ #define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index a18158a7eb..5d629452ba 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -39,6 +39,5 @@ /* Network */ #define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE #endif /* __CONFIG_K2L_EVM_H */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 532370e918..80bff4b893 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -149,7 +149,6 @@ /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 9c3174d0e0..f7bb97aa0e 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -18,7 +18,6 @@ /* DDR */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 828f910963..7a66df548a 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -14,13 +14,6 @@ * Enable platform initialisation via misc_init_r() function */ -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#endif - /* * Enable GPI0 support */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index abe470fe89..794c1fcbed 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -48,7 +48,6 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_SETUP_INITRD_TAG #define CONFIG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ "fdtfile=da850-lego-ev3.dtb\0" \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index b190bfe9c8..2ccb20192d 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -12,7 +12,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e54e903a8a..d0380b3373 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -31,7 +31,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index dab57382ed..1dca7f0aa6 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -107,7 +107,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 12c4853ea9..043904197f 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -82,7 +82,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_SIZE (1024 << 10) diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 4ed5481c3e..250891e9e3 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -31,7 +31,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 1759d25f3a..5e03a962d1 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -45,7 +45,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE /* IFC Timing Params */ #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index e9b8ad0c0b..c4e5f4928d 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -123,7 +123,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #endif #ifdef CONFIG_NAND_BOOT diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index f3904e7b3f..ad766b034b 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -50,7 +50,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE /* * CPLD diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 57429d4bbe..bcba8d81c0 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -29,7 +29,6 @@ /* Link Definitions */ #define CFG_SYS_FSL_QSPI_BASE 0x20000000 -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index dc9cded49f..49ad146926 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -97,7 +97,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index e2444cd8eb..9033f6e937 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -81,7 +81,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CFG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_BRDCFG4_OFFSET 0x54 diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e82456fd81..bd78bdb793 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -16,7 +16,6 @@ /* Link Definitions */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4e6d40afbf..7d3e8912c3 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -98,7 +98,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 8f36958f71..4573906115 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -95,7 +95,6 @@ #define CFG_SYS_NAND_FTIM3 0x0 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } -#define CONFIG_MTD_NAND_VERIFY_WRITE #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index a469c83fa4..3347920f03 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -13,7 +13,6 @@ #define CFG_SYS_FLASH_BASE 0x20000000 /* DDR */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL diff --git a/include/configs/malta.h b/include/configs/malta.h index 65f4b05649..8ba04b4e6c 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -11,8 +11,6 @@ */ #define CONFIG_MALTA -#define CONFIG_MEMSIZE_IN_BYTES - /* * CPU Configuration */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 7c8c67f446..b6e680bcc7 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -10,7 +10,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED 0x1c000000 #define CFG_SYS_INIT_SP_OFFSET 0x800000 diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 99b09ad41e..f6ab486fa2 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -15,10 +15,7 @@ /* Environment */ -/* Defines for SPL */ - -#define CONFIG_SPI_ADDR 0x30000000 -#define CFG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) +#define CFG_SYS_UBOOT_BASE (0x30000000 + CONFIG_SPL_PAD_TO) /* SPL -> Uboot */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 30f27e7f0c..32e0e06617 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -86,9 +86,4 @@ #define CFG_SYS_NAND_BASE 0x60000000 #endif -/* SPI */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SPI_HALF_DUPLEX -#endif - #endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 1b7eb34334..85691ca94f 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -39,16 +39,4 @@ "bootargs=console=ttyS0,115200\0" \ "autostart=no\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - -/* - * EFI partition - */ - #endif /* _CONFIG_NAS220_H */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index 62f0701180..e2ad77072c 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -46,8 +46,4 @@ #endif /* CONFIG_SPL_BUILD */ -/* Ethernet driver configuration */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 1 - #endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index baa452156e..21002f99dc 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -18,9 +18,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 006f06e6af..2cec20ca42 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -33,26 +33,4 @@ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -# else -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -# endif -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_PHY_BASE_ADR 0x0 -# define PHY_NO "88E1121" -# else -# define CONFIG_PHY_BASE_ADR 0x8 -# define PHY_NO "88E1116" -# endif -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ - #endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h index 6633d541a3..a608df44e8 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -38,10 +38,4 @@ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" -/* MIU (Memory Interleaving Unit) */ -#define CONFIG_MIU_2BIT_21_7_INTERLEAVED - -#define RESERVE_BLOCK_SIZE (512) -#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ - #endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index ecd0405d29..653b4c583a 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 7f942888e7..2913d5304b 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 50cddb4a4a..e78e3c4d6b 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -19,9 +19,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* _P2571_H */ diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index ec1a8634e7..bab02dc2d6 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -23,9 +23,6 @@ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -/* Environment at end of QSPI, in the VER partition */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #define BOARD_EXTRA_ENV_SETTINGS \ "preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \ "load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 9fd897958a..fa08744b6f 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -159,11 +159,6 @@ /* PSRAM */ #define PHYS_PSRAM 0x70000000 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ -/* Slave EBI1, PSRAM connected */ -#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ - AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ - AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ - AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index 085732214e..fc9f113dee 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -23,10 +23,4 @@ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_POGO_E02_H */ diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index b5ce2dd13d..239d33d8e9 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -69,10 +69,4 @@ BOOTENV #endif /* CONFIG_SPL_BUILD */ -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_POGO_V4_H */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 88fa65e0ff..e0f77f358b 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -21,9 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index d056189958..20be4af462 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -29,7 +29,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* * DDR Setup */ -#define CONFIG_VERY_BIG_RAM #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index e9cbd25382..86012adfb3 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -28,7 +28,6 @@ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) /* ENV setting */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index e459581715..a721f27ec0 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -10,16 +10,6 @@ #define CONFIG_IRAM_BASE 0xff8c0000 -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) -#else -/* BSS setup */ -#endif - -/* MMC/SD IP block */ -#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 - -/* RAW SD card / eMMC locations. */ - /* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf8000000 diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 19701ccce2..d7923967a7 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -21,10 +21,4 @@ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" -/* - * Ethernet Driver configuration - */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - #endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 58613effaf..6d605edf78 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -21,9 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 0392530c0a..0cb70762d9 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -12,8 +12,6 @@ #include #include -#define CONFIG_SMDK5420 /* which is in a SMDK5420 */ - #define CFG_SYS_SDRAM_BASE 0x20000000 /* DRAM Memory Banks */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 601c16ea45..38de1fa984 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -34,9 +34,6 @@ /* FLASH and environment organization */ -#define RESERVE_BLOCK_SIZE (512) -#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_ENV_SROM_BANK 1 diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index 432144cb40..caff0cf252 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -11,15 +11,9 @@ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ /* Ethernet on SoC (EMAC) */ -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII /* The PHY is autodetected, so no MII PHY address is needed here */ #define PHY_ANEG_TIMEOUT 8000 -/* Enable SPI NOR flash reset, needed for SPI booting */ -#define CONFIG_SPI_N25Q256A_RESET - -/* Environment setting for SPI flash */ - /* The rest of the configuration is shared */ #include diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 2a07671602..11d8402233 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -16,9 +16,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ -#define CONFIG_SOCRATES 1 - /* * Only possible on E500 Version 2 or newer cores. */ @@ -55,7 +52,6 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM /* I2C addresses of SPD EEPROMs */ #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ diff --git a/include/configs/stout.h b/include/configs/stout.h index f49e88cb17..977c0adc5f 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -25,9 +25,6 @@ /* SCIF */ #define CONFIG_SCIF_A -/* SPI */ -#define CONFIG_SPI_FLASH_QUAD - /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 6992689001..a2b6a1f57d 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -14,7 +14,6 @@ #define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ -#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */ #define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE #define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 0987966370..c98322cf08 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -16,12 +16,6 @@ #define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index b2dc04a975..a4eb4bf4aa 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -20,9 +20,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 9f72bdde81..1c1789ac3f 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -39,9 +39,6 @@ /* USB device */ -/* Ethernet Hardware */ -#define CONFIG_MACB_SEARCH_PHY - #ifdef CONFIG_SPI_BOOT /* bootstrap + u-boot + env + linux in serial flash */ /* Use our own mapping for the VInCo platform */ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 9bf2462010..d71108dd31 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -10,22 +10,6 @@ #ifndef __CONFIG_X86_COMMON_H #define __CONFIG_X86_COMMON_H -/* - * High Level Configuration Options - * (easy to change) - */ - -/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 - -/*----------------------------------------------------------------------- - * Serial Configuration - */ - -/* - * Miscellaneous configurable options - */ - /*----------------------------------------------------------------------- * CPU Features */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 3e604894ad..9f1f2d90db 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -34,9 +34,6 @@ #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_UBOOT_SECTOR_START 0x2 -#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ @@ -75,8 +72,8 @@ "bootz; " \ "fi;\0" \ "uboot=ccv/u-boot.imx\0" \ - "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ + "uboot_start=0x2\0" \ + "uboot_size=0x3fe\0" \ "update_uboot=if tftp ${uboot}; then " \ "if itest ${filesize} > 0; then " \ "mmc dev 0 1;" \ From acdf89ec060931ae4c87780ab0e65a6783ccd94b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:32 -0500 Subject: [PATCH 199/424] Convert CONFIG_KSNET_NETCP_V1_0 et al to Kconfig This converts the following to Kconfig: CONFIG_KSNET_NETCP_V1_0 CONFIG_KSNET_NETCP_V1_5 Signed-off-by: Tom Rini --- configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + drivers/net/ti/Kconfig | 13 +++++++++++++ include/configs/k2e_evm.h | 1 - include/configs/k2g_evm.h | 1 - include/configs/k2hk_evm.h | 1 - include/configs/k2l_evm.h | 1 - 7 files changed, 15 insertions(+), 4 deletions(-) diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index b0069fd60b..2bcf2265c7 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -87,6 +87,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_KSNET_NETCP_V1_0=y CONFIG_PHY=y CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index 9ca26ae61f..94ab680343 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -62,6 +62,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_MARVELL=y CONFIG_MII=y CONFIG_DRIVER_TI_KEYSTONE_NET=y +CONFIG_KSNET_NETCP_V1_0=y CONFIG_PHY=y CONFIG_NOP_PHY=y CONFIG_KEYSTONE_USB_PHY=y diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 59c96d862d..e13dbc9401 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -25,6 +25,19 @@ config DRIVER_TI_KEYSTONE_NET help This driver supports the TI Keystone 2 Ethernet subsystem +choice + prompt "TI Keystone 2 Ethernet NETCP IP revision" + depends on DRIVER_TI_KEYSTONE_NET + default KSNET_NETCP_V1_5 + +config KSNET_NETCP_V1_0 + bool "NETCP version 1.0" + +config KSNET_NETCP_V1_5 + bool "NETCP version 1.5" + +endchoice + config TI_AM65_CPSW_NUSS bool "TI K3 AM65x MCU CPSW Nuss Ethernet controller driver" depends on ARCH_K3 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 174a91c83e..1283f450b3 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -37,7 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 9 #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index dc06d5943e..fd3708ba81 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -51,7 +51,6 @@ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" /* Network */ -#define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 2 #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 68cbe98b55..36e3c59d1c 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -37,7 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index 5d629452ba..cb7b036781 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -37,7 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_NETCP_V1_5 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2L_EVM_H */ From 960379d4501fcb64ca20810c4fc4fe74806ede7b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:33 -0500 Subject: [PATCH 200/424] Convert CONFIG_L2_CACHE to Kconfig This converts the following to Kconfig: CONFIG_L2_CACHE Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 3 +++ configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/socrates_defconfig | 1 + include/configs/MPC8548CDS.h | 5 ----- include/configs/P1010RDB.h | 5 ----- include/configs/p1_p2_rdb_pc.h | 5 ----- include/configs/socrates.h | 5 ----- 45 files changed, 43 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 721dafc5ab..36519613a2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1297,6 +1297,9 @@ config SYS_NUM_TLBCAMS Number of TLB CAM entries for Book-E chips. 64 for E500MC, 16 for other E500 SoCs. +config L2_CACHE + bool "Enable L2 cache support" + if HETROGENOUS_CLUSTERS config SYS_MAPLE diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 241cb80fde..05034ce2e4 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -13,6 +13,7 @@ CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_USE_UBOOTPATH=y CONFIG_UBOOTPATH="8548cds/u-boot.bin" diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 5af056bd4f..965c37e45e 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -13,6 +13,7 @@ CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_USE_UBOOTPATH=y CONFIG_UBOOTPATH="8548cds/u-boot.bin" diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 34d1938129..004175c804 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -13,6 +13,7 @@ CONFIG_SRIO1=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 3fb993e201..c12948ae7c 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index dc6dd717df..6a320713eb 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index bc29526f63..e3b786d4ef 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 5c42d5ee36..e6ce59e297 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index b6e68d2788..99b94a061d 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index fe24faa175..071123362f 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 110a9b4ad3..9f2afcdadc 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index fcd60f7a4e..7c64fdcf6f 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 76919c3881..87953b8f19 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index b297258694..bf7078015e 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index df80488cff..4dbf8695e4 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index d27ea17a0b..f5bcffbd49 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 88de4f9b92..82f29bed54 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 2e86aec595..985243cebd 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index d5bbd6dca5..3dfb509c8a 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 66efe739e9..f3d399f84f 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_SPI=y CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 0f082f6e6e..de04556b22 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 88e10af29a..2d201bf55e 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 729e93eae2..a6b7a4abf5 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 2860c286d7..58f2475571 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 0958a0a94b..cf47bd49c7 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 81bb26cb8f..3a86a9ef52 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 481009f307..9fe2b1d88f 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 49207eb65a..17bde92263 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 7e22b4e34c..2f768c0670 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 62b25f0398..6cb3be08dc 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index f5864dea4d..0eb2b3ab74 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index ca04007288..b0ccaa1cfd 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 2420217b89..c53c4c6c7c 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 22b0023ec6..0ac74287fd 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 8c95203a4a..9da9ef0c69 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index b87c965d50..bb5df66c74 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 1d33cf6750..4758e0e371 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 8d44e5b425..1584a8a7c3 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 9155768c15..6acb0bcb12 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 4f3be9eb24..2afef4a5eb 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_USE_UBOOTPATH=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 4cc50d3558..46be662037 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -10,6 +10,7 @@ CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y +CONFIG_L2_CACHE=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MONITOR_LEN=393216 CONFIG_FIT=y diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1f1eacdb69..3d0c2192ee 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -17,11 +17,6 @@ #include #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ - /* * Only possible on E500 Version 2 or newer cores. */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 02d49c3d34..c398ece784 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -95,11 +95,6 @@ #endif #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ - /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index ee25990b03..c05904a813 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -109,11 +109,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE - #define CFG_SYS_CCSRBAR 0xffe00000 #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 11d8402233..0547ed0256 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -34,11 +34,6 @@ * in the README.mpc85xxads. */ -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ - #define CFG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ #undef CFG_SYS_DRAM_TEST /* memory test, takes time */ From 2cc61a631bb8ae1acfadac9840abaa803091b7ac Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:34 -0500 Subject: [PATCH 201/424] malta: Rename CONFIG_MALTA to CONFIG_TARGET_MALTA Fixup this last remnant of CONFIG_MALTA. Cc: Paul Burton Signed-off-by: Tom Rini --- drivers/rtc/mc146818.c | 2 +- include/configs/malta.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 122691b978..03ce081d57 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_X86) || defined(CONFIG_MALTA) +#if defined(CONFIG_X86) || defined(CONFIG_TARGET_MALTA) #include #define in8(p) inb(p) #define out8(p, v) outb(v, p) diff --git a/include/configs/malta.h b/include/configs/malta.h index 8ba04b4e6c..c17a4a4a8e 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -9,7 +9,6 @@ /* * System configuration */ -#define CONFIG_MALTA /* * CPU Configuration From 829e9d223657f5779668bb7a46e902a85e09b664 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:35 -0500 Subject: [PATCH 202/424] ddr: fsl: Remove CONFIG_MEM_INIT_VALUE The way all of the memory init code here works is that we pass 0xDEADBEEF around for the initial value (as it's a well known 'poison' value and so easily recognized in debuggers, etc). The only point of this CONFIG symbol was to pass in a different value for that purpose. Drop this symbol and cleanup the code slightly. Signed-off-by: Tom Rini --- arch/powerpc/include/asm/fsl_dma.h | 2 +- drivers/ddr/fsl/ctrl_regs.c | 17 ++--------------- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 2 +- drivers/dma/fsl_dma.c | 4 ++-- include/configs/MPC8548CDS.h | 2 -- include/configs/P1010RDB.h | 2 -- include/configs/T102xRDB.h | 3 --- include/configs/T104xRDB.h | 3 --- include/configs/T208xQDS.h | 7 ------- include/configs/T208xRDB.h | 7 ------- include/configs/T4240RDB.h | 7 ------- include/configs/kontron_sl28.h | 3 --- include/configs/ls1021aqds.h | 4 ---- include/configs/ls1043aqds.h | 4 ---- include/configs/ls1043ardb.h | 6 ------ include/configs/ls1046aqds.h | 4 ---- include/configs/ls1046ardb.h | 2 -- include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/socrates.h | 3 --- 23 files changed, 6 insertions(+), 81 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_dma.h b/arch/powerpc/include/asm/fsl_dma.h index 727f4a7e92..1459db74be 100644 --- a/arch/powerpc/include/asm/fsl_dma.h +++ b/arch/powerpc/include/asm/fsl_dma.h @@ -117,7 +117,7 @@ typedef struct fsl_dma { void dma_init(void); int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n); #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) -void dma_meminit(uint val, uint size); +void dma_meminit(uint size); #endif #endif diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index df7ec48465..759921bc58 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -938,7 +938,7 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ d_init = popts->ecc_init_using_memctl; - ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; + ddr->ddr_data_init = 0xDEADBEEF; debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); #else /* Memory will be initialized via DMA, or not at all. */ @@ -1842,19 +1842,6 @@ static void set_ddr_sdram_mode(const unsigned int ctrl_num, } #endif -/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ -static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_value; /* Initialization value */ - -#ifdef CONFIG_MEM_INIT_VALUE - init_value = CONFIG_MEM_INIT_VALUE; -#else - init_value = 0xDEADBEEF; -#endif - ddr->ddr_data_init = init_value; -} - /* * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) * The old controller on the 8540/60 doesn't have this register. @@ -2537,7 +2524,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm); set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); - set_ddr_data_init(ddr); + ddr->ddr_data_init = 0xDEADBEEF; set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); set_ddr_init_ext_addr(ddr); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index 0f1e99eeb0..16186bdbae 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -73,7 +73,7 @@ ddr_enable_ecc(unsigned int dram_size) struct ccsr_ddr __iomem *ddr = (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR); - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); + dma_meminit(dram_size); /* * Enable errors for ECC. diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index cd78e45d88..700df2236b 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -133,7 +133,7 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { */ #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))) -void dma_meminit(uint val, uint size) +void dma_meminit(uint size) { uint *p = 0; uint i = 0; @@ -142,7 +142,7 @@ void dma_meminit(uint val, uint size) if (((uint)p & 0x1f) == 0) ppcDcbz((ulong)p); - *p = (uint)CONFIG_MEM_INIT_VALUE; + *p = (uint)0xDEADBEEF; if (((uint)p & 0x1c) == 0x1c) ppcDcbf((ulong)p); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 3d0c2192ee..1e3ba6de6e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -26,8 +26,6 @@ /* DDR Setup */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c398ece784..2267a7a9c8 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -98,8 +98,6 @@ /* DDR Setup */ #define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #ifndef __ASSEMBLY__ extern unsigned long get_sdram_size(void); #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4b443c7504..4794c5a84d 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -94,9 +94,6 @@ * These can be toggled for performance analysis, otherwise use default. */ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index dfad76e16f..5bdc2105f5 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -64,9 +64,6 @@ * These can be toggled for performance analysis, otherwise use default. */ #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif /* * Config the L3 Cache as L3 SRAM diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 24c1daf998..4b6bdaa344 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -59,13 +59,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index c825e7fa0c..fab40f792a 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -59,13 +59,6 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 95735f3fcb..41565f284c 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -40,13 +40,6 @@ #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * Config the L3 Cache as L3 SRAM */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index f7bb97aa0e..a073a06c82 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -15,9 +15,6 @@ #undef CFG_SYS_MEM_RESERVE_SECURE #endif -/* DDR */ -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e49588489c..fead9edecc 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -22,10 +22,6 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * IFC Definitions */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 1dca7f0aa6..7ccbb20bf2 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -12,10 +12,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - #ifdef CONFIG_SYS_DPAA_FMAN #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 043904197f..c8a6f0146a 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -9,12 +9,6 @@ #include "ls1043a_common.h" -/* Physical Memory Map */ - -#ifndef CONFIG_SPL -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - /* * NOR Flash Definitions */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index c4e5f4928d..4b4bd7cbe4 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -12,10 +12,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#ifdef CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - #ifdef CONFIG_SYS_DPAA_FMAN #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index ad766b034b..0e42a51fc5 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -13,8 +13,6 @@ #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - #if defined(CONFIG_QSPI_BOOT) #define CFG_SYS_UBOOT_BASE 0x40100000 #endif diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 49ad146926..3391540c6e 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -14,7 +14,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 9033f6e937..1ddf0687f4 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -15,7 +15,6 @@ #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 7d3e8912c3..4a52fcdfdd 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -16,7 +16,6 @@ #define CFG_SYS_I2C_FPGA_ADDR 0x66 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS3 0x53 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 4573906115..b8ab501c98 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -21,7 +21,6 @@ #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS3 0x53 diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 3347920f03..c1a98fd3e4 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -18,7 +18,6 @@ #define CFG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CFG_SYS_SDRAM_SIZE 0x200000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS3 0x53 diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 0547ed0256..4c752091fb 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -42,9 +42,6 @@ #define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR /* DDR Setup */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - #define CFG_SYS_DDR_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE From e52fca2236153341c495bff3c5631fcced291ffe Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:36 -0500 Subject: [PATCH 203/424] Convert CONFIG_MONITOR_IS_IN_RAM to Kconfig This converts the following to Kconfig: CONFIG_MONITOR_IS_IN_RAM As part of this, reword some of the documentation slightly to reflect that this is in Kconfig and not a define now. Signed-off-by: Tom Rini --- arch/Kconfig | 4 ++++ board/cobra5272/README | 27 +++++++++------------------ configs/10m50_defconfig | 1 + configs/3c120_defconfig | 1 + doc/arch/m68k.rst | 4 ++-- include/configs/10m50_devboard.h | 1 - include/configs/3c120_devboard.h | 1 - include/configs/M5249EVB.h | 2 -- include/configs/M5272C3.h | 2 -- include/configs/M5282EVB.h | 2 -- include/configs/astro_mcf5373l.h | 25 ------------------------- include/configs/cobra5272.h | 21 --------------------- include/configs/eb_cpu5282.h | 2 -- 13 files changed, 17 insertions(+), 76 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 5ffbdc6a3f..5f2b72f535 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -380,6 +380,10 @@ config SYS_IMMR Address for the Internal Memory-Mapped Registers (IMMR) window used to configure the features of many Freescale / NXP SoCs. +config MONITOR_IS_IN_RAM + bool "U-Boot is loaded in to RAM by a pre-loader" + depends on M68K || NIOS2 + config SKIP_LOWLEVEL_INIT bool "Skip the calls to certain low level initialization functions" depends on ARM || MIPS || RISCV diff --git a/board/cobra5272/README b/board/cobra5272/README index ac62e557a0..11abcfacdb 100644 --- a/board/cobra5272/README +++ b/board/cobra5272/README @@ -77,21 +77,16 @@ in dir ./u-boot-x-x-x/ please first check: - in ./include/configs/cobra5272.h + in ./configs/cobra5272_defconfig - CONFIG_MONITOR_IS_IN_RAM has to be undefined, e. g. as follows: - - #if 0 - #define CONFIG_MONITOR_IS_IN_RAM - /* define if monitor is started from a pre-loader */ - #endif + CONFIG_MONITOR_IS_IN_RAM has to be not present in the file => u-boot as single bootloader starting from flash - in board/cobra5272/config.mk CONFIG_TEXT_BASE should be + in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be - CONFIG_TEXT_BASE = 0xffe00000 + CONFIG_TEXT_BASE=0xffe00000 => linking address for u-boot as single bootloader stored in flash @@ -115,22 +110,18 @@ in dir ./u-boot-x-x-x/ host> make distclean please modify the settings: + in ./configs/cobra5272_defconfig - in ./include/configs/cobra5272.h + CONFIG_MONITOR_IS_IN_RAM now has to be enabled, e. g. as follows: - CONFIG_MONITOR_IS_IN_RAM now has to be defined, e. g. as follows: - - #if 1 - #define CONFIG_MONITOR_IS_IN_RAM - /*define if monitor is started from a pre-loader */ - #endif + CONFIG_MONITOR_IS_IN_RAM=y => u-boot as RAM version, chainloaded by another bootloader or using bdm cable - in board/cobra5272/config.mk CONFIG_TEXT_BASE should be + in configs/cobra5272_defconfig CONFIG_TEXT_BASE should be - CONFIG_TEXT_BASE = 0x00020000 + CONFIG_TEXT_BASE=0x00020000 => target linking address for RAM diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index 28966e0d0a..7dc9d2ed27 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -1,5 +1,6 @@ CONFIG_NIOS2=y CONFIG_SYS_CONFIG_NAME="10m50_devboard" +CONFIG_MONITOR_IS_IN_RAM=y CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index 8c421f099b..46dfaf827a 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -1,5 +1,6 @@ CONFIG_NIOS2=y CONFIG_SYS_CONFIG_NAME="3c120_devboard" +CONFIG_MONITOR_IS_IN_RAM=y CONFIG_SYS_MALLOC_LEN=0x20000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 770327fea2..a9180fd785 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -93,10 +93,10 @@ Configuration to use a pre-loader ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ If U-Boot should be loaded to RAM and started by a pre-loader -CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the +CONFIG_MONITOR_IS_IN_RAM must be enabled. If it is enabled the initial vector table and basic processor initialization will not be compiled in. The start address of U-Boot must be adjusted in -the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile +the boards defconfig file (CONFIG_SYS_MONITOR_BASE) and Makefile (CONFIG_TEXT_BASE) to the load address. ColdFire CPU specific options/settings diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 3a4fbc6eab..b898ec0cc3 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -32,6 +32,5 @@ */ #define CFG_SYS_SDRAM_BASE 0xc8000000 #define CFG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index ab889180ee..e67338c202 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -28,6 +28,5 @@ */ #define CFG_SYS_SDRAM_BASE 0xD0000000 #define CFG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_MONITOR_IS_IN_RAM #endif /* __CONFIG_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 0e38eeb4a3..c71130909f 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -20,8 +20,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ - /* * Clock configuration: enable only one of the following options */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index c58d19c810..6aae584afd 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -19,8 +19,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index e23439fd78..7cfe7a2da3 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -19,8 +19,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 62aa99342a..6aef3bd86f 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -38,16 +38,6 @@ #error No card type defined! #endif -/* - * CONFIG_RAM defines if u-boot is loaded via BDM (or started from - * a different bootloader that has already performed RAM setup) or - * started directly from flash, which is the regular case for production - * boards. - */ -#ifdef CONFIG_RAM -#define CONFIG_MONITOR_IS_IN_RAM -#endif - /* I2C */ /* @@ -69,21 +59,6 @@ #define CFG_SYS_UART_PORT (2) #define CFG_SYS_UART2_ALT3_GPIO -/* - * Configuration for environment - * Environment is located in the last sector of the flash - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#else -/* - * environment in RAM - This is used to use a single PC-based application - * to load an image, load U-Boot, load an environment and then start U-Boot - * to execute the commands from the environment. Feedback is done via setting - * and reading memory locations. - */ -#endif - /* here we put our FPGA configuration... */ /* Define user parameters that have to be customized most likely */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 8c83c3ac06..cd50ffe98d 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -42,27 +42,6 @@ #define CFG_SYS_UART_PORT (0) -/* --- - * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different - * bootloader residing in flash ('chainloading'); if you want to use - * chainloading or want to compile a u-boot binary that can be loaded into - * RAM via BDM set - * "#if 0" to "#if 1" - * You will need a first stage bootloader then, e. g. colilo or a working BDM - * cable (Background Debug Mode) - * - * Setting #if 0: u-boot will start from flash and relocate itself to RAM - * - * Please do not forget to modify the setting of CONFIG_TEXT_BASE - * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) - * - * --- - */ - -#if 0 -#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ -#endif - /* --- * Configuration for environment * Environment is embedded in u-boot in the second sector of the flash diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 029f13dad3..b267b74b15 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -14,8 +14,6 @@ #define CFG_SYS_UART_PORT (0) -#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ - /*----------------------------------------------------------------------* * Options * *----------------------------------------------------------------------*/ From 71894173bb15fffacb166bdc04168a0fcb86cbbf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:37 -0500 Subject: [PATCH 204/424] Convert CONFIG_MXC_NAND_HWECC to Kconfig This converts the following to Kconfig: CONFIG_MXC_NAND_HWECC Signed-off-by: Tom Rini --- configs/m53menlo_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/m53menlo.h | 1 - 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index b70d10433d..70df2b5fd2 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -88,6 +88,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXC=y +CONFIG_MXC_NAND_HWECC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 25b829f11c..1e4e5c9206 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -479,6 +479,10 @@ config SYS_NAND_SIZE depends on NAND_MXC && SPL_NAND_SUPPORT default 268435456 +config MXC_NAND_HWECC + bool "Hardware ECC support in MXC NAND" + depends on NAND_MXC + config NAND_MXS bool "MXS NAND support" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 189b2113f7..d42ad9acb4 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -48,7 +48,6 @@ #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CFG_SYS_NAND_LARGEPAGE -#define CONFIG_MXC_NAND_HWECC #endif /* From 3348c6b6a5cbf71bde837bf80cf962ee6aaeff20 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:38 -0500 Subject: [PATCH 205/424] etamin: Rework CONFIG_NAND_CS_INIT Enable this in the board Kconfig file, but then check for it via CONFIG_IS_ENABLED so that it will only be true in the non-SPL case, as is done today. As part of this we move some defines local to where they are used as it's board specific. Cc: Samuel Egli Signed-off-by: Tom Rini --- board/siemens/common/board.c | 2 +- board/siemens/draco/Kconfig | 2 ++ board/siemens/draco/board.c | 9 ++++++++- include/configs/etamin.h | 12 +----------- 4 files changed, 12 insertions(+), 13 deletions(-) diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 2efede62aa..8fa9197a6d 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -93,7 +93,7 @@ int board_init(void) gpmc_init(); -#ifdef CONFIG_NAND_CS_INIT +#if CONFIG_IS_ENABLED(NAND_CS_INIT) board_nand_cs_init(); #endif diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index a699c7d46f..1eb8a4886f 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -60,4 +60,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "etamin" +config NAND_CS_INIT + def_bool y endif diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index f898bba4b0..8874659013 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -370,7 +370,14 @@ U_BOOT_CMD( #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ -#ifdef CONFIG_NAND_CS_INIT +#if CONFIG_IS_ENABLED(NAND_CS_INIT) +#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 +#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 +#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 +#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e +#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 + /* GPMC definitions for second nand cs1 */ static const u32 gpmc_nand_config[] = { ETAMIN_NAND_GPMC_CONFIG1, diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 6647148c96..811c7cb961 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -127,16 +127,6 @@ "bootm ${kloadaddr} - ${loadaddr}\0" \ COMMON_ENV_NAND_CMDS -#ifndef CONFIG_SPL_BUILD - -#define CONFIG_NAND_CS_INIT -#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 -#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 -#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e -#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 - /* Default env settings */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hostname=etamin\0" \ @@ -147,5 +137,5 @@ CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 -#endif /* CONFIG_SPL_BUILD */ + #endif /* ! __CONFIG_ETAMIN_H */ From 0a69d6afcab9b2fa364cd78aa67340185c5f75a0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:39 -0500 Subject: [PATCH 206/424] Convert CONFIG_OVERWRITE_ETHADDR_ONCE to Kconfig This converts the following to Kconfig: CONFIG_OVERWRITE_ETHADDR_ONCE Signed-off-by: Tom Rini --- README | 7 ------- configs/M5253DEMO_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + env/Kconfig | 9 +++++++++ include/configs/M5253DEMO.h | 2 -- include/configs/M5275EVB.h | 4 ---- include/configs/eb_cpu5282.h | 4 ---- 9 files changed, 13 insertions(+), 17 deletions(-) diff --git a/README b/README index 9e2627863c..3ebee1cb37 100644 --- a/README +++ b/README @@ -1071,13 +1071,6 @@ The following options need to be configured: completely disabled. Anybody can change or delete these parameters. - Alternatively, if you define _both_ an ethaddr in the - default env _and_ CONFIG_OVERWRITE_ETHADDR_ONCE, a default - Ethernet address is installed in the environment, - which can be changed exactly ONCE by the user. [The - serial# is unaffected by this, i. e. it remains - read-only.] - The same can be accomplished in a more flexible way for any variable by configuring the type of access to allow for those variables in the ".flags" variable diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 4de6290b7d..ea079972c9 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5253DEMO" diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 01961e5ae2..d84d9d98c5 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index a831c1c5d2..7304b49387 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -32,6 +32,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_DATE=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 6a673c9181..5ecdda418a 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -30,6 +30,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_DATE=y +CONFIG_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SYS_I2C_LEGACY=y diff --git a/env/Kconfig b/env/Kconfig index c28d9e89f6..7ca992aa1d 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -30,6 +30,15 @@ config ENV_OVERWRITE Use this to permit overriding of certain environmental variables like Ethernet and Serial +config OVERWRITE_ETHADDR_ONCE + bool "Enable overwriting ethaddr environment variables once" + depends on !ENV_OVERWRITE + help + Enable this to allow for the ethaddr environment variables to be + overwritten one time per boot, only. This allows for a default + to be installed in the environment, which can be changed exactly ONCE + by the user. + config ENV_MIN_ENTRIES int "Minimum number of entries in the environment hashtable" default 64 diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 65a7aa0408..bc156df20d 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -20,8 +20,6 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_OVERWRITE_ETHADDR_ONCE - # define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index ff9f853589..41974cff41 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -38,10 +38,6 @@ #define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CFG_SYS_I2C_PINMUX_SET (0x000F) -#ifdef CONFIG_MCFFEC -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index b267b74b15..26e4ade34e 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -42,10 +42,6 @@ * Network * *----------------------------------------------------------------------*/ -#ifdef CONFIG_MCFFEC -#define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif - /*------------------------------------------------------------------------- * Low Level Configuration Settings * (address mappings, register initial values, etc.) From 2b210540b13ab528fbccc0122605ef07a57881af Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:40 -0500 Subject: [PATCH 207/424] Convert CONFIG_PEN_ADDR_BIG_ENDIAN to Kconfig This converts the following to Kconfig: CONFIG_PEN_ADDR_BIG_ENDIAN Signed-off-by: Tom Rini --- arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +++ include/configs/ls1021aiot.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1021atwr.h | 1 - 5 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8381e09e10..6e191e41d5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1599,6 +1599,7 @@ config TARGET_LS1021AQDS select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select SYS_FSL_DDR select FSL_DDR_INTERACTIVE @@ -1617,6 +1618,7 @@ config TARGET_LS1021ATWR select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select LS1_DEEP_SLEEP + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER @@ -1681,6 +1683,7 @@ config TARGET_LS1021AIOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select PEN_ADDR_BIG_ENDIAN select SUPPORT_SPL select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI select GPIO_EXTRA_HEADER diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 7e138e0cc5..a83eb7e8fd 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -51,6 +51,9 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config PEN_ADDR_BIG_ENDIAN + bool + config SYS_CCI400_OFFSET hex "Offset for CCI400 base" depends on SYS_FSL_HAS_CCI400 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 179c5128e3..0e3ff3c5b7 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -68,7 +68,6 @@ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index fead9edecc..76e75335c5 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -242,7 +242,6 @@ * MMC */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b07978a999..281b26fa2b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -152,7 +152,6 @@ /* GPIO */ -#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 From f55281665af3980e5151552fd126fb7293253e96 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:41 -0500 Subject: [PATCH 208/424] arm: ti814x: Remove remaining support code When the ti814x_evm config was removed most, but not all, of the relevant support code was remove. Get rid of what was missed. Fixes: 50b532686849 ("ti814x: Remove platform") Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/clock.h | 2 +- .../include/asm/arch-am33xx/clock_ti81xx.h | 36 +- arch/arm/include/asm/arch-am33xx/hardware.h | 2 - .../include/asm/arch-am33xx/hardware_ti814x.h | 60 --- .../include/asm/arch-am33xx/mmc_host_def.h | 5 +- arch/arm/include/asm/arch-am33xx/mux.h | 2 - arch/arm/include/asm/arch-am33xx/mux_ti814x.h | 311 ------------- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- arch/arm/include/asm/arch-am33xx/spl.h | 16 +- arch/arm/mach-omap2/Kconfig | 8 - arch/arm/mach-omap2/am33xx/Kconfig | 10 - arch/arm/mach-omap2/am33xx/Makefile | 1 - arch/arm/mach-omap2/am33xx/clock_ti814x.c | 410 ------------------ arch/arm/mach-omap2/am33xx/emif4.c | 20 - arch/arm/mach-omap2/boot-common.c | 2 +- drivers/i2c/Kconfig | 2 +- drivers/net/ti/cpsw.c | 4 - include/configs/ti814x_evm.h | 102 ----- 18 files changed, 12 insertions(+), 983 deletions(-) delete mode 100644 arch/arm/include/asm/arch-am33xx/hardware_ti814x.h delete mode 100644 arch/arm/include/asm/arch-am33xx/mux_ti814x.h delete mode 100644 arch/arm/mach-omap2/am33xx/clock_ti814x.c delete mode 100644 include/configs/ti814x_evm.h diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 79e3b8c7d9..ad25b3e8aa 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,7 +13,7 @@ #include #include -#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#if defined(CONFIG_TI816X) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h index f0699229a3..d22d958706 100644 --- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h @@ -44,9 +44,7 @@ struct cm_alwon { unsigned int mmu_clkstctrl; unsigned int mmucfg_clkstctrl; unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkstctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int ocmc1clkstctrl; #endif unsigned int mpuclkstctrl; @@ -67,16 +65,7 @@ struct cm_alwon { unsigned int gpio1clkctrl; unsigned int i2c0clkctrl; unsigned int i2c1clkctrl; -#if defined(CONFIG_TI814X) - unsigned int mcasp345clkctrl; - unsigned int atlclkctrl; - unsigned int mlbclkctrl; - unsigned int pataclkctrl; - unsigned int resv1[1]; - unsigned int uart3clkctrl; - unsigned int uart4clkctrl; - unsigned int uart5clkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv1[1]; unsigned int timer1clkctrl; unsigned int timer2clkctrl; @@ -93,16 +82,12 @@ struct cm_alwon { unsigned int mmudataclkctrl; unsigned int resv2[2]; unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv3[2]; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv3[1]; unsigned int sdioclkctrl; #endif unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI814X) - unsigned int vcpclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int ocmc1clkctrl; #endif unsigned int resv4[2]; @@ -112,9 +97,7 @@ struct cm_alwon { unsigned int ethernet0clkctrl; unsigned int ethernet1clkctrl; unsigned int mpuclkctrl; -#if defined(CONFIG_TI814X) - unsigned int debugssclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int resv6[1]; #endif unsigned int l3clkctrl; @@ -126,14 +109,7 @@ struct cm_alwon { unsigned int tptc1clkctrl; unsigned int tptc2clkctrl; unsigned int tptc3clkctrl; -#if defined(CONFIG_TI814X) - unsigned int resv6[4]; - unsigned int dcan01clkctrl; - unsigned int mmchs0clkctrl; - unsigned int mmchs1clkctrl; - unsigned int mmchs2clkctrl; - unsigned int custefuseclkctrl; -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) unsigned int sr0clkctrl; unsigned int sr1clkctrl; #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 0508b8c912..2d7f9da365 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -16,8 +16,6 @@ #include #elif defined(CONFIG_TI816X) #include -#elif defined(CONFIG_TI814X) -#include #elif defined(CONFIG_AM43XX) #include #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h deleted file mode 100644 index b00d592bc3..0000000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * hardware_ti814x.h - * - * TI814x hardware specific header - * - * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ - */ - -#ifndef __AM33XX_HARDWARE_TI814X_H -#define __AM33XX_HARDWARE_TI814X_H - -/* Module base addresses */ - -/* UART Base Address */ -#define UART0_BASE 0x48020000 - -/* Watchdog Timer */ -#define WDT_BASE 0x481C7000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 -#define CM_PER 0x44E00000 -#define CM_WKUP 0x44E00400 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* PLL Subsystem Base Address */ -#define PLL_SUBSYS_BASE 0x481C5000 - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48140E0C -#define VTP1_CTRL_ADDR 0x48140E10 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x47C0C400 -#define DDR_PHY_DATA_ADDR 0x47C0C4C8 -#define DDR_PHY_CMD_ADDR2 0x47C0C800 -#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 -#define DDR_DATA_REGS_NR 4 - -#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) -#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE - -/* CPSW Config space */ -#define CPSW_MDIO_BASE 0x4A100800 - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -/* OTG */ -#define USB0_OTG_BASE 0x47401000 -#define USB1_OTG_BASE 0x47401800 - -#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 5a2ea8faef..ed15d15c5b 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -24,10 +24,7 @@ #define OMAP_HSMMC1_BASE 0x48060000 #define OMAP_HSMMC2_BASE 0x481D8000 -#if defined(CONFIG_TI814X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 192 /* MHz */ -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) #undef MMC_CLOCK_REFERENCE #define MMC_CLOCK_REFERENCE 48 /* MHz */ #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index b16b184733..7cf973710d 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -20,8 +20,6 @@ #ifdef CONFIG_AM33XX #include -#elif defined(CONFIG_TI814X) -#include #elif defined(CONFIG_TI816X) #include #elif defined(CONFIG_AM43XX) diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h deleted file mode 100644 index a26e5038f7..0000000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * mux_ti814x.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI814X_H_ -#define _MUX_TI814X_H_ - -/* PAD Control Fields */ -#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ -#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ -#define PULLUDEN (0x0 << 16) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -#define MUX_CFG(value, offset) \ -{ \ - int tmp; \ - tmp = __raw_readl(CTRL_BASE + offset); \ - tmp &= PINCNTL_RSV_MSK; \ - __raw_writel(tmp | value, (CTRL_BASE + offset));\ -} - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; -}; - -#endif /* endif _MUX_TI814X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index bc9f0a1146..4c71dbf3ab 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -20,7 +20,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) +#elif defined(CONFIG_TI816X) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define NON_SECURE_SRAM_IMG_END 0x4031B800 diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index f3910c2123..6bd3ca0d07 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,21 +9,7 @@ #define BOOT_DEVICE_NONE 0x00 #define BOOT_DEVICE_MMC2_2 0xFF -#if defined(CONFIG_TI814X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x05 -#define BOOT_DEVICE_NAND_I2C 0x06 -#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x09 -#define BOOT_DEVICE_SPI 0x15 -#define BOOT_DEVICE_UART 0x41 -#define BOOT_DEVICE_USBETH 0x44 -#define BOOT_DEVICE_CPGMAC 0x46 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_TI816X) +#if defined(CONFIG_TI816X) #define BOOT_DEVICE_XIP 0x01 #define BOOT_DEVICE_XIPWAIT 0x02 #define BOOT_DEVICE_NAND 0x03 diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3bf9720522..1db71df272 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -75,14 +75,6 @@ config OMAP54XX imply SPL_SERIAL imply SYS_I2C_OMAP24XX -config TI814X - bool "TI814X SoC" - select SPECIFY_CONSOLE_INDEX - help - Support for AM335x SOC from Texas Instruments. - The AM335x high performance SOC features a Cortex-A8 - ARM core and more. - config TI816X bool "TI816X SoC" select SPECIFY_CONSOLE_INDEX diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index b666e81110..1299aec055 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -8,16 +8,6 @@ config TARGET_TI816X_EVM endif -if TI814X - -config TARGET_TI814X_EVM - bool "Support ti814x_evm" - help - This option specifies support for the TI8148 - EVM development platform. - -endif - if AM33XX config AM33XX_CHILISOM diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 4e4f98ea90..bf94d345da 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -3,7 +3,6 @@ # Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ obj-$(CONFIG_AM33XX) += clock_am33xx.o -obj-$(CONFIG_TI814X) += clock_ti814x.o obj-$(CONFIG_AM43XX) += clock_am43xx.o ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) diff --git a/arch/arm/mach-omap2/am33xx/clock_ti814x.c b/arch/arm/mach-omap2/am33xx/clock_ti814x.c deleted file mode 100644 index 27abaff48f..0000000000 --- a/arch/arm/mach-omap2/am33xx/clock_ti814x.c +++ /dev/null @@ -1,410 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * clock_ti814x.c - * - * Clocks for TI814X based boards - * - * Copyright (C) 2013, Texas Instruments, Incorporated - */ - -#include -#include -#include -#include -#include -#include - -/* PRCM */ -#define PRCM_MOD_EN 0x2 - -/* CLK_SRC */ -#define OSC_SRC0 0 -#define OSC_SRC1 1 - -#define L3_OSC_SRC OSC_SRC0 - -#define OSC_0_FREQ 20 - -#define DCO_HS2_MIN 500 -#define DCO_HS2_MAX 1000 -#define DCO_HS1_MIN 1000 -#define DCO_HS1_MAX 2000 - -#define SELFREQDCO_HS2 0x00000801 -#define SELFREQDCO_HS1 0x00001001 - -#define MPU_N 0x1 -#define MPU_M 0x3C -#define MPU_M2 1 -#define MPU_CLKCTRL 0x1 - -#define L3_N 19 -#define L3_M 880 -#define L3_M2 4 -#define L3_CLKCTRL 0x801 - -#define DDR_N 19 -#define DDR_M 666 -#define DDR_M2 2 -#define DDR_CLKCTRL 0x801 - -/* ADPLLJ register values */ -#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ -#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) -#define ADPLLJ_CLKCTRL_IDLE (1 << 23) -#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) -#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) -#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) -#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) -#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) -#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) -#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) -#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ - ADPLLJ_CLKCTRL_CLKOUTEN | \ - ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ - ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) - -#define ADPLLJ_STATUS_PHASELOCK (1 << 10) -#define ADPLLJ_STATUS_FREQLOCK (1 << 9) -#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ - ADPLLJ_STATUS_FREQLOCK) -#define ADPLLJ_STATUS_BYPASSACK (1 << 8) -#define ADPLLJ_STATUS_BYPASS (1 << 0) -#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ - ADPLLJ_STATUS_BYPASS) - -#define ADPLLJ_TENABLE_ENB (1 << 0) -#define ADPLLJ_TENABLEDIV_ENB (1 << 0) - -#define ADPLLJ_M2NDIV_M2SHIFT 16 - -#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) -#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) -#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) - -struct ad_pll { - unsigned int pwrctrl; - unsigned int clkctrl; - unsigned int tenable; - unsigned int tenablediv; - unsigned int m2ndiv; - unsigned int mn2div; - unsigned int fracdiv; - unsigned int bwctrl; - unsigned int fracctrl; - unsigned int status; - unsigned int m3div; - unsigned int rampctrl; -}; - -#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) - -#define ENET_CLKCTRL_CMPL 0x30000 - -#define SATA_PLL_BASE (CTRL_BASE + 0x0720) - -struct sata_pll { - unsigned int pllcfg0; - unsigned int pllcfg1; - unsigned int pllcfg2; - unsigned int pllcfg3; - unsigned int pllcfg4; - unsigned int pllstatus; - unsigned int rxstatus; - unsigned int txstatus; - unsigned int testcfg; -}; - -#define SEL_IN_FREQ (0x1 << 31) -#define DIGCLRZ (0x1 << 30) -#define ENDIGLDO (0x1 << 4) -#define APLL_CP_CURR (0x1 << 3) -#define ENBGSC_REF (0x1 << 2) -#define ENPLLLDO (0x1 << 1) -#define ENPLL (0x1 << 0) - -#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF) -#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF) -#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO) -#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \ - ENPLLLDO | ENPLL) - -#define PLL_LOCK (0x1 << 0) - -#define ENSATAMODE (0x1 << 31) -#define PLLREFSEL (0x1 << 30) -#define MDIVINT (0x4b << 18) -#define EN_CLKAUX (0x1 << 5) -#define EN_CLK125M (0x1 << 4) -#define EN_CLK100M (0x1 << 3) -#define EN_CLK50M (0x1 << 2) - -#define SATA_PLLCFG1 (ENSATAMODE | \ - PLLREFSEL | \ - MDIVINT | \ - EN_CLKAUX | \ - EN_CLK125M | \ - EN_CLK100M | \ - EN_CLK50M) - -#define DIGLDO_EN_CAPLESSMODE (0x1 << 22) -#define PLLDO_EN_LDO_STABLE (0x1 << 11) -#define PLLDO_EN_BUF_CUR (0x1 << 7) -#define PLLDO_EN_LP (0x1 << 6) -#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1) - -#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \ - PLLDO_EN_LDO_STABLE | \ - PLLDO_EN_BUF_CUR | \ - PLLDO_EN_LP | \ - PLLDO_CTRL_TRIM_1_4V) - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE; - -/* - * Enable the peripheral clock for required peripherals - */ -static void enable_per_clocks(void) -{ - /* HSMMC1 */ - writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); - while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0) - ; - - /* RTC clocks */ - writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl); - while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN) - ; -} - -/* - * select the HS1 or HS2 for DCO Freq - * return : CLKCTRL - */ -static u32 pll_dco_freq_sel(u32 clkout_dco) -{ - if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) - return SELFREQDCO_HS2; - else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) - return SELFREQDCO_HS1; - else - return -1; -} - -/* - * select the sigma delta config - * return: sigma delta val - */ -static u32 pll_sigma_delta_val(u32 clkout_dco) -{ - u32 sig_val = 0; - - sig_val = (clkout_dco + 225) / 250; - sig_val = sig_val << 24; - - return sig_val; -} - -/* - * configure individual ADPLLJ - */ -static void pll_config(u32 base, u32 n, u32 m, u32 m2, - u32 clkctrl_val, int adpllj) -{ - const struct ad_pll *adpll = (struct ad_pll *)base; - u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; - u32 sig_val = 0, hs_mod = 0; - - m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; - mn2val = m; - - /* calculate clkout_dco */ - clkout_dco = ((OSC_0_FREQ / (n+1)) * m); - - /* sigma delta & Hs mode selection skip for ADPLLS*/ - if (adpllj) { - sig_val = pll_sigma_delta_val(clkout_dco); - hs_mod = pll_dco_freq_sel(clkout_dco); - } - - /* by-pass pll */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); - while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) - != ADPLLJ_STATUS_BYPASSANDACK) - ; - - /* clear TINITZ */ - read_clkctrl = readl(&adpll->clkctrl); - writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* - * ref_clk = 20/(n + 1); - * clkout_dco = ref_clk * m; - * clk_out = clkout_dco/m2; - */ - read_clkctrl = readl(&adpll->clkctrl) & - ~(ADPLLJ_CLKCTRL_LPMODE | - ADPLLJ_CLKCTRL_DRIFTGUARDIAN | - ADPLLJ_CLKCTRL_REGM4XEN); - writel(m2nval, &adpll->m2ndiv); - writel(mn2val, &adpll->mn2div); - - /* Skip for modena(ADPLLS) */ - if (adpllj) { - writel(sig_val, &adpll->fracdiv); - writel((read_clkctrl | hs_mod), &adpll->clkctrl); - } - - /* Load M2, N2 dividers of ADPLL */ - writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); - - /* Load M, N dividers of ADPLL */ - writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); - writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); - - /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; - if (adpllj) - writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), - &adpll->clkctrl); - - /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ - read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; - writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); - - /* Wait for phase and freq lock */ - while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != - ADPLLJ_STATUS_PHSFRQLOCK) - ; -} - -static void unlock_pll_control_mmr(void) -{ - /* TRM 2.10.1.4 and 3.2.7-3.2.11 */ - writel(0x1EDA4C3D, 0x481C5040); - writel(0x2FF1AC2B, 0x48140060); - writel(0xF757FDC0, 0x48140064); - writel(0xE2BC3A6D, 0x48140068); - writel(0x1EBF131D, 0x4814006c); - writel(0x6F361E05, 0x48140070); -} - -static void mpu_pll_config(void) -{ - pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); -} - -static void l3_pll_config(void) -{ - u32 l3_osc_src, rd_osc_src = 0; - - l3_osc_src = L3_OSC_SRC; - rd_osc_src = readl(OSC_SRC_CTRL); - - if (OSC_SRC0 == l3_osc_src) - writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); - else - writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); - - pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); -} - -void ddr_pll_config(unsigned int ddrpll_m) -{ - pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); -} - -void sata_pll_config(void) -{ - /* - * This sequence for configuring the SATA PLL - * resident in the control module is documented - * in TI8148 TRM section 21.3.1 - */ - writel(SATA_PLLCFG1, &spll->pllcfg1); - udelay(50); - - writel(SATA_PLLCFG3, &spll->pllcfg3); - udelay(50); - - writel(SATA_PLLCFG0_1, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_2, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_3, &spll->pllcfg0); - udelay(50); - - writel(SATA_PLLCFG0_4, &spll->pllcfg0); - udelay(50); - - while (((readl(&spll->pllstatus) & PLL_LOCK) == 0)) - ; -} - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->fwclkctrl); - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) - ; - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_clocks_for_console(void) -{ - unlock_pll_control_mmr(); - /* UART0 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -/* - * Configure the PLL/PRCM for necessary peripherals - */ -void prcm_init(void) -{ - /* Enable the control module */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - /* Configure PLLs */ - mpu_pll_config(); - l3_pll_config(); - sata_pll_config(); - - /* Enable the required peripherals */ - enable_per_clocks(); -} diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index a5fdb0433d..bf3da43ed9 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -28,26 +28,6 @@ static struct cm_device_inst *cm_device = (struct cm_device_inst *)CM_DEVICE_INST; #endif -#ifdef CONFIG_TI814X -void config_dmm(const struct dmm_lisa_map_regs *regs) -{ - struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; - - enable_dmm_clocks(); - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); -} -#endif - static void config_vtp(int nr) { writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index f955d49471..d104f23b3e 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -183,7 +183,7 @@ void save_omap_boot_params(void) gd->arch.omap_boot_mode = boot_mode; -#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ +#if !defined(CONFIG_TI816X) && \ !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) /* CH flags */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 08b6c7bdcc..76e19918aa 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -704,7 +704,7 @@ config SYS_I2C_BUS_MAX depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA default 2 if TI816X default 3 if OMAP34XX || AM33XX || AM43XX - default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X + default 4 if ARCH_SOCFPGA || OMAP44XX default 5 if OMAP54XX help Define the maximum number of available I2C buses. diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c index a19dc38e52..3a8cc9c52a 100644 --- a/drivers/net/ti/cpsw.c +++ b/drivers/net/ti/cpsw.c @@ -79,10 +79,6 @@ struct cpsw_slave_regs { u32 tx_pri_map; #ifdef CONFIG_AM33XX u32 gap_thresh; -#elif defined(CONFIG_TI814X) - u32 ts_ctl; - u32 ts_seq_ltype; - u32 ts_vlan; #endif u32 sa_lo; u32 sa_hi; diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h deleted file mode 100644 index 03849adb5a..0000000000 --- a/include/configs/ti814x_evm.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * ti814x_evm.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_TI814X_EVM_H -#define __CONFIG_TI814X_EVM_H - -#include - -/* commands to include */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ - "fdtfile=\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - "fdtfile=ti814x-evm.dtb\0" \ - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - - -/* Console I/O Buffer Size */ - -/** - * Physical Memory Map - */ -#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ - -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/** - * Platform/Board specific defs - */ -#define CFG_SYS_TIMERBASE 0x4802E000 - -/* NS16550 Configuration */ -#define CFG_SYS_NS16550_CLK (48000000) -#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ - -/* CPU */ - -/* Defines for SPL */ - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80800000 should not be used for any - * other needs. - */ - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ - -/* Ethernet */ -#define CONFIG_PHY_ET1011C_TX_CLK_FIX - -#endif /* ! __CONFIG_TI814X_EVM_H */ From abbb4043c4d38228cb980ddddc0edb8e0fe81eae Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:42 -0500 Subject: [PATCH 209/424] powerpc: Migrate CONFIG_PPC_SPINTABLE_COMPATIBLE to Kconfig Move this symbol to Kconfig, and preserve the current behavior. The help text here comes from where the relevant code is implemented and it is quite likely at this point in time we could either disable this option or at least make it configurable. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 13 +++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 6 ------ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 36519613a2..03373bf869 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -1,6 +1,19 @@ menu "mpc85xx CPU" depends on MPC85xx +config PPC_SPINTABLE_COMPATIBLE + depends on MP + def_bool y + help + To comply with ePAPR 1.1, the spin table has been moved to + cache-enabled memory. Old OS may not work with this change. A patch + is waiting to be accepted for Linux kernel. Other OS needs similar + fix to spin table. For OSes with old spin table code, we can enable + this temporary fix by setting environmental variable + "spin_table_compat". For new OSes, set "spin_table_compat=no". After + Linux is fixed, we can remove this macro and related code. For now, + it is enabled by default. + config SYS_CPU default "mpc85xx" diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index e805991060..246bcb9fe4 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -8,12 +8,6 @@ /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ -/* - * This macro should be removed when we no longer care about backwards - * compatibility with older operating systems. - */ -#define CONFIG_PPC_SPINTABLE_COMPATIBLE - #include #if defined(CONFIG_ARCH_MPC8548) From c46597155ec38114c9908a6c6fed6819223e6adc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:43 -0500 Subject: [PATCH 210/424] sandbox: Finish migration to Kconfig Stop using CONFIG_SANDBOX_ARCH and use CONFIG_SANDBOX instead. For the SPI related defines, set them directly in Kconfig. This now empties arch/sandbox/include/asm/config.h. Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/sandbox/include/asm/config.h | 10 ---------- drivers/adc/adc-uclass.c | 2 +- drivers/spi/Kconfig | 10 ++++++++++ 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/sandbox/include/asm/config.h b/arch/sandbox/include/asm/config.h index 50215b35d7..87b9d23b37 100644 --- a/arch/sandbox/include/asm/config.h +++ b/arch/sandbox/include/asm/config.h @@ -6,14 +6,4 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#define CONFIG_SANDBOX_ARCH - -/* Used by drivers/spi/sandbox_spi.c and arch/sandbox/include/asm/state.h */ -#ifndef CONFIG_SANDBOX_SPI_MAX_BUS -#define CONFIG_SANDBOX_SPI_MAX_BUS 1 -#endif -#ifndef CONFIG_SANDBOX_SPI_MAX_CS -#define CONFIG_SANDBOX_SPI_MAX_CS 10 -#endif - #endif diff --git a/drivers/adc/adc-uclass.c b/drivers/adc/adc-uclass.c index 67137ffb34..9646e4d706 100644 --- a/drivers/adc/adc-uclass.c +++ b/drivers/adc/adc-uclass.c @@ -22,7 +22,7 @@ #define CHECK_MASK (!CHECK_NUMBER) /* TODO: add support for timer uclass (for early calls) */ -#ifdef CONFIG_SANDBOX_ARCH +#ifdef CONFIG_SANDBOX #define sdelay(x) udelay(x) #else extern void sdelay(unsigned long loops); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c6900f449d..64ceed12ce 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -429,6 +429,16 @@ config SANDBOX_SPI }; }; +config SANDBOX_SPI_MAX_BUS + int + depends on SANDBOX + default 1 + +config SANDBOX_SPI_MAX_CS + int + depends on SANDBOX + default 10 + config SPI_ASPEED_SMC bool "ASPEED SPI flash controller driver" depends on DM_SPI && SPI_MEM From 32b7e39db4d3af0d94f1387a7641152f375b23ac Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:44 -0500 Subject: [PATCH 211/424] Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig This converts the following to Kconfig: CONFIG_STANDALONE_LOAD_ADDR Signed-off-by: Tom Rini --- README | 7 ------- api/Kconfig | 19 +++++++++++++++++++ arch/arc/config.mk | 3 --- arch/arm/config.mk | 8 -------- .../include/asm/arch-fsl-layerscape/config.h | 2 -- arch/m68k/config.mk | 2 -- arch/microblaze/config.mk | 2 -- arch/mips/config.mk | 2 -- arch/nios2/config.mk | 2 -- arch/powerpc/config.mk | 1 - arch/riscv/config.mk | 2 -- arch/sh/config.mk | 1 - arch/x86/config.mk | 2 -- configs/display5_defconfig | 1 + configs/display5_factory_defconfig | 1 + configs/microchip_mpfs_icicle_defconfig | 1 + configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + configs/qemu-riscv64_spl_defconfig | 1 + configs/sifive_unleashed_defconfig | 1 + configs/sifive_unmatched_defconfig | 1 + configs/xtfpga_defconfig | 1 + include/configs/display5.h | 2 -- include/configs/microchip_mpfs_icicle.h | 2 -- include/configs/opos6uldev.h | 1 - include/configs/qemu-riscv.h | 2 -- include/configs/sifive-unleashed.h | 2 -- include/configs/sifive-unmatched.h | 2 -- include/configs/sunxi-common.h | 3 --- include/configs/xtfpga.h | 16 ---------------- 33 files changed, 31 insertions(+), 64 deletions(-) diff --git a/README b/README index 3ebee1cb37..c8f6b21e2d 100644 --- a/README +++ b/README @@ -1166,13 +1166,6 @@ The following options need to be configured: this is instead controlled by the value of /config/load-environment. - CONFIG_STANDALONE_LOAD_ADDR - - This option defines a board specific value for the - address where standalone program gets loaded, thus - overwriting the architecture dependent default - settings. - - Automatic software updates via TFTP server CONFIG_UPDATE_TFTP CONFIG_UPDATE_TFTP_CNT_MAX diff --git a/api/Kconfig b/api/Kconfig index eb8d5d0596..d9362724e5 100644 --- a/api/Kconfig +++ b/api/Kconfig @@ -11,3 +11,22 @@ config SYS_MMC_MAX_DEVICE default 1 endmenu + +config STANDALONE_LOAD_ADDR + hex "Address in memory to link standalone applications to" + default 0xffffffff80200000 if MIPS && 64BIT + default 0x8c000000 if SH + default 0x82000000 if ARC + default 0x80f00000 if MICROBLAZE + default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3 + default 0x80200000 if MIPS && 32BIT + default 0x0c100000 if ARM + default 0x02000000 if NIOS2 + default 0x00040000 if PPC || X86 + default 0x00020000 if M68K + default 0x0 if RISCV + default SYS_LOAD_ADDR + help + This option defines a board specific value for the address where + standalone program gets loaded, thus overwriting the architecture + dependent default settings. diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 2b70945ac3..b713fa3054 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -21,6 +21,3 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common # Needed for relocation LDFLAGS_FINAL += -pie --gc-sections - -# Load address for standalone apps -CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 2065438d05..bf781f1026 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -3,14 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifndef CONFIG_STANDALONE_LOAD_ADDR -ifneq ($(CONFIG_ARCH_OMAP2PLUS),) -CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 -else -CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 -endif -endif - CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \ -fstack-protector-strong CFLAGS_EFI := -fpic -fshort-wchar diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index c9c72e3271..57d92f6552 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -14,8 +14,6 @@ #include #endif -#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 - /* * Reserve secure memory * To be aligned with MMU block size diff --git a/arch/m68k/config.mk b/arch/m68k/config.mk index ed592334af..3ccbe49220 100644 --- a/arch/m68k/config.mk +++ b/arch/m68k/config.mk @@ -3,8 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000 - PLATFORM_CPPFLAGS += -D__M68K__ KBUILD_LDFLAGS += -n PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index d35b4f6db7..467c5ca1b1 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -6,8 +6,6 @@ # (C) Copyright 2004 Atmark Techno, Inc. # Yasushi SHOJI -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000 - PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 04f3627805..745f03190e 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -25,14 +25,12 @@ ifdef CONFIG_32BIT PLATFORM_CPPFLAGS += -mabi=32 KBUILD_LDFLAGS += -m $(32bit-emul) OBJCOPYFLAGS += -O $(32bit-bfd) -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 endif ifdef CONFIG_64BIT PLATFORM_CPPFLAGS += -mabi=64 KBUILD_LDFLAGS += -m$(64bit-emul) OBJCOPYFLAGS += -O $(64bit-bfd) -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 endif PLATFORM_CPPFLAGS += -D__MIPS__ diff --git a/arch/nios2/config.mk b/arch/nios2/config.mk index 44260b1431..b18b9b78ab 100644 --- a/arch/nios2/config.mk +++ b/arch/nios2/config.mk @@ -4,8 +4,6 @@ # Psyent Corporation # Scott McNutt -CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000 - PLATFORM_CPPFLAGS += -D__NIOS2__ PLATFORM_CPPFLAGS += -G0 diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 307ca65745..725a4f48aa 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -3,7 +3,6 @@ # (C) Copyright 2000-2010 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 LDFLAGS_FINAL += --gc-sections LDFLAGS_FINAL += --bss-plt PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \ diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index 1ebce5bd67..a8ed3faf28 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -23,8 +23,6 @@ KBUILD_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 - PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ -fdata-sections diff --git a/arch/sh/config.mk b/arch/sh/config.mk index 78bb2660e1..a408264d4b 100644 --- a/arch/sh/config.mk +++ b/arch/sh/config.mk @@ -3,7 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000 ifeq ($(CPU),sh2) LDFLAGS_STANDALONE += -EB endif diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 889497b6bd..a4a694ddf3 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -3,8 +3,6 @@ # (C) Copyright 2000-2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 - PLATFORM_CPPFLAGS += -fomit-frame-pointer PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -fno-unit-at-a-time)) diff --git a/configs/display5_defconfig b/configs/display5_defconfig index dbd917b4dd..c46a0a0b69 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -30,6 +30,7 @@ CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MONITOR_LEN=409600 +CONFIG_STANDALONE_LOAD_ADDR=0x10001000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 7508702eb9..cacdf33d53 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -27,6 +27,7 @@ CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_MONITOR_LEN=409600 +CONFIG_STANDALONE_LOAD_ADDR=0x10001000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index fbb2df4a74..c2b938e7e7 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -12,6 +12,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 425bb37c98..844c95380e 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -9,6 +9,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index eeb90360cd..2be349ada7 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -10,6 +10,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index 04447e5ed3..894b6d5d17 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -12,6 +12,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SYS_MONITOR_LEN=786432 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 7430fa075d..8b558e6bc2 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 03ef58ba47..6ed88de234 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -10,6 +10,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig index 840e0ff151..adc6f730d2 100644 --- a/configs/qemu-riscv64_spl_defconfig +++ b/configs/qemu-riscv64_spl_defconfig @@ -11,6 +11,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 99faabaa2f..6c85962cbb 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -16,6 +16,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_USE_PREBOOT=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index c390af2689..3d96aa5411 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -19,6 +19,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_STANDALONE_LOAD_ADDR=0x80200000 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 CONFIG_USE_PREBOOT=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index f5eeea426b..d3a350f540 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_ENV_ADDR=0xF7FE0000 CONFIG_XTFPGA_KC705=y CONFIG_SYS_MONITOR_LEN=262144 +CONFIG_STANDALONE_LOAD_ADDR=0x00800000 CONFIG_SYS_MONITOR_BASE=0xF6000000 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/include/configs/display5.h b/include/configs/display5.h index 5cbeb9224c..4401515a65 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -276,8 +276,6 @@ /* Miscellaneous configurable options */ -#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CFG_SYS_SDRAM_BASE PHYS_SDRAM diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index 3def93d61e..c73c5a1d9f 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -11,8 +11,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - /* Environment options */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 5c44b9dcb2..459134b93f 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -11,7 +11,6 @@ #include "mx6_common.h" /* Miscellaneous configurable options */ -#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR /* Physical Memory Map */ #define CFG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 72f35cc054..35172da3ff 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -10,8 +10,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - #define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMER_FREQ 1000000 diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 5ad2124bdd..4a453a9df4 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -13,8 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - #define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMER_FREQ 1000000 diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index f4b1a16019..ac42108620 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -13,8 +13,6 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - /* Environment options */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 496139f346..5d82e7e560 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -73,9 +73,6 @@ * Miscellaneous configurable options */ -/* standalone support */ -#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR - /* FLASH and environment organization */ /* diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 9201dac7ab..e0189c58f0 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -53,22 +53,6 @@ /* Memory test is destructive so default must not overlap vectors or U-Boot*/ -/* Load address for stand-alone applications. - * MEMADDR cannot be used here, because the definition needs to be - * a plain number as it's used as -Ttext argument for ld in standalone - * example makefile. - * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. - */ -#if XCHAL_HAVE_PTP_MMU -#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR -#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 -#endif -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 -#endif - #if defined(CONFIG_MAX_MEM_MAPPED) && \ CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ From d14f3f272519a5525d93ec98cbdd4d9eec7db6e9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:45 -0500 Subject: [PATCH 212/424] Convert CONFIG_TEGRA_ENABLE_UARTA et al to Kconfig This converts the following to Kconfig: CONFIG_TEGRA_ENABLE_UARTA CONFIG_TEGRA_ENABLE_UARTB CONFIG_TEGRA_ENABLE_UARTC CONFIG_TEGRA_ENABLE_UARTD CONFIG_TEGRA_SPI CONFIG_TEGRA_UARTA_GPU CONFIG_TEGRA_UARTA_SDIO1 CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 Signed-off-by: Tom Rini --- arch/arm/mach-tegra/Kconfig | 23 +++++++++++++++++++++++ arch/arm/mach-tegra/tegra20/Kconfig | 8 ++++++++ arch/arm/mach-tegra/tegra30/Kconfig | 8 ++++++++ configs/cei-tk1-som_defconfig | 1 + configs/dalmore_defconfig | 1 + configs/harmony_defconfig | 1 + configs/jetson-tk1_defconfig | 1 + configs/medcom-wide_defconfig | 1 + configs/plutux_defconfig | 1 + configs/seaboard_defconfig | 1 + configs/tec-ng_defconfig | 1 + configs/tec_defconfig | 1 + configs/ventana_defconfig | 1 + include/configs/apalis-tk1.h | 1 - include/configs/apalis_t30.h | 1 - include/configs/beaver.h | 4 ---- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 1 - include/configs/colibri_t20.h | 2 -- include/configs/colibri_t30.h | 1 - include/configs/dalmore.h | 1 - include/configs/harmony.h | 1 - include/configs/jetson-tk1.h | 1 - include/configs/medcom-wide.h | 1 - include/configs/nyan-big.h | 1 - include/configs/p2371-0000.h | 1 - include/configs/p2371-2180.h | 1 - include/configs/p2571.h | 1 - include/configs/p3450-0000.h | 1 - include/configs/paz00.h | 1 - include/configs/plutux.h | 1 - include/configs/seaboard.h | 1 - include/configs/tec-ng.h | 1 - include/configs/tec.h | 1 - include/configs/tegra-common-post.h | 4 ---- include/configs/trimslice.h | 2 -- include/configs/venice2.h | 1 - include/configs/ventana.h | 1 - 38 files changed, 49 insertions(+), 36 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index edcf967afd..1b575cc0f4 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -177,6 +177,29 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config TEGRA_SPI + def_bool y + depends on TEGRA20_SFLASH || TEGRA20_SLINK || TEGRA114_SPI + +choice + prompt "UART to use for console" + depends on TEGRA_PINCTRL + default TEGRA_ENABLE_UARTA + +config TEGRA_ENABLE_UARTA + bool "Use UARTA" + +config TEGRA_ENABLE_UARTB + bool "Use UARTB" + +config TEGRA_ENABLE_UARTC + bool "Use UARTC" + +config TEGRA_ENABLE_UARTD + bool "Use UARTD" + +endchoice + config TEGRA_GPU bool "Enable setting up the GPU" depends on TEGRA124 || TEGRA210 diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 345563fc78..955786c0c4 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -10,6 +10,12 @@ config TEGRA_PMU config TEGRA_CLOCK_SCALING bool +config TEGRA_UARTA_GPU + bool + +config TEGRA_UARTA_SDIO1 + bool + choice prompt "Tegra20 board select" optional @@ -43,6 +49,7 @@ config TARGET_TEC config TARGET_TRIMSLICE bool "Compulab TrimSlice board" select BOARD_LATE_INIT + select TEGRA_UARTA_GPU config TARGET_VENTANA bool "NVIDIA Tegra20 Ventana evaluation board" @@ -51,6 +58,7 @@ config TARGET_VENTANA config TARGET_COLIBRI_T20 bool "Toradex Colibri T20 board" select BOARD_LATE_INIT + select TEGRA_UARTA_SDIO1 endchoice diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 85b8ce294f..5619d1cd42 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -1,5 +1,11 @@ if TEGRA30 +config TEGRA_VDD_CORE_TPS62361B_SET3 + bool + +config TEGRA_VDD_CORE_TPS62366A_SET1 + bool + choice prompt "Tegra30 board select" optional @@ -11,10 +17,12 @@ config TARGET_APALIS_T30 config TARGET_BEAVER bool "NVIDIA Tegra30 Beaver evaluation board" select BOARD_LATE_INIT + select TEGRA_VDD_CORE_TPS62366A_SET1 config TARGET_CARDHU bool "NVIDIA Tegra30 Cardhu evaluation board" select BOARD_LATE_INIT + select TEGRA_VDD_CORE_TPS62361B_SET3 config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 58d75a52a0..0c4627aff0 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra124 (TK1-SOM) # " CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_TEGRA_GPU=y CONFIG_ARMV7_PSCI_0_1=y CONFIG_SYS_LOAD_ADDR=0x81000000 diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index cc46f4eda4..5d29dae341 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra114 (Dalmore) # " CONFIG_TEGRA114=y CONFIG_TARGET_DALMORE=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 353d1a33fa..c8694bba68 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Harmony) # " CONFIG_TEGRA20=y CONFIG_TARGET_HARMONY=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_STDIO_DEREGISTER=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index b391a86c02..d935e784ab 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra124 (Jetson TK1) # " CONFIG_TEGRA124=y CONFIG_TARGET_JETSON_TK1=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_TEGRA_GPU=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 76e4eb3078..563e01459a 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Medcom-Wide) # " CONFIG_TEGRA20=y CONFIG_TARGET_MEDCOM_WIDE=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index 170ac86468..789b5d9398 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Plutux) # " CONFIG_TEGRA20=y CONFIG_TARGET_PLUTUX=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 2375040a9e..dc9225188f 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (SeaBoard) # " CONFIG_TEGRA20=y CONFIG_TARGET_SEABOARD=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 02d6b496f9..8c3f8d5e06 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_SYS_PROMPT="Tegra30 (TEC-NG) # " CONFIG_TEGRA30=y CONFIG_TARGET_TEC_NG=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 967d3050ef..a1900f0181 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (TEC) # " CONFIG_TEGRA20=y CONFIG_TARGET_TEC=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_FIT=y CONFIG_OF_SYSTEM_SETUP=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index 3c924ec9ea..3d94f454be 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x00108000 CONFIG_SYS_PROMPT="Tegra20 (Ventana) # " CONFIG_TEGRA20=y CONFIG_TARGET_VENTANA=y +CONFIG_TEGRA_ENABLE_UARTD=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_OF_SYSTEM_SETUP=y CONFIG_USE_PREBOOT=y diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 1d478078b2..71d4727ca9 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -13,7 +13,6 @@ #include "tegra124-common.h" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define FDT_MODULE "apalis-v1.2" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 4f00b3bad3..80204d706d 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -20,7 +20,6 @@ * Apalis UART3: NVIDIA UARTB * Apalis UART4: NVIDIA UARTC */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 7078c2745c..7e0e477960 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -10,14 +10,10 @@ #include "tegra30-common.h" -/* VDD core PMIC */ -#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 - /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 5cca1e1834..64d713a196 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -10,9 +10,6 @@ #include "tegra30-common.h" -/* VDD core PMIC */ -#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 - /* High-level configuration options */ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" @@ -21,7 +18,6 @@ "fdtfile=tegra30-cardhu-a04.dtb\0" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index e3519ed751..e49eb60208 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -19,7 +19,6 @@ #define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #include "tegra-common-post.h" diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 2ba3c3bc87..ea7d648eb6 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -11,8 +11,6 @@ #include "tegra20-common.h" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_SDIO1 #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* NAND support */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index ffed71a2e8..7edb2c0b26 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -21,7 +21,6 @@ * Colibri UART-B: NVIDIA UARTD * Colibri UART-C: NVIDIA UARTB */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #define UBOOT_UPDATE \ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 82b2efdfe8..c9009e3962 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 211dab4d23..a1a66bfb64 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: keyboard satellite board UART, default */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index ea4964b13d..aa9e1d811a 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #include "tegra-common-post.h" diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index a8d8d8b09e..efac0febdf 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 21002f99dc..e885526e62 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index 653b4c583a..f426889e1c 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 2913d5304b..24adf4e13f 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index e78e3c4d6b..8a1e7d9b96 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index bab02dc2d6..078d35dde2 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA /* Only MMC/PXE/DHCP for now, add USB back in later when supported */ #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index a945f4e9b2..898167009f 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -16,7 +16,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 99db59c489..1d8ac618c0 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index f272fe9bf8..e5d672746b 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index c98322cf08..ae879abe3f 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -13,7 +13,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE #include "tegra-common-post.h" diff --git a/include/configs/tec.h b/include/configs/tec.h index ddf753da4a..e8a9df756d 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* NAND support */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 69acabf19f..2c668e0611 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -73,8 +73,4 @@ BOOTENV \ BOARD_EXTRA_ENV_SETTINGS -#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) -#define CONFIG_TEGRA_SPI -#endif - #endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index e4cbc7da84..b5bf991220 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -14,8 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_GPU #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* SPI */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index a4eb4bf4aa..970893ca17 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -15,7 +15,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index f7a507768e..e7b7b911d9 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -14,7 +14,6 @@ #define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" /* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE /* Environment in eMMC, at the end of 2nd "boot sector" */ From 60910a3f0267ccf2f87f1205aa3fb76491e674b5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:46 -0500 Subject: [PATCH 213/424] Convert CONFIG_THOR_RESET_OFF to Kconfig This converts the following to Kconfig: CONFIG_THOR_RESET_OFF Signed-off-by: Tom Rini --- cmd/Kconfig | 4 ++++ configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + include/configs/xilinx_versal.h | 1 - include/configs/xilinx_versal_net.h | 1 - include/configs/xilinx_zynqmp.h | 1 - include/configs/zynq-common.h | 1 - 10 files changed, 9 insertions(+), 4 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index d93731f2af..47d2ef04a2 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -526,6 +526,10 @@ config CMD_THOR_DOWNLOAD There is no documentation about this within the U-Boot source code but you should be able to find something on the interwebs. +config THOR_RESET_OFF + bool "thor: Disable reset on completion" + depends on CMD_THOR_DOWNLOAD + config CMD_ZBOOT bool "zboot - x86 boot command" help diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index ece625f629..2ae1fb8279 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 693a602ea3..510ff2ebd8 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 97624e69e7..0b708cccf6 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -40,6 +40,7 @@ CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=2077 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_DFU=y CONFIG_CMD_I2C=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 5068565769..610d9de2a6 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_PBSIZE=2071 CONFIG_SYS_BOOTM_LEN=0x3c00000 CONFIG_CMD_IMLS=y CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 4732c39bdb..ab2a542651 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -55,6 +55,7 @@ CONFIG_SYS_PBSIZE=2073 CONFIG_SYS_BOOTM_LEN=0x6400000 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_THOR_DOWNLOAD=y +CONFIG_THOR_RESET_OFF=y CONFIG_CMD_GREPENV=y CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMTEST=y diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index ee3130ed32..6ee6786e05 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -25,7 +25,6 @@ #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF #endif /* Ethernet driver */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 7d77189693..37bdb21462 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -25,7 +25,6 @@ #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index efe241df97..f71cd66099 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -31,7 +31,6 @@ #if defined(CONFIG_ZYNQMP_USB) #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF # define PARTS_DEFAULT \ "partitions=uuid_disk=${uuid_gpt_disk};" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 37b5428907..d95178eb64 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -38,7 +38,6 @@ #ifdef CONFIG_USB_EHCI_ZYNQ # define DFU_DEFAULT_POLL_TIMEOUT 300 -# define CONFIG_THOR_RESET_OFF #endif /* enable preboot to be loaded before CONFIG_BOOTDELAY */ From 4fd9373bbb3f160c2975fc9de2fab49040141833 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:47 -0500 Subject: [PATCH 214/424] net: Remove more legacy functions Remove some of the board and arch specific non-DM_ETH helper code. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/ls102xa/cpu.c | 9 --------- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 --- arch/powerpc/cpu/mpc83xx/cpu.c | 18 ----------------- arch/powerpc/cpu/mpc8xxx/cpu.c | 26 ------------------------- drivers/net/qe/uec.h | 1 - include/configs/km/km-mpc83xx.h | 5 ----- include/fm_eth.h | 1 - include/netdev.h | 1 - 8 files changed, 64 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 25e4b49c70..c455969609 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -302,15 +302,6 @@ int cpu_mmc_init(struct bd_info *bis) } #endif -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH) - tsec_standard_init(bis); -#endif - - return 0; -} - int arch_cpu_init(void) { void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 99413ef52e..2aeec7dea7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1057,9 +1057,6 @@ int cpu_eth_init(struct bd_info *bis) #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) error = fsl_mc_ldpaa_init(bis); -#endif -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); #endif return error; } diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 8d531898bd..a6c063556e 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -180,24 +180,6 @@ void watchdog_reset (void) } #endif -#ifndef CONFIG_DM_ETH -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) - tsec_standard_init(bis); -#endif - return 0; -} -#endif /* !CONFIG_DM_ETH */ - /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 7f20190922..73d28f2a4e 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -343,29 +343,3 @@ int fixup_cpu(void) #endif return 0; } - -#ifndef CONFIG_DM_ETH -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_UEC_ETH) - uec_standard_init(bis); -#endif - -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) - tsec_standard_init(bis); -#endif - -#ifdef CONFIG_FMAN_ENET - fm_standard_init(bis); -#endif - -#ifdef CONFIG_VSC9953 - vsc9953_init(bis); -#endif - return 0; -} -#endif diff --git a/drivers/net/qe/uec.h b/drivers/net/qe/uec.h index 551d7061cc..4510205da3 100644 --- a/drivers/net/qe/uec.h +++ b/drivers/net/qe/uec.h @@ -689,5 +689,4 @@ struct uec_priv { int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info); int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num); -int uec_standard_init(struct bd_info *bis); #endif /* __UEC_H__ */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 1f03f95ace..c939caf2a1 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -58,8 +58,3 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_SYS_BOOTMAPSZ (8 << 20) - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH diff --git a/include/fm_eth.h b/include/fm_eth.h index aeb640925e..6012a449fd 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -202,7 +202,6 @@ struct memac_mdio_info { int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info); int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info); -int fm_standard_init(struct bd_info *bis); void fman_enet_init(void); void fdt_fixup_fman_ethernet(void *fdt); phy_interface_t fm_info_get_enet_if(enum fm_port port); diff --git a/include/netdev.h b/include/netdev.h index b3f8584e90..2b4e474ed0 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -70,7 +70,6 @@ int sh_eth_initialize(struct bd_info *bis); int skge_initialize(struct bd_info *bis); int smc91111_initialize(u8 dev_num, phys_addr_t base_addr); int smc911x_initialize(u8 dev_num, phys_addr_t base_addr); -int uec_standard_init(struct bd_info *bis); int uli526x_initialize(struct bd_info *bis); int armada100_fec_register(unsigned long base_addr); From 8747decc9bda5512c2d7eff4c7cab178e5ad6152 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:48 -0500 Subject: [PATCH 215/424] net: vsc9953: Remove this driver No platforms enable this driver as there's no T1040D4RDB nor T1040RDB support at this time. Remove. Signed-off-by: Tom Rini --- board/freescale/t104xrdb/eth.c | 46 - drivers/net/Kconfig | 3 - drivers/net/Makefile | 1 - drivers/net/vsc9953.c | 2754 -------------------------------- 4 files changed, 2804 deletions(-) delete mode 100644 drivers/net/vsc9953.c diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index fe51d68c7b..c011aa96fb 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -22,10 +22,6 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info memac_mdio_info; unsigned int i; int phy_addr = 0; -#ifdef CONFIG_VSC9953 - phy_interface_t phy_int; - struct mii_dev *bus; -#endif printf("Initializing Fman\n"); @@ -107,48 +103,6 @@ int board_eth_init(struct bd_info *bis) DEFAULT_FM_MDIO_NAME)); } -#ifdef CONFIG_VSC9953 - /* SerDes configured for QSGMII */ - if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) { - for (i = 0; i < 4; i++) { - bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CFG_SYS_FM1_QSGMII11_PHY_ADDR + i; - phy_int = PHY_INTERFACE_MODE_QSGMII; - - vsc9953_port_info_set_mdio(i, bus); - vsc9953_port_info_set_phy_address(i, phy_addr); - vsc9953_port_info_set_phy_int(i, phy_int); - vsc9953_port_enable(i); - } - } - if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) { - for (i = 4; i < 8; i++) { - bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - phy_addr = CFG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4; - phy_int = PHY_INTERFACE_MODE_QSGMII; - - vsc9953_port_info_set_mdio(i, bus); - vsc9953_port_info_set_phy_address(i, phy_addr); - vsc9953_port_info_set_phy_int(i, phy_int); - vsc9953_port_enable(i); - } - } - - /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */ - if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0) - vsc9953_port_enable(8); - - /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */ - if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { - /* Enable L2 On MAC2 using SCFG */ - struct ccsr_scfg *scfg = (struct ccsr_scfg *) - CFG_SYS_MPC85xx_SCFG; - - out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | - (0x80000000)); - vsc9953_port_enable(9); - } -#endif cpu_eth_init(bis); #endif diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 53fb69f526..7873538cc2 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -709,9 +709,6 @@ config XILINX_AXIMRMAC config VSC7385_ENET bool "Vitesse 7385 Switch Firmware Upload driver" -config VSC9953 - bool "Vitesse VSC9953 L2 Switch driver" - config XILINX_EMACLITE select PHYLIB select MII diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d3fc6b7d3e..5b4e60eea3 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -87,7 +87,6 @@ obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o obj-$(CONFIG_TULIP) += dc2114x.o obj-$(CONFIG_VSC7385_ENET) += vsc7385.o -obj-$(CONFIG_VSC9953) += vsc9953.o obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o diff --git a/drivers/net/vsc9953.c b/drivers/net/vsc9953.c deleted file mode 100644 index 29f26b4b33..0000000000 --- a/drivers/net/vsc9953.c +++ /dev/null @@ -1,2754 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. - * - * Driver for the Vitesse VSC9953 L2 Switch - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct vsc9953_info vsc9953_l2sw = { - .port[0] = VSC9953_PORT_INFO_INITIALIZER(0), - .port[1] = VSC9953_PORT_INFO_INITIALIZER(1), - .port[2] = VSC9953_PORT_INFO_INITIALIZER(2), - .port[3] = VSC9953_PORT_INFO_INITIALIZER(3), - .port[4] = VSC9953_PORT_INFO_INITIALIZER(4), - .port[5] = VSC9953_PORT_INFO_INITIALIZER(5), - .port[6] = VSC9953_PORT_INFO_INITIALIZER(6), - .port[7] = VSC9953_PORT_INFO_INITIALIZER(7), - .port[8] = VSC9953_PORT_INFO_INITIALIZER(8), - .port[9] = VSC9953_PORT_INFO_INITIALIZER(9), -}; - -void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus) -{ - if (!VSC9953_PORT_CHECK(port_no)) - return; - - vsc9953_l2sw.port[port_no].bus = bus; -} - -void vsc9953_port_info_set_phy_address(int port_no, int address) -{ - if (!VSC9953_PORT_CHECK(port_no)) - return; - - vsc9953_l2sw.port[port_no].phyaddr = address; -} - -void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int) -{ - if (!VSC9953_PORT_CHECK(port_no)) - return; - - vsc9953_l2sw.port[port_no].enet_if = phy_int; -} - -void vsc9953_port_enable(int port_no) -{ - if (!VSC9953_PORT_CHECK(port_no)) - return; - - vsc9953_l2sw.port[port_no].enabled = 1; -} - -void vsc9953_port_disable(int port_no) -{ - if (!VSC9953_PORT_CHECK(port_no)) - return; - - vsc9953_l2sw.port[port_no].enabled = 0; -} - -static void vsc9953_mdio_write(struct vsc9953_mii_mng *phyregs, int port_addr, - int regnum, int value) -{ - int timeout = 50000; - - out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | - ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | - (0x1 << 1)); - asm("sync"); - - while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) - udelay(1); - - if (timeout == 0) - debug("Timeout waiting for MDIO write\n"); -} - -static int vsc9953_mdio_read(struct vsc9953_mii_mng *phyregs, int port_addr, - int regnum) -{ - int value = 0xFFFF; - int timeout = 50000; - - while ((in_le32(&phyregs->miimstatus) & MIIMIND_OPR_PEND) && --timeout) - udelay(1); - if (timeout == 0) { - debug("Timeout waiting for MDIO operation to finish\n"); - return value; - } - - /* Put the address of the phy, and the register - * number into MIICMD - */ - out_le32(&phyregs->miimcmd, (0x1 << 31) | ((port_addr & 0x1f) << 25) | - ((regnum & 0x1f) << 20) | ((value & 0xffff) << 4) | - (0x2 << 1)); - - timeout = 50000; - /* Wait for the the indication that the read is done */ - while ((in_le32(&phyregs->miimstatus) & 0x8) && --timeout) - udelay(1); - if (timeout == 0) - debug("Timeout waiting for MDIO read\n"); - - /* Grab the value read from the PHY */ - value = in_le32(&phyregs->miimdata); - - if ((value & 0x00030000) == 0) - return value & 0x0000ffff; - - return value; -} - -static int init_phy(struct eth_device *dev) -{ - struct vsc9953_port_info *l2sw_port = dev->priv; - struct phy_device *phydev = NULL; - -#ifdef CONFIG_PHYLIB - if (!l2sw_port->bus) - return 0; - phydev = phy_connect(l2sw_port->bus, l2sw_port->phyaddr, dev, - l2sw_port->enet_if); - if (!phydev) { - printf("Failed to connect\n"); - return -1; - } - - phydev->supported &= SUPPORTED_10baseT_Half | - SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | - SUPPORTED_100baseT_Full | - SUPPORTED_1000baseT_Full; - phydev->advertising = phydev->supported; - - l2sw_port->phydev = phydev; - - phy_config(phydev); -#endif - - return 0; -} - -static int vsc9953_port_init(int port_no) -{ - struct eth_device *dev; - - /* Internal ports never have a PHY */ - if (VSC9953_INTERNAL_PORT_CHECK(port_no)) - return 0; - - /* alloc eth device */ - dev = (struct eth_device *)calloc(1, sizeof(struct eth_device)); - if (!dev) - return -ENOMEM; - - sprintf(dev->name, "SW@PORT%d", port_no); - dev->priv = &vsc9953_l2sw.port[port_no]; - dev->init = NULL; - dev->halt = NULL; - dev->send = NULL; - dev->recv = NULL; - - if (init_phy(dev)) { - free(dev); - return -ENODEV; - } - - return 0; -} - -static int vsc9953_vlan_table_poll_idle(void) -{ - struct vsc9953_analyzer *l2ana_reg; - int timeout; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - timeout = 50000; - while (((in_le32(&l2ana_reg->ana_tables.vlan_access) & - VSC9953_VLAN_CMD_MASK) != VSC9953_VLAN_CMD_IDLE) && --timeout) - udelay(1); - - return timeout ? 0 : -EBUSY; -} - -#ifdef CONFIG_CMD_ETHSW -/* Add/remove a port to/from a VLAN */ -static void vsc9953_vlan_table_membership_set(int vid, u32 port_no, u8 add) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } - - val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); - val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); - out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); - - clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, - VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); - - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } - - val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); - val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid); - out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); - - val = in_le32(&l2ana_reg->ana_tables.vlan_access); - if (!add) { - val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, - VSC9953_VLAN_CMD_WRITE) & - ~(bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, - (1 << port_no))); - ; - } else { - val = bitfield_replace_by_mask(val, VSC9953_VLAN_CMD_MASK, - VSC9953_VLAN_CMD_WRITE) | - bitfield_replace_by_mask(0, VSC9953_VLAN_PORT_MASK, - (1 << port_no)); - } - out_le32(&l2ana_reg->ana_tables.vlan_access, val); - - /* wait for VLAN table command to flush */ - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } -} - -/* show VLAN membership for a port */ -static void vsc9953_vlan_membership_show(int port_no) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - u32 vid; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - printf("Port %d VLAN membership: ", port_no); - - for (vid = 0; vid < VSC9953_MAX_VLAN; vid++) { - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } - - val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); - val = bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, - vid); - out_le32(&l2ana_reg->ana_tables.vlan_tidx, val); - - clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, - VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); - - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } - - val = in_le32(&l2ana_reg->ana_tables.vlan_access); - - if (bitfield_extract_by_mask(val, VSC9953_VLAN_PORT_MASK) & - (1 << port_no)) - printf("%d ", vid); - } - printf("\n"); -} -#endif - -/* vlan table set/clear all membership of vid */ -static void vsc9953_vlan_table_membership_all_set(int vid, int set_member) -{ - uint val; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } - - /* read current vlan configuration */ - val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); - out_le32(&l2ana_reg->ana_tables.vlan_tidx, - bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); - - clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, - VSC9953_VLAN_CMD_MASK, VSC9953_VLAN_CMD_READ); - - if (vsc9953_vlan_table_poll_idle() < 0) { - debug("VLAN table timeout\n"); - return; - } - - val = in_le32(&l2ana_reg->ana_tables.vlan_tidx); - out_le32(&l2ana_reg->ana_tables.vlan_tidx, - bitfield_replace_by_mask(val, VSC9953_ANA_TBL_VID_MASK, vid)); - - clrsetbits_le32(&l2ana_reg->ana_tables.vlan_access, - VSC9953_VLAN_PORT_MASK | VSC9953_VLAN_CMD_MASK, - VSC9953_VLAN_CMD_WRITE | - (set_member ? VSC9953_VLAN_PORT_MASK : 0)); -} - -#ifdef CONFIG_CMD_ETHSW -/* Get PVID of a VSC9953 port */ -static int vsc9953_port_vlan_pvid_get(int port_nr, int *pvid) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_nr].enabled) { - printf("Port %d is administrative down\n", port_nr); - return -1; - } - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* Get ingress PVID */ - val = in_le32(&l2ana_reg->port[port_nr].vlan_cfg); - *pvid = bitfield_extract_by_mask(val, VSC9953_VLAN_CFG_VID_MASK); - - return 0; -} -#endif - -/* Set PVID for a VSC9953 port */ -static void vsc9953_port_vlan_pvid_set(int port_no, int pvid) -{ - uint val; - struct vsc9953_analyzer *l2ana_reg; - struct vsc9953_rew_reg *l2rew_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + - VSC9953_REW_OFFSET); - - /* Set PVID on ingress */ - val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); - val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_VID_MASK, pvid); - out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); - - /* Set PVID on egress */ - val = in_le32(&l2rew_reg->port[port_no].port_vlan_cfg); - val = bitfield_replace_by_mask(val, VSC9953_PORT_VLAN_CFG_VID_MASK, - pvid); - out_le32(&l2rew_reg->port[port_no].port_vlan_cfg, val); -} - -static void vsc9953_port_all_vlan_pvid_set(int pvid) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_pvid_set(i, pvid); -} - -/* Enable/disable vlan aware of a VSC9953 port */ -static void vsc9953_port_vlan_aware_set(int port_no, int enabled) -{ - struct vsc9953_analyzer *l2ana_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - if (enabled) - setbits_le32(&l2ana_reg->port[port_no].vlan_cfg, - VSC9953_VLAN_CFG_AWARE_ENA); - else - clrbits_le32(&l2ana_reg->port[port_no].vlan_cfg, - VSC9953_VLAN_CFG_AWARE_ENA); -} - -/* Set all VSC9953 ports' vlan aware */ -static void vsc9953_port_all_vlan_aware_set(int enabled) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_aware_set(i, enabled); -} - -/* Enable/disable vlan pop count of a VSC9953 port */ -static void vsc9953_port_vlan_popcnt_set(int port_no, int popcnt) -{ - uint val; - struct vsc9953_analyzer *l2ana_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - if (popcnt > 3 || popcnt < 0) { - printf("Invalid pop count value: %d\n", port_no); - return; - } - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - val = in_le32(&l2ana_reg->port[port_no].vlan_cfg); - val = bitfield_replace_by_mask(val, VSC9953_VLAN_CFG_POP_CNT_MASK, - popcnt); - out_le32(&l2ana_reg->port[port_no].vlan_cfg, val); -} - -/* Set all VSC9953 ports' pop count */ -static void vsc9953_port_all_vlan_poncnt_set(int popcnt) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_popcnt_set(i, popcnt); -} - -/* Enable/disable learning for frames dropped due to ingress filtering */ -static void vsc9953_vlan_ingr_fltr_learn_drop(int enable) -{ - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - if (enable) - setbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); - else - clrbits_le32(&l2ana_reg->ana.adv_learn, VSC9953_VLAN_CHK); -} - -enum aggr_code_mode { - AGGR_CODE_RAND = 0, - AGGR_CODE_ALL, /* S/D MAC, IPv4 S/D IP, IPv6 Flow Label, S/D PORT */ -}; - -/* Set aggregation code generation mode */ -static int vsc9953_aggr_code_set(enum aggr_code_mode ac) -{ - int rc; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - switch (ac) { - case AGGR_CODE_RAND: - clrsetbits_le32(&l2ana_reg->common.aggr_cfg, - VSC9953_AC_DMAC_ENA | VSC9953_AC_SMAC_ENA | - VSC9953_AC_IP6_LBL_ENA | - VSC9953_AC_IP6_TCPUDP_ENA | - VSC9953_AC_IP4_SIPDIP_ENA | - VSC9953_AC_IP4_TCPUDP_ENA, VSC9953_AC_RND_ENA); - rc = 0; - break; - case AGGR_CODE_ALL: - clrsetbits_le32(&l2ana_reg->common.aggr_cfg, VSC9953_AC_RND_ENA, - VSC9953_AC_DMAC_ENA | VSC9953_AC_SMAC_ENA | - VSC9953_AC_IP6_LBL_ENA | - VSC9953_AC_IP6_TCPUDP_ENA | - VSC9953_AC_IP4_SIPDIP_ENA | - VSC9953_AC_IP4_TCPUDP_ENA); - rc = 0; - break; - default: - /* unknown mode for aggregation code */ - rc = -EINVAL; - } - - return rc; -} - -/* Egress untag modes of a VSC9953 port */ -enum egress_untag_mode { - EGRESS_UNTAG_ALL = 0, - EGRESS_UNTAG_PVID_AND_ZERO, - EGRESS_UNTAG_ZERO, - EGRESS_UNTAG_NONE, -}; - -#ifdef CONFIG_CMD_ETHSW -/* Get egress tagging configuration for a VSC9953 port */ -static int vsc9953_port_vlan_egr_untag_get(int port_no, - enum egress_untag_mode *mode) -{ - u32 val; - struct vsc9953_rew_reg *l2rew_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return -1; - } - - l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + - VSC9953_REW_OFFSET); - - val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); - - switch (val & VSC9953_TAG_CFG_MASK) { - case VSC9953_TAG_CFG_NONE: - *mode = EGRESS_UNTAG_ALL; - return 0; - case VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO: - *mode = EGRESS_UNTAG_PVID_AND_ZERO; - return 0; - case VSC9953_TAG_CFG_ALL_BUT_ZERO: - *mode = EGRESS_UNTAG_ZERO; - return 0; - case VSC9953_TAG_CFG_ALL: - *mode = EGRESS_UNTAG_NONE; - return 0; - default: - printf("Unknown egress tagging configuration for port %d\n", - port_no); - return -1; - } -} - -/* Show egress tagging configuration for a VSC9953 port */ -static void vsc9953_port_vlan_egr_untag_show(int port_no) -{ - enum egress_untag_mode mode; - - if (vsc9953_port_vlan_egr_untag_get(port_no, &mode)) { - printf("%7d\t%17s\n", port_no, "-"); - return; - } - - printf("%7d\t", port_no); - switch (mode) { - case EGRESS_UNTAG_ALL: - printf("%17s\n", "all"); - break; - case EGRESS_UNTAG_NONE: - printf("%17s\n", "none"); - break; - case EGRESS_UNTAG_PVID_AND_ZERO: - printf("%17s\n", "PVID and 0"); - break; - case EGRESS_UNTAG_ZERO: - printf("%17s\n", "0"); - break; - default: - printf("%17s\n", "-"); - } -} -#endif - -static void vsc9953_port_vlan_egr_untag_set(int port_no, - enum egress_untag_mode mode) -{ - struct vsc9953_rew_reg *l2rew_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + - VSC9953_REW_OFFSET); - - switch (mode) { - case EGRESS_UNTAG_ALL: - clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, - VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_NONE); - break; - case EGRESS_UNTAG_PVID_AND_ZERO: - clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, - VSC9953_TAG_CFG_MASK, - VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO); - break; - case EGRESS_UNTAG_ZERO: - clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, - VSC9953_TAG_CFG_MASK, - VSC9953_TAG_CFG_ALL_BUT_ZERO); - break; - case EGRESS_UNTAG_NONE: - clrsetbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, - VSC9953_TAG_CFG_MASK, VSC9953_TAG_CFG_ALL); - break; - default: - printf("Unknown untag mode for port %d\n", port_no); - } -} - -static void vsc9953_port_all_vlan_egress_untagged_set( - enum egress_untag_mode mode) -{ - int i; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_egr_untag_set(i, mode); -} - -static int vsc9953_autoage_time_set(int age_period) -{ - u32 autoage; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - if (age_period < 0 || age_period > VSC9953_AUTOAGE_PERIOD_MASK) - return -EINVAL; - - autoage = bitfield_replace_by_mask(in_le32(&l2ana_reg->ana.auto_age), - VSC9953_AUTOAGE_PERIOD_MASK, - age_period); - out_le32(&l2ana_reg->ana.auto_age, autoage); - - return 0; -} - -#ifdef CONFIG_CMD_ETHSW - -/* Enable/disable status of a VSC9953 port */ -static void vsc9953_port_status_set(int port_no, u8 enabled) -{ - struct vsc9953_qsys_reg *l2qsys_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) - return; - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - if (enabled) - setbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], - VSC9953_PORT_ENA); - else - clrbits_le32(&l2qsys_reg->sys.switch_port_mode[port_no], - VSC9953_PORT_ENA); -} - -/* Start autonegotiation for a VSC9953 PHY */ -static void vsc9953_phy_autoneg(int port_no) -{ - if (!vsc9953_l2sw.port[port_no].phydev) - return; - - if (vsc9953_l2sw.port[port_no].phydev->drv->startup( - vsc9953_l2sw.port[port_no].phydev)) - printf("Failed to start PHY for port %d\n", port_no); -} - -/* Print a VSC9953 port's configuration */ -static void vsc9953_port_config_show(int port_no) -{ - int speed; - int duplex; - int link; - u8 enabled; - u32 val; - struct vsc9953_qsys_reg *l2qsys_reg; - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - val = in_le32(&l2qsys_reg->sys.switch_port_mode[port_no]); - enabled = vsc9953_l2sw.port[port_no].enabled && - (val & VSC9953_PORT_ENA); - - /* internal ports (8 and 9) are fixed */ - if (VSC9953_INTERNAL_PORT_CHECK(port_no)) { - link = 1; - speed = SPEED_2500; - duplex = DUPLEX_FULL; - } else { - if (vsc9953_l2sw.port[port_no].phydev) { - link = vsc9953_l2sw.port[port_no].phydev->link; - speed = vsc9953_l2sw.port[port_no].phydev->speed; - duplex = vsc9953_l2sw.port[port_no].phydev->duplex; - } else { - link = -1; - speed = -1; - duplex = -1; - } - } - - printf("%8d ", port_no); - printf("%8s ", enabled == 1 ? "enabled" : "disabled"); - printf("%8s ", link == 1 ? "up" : "down"); - - switch (speed) { - case SPEED_10: - printf("%8d ", 10); - break; - case SPEED_100: - printf("%8d ", 100); - break; - case SPEED_1000: - printf("%8d ", 1000); - break; - case SPEED_2500: - printf("%8d ", 2500); - break; - case SPEED_10000: - printf("%8d ", 10000); - break; - default: - printf("%8s ", "-"); - } - - printf("%8s\n", duplex == DUPLEX_FULL ? "full" : "half"); -} - -/* Show VSC9953 ports' statistics */ -static void vsc9953_port_statistics_show(int port_no) -{ - u32 rx_val; - u32 tx_val; - struct vsc9953_system_reg *l2sys_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + - VSC9953_SYS_OFFSET); - - printf("Statistics for L2 Switch port %d:\n", port_no); - - /* Set counter view for our port */ - out_le32(&l2sys_reg->sys.stat_cfg, port_no); - -#define VSC9953_STATS_PRINTF "%-15s %10u" - - /* Get number of Rx and Tx frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx frames:", rx_val, "Tx frames:", tx_val); - - /* Get number of Rx and Tx bytes */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_oct); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_oct); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx bytes:", rx_val, "Tx bytes:", tx_val); - - /* Get number of Rx frames received ok and Tx frames sent ok */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_0) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_1) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_2) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_3) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_4) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_5) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_6) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_yellow_prio_7) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_0) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_1) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_2) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_3) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_4) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_5) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_6) + - in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_green_prio_7); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx frames ok:", rx_val, "Tx frames ok:", tx_val); - - /* Get number of Rx and Tx unicast frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_uc); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_uc); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx unicast:", rx_val, "Tx unicast:", tx_val); - - /* Get number of Rx and Tx broadcast frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_bc); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_bc); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx broadcast:", rx_val, "Tx broadcast:", tx_val); - - /* Get number of Rx and Tx frames of 64B */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_64); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_64); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx 64B:", rx_val, "Tx 64B:", tx_val); - - /* Get number of Rx and Tx frames with sizes between 65B and 127B */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_65_127); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_65_127); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx 65B-127B:", rx_val, "Tx 65B-127B:", tx_val); - - /* Get number of Rx and Tx frames with sizes between 128B and 255B */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_128_255); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_128_255); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx 128B-255B:", rx_val, "Tx 128B-255B:", tx_val); - - /* Get number of Rx and Tx frames with sizes between 256B and 511B */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_256_511); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_256_511); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx 256B-511B:", rx_val, "Tx 256B-511B:", tx_val); - - /* Get number of Rx and Tx frames with sizes between 512B and 1023B */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_512_1023); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_512_1023); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx 512B-1023B:", rx_val, "Tx 512B-1023B:", tx_val); - - /* Get number of Rx and Tx frames with sizes between 1024B and 1526B */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_1024_1526); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_1024_1526); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx 1024B-1526B:", rx_val, "Tx 1024B-1526B:", tx_val); - - /* Get number of Rx and Tx jumbo frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_sz_jumbo); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_sz_jumbo); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx jumbo:", rx_val, "Tx jumbo:", tx_val); - - /* Get number of Rx and Tx dropped frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_tail) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_0) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_1) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_2) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_3) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_4) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_5) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_6) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_yellow_prio_7) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_0) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_1) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_2) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_3) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_4) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_5) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_6) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_green_prio_7); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_drop) + - in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx drops:", rx_val, "Tx drops:", tx_val); - - /* - * Get number of Rx frames with CRC or alignment errors - * and number of detected Tx collisions - */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_crc); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_col); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx CRC&align:", rx_val, "Tx coll:", tx_val); - - /* - * Get number of Rx undersized frames and - * number of Tx aged frames - */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_short); - tx_val = in_le32(&l2sys_reg->stat.tx_cntrs.c_tx_aged); - printf(VSC9953_STATS_PRINTF"\t\t"VSC9953_STATS_PRINTF"\n", - "Rx undersize:", rx_val, "Tx aged:", tx_val); - - /* Get number of Rx oversized frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_long); - printf(VSC9953_STATS_PRINTF"\n", "Rx oversized:", rx_val); - - /* Get number of Rx fragmented frames */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_frag); - printf(VSC9953_STATS_PRINTF"\n", "Rx fragments:", rx_val); - - /* Get number of Rx jabber errors */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_jabber); - printf(VSC9953_STATS_PRINTF"\n", "Rx jabbers:", rx_val); - - /* - * Get number of Rx frames filtered due to classification rules or - * no destination ports - */ - rx_val = in_le32(&l2sys_reg->stat.rx_cntrs.c_rx_cat_drop) + - in_le32(&l2sys_reg->stat.drop_cntrs.c_dr_local); - printf(VSC9953_STATS_PRINTF"\n", "Rx filtered:", rx_val); - - printf("\n"); -} - -/* Clear statistics for a VSC9953 port */ -static void vsc9953_port_statistics_clear(int port_no) -{ - struct vsc9953_system_reg *l2sys_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + - VSC9953_SYS_OFFSET); - - /* Clear all counter groups for our ports */ - out_le32(&l2sys_reg->sys.stat_cfg, port_no | - VSC9953_STAT_CLEAR_RX | VSC9953_STAT_CLEAR_TX | - VSC9953_STAT_CLEAR_DR); -} - -enum port_learn_mode { - PORT_LEARN_NONE, - PORT_LEARN_AUTO -}; - -/* Set learning configuration for a VSC9953 port */ -static void vsc9953_port_learn_mode_set(int port_no, enum port_learn_mode mode) -{ - struct vsc9953_analyzer *l2ana_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return; - } - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - switch (mode) { - case PORT_LEARN_NONE: - clrbits_le32(&l2ana_reg->port[port_no].port_cfg, - VSC9953_PORT_CFG_LEARN_DROP | - VSC9953_PORT_CFG_LEARN_CPU | - VSC9953_PORT_CFG_LEARN_AUTO | - VSC9953_PORT_CFG_LEARN_ENA); - break; - case PORT_LEARN_AUTO: - clrsetbits_le32(&l2ana_reg->port[port_no].port_cfg, - VSC9953_PORT_CFG_LEARN_DROP | - VSC9953_PORT_CFG_LEARN_CPU, - VSC9953_PORT_CFG_LEARN_ENA | - VSC9953_PORT_CFG_LEARN_AUTO); - break; - default: - printf("Unknown learn mode for port %d\n", port_no); - } -} - -/* Get learning configuration for a VSC9953 port */ -static int vsc9953_port_learn_mode_get(int port_no, enum port_learn_mode *mode) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - /* Administrative down */ - if (!vsc9953_l2sw.port[port_no].enabled) { - printf("Port %d is administrative down\n", port_no); - return -1; - } - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* For now we only support HW learning (auto) and no learning */ - val = in_le32(&l2ana_reg->port[port_no].port_cfg); - if ((val & (VSC9953_PORT_CFG_LEARN_ENA | - VSC9953_PORT_CFG_LEARN_AUTO)) == - (VSC9953_PORT_CFG_LEARN_ENA | VSC9953_PORT_CFG_LEARN_AUTO)) - *mode = PORT_LEARN_AUTO; - else - *mode = PORT_LEARN_NONE; - - return 0; -} - -/* wait for FDB to become available */ -static int vsc9953_mac_table_poll_idle(void) -{ - struct vsc9953_analyzer *l2ana_reg; - u32 timeout; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - timeout = 50000; - while (((in_le32(&l2ana_reg->ana_tables.mac_access) & - VSC9953_MAC_CMD_MASK) != - VSC9953_MAC_CMD_IDLE) && --timeout) - udelay(1); - - return timeout ? 0 : -EBUSY; -} - -/* enum describing available commands for the MAC table */ -enum mac_table_cmd { - MAC_TABLE_READ, - MAC_TABLE_LOOKUP, - MAC_TABLE_WRITE, - MAC_TABLE_LEARN, - MAC_TABLE_FORGET, - MAC_TABLE_GET_NEXT, - MAC_TABLE_AGE, -}; - -/* Issues a command to the FDB table */ -static int vsc9953_mac_table_cmd(enum mac_table_cmd cmd) -{ - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - switch (cmd) { - case MAC_TABLE_READ: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK | VSC9953_MAC_CMD_VALID, - VSC9953_MAC_CMD_READ); - break; - case MAC_TABLE_LOOKUP: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK, VSC9953_MAC_CMD_READ | - VSC9953_MAC_CMD_VALID); - break; - case MAC_TABLE_WRITE: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK | - VSC9953_MAC_ENTRYTYPE_MASK, - VSC9953_MAC_CMD_WRITE | - VSC9953_MAC_ENTRYTYPE_LOCKED); - break; - case MAC_TABLE_LEARN: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK | - VSC9953_MAC_ENTRYTYPE_MASK, - VSC9953_MAC_CMD_LEARN | - VSC9953_MAC_ENTRYTYPE_LOCKED | - VSC9953_MAC_CMD_VALID); - break; - case MAC_TABLE_FORGET: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK | - VSC9953_MAC_ENTRYTYPE_MASK, - VSC9953_MAC_CMD_FORGET); - break; - case MAC_TABLE_GET_NEXT: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK | - VSC9953_MAC_ENTRYTYPE_MASK, - VSC9953_MAC_CMD_NEXT); - break; - case MAC_TABLE_AGE: - clrsetbits_le32(&l2ana_reg->ana_tables.mac_access, - VSC9953_MAC_CMD_MASK | - VSC9953_MAC_ENTRYTYPE_MASK, - VSC9953_MAC_CMD_AGE); - break; - default: - printf("Unknown MAC table command\n"); - } - - if (vsc9953_mac_table_poll_idle() < 0) { - debug("MAC table timeout\n"); - return -1; - } - - return 0; -} - -/* show the FDB entries that correspond to a port and a VLAN */ -static void vsc9953_mac_table_show(int port_no, int vid) -{ - int rc[VSC9953_MAX_PORTS]; - enum port_learn_mode mode[VSC9953_MAX_PORTS]; - int i; - u32 val; - u32 vlan; - u32 mach; - u32 macl; - u32 dest_indx; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* disable auto learning */ - if (port_no == ETHSW_CMD_PORT_ALL) { - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); - if (!rc[i] && mode[i] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); - } - } else { - rc[port_no] = vsc9953_port_learn_mode_get(port_no, - &mode[port_no]); - if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); - } - - /* write port and vid to get selected FDB entries */ - val = in_le32(&l2ana_reg->ana.anag_efil); - if (port_no != ETHSW_CMD_PORT_ALL) { - val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, - port_no) | VSC9953_AGE_PORT_EN; - } - if (vid != ETHSW_CMD_VLAN_ALL) { - val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, - vid) | VSC9953_AGE_VID_EN; - } - out_le32(&l2ana_reg->ana.anag_efil, val); - - /* set MAC and VLAN to 0 to look from beginning */ - clrbits_le32(&l2ana_reg->ana_tables.mach_data, - VSC9953_MAC_VID_MASK | VSC9953_MAC_MACH_MASK); - out_le32(&l2ana_reg->ana_tables.macl_data, 0); - - /* get entries */ - printf("%10s %17s %5s %4s\n", "EntryType", "MAC", "PORT", "VID"); - do { - if (vsc9953_mac_table_cmd(MAC_TABLE_GET_NEXT) < 0) { - debug("GET NEXT MAC table command failed\n"); - break; - } - - val = in_le32(&l2ana_reg->ana_tables.mac_access); - - /* get out when an invalid entry is found */ - if (!(val & VSC9953_MAC_CMD_VALID)) - break; - - switch (val & VSC9953_MAC_ENTRYTYPE_MASK) { - case VSC9953_MAC_ENTRYTYPE_NORMAL: - printf("%10s ", "Dynamic"); - break; - case VSC9953_MAC_ENTRYTYPE_LOCKED: - printf("%10s ", "Static"); - break; - case VSC9953_MAC_ENTRYTYPE_IPV4MCAST: - printf("%10s ", "IPv4 Mcast"); - break; - case VSC9953_MAC_ENTRYTYPE_IPV6MCAST: - printf("%10s ", "IPv6 Mcast"); - break; - default: - printf("%10s ", "Unknown"); - } - - dest_indx = bitfield_extract_by_mask(val, - VSC9953_MAC_DESTIDX_MASK); - - val = in_le32(&l2ana_reg->ana_tables.mach_data); - vlan = bitfield_extract_by_mask(val, VSC9953_MAC_VID_MASK); - mach = bitfield_extract_by_mask(val, VSC9953_MAC_MACH_MASK); - macl = in_le32(&l2ana_reg->ana_tables.macl_data); - - printf("%02x:%02x:%02x:%02x:%02x:%02x ", (mach >> 8) & 0xff, - mach & 0xff, (macl >> 24) & 0xff, (macl >> 16) & 0xff, - (macl >> 8) & 0xff, macl & 0xff); - printf("%5d ", dest_indx); - printf("%4d\n", vlan); - } while (1); - - /* set learning mode to previous value */ - if (port_no == ETHSW_CMD_PORT_ALL) { - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (!rc[i] && mode[i] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(i, mode[i]); - } - } else { - /* If administrative down, skip */ - if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(port_no, mode[port_no]); - } - - /* reset FDB port and VLAN FDB selection */ - clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | - VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | - VSC9953_AGE_VID_MASK); -} - -/* Add a static FDB entry */ -static int vsc9953_mac_table_add(u8 port_no, uchar mac[6], int vid) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - val = in_le32(&l2ana_reg->ana_tables.mach_data); - val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | - (mac[0] << 8) | (mac[1] << 0); - out_le32(&l2ana_reg->ana_tables.mach_data, val); - - out_le32(&l2ana_reg->ana_tables.macl_data, - (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | - (mac[5] << 0)); - - /* set on which port is the MAC address added */ - val = in_le32(&l2ana_reg->ana_tables.mac_access); - val = bitfield_replace_by_mask(val, VSC9953_MAC_DESTIDX_MASK, port_no); - out_le32(&l2ana_reg->ana_tables.mac_access, val); - - if (vsc9953_mac_table_cmd(MAC_TABLE_LEARN) < 0) - return -1; - - /* check if the MAC address was indeed added */ - val = in_le32(&l2ana_reg->ana_tables.mach_data); - val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | - (mac[0] << 8) | (mac[1] << 0); - out_le32(&l2ana_reg->ana_tables.mach_data, val); - - out_le32(&l2ana_reg->ana_tables.macl_data, - (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | - (mac[5] << 0)); - - if (vsc9953_mac_table_cmd(MAC_TABLE_READ) < 0) - return -1; - - val = in_le32(&l2ana_reg->ana_tables.mac_access); - - if ((port_no != bitfield_extract_by_mask(val, - VSC9953_MAC_DESTIDX_MASK))) { - printf("Failed to add MAC address\n"); - return -1; - } - return 0; -} - -/* Delete a FDB entry */ -static int vsc9953_mac_table_del(uchar mac[6], u16 vid) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* check first if MAC entry is present */ - val = in_le32(&l2ana_reg->ana_tables.mach_data); - val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | - (mac[0] << 8) | (mac[1] << 0); - out_le32(&l2ana_reg->ana_tables.mach_data, val); - - out_le32(&l2ana_reg->ana_tables.macl_data, - (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | - (mac[5] << 0)); - - if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { - debug("Lookup in the MAC table failed\n"); - return -1; - } - - if (!(in_le32(&l2ana_reg->ana_tables.mac_access) & - VSC9953_MAC_CMD_VALID)) { - printf("The MAC address: %02x:%02x:%02x:%02x:%02x:%02x ", - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - printf("VLAN: %d does not exist.\n", vid); - return -1; - } - - /* FDB entry found, proceed to delete */ - val = in_le32(&l2ana_reg->ana_tables.mach_data); - val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | - (mac[0] << 8) | (mac[1] << 0); - out_le32(&l2ana_reg->ana_tables.mach_data, val); - - out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | - (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); - - if (vsc9953_mac_table_cmd(MAC_TABLE_FORGET) < 0) - return -1; - - /* check if the MAC entry is still in FDB */ - val = in_le32(&l2ana_reg->ana_tables.mach_data); - val = bitfield_replace_by_mask(val, VSC9953_MACHDATA_VID_MASK, vid) | - (mac[0] << 8) | (mac[1] << 0); - out_le32(&l2ana_reg->ana_tables.mach_data, val); - - out_le32(&l2ana_reg->ana_tables.macl_data, (mac[2] << 24) | - (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); - - if (vsc9953_mac_table_cmd(MAC_TABLE_LOOKUP) < 0) { - debug("Lookup in the MAC table failed\n"); - return -1; - } - if (in_le32(&l2ana_reg->ana_tables.mac_access) & - VSC9953_MAC_CMD_VALID) { - printf("Failed to delete MAC address\n"); - return -1; - } - - return 0; -} - -/* age the unlocked entries in FDB */ -static void vsc9953_mac_table_age(int port_no, int vid) -{ - int rc[VSC9953_MAX_PORTS]; - enum port_learn_mode mode[VSC9953_MAX_PORTS]; - u32 val; - int i; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* set port and VID for selective aging */ - val = in_le32(&l2ana_reg->ana.anag_efil); - if (port_no != ETHSW_CMD_PORT_ALL) { - /* disable auto learning */ - rc[port_no] = vsc9953_port_learn_mode_get(port_no, - &mode[port_no]); - if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(port_no, PORT_LEARN_NONE); - - val = bitfield_replace_by_mask(val, VSC9953_AGE_PORT_MASK, - port_no) | VSC9953_AGE_PORT_EN; - } else { - /* disable auto learning on all ports */ - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - rc[i] = vsc9953_port_learn_mode_get(i, &mode[i]); - if (!rc[i] && mode[i] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(i, PORT_LEARN_NONE); - } - } - - if (vid != ETHSW_CMD_VLAN_ALL) { - val = bitfield_replace_by_mask(val, VSC9953_AGE_VID_MASK, vid) | - VSC9953_AGE_VID_EN; - } - out_le32(&l2ana_reg->ana.anag_efil, val); - - /* age the dynamic FDB entries */ - vsc9953_mac_table_cmd(MAC_TABLE_AGE); - - /* clear previously set port and VID */ - clrbits_le32(&l2ana_reg->ana.anag_efil, VSC9953_AGE_PORT_EN | - VSC9953_AGE_PORT_MASK | VSC9953_AGE_VID_EN | - VSC9953_AGE_VID_MASK); - - if (port_no != ETHSW_CMD_PORT_ALL) { - if (!rc[port_no] && mode[port_no] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(port_no, mode[port_no]); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (!rc[i] && mode[i] != PORT_LEARN_NONE) - vsc9953_port_learn_mode_set(i, mode[i]); - } - } -} - -/* Delete all the dynamic FDB entries */ -static void vsc9953_mac_table_flush(int port, int vid) -{ - vsc9953_mac_table_age(port, vid); - vsc9953_mac_table_age(port, vid); -} - -enum egress_vlan_tag { - EGR_TAG_CLASS = 0, - EGR_TAG_PVID, -}; - -/* Set egress tag mode for a VSC9953 port */ -static void vsc9953_port_vlan_egress_tag_set(int port_no, - enum egress_vlan_tag mode) -{ - struct vsc9953_rew_reg *l2rew_reg; - - l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + - VSC9953_REW_OFFSET); - - switch (mode) { - case EGR_TAG_CLASS: - clrbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, - VSC9953_TAG_VID_PVID); - break; - case EGR_TAG_PVID: - setbits_le32(&l2rew_reg->port[port_no].port_tag_cfg, - VSC9953_TAG_VID_PVID); - break; - default: - printf("Unknown egress VLAN tag mode for port %d\n", port_no); - } -} - -/* Get egress tag mode for a VSC9953 port */ -static void vsc9953_port_vlan_egress_tag_get(int port_no, - enum egress_vlan_tag *mode) -{ - u32 val; - struct vsc9953_rew_reg *l2rew_reg; - - l2rew_reg = (struct vsc9953_rew_reg *)(VSC9953_OFFSET + - VSC9953_REW_OFFSET); - - val = in_le32(&l2rew_reg->port[port_no].port_tag_cfg); - if (val & VSC9953_TAG_VID_PVID) - *mode = EGR_TAG_PVID; - else - *mode = EGR_TAG_CLASS; -} - -/* VSC9953 VLAN learning modes */ -enum vlan_learning_mode { - SHARED_VLAN_LEARNING, - PRIVATE_VLAN_LEARNING, -}; - -/* Set VLAN learning mode for VSC9953 */ -static void vsc9953_vlan_learning_set(enum vlan_learning_mode lrn_mode) -{ - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - switch (lrn_mode) { - case SHARED_VLAN_LEARNING: - setbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); - break; - case PRIVATE_VLAN_LEARNING: - clrbits_le32(&l2ana_reg->ana.agen_ctrl, VSC9953_FID_MASK_ALL); - break; - default: - printf("Unknown VLAN learn mode\n"); - } -} - -/* Get VLAN learning mode for VSC9953 */ -static int vsc9953_vlan_learning_get(enum vlan_learning_mode *lrn_mode) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - val = in_le32(&l2ana_reg->ana.agen_ctrl); - - if (!(val & VSC9953_FID_MASK_ALL)) { - *lrn_mode = PRIVATE_VLAN_LEARNING; - } else if ((val & VSC9953_FID_MASK_ALL) == VSC9953_FID_MASK_ALL) { - *lrn_mode = SHARED_VLAN_LEARNING; - } else { - printf("Unknown VLAN learning mode\n"); - return -EINVAL; - } - - return 0; -} - -/* Enable/disable VLAN ingress filtering on a VSC9953 port */ -static void vsc9953_port_ingress_filtering_set(int port_no, int enabled) -{ - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - if (enabled) - setbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); - else - clrbits_le32(&l2ana_reg->ana.vlan_mask, 1 << port_no); -} - -/* Return VLAN ingress filtering on a VSC9953 port */ -static int vsc9953_port_ingress_filtering_get(int port_no) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - val = in_le32(&l2ana_reg->ana.vlan_mask); - return !!(val & (1 << port_no)); -} - -/* Get the aggregation group of a port */ -static int vsc9953_port_aggr_grp_get(int port_no, int *aggr_grp) -{ - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - if (!VSC9953_PORT_CHECK(port_no)) - return -EINVAL; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - val = in_le32(&l2ana_reg->port[port_no].port_cfg); - *aggr_grp = bitfield_extract_by_mask(val, - VSC9953_PORT_CFG_PORTID_MASK); - - return 0; -} - -static void vsc9953_aggr_grp_members_get(int aggr_grp, - u8 aggr_membr[VSC9953_MAX_PORTS]) -{ - int port_no; - int aggr_membr_grp; - - for (port_no = 0; port_no < VSC9953_MAX_PORTS; port_no++) { - aggr_membr[port_no] = 0; - - if (vsc9953_port_aggr_grp_get(port_no, &aggr_membr_grp)) - continue; - - if (aggr_grp == aggr_membr_grp) - aggr_membr[port_no] = 1; - } -} - -static void vsc9953_update_dest_members_masks(int port_no, u32 membr_bitfld_old, - u32 membr_bitfld_new) -{ - int i; - u32 pgid; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* - * NOTE: Only the unicast destination masks are updated, since - * we do not support for now Layer-2 multicast entries - */ - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (i == port_no) { - clrsetbits_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], - VSC9953_PGID_PORT_MASK, - membr_bitfld_new); - continue; - } - - pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[i]); - if ((u32)(1 << i) & membr_bitfld_old & VSC9953_PGID_PORT_MASK) - pgid &= ~((u32)(1 << port_no)); - if ((u32)(1 << i) & membr_bitfld_new & VSC9953_PGID_PORT_MASK) - pgid |= ((u32)(1 << port_no)); - - out_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], pgid); - } -} - -static void vsc9953_update_source_members_masks(int port_no, - u32 membr_bitfld_old, - u32 membr_bitfld_new) -{ - int i; - int index; - u32 pgid; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - for (i = 0; i < VSC9953_MAX_PORTS + 1; i++) { - index = PGID_SRC_START + i; - pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[index]); - if (i == port_no) { - pgid = (pgid | VSC9953_PGID_PORT_MASK) & - ~membr_bitfld_new; - out_le32(&l2ana_reg->port_id_tbl.port_grp_id[index], - pgid); - continue; - } - - if ((u32)(1 << i) & membr_bitfld_old & VSC9953_PGID_PORT_MASK) - pgid |= (u32)(1 << port_no); - - if ((u32)(1 << i) & membr_bitfld_new & VSC9953_PGID_PORT_MASK) - pgid &= ~(u32)(1 << port_no); - out_le32(&l2ana_reg->port_id_tbl.port_grp_id[index], pgid); - } -} - -static u32 vsc9953_aggr_mask_get_next(u32 aggr_mask, u32 member_bitfield) -{ - if (!member_bitfield) - return 0; - - if (!(aggr_mask & VSC9953_PGID_PORT_MASK)) - aggr_mask = 1; - else - aggr_mask <<= 1; - - while (!(aggr_mask & member_bitfield)) { - aggr_mask <<= 1; - if (!(aggr_mask & VSC9953_PGID_PORT_MASK)) - aggr_mask = 1; - } - - return aggr_mask; -} - -static void vsc9953_update_aggr_members_masks(int port_no, u32 membr_bitfld_old, - u32 membr_bitfld_new) -{ - int i; - u32 pgid; - u32 aggr_mask_old = 0; - u32 aggr_mask_new = 0; - struct vsc9953_analyzer *l2ana_reg; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - /* Update all the PGID aggregation masks */ - for (i = PGID_AGGR_START; i < PGID_SRC_START; i++) { - pgid = in_le32(&l2ana_reg->port_id_tbl.port_grp_id[i]); - - aggr_mask_old = vsc9953_aggr_mask_get_next(aggr_mask_old, - membr_bitfld_old); - pgid = (pgid & ~membr_bitfld_old) | aggr_mask_old; - - aggr_mask_new = vsc9953_aggr_mask_get_next(aggr_mask_new, - membr_bitfld_new); - pgid = (pgid & ~membr_bitfld_new) | aggr_mask_new; - - out_le32(&l2ana_reg->port_id_tbl.port_grp_id[i], pgid); - } -} - -static u32 vsc9953_aggr_membr_bitfield_get(u8 member[VSC9953_MAX_PORTS]) -{ - int i; - u32 member_bitfield = 0; - - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (member[i]) - member_bitfield |= 1 << i; - } - member_bitfield &= VSC9953_PGID_PORT_MASK; - - return member_bitfield; -} - -static void vsc9953_update_members_masks(int port_no, - u8 member_old[VSC9953_MAX_PORTS], - u8 member_new[VSC9953_MAX_PORTS]) -{ - u32 membr_bitfld_old = vsc9953_aggr_membr_bitfield_get(member_old); - u32 membr_bitfld_new = vsc9953_aggr_membr_bitfield_get(member_new); - - vsc9953_update_dest_members_masks(port_no, membr_bitfld_old, - membr_bitfld_new); - vsc9953_update_source_members_masks(port_no, membr_bitfld_old, - membr_bitfld_new); - vsc9953_update_aggr_members_masks(port_no, membr_bitfld_old, - membr_bitfld_new); -} - -/* Set the aggregation group of a port */ -static int vsc9953_port_aggr_grp_set(int port_no, int aggr_grp) -{ - u8 aggr_membr_old[VSC9953_MAX_PORTS]; - u8 aggr_membr_new[VSC9953_MAX_PORTS]; - int rc; - int aggr_grp_old; - u32 val; - struct vsc9953_analyzer *l2ana_reg; - - if (!VSC9953_PORT_CHECK(port_no) || !VSC9953_PORT_CHECK(aggr_grp)) - return -EINVAL; - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - rc = vsc9953_port_aggr_grp_get(port_no, &aggr_grp_old); - if (rc) - return rc; - - /* get all the members of the old aggregation group */ - vsc9953_aggr_grp_members_get(aggr_grp_old, aggr_membr_old); - - /* get all the members of the same aggregation group */ - vsc9953_aggr_grp_members_get(aggr_grp, aggr_membr_new); - - /* add current port as member to the new aggregation group */ - aggr_membr_old[port_no] = 0; - aggr_membr_new[port_no] = 1; - - /* update masks */ - vsc9953_update_members_masks(port_no, aggr_membr_old, aggr_membr_new); - - /* Change logical port number */ - val = in_le32(&l2ana_reg->port[port_no].port_cfg); - val = bitfield_replace_by_mask(val, - VSC9953_PORT_CFG_PORTID_MASK, aggr_grp); - out_le32(&l2ana_reg->port[port_no].port_cfg, val); - - return 0; -} - -static int vsc9953_port_status_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - u8 enabled; - - /* Last keyword should tell us if we should enable/disable the port */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_enable) - enabled = 1; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_disable) - enabled = 0; - else - return CMD_RET_USAGE; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_status_set(parsed_cmd->port, enabled); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_status_set(i, enabled); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_port_config_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_phy_autoneg(parsed_cmd->port); - printf("%8s %8s %8s %8s %8s\n", - "Port", "Status", "Link", "Speed", - "Duplex"); - vsc9953_port_config_show(parsed_cmd->port); - - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_phy_autoneg(i); - printf("%8s %8s %8s %8s %8s\n", - "Port", "Status", "Link", "Speed", "Duplex"); - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_config_show(i); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_port_stats_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_statistics_show(parsed_cmd->port); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_statistics_show(i); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_port_stats_clear_key_func(struct ethsw_command_def - *parsed_cmd) -{ - int i; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_statistics_clear(parsed_cmd->port); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_statistics_clear(i); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_learn_show_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - enum port_learn_mode mode; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - if (vsc9953_port_learn_mode_get(parsed_cmd->port, &mode)) - return CMD_RET_FAILURE; - printf("%7s %11s\n", "Port", "Learn mode"); - switch (mode) { - case PORT_LEARN_NONE: - printf("%7d %11s\n", parsed_cmd->port, "disable"); - break; - case PORT_LEARN_AUTO: - printf("%7d %11s\n", parsed_cmd->port, "auto"); - break; - default: - printf("%7d %11s\n", parsed_cmd->port, "-"); - } - } else { - printf("%7s %11s\n", "Port", "Learn mode"); - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (vsc9953_port_learn_mode_get(i, &mode)) - continue; - switch (mode) { - case PORT_LEARN_NONE: - printf("%7d %11s\n", i, "disable"); - break; - case PORT_LEARN_AUTO: - printf("%7d %11s\n", i, "auto"); - break; - default: - printf("%7d %11s\n", i, "-"); - } - } - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_learn_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - enum port_learn_mode mode; - - /* Last keyword should tell us the learn mode */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_auto) - mode = PORT_LEARN_AUTO; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_disable) - mode = PORT_LEARN_NONE; - else - return CMD_RET_USAGE; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_learn_mode_set(parsed_cmd->port, mode); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_learn_mode_set(i, mode); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_fdb_show_key_func(struct ethsw_command_def *parsed_cmd) -{ - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && - !VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - - if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && - !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { - printf("Invalid VID number: %d\n", parsed_cmd->vid); - return CMD_RET_FAILURE; - } - - vsc9953_mac_table_show(parsed_cmd->port, parsed_cmd->vid); - - return CMD_RET_SUCCESS; -} - -static int vsc9953_fdb_flush_key_func(struct ethsw_command_def *parsed_cmd) -{ - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL && - !VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - - if (parsed_cmd->vid != ETHSW_CMD_VLAN_ALL && - !VSC9953_VLAN_CHECK(parsed_cmd->vid)) { - printf("Invalid VID number: %d\n", parsed_cmd->vid); - return CMD_RET_FAILURE; - } - - vsc9953_mac_table_flush(parsed_cmd->port, parsed_cmd->vid); - - return CMD_RET_SUCCESS; -} - -static int vsc9953_fdb_entry_add_key_func(struct ethsw_command_def *parsed_cmd) -{ - int vid; - - /* a port number must be present */ - if (parsed_cmd->port == ETHSW_CMD_PORT_ALL) { - printf("Please specify a port\n"); - return CMD_RET_FAILURE; - } - - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - - /* Use VLAN 1 if VID is not set */ - vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); - - if (!VSC9953_VLAN_CHECK(vid)) { - printf("Invalid VID number: %d\n", vid); - return CMD_RET_FAILURE; - } - - if (vsc9953_mac_table_add(parsed_cmd->port, parsed_cmd->ethaddr, vid)) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -static int vsc9953_fdb_entry_del_key_func(struct ethsw_command_def *parsed_cmd) -{ - int vid; - - /* Use VLAN 1 if VID is not set */ - vid = (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL ? 1 : parsed_cmd->vid); - - if (!VSC9953_VLAN_CHECK(vid)) { - printf("Invalid VID number: %d\n", vid); - return CMD_RET_FAILURE; - } - - if (vsc9953_mac_table_del(parsed_cmd->ethaddr, vid)) - return CMD_RET_FAILURE; - - return CMD_RET_SUCCESS; -} - -static int vsc9953_pvid_show_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - int pvid; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - - if (vsc9953_port_vlan_pvid_get(parsed_cmd->port, &pvid)) - return CMD_RET_FAILURE; - printf("%7s %7s\n", "Port", "PVID"); - printf("%7d %7d\n", parsed_cmd->port, pvid); - } else { - printf("%7s %7s\n", "Port", "PVID"); - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (vsc9953_port_vlan_pvid_get(i, &pvid)) - continue; - printf("%7d %7d\n", i, pvid); - } - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_pvid_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - /* PVID number should be set in parsed_cmd->vid */ - if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { - printf("Please set a pvid value\n"); - return CMD_RET_FAILURE; - } - - if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { - printf("Invalid VID number: %d\n", parsed_cmd->vid); - return CMD_RET_FAILURE; - } - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_vlan_pvid_set(parsed_cmd->port, parsed_cmd->vid); - } else { - vsc9953_port_all_vlan_pvid_set(parsed_cmd->vid); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_vlan_show_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_vlan_membership_show(parsed_cmd->port); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_vlan_membership_show(i); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_vlan_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - int add; - - /* VLAN should be set in parsed_cmd->vid */ - if (parsed_cmd->vid == ETHSW_CMD_VLAN_ALL) { - printf("Please set a vlan value\n"); - return CMD_RET_FAILURE; - } - - if (!VSC9953_VLAN_CHECK(parsed_cmd->vid)) { - printf("Invalid VID number: %d\n", parsed_cmd->vid); - return CMD_RET_FAILURE; - } - - /* keywords add/delete should be the last but one in array */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == - ethsw_id_add) - add = 1; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 2] == - ethsw_id_del) - add = 0; - else - return CMD_RET_USAGE; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_vlan_table_membership_set(parsed_cmd->vid, - parsed_cmd->port, add); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_vlan_table_membership_set(parsed_cmd->vid, i, - add); - } - - return CMD_RET_SUCCESS; -} -static int vsc9953_port_untag_show_key_func( - struct ethsw_command_def *parsed_cmd) -{ - int i; - - printf("%7s\t%17s\n", "Port", "Untag"); - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_vlan_egr_untag_show(parsed_cmd->port); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_egr_untag_show(i); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_port_untag_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - enum egress_untag_mode mode; - - /* keywords for the untagged mode are the last in the array */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_all) - mode = EGRESS_UNTAG_ALL; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_none) - mode = EGRESS_UNTAG_NONE; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_pvid) - mode = EGRESS_UNTAG_PVID_AND_ZERO; - else - return CMD_RET_USAGE; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_vlan_egr_untag_set(parsed_cmd->port, mode); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_egr_untag_set(i, mode); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_egr_vlan_tag_show_key_func( - struct ethsw_command_def *parsed_cmd) -{ - int i; - enum egress_vlan_tag mode; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_vlan_egress_tag_get(parsed_cmd->port, &mode); - printf("%7s\t%12s\n", "Port", "Egress VID"); - printf("%7d\t", parsed_cmd->port); - switch (mode) { - case EGR_TAG_CLASS: - printf("%12s\n", "classified"); - break; - case EGR_TAG_PVID: - printf("%12s\n", "pvid"); - break; - default: - printf("%12s\n", "-"); - } - } else { - printf("%7s\t%12s\n", "Port", "Egress VID"); - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - vsc9953_port_vlan_egress_tag_get(i, &mode); - switch (mode) { - case EGR_TAG_CLASS: - printf("%7d\t%12s\n", i, "classified"); - break; - case EGR_TAG_PVID: - printf("%7d\t%12s\n", i, "pvid"); - break; - default: - printf("%7d\t%12s\n", i, "-"); - } - } - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_egr_vlan_tag_set_key_func( - struct ethsw_command_def *parsed_cmd) -{ - int i; - enum egress_vlan_tag mode; - - /* keywords for the egress vlan tag mode are the last in the array */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_pvid) - mode = EGR_TAG_PVID; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_classified) - mode = EGR_TAG_CLASS; - else - return CMD_RET_USAGE; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_vlan_egress_tag_set(parsed_cmd->port, mode); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_vlan_egress_tag_set(i, mode); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_vlan_learn_show_key_func( - struct ethsw_command_def *parsed_cmd) -{ - int rc; - enum vlan_learning_mode mode; - - rc = vsc9953_vlan_learning_get(&mode); - if (rc) - return CMD_RET_FAILURE; - - switch (mode) { - case SHARED_VLAN_LEARNING: - printf("VLAN learning mode: shared\n"); - break; - case PRIVATE_VLAN_LEARNING: - printf("VLAN learning mode: private\n"); - break; - default: - printf("Unknown VLAN learning mode\n"); - rc = CMD_RET_FAILURE; - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_vlan_learn_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - enum vlan_learning_mode mode; - - /* keywords for shared/private are the last in the array */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_shared) - mode = SHARED_VLAN_LEARNING; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_private) - mode = PRIVATE_VLAN_LEARNING; - else - return CMD_RET_USAGE; - - vsc9953_vlan_learning_set(mode); - - return CMD_RET_SUCCESS; -} - -static int vsc9953_ingr_fltr_show_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - int enabled; - - printf("%7s\t%18s\n", "Port", "Ingress filtering"); - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - enabled = vsc9953_port_ingress_filtering_get(parsed_cmd->port); - printf("%7d\t%18s\n", parsed_cmd->port, enabled ? "enable" : - "disable"); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - enabled = vsc9953_port_ingress_filtering_get(i); - printf("%7d\t%18s\n", parsed_cmd->port, enabled ? - "enable" : - "disable"); - } - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_ingr_fltr_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - int enable; - - /* keywords for enabling/disabling ingress filtering - * are the last in the array - */ - if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_enable) - enable = 1; - else if (parsed_cmd->cmd_to_keywords[parsed_cmd->cmd_keywords_nr - 1] == - ethsw_id_disable) - enable = 0; - else - return CMD_RET_USAGE; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - vsc9953_port_ingress_filtering_set(parsed_cmd->port, enable); - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) - vsc9953_port_ingress_filtering_set(i, enable); - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_port_aggr_show_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - int aggr_grp; - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - - if (vsc9953_port_aggr_grp_get(parsed_cmd->port, &aggr_grp)) - return CMD_RET_FAILURE; - printf("%7s %10s\n", "Port", "Aggr grp"); - printf("%7d %10d\n", parsed_cmd->port, aggr_grp); - } else { - printf("%7s %10s\n", "Port", "Aggr grp"); - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (vsc9953_port_aggr_grp_get(i, &aggr_grp)) - continue; - printf("%7d %10d\n", i, aggr_grp); - } - } - - return CMD_RET_SUCCESS; -} - -static int vsc9953_port_aggr_set_key_func(struct ethsw_command_def *parsed_cmd) -{ - int i; - - /* Aggregation group number should be set in parsed_cmd->aggr_grp */ - if (parsed_cmd->aggr_grp == ETHSW_CMD_AGGR_GRP_NONE) { - printf("Please set an aggregation group value\n"); - return CMD_RET_FAILURE; - } - - if (!VSC9953_PORT_CHECK(parsed_cmd->aggr_grp)) { - printf("Invalid aggregation group number: %d\n", - parsed_cmd->aggr_grp); - return CMD_RET_FAILURE; - } - - if (parsed_cmd->port != ETHSW_CMD_PORT_ALL) { - if (!VSC9953_PORT_CHECK(parsed_cmd->port)) { - printf("Invalid port number: %d\n", parsed_cmd->port); - return CMD_RET_FAILURE; - } - if (vsc9953_port_aggr_grp_set(parsed_cmd->port, - parsed_cmd->aggr_grp)) { - printf("Port %d: failed to set aggr group %d\n", - parsed_cmd->port, parsed_cmd->aggr_grp); - } - } else { - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (vsc9953_port_aggr_grp_set(i, - parsed_cmd->aggr_grp)) { - printf("Port %d: failed to set aggr group %d\n", - i, parsed_cmd->aggr_grp); - } - } - } - - return CMD_RET_SUCCESS; -} - -static struct ethsw_command_func vsc9953_cmd_func = { - .ethsw_name = "L2 Switch VSC9953", - .port_enable = &vsc9953_port_status_key_func, - .port_disable = &vsc9953_port_status_key_func, - .port_show = &vsc9953_port_config_key_func, - .port_stats = &vsc9953_port_stats_key_func, - .port_stats_clear = &vsc9953_port_stats_clear_key_func, - .port_learn = &vsc9953_learn_set_key_func, - .port_learn_show = &vsc9953_learn_show_key_func, - .fdb_show = &vsc9953_fdb_show_key_func, - .fdb_flush = &vsc9953_fdb_flush_key_func, - .fdb_entry_add = &vsc9953_fdb_entry_add_key_func, - .fdb_entry_del = &vsc9953_fdb_entry_del_key_func, - .pvid_show = &vsc9953_pvid_show_key_func, - .pvid_set = &vsc9953_pvid_set_key_func, - .vlan_show = &vsc9953_vlan_show_key_func, - .vlan_set = &vsc9953_vlan_set_key_func, - .port_untag_show = &vsc9953_port_untag_show_key_func, - .port_untag_set = &vsc9953_port_untag_set_key_func, - .port_egr_vlan_show = &vsc9953_egr_vlan_tag_show_key_func, - .port_egr_vlan_set = &vsc9953_egr_vlan_tag_set_key_func, - .vlan_learn_show = &vsc9953_vlan_learn_show_key_func, - .vlan_learn_set = &vsc9953_vlan_learn_set_key_func, - .port_ingr_filt_show = &vsc9953_ingr_fltr_show_key_func, - .port_ingr_filt_set = &vsc9953_ingr_fltr_set_key_func, - .port_aggr_show = &vsc9953_port_aggr_show_key_func, - .port_aggr_set = &vsc9953_port_aggr_set_key_func, -}; - -#endif /* CONFIG_CMD_ETHSW */ - -/***************************************************************************** -At startup, the default configuration would be: - - HW learning enabled on all ports; (HW default) - - All ports are in VLAN 1; - - All ports are VLAN aware; - - All ports have POP_COUNT 1; - - All ports have PVID 1; - - All ports have TPID 0x8100; (HW default) - - All ports tag frames classified to all VLANs that are not PVID; -*****************************************************************************/ -void vsc9953_default_configuration(void) -{ - int i; - - if (vsc9953_autoage_time_set(VSC9953_DEFAULT_AGE_TIME)) - debug("VSC9953: failed to set AGE time to %d\n", - VSC9953_DEFAULT_AGE_TIME); - - for (i = 0; i < VSC9953_MAX_VLAN; i++) - vsc9953_vlan_table_membership_all_set(i, 0); - vsc9953_port_all_vlan_aware_set(1); - vsc9953_port_all_vlan_pvid_set(1); - vsc9953_port_all_vlan_poncnt_set(1); - vsc9953_vlan_table_membership_all_set(1, 1); - vsc9953_vlan_ingr_fltr_learn_drop(1); - vsc9953_port_all_vlan_egress_untagged_set(EGRESS_UNTAG_PVID_AND_ZERO); - if (vsc9953_aggr_code_set(AGGR_CODE_ALL)) - debug("VSC9953: failed to set default aggregation code mode\n"); -} - -static void vcap_entry2cache_init(u32 target, u32 entry_words) -{ - int i; - - for (i = 0; i < entry_words; i++) { - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CACHE_ENTRY_DAT(target, i)), 0x00); - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CACHE_MASK_DAT(target, i)), 0xFF); - } - - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CACHE_TG_DAT(target)), 0x00); - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CFG_MV_CFG(target)), - VSC9953_VCAP_CFG_MV_CFG_SIZE(entry_words)); -} - -static void vcap_action2cache_init(u32 target, u32 action_words, - u32 counter_words) -{ - int i; - - for (i = 0; i < action_words; i++) - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CACHE_ACTION_DAT(target, i)), 0x00); - - for (i = 0; i < counter_words; i++) - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CACHE_CNT_DAT(target, i)), 0x00); -} - -static int vcap_cmd(u32 target, u16 ix, int cmd, int sel, int entry_count) -{ - u32 tgt = target; - u32 value = (VSC9953_VCAP_UPDATE_CTRL_UPDATE_CMD(cmd) | - VSC9953_VCAP_UPDATE_CTRL_UPDATE_ADDR(ix) | - VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT); - - if ((sel & TCAM_SEL_ENTRY) && ix >= entry_count) - return CMD_RET_FAILURE; - - if (!(sel & TCAM_SEL_ENTRY)) - value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS; - - if (!(sel & TCAM_SEL_ACTION)) - value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS; - - if (!(sel & TCAM_SEL_COUNTER)) - value |= VSC9953_VCAP_UPDATE_CTRL_UPDATE_CNT_DIS; - - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CFG_UPDATE_CTRL(tgt)), value); - - do { - value = in_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CFG_UPDATE_CTRL(tgt))); - - } while (value & VSC9953_VCAP_UPDATE_CTRL_UPDATE_SHOT); - - return CMD_RET_SUCCESS; -} - -static void vsc9953_vcap_init(void) -{ - u32 tgt = VSC9953_ES0; - int cmd_ret; - - /* write entries */ - vcap_entry2cache_init(tgt, ENTRY_WORDS_ES0); - cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, - ENTRY_WORDS_ES0); - if (cmd_ret != CMD_RET_SUCCESS) - debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n", - __LINE__); - - /* write actions and counters */ - vcap_action2cache_init(tgt, BITS_TO_DWORD(ES0_ACT_WIDTH), - BITS_TO_DWORD(ES0_CNT_WIDTH)); - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CFG_MV_CFG(tgt)), - VSC9953_VCAP_CFG_MV_CFG_SIZE(ES0_ACT_COUNT)); - cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, - TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_ES0); - if (cmd_ret != CMD_RET_SUCCESS) - debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", - __LINE__); - - tgt = VSC9953_IS1; - - /* write entries */ - vcap_entry2cache_init(tgt, ENTRY_WORDS_IS1); - cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, - ENTRY_WORDS_IS1); - if (cmd_ret != CMD_RET_SUCCESS) - debug("VSC9953:%d invalid TCAM_SEL_ENTRY\n", - __LINE__); - - /* write actions and counters */ - vcap_action2cache_init(tgt, BITS_TO_DWORD(IS1_ACT_WIDTH), - BITS_TO_DWORD(IS1_CNT_WIDTH)); - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CFG_MV_CFG(tgt)), - VSC9953_VCAP_CFG_MV_CFG_SIZE(IS1_ACT_COUNT)); - cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, - TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS1); - if (cmd_ret != CMD_RET_SUCCESS) - debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", - __LINE__); - - tgt = VSC9953_IS2; - - /* write entries */ - vcap_entry2cache_init(tgt, ENTRY_WORDS_IS2); - cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, TCAM_SEL_ENTRY, - ENTRY_WORDS_IS2); - if (cmd_ret != CMD_RET_SUCCESS) - debug("VSC9953:%d invalid selection: TCAM_SEL_ENTRY\n", - __LINE__); - - /* write actions and counters */ - vcap_action2cache_init(tgt, BITS_TO_DWORD(IS2_ACT_WIDTH), - BITS_TO_DWORD(IS2_CNT_WIDTH)); - out_le32((unsigned int *)(VSC9953_OFFSET + - VSC9953_VCAP_CFG_MV_CFG(tgt)), - VSC9953_VCAP_CFG_MV_CFG_SIZE(IS2_ACT_COUNT)); - cmd_ret = vcap_cmd(tgt, 0, TCAM_CMD_INITIALIZE, - TCAM_SEL_ACTION | TCAM_SEL_COUNTER, ENTRY_WORDS_IS2); - if (cmd_ret != CMD_RET_SUCCESS) - debug("VSC9953:%d invalid TCAM_SEL_ACTION | TCAM_SEL_COUNTER\n", - __LINE__); -} - -void vsc9953_init(struct bd_info *bis) -{ - u32 i; - u32 hdx_cfg = 0; - u32 phy_addr = 0; - int timeout; - struct vsc9953_system_reg *l2sys_reg; - struct vsc9953_qsys_reg *l2qsys_reg; - struct vsc9953_dev_gmii *l2dev_gmii_reg; - struct vsc9953_analyzer *l2ana_reg; - struct vsc9953_devcpu_gcb *l2dev_gcb; - - l2dev_gmii_reg = (struct vsc9953_dev_gmii *)(VSC9953_OFFSET + - VSC9953_DEV_GMII_OFFSET); - - l2ana_reg = (struct vsc9953_analyzer *)(VSC9953_OFFSET + - VSC9953_ANA_OFFSET); - - l2sys_reg = (struct vsc9953_system_reg *)(VSC9953_OFFSET + - VSC9953_SYS_OFFSET); - - l2qsys_reg = (struct vsc9953_qsys_reg *)(VSC9953_OFFSET + - VSC9953_QSYS_OFFSET); - - l2dev_gcb = (struct vsc9953_devcpu_gcb *)(VSC9953_OFFSET + - VSC9953_DEVCPU_GCB); - - out_le32(&l2dev_gcb->chip_regs.soft_rst, - VSC9953_SOFT_SWC_RST_ENA); - timeout = 50000; - while ((in_le32(&l2dev_gcb->chip_regs.soft_rst) & - VSC9953_SOFT_SWC_RST_ENA) && --timeout) - udelay(1); /* busy wait for vsc9953 soft reset */ - if (timeout == 0) - debug("Timeout waiting for VSC9953 to reset\n"); - - out_le32(&l2sys_reg->sys.reset_cfg, VSC9953_MEM_ENABLE | - VSC9953_MEM_INIT); - - timeout = 50000; - while ((in_le32(&l2sys_reg->sys.reset_cfg) & - VSC9953_MEM_INIT) && --timeout) - udelay(1); /* busy wait for vsc9953 memory init */ - if (timeout == 0) - debug("Timeout waiting for VSC9953 memory to initialize\n"); - - out_le32(&l2sys_reg->sys.reset_cfg, (in_le32(&l2sys_reg->sys.reset_cfg) - | VSC9953_CORE_ENABLE)); - - /* VSC9953 Setting to be done once only */ - out_le32(&l2qsys_reg->sys.ext_cpu_cfg, 0x00000b00); - - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - if (vsc9953_port_init(i)) - printf("Failed to initialize l2switch port %d\n", i); - - if (!vsc9953_l2sw.port[i].enabled) - continue; - - /* Enable VSC9953 GMII Ports Port ID 0 - 7 */ - if (VSC9953_INTERNAL_PORT_CHECK(i)) { - out_le32(&l2ana_reg->pfc[i].pfc_cfg, - VSC9953_PFC_FC_QSGMII); - out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], - VSC9953_MAC_FC_CFG_QSGMII); - } else { - out_le32(&l2ana_reg->pfc[i].pfc_cfg, - VSC9953_PFC_FC); - out_le32(&l2sys_reg->pause_cfg.mac_fc_cfg[i], - VSC9953_MAC_FC_CFG); - } - - l2dev_gmii_reg = (struct vsc9953_dev_gmii *) - (VSC9953_OFFSET + VSC9953_DEV_GMII_OFFSET + - T1040_SWITCH_GMII_DEV_OFFSET * i); - - out_le32(&l2dev_gmii_reg->port_mode.clock_cfg, - VSC9953_CLOCK_CFG); - out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ena_cfg, - VSC9953_MAC_ENA_CFG); - out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_mode_cfg, - VSC9953_MAC_MODE_CFG); - out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_ifg_cfg, - VSC9953_MAC_IFG_CFG); - /* mac_hdx_cfg varies with port id*/ - hdx_cfg = VSC9953_MAC_HDX_CFG | (i << 16); - out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_hdx_cfg, hdx_cfg); - out_le32(&l2sys_reg->sys.front_port_mode[i], - VSC9953_FRONT_PORT_MODE); - setbits_le32(&l2qsys_reg->sys.switch_port_mode[i], - VSC9953_PORT_ENA); - out_le32(&l2dev_gmii_reg->mac_cfg_status.mac_maxlen_cfg, - VSC9953_MAC_MAX_LEN); - out_le32(&l2sys_reg->pause_cfg.pause_cfg[i], - VSC9953_PAUSE_CFG); - /* WAIT FOR 2 us*/ - udelay(2); - - /* Initialize Lynx PHY Wrappers */ - phy_addr = 0; - if (vsc9953_l2sw.port[i].enet_if == - PHY_INTERFACE_MODE_QSGMII) - phy_addr = (i + 0x4) & 0x1F; - else if (vsc9953_l2sw.port[i].enet_if == - PHY_INTERFACE_MODE_SGMII) - phy_addr = (i + 1) & 0x1F; - - if (phy_addr) { - /* SGMII IF mode + AN enable */ - vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, - 0x14, PHY_SGMII_IF_MODE_AN | - PHY_SGMII_IF_MODE_SGMII); - /* Dev ability according to SGMII specification */ - vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, - 0x4, PHY_SGMII_DEV_ABILITY_SGMII); - /* Adjust link timer for SGMII - * 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 - */ - vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, - 0x13, 0x0003); - vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, - 0x12, 0x0d40); - /* Restart AN */ - vsc9953_mdio_write(&l2dev_gcb->mii_mng[0], phy_addr, - 0x0, PHY_SGMII_CR_DEF_VAL | - PHY_SGMII_CR_RESET_AN); - - timeout = 50000; - while ((vsc9953_mdio_read(&l2dev_gcb->mii_mng[0], - phy_addr, 0x01) & 0x0020) && --timeout) - udelay(1); /* wait for AN to complete */ - if (timeout == 0) - debug("Timeout waiting for AN to complete\n"); - } - } - - vsc9953_vcap_init(); - vsc9953_default_configuration(); - -#ifdef CONFIG_CMD_ETHSW - if (ethsw_define_functions(&vsc9953_cmd_func) < 0) - debug("Unable to use \"ethsw\" commands\n"); -#endif - - printf("VSC9953 L2 switch initialized\n"); - return; -} From 0c3a6d443f4751b681566e8a752d12e04f4369f4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:49 -0500 Subject: [PATCH 216/424] usb: Remove CONFIG_USBD_HS This define is not enabled by the only platform which currently enables the legacy option of CONFIG_USB_DEVICE. We can drop this code. Signed-off-by: Tom Rini --- README | 8 ----- drivers/serial/usbtty.c | 50 -------------------------- drivers/serial/usbtty.h | 4 --- drivers/usb/gadget/ep0.c | 19 ---------- include/configs/apalis_imx6.h | 2 -- include/configs/colibri-imx6ull.h | 2 -- include/configs/colibri_imx6.h | 2 -- include/configs/colibri_imx7.h | 2 -- include/configs/ge_b1x5v2.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/imx7-cm.h | 2 -- include/configs/librem5.h | 2 -- include/configs/mx6sabre_common.h | 2 -- include/configs/mx7dsabresd.h | 2 -- include/configs/nitrogen6x.h | 2 -- include/configs/novena.h | 2 -- include/configs/pico-imx6ul.h | 2 -- include/configs/siemens-am33x-common.h | 3 -- include/configs/tbs2910.h | 3 -- include/configs/warp7.h | 2 -- include/usbdescriptors.h | 15 -------- include/usbdevice.h | 19 ---------- 22 files changed, 147 deletions(-) diff --git a/README b/README index c8f6b21e2d..2944646665 100644 --- a/README +++ b/README @@ -618,14 +618,6 @@ The following options need to be configured: variable usbtty to be cdc_acm should suffice. The following might be defined in YourBoardName.h - CONFIG_USBD_HS - Define this to enable the high speed support for usb - device and usbtty. If this feature is enabled, a routine - int is_usbd_high_speed(void) - also needs to be defined by the driver to dynamically poll - whether the enumeration has succeded at high speed or full - speed. - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index 4f4eb02de0..07a59ec960 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -120,20 +120,6 @@ static struct usb_device_descriptor device_descriptor = { .bNumConfigurations = NUM_CONFIGS }; - -#if defined(CONFIG_USBD_HS) -static struct usb_qualifier_descriptor qualifier_descriptor = { - .bLength = sizeof(struct usb_qualifier_descriptor), - .bDescriptorType = USB_DT_QUAL, - .bcdUSB = cpu_to_le16(USB_BCD_VERSION), - .bDeviceClass = COMMUNICATIONS_DEVICE_CLASS, - .bDeviceSubClass = 0x00, - .bDeviceProtocol = 0x00, - .bMaxPacketSize0 = EP0_MAX_PACKET_SIZE, - .bNumConfigurations = NUM_CONFIGS -}; -#endif - /* * Static CDC ACM specific descriptors */ @@ -639,9 +625,6 @@ static void usbtty_init_instances (void) memset (device_instance, 0, sizeof (struct usb_device_instance)); device_instance->device_state = STATE_INIT; device_instance->device_descriptor = &device_descriptor; -#if defined(CONFIG_USBD_HS) - device_instance->qualifier_descriptor = &qualifier_descriptor; -#endif device_instance->event = usbtty_event_handler; device_instance->cdc_recv_setup = usbtty_cdc_setup; device_instance->bus = bus_instance; @@ -755,10 +738,6 @@ static void usbtty_init_terminal_type(short type) device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM); -#if defined(CONFIG_USBD_HS) - qualifier_descriptor.bDeviceClass = - COMMUNICATIONS_DEVICE_CLASS; -#endif /* Assign endpoint indices */ tx_endpoint = ACM_TX_ENDPOINT; rx_endpoint = ACM_RX_ENDPOINT; @@ -787,9 +766,6 @@ static void usbtty_init_terminal_type(short type) device_descriptor.bDeviceClass = 0xFF; device_descriptor.idProduct = cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL); -#if defined(CONFIG_USBD_HS) - qualifier_descriptor.bDeviceClass = 0xFF; -#endif /* Assign endpoint indices */ tx_endpoint = GSERIAL_TX_ENDPOINT; rx_endpoint = GSERIAL_RX_ENDPOINT; @@ -937,9 +913,6 @@ static int usbtty_configured (void) static void usbtty_event_handler (struct usb_device_instance *device, usb_device_event_t event, int data) { -#if defined(CONFIG_USBD_HS) - int i; -#endif switch (event) { case DEVICE_RESET: case DEVICE_BUS_INACTIVE: @@ -950,29 +923,6 @@ static void usbtty_event_handler (struct usb_device_instance *device, break; case DEVICE_ADDRESS_ASSIGNED: -#if defined(CONFIG_USBD_HS) - /* - * is_usbd_high_speed routine needs to be defined by - * specific gadget driver - * It returns true if device enumerates at High speed - * Retuns false otherwise - */ - for (i = 0; i < NUM_ENDPOINTS; i++) { - if (((ep_descriptor_ptrs[i]->bmAttributes & - USB_ENDPOINT_XFERTYPE_MASK) == - USB_ENDPOINT_XFER_BULK) - && is_usbd_high_speed()) { - - ep_descriptor_ptrs[i]->wMaxPacketSize = - CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE; - } - - endpoint_instance[i + 1].tx_packetSize = - ep_descriptor_ptrs[i]->wMaxPacketSize; - endpoint_instance[i + 1].rcv_packetSize = - ep_descriptor_ptrs[i]->wMaxPacketSize; - } -#endif usbtty_init_endpoints (); default: diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index e27aa368c9..ac4d22044d 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -51,10 +51,6 @@ #define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE #define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE -#if defined(CONFIG_USBD_HS) -#define CONFIG_USBD_SERIAL_BULK_HS_PKTSIZE UDC_BULK_HS_PACKET_SIZE -#endif - #define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS #define USBTTY_BCD_DEVICE 0x00 diff --git a/drivers/usb/gadget/ep0.c b/drivers/usb/gadget/ep0.c index 6624f61b76..c256cc31fb 100644 --- a/drivers/usb/gadget/ep0.c +++ b/drivers/usb/gadget/ep0.c @@ -371,26 +371,7 @@ static int ep0_get_descriptor (struct usb_device_instance *device, } break; case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: -#if defined(CONFIG_USBD_HS) - { - struct usb_qualifier_descriptor *qualifier_descriptor = - device->qualifier_descriptor; - - if (!qualifier_descriptor) - return -1; - - /* copy descriptor for this device */ - copy_config(urb, qualifier_descriptor, - sizeof(struct usb_qualifier_descriptor), - max); - - } - dbg_ep0(3, "copied qualifier descriptor, actual_length: 0x%x", - urb->actual_length); -#else return -1; -#endif - break; default: return -1; diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 25a84458f5..07587c7609 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -28,8 +28,6 @@ /* Host */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS /* Framebuffer and LCD */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2f09a264cb..6f3524deb5 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -126,8 +126,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 19daad21cb..4e51df123a 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -25,8 +25,6 @@ /* Host */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS /* Command definition */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 48c3f01547..89546b857f 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -170,6 +170,4 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - #endif diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 1458b187de..1aaa3e67d6 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -26,7 +26,6 @@ /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 298a8f5aa2..5a78c68e2f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -38,7 +38,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS /* Miscellaneous configurable options */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 76771fd66c..8e9dbefc49 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -81,6 +81,4 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - #endif /* __CONFIG_H */ diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 11b3fa6c85..377e3e7b3f 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -27,8 +27,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_USBD_HS - #define CONSOLE_ON_UART1 #ifdef CONSOLE_ON_UART1 diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 6294fd1e2c..96a48a97a3 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -145,6 +145,4 @@ /* Environment organization */ -#define CONFIG_USBD_HS - #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 6c165521f7..bd70b62bd2 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -101,6 +101,4 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - #endif /* __CONFIG_H */ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 5020b3bb71..1d101977c2 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,8 +11,6 @@ #include "mx6_common.h" -#define CONFIG_USBD_HS - #define CONFIG_MXC_UART_BASE UART2_BASE /* MMC Configs */ diff --git a/include/configs/novena.h b/include/configs/novena.h index 79e49c74f8..b0d473eeee 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -55,8 +55,6 @@ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -/* Gadget part */ -#define CONFIG_USBD_HS #endif /* Extra U-Boot environment. */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 8af8883fad..faf11d5a72 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -26,8 +26,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS - #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_DFU_ENV_SETTINGS \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 1b1787a3d3..406a179842 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -70,9 +70,6 @@ * we don't need to do it twice. */ -/* USB DRACO ID as default */ -#define CONFIG_USBD_HS - /* USB Device Firmware Update support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index fcc9674942..689914cb18 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -28,9 +28,6 @@ /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#ifdef CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USBD_HS -#endif /* CONFIG_CMD_USB_MASS_STORAGE */ #endif /* CONFIG_CMD_USB */ #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 56c90aa103..a985c6f28f 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -95,8 +95,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/usbdescriptors.h b/include/usbdescriptors.h index 9a50387451..641b4a3e6f 100644 --- a/include/usbdescriptors.h +++ b/include/usbdescriptors.h @@ -227,21 +227,6 @@ struct usb_device_descriptor { u8 bNumConfigurations; } __attribute__ ((packed)); -#if defined(CONFIG_USBD_HS) -struct usb_qualifier_descriptor { - u8 bLength; - u8 bDescriptorType; - - u16 bcdUSB; - u8 bDeviceClass; - u8 bDeviceSubClass; - u8 bDeviceProtocol; - u8 bMaxPacketSize0; - u8 bNumConfigurations; - u8 breserved; -} __attribute__ ((packed)); -#endif - struct usb_string_descriptor { u8 bLength; u8 bDescriptorType; /* 0x03 */ diff --git a/include/usbdevice.h b/include/usbdevice.h index 611cd6e4ab..80c5af0cbc 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -196,10 +196,6 @@ struct usb_bus_instance; #define USB_DT_INTERFACE 0x04 #define USB_DT_ENDPOINT 0x05 -#if defined(CONFIG_USBD_HS) -#define USB_DT_QUAL 0x06 -#endif - #define USB_DT_HID (USB_TYPE_CLASS | 0x01) #define USB_DT_REPORT (USB_TYPE_CLASS | 0x02) #define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03) @@ -279,11 +275,7 @@ struct usb_bus_instance; * USB Spec Release number */ -#if defined(CONFIG_USBD_HS) -#define USB_BCD_VERSION 0x0200 -#else #define USB_BCD_VERSION 0x0110 -#endif /* @@ -552,9 +544,6 @@ struct usb_device_instance { /* generic */ char *name; struct usb_device_descriptor *device_descriptor; /* per device descriptor */ -#if defined(CONFIG_USBD_HS) - struct usb_qualifier_descriptor *qualifier_descriptor; -#endif void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data); @@ -644,14 +633,6 @@ struct usb_string_descriptor *usbd_get_string (u8); struct usb_device_descriptor *usbd_device_device_descriptor(struct usb_device_instance *, int); -#if defined(CONFIG_USBD_HS) -/* - * is_usbd_high_speed routine needs to be defined by specific gadget driver - * It returns true if device enumerates at High speed - * Retuns false otherwise - */ -int is_usbd_high_speed(void); -#endif int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint); void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad); void usbd_tx_complete (struct usb_endpoint_instance *endpoint); From 46df77669ec4d8f04b0faf770d661f79971775a6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:50 -0500 Subject: [PATCH 217/424] nxp: Rename CONFIG_U_BOOT_HDR_SIZE to FSL_U_BOOT_HDR_SIZE This is always defined to 16K, so we move this over to include/fsl_validate.h to start with. Next, we rename this from CONFIG_ to FSL_. Coalesce the various comments around this definition to be in fsl_validate.h as well to explain the usage. Signed-off-by: Tom Rini --- board/freescale/common/fsl_chain_of_trust.c | 2 +- drivers/mtd/nand/raw/fsl_ifc_spl.c | 6 ++--- include/configs/T104xRDB.h | 8 +----- include/configs/ls1021atsn.h | 15 ------------ include/configs/ls1021atwr.h | 19 --------------- include/configs/ls1043a_common.h | 27 --------------------- include/configs/ls1046a_common.h | 13 ---------- include/configs/ls1088a_common.h | 13 ---------- include/fsl_validate.h | 7 ++++++ 9 files changed, 12 insertions(+), 98 deletions(-) diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 9ca350ed46..029d06bbf9 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -143,7 +143,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) (image_entry_noargs_t)(unsigned long)spl_image->entry_point; hdr_addr = (spl_image->entry_point + spl_image->size - - CONFIG_U_BOOT_HDR_SIZE); + FSL_U_BOOT_HDR_SIZE); spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); /* * In case of failure in validation, spl_validate_uboot would diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 3b464ce10c..60a865b566 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -278,11 +278,11 @@ void nand_boot(void) * U-Boot header is appended at end of U-boot image, so * calculate U-boot header address using U-boot header size. */ -#define CONFIG_U_BOOT_HDR_ADDR \ +#define FSL_U_BOOT_HDR_ADDR \ ((CFG_SYS_NAND_U_BOOT_START + \ CFG_SYS_NAND_U_BOOT_SIZE) - \ - CONFIG_U_BOOT_HDR_SIZE) - spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, + FSL_U_BOOT_HDR_SIZE) + spl_validate_uboot(FSL_U_BOOT_HDR_ADDR, CFG_SYS_NAND_U_BOOT_START); /* * In case of failure in validation, spl_validate_uboot would diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5bdc2105f5..7a5bf937e4 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -20,13 +20,7 @@ #ifdef CONFIG_MTD_RAW_NAND #ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ - CONFIG_U_BOOT_HDR_SIZE) +#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + (16 << 10)) #else #define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10) #endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 5612c60ae9..b15c4a238b 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -38,21 +38,6 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_NXP_ESBC */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw U-Boot image instead of FIT image. - */ -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 281b26fa2b..9b22a2db21 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -37,25 +37,6 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_NXP_ESBC */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index d0380b3373..685e7e65d1 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -41,37 +41,10 @@ /* Serial Port */ #define CFG_SYS_NS16550_CLK (get_serial_clock()) -/* SD boot SPL */ -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_NXP_ESBC */ -#endif - /* NAND SPL */ #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE - -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_NXP_ESBC */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ - #endif /* GPIO */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 250891e9e3..ae9dc0c73b 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -41,19 +41,6 @@ /* Serial Port */ #define CFG_SYS_NS16550_CLK (get_serial_clock()) -/* SD boot SPL */ -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_NXP_ESBC */ -#endif - /* NAND SPL */ #ifdef CONFIG_NAND_BOOT #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index bcba8d81c0..86c5d48c0d 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -133,17 +133,4 @@ unsigned long long get_qixis_addr(void); " 0x580e00000 \0" #endif -#ifdef CONFIG_SPL -#ifdef CONFIG_NXP_ESBC -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#endif /* ifdef CONFIG_NXP_ESBC */ - -#endif - #endif /* __LS1088_COMMON_H */ diff --git a/include/fsl_validate.h b/include/fsl_validate.h index 252d499e7b..fbcbd42496 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -280,4 +280,11 @@ int fsl_setenv_chain_of_trust(void); * Architecture header (appended to U-boot image). */ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); + +/* + * This header is appended at end of image and copied to DDR along + * with the U-Boot image and later used as part of the validation + * flow + */ +#define FSL_U_BOOT_HDR_SIZE (16 << 10) #endif From 8214b772cf213f1f02e5e33f4a5158f52d9d2c23 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 Dec 2022 16:42:51 -0500 Subject: [PATCH 218/424] T104xRDB: Remove non-TARGET_T1042D4RDB variants At this point only the TARGET_T1042D4RDB variant of this is supported in tree, so remove the remaining parts of the other platforms. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 17 ------- arch/powerpc/include/asm/fsl_secure_boot.h | 2 - board/freescale/t104xrdb/Kconfig | 4 +- board/freescale/t104xrdb/cpld.h | 2 +- board/freescale/t104xrdb/eth.c | 19 -------- board/freescale/t104xrdb/t104xrdb.c | 19 +------- include/configs/T104xRDB.h | 52 ++-------------------- 7 files changed, 7 insertions(+), 108 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 03373bf869..3275d4fa9b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -200,14 +200,6 @@ config TARGET_T1024RDB imply CMD_EEPROM imply PANIC_HANG -config TARGET_T1042RDB - bool "Support T1042RDB" - select ARCH_T1042 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select SYS_L3_SIZE_256KB - config TARGET_T1042D4RDB bool "Support T1042D4RDB" select ARCH_T1042 @@ -217,15 +209,6 @@ config TARGET_T1042D4RDB select SYS_L3_SIZE_256KB imply PANIC_HANG -config TARGET_T1042RDB_PI - bool "Support T1042RDB_PI" - select ARCH_T1042 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select SYS_L3_SIZE_256KB - imply PANIC_HANG - config TARGET_T2080QDS bool "Support T2080QDS" select ARCH_T2080 diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 09f37ec3e4..236098e718 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -17,9 +17,7 @@ #if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ - defined(CONFIG_TARGET_T1042RDB) || \ defined(CONFIG_TARGET_T1042D4RDB) || \ - defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) #undef CFG_SYS_INIT_L3_ADDR #define CFG_SYS_INIT_L3_ADDR 0xbff00000 diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig index e33d317365..e4814915e3 100644 --- a/board/freescale/t104xrdb/Kconfig +++ b/board/freescale/t104xrdb/Kconfig @@ -1,6 +1,4 @@ -if TARGET_T1040RDB || TARGET_T1040D4RDB || \ - TARGET_T1042RDB || TARGET_T1042D4RDB || \ - TARGET_T1042RDB_PI +if TARGET_T1042D4RDB config SYS_BOARD default "t104xrdb" diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 769883f946..0384202fbc 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -20,7 +20,7 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) u8 int_mask; /* 0x15 - Interrupt mask Register */ #else u8 led_ctl_status; /* 0x15 - LED control and status register */ diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index c011aa96fb..3906c8381e 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -39,25 +39,6 @@ int board_eth_init(struct bd_info *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) - case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB & T1040D4RDB only supports SGMII on - * DTSEC3 - */ - fm_info_set_phy_address(FM1_DTSEC3, - CFG_SYS_SGMII1_PHY_ADDR); - break; -#endif -#ifdef CONFIG_TARGET_T1042RDB - case PHY_INTERFACE_MODE_SGMII: - /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */ - if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i)) - fm_info_set_phy_address(i, 0); - /* T1042RDB only supports SGMII on DTSEC3 */ - fm_info_set_phy_address(FM1_DTSEC3, - CFG_SYS_SGMII1_PHY_ADDR); - break; -#endif #ifdef CONFIG_TARGET_T1042D4RDB case PHY_INTERFACE_MODE_SGMII: /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 45ebdd3000..8cec71217a 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -34,7 +34,7 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) printf("Board: %sD4RDB\n", cpu->name); #else printf("Board: %sRDB\n", cpu->name); @@ -110,23 +110,6 @@ int misc_init_r(void) CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); -#if defined(CONFIG_TARGET_T1040D4RDB) - if (hwconfig("qe-tdm")) { - CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) | - MISC_MUX_QE_TDM); - printf("QECSR : 0x%02x, mux to qe-tdm\n", - CPLD_READ(sfp_ctl_status)); - } - /* Mask all CPLD interrupt sources, except QSGMII interrupts */ - if (CPLD_READ(sw_ver) < 0x03) { - debug("CPLD SW version 0x%02x doesn't support int_mask\n", - CPLD_READ(sw_ver)); - } else { - CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & - ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2)); - } -#endif - return 0; } diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 7a5bf937e4..cfde8ecf9c 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -127,24 +127,10 @@ #define CPLD_LBMAP_RESET 0xFF #define CPLD_LBMAP_SHIFT 0x03 -#if defined(CONFIG_TARGET_T1042RDB_PI) -#define CPLD_DIU_SEL_DFP 0x80 -#elif defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) #define CPLD_DIU_SEL_DFP 0xc0 #endif -#if defined(CONFIG_TARGET_T1040D4RDB) -#define CPLD_INT_MASK_ALL 0xFF -#define CPLD_INT_MASK_THERM 0x80 -#define CPLD_INT_MASK_DVI_DFP 0x40 -#define CPLD_INT_MASK_QSGMII1 0x20 -#define CPLD_INT_MASK_QSGMII2 0x10 -#define CPLD_INT_MASK_SGMI1 0x08 -#define CPLD_INT_MASK_SGMI2 0x04 -#define CPLD_INT_MASK_TDMR1 0x02 -#define CPLD_INT_MASK_TDMR2 0x01 -#endif - #define CFG_SYS_CPLD_BASE 0xffdf0000 #define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE) #define CFG_SYS_CSPR2_EXT (0xf) @@ -266,9 +252,7 @@ #define I2C_MUX_PCA_ADDR 0x70 #define I2C_MUX_CH_DEFAULT 0x8 -#if defined(CONFIG_TARGET_T1042RDB_PI) || \ - defined(CONFIG_TARGET_T1040D4RDB) || \ - defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) /* * RTC configuration */ @@ -350,36 +334,16 @@ #endif /* CONFIG_NOBQFMAN */ #ifdef CONFIG_FMAN_ENET -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CFG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_TARGET_T1040D4RDB) -#define CFG_SYS_SGMII1_PHY_ADDR 0x01 -#elif defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) #define CFG_SYS_SGMII1_PHY_ADDR 0x02 #define CFG_SYS_SGMII2_PHY_ADDR 0x03 #define CFG_SYS_SGMII3_PHY_ADDR 0x01 #endif -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CFG_SYS_RGMII1_PHY_ADDR 0x04 -#define CFG_SYS_RGMII2_PHY_ADDR 0x05 -#else #define CFG_SYS_RGMII1_PHY_ADDR 0x01 #define CFG_SYS_RGMII2_PHY_ADDR 0x02 #endif -/* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#ifdef CONFIG_TARGET_T1040RDB -#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 -#else -#define CFG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CFG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c -#endif -#endif -#endif - /* * Miscellaneous configurable options */ @@ -402,15 +366,7 @@ #define __USB_PHY_TYPE utmi #define RAMDISKFILE "t104xrdb/ramdisk.uboot" -#ifdef CONFIG_TARGET_T1040RDB -#define FDTFILE "t1040rdb/t1040rdb.dtb" -#elif defined(CONFIG_TARGET_T1042RDB_PI) -#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" -#elif defined(CONFIG_TARGET_T1042RDB) -#define FDTFILE "t1042rdb/t1042rdb.dtb" -#elif defined(CONFIG_TARGET_T1040D4RDB) -#define FDTFILE "t1042rdb/t1040d4rdb.dtb" -#elif defined(CONFIG_TARGET_T1042D4RDB) +#if defined(CONFIG_TARGET_T1042D4RDB) #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif From b9d1f88b3aae10c15c0cd767acccc1026f5ef6d8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:26 -0500 Subject: [PATCH 219/424] exynos: Rework legacy PWM usage The way that the timer support is currently done for exynos/nexell platforms relies on the legacy PWM infrastructure, and that needs to be updated. However, we really cannot safely undef CONFIG_DM_PWM to build the timer.c file without warnings. For now, rename the relevant legacy functions to be prefixed with s5p_ and add prototypes to the arch pwm.h files. Cc: Minkyu Kang Cc: Jaehoon Chung Cc: Dzmitry Sankouski Cc: Stefan Bosch Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/cpu/armv7/s5p-common/pwm.c | 11 +++++------ arch/arm/cpu/armv7/s5p-common/timer.c | 10 +++------- arch/arm/mach-exynos/include/mach/pwm.h | 5 +++++ arch/arm/mach-nexell/include/mach/pwm.h | 5 +++++ arch/arm/mach-s5pc1xx/include/mach/pwm.h | 5 +++++ board/friendlyarm/nanopi2/board.c | 4 ++-- board/friendlyarm/nanopi2/onewire.c | 4 ++-- 7 files changed, 27 insertions(+), 17 deletions(-) diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index aef2e5574b..5068327d3c 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -7,12 +7,11 @@ #include #include -#include #include #include #include -int pwm_enable(int pwm_id) +int s5p_pwm_enable(int pwm_id) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -30,7 +29,7 @@ int pwm_enable(int pwm_id) return 0; } -void pwm_disable(int pwm_id) +void s5p_pwm_disable(int pwm_id) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -92,7 +91,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) #define NS_IN_SEC 1000000000UL -int pwm_config(int pwm_id, int duty_ns, int period_ns) +int s5p_pwm_config(int pwm_id, int duty_ns, int period_ns) { const struct s5p_timer *pwm = #if defined(CONFIG_ARCH_NEXELL) @@ -157,7 +156,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) return 0; } -int pwm_init(int pwm_id, int div, int invert) +int s5p_pwm_init(int pwm_id, int div, int invert) { u32 val; const struct s5p_timer *pwm = @@ -219,7 +218,7 @@ int pwm_init(int pwm_id, int div, int invert) val |= TCON_INVERTER(pwm_id); writel(val, &pwm->tcon); - pwm_enable(pwm_id); + s5p_pwm_enable(pwm_id); return 0; } diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index 8533d04878..f4a045e2f0 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -16,10 +16,6 @@ #include #include -/* Use the old PWM interface for now */ -#undef CONFIG_DM_PWM -#include - DECLARE_GLOBAL_DATA_PTR; unsigned long get_current_tick(void); @@ -49,9 +45,9 @@ static unsigned long timer_get_us_down(void) int timer_init(void) { /* PWM Timer 4 */ - pwm_init(4, MUX_DIV_4, 0); - pwm_config(4, 100000, 100000); - pwm_enable(4); + s5p_pwm_init(4, MUX_DIV_4, 0); + s5p_pwm_config(4, 100000, 100000); + s5p_pwm_enable(4); /* Use this as the current monotonic time in us */ gd->arch.timer_reset_value = 0; diff --git a/arch/arm/mach-exynos/include/mach/pwm.h b/arch/arm/mach-exynos/include/mach/pwm.h index 417fc15551..17372492d5 100644 --- a/arch/arm/mach-exynos/include/mach/pwm.h +++ b/arch/arm/mach-exynos/include/mach/pwm.h @@ -49,6 +49,11 @@ struct s5p_timer { unsigned int tcnto4; unsigned int tintcstat; }; + +int s5p_pwm_init (int pwm_id, int div, int invert); +int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns); +int s5p_pwm_enable (int pwm_id); +void s5p_pwm_disable (int pwm_id); #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-nexell/include/mach/pwm.h b/arch/arm/mach-nexell/include/mach/pwm.h index 08a287d308..1e12058dd5 100644 --- a/arch/arm/mach-nexell/include/mach/pwm.h +++ b/arch/arm/mach-nexell/include/mach/pwm.h @@ -49,6 +49,11 @@ struct s5p_timer { unsigned int tcnto4; unsigned int tintcstat; }; + +int s5p_pwm_init (int pwm_id, int div, int invert); +int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns); +int s5p_pwm_enable (int pwm_id); +void s5p_pwm_disable (int pwm_id); #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/mach-s5pc1xx/include/mach/pwm.h b/arch/arm/mach-s5pc1xx/include/mach/pwm.h index 1a531beddc..6d53e52f64 100644 --- a/arch/arm/mach-s5pc1xx/include/mach/pwm.h +++ b/arch/arm/mach-s5pc1xx/include/mach/pwm.h @@ -49,6 +49,11 @@ struct s5p_timer { unsigned int tcnto4; unsigned int tintcstat; }; + +int s5p_pwm_init (int pwm_id, int div, int invert); +int s5p_pwm_config (int pwm_id, int duty_ns, int period_ns); +int s5p_pwm_enable (int pwm_id); +void s5p_pwm_disable (int pwm_id); #endif /* __ASSEMBLY__ */ #endif diff --git a/board/friendlyarm/nanopi2/board.c b/board/friendlyarm/nanopi2/board.c index 954197282e..393c5a447d 100644 --- a/board/friendlyarm/nanopi2/board.c +++ b/board/friendlyarm/nanopi2/board.c @@ -80,9 +80,9 @@ static void bd_backlight_on(void) #elif defined(BACKLIGHT_CH) /* pwm backlight ON: HIGH, ON: LOW */ - pwm_init(BACKLIGHT_CH, + s5p_pwm_init(BACKLIGHT_CH, BACKLIGHT_DIV, BACKLIGHT_INV); - pwm_config(BACKLIGHT_CH, + s5p_pwm_config(BACKLIGHT_CH, TO_DUTY_NS(BACKLIGHT_DUTY, BACKLIGHT_HZ), TO_PERIOD_NS(BACKLIGHT_HZ)); #endif diff --git a/board/friendlyarm/nanopi2/onewire.c b/board/friendlyarm/nanopi2/onewire.c index fb356639be..56f0f2dfce 100644 --- a/board/friendlyarm/nanopi2/onewire.c +++ b/board/friendlyarm/nanopi2/onewire.c @@ -9,8 +9,8 @@ #include #include #include +#include #include -#include #include @@ -102,7 +102,7 @@ static int onewire_init_timer(void) /* range: 1080~1970 */ period_ns -= 1525; - return pwm_config(PWM_CH, period_ns >> 1, period_ns); + return s5p_pwm_config(PWM_CH, period_ns >> 1, period_ns); } static void wait_one_tick(void) From 957848882c88722da8a3a2e6fba77c2cf113b17e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:27 -0500 Subject: [PATCH 220/424] rk32xx: Use standard TPL linker script As of 2f41ade79e59 ("linker: Modify linker scripts to be more generic") we can use the same linker script for SPL and TPL and not have to make use of #undef tricks. Remove these last remnants. Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- arch/arm/mach-rockchip/rk3288/Kconfig | 3 --- arch/arm/mach-rockchip/u-boot-tpl.lds | 12 ------------ configs/evb-rk3229_defconfig | 1 - 3 files changed, 16 deletions(-) delete mode 100644 arch/arm/mach-rockchip/u-boot-tpl.lds diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 1be2b58521..ea94ad1142 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -168,9 +168,6 @@ config SPL_LIBGENERIC_SUPPORT config SPL_SERIAL default y -config TPL_LDSCRIPT - default "arch/arm/mach-rockchip/u-boot-tpl.lds" - config TPL_STACK default 0xff718000 diff --git a/arch/arm/mach-rockchip/u-boot-tpl.lds b/arch/arm/mach-rockchip/u-boot-tpl.lds deleted file mode 100644 index f5a89721ce..0000000000 --- a/arch/arm/mach-rockchip/u-boot-tpl.lds +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019 Rockchip Electronic Co.,Ltd - */ - -#undef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE - -#undef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE - -#include "../cpu/u-boot-spl.lds" diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 33202e48fe..8b4da5b3e7 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -11,7 +11,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" CONFIG_SPL_TEXT_BASE=0x60000000 CONFIG_ROCKCHIP_RK322X=y CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 -CONFIG_TPL_LDSCRIPT="arch/arm/mach-rockchip/u-boot-tpl.lds" CONFIG_TARGET_EVB_RK3229=y CONFIG_SPL_STACK_R_ADDR=0x60600000 CONFIG_DEBUG_UART_BASE=0x11030000 From 7ee2f977b7913ac7c1eda11051fe7401ab73ab89 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:28 -0500 Subject: [PATCH 221/424] Convert CONFIG_NEVER_ASSERT_ODT_TO_CPU to Kconfig This converts the following to Kconfig: CONFIG_NEVER_ASSERT_ODT_TO_CPU Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/Kconfig | 3 +++ include/configs/MPC837XERDB.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 563f52c5fd..b695c7e4d8 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -200,6 +200,9 @@ config FSL_SERDES bool "SerDes initialization" depends on !MPC83XX_SERDES +config NEVER_ASSERT_ODT_TO_CPU + bool "Never assert ODT to internal IOs" + source "board/freescale/mpc837xerdb/Kconfig" source "board/gdsys/mpc8308/Kconfig" diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 7b932eb389..e0ac9338d3 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -55,8 +55,6 @@ #define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) -#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - /* * Manually set up DDR parameters */ From f00f676af6bcae0702efbac45b88c1b8b686d400 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:29 -0500 Subject: [PATCH 222/424] Convert CONFIG_SYS_FPGA_CHECK_BUSY to Kconfig This converts the following to Kconfig: CONFIG_SYS_FPGA_CHECK_BUSY Signed-off-by: Tom Rini --- drivers/fpga/Kconfig | 4 ++++ drivers/fpga/spartan2.c | 2 -- drivers/fpga/spartan3.c | 2 -- drivers/fpga/virtex2.c | 7 ++----- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 813d6a836d..11b742eeeb 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -96,6 +96,10 @@ config FPGA_VIRTEX2 Enable Virtex-II FPGA driver for loading in BIT format. This driver also supports many newer Xilinx FPGA families. +config SYS_FPGA_CHECK_BUSY + bool "Perform busy check during load from FPGA" + depends on FPGA_SPARTAN2 || FPGA_SPARTAN3 || FPGA_VIRTEX2 + config FPGA_ZYNQPL bool "Enable Xilinx FPGA for Zynq" depends on ARCH_ZYNQ diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 57a4532f73..68971d9347 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -10,8 +10,6 @@ #include #include /* Spartan-II device family */ -#undef CONFIG_SYS_FPGA_CHECK_BUSY - /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). * If there is a need to operate slower, define CONFIG_FPGA_DELAY in diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index fdec89bb81..1d5073cb59 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -15,8 +15,6 @@ #include #include /* Spartan-II device family */ -#undef CONFIG_SYS_FPGA_CHECK_BUSY - /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). * If there is a need to operate slower, define CONFIG_FPGA_DELAY in diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 8871deaea6..ed2a4163f6 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -21,14 +21,11 @@ #include /* - * If the SelectMap interface can be overrun by the processor, define - * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board + * If the SelectMap interface can be overrun by the processor, enable + * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CONFIG_FPGA_DELAY in the board * configuration file and add board-specific support for checking BUSY status. * By default, assume that the SelectMap interface cannot be overrun. */ -#ifndef CONFIG_SYS_FPGA_CHECK_BUSY -#undef CONFIG_SYS_FPGA_CHECK_BUSY -#endif #ifndef CONFIG_FPGA_DELAY #define CONFIG_FPGA_DELAY() From 2c065aeeee8c4033f41836eafef0d949c94bf769 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:30 -0500 Subject: [PATCH 223/424] mtd: ubi: Finish moving configuration to Kconfig We have some unused and undefined symbols to remove references to, so do that. Move the final things that we do set (or need to keep unset) to Kconfig instead. Signed-off-by: Tom Rini --- drivers/mtd/ubi/Kconfig | 12 ++++++++++++ include/ubi_uboot.h | 22 ---------------------- 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index 67a3cf1d7a..5783d36c04 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -20,6 +20,18 @@ config MTD_UBI if MTD_UBI +config MTD_UBI_BLOCK + def_bool n + +config MTD_UBI_MODULE + def_bool y + help + ubi_init() disables returning error codes when built into the Linux + kernel so that it doesn't hang the Linux kernel boot process. Since + the U-Boot driver code depends on getting valid error codes from this + function we just tell the UBI layer that we are building as a module + (which only enables the additional error reporting). + config MTD_UBI_WL_THRESHOLD int "UBI wear-leveling threshold" default 4096 diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 0770228cd8..6da348eb62 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -34,28 +34,6 @@ #include -/* configurable */ -#define CONFIG_MTD_UBI_BEB_RESERVE 1 - -/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */ -#undef CONFIG_MTD_UBI_DEBUG -#undef CONFIG_MTD_UBI_DEBUG_PARANOID -#undef CONFIG_MTD_UBI_DEBUG_MSG -#undef CONFIG_MTD_UBI_DEBUG_MSG_EBA -#undef CONFIG_MTD_UBI_DEBUG_MSG_WL -#undef CONFIG_MTD_UBI_DEBUG_MSG_IO -#undef CONFIG_MTD_UBI_DEBUG_MSG_BLD - -#undef CONFIG_MTD_UBI_BLOCK - -/* ubi_init() disables returning error codes when built into the Linux - * kernel so that it doesn't hang the Linux kernel boot process. Since - * the U-Boot driver code depends on getting valid error codes from this - * function we just tell the UBI layer that we are building as a module - * (which only enables the additional error reporting). - */ -#define CONFIG_MTD_UBI_MODULE - /* build.c */ #define get_device(...) #define put_device(...) From 991bc169518a000c8d559bac2c2e857bd1969a40 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:31 -0500 Subject: [PATCH 224/424] atmel_nand: Remove undef during SPL_BUILD We cannot disable features in SPL in this manner, remove the undef here. Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/atmel_nand.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 9fbb0b57cf..b7e473c598 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -38,10 +38,6 @@ #ifdef CONFIG_ATMEL_NAND_HW_PMECC -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_SYS_NAND_ONFI_DETECTION -#endif - struct atmel_nand_host { struct pmecc_regs __iomem *pmecc; struct pmecc_errloc_regs __iomem *pmerrloc; From dc2c451a94e11e0b5ac006fd603b746632734d5c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:32 -0500 Subject: [PATCH 225/424] valgrind: Rework test for unsupported platforms Change things so that on an unsupported platform we will #error rather than undef the feature. Signed-off-by: Tom Rini --- include/valgrind/valgrind.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/valgrind/valgrind.h b/include/valgrind/valgrind.h index e59a7fde32..5d4fa5f43b 100644 --- a/include/valgrind/valgrind.h +++ b/include/valgrind/valgrind.h @@ -121,7 +121,9 @@ #else /* If we're not compiling for our target platform, don't generate any inline asms. */ -# undef CONFIG_VALGRIND +# if IS_ENABLED(CONFIG_VALGRIND) +# error "Unsupported platform for valgrind" +# endif #endif From d5c4b8b0631a1da03e67fdeb1b5bf4a637a33c20 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:33 -0500 Subject: [PATCH 226/424] log: Remove some places where we redefine LOGLEVEL We cannot redefine a CONFIG value per file in this manner. Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/octeontx_bch.c | 5 ----- drivers/mtd/nand/raw/octeontx_nand.c | 5 ----- test/log/pr_cont_test.c | 3 --- 3 files changed, 13 deletions(-) diff --git a/drivers/mtd/nand/raw/octeontx_bch.c b/drivers/mtd/nand/raw/octeontx_bch.c index c1d721cabf..fc16b77416 100644 --- a/drivers/mtd/nand/raw/octeontx_bch.c +++ b/drivers/mtd/nand/raw/octeontx_bch.c @@ -27,11 +27,6 @@ #include #include "octeontx_bch.h" -#ifdef DEBUG -# undef CONFIG_LOGLEVEL -# define CONFIG_LOGLEVEL 8 -#endif - LIST_HEAD(octeontx_bch_devices); static unsigned int num_vfs = BCH_NR_VF; static void *bch_pf; diff --git a/drivers/mtd/nand/raw/octeontx_nand.c b/drivers/mtd/nand/raw/octeontx_nand.c index b338b204f3..1ffadad9ca 100644 --- a/drivers/mtd/nand/raw/octeontx_nand.c +++ b/drivers/mtd/nand/raw/octeontx_nand.c @@ -31,11 +31,6 @@ #include #include "octeontx_bch.h" -#ifdef DEBUG -# undef CONFIG_LOGLEVEL -# define CONFIG_LOGLEVEL 8 -#endif - /* * The NDF_CMD queue takes commands between 16 - 128 bit. * All commands must be 16 bit aligned and are little endian. diff --git a/test/log/pr_cont_test.c b/test/log/pr_cont_test.c index 6abddf7a11..df4520d280 100644 --- a/test/log/pr_cont_test.c +++ b/test/log/pr_cont_test.c @@ -16,9 +16,6 @@ #define BUFFSIZE 64 -#undef CONFIG_LOGLEVEL -#define CONFIG_LOGLEVEL 4 - DECLARE_GLOBAL_DATA_PTR; static int log_test_pr_cont(struct unit_test_state *uts) From 218ce3695bfd02f048443f888137e134dbcfcbfc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:34 -0500 Subject: [PATCH 227/424] global: Remove undef CONFIG_... for unused values We have a number of places that undef CONFIG_... while we never reference CONFIG_... in the first place. Remove these lines. Signed-off-by: Tom Rini --- common/cli_hush.c | 1 - drivers/ddr/marvell/axp/ddr3_axp_config.h | 2 -- include/configs/P1010RDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/s5p4418_nanopi2.h | 2 -- 5 files changed, 7 deletions(-) diff --git a/common/cli_hush.c b/common/cli_hush.c index 1467ff81b3..a80b84756b 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -112,7 +112,6 @@ #define applet_name "hush" #include "standalone.h" #define hush_main main -#undef CONFIG_FEATURE_SH_FANCY_PROMPT #define BB_BANNER #endif #endif diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index ab09e72623..04bb4ed8f3 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -59,12 +59,10 @@ /* Marvell boards specific configurations */ #if defined(DB_78X60_PCAC) -#undef CONFIG_SPD_EEPROM #define STATIC_TRAINING #endif #if defined(DB_78X60_AMC) -#undef CONFIG_SPD_EEPROM #undef DRAM_ECC #define DRAM_ECC 1 #endif diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 2267a7a9c8..afb602c5bc 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -309,7 +309,6 @@ extern unsigned long get_sdram_size(void); #endif /* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CFG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c05904a813..74627b2e63 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -302,7 +302,6 @@ * open - index 2 * shorted - index 1 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CFG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index e071d4da5e..b4b2dbd038 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -66,8 +66,6 @@ /*----------------------------------------------------------------------- * High Level System Configuration */ -/* Not used: not need IRQ/FIQ stuff */ -#undef CONFIG_USE_IRQ /* decrementer freq: 1ms ticks */ /*----------------------------------------------------------------------- From 137de2cf0dc62d574de7363dd4ac7cc1f4848fcf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 6 Dec 2022 13:51:21 -0500 Subject: [PATCH 228/424] rsa-verify: Rework host check for CONFIG_RSA_VERIFY_WITH_PKEY While we do not want to use CONFIG_RSA_VERIFY_WITH_PKEY on the host, we cannot undef the symbol in this manner. As this ends up being a test within another function we can use !tools_build() as a test here. Cc: AKASHI Takahiro Cc: Simon Glass Signed-off-by: Tom Rini Reviewed-by: Simon Glass --- lib/rsa/rsa-verify.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c index 9605c37639..2f3b344039 100644 --- a/lib/rsa/rsa-verify.c +++ b/lib/rsa/rsa-verify.c @@ -23,18 +23,6 @@ #include #include -#ifndef __UBOOT__ -/* - * NOTE: - * Since host tools, like mkimage, make use of openssl library for - * RSA encryption, rsa_verify_with_pkey()/rsa_gen_key_prop() are - * of no use and should not be compiled in. - * So just turn off CONFIG_RSA_VERIFY_WITH_PKEY. - */ - -#undef CONFIG_RSA_VERIFY_WITH_PKEY -#endif - /* Default public exponent for backward compatibility */ #define RSA_DEFAULT_PUBEXP 65537 @@ -506,7 +494,13 @@ int rsa_verify_hash(struct image_sign_info *info, { int ret = -EACCES; - if (CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY) && !info->fdt_blob) { + /* + * Since host tools, like mkimage, make use of openssl library for + * RSA encryption, rsa_verify_with_pkey()/rsa_gen_key_prop() are + * of no use and should not be compiled in. + */ + if (!tools_build() && CONFIG_IS_ENABLED(RSA_VERIFY_WITH_PKEY) && + !info->fdt_blob) { /* don't rely on fdt properties */ ret = rsa_verify_with_pkey(info, hash, sig, sig_len); if (ret) From 04501ecca26d0f3ad10065775c1bddda02a02db0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:36 -0500 Subject: [PATCH 229/424] global: Migrate CONFIG_ARM_GIC_BASE_ADDRESS to CFG Perform a simple rename of CONFIG_ARM_GIC_BASE_ADDRESS to CFG_ARM_GIC_BASE_ADDRESS Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- arch/arm/cpu/armv7/virt-v7.c | 4 ++-- include/configs/arndale.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 5ee6577c2c..a303039ba5 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -112,8 +112,8 @@ ENTRY(_do_nonsec_entry) ENDPROC(_do_nonsec_entry) .macro get_cbar_addr addr -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#ifdef CFG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CFG_ARM_GIC_BASE_ADDRESS #else mrc p15, 4, \addr, c15, c0, 0 @ read CBAR bfc \addr, #0, #15 @ clear reserved bits diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 5ffeca13d9..c82b215b6f 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -26,8 +26,8 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; +#ifdef CFG_ARM_GIC_BASE_ADDRESS + return CFG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 7a244769e3..8acc525b11 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -19,6 +19,6 @@ #define CONFIG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ -#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 +#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000 #endif /* __CONFIG_H */ From 207972acfc19bd64f390744c2636b9218f41673d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:37 -0500 Subject: [PATCH 230/424] global: Migrate CONFIG_BOARDDIR to CFG Perform a simple rename of CONFIG_BOARDDIR to CFG_BOARDDIR Signed-off-by: Tom Rini --- arch/sh/cpu/u-boot.lds | 2 +- doc/README.kwbimage | 2 +- scripts/Makefile.autoconf | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index d360eea7eb..c31deecec6 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -35,7 +35,7 @@ SECTIONS .text : { KEEP(*/start.o (.text)) - KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) + KEEP(CFG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) KEEP(*(.spiboot2.text)) . = ALIGN(8192); #ifdef CONFIG_ENV_IS_IN_FLASH diff --git a/doc/README.kwbimage b/doc/README.kwbimage index 762b2e3acb..a1d247c32d 100644 --- a/doc/README.kwbimage +++ b/doc/README.kwbimage @@ -42,7 +42,7 @@ Board specific configuration file specifications: kwbimage.cfg. The name can be set as part of the full path to the file using CONFIG_SYS_KWD_CONFIG (probably in include/configs/.h). The path should look like: - $(CONFIG_BOARDDIR)/.cfg + $(CFG_BOARDDIR)/.cfg 2. This file can have empty lines and lines starting with "#" as first character to put comments 3. This file can have configuration command lines as mentioned below, diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 5a4a148955..f5f5e4a4d5 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -112,7 +112,7 @@ vpl/include/autoconf.mk: vpl/u-boot.cfg # Prior to Kconfig, it was generated by mkconfig. Now it is created here. define filechk_config_h (echo "/* Automatically generated - do not edit */"; \ - echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ + echo \#define CFG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ echo \#include \; \ echo \#include \; \ echo \#include \; \ From b8089c6d688dd031d07274fc07678a2005b466e9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:38 -0500 Subject: [PATCH 231/424] global: Migrate CONFIG_DFU_ALT et al to CFG Perform simple renames of: CONFIG_DFU_ALT to CFG_DFU_ALT CONFIG_DFU_ALT_BOOT_EMMC to CFG_DFU_ALT_BOOT_EMMC CONFIG_DFU_ALT_BOOT_SD to CFG_DFU_ALT_BOOT_SD CONFIG_DFU_ALT_SYSTEM to CFG_DFU_ALT_SYSTEM CONFIG_DFU_ENV_SETTINGS to CFG_DFU_ENV_SETTINGS Signed-off-by: Tom Rini --- board/samsung/common/exynos5-dt.c | 4 ++-- board/samsung/odroid/odroid.c | 4 ++-- include/configs/mx7dsabresd.h | 4 ++-- include/configs/odroid.h | 8 ++++---- include/configs/odroid_xu3.h | 8 ++++---- include/configs/pico-imx6.h | 4 ++-- include/configs/pico-imx6ul.h | 4 ++-- include/configs/pico-imx7d.h | 4 ++-- include/configs/s5p_goni.h | 4 ++-- include/configs/trats.h | 4 ++-- include/configs/trats2.h | 4 ++-- include/configs/warp7.h | 4 ++-- 12 files changed, 28 insertions(+), 28 deletions(-) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 0d77a57f80..cde77d79a0 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -179,9 +179,9 @@ char *get_dfu_alt_boot(char *interface, char *devstr) return NULL; if (IS_SD(mmc)) - alt_boot = CONFIG_DFU_ALT_BOOT_SD; + alt_boot = CFG_DFU_ALT_BOOT_SD; else - alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; + alt_boot = CFG_DFU_ALT_BOOT_EMMC; return alt_boot; } diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 35e4cee74f..39a60e4ad2 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -94,8 +94,8 @@ char *get_dfu_alt_boot(char *interface, char *devstr) if (mmc_init(mmc)) return NULL; - alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD : - CONFIG_DFU_ALT_BOOT_EMMC; + alt_boot = IS_SD(mmc) ? CFG_DFU_ALT_BOOT_SD : + CFG_DFU_ALT_BOOT_EMMC; return alt_boot; } diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index bd70b62bd2..e56b6101af 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -44,7 +44,7 @@ "initrd_high=0xffffffff\0" \ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=image raw 0 0x800000;"\ "u-boot raw 0 0x4000;"\ "bootimg part 0 1;"\ @@ -53,7 +53,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index f252b34943..e2331e45cd 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -27,7 +27,7 @@ #define PARTS_BOOT "boot" #define PARTS_ROOT "platform" -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ "Image.itb fat 0 1;" \ @@ -39,13 +39,13 @@ #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) -#define CONFIG_DFU_ALT_BOOT_EMMC \ +#define CFG_DFU_ALT_BOOT_EMMC \ "u-boot raw 0x3e 0x800 mmcpart 1;" \ "bl1 raw 0x0 0x1e mmcpart 1;" \ "bl2 raw 0x1e 0x1d mmcpart 1;" \ "tzsw raw 0x83e 0x138 mmcpart 1\0" -#define CONFIG_DFU_ALT_BOOT_SD \ +#define CFG_DFU_ALT_BOOT_SD \ "u-boot raw 0x3f 0x800;" \ "bl1 raw 0x1 0x1e;" \ "bl2 raw 0x1f 0x1d;" \ @@ -132,7 +132,7 @@ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \ - "dfu_alt_system="CONFIG_DFU_ALT \ + "dfu_alt_system="CFG_DFU_ALT \ "dfu_alt_info=Please reset the board\0" \ "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ "consoleoff=set console console=ram; save; reset\0" \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index bf63a4de07..e4a81499a7 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -20,7 +20,7 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 #define DFU_MANIFEST_POLL_TIMEOUT 25000 -#define CONFIG_DFU_ALT_SYSTEM \ +#define CFG_DFU_ALT_SYSTEM \ "uImage fat 0 1;" \ "zImage fat 0 1;" \ "Image.itb fat 0 1;" \ @@ -34,14 +34,14 @@ "boot part 0 1;" \ "root part 0 2\0" -#define CONFIG_DFU_ALT_BOOT_EMMC \ +#define CFG_DFU_ALT_BOOT_EMMC \ "u-boot raw 0x3e 0x800 mmcpart 1;" \ "bl1 raw 0x0 0x1e mmcpart 1;" \ "bl2 raw 0x1e 0x1d mmcpart 1;" \ "tzsw raw 0x83e 0x200 mmcpart 1;" \ "params.bin raw 0x1880 0x20\0" -#define CONFIG_DFU_ALT_BOOT_SD \ +#define CFG_DFU_ALT_BOOT_SD \ "u-boot raw 0x3f 0x800;" \ "bl1 raw 0x1 0x1e;" \ "bl2 raw 0x1f 0x1d;" \ @@ -75,7 +75,7 @@ "mmcrootdev=0\0" \ "mmcbootpart=1\0" \ "mmcrootpart=2\0" \ - "dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \ + "dfu_alt_system="CFG_DFU_ALT_SYSTEM \ "dfu_alt_info=Autoset by THOR/DFU command run.\0" #endif /* __CONFIG_H */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 6d7873daa0..719b701440 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -21,7 +21,7 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ "u-boot raw 0x8a 0x1000;" \ @@ -47,7 +47,7 @@ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "finduuid=part uuid mmc 0:1 uuid\0" \ "findfdt="\ "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index faf11d5a72..36f648f634 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -28,7 +28,7 @@ #define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ "u-boot raw 0x8a 0x400;" \ @@ -63,7 +63,7 @@ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "mmcautodetect=yes\0" \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "findfdt=" \ "if test $fdtfile = ask ; then " \ "bootmenu -1; fi;" \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 83907b06eb..5819215104 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -15,7 +15,7 @@ /* MMC Config */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ "spl raw 0x2 0x400;" \ "u-boot raw 0x8a 0x1000;" \ @@ -67,7 +67,7 @@ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "findfdt=" \ "if test $fdtfile = ask ; then " \ "bootmenu -1; fi;" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index da83db1f68..555bedb93d 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -35,7 +35,7 @@ #define PARTS_CSC "csc" #define PARTS_UMS "ums" -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "u-boot raw 0x80 0x400;" \ "uImage ext4 0 2;" \ "exynos3-goni.dtb ext4 0 2;" \ @@ -102,7 +102,7 @@ "ubiblock=8\0" \ "ubi=enabled\0" \ "opts=always_resume=1\0" \ - "dfu_alt_info=" CONFIG_DFU_ALT "\0" + "dfu_alt_info=" CFG_DFU_ALT "\0" /* Goni has 3 banks of DRAM, but swap the bank */ #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ diff --git a/include/configs/trats.h b/include/configs/trats.h index ec18842bbe..3eac66539d 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -39,7 +39,7 @@ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "u-boot raw 0x80 0x400;" \ "/uImage ext4 0 2;" \ "/modem.bin ext4 0 2;" \ @@ -98,7 +98,7 @@ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ "partitions=" PARTS_DEFAULT \ - "dfu_alt_info=" CONFIG_DFU_ALT \ + "dfu_alt_info=" CFG_DFU_ALT \ "spladdr=0x40000100\0" \ "splsize=0x200\0" \ "splfile=falcon.bin\0" \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 4d39b4005b..18fca09a38 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -40,7 +40,7 @@ "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ -#define CONFIG_DFU_ALT \ +#define CFG_DFU_ALT \ "u-boot raw 0x80 0x800;" \ "/uImage ext4 0 2;" \ "/modem.bin ext4 0 2;" \ @@ -86,7 +86,7 @@ "mmcrootpart=5\0" \ "opts=always_resume=1\0" \ "partitions=" PARTS_DEFAULT \ - "dfu_alt_info=" CONFIG_DFU_ALT \ + "dfu_alt_info=" CFG_DFU_ALT \ "uartpath=ap\0" \ "usbpath=ap\0" \ "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a985c6f28f..188180da54 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -16,7 +16,7 @@ /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_DFU_ENV_SETTINGS \ +#define CFG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ /* When booting with FIT specify the node entry containing boot.scr */ @@ -27,7 +27,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ + CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "bootscr_fitimage_name=bootscr\0" \ "script_signed=boot.scr.imx-signed\0" \ From 42119de8b51ca703d5e6c489b59c99aa3db7ab30 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:39 -0500 Subject: [PATCH 232/424] global: Migrate CONFIG_DW_WDT_CLOCK_KHZ to CFG Perform a simple rename of CONFIG_DW_WDT_CLOCK_KHZ to CFG_DW_WDT_CLOCK_KHZ Signed-off-by: Tom Rini --- drivers/watchdog/designware_wdt.c | 2 +- include/configs/socfpga_common.h | 2 +- include/configs/socfpga_soc64_common.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c index f8df1916b5..447a22d3b3 100644 --- a/drivers/watchdog/designware_wdt.c +++ b/drivers/watchdog/designware_wdt.c @@ -132,7 +132,7 @@ static int designware_wdt_probe(struct udevice *dev) goto err; } #else - priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ; + priv->clk_khz = CFG_DW_WDT_CLOCK_KHZ; #endif if (CONFIG_IS_ENABLED(DM_RESET) && diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 088cd4d4f7..d0f5331d45 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -64,7 +64,7 @@ /* * L4 Watchdog */ -#define CONFIG_DW_WDT_CLOCK_KHZ 25000 +#define CFG_DW_WDT_CLOCK_KHZ 25000 /* * NAND Support diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 47089f312d..df3927297b 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -90,10 +90,10 @@ #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); -#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) +#define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) #endif #else -#define CONFIG_DW_WDT_CLOCK_KHZ 100000 +#define CFG_DW_WDT_CLOCK_KHZ 100000 #endif /* From acf29d8ccb56e1c366a8c360cfa7cc8f44d4d281 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:40 -0500 Subject: [PATCH 233/424] global: Migrate CONFIG_ENV_FLAGS_LIST_STATIC to CFG Perform a simple rename of CONFIG_ENV_FLAGS_LIST_STATIC to CFG_ENV_FLAGS_LIST_STATIC Signed-off-by: Tom Rini --- README | 6 +++--- include/configs/aristainetos2.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/env_flags.h | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/README b/README index 2944646665..e19aa1f722 100644 --- a/README +++ b/README @@ -1066,7 +1066,7 @@ The following options need to be configured: The same can be accomplished in a more flexible way for any variable by configuring the type of access to allow for those variables in the ".flags" variable - or define CONFIG_ENV_FLAGS_LIST_STATIC. + or define CFG_ENV_FLAGS_LIST_STATIC. - Protected RAM: CONFIG_PRAM @@ -1405,7 +1405,7 @@ Configuration Settings: Use buffered writes to flash. - CONFIG_ENV_FLAGS_LIST_DEFAULT -- CONFIG_ENV_FLAGS_LIST_STATIC +- CFG_ENV_FLAGS_LIST_STATIC Enable validation of the values given to environment variables when calling env set. Variables can be restricted to only decimal, hexadecimal, or boolean. If CONFIG_CMD_NET is also defined, @@ -1436,7 +1436,7 @@ Configuration Settings: Define this to a list (string) to define the ".flags" environment variable in the default or embedded environment. - - CONFIG_ENV_FLAGS_LIST_STATIC + - CFG_ENV_FLAGS_LIST_STATIC Define this to a list (string) to define validation that should be done if an entry is not found in the ".flags" environment variable. To override a setting in the static diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8541354571..ff213a41b8 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -418,7 +418,7 @@ /* UBI support */ -#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ +#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" #endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 99da081cda..392f97050a 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -45,7 +45,7 @@ "save_env=env save; env save\0" \ "altbootcmd=run handle_ustate; run switch_bootset; run save_env; run bootcmd\0" -#define CONFIG_ENV_FLAGS_LIST_STATIC \ +#define CFG_ENV_FLAGS_LIST_STATIC \ "bootset:bw," \ "clone_pending:bw," \ "endurance_test:bw," \ diff --git a/include/env_flags.h b/include/env_flags.h index 718d72773c..6bd574c2bd 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -35,8 +35,8 @@ enum env_flags_varaccess { #define ENV_FLAGS_VARTYPE_LOC 0 #define ENV_FLAGS_VARACCESS_LOC 1 -#ifndef CONFIG_ENV_FLAGS_LIST_STATIC -#define CONFIG_ENV_FLAGS_LIST_STATIC "" +#ifndef CFG_ENV_FLAGS_LIST_STATIC +#define CFG_ENV_FLAGS_LIST_STATIC "" #endif #ifdef CONFIG_NET @@ -87,7 +87,7 @@ enum env_flags_varaccess { NET_FLAGS \ NET6_FLAGS \ SERIAL_FLAGS \ - CONFIG_ENV_FLAGS_LIST_STATIC + CFG_ENV_FLAGS_LIST_STATIC #ifdef CONFIG_CMD_ENV_FLAGS /* From 7c5b8c7c643be917230c1b75da4267d76f484443 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:41 -0500 Subject: [PATCH 234/424] global: Migrate CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS to CFG_ENV_SETTINGS_BUTTONS_AND_LEDS Signed-off-by: Tom Rini --- include/configs/draco.h | 4 ++-- include/configs/etamin.h | 4 ++-- include/configs/pxm2.h | 4 ++-- include/configs/rastaban.h | 4 ++-- include/configs/thuban.h | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/configs/draco.h b/include/configs/draco.h index 4869008da4..d1c7abe1b3 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -19,7 +19,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "led0=103,1,0\0" \ "led1=64,0,1\0" @@ -34,7 +34,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 811c7cb961..8bfc9c9f62 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -56,7 +56,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ /* In dfu mode keep led1 on */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "button_dfu1=87\0" \ "led0=3,0,1\0" \ @@ -134,7 +134,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 586a7edcbb..eafa6ae9a9 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -18,7 +18,7 @@ #define DDR_IOCTRL_VAL 0x18b #define DDR_PLL_FREQ 266 -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=59\0" \ "led0=117,0,1\0" \ @@ -34,7 +34,7 @@ "nand_img_size=0x500000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "splashpos=m,m\0" \ CONFIG_ENV_SETTINGS_V1 \ CONFIG_ENV_SETTINGS_NAND_V1 \ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 49cd11c17b..2e002faf2e 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -21,7 +21,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ /* In dfu mode keep led1 on */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "button_dfu1=87\0" \ "led0=3,0,1\0" \ @@ -44,7 +44,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 696306e465..25c5a8ccd2 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -19,7 +19,7 @@ #define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ #define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ +#define CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "button_dfu0=27\0" \ "led0=103,1,0\0" \ "led1=64,0,1\0" @@ -37,7 +37,7 @@ "nand_img_size=0x400000\0" \ "optargs=\0" \ "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ + CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ CONFIG_ENV_SETTINGS_NAND_V2 From fe5a5393bdf4cd2acad715b1ffa80f37c304b843 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:42 -0500 Subject: [PATCH 235/424] global: Migrate CONFIG_ENV_SETTINGS_NAND_V1 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_NAND_V1 to CFG_ENV_SETTINGS_NAND_V1 Signed-off-by: Tom Rini --- include/configs/pxm2.h | 2 +- include/configs/rut.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index eafa6ae9a9..c6a01270a5 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -37,7 +37,7 @@ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "splashpos=m,m\0" \ CONFIG_ENV_SETTINGS_V1 \ - CONFIG_ENV_SETTINGS_NAND_V1 \ + CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ "mmc_root_fs_type=ext4 rootwait\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index ac48372b6c..f51771f9ca 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -34,7 +34,7 @@ "splashpos=m,m\0" \ "optargs=fixrtc --no-log consoleblank=0 \0" \ CONFIG_ENV_SETTINGS_V1 \ - CONFIG_ENV_SETTINGS_NAND_V1 \ + CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ "mmc_root_fs_type=ext4 rootwait\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 406a179842..296ac34da6 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -196,7 +196,7 @@ "kernel_b part 0 8;" \ "rootfs partubi 0 10" -#define CONFIG_ENV_SETTINGS_NAND_V1 \ +#define CFG_ENV_SETTINGS_NAND_V1 \ "nand_active_ubi_vol=rootfs_a\0" \ "nand_active_ubi_vol_A=rootfs_a\0" \ "nand_active_ubi_vol_B=rootfs_b\0" \ From 4a609781d514456980654079407dad0a801ff485 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:43 -0500 Subject: [PATCH 236/424] global: Migrate CONFIG_ENV_SETTINGS_NAND_V2 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_NAND_V2 to CFG_ENV_SETTINGS_NAND_V2 Signed-off-by: Tom Rini --- include/configs/draco.h | 2 +- include/configs/etamin.h | 6 +++--- include/configs/rastaban.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/thuban.h | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/configs/draco.h b/include/configs/draco.h index d1c7abe1b3..5b0daec11a 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -36,6 +36,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 8bfc9c9f62..c68d0df02a 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -93,8 +93,8 @@ "u-boot.env1 mtddev;" \ "rootfs mtddevubi" \ -#undef CONFIG_ENV_SETTINGS_NAND_V2 -#define CONFIG_ENV_SETTINGS_NAND_V2 \ +#undef CFG_ENV_SETTINGS_NAND_V2 +#define CFG_ENV_SETTINGS_NAND_V2 \ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ @@ -136,6 +136,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_ETAMIN_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 2e002faf2e..f3435b2b8c 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -46,6 +46,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 296ac34da6..7e9a55ec61 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -273,7 +273,7 @@ "u-boot.env1 part 0 7;" \ "rootfs partubi 0 9" \ -#define CONFIG_ENV_SETTINGS_NAND_V2 \ +#define CFG_ENV_SETTINGS_NAND_V2 \ "nand_active_ubi_vol=rootfs_a\0" \ "rootfs_name=rootfs\0" \ "kernel_name=uImage\0"\ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 25c5a8ccd2..960b42dffd 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -39,6 +39,6 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 + CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_THUBAN_H */ From 10bb746127f2bf8d7b4475dd7528b10712e07d8e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:44 -0500 Subject: [PATCH 237/424] global: Migrate CONFIG_ENV_SETTINGS_V1 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_V1 to CFG_ENV_SETTINGS_V1 Signed-off-by: Tom Rini --- include/configs/pxm2.h | 2 +- include/configs/rut.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index c6a01270a5..48f49906b8 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -36,7 +36,7 @@ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ "splashpos=m,m\0" \ - CONFIG_ENV_SETTINGS_V1 \ + CFG_ENV_SETTINGS_V1 \ CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ diff --git a/include/configs/rut.h b/include/configs/rut.h index f51771f9ca..b07d0c5060 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -33,7 +33,7 @@ "nand_img_size=0x500000\0" \ "splashpos=m,m\0" \ "optargs=fixrtc --no-log consoleblank=0 \0" \ - CONFIG_ENV_SETTINGS_V1 \ + CFG_ENV_SETTINGS_V1 \ CFG_ENV_SETTINGS_NAND_V1 \ "mmc_dev=0\0" \ "mmc_root=/dev/mmcblk0p2 rw\0" \ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 7e9a55ec61..4f277f08a4 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -229,7 +229,7 @@ "${nand_img_size}; bootm ${kloadaddr}\0" \ COMMON_ENV_NAND_CMDS -#define CONFIG_ENV_SETTINGS_V1 \ +#define CFG_ENV_SETTINGS_V1 \ COMMON_ENV_SETTINGS \ "net_args=run bootargs_defaults;" \ "mtdparts default;" \ From d6ae6c7076b3f34b7e40b3570ccc7bdf8a0937f7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:45 -0500 Subject: [PATCH 238/424] global: Migrate CONFIG_ENV_SETTINGS_V2 to CFG Perform a simple rename of CONFIG_ENV_SETTINGS_V2 to CFG_ENV_SETTINGS_V2 Signed-off-by: Tom Rini --- include/configs/draco.h | 2 +- include/configs/etamin.h | 2 +- include/configs/rastaban.h | 2 +- include/configs/siemens-am33x-common.h | 2 +- include/configs/thuban.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/draco.h b/include/configs/draco.h index 5b0daec11a..ab3cf10d77 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -35,7 +35,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index c68d0df02a..57f619f55f 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -135,7 +135,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_ETAMIN_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index f3435b2b8c..59d56d6662 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -45,7 +45,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 4f277f08a4..7def657bcd 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -306,7 +306,7 @@ "bootm ${kloadaddr} - ${loadaddr}\0" \ COMMON_ENV_NAND_CMDS -#define CONFIG_ENV_SETTINGS_V2 \ +#define CFG_ENV_SETTINGS_V2 \ COMMON_ENV_SETTINGS \ "net_args=run bootargs_defaults;" \ "mtdparts default;" \ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 960b42dffd..c8b27263e8 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -38,7 +38,7 @@ "optargs=\0" \ "preboot=draco_led 0\0" \ CFG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ + CFG_ENV_SETTINGS_V2 \ CFG_ENV_SETTINGS_NAND_V2 #endif /* ! __CONFIG_THUBAN_H */ From 3673a47b55c67359dc883bdf7be372d32ae6dbe6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:46 -0500 Subject: [PATCH 239/424] global: Migrate CONFIG_ENV_SROM_BANK to CFG Perform a simple rename of CONFIG_ENV_SROM_BANK to CFG_ENV_SROM_BANK Signed-off-by: Tom Rini --- board/samsung/smdkc100/smdkc100.c | 6 +++--- board/samsung/smdkv310/smdkv310.c | 6 +++--- include/configs/exynos5-common.h | 2 +- include/configs/smdkc100.h | 2 +- include/configs/smdkv310.h | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index b944e44c1a..4f46911b0b 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -25,16 +25,16 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - gpio_cfg_pin(S5PC100_GPIO_K00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(S5PC100_GPIO_K00 + CFG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ - smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bw_conf = SMC_DATA16_WIDTH(CFG_ENV_SROM_BANK); smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4) | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0); /* Select and configure the SROMC bank */ - s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + s5p_config_sromc(CFG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); } int board_init(void) diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index bb61ba1f81..47483a26a6 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -24,17 +24,17 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); + gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CFG_ENV_SROM_BANK, S5P_GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ - smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); + smc_bw_conf = SROMC_DATA16_WIDTH(CFG_ENV_SROM_BANK); smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F) | SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F) | SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F) | SROMC_BC_PMC(0x0F); /* Select and configure the SROMC bank */ - s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); + s5p_config_sromc(CFG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf); } int board_init(void) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 8e277ce7ff..43ea34db7b 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -48,7 +48,7 @@ /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 1 +#define CFG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ /* Enable Time Command */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ffa1a1fcb0..ccb7ec38d0 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -94,7 +94,7 @@ * Ethernet Contoller driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ +#define CFG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ #endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 38de1fa984..f0604195ad 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -36,7 +36,7 @@ /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 1 +#define CFG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ #endif /* __CONFIG_H */ From ef2e1745da9151083c197d6077d0a14498eec13b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:47 -0500 Subject: [PATCH 240/424] global: Migrate CONFIG_ENV_TOTAL_SIZE to CFG Perform a simple rename of CONFIG_ENV_TOTAL_SIZE to CFG_ENV_TOTAL_SIZE Signed-off-by: Tom Rini --- board/keymile/kmcent2/kmcent2.env | 6 +++--- include/configs/kmcent2.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/keymile/kmcent2/kmcent2.env b/board/keymile/kmcent2/kmcent2.env index 7c8f8306c5..6b676a4ceb 100644 --- a/board/keymile/kmcent2/kmcent2.env +++ b/board/keymile/kmcent2/kmcent2.env @@ -10,9 +10,9 @@ hostname=kmcent2 hwconfig=fsl_ddr:ctlr_intlv=cacheline netdev=eth2 -newenv=protect off ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && - erase ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE && - protect on ENV_DEL_ADDR +CONFIG_ENV_TOTAL_SIZE +newenv=protect off ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE && + erase ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE && + protect on ENV_DEL_ADDR +CFG_ENV_TOTAL_SIZE set_fdthigh=true uimage=uImage diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 80bff4b893..a4b6a6e555 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -127,7 +127,7 @@ #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS /* Environment in parallel NOR-Flash */ -#define CONFIG_ENV_TOTAL_SIZE 0x040000 +#define CFG_ENV_TOTAL_SIZE 0x040000 #define ENV_DEL_ADDR 0xebf00000 /*direct for newenv*/ /* From b9abcb8c9fc196ef502eb8b2909bbb92a109deab Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:48 -0500 Subject: [PATCH 241/424] global: Migrate CONFIG_ET1100_BASE to CFG Perform a simple rename of CONFIG_ET1100_BASE to CFG_ET1100_BASE Signed-off-by: Tom Rini --- board/esd/meesc/meesc.c | 2 +- include/configs/meesc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 21f4ba98b5..9e36210422 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -163,7 +163,7 @@ int checkboard(void) u_char hw_type; /* hardware type */ /* read the "Type" register of the ET1100 controller */ - hw_type = readb(CONFIG_ET1100_BASE); + hw_type = readb(CFG_ET1100_BASE); switch (hw_type) { case 0x11: diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d190e4b503..38da55c70b 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -60,6 +60,6 @@ #endif /* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 +#define CFG_ET1100_BASE 0x70000000 #endif From fb55ac2cfe017b5f83d97f25e3ed2ceaa9946405 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:49 -0500 Subject: [PATCH 242/424] global: Migrate CONFIG_ETHBASE to CFG Perform a simple rename of CONFIG_ETHBASE to CFG_ETHBASE Signed-off-by: Tom Rini --- board/cadence/xtfpga/xtfpga.c | 2 +- include/configs/xtfpga.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c index f38f5564a0..8e4081b4c6 100644 --- a/board/cadence/xtfpga/xtfpga.c +++ b/board/cadence/xtfpga/xtfpga.c @@ -89,7 +89,7 @@ int misc_init_r(void) char *s = env_get("ethaddr"); if (s == 0) { unsigned int x; - char s[] = __stringify(CONFIG_ETHBASE); + char s[] = __stringify(CFG_ETHBASE); x = (*(volatile u32 *)CFG_SYS_FPGAREG_DIPSW) & FPGAREG_MAC_MASK; sprintf(&s[15], "%02x", x); diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index e0189c58f0..83a0539d8f 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -120,7 +120,7 @@ /* Ethernet Driver Info */ /*======================*/ -#define CONFIG_ETHBASE 00:50:C2:13:6f:00 +#define CFG_ETHBASE 00:50:C2:13:6f:00 #define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000) #define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) From 0613c36a7a5973d58a50b764ee647099e80cc97d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:50 -0500 Subject: [PATCH 243/424] global: Migrate CONFIG_EXTRA_ENV_SETTINGS to CFG Perform a simple rename of CONFIG_EXTRA_ENV_SETTINGS to CFG_EXTRA_ENV_SETTINGS Signed-off-by: Tom Rini --- README | 4 ++-- doc/README.fsl-ddr | 4 ++-- doc/README.link-local | 2 +- doc/arch/x86.rst | 4 ++-- doc/develop/devicetree/control.rst | 2 +- doc/develop/distro.rst | 2 +- doc/usage/environment.rst | 2 +- env/Kconfig | 4 ++-- include/configs/M5208EVBE.h | 2 +- include/configs/M5235EVB.h | 2 +- include/configs/M5253DEMO.h | 2 +- include/configs/M5272C3.h | 2 +- include/configs/M5275EVB.h | 2 +- include/configs/M5282EVB.h | 2 +- include/configs/M53017EVB.h | 2 +- include/configs/M5329EVB.h | 2 +- include/configs/M5373EVB.h | 2 +- include/configs/MCR3000.h | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/alt.h | 2 +- include/configs/am335x_evm.h | 2 +- include/configs/am335x_guardian.h | 2 +- include/configs/am335x_igep003x.h | 2 +- include/configs/am335x_shc.h | 2 +- include/configs/am335x_sl50.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/am62ax_evm.h | 2 +- include/configs/am62x_evm.h | 2 +- include/configs/am64x_evm.h | 2 +- include/configs/am65x_evm.h | 2 +- include/configs/amcore.h | 2 +- include/configs/apalis-imx8.h | 2 +- include/configs/apalis_imx6.h | 2 +- include/configs/apple.h | 2 +- include/configs/arbel.h | 2 +- include/configs/aristainetos2.h | 2 +- include/configs/astro_mcf5373l.h | 2 +- include/configs/at91sam9263ek.h | 2 +- include/configs/at91sam9n12ek.h | 2 +- include/configs/ax25-ae350.h | 2 +- include/configs/axs10x.h | 2 +- include/configs/baltos.h | 2 +- include/configs/bcm_ns3.h | 2 +- include/configs/bcmstb.h | 2 +- include/configs/beacon-rzg2m.h | 4 ++-- include/configs/bitmain_antminer_s9.h | 2 +- include/configs/bk4r1.h | 2 +- include/configs/brppt1.h | 2 +- include/configs/brppt2.h | 2 +- include/configs/brsmarc1.h | 2 +- include/configs/brxre1.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/chiliboard.h | 2 +- include/configs/cl-som-imx7.h | 4 ++-- include/configs/clearfog.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/cm_t43.h | 2 +- include/configs/colibri-imx6ull.h | 2 +- include/configs/colibri-imx8x.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/colibri_imx7.h | 2 +- include/configs/colibri_vf.h | 2 +- include/configs/conga-qeval20-qa3-e3845.h | 4 ++-- include/configs/controlcenterdc.h | 2 +- include/configs/crs3xx-98dx3236.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/db-88f6820-amc.h | 2 +- include/configs/db-88f6820-gp.h | 2 +- include/configs/db-xc3-24g4xg.h | 2 +- include/configs/devkit3250.h | 2 +- include/configs/devkit8000.h | 2 +- include/configs/dfi-bt700.h | 4 ++-- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/dns325.h | 2 +- include/configs/dockstar.h | 2 +- include/configs/draco.h | 2 +- include/configs/dragonboard410c.h | 2 +- include/configs/dragonboard820c.h | 2 +- include/configs/dragonboard845c.h | 2 +- include/configs/dreamplug.h | 2 +- include/configs/ds109.h | 2 +- include/configs/ds414.h | 2 +- include/configs/durian.h | 2 +- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/emsdp.h | 2 +- include/configs/etamin.h | 2 +- include/configs/evb_ast2500.h | 2 +- include/configs/evb_ast2600.h | 2 +- include/configs/evb_rv1108.h | 4 ++-- include/configs/exynos5-common.h | 2 +- include/configs/exynos7420-common.h | 2 +- include/configs/exynos78x0-common.h | 2 +- include/configs/gazerbeam.h | 2 +- include/configs/ge_b1x5v2.h | 2 +- include/configs/ge_bx50v3.h | 2 +- include/configs/goflexhome.h | 2 +- include/configs/gose.h | 2 +- include/configs/guruplug.h | 2 +- include/configs/helios4.h | 2 +- include/configs/highbank.h | 2 +- include/configs/hikey.h | 2 +- include/configs/hikey960.h | 2 +- include/configs/hsdk-4xd.h | 2 +- include/configs/hsdk.h | 2 +- include/configs/ib62x0.h | 2 +- include/configs/iconnect.h | 2 +- include/configs/imx6-engicam.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6q-bosch-acc.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 4 ++-- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm-mx8menlo.h | 4 ++-- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_beacon.h | 2 +- include/configs/imx8mn_bsh_smm_s2.h | 2 +- include/configs/imx8mn_bsh_smm_s2pro.h | 2 +- include/configs/imx8mn_evk.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mn_venice.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mp_venice.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/imxrt1050-evk.h | 2 +- include/configs/iot2050.h | 2 +- include/configs/j721e_evm.h | 2 +- include/configs/j721s2_evm.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/kp_imx53.h | 2 +- include/configs/kp_imx6q_tpc.h | 2 +- include/configs/lacie_kw.h | 2 +- include/configs/lager.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/librem5.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/ls1012a2g5rdb.h | 4 ++-- include/configs/ls1012a_common.h | 2 +- include/configs/ls1012afrdm.h | 4 ++-- include/configs/ls1012afrwy.h | 4 ++-- include/configs/ls1012aqds.h | 4 ++-- include/configs/ls1012ardb.h | 4 ++-- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 4 ++-- include/configs/ls1021atsn.h | 2 +- include/configs/ls1021atwr.h | 4 ++-- include/configs/ls1028aqds.h | 4 ++-- include/configs/ls1028ardb.h | 4 ++-- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls1088aqds.h | 20 ++++++++++---------- include/configs/ls1088ardb.h | 6 +++--- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080aqds.h | 10 +++++----- include/configs/ls2080ardb.h | 6 +++--- include/configs/lsxl.h | 2 +- include/configs/lx2160aqds.h | 2 +- include/configs/lx2160ardb.h | 2 +- include/configs/lx2162aqds.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/meson64.h | 4 ++-- include/configs/meson64_android.h | 2 +- include/configs/microblaze-generic.h | 4 ++-- include/configs/microchip_mpfs_icicle.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mt7623.h | 2 +- include/configs/mt8183.h | 2 +- include/configs/mt8512.h | 2 +- include/configs/mt8516.h | 2 +- include/configs/mt8518.h | 2 +- include/configs/mvebu_alleycat-5.h | 2 +- include/configs/mvebu_armada-37xx.h | 2 +- include/configs/mvebu_armada-8k.h | 2 +- include/configs/mx23_olinuxino.h | 2 +- include/configs/mx23evk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx53ppd.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mx7ulp_evk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nas220.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/nsa310s.h | 2 +- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/octeontx2_common.h | 2 +- include/configs/octeontx_common.h | 4 ++-- include/configs/odroid.h | 2 +- include/configs/odroid_xu3.h | 4 ++-- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_igep00x0.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/openpiton-riscv64.h | 2 +- include/configs/openrd.h | 2 +- include/configs/origen.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pcm052.h | 2 +- include/configs/pcm058.h | 2 +- include/configs/pdu001.h | 2 +- include/configs/phycore_am335x_r2.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/pic32mzdask.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/pm9261.h | 2 +- include/configs/pm9263.h | 2 +- include/configs/pogo_e02.h | 2 +- include/configs/pogo_v4.h | 2 +- include/configs/poleg.h | 2 +- include/configs/pomelo.h | 2 +- include/configs/poplar.h | 2 +- include/configs/porter.h | 2 +- include/configs/presidio_asic.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/pxm2.h | 2 +- include/configs/qcs404-evb.h | 2 +- include/configs/qemu-arm.h | 2 +- include/configs/qemu-riscv.h | 2 +- include/configs/rastaban.h | 2 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/rk3036_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rpi.h | 2 +- include/configs/rut.h | 2 +- include/configs/rv1108_common.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/s5p_goni.h | 2 +- include/configs/s5pc210_universal.h | 2 +- include/configs/sdm845.h | 2 +- include/configs/sheevaplug.h | 2 +- include/configs/sifive-unleashed.h | 2 +- include/configs/sifive-unmatched.h | 2 +- include/configs/silk.h | 2 +- include/configs/sipeed-maix.h | 4 ++-- include/configs/slimbootloader.h | 6 +++--- include/configs/smartweb.h | 2 +- include/configs/smdkc100.h | 2 +- include/configs/smegw01.h | 2 +- include/configs/snapper9g45.h | 2 +- include/configs/sniper.h | 2 +- include/configs/socfpga_chameleonv3.h | 2 +- include/configs/socfpga_common.h | 4 ++-- include/configs/socfpga_dbm_soc1.h | 2 +- include/configs/socfpga_mcvevk.h | 2 +- include/configs/socfpga_n5x_socdk.h | 4 ++-- include/configs/socfpga_soc64_common.h | 2 +- include/configs/socfpga_vining_fpga.h | 2 +- include/configs/socrates.h | 2 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/stemmy.h | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32f429-discovery.h | 2 +- include/configs/stm32f429-evaluation.h | 2 +- include/configs/stm32f469-discovery.h | 2 +- include/configs/stm32f746-disco.h | 2 +- include/configs/stm32h743-disco.h | 2 +- include/configs/stm32h743-eval.h | 2 +- include/configs/stm32h750-art-pi.h | 2 +- include/configs/stm32mp13_common.h | 2 +- include/configs/stm32mp15_common.h | 2 +- include/configs/stm32mp15_dh_dhsom.h | 2 +- include/configs/stm32mp15_st_common.h | 6 +++--- include/configs/stmark2.h | 2 +- include/configs/stout.h | 2 +- include/configs/sunxi-common.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/syzygy_hub.h | 2 +- include/configs/taurus.h | 2 +- include/configs/tbs2910.h | 2 +- include/configs/tegra-common-post.h | 2 +- include/configs/ten64.h | 4 ++-- include/configs/theadorable-x86-common.h | 4 ++-- include/configs/theadorable.h | 2 +- include/configs/thuban.h | 2 +- include/configs/thunderx_88xx.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/ti_omap5_common.h | 2 +- include/configs/topic_miami.h | 4 ++-- include/configs/total_compute.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/trats.h | 2 +- include/configs/trats2.h | 2 +- include/configs/turris_mox.h | 2 +- include/configs/turris_omnia.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/uniphier.h | 2 +- include/configs/usb_a9263.h | 2 +- include/configs/usbarmory.h | 2 +- include/configs/vcoreiii.h | 2 +- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- include/configs/vexpress_aemv8.h | 2 +- include/configs/vexpress_common.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vinco.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/warp7.h | 2 +- include/configs/x530.h | 2 +- include/configs/x86-common.h | 2 +- include/configs/xea.h | 2 +- include/configs/xenguest_arm64.h | 6 +++--- include/configs/xilinx_versal.h | 4 ++-- include/configs/xilinx_versal_mini.h | 4 ++-- include/configs/xilinx_versal_net.h | 4 ++-- include/configs/xilinx_versal_net_mini.h | 4 ++-- include/configs/xilinx_zynqmp.h | 8 ++++---- include/configs/xilinx_zynqmp_mini.h | 4 ++-- include/configs/xilinx_zynqmp_r5.h | 2 +- include/configs/xpress.h | 2 +- include/configs/zynq-common.h | 4 ++-- include/configs/zynq_cse.h | 2 +- include/env_default.h | 4 ++-- 378 files changed, 441 insertions(+), 441 deletions(-) diff --git a/README b/README index e19aa1f722..a278825bbc 100644 --- a/README +++ b/README @@ -1124,7 +1124,7 @@ The following options need to be configured: symbols. - Default Environment: - CONFIG_EXTRA_ENV_SETTINGS + CFG_EXTRA_ENV_SETTINGS Define this to contain any number of null terminated strings (variable = value pairs) that will be part of @@ -1133,7 +1133,7 @@ The following options need to be configured: For example, place something like this in your board's config file: - #define CONFIG_EXTRA_ENV_SETTINGS \ + #define CFG_EXTRA_ENV_SETTINGS \ "myvar1=value1\0" \ "myvar2=value2\0" diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 10e63f3be1..f44bb2aa25 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -56,8 +56,8 @@ Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting - under "CONFIG_EXTRA_ENV_SETTINGS", like: - #define CONFIG_EXTRA_ENV_SETTINGS \ + under "CFG_EXTRA_ENV_SETTINGS", like: + #define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... diff --git a/doc/README.link-local b/doc/README.link-local index 148b4987f2..ec2ef940e4 100644 --- a/doc/README.link-local +++ b/doc/README.link-local @@ -51,7 +51,7 @@ by env variables. It depends on CONFIG_CMD_LINK_LOCAL, CONFIG_CMD_DHCP, and CONFIG_BOOTP_MAY_FAIL. If both fail or are disabled, static settings are used. -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ipconfigcmd=if test \\\"$dhcpenabled\\\" -ne 0;" \ "then " \ "dhcpfail=0;dhcp || dhcpfail=1;" \ diff --git a/doc/arch/x86.rst b/doc/arch/x86.rst index 634387ac09..725a1ae586 100644 --- a/doc/arch/x86.rst +++ b/doc/arch/x86.rst @@ -355,8 +355,8 @@ environment variables if you add this to minnowmax.h: "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \ "run boot" - #undef CONFIG_EXTRA_ENV_SETTINGS - #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}" + #undef CFG_EXTRA_ENV_SETTINGS + #define CFG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}" and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:: diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index c71570d64b..0b3b32be1b 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -135,7 +135,7 @@ control the boot process of Linux with bootm/bootz commands. To use this, put something like this in your board header file:: - #define CONFIG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" + #define CFG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" Build: diff --git a/doc/develop/distro.rst b/doc/develop/distro.rst index bc72aa951e..8016acad09 100644 --- a/doc/develop/distro.rst +++ b/doc/develop/distro.rst @@ -214,7 +214,7 @@ Required Environment Variables The U-Boot "syslinux" and "pxe boot" commands require a number of environment variables be set. Default values for these variables are often hard-coded into -CONFIG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that +CFG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that the user doesn't have to configure them. fdt_addr: diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 83f210d2d0..2c44e5da6a 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -89,7 +89,7 @@ Old-style C environment Traditionally, the default environment is created in `include/env_default.h`, and can be augmented by various `CONFIG` defines. See that file for details. In -particular you can define `CONFIG_EXTRA_ENV_SETTINGS` in your board file +particular you can define `CFG_EXTRA_ENV_SETTINGS` in your board file to add environment variables. Board maintainers are encouraged to migrate to the text-based environment as it diff --git a/env/Kconfig b/env/Kconfig index 7ca992aa1d..f73f0b8bc0 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -19,7 +19,7 @@ config ENV_SOURCE_FILE If this CONFIG is empty, U-Boot uses CONFIG SYS_BOARD as a default, if the file board///.env exists. Otherwise the environment is assumed to come from the ad-hoc - CONFIG_EXTRA_ENV_SETTINGS #define + CFG_EXTRA_ENV_SETTINGS #define config SAVEENV def_bool y if CMD_SAVEENV @@ -657,7 +657,7 @@ config USE_DEFAULT_ENV_FILE help Normally, the default environment is automatically generated based on the settings of various CONFIG_* options, as well - as the CONFIG_EXTRA_ENV_SETTINGS. By selecting this option, + as the CFG_EXTRA_ENV_SETTINGS. By selecting this option, you can instead define the entire default environment in an external file. diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index e14650fe0d..f7aba6e417 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -17,7 +17,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 220524bfae..049516edf4 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -27,7 +27,7 @@ /* this must be included AFTER the definition of CONFIG COMMANDS (if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index bc156df20d..a6349fc086 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -20,7 +20,7 @@ env/embedded.o(.text*); #ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_EXTRA_ENV_SETTINGS \ +# define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ "loadaddr=10000\0" \ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 6aae584afd..33c2fc0870 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -27,7 +27,7 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text); -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 41974cff41..607c5dee2f 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -38,7 +38,7 @@ #define CFG_SYS_I2C_PINMUX_CLR (0xFFF0) #define CFG_SYS_I2C_PINMUX_SET (0x000F) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "uboot=u-boot.bin\0" \ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 7cfe7a2da3..31699a40b6 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -27,7 +27,7 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*); -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index ac2bd0b224..b6d82c730c 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -30,7 +30,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index a86a117fd8..d74a636fd7 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -22,7 +22,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=40010000\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index b2ad03cc3c..fa6f2d23e7 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -24,7 +24,7 @@ /* I2C */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index f8368823aa..c6929c1b98 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -9,7 +9,7 @@ /* High Level Configuration Options */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "sdram_type=SDRAM\0" \ "flash_type=AM29LV160DB\0" \ "loadaddr=0x400000\0" \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index e0ac9338d3..fad161597e 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -195,7 +195,7 @@ #define FDTFILE "mpc8379_rdb.dtb" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ "tftpflash=tftp $loadaddr $uboot;" \ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 1e3ba6de6e..6f3e298a24 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -291,7 +291,7 @@ * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index afb602c5bc..b57e8638ab 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -371,7 +371,7 @@ extern unsigned long get_sdram_size(void); * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 1a157a7da0..6e755fc0a8 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -304,7 +304,7 @@ #define __USB_PHY_TYPE utmi -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4794c5a84d..063b864f9f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -430,7 +430,7 @@ "fdtfile=t1023rdb/t1023rdb.dtb\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ARCH_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index cfde8ecf9c..9d04d30a53 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -370,7 +370,7 @@ #define FDTFILE "t1042rdb/t1042d4rdb.dtb" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 4b6bdaa344..7f332cf2e3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -413,7 +413,7 @@ #define __USB_PHY_TYPE utmi -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index fab40f792a..d6dd9c07b7 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -379,7 +379,7 @@ #define __USB_PHY_TYPE utmi -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 41565f284c..22cbf92efb 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -368,7 +368,7 @@ #define CTRL_INTLV_PREFERED cacheline #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ "bank_intlv=auto;" \ diff --git a/include/configs/alt.h b/include/configs/alt.h index f277400169..29f4d06b7f 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -30,7 +30,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "usb_pgood_delay=2000\0" diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 755f7fae3e..1f473b5a15 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -78,7 +78,7 @@ #ifndef CONFIG_SPL_BUILD #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=undefined\0" \ "finduuid=part uuid mmc 0:2 uuid\0" \ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h index a5b83b0c25..a8fa61c7e5 100644 --- a/include/configs/am335x_guardian.h +++ b/include/configs/am335x_guardian.h @@ -45,7 +45,7 @@ "main_pcba_aux_3=0\0" \ "main_pcba_aux_4=0\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AM335XX_BOARD_FDTFILE \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV \ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h index abd868c145..e2beaf2718 100644 --- a/include/configs/am335x_igep003x.h +++ b/include/configs/am335x_igep003x.h @@ -20,7 +20,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "bootdir=/boot\0" \ "bootfile=zImage\0" \ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h index 70645edcb1..ee6f62275a 100644 --- a/include/configs/am335x_shc.h +++ b/include/configs/am335x_shc.h @@ -21,7 +21,7 @@ #define V_SCLK (V_OSCK) #ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "kloadaddr=0x84000000\0" \ "fdtaddr=0x85000000\0" \ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h index 342a068c85..f3d3d18c05 100644 --- a/include/configs/am335x_sl50.h +++ b/include/configs/am335x_sl50.h @@ -30,7 +30,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AM335XX_BOARD_FDTFILE \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index c57a0ddc21..b75c648388 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -38,7 +38,7 @@ #endif /* CONFIG_MTD_RAW_NAND */ /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ "fdtfile=am3517-evm.dtb\0" \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 7659c1cc06..3a6ffd9de0 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -66,7 +66,7 @@ #ifndef CONFIG_SPL_BUILD #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=undefined\0" \ "finduuid=part uuid mmc 0:2 uuid\0" \ diff --git a/include/configs/am62ax_evm.h b/include/configs/am62ax_evm.h index 5406c39350..1bd900df7a 100644 --- a/include/configs/am62ax_evm.h +++ b/include/configs/am62ax_evm.h @@ -56,7 +56,7 @@ "partitions=" PARTS_DEFAULT /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM62A7_BOARD_SETTINGS \ diff --git a/include/configs/am62x_evm.h b/include/configs/am62x_evm.h index 57f3f37908..809d89119c 100644 --- a/include/configs/am62x_evm.h +++ b/include/configs/am62x_evm.h @@ -55,7 +55,7 @@ "partitions=" PARTS_DEFAULT /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM625_BOARD_SETTINGS \ diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 25c71f00a2..26a7f2521e 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -95,7 +95,7 @@ DFU_ALT_INFO_OSPI /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ EXTRA_ENV_AM642_BOARD_SETTINGS \ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 0307426e4a..33dd6cfdfa 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -88,7 +88,7 @@ #endif /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/amcore.h b/include/configs/amcore.h index ca29346fe6..648d30a5b2 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -10,7 +10,7 @@ #define CFG_SYS_UART_PORT 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade_uboot=loady; " \ "protect off 0xffc00000 0xffc1ffff; " \ "erase 0xffc00000 0xffc1ffff; " \ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index aa3dcf4a88..73d8d245a9 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -31,7 +31,7 @@ #define BOOTENV_RUN_NET_USB_START "" /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 07587c7609..d46159076f 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -62,7 +62,7 @@ "ramdisk_addr_r=0x18400000\0" \ "scriptaddr=0x18280000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ diff --git a/include/configs/apple.h b/include/configs/apple.h index b06660add4..fe7d11bcdb 100644 --- a/include/configs/apple.h +++ b/include/configs/apple.h @@ -27,7 +27,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_DEVICE_SETTINGS \ BOOTENV diff --git a/include/configs/arbel.h b/include/configs/arbel.h index 60758b0ca0..8e27fb52a1 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -12,7 +12,7 @@ #define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Default environemnt variables */ -#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ +#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index ff213a41b8..a6e9d2bb65 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -94,7 +94,7 @@ "done\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "disable_giga=yes\0" \ "usb_pgood_delay=2000\0" \ "nor_bootdelay=-2\0" \ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index 6aef3bd86f..65224324fb 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -71,7 +71,7 @@ * u-boot: 'set' command */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loaderversion=11\0" \ "card_id="__stringify(ASTRO_ID)"\0" \ "alterafile=0\0" \ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index afdb74785f..4101440ff5 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -36,7 +36,7 @@ /* Address and size of Primary Environment Sector */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ "update=" \ "protect off ${monitor_base} +${filesize};" \ diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 0f9e2cfb58..c59d4bb38c 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -28,7 +28,7 @@ #define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index d70f038230..b566ecf296 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -82,7 +82,7 @@ func(RAM, ram, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x00080000\0" \ "pxefile_addr_r=0x01f00000\0" \ "scriptaddr=0x01f00000\0" \ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h index 04dc50b1cb..a82dfc9029 100644 --- a/include/configs/axs10x.h +++ b/include/configs/axs10x.h @@ -39,7 +39,7 @@ /* * Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade=if mmc rescan && " \ "fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ diff --git a/include/configs/baltos.h b/include/configs/baltos.h index 6f6552e6dc..e7946389ef 100644 --- a/include/configs/baltos.h +++ b/include/configs/baltos.h @@ -49,7 +49,7 @@ #define NANDARGS "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "boot_fdt=try\0" \ "bootpart=0:2\0" \ diff --git a/include/configs/bcm_ns3.h b/include/configs/bcm_ns3.h index fc176dc201..47de4bc201 100644 --- a/include/configs/bcm_ns3.h +++ b/include/configs/bcm_ns3.h @@ -793,7 +793,7 @@ QSPI_FLASH \ FLASH_IMAGES -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ARCH_ENV_SETTINGS #endif /* __BCM_NS3_H */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 57360b60ca..d1de3561af 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -131,7 +131,7 @@ extern phys_addr_t prior_stage_fdt_address; /* * Enable in-place RFS with this initrd_high setting. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0" \ "initrd_high=0xffffffff\0" \ "fdt_high=0xffffffff\0" diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h index 2713b15843..65c01835cc 100644 --- a/include/configs/beacon-rzg2m.h +++ b/include/configs/beacon-rzg2m.h @@ -8,9 +8,9 @@ #include "rcar-gen3-common.h" -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "usb_pgood_delay=2000\0" \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h index 556bfa08eb..3662668c6a 100644 --- a/include/configs/bitmain_antminer_s9.h +++ b/include/configs/bitmain_antminer_s9.h @@ -9,7 +9,7 @@ #define CFG_SYS_SDRAM_BASE 0x00000000 #define CFG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "pxefile_addr_r=0x2000000\0" \ "scriptaddr=0x3000000\0" \ "kernel_addr_r=0x2000000\0" \ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index 0842a4a8f5..5df8d03c70 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -57,7 +57,7 @@ /* boot command, including the target-defined one if any */ /* Extra env settings (including the target-defined ones if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BK4_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 2c5236aa58..236d720a55 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -67,7 +67,7 @@ MMC_TGTS \ #define LOAD_OFFSET(x) 0x8##x -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "verify=no\0" \ "scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 984602c2cf..32d9f503d9 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -24,7 +24,7 @@ /* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "cfgaddr=0x106F0000\0" \ "scraddr=0x10700000\0" \ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h index f9908352b0..ffb4cd3027 100644 --- a/include/configs/brsmarc1.h +++ b/include/configs/brsmarc1.h @@ -24,7 +24,7 @@ #define V_SCLK (V_OSCK) /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "cfgscr=mw ${dtbaddr} 0;" \ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h index 410b3e641c..9ca6d6f863 100644 --- a/include/configs/brxre1.h +++ b/include/configs/brxre1.h @@ -20,7 +20,7 @@ #define V_SCLK (V_OSCK) /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BUR_COMMON_ENV \ "scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootaddr=0x80001100\0" \ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 474ad69d99..a8273a7fcd 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -67,7 +67,7 @@ "emmc_dev=0\0" /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ AHAB_ENV \ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6f3396bad4..263981860e 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -55,7 +55,7 @@ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h index 1e5154af0a..850eb892db 100644 --- a/include/configs/chiliboard.h +++ b/include/configs/chiliboard.h @@ -25,7 +25,7 @@ "nand read ${loadaddr} NAND.kernel; " \ "bootz ${loadaddr} - ${fdt_addr}\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "fdt_addr=0x87800000\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 5c9004cbd9..2d56d37f06 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -24,9 +24,9 @@ #define CFG_SYS_I2C_PCA953X_ADDR 0x20 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index 9c9e9506dc..062d3d8702 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -110,7 +110,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "console=ttyS0,115200\0" \ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 9df8baa8a9..c66cf72187 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -30,7 +30,7 @@ /* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 8a18d6f97a..aa17c9cbe2 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -41,7 +41,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x81200000\0" \ "bootm_size=0x8000000\0" \ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 6f3524deb5..5b802aa92a 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -79,7 +79,7 @@ #endif #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ UBI_BOOTCMD \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 215c633a4c..13bc4e7e68 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -56,7 +56,7 @@ "${fdt_addr};\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ BOOTENV \ CONFIG_MFG_ENV_SETTINGS \ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 4e51df123a..bf2a9bbaaf 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -56,7 +56,7 @@ "ramdisk_addr_r=0x18400000\0" \ "scriptaddr=0x18280000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "boot_file=zImage\0" \ "boot_script_dhcp=boot.scr\0" \ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 89546b857f..91f87ea283 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -119,7 +119,7 @@ #endif #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ MODULE_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index e8918df69e..60f31389fd 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -47,7 +47,7 @@ #define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ UBI_BOOTCMD \ diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index e9b85b4e1c..6f43172526 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -18,8 +18,8 @@ #define VIDEO_IO_OFFSET 0 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-22\0" \ "boot=zboot 03000000 0 04000000 ${filesize}\0" \ "upd_uboot=tftp 100000 conga/u-boot.rom;" \ diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 119a834fe7..0e922b9664 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -21,7 +21,7 @@ * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth1\0" \ "consoledev=ttyS1\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index 25bcc2a684..6535730731 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -13,7 +13,7 @@ /* Environment in SPI NOR flash */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index a818a4b39f..cfc8330e35 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -145,7 +145,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ "bootpart=0:2\0" \ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 4b31bbf4e1..323703ac5c 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -68,7 +68,7 @@ "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "console=ttymxc0,115200n8\0" \ "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index b9d03d253d..c4ae397e3e 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -17,7 +17,7 @@ /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index bba2b607aa..6dbf582d73 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -18,7 +18,7 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 84ea1baa99..0ee914e91d 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -11,7 +11,7 @@ /* NAND */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 66aa6d5c3c..ab10101f20 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -67,7 +67,7 @@ * Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ethaddr=00:01:90:00:C0:81\0" \ "dtbaddr=0x81000000\0" \ "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e3621fd6f9..c522d334dc 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -22,7 +22,7 @@ DEFAULT_LINUX_BOOT_ENV /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 154c4f4f13..d10422b6c1 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -22,8 +22,8 @@ #define VIDEO_IO_OFFSET 0 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "kernel-ver=4.4.0-24\0" \ "boot=zboot 03000000 0 04000000 ${filesize}\0" \ "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 3aed6299ed..6aef15c658 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -41,7 +41,7 @@ #endif #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/display5.h b/include/configs/display5.h index 4401515a65..70ad88c907 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -164,7 +164,7 @@ "sf write ${loadaddr} 0x0 ${filesize};" \ "fi\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ PARTS_DEFAULT \ "gpio_recovery=93\0" \ "check_em_pad=gpio input ${gpio_recovery};test $? -eq 0;\0" \ diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 1bfb741346..4842eccf40 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -28,7 +28,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h index a6c1e9c6d0..999389197c 100644 --- a/include/configs/dockstar.h +++ b/include/configs/dockstar.h @@ -22,7 +22,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/uImage\0" \ "initrd=/boot/uInitrd\0" \ diff --git a/include/configs/draco.h b/include/configs/draco.h index ab3cf10d77..b56ba9132a 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -28,7 +28,7 @@ #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=draco\0" \ "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index daf7ecd797..73aec34845 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -28,6 +28,6 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h index 31cd8536de..4997083711 100644 --- a/include/configs/dragonboard820c.h +++ b/include/configs/dragonboard820c.h @@ -26,7 +26,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x95000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h index bd88c42a3b..c1e590fae2 100644 --- a/include/configs/dragonboard845c.h +++ b/include/configs/dragonboard845c.h @@ -13,7 +13,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ "bootm_low=0x80000000\0" \ "bootcmd=bootm $prevbl_initrd_start_addr\0" diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h index 98322a54f6..85b47a15d7 100644 --- a/include/configs/dreamplug.h +++ b/include/configs/dreamplug.h @@ -17,7 +17,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "x_bootcmd_ethernet=ping 192.168.2.1\0" \ "x_bootcmd_usb=usb start\0" \ "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ diff --git a/include/configs/ds109.h b/include/configs/ds109.h index 8e7a86e062..ea77abb474 100644 --- a/include/configs/ds109.h +++ b/include/configs/ds109.h @@ -26,7 +26,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "x_bootcmd_ethernet=ping 192.168.1.2\0" \ "x_bootcmd_usb=usb start\0" \ "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 76d1713fdc..e69883ba73 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -43,7 +43,7 @@ /* Default Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "initrd_high=0xffffffff\0" \ "ramdisk_addr_r=0x8000000\0" \ "usb0Mode=host\0usb1Mode=host\0usb2Mode=device\0" \ diff --git a/include/configs/durian.h b/include/configs/durian.h index 001596c00a..9f11e18d34 100644 --- a/include/configs/durian.h +++ b/include/configs/durian.h @@ -15,7 +15,7 @@ /* BOOT */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \ "load_fdt=ext4load scsi 0:1 0x95000000 ft2004-pci-64.dtb\0"\ "boot_fdt=bootm 0x90100000 -:- 0x95000000\0" \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 89e071c0df..a5e2dc063a 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -23,7 +23,7 @@ #define CONFIG_MXC_UART_BASE UART2_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "board=EL6Q\0" \ "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 1742b1192f..c1748fc260 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -76,7 +76,7 @@ CONSOLE_STDIN_SETTINGS \ CONSOLE_STDOUT_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdtfile=" FDTFILE "\0" \ diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h index c2b921e7cb..83aaa09cdb 100644 --- a/include/configs/emsdp.h +++ b/include/configs/emsdp.h @@ -15,7 +15,7 @@ * Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade_image=u-boot.bin\0" \ "upgrade=emsdp rom unlock && " \ "fatload mmc 0 ${loadaddr} ${upgrade_image} && " \ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 57f619f55f..8d8e717b38 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -128,7 +128,7 @@ COMMON_ENV_NAND_CMDS /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=etamin\0" \ "ubi_off=4096\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h index bec1660cf4..f304929263 100644 --- a/include/configs/evb_ast2500.h +++ b/include/configs/evb_ast2500.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Misc */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "" #endif /* __CONFIG_H */ diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h index c9c988b937..e1cce58fa9 100644 --- a/include/configs/evb_ast2600.h +++ b/include/configs/evb_ast2600.h @@ -14,7 +14,7 @@ #define STR_HELPER(s) #s #define STR(s) STR_HELPER(s) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootspi=fdt addr 20100000 && fdt header get fitsize totalsize && " \ "cp.b 20100000 ${loadaddr} ${fitsize} && bootm; " \ diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h index 13e3cb2ffe..e7d866551a 100644 --- a/include/configs/evb_rv1108.h +++ b/include/configs/evb_rv1108.h @@ -11,8 +11,8 @@ /* * Default environment settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ipaddr=172.16.12.50\0" \ "serverip=172.16.12.69\0" \ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 43ea34db7b..ec09f6cc5d 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -91,7 +91,7 @@ #define EXYNOS_FDTFILE_SETTING #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index e22dd036cc..9971385848 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -63,7 +63,7 @@ #define EXYNOS_FDTFILE_SETTING #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS diff --git a/include/configs/exynos78x0-common.h b/include/configs/exynos78x0-common.h index 8672b9e952..92c84cd8ce 100644 --- a/include/configs/exynos78x0-common.h +++ b/include/configs/exynos78x0-common.h @@ -74,7 +74,7 @@ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS #endif /* __CONFIG_EXYNOS78x0_COMMON_H */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 671b75e698..855aaa1aa5 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -55,7 +55,7 @@ * Environment Configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS1\0" \ "u-boot=u-boot.bin\0" \ diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 1aaa3e67d6..0523ff9a64 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -35,7 +35,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Command definition */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=/boot/fitImage\0" \ "fdt_addr_r=0x18000000\0" \ "splash_addr_r=0x20000000\0" \ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index f62b8f175e..32960fb932 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -41,7 +41,7 @@ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ NETWORKBOOT \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index 1c86dcb1f6..b7de159c86 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -31,7 +31,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/uImage\0" \ "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" diff --git a/include/configs/gose.h b/include/configs/gose.h index d1fe375a2c..45f0ec6f6a 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -29,7 +29,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __GOSE_H */ diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h index d196c4eda5..44b4595440 100644 --- a/include/configs/guruplug.h +++ b/include/configs/guruplug.h @@ -23,7 +23,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "mtdids=nand0=orion_nand\0" \ "kernel=/boot/zImage\0" \ diff --git a/include/configs/helios4.h b/include/configs/helios4.h index fc32487e1c..7d81d1cf1e 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -110,7 +110,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 4aef0b4abd..76e6054b0c 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -16,7 +16,7 @@ #define CFG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" diff --git a/include/configs/hikey.h b/include/configs/hikey.h index d4280decc9..36bf22b187 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -42,7 +42,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_name=Image\0" \ "kernel_addr_r=0x00080000\0" \ "fdtfile=hi6220-hikey.dtb\0" \ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index fad1f98048..40d5e653c3 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -28,7 +28,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "fdtfile=hi3660-hikey960.dtb\0" \ "fdt_addr_r=0x10000000\0" \ diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h index 59ea896007..f59da41773 100644 --- a/include/configs/hsdk-4xd.h +++ b/include/configs/hsdk-4xd.h @@ -37,7 +37,7 @@ /* * Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade=if mmc rescan && " \ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h index fbfcded471..2177fafcdc 100644 --- a/include/configs/hsdk.h +++ b/include/configs/hsdk.h @@ -36,7 +36,7 @@ /* * Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "upgrade=if mmc rescan && " \ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h index 76fc4ac8b6..e1b62f78b2 100644 --- a/include/configs/ib62x0.h +++ b/include/configs/ib62x0.h @@ -18,7 +18,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/ib62x0.dtb\0" \ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h index 6d2104b3a1..d372ffb802 100644 --- a/include/configs/iconnect.h +++ b/include/configs/iconnect.h @@ -11,7 +11,7 @@ #include "mv-common.h" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/uImage\0" \ "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 36b6b95b84..4208ba9591 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -24,7 +24,7 @@ #endif /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 4e23f1a2dc..0df61916b7 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -21,7 +21,7 @@ /* Ethernet Configs */ #define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "bootm_size=0x10000000\0" \ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 402f83c18e..b6006c021d 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -20,7 +20,7 @@ /* Environment in MMC */ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x14000000\0" \ "fdt_addr_r=0x13000000\0" \ "kernel_addr_r=0x10008000\0" \ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 392f97050a..e28185f24d 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -72,7 +72,7 @@ #endif /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootconf=conf-imx6q-bosch-acc.dtb\0"\ "mmcfit_name=fitImage\0" \ "mmcloadfit=ext4load mmc ${mmcdev}:${fitpart} ${fit_addr} ${mmcfit_name}\0" \ diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 2d9d3c34b0..c95038eaa5 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -54,7 +54,7 @@ #devtypel #instance " " /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ NANDARGS \ BOOTENV diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 8e9dbefc49..66cf5b463f 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -12,7 +12,7 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS /* * Use: @@ -22,7 +22,7 @@ */ #define MY_CONFIG_BOOT_MODE "boot-mode=sd\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MY_CONFIG_BOOT_MODE \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c228cf7f37..00ce7fb62a 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -63,7 +63,7 @@ BOOT_TARGET_DHCP(func) /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8mm-mx8menlo.h b/include/configs/imx8mm-mx8menlo.h index 938c5406b8..a86bd76a3c 100644 --- a/include/configs/imx8mm-mx8menlo.h +++ b/include/configs/imx8mm-mx8menlo.h @@ -9,8 +9,8 @@ #include /* Custom initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "devtype=mmc\0" \ diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 03325e6c3a..ee524f0e63 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -20,7 +20,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 80321cf2d8..44d74bb1a7 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -34,7 +34,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ "bootlimit=3\0" \ "devtype=mmc\0" \ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 8a694c88a5..d28f3f1972 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -37,7 +37,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 41ab930779..e718daa07c 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -30,7 +30,7 @@ "ramdisk_addr_r=0x46400000\0" \ "scriptaddr=0x46000000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 28ce834769..c490e3829f 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -25,7 +25,7 @@ func(USB, usb, 1) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "splblk=0x42\0" \ BOOTENV diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 85fd5e2371..bb3dfe3fa0 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -13,7 +13,7 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "ramdiskimage=rootfs.cpio.uboot\0" \ diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index a768ff3551..e97b8e871d 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -35,7 +35,7 @@ #devtypel #instance " " /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ NANDARGS \ BOOTENV diff --git a/include/configs/imx8mn_bsh_smm_s2pro.h b/include/configs/imx8mn_bsh_smm_s2pro.h index 035e5c7bd9..8619fdde7f 100644 --- a/include/configs/imx8mn_bsh_smm_s2pro.h +++ b/include/configs/imx8mn_bsh_smm_s2pro.h @@ -22,7 +22,7 @@ "emmc_ack=1\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ EMMCARGS \ BOOTENV diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 024b86c7f1..b759b834b8 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -32,7 +32,7 @@ "scriptaddr=0x40000000\0" \ "pxefile_addr_r=0x40100000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 4633843d1b..205337948c 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -37,7 +37,7 @@ "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a585cbf87e..80c2df9f30 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -19,7 +19,7 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "splblk=0x40\0" \ BOOTENV diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 5443022b04..b8fdedefa2 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -28,7 +28,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ "bootlimit=3\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 137bd3b095..c6e3b105a8 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -26,7 +26,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index b261a81e44..c3abcee40e 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -29,7 +29,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 58f7dc6518..ed4da0e69b 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -71,7 +71,7 @@ BOOT_TARGET_DHCP(func) /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index e79aa57075..4b32d5a77e 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -19,7 +19,7 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "splblk=0x40\0" \ BOOTENV diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 4df98e3f37..f6f356d27b 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -30,7 +30,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=0x43500000\0" \ "kernel_addr_r=0x40880000\0" \ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 688c0bf700..c40448715f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -35,7 +35,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 3b4cd65622..8fed3e3196 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -29,7 +29,7 @@ "initrd_high=0xffffffff\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index f1f907f3e5..7772e71013 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -23,7 +23,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 2e2e5ed43c..5692e3d000 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -47,7 +47,7 @@ "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index d75b8bf0c1..669da591fa 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -23,7 +23,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index d313bdc2a4..30dd5af03b 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -34,7 +34,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 895c50f602..5cd6492dd5 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -28,7 +28,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=0x83500000\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 84228676c7..7688464841 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -19,7 +19,7 @@ DMAMEM_SZ_ALL) #ifdef CONFIG_VIDEO -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=serial\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/iot2050.h b/include/configs/iot2050.h index 0f6150fc9c..7d08741336 100644 --- a/include/configs/iot2050.h +++ b/include/configs/iot2050.h @@ -40,7 +40,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ BOOTENV \ EXTRA_ENV_IOT2050_BOARD_SETTINGS diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index e66f994a37..a7210b5cf3 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -170,7 +170,7 @@ #include /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index ab204c62b7..54dfea6952 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -127,7 +127,7 @@ DFU_ALT_INFO_OSPI /* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 736865ad80..61ff80d2c9 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -29,7 +29,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 7c5f673c0f..e3ae91089f 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -45,6 +45,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif /* __KONTRON_MX6UL_CONFIG_H */ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index beb1926c12..e4d6a8a154 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -49,6 +49,6 @@ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif -#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV +#define CFG_EXTRA_ENV_SETTINGS BOOTENV #endif /* __KONTRON_MX8MM_CONFIG_H */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 17c63d8341..d909bbbbcf 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -50,7 +50,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc2,115200\0" \ "boot_fdt=try\0" \ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index a073a06c82..0d293f316b 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -61,7 +61,7 @@ func(PXE, pxe, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "env_addr=0x203e0004\0" \ "envload=env import -d -b ${env_addr}\0" \ "install_rcw=source 20200000\0" \ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index c551585a20..da8a67b4ab 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -16,7 +16,7 @@ /* Command definition */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ "fdt_addr=0x75000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 136e228682..99321b320f 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -22,7 +22,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 7a66df548a..7ad29f9299 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -44,7 +44,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/lager.h b/include/configs/lager.h index f3feaa539f..777d5b94d1 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -30,7 +30,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 794c1fcbed..687ac89b85 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -48,7 +48,7 @@ * Linux Information */ #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootenvfile=uEnv.txt\0" \ "fdtfile=da850-lego-ev3.dtb\0" \ "memsize=64M\0" \ diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 377e3e7b3f..7417f8582a 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -62,7 +62,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x80000000\0" \ "pxefile_addr_r=0x80100000\0" \ "kernel_addr_r=0x80800000\0" \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 721da81863..938ab5ade9 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -20,7 +20,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index f0a9e9ab31..d1e0ed5817 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -11,8 +11,8 @@ /* DDR */ #define CFG_SYS_SDRAM_SIZE 0x40000000 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 9e4f949016..a5f680db2d 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -34,7 +34,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index c19ed2f43e..4243a21f1f 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -16,8 +16,8 @@ #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 1b417c72e7..872296749c 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -25,8 +25,8 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index 495bb3911b..35e8ff0579 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -55,8 +55,8 @@ #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index d74936d128..1e843f896c 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -36,8 +36,8 @@ #define __PHY_ETH2_MASK 0xFB #define __PHY_ETH1_MASK 0xFD -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr=0x01000000\0" \ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 0e3ff3c5b7..8b5fba51c6 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -72,7 +72,7 @@ #define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 76e75335c5..78432e5581 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -247,12 +247,12 @@ #define HWCONFIG_BUFFER_SIZE 256 #ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index b15c4a238b..b722586dd6 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -60,7 +60,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ "kernel_addr=0x61000000\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 9b22a2db21..a387eeab47 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -144,7 +144,7 @@ #include #ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ @@ -200,7 +200,7 @@ "cp.b $kernel_addr $load_addr " \ "$kernel_size && bootm $load_addr#$board\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index 228fb122f5..769ece901c 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -61,8 +61,8 @@ /* SATA */ #ifndef SPL_NO_ENV -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028aqds\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 5c13461257..8c53636bea 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -56,8 +56,8 @@ /* Initial environment variables */ #ifndef SPL_NO_ENV -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "board=ls1028ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 685e7e65d1..ac2319c1b4 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -88,7 +88,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ae9dc0c73b..38fb1d45bc 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -84,7 +84,7 @@ #endif #ifndef SPL_NO_MISC /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 86c5d48c0d..720a95d2f5 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -117,7 +117,7 @@ unsigned long long get_qixis_addr(void); #ifndef SPL_NO_ENV /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 3391540c6e..084ee064ae 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -293,8 +293,8 @@ /* Initial environment variables */ #ifdef CONFIG_NXP_ESBC -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -325,8 +325,8 @@ #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580A00000 0x580E00000\0" -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -387,8 +387,8 @@ "$kernel_size && bootm $kernel_load#$BOARD\0" #else #if defined(CONFIG_QSPI_BOOT) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -405,8 +405,8 @@ "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #elif defined(CONFIG_SD_BOOT) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ @@ -423,8 +423,8 @@ "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #else /* NOR BOOT */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 1ddf0687f4..a1749149e5 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -234,9 +234,9 @@ #endif #endif /* CONFIG_TFABOOT */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #ifdef CONFIG_TFABOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "BOARD=ls1088ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ @@ -304,7 +304,7 @@ " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "BOARD=ls1088ardb\0" \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index bd78bdb793..f51eb31ed0 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -109,7 +109,7 @@ unsigned long long get_qixis_addr(void); #define HWCONFIG_BUFFER_SIZE 128 /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 4a52fcdfdd..7ad2432a77 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -226,9 +226,9 @@ #define CFG_SYS_I2C_RTC_ADDR 0x68 /* Initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ @@ -253,7 +253,7 @@ #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "loadaddr_sd=0x90100000\0" \ @@ -309,7 +309,7 @@ "$kernel_addr_sd $kernel_size_sd && " \ "bootm $load_addr#$BOARD\0" #elif defined(CONFIG_SD_BOOT) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x800\0" \ @@ -325,7 +325,7 @@ "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b8ab501c98..794ea84852 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -275,9 +275,9 @@ #endif /* Initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #ifdef CONFIG_TFABOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ @@ -339,7 +339,7 @@ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ "bootm $load_addr#$board\0" #else -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index c82eb8b04b..47d7ec57b8 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -22,7 +22,7 @@ /* * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootsource=legacy\0" \ "hdpart=0:1\0" \ "kernel_addr_r=0x00800000\0" \ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 9f891064bd..3a316e7330 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -14,7 +14,7 @@ /* MAC/PHY configuration */ /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2160aqds_boot.scr\0" \ "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 58c0ff3657..8cc4e0db03 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -18,7 +18,7 @@ #define I2C_EMC2305_PWM 0x80 /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2160ardb_boot.scr\0" \ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 157688ef7d..54d7cea4c5 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -14,7 +14,7 @@ #define CFG_SYS_RTC_BUS_NUM 0 /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \ "boot_scripts=lx2162aqds_boot.scr\0" \ "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index d42ad9acb4..0deb7672f9 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -84,7 +84,7 @@ * Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "consdev=ttymxc0\0" \ "baudrate=115200\0" \ "bootscript=boot.scr\0" \ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index a7f5507692..436f5f0059 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -33,7 +33,7 @@ /* Ethernet Configuration */ #define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200 quiet\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/meson64.h b/include/configs/meson64.h index a22f7a81b0..9244601284 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -83,8 +83,8 @@ #include -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "stdin=" STDIN_CFG "\0" \ "stdout=" STDOUT_CFG "\0" \ "stderr=" STDOUT_CFG "\0" \ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h index 1266851196..c0e977abb0 100644 --- a/include/configs/meson64_android.h +++ b/include/configs/meson64_android.h @@ -279,7 +279,7 @@ "fi;" \ "fi;" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ EXTRA_ANDROID_ENV_SETTINGS \ "partitions=" PARTS_DEFAULT "\0" \ "mmcdev=2\0" \ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index b8b08974c7..6740ab2be3 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -76,8 +76,8 @@ #include -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "unlock=yes\0"\ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h index c73c5a1d9f..5ced45b88b 100644 --- a/include/configs/microchip_mpfs_icicle.h +++ b/include/configs/microchip_mpfs_icicle.h @@ -19,7 +19,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "kernel_addr_r=0x84000000\0" \ "fdt_addr_r=0x88000000\0" \ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index cfe926c0a1..ef2111cd20 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -30,7 +30,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 93161bd24f..db12377b00 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -42,7 +42,7 @@ #include /* Extra environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index 3da7619d78..1f973829bb 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -21,7 +21,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x40000000\0" \ BOOTENV diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 3a35527da1..c0fc8688ca 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -26,7 +26,7 @@ #define ENV_BOOT_CMD \ "mtk_boot=run boot_rd_img;bootm;\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c000000\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 0f7981a566..73776e3705 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -21,7 +21,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x40000000\0" \ BOOTENV diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8a8bc85ca7..d6bd1a1038 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -33,7 +33,7 @@ "serial#=1234567890ABCDEF\0" \ "board=mt8518\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c000000\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ diff --git a/include/configs/mvebu_alleycat-5.h b/include/configs/mvebu_alleycat-5.h index 3ad3aefa75..39e37ffbf7 100644 --- a/include/configs/mvebu_alleycat-5.h +++ b/include/configs/mvebu_alleycat-5.h @@ -22,7 +22,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "kernel_addr_r=0x202000000\0" \ "fdt_addr_r=0x201000000\0" \ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 9bfc48c52d..76e148f55e 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -89,7 +89,7 @@ "" /* fdt_addr and kernel_addr are needed for existing distribution boot scripts */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x6d00000\0" \ "pxefile_addr_r=0x6e00000\0" \ "fdt_addr=0x6f00000\0" \ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index beac3ae649..239a09763a 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -41,7 +41,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x6d00000\0" \ "pxefile_addr_r=0x6e00000\0" \ "fdt_addr_r=0x6f00000\0" \ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index aa3d7a1a3f..e769ba2e83 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -19,7 +19,7 @@ /* Ethernet */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index f597cdb305..5ceba8b15f 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -16,7 +16,7 @@ #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "update_sd_firmware_filename=u-boot.sd\0" \ "update_sd_firmware=" /* Update the SD firmware partition */ \ "if mmc rescan ; then " \ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index c740d85332..f9f65f6968 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -18,7 +18,7 @@ /* UBI and NAND partitioning */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ubifs_file=filesystem.ubifs\0" \ "update_nand_full_filename=u-boot.nand\0" \ "update_nand_firmware_filename=u-boot.sb\0" \ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ddd37b3936..8ab1ee79a7 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -39,7 +39,7 @@ /* Framebuffer and LCD */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "fdt_file=imx51-babbage.dtb\0" \ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index cd806cb698..baffe65c36 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -37,7 +37,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x75000000\0" \ "pxefile_addr_r=0x73000000\0" \ "scriptaddr=0x74000000\0" \ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index d0107fcc8c..0ac93d6e04 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -27,7 +27,7 @@ /* Command definition */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "fdt_addr=0x71000000\0" \ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 9464d6e44a..94d2191af9 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -35,7 +35,7 @@ "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ "${nfsserver}:${image}; bootm ${loadaddr}\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ PPD_CONFIG_NFS \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index f7f209c20b..d4af96b51e 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ "has_emmc=undefined\0" \ "fdtfile=undefined\0" \ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 96a48a97a3..9c61350a33 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -35,7 +35,7 @@ #define EMMC_ENV "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "fdtfile=undefined\0" \ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 358d9f47c0..4fbd06783a 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -15,7 +15,7 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 8731f6a3e4..cf4871cbae 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -12,7 +12,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 0dd40563c2..9d8737c194 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -12,7 +12,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 6f5dffe4fb..8372f979dc 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -34,7 +34,7 @@ #define UPDATE_M4_ENV "" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index cb1019bd56..90c7884687 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -30,7 +30,7 @@ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 0e986093f3..4a27fd2290 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -24,7 +24,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index e56b6101af..e56083f8e6 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -50,7 +50,7 @@ "bootimg part 0 1;"\ "rootfs part 0 2\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ CFG_DFU_ENV_SETTINGS \ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 85922fa436..5ee5129801 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -28,7 +28,7 @@ #define PHYS_SDRAM 0x60000000 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttyLP0\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 99e01896c7..5f4cd93062 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -28,7 +28,7 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttyLP0\0" \ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index a32fcd57f8..43261824d3 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -33,7 +33,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/nas220.h b/include/configs/nas220.h index 85691ca94f..358c3bb85a 100644 --- a/include/configs/nas220.h +++ b/include/configs/nas220.h @@ -35,7 +35,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs=console=ttyS0,115200\0" \ "autostart=no\0" diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 1d101977c2..496a3164f4 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -64,7 +64,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc1\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index caaa9ed86b..97d0868529 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -58,7 +58,7 @@ #define CFG_SYS_ONENAND_BASE ONENAND_MAP /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "usbtty=cdc_acm\0" \ "stdin=usbtty,serial,keyboard\0" \ "stdout=usbtty,serial,vidconsole\0" \ diff --git a/include/configs/novena.h b/include/configs/novena.h index b0d473eeee..3ffb44ab72 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -58,7 +58,7 @@ #endif /* Extra U-Boot environment. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "consdev=ttymxc1\0" \ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 2eebd0c9a4..a12e34b6e6 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -38,7 +38,7 @@ #define CONFIG_FEC_ENET_DEV 1 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "image=zImage\0" \ "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h index e2ad77072c..fa029a176b 100644 --- a/include/configs/nsa310s.h +++ b/include/configs/nsa310s.h @@ -36,7 +36,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=console=ttyS0,115200\0" \ "kernel=/boot/zImage\0" \ "fdt=/boot/nsa310s.dtb\0" \ diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index ea1edab9fc..0e1083a213 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -15,7 +15,7 @@ # define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "mmcdev=0\0" \ "mmcpart=2\0" \ "mmcargs=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcpart} console=ttymxc0,${baudrate} panic=30\0" \ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 03d1a8e7b5..c4db38562d 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -15,7 +15,7 @@ /** Stack starting address */ /** Extra environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ "ethrotate=yes\0" diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 58275ccffa..0be26ef328 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -17,7 +17,7 @@ #include /* Extra environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x20080000\0" \ "kernel_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x03000000\0" \ @@ -27,7 +27,7 @@ #else /** Extra environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=20080000\0" \ "autoload=0\0" diff --git a/include/configs/odroid.h b/include/configs/odroid.h index e2331e45cd..3ac13a65d6 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -71,7 +71,7 @@ * 1. BOOT: 100MiB 2MiB * 2. ROOT: - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ "boot.scr\0" \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index e4a81499a7..2bac017ea0 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -60,8 +60,8 @@ */ /* Define new extra env settings, including DFU settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS \ EXYNOS_FDTFILE_SETTING \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index f4e23bbb0f..efeb7bf100 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -73,7 +73,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bb8521f1c..adb25a6297 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -69,7 +69,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index a6b5e55b54..93d36353ff 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -59,7 +59,7 @@ "if test ${fdtfile} = ''; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_FINDFDT \ ENV_DEVICE_SETTINGS \ MEM_LAYOUT_SETTINGS \ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 3895537751..957f1c369e 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -30,7 +30,7 @@ /* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "mmcdev=0\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index f19211fe64..5e71ebcba8 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -137,7 +137,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ "bootpart=0:2\0" \ diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h index 5b097e9fef..5adfc67195 100644 --- a/include/configs/openpiton-riscv64.h +++ b/include/configs/openpiton-riscv64.h @@ -20,7 +20,7 @@ * Board boot configuration */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x86000000\0" \ "kernel_addr_r=0x80200000\0" \ "image=boot/Image\0" \ diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 2cec20ca42..1e6b16b4e7 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -27,7 +27,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ +#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ "x_bootcmd_usb=usb start\0" \ diff --git a/include/configs/origen.h b/include/configs/origen.h index a608df44e8..fd4cc70a67 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -23,7 +23,7 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x40007000\0" \ "rdaddr=0x48000000\0" \ "kerneladdr=0x40007000\0" \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 74627b2e63..a353c16f74 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -393,7 +393,7 @@ #include "p1_p2_bootsrc.h" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ "loadaddr=1000000\0" \ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 2a1660bf18..146f87e9ce 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -45,7 +45,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "fdt_addr_r=0x82000000\0" \ "fdt_high=0xffffffff\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 4421e740d9..0890c11570 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -65,7 +65,7 @@ "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ /* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "console=ttymxc0,115200n8\0" \ "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index 5c2ff5d02e..34994016c5 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -29,7 +29,7 @@ /* boot command, including the target-defined one if any */ /* Extra env settings (including the target-defined ones if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ PCM052_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 3674e4cdda..2991076c50 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -39,7 +39,7 @@ "nandloadfit=ubi part rootfs;ubi readvol ${loadaddr} fit\0" \ "nandboot=run nandloadfit;run nandargs;bootm ${loadaddr}\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x30000000\0" \ "optargs=rw rootwait\0" \ ENV_MMC \ diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h index 7180783767..80b14b002a 100644 --- a/include/configs/pdu001.h +++ b/include/configs/pdu001.h @@ -32,7 +32,7 @@ #define CONSOLE_DEV "ttyO5" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ "fdtfile=am335x-pdu001.dtb\0" \ "bootfile=zImage\0" \ diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h index f922491637..4e6dc79f41 100644 --- a/include/configs/phycore_am335x_r2.h +++ b/include/configs/phycore_am335x_r2.h @@ -62,7 +62,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_MMC_TI_ARGS \ DEFAULT_LINUX_BOOT_ENV \ "bootfile=zImage\0" \ diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 7f73117ac1..9160c78c04 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -20,7 +20,7 @@ /* For RAW image gives a error info not panic */ #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc2,115200\0" \ "fdt_addr=0x48000000\0" \ diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 7a38382034..d79d364c8e 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -13,7 +13,7 @@ #define CFG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ "console=ttymxc0,115200\0" \ "fdt_addr=0x48000000\0" \ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 3cc2a693ce..60c7473275 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -69,7 +69,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ CONFIG_LEGACY_BOOTCMD_ENV \ BOOTENV diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 719b701440..66258a3ab7 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -38,7 +38,7 @@ "bootmenu_3=Boot using PICO-Nymph baseboard=" \ "setenv baseboard nymph; saveenv; run base_boot\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTMENU_ENV \ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 36f648f634..45fc6126c8 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -45,7 +45,7 @@ "bootmenu_2=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx6ul-pico-pi.dtb\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "splashpos=m,m\0" \ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 5819215104..7fc6211ff7 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -51,7 +51,7 @@ BOOTENV #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index f9301a5524..ac25991703 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -25,7 +25,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index a233fb8ed7..f4a34f261a 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -144,7 +144,7 @@ /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index fa08744b6f..cd9d21e420 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -163,7 +163,7 @@ /* USB */ #define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "partition=nand0,0\0" \ "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h index fc9f113dee..b1354219c9 100644 --- a/include/configs/pogo_e02.h +++ b/include/configs/pogo_e02.h @@ -18,7 +18,7 @@ * Default environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs_console=console=ttyS0,115200\0" \ "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ "ext2load usb 0:1 0x01100000 /uInitrd\0" diff --git a/include/configs/pogo_v4.h b/include/configs/pogo_v4.h index 239d33d8e9..3371579023 100644 --- a/include/configs/pogo_v4.h +++ b/include/configs/pogo_v4.h @@ -61,7 +61,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ diff --git a/include/configs/poleg.h b/include/configs/poleg.h index 075729e5d3..c3f1d3393c 100644 --- a/include/configs/poleg.h +++ b/include/configs/poleg.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE 0x0 /* Default environemnt variables */ -#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ +#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h index 1c11685f49..8e74dc4888 100644 --- a/include/configs/pomelo.h +++ b/include/configs/pomelo.h @@ -21,7 +21,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ "scriptaddr=0x90100000\0" \ diff --git a/include/configs/poplar.h b/include/configs/poplar.h index c58105597e..6e8adf9187 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -31,7 +31,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loader_mmc_blknum=0x0\0" \ "loader_mmc_nblks=0x780\0" \ "env_mmc_blknum=0xf80\0" \ diff --git a/include/configs/porter.h b/include/configs/porter.h index e0f77f358b..202bd914d5 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -31,7 +31,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 2b25c31b1d..df07df6a5a 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -54,7 +54,7 @@ #define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c /* max command args */ -#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0" +#define CFG_EXTRA_ENV_SETTINGS "silent=y\0" /* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 99376155b4..003686930a 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -27,7 +27,7 @@ "ramdisk_addr_r=0x0a200000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 48f49906b8..10eaeb49de 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -28,7 +28,7 @@ /* Use common default */ /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=pxm2\0" \ "ubi_off=2048\0"\ "nand_img_size=0x500000\0" \ diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h index c41bb341d8..8ea59aa21c 100644 --- a/include/configs/qcs404-evb.h +++ b/include/configs/qcs404-evb.h @@ -13,7 +13,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x5000000\0" \ "bootm_low=0x80000000\0" \ "bootcmd=bootm $prevbl_initrd_start_addr\0" diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h index a67af73fd5..45bd94ee5c 100644 --- a/include/configs/qemu-arm.h +++ b/include/configs/qemu-arm.h @@ -76,7 +76,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "fdt_addr=0x40000000\0" \ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 35172da3ff..20135f569e 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -34,7 +34,7 @@ #define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \ "qemu " -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 59d56d6662..777df4c112 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -38,7 +38,7 @@ #define EEPROM_ADDR_CHIP 0x120 /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=rastaban\0" \ "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 86012adfb3..8e0837a302 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -32,7 +32,7 @@ /* ENV setting */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" #endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index a4cae69718..ea6073f294 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -25,7 +25,7 @@ /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0x7fffffff\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index 99c86edeaa..c4758e148b 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -24,7 +24,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6fffffff\0" \ "initrd_high=0x6fffffff\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 302546630a..5b0ec37000 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -27,7 +27,7 @@ "ramdisk_addr_r=0x64000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 334fb3affa..58f491c2f3 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -31,7 +31,7 @@ /* Linux fails to load the fdt if it's loaded above 256M on a Rock board, * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0x6fffffff\0" \ "initrd_high=0x6fffffff\0" \ diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 58ad62afe1..b95268df87 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -27,7 +27,7 @@ /* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_high=0x7fffffff\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 6b55c57dd7..d3b8a5150f 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -30,7 +30,7 @@ /* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so * limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x0fffffff\0" \ "initrd_high=0x0fffffff\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 4b510b1399..bc03e113fe 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -22,7 +22,7 @@ "ramdisk_addr_r=0x04000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "partitions=" PARTS_DEFAULT \ ROCKCHIP_DEVICE_SETTINGS \ diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 132b7d0fe9..85d2186f23 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -22,7 +22,7 @@ "ramdisk_addr_r=0x06000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 92cdc1a51f..1763625051 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -25,7 +25,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index a721f27ec0..2278b6215d 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -50,7 +50,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index d43dc2580e..750f16d039 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -21,7 +21,7 @@ "ramdisk_addr_r=0x0a200000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/rpi.h b/include/configs/rpi.h index e354927513..c3f8e7bf85 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -157,7 +157,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ ENV_DEVICE_SETTINGS \ ENV_DFU_SETTINGS \ diff --git a/include/configs/rut.h b/include/configs/rut.h index b07d0c5060..99799f8494 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -27,7 +27,7 @@ /* Use common default */ /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=rut\0" \ "ubi_off=2048\0"\ "nand_img_size=0x500000\0" \ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 84a5ae6965..6e17b23b62 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -26,7 +26,7 @@ "ramdisk_addr_r=0x64000000\0" #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "partitions=" PARTS_DEFAULT \ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index b4b2dbd038..bfe559f6e2 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -140,7 +140,7 @@ #define EXTRA_ENV_BOOT_LOGO EXTRA_ENV_DTB_RESERVE #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "rootdev=" __stringify(CONFIG_ROOT_DEV) "\0" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 555bedb93d..d1ff00a27f 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -54,7 +54,7 @@ #define COMMON_BOOT "${console} ${meminfo} ${mtdparts}" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ "onenand write 0x32008000 0x0 0x100000\0" \ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 80d3fc9258..bf2d04a169 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -29,7 +29,7 @@ ",100M(swap)"\ ",-(UMS)\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x100000;" \ "onenand write 0x42008000 0x0 0x100000\0" \ diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h index f7cdd5a195..9a4fe530a2 100644 --- a/include/configs/sdm845.h +++ b/include/configs/sdm845.h @@ -13,7 +13,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x4000000\0" \ "bootm_low=0x80000000\0" \ "stdout=vidconsole\0" \ diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index d7923967a7..4e0b3c663c 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -15,7 +15,7 @@ /* * Environment variables configurations */ -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ +#define CFG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ "x_bootcmd_usb=usb start\0" \ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index 4a453a9df4..de3a0dcdd5 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -37,7 +37,7 @@ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ "name=system,size=-,bootable,type=${type_guid_gpt_system};" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_addr_r=0x84000000\0" \ diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index ac42108620..24904aa238 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -34,7 +34,7 @@ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \ "name=system,size=-,bootable,type=${type_guid_gpt_system};" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x84000000\0" \ "kernel_comp_addr_r=0x88000000\0" \ "kernel_comp_size=0x4000000\0" \ diff --git a/include/configs/silk.h b/include/configs/silk.h index 6d605edf78..9114a05758 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -31,7 +31,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h index 974531ea0d..760a0a5b91 100644 --- a/include/configs/sipeed-maix.h +++ b/include/configs/sipeed-maix.h @@ -11,8 +11,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define CFG_SYS_SDRAM_SIZE SZ_8M -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80060000\0" \ "fdt_addr_r=0x80400000\0" \ "scriptaddr=0x80020000\0" \ diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h index ff0ed180e9..748a423b08 100644 --- a/include/configs/slimbootloader.h +++ b/include/configs/slimbootloader.h @@ -14,10 +14,10 @@ "stderr=serial\0" /* - * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h + * Override CFG_EXTRA_ENV_SETTINGS in x86-common.h */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index b988b96e58..762f61470b 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -73,7 +73,7 @@ * Predefined environment variables. * Usefull to define some easy to use boot commands. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ \ "basicargs=console=ttyS0,115200\0" \ \ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index ccb7ec38d0..c148757915 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -28,7 +28,7 @@ " mem=128M " \ " " CONFIG_MTDPARTS_DEFAULT -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "updateb=" \ "onenand erase 0x0 0x40000;" \ "onenand write 0x32008000 0x0 0x40000\0" \ diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 14f9cf5602..11031744be 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -17,7 +17,7 @@ /* MMC Config*/ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdtfile=imx7d-smegw01.dtb\0" \ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index b7aa49ce43..df8ed451a4 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -41,7 +41,7 @@ /* Environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ethaddr=00:00:00:00:00:00\0" \ "serial=0\0" \ "stdout=serial_atmel\0" \ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index afca7e18e9..eaee8dd373 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -62,7 +62,7 @@ * Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ "loadaddr=0x82000000\0" \ "fdt_addr_r=0x88000000\0" \ diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h index aa13878177..2ce7011529 100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@ -19,7 +19,7 @@ */ #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "autoload=no\0" \ "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \ "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index d0f5331d45..0c96c9c24f 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -144,8 +144,8 @@ #include -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "bootm_size=0xa000000\0" \ "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h index 8f1c2de998..565a661258 100644 --- a/include/configs/socfpga_dbm_soc1.h +++ b/include/configs/socfpga_dbm_soc1.h @@ -13,7 +13,7 @@ /* Environment is in MMC */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ "bootscript=boot.scr\0" \ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h index e76438e228..ac70d91e20 100644 --- a/include/configs/socfpga_mcvevk.h +++ b/include/configs/socfpga_mcvevk.h @@ -13,7 +13,7 @@ /* Environment is in MMC */ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ "bootscript=boot.scr\0" \ diff --git a/include/configs/socfpga_n5x_socdk.h b/include/configs/socfpga_n5x_socdk.h index c295e91e3d..fe5286e12c 100644 --- a/include/configs/socfpga_n5x_socdk.h +++ b/include/configs/socfpga_n5x_socdk.h @@ -9,8 +9,8 @@ #include -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=1100000\0" \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index df3927297b..66ecb168a0 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -36,7 +36,7 @@ /* * Environment variable */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "bootfile=" CONFIG_BOOTFILE "\0" \ "fdt_addr=8000000\0" \ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index d88b07bc15..4bb15cf462 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -27,7 +27,7 @@ * Linux system after 5 seconds */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "verify=n\0" \ "consdev=ttyS0\0" \ "baudrate=115200\0" \ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 4c752091fb..2b35be83ec 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -111,7 +111,7 @@ #define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index de0f48b79a..e132805635 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -20,7 +20,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 #endif /* CONFIG_FSL_USDHC */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" \ "console=ttymxc0\0" \ "initrd_addr=0x86800000\0" \ diff --git a/include/configs/stemmy.h b/include/configs/stemmy.h index a5987c5e17..e58ddd752c 100644 --- a/include/configs/stemmy.h +++ b/include/configs/stemmy.h @@ -38,7 +38,7 @@ #define BOOTCMD_ENV \ "fastbootcmd=echo '*** FASTBOOT MODE ***'; fastboot usb 0\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOT_ENV \ CONSOLE_ENV \ FASTBOOT_ENV \ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 9294d57ca8..b3fce50316 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -29,7 +29,7 @@ func(USB, usb, 0) \ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x40000000\0" \ "fdtfile=stih410-b2260.dtb\0" \ "fdt_addr_r=0x47000000\0" \ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index afd7d50428..de5019a364 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -15,7 +15,7 @@ #define CFG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ "bootm 0x08044000 - 0x08042000\0" diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index c8aad47966..a4f3e43dc5 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -24,7 +24,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x00008000\0" \ "fdtfile=stm32429i-eval.dtb\0" \ "fdt_addr_r=0x00408000\0" \ diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 573a6b1795..62a7e9af0c 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -24,7 +24,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x00008000\0" \ "fdtfile=stm32f469-disco.dtb\0" \ "fdt_addr_r=0x00408000\0" \ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 14e883a358..34856d3004 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -24,7 +24,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xC0008000\0" \ "fdtfile="CONFIG_DEFAULT_DEVICE_TREE".dtb\0" \ "fdt_addr_r=0xC0408000\0" \ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index 67e6a3a19d..d36cd6fdd4 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -21,7 +21,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xD0008000\0" \ "fdtfile=stm32h743i-disco.dtb\0" \ "fdt_addr_r=0xD0408000\0" \ diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 4786eb001b..8f242bf0ff 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -21,7 +21,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xD0008000\0" \ "fdtfile=stm32h743i-eval.dtb\0" \ "fdt_addr_r=0xD0408000\0" \ diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index e667fe6f6a..d27b6a3d1d 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -21,7 +21,7 @@ func(MMC, mmc, 0) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0xC0008000\0" \ "fdtfile=stm32h750i-art-pi.dtb\0" \ "fdt_addr_r=0xC0408000\0" \ diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index c259a61613..7c59c69e0b 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -81,7 +81,7 @@ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ BOOTENV \ diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 9715dfad1c..7db72a19ed 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -135,7 +135,7 @@ "fdtoverlay_addr_r=" __FDTOVERLAY_ADDR_R "\0" \ "ramdisk_addr_r=" __RAMDISK_ADDR_R "\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ STM32MP_PARTS_DEFAULT \ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index 910d7ef107..9192169062 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -12,7 +12,7 @@ #define PHY_ANEG_TIMEOUT 20000 #ifdef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=u-boot.itb ram " \ __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) \ " 0x800000\0" diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 38b5aa7319..d0cd4130ce 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -18,7 +18,7 @@ 230400, 460800, 921600, \ 1000000, 2000000 } -#ifdef CONFIG_EXTRA_ENV_SETTINGS +#ifdef CFG_EXTRA_ENV_SETTINGS /* * default bootcmd for stm32mp1 STMicroelectronics boards: * for serial/usb: execute the stm32prog command @@ -42,8 +42,8 @@ "run distro_bootcmd;" \ "fi;\0" -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ ST_STM32MP1_BOOTCMD \ STM32MP_PARTS_DEFAULT \ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index ce941d832a..fe2ba9a03b 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -13,7 +13,7 @@ #define LDS_BOARD_TEXT \ board/sysam/stmark2/sbf_dram_init.o (.text*) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kern_size=0x700000\0" \ "loadaddr=0x40001000\0" \ "-(rootfs)\0" \ diff --git a/include/configs/stout.h b/include/configs/stout.h index 977c0adc5f..ee1abe691b 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -35,7 +35,7 @@ /* Board Clock */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" /* SPL support */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d82e7e560..eae107fe5e 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -318,7 +318,7 @@ #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CONSOLE_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ MEM_LAYOUT_ENV_EXTRA_SETTINGS \ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index a2b6a1f57d..a62d1d3254 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -91,7 +91,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r=0x9fe00000\0" \ "kernel_addr_r=0x90000000\0" \ "ramdisk_addr_r=0xa0000000\0" \ diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h index 7af7b08eb4..e8a207f541 100644 --- a/include/configs/syzygy_hub.h +++ b/include/configs/syzygy_hub.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_SYZYGY_HUB_H #define __CONFIG_SYZYGY_HUB_H -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ "bitstream_image=download.bit\0" \ "loadbit_addr=0x1000000\0" \ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 30f8425582..855218a890 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -72,7 +72,7 @@ /* bootstrap in spi flash , u-boot + env + linux in nandflash */ #if defined(CONFIG_BOARD_AXM) -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 689914cb18..9b396e6e73 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -30,7 +30,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 2c668e0611..0fdb5a8160 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -65,7 +65,7 @@ #define INITRD_HIGH "ffffffff" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "fdt_high=" FDT_HIGH "\0" \ diff --git a/include/configs/ten64.h b/include/configs/ten64.h index 57724719a9..e86c163132 100644 --- a/include/configs/ten64.h +++ b/include/configs/ten64.h @@ -34,9 +34,9 @@ func(PXE, pxe, 0) #include -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "BOARD=ten64\0" \ "fdt_addr_r=0x90000000\0" \ "fdt_high=0xa0000000\0" \ diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index b57b1beaaf..746995179f 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -19,9 +19,9 @@ /* Environment settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "tftpdir=" DEF_ENV_TFTPDIR "\0" \ "eth_init=" DEF_ENV_ETH_INIT "\0" \ "ubuntu_part=" __stringify(DEF_ENV_UBUNTU_PART) "\0" \ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 76b496303f..9722b0db72 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -35,7 +35,7 @@ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ /* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/thuban.h b/include/configs/thuban.h index c8b27263e8..1753fa410d 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -31,7 +31,7 @@ #define EEPROM_ADDR_CHIP 0x120 /* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "hostname=thuban\0" \ "ubi_off=2048\0"\ "nand_img_size=0x400000\0" \ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 7becf1eb7c..8ba40546b2 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -35,7 +35,7 @@ /* Initial environment variables */ #define UBOOT_IMG_HEAD_SIZE 0x40 /* C80000 - 0x40 */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr=08007ffc0\0" \ "fdt_addr=0x94C00000\0" \ "fdt_high=0x9fffffff\0" diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 7b04292d21..2d9d2fd66e 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -12,7 +12,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV /* Clock Defines */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index ea45bba409..479ab46e4e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -106,7 +106,7 @@ "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ "rproc start ${dev_pmmc}\0" \ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ ENV_KS2_BOARD_SETTINGS \ DFUARGS \ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 64ec59d78e..49f4263e16 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -58,7 +58,7 @@ #include #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 37ab2e4467..e9723ed5b3 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -247,7 +247,7 @@ #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DEFAULT_LINUX_BOOT_ENV \ DEFAULT_MMC_TI_ARGS \ DEFAULT_FIT_TI_ARGS \ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 83abaeddf1..3795e6152f 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -44,8 +44,8 @@ # define EXTRA_ENV_USB #endif -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_image=uImage\0" \ "kernel_addr=0x2080000\0" \ "ramdisk_image=uramdisk.image.gz\0" \ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index 0f28690612..e007be8e45 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -28,7 +28,7 @@ #define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ "load_addr=0xa0000000\0" \ "kernel_addr_r=0x80080000\0" \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 7a1ad9544a..14d7730f67 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -197,7 +197,7 @@ /* set to a resonable value, changeable by user */ #define TQMA6_CMA_SIZE 160M -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "board=tqma6\0" \ "uimage=uImage\0" \ "zimage=zImage\0" \ diff --git a/include/configs/trats.h b/include/configs/trats.h index 3eac66539d..2067327918 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -54,7 +54,7 @@ "params.bin raw 0x38 0x8;" \ "/Image.itb ext4 0 2\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaduimage;" \ "if run loaddtb; then " \ diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 18fca09a38..9925531aba 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -55,7 +55,7 @@ "params.bin raw 0x38 0x8;" \ "/Image.itb ext4 0 2\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootk=" \ "run loaduimage;" \ "if run loaddtb; then " \ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h index fdb420ed87..3443c80d06 100644 --- a/include/configs/turris_mox.h +++ b/include/configs/turris_mox.h @@ -35,7 +35,7 @@ "lzmadec 0x5000000 0x5800000 && " \ "bootm 0x5800000" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr=0x4c00000\0" \ "scriptaddr=0x4d00000\0" \ "pxefile_addr_r=0x4e00000\0" \ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 52de4cdc78..47b220ff9e 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -80,7 +80,7 @@ "fi; " \ "bootz 0x1000000" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index fac8c1eeb4..f0092eff14 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -15,7 +15,7 @@ /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index d4c92233ac..5d7d734daa 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -19,7 +19,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* Linux only */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 7fee64029d..ecf0d2ac44 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -86,7 +86,7 @@ "run boot_common\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_addr_r_offset=0x05100000\0" \ "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \ "ramdisk_addr_r_offset=0x06000000\0" \ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 657dbadd33..b90e047955 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -43,6 +43,6 @@ #endif /* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ #endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 7f79c6342f..11706148f1 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -40,7 +40,7 @@ "pxefile_addr_r=0x70800000\0" \ "ramdisk_addr_r=0x73000000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \ "fdtfile=imx53-usbarmory.dtb\0" \ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index b03159805c..2e150276e7 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -25,7 +25,7 @@ #error Unknown DDR size - please add! #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "loadaddr=0x81000000\0" \ "spi_image_off=0x00100000\0" \ "console=ttyS0,115200\0" \ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 18ac6b2b08..7f3fa795af 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -34,7 +34,7 @@ #include /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "bootcmd_mfg=fastboot 0\0" \ diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 22dc364223..2cb076caba 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -43,7 +43,7 @@ #endif /* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ BOOTENV \ MEM_LAYOUT_ENV_SETTINGS \ "bootcmd_mfg=fastboot 0\0" \ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 30c1f5025b..87b8c5d57e 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -244,7 +244,7 @@ #include /* Default load addresses and names for the different payloads. */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index e8b6acf8b8..705a941e36 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -145,7 +145,7 @@ func(DHCP, dhcp, na) #include -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x60100000\0" \ "fdt_addr_r=0x60000000\0" \ "bootargs=console=tty0 console=ttyAMA0,38400n8\0" \ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 14e6b2bac9..0e0b3a7b59 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -44,7 +44,7 @@ "rdaddr=0x84080000\0" \ "ramdisk_addr_r=0x84080000\0" -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 1c1789ac3f..0698ae1d1c 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -45,7 +45,7 @@ /* Update the bootcommand according to our mapping for the VInCo platform */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "kernel_start=0x20000\0" \ "kernel_size=0x800000\0" \ "mmcblksize=0x200\0" \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 6923009d45..1e765439fa 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -20,7 +20,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ "splashpos=m,m\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 188180da54..0826e0bbe0 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -26,7 +26,7 @@ #define BOOT_SCR_STRING "source ${bootscriptaddr}\0" #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "bootscr_fitimage_name=bootscr\0" \ diff --git a/include/configs/x530.h b/include/configs/x530.h index 4cf41f52fd..fddf00d3d1 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -47,7 +47,7 @@ #include /* Keep device tree and initrd in low memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "fdt_high=0x10000000\0" \ "initrd_high=0x10000000\0" diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index d71108dd31..65a1e63e00 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -42,7 +42,7 @@ #define SPLASH_SETTINGS #endif -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ DISTRO_BOOTENV \ CONFIG_STD_DEVICES_SETTINGS \ SPLASH_SETTINGS \ diff --git a/include/configs/xea.h b/include/configs/xea.h index a3dc0c74eb..04ca5aa12a 100644 --- a/include/configs/xea.h +++ b/include/configs/xea.h @@ -27,7 +27,7 @@ /* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "bootmode=update\0" \ "bootpri=mmc_mmc\0" \ "bootsec=sf_swu\0" \ diff --git a/include/configs/xenguest_arm64.h b/include/configs/xenguest_arm64.h index 612436aeb4..bc268d25dc 100644 --- a/include/configs/xenguest_arm64.h +++ b/include/configs/xenguest_arm64.h @@ -9,12 +9,12 @@ #include #endif -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #undef CFG_SYS_SDRAM_BASE -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "loadimage=ext4load pvblock 0 0x90000000 /boot/Image;\0" \ "pvblockboot=run loadimage;" \ "booti 0x90000000 - 0x88000000;\0" diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 6ee6786e05..e70acd93ba 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -126,8 +126,8 @@ #include /* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV #endif diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index e1f95de3c3..23655a4752 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,11 +10,11 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h index 37bdb21462..424ead038e 100644 --- a/include/configs/xilinx_versal_net.h +++ b/include/configs/xilinx_versal_net.h @@ -123,8 +123,8 @@ #include /* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV \ DFU_ALT_INFO diff --git a/include/configs/xilinx_versal_net_mini.h b/include/configs/xilinx_versal_net_mini.h index 1939832a84..50bacc39ac 100644 --- a/include/configs/xilinx_versal_net_mini.h +++ b/include/configs/xilinx_versal_net_mini.h @@ -11,11 +11,11 @@ #ifndef __CONFIG_VERSAL_NET_MINI_H #define __CONFIG_VERSAL_NET_MINI_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #endif /* __CONFIG_VERSAL_NET_MINI_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f71cd66099..011f0034c5 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -173,16 +173,16 @@ #include /* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ ENV_MEM_LAYOUT_SETTINGS \ BOOTENV #endif /* SPL can't handle all huge variables - define just DFU */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -#undef CONFIG_EXTRA_ENV_SETTINGS -# define CONFIG_EXTRA_ENV_SETTINGS \ +#undef CFG_EXTRA_ENV_SETTINGS +# define CFG_EXTRA_ENV_SETTINGS \ "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \ "atf-uboot.ub ram 0x10000000 0x1000000;" \ "Image ram 0x80000 0x3f80000;" \ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h index 1c0ab25c64..9af0545664 100644 --- a/include/configs/xilinx_zynqmp_mini.h +++ b/include/configs/xilinx_zynqmp_mini.h @@ -10,11 +10,11 @@ #ifndef __CONFIG_ZYNQMP_MINI_H #define __CONFIG_ZYNQMP_MINI_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h index 3a7b7e03d6..918aa3d740 100644 --- a/include/configs/xilinx_zynqmp_r5.h +++ b/include/configs/xilinx_zynqmp_r5.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_ZYNQMP_R5_H #define __CONFIG_ZYNQMP_R5_H -#define CONFIG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS /* Serial drivers */ /* The following table includes the supported baudrates */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 9f1f2d90db..0d72008bb4 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -34,7 +34,7 @@ #define CONFIG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc6\0" \ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index d95178eb64..e372e90317 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -170,8 +170,8 @@ #endif /* CONFIG_SPL_BUILD */ /* Default environment */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#ifndef CFG_EXTRA_ENV_SETTINGS +#define CFG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x20000\0" \ "script_size_f=0x40000\0" \ "fdt_addr_r=0x1f00000\0" \ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index ac6e8c4ff8..a9bb5bb90a 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -12,7 +12,7 @@ #include /* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CFG_EXTRA_ENV_SETTINGS #undef CFG_SYS_INIT_RAM_ADDR #undef CFG_SYS_INIT_RAM_SIZE diff --git a/include/env_default.h b/include/env_default.h index 3b7685ee26..c0df39d62f 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -118,8 +118,8 @@ const char default_environment[] = { /* This is created in the Makefile */ CONFIG_EXTRA_ENV_TEXT #endif -#ifdef CONFIG_EXTRA_ENV_SETTINGS - CONFIG_EXTRA_ENV_SETTINGS +#ifdef CFG_EXTRA_ENV_SETTINGS + CFG_EXTRA_ENV_SETTINGS #endif "\0" #else /* CONFIG_USE_DEFAULT_ENV_FILE */ From 2aac334a9b57df2653da3a5d6169c473c760a14d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:51 -0500 Subject: [PATCH 244/424] global: Migrate CONFIG_FB_ADDR to CFG Perform a simple rename of CONFIG_FB_ADDR to CFG_FB_ADDR Signed-off-by: Tom Rini --- drivers/video/nexell_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index 5595796a67..af2698ffca 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -560,7 +560,7 @@ static int nx_display_bind(struct udevice *dev) /* Datasheet S5p4418: * Resolution up to 2048 x 1280, up to 12 Bit per color (HDMI) * Actual (max.) size is 0x1000000 because in U-Boot nanopi2-2016.01 - * "#define CONFIG_FB_ADDR 0x77000000" and next address is + * "#define CFG_FB_ADDR 0x77000000" and next address is * "#define BMP_LOAD_ADDR 0x78000000" */ plat->size = 0x1000000; From 4daffb58e6ccd36f9fdab8ef45cde8548226c4f6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:52 -0500 Subject: [PATCH 245/424] global: Migrate CONFIG_FEC_ENET_DEV to CFG Perform a simple rename of CONFIG_FEC_ENET_DEV to CFG_FEC_ENET_DEV Signed-off-by: Tom Rini --- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 2 +- board/freescale/mx6ullevk/mx6ullevk.c | 2 +- board/seeed/npi_imx6ull/npi_imx6ull.c | 2 +- board/variscite/dart_6ul/dart_6ul.c | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/mx6ul_14x14_evk.h | 6 +++--- include/configs/mx6ullevk.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/xpress.h | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 1eec048a66..570b5014db 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -281,7 +281,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif #ifdef CONFIG_USB_EHCI_MX6 diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index 86c11c7bd3..e247380647 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -110,7 +110,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif return 0; diff --git a/board/seeed/npi_imx6ull/npi_imx6ull.c b/board/seeed/npi_imx6ull/npi_imx6ull.c index eb9ee555c8..c610d2c306 100644 --- a/board/seeed/npi_imx6ull/npi_imx6ull.c +++ b/board/seeed/npi_imx6ull/npi_imx6ull.c @@ -100,7 +100,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif return 0; diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c index 7326daa179..98d8d1c312 100644 --- a/board/variscite/dart_6ul/dart_6ul.c +++ b/board/variscite/dart_6ul/dart_6ul.c @@ -147,7 +147,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(CFG_FEC_ENET_DEV); #endif #ifdef CONFIG_NAND_MXS diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index a8273a7fcd..63afa6e189 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -19,7 +19,7 @@ #endif /* CONFIG_SPL_BUILD */ /* ENET1 connects to base board and MUX with ESAI */ -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 #define CONFIG_FEC_MXC_PHYADDR 0x0 /* EEPROM */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 323703ac5c..c2ed9c7c56 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -18,7 +18,7 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 0 +#define CFG_FEC_ENET_DEV 0 #endif /* Environment settings */ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 938ab5ade9..7200c69bd9 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -100,7 +100,7 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 0 +#define CFG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 #endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 90c7884687..efc599f37a 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -121,11 +121,11 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 -#if (CONFIG_FEC_ENET_DEV == 0) +#if (CFG_FEC_ENET_DEV == 0) #define CONFIG_FEC_MXC_PHYADDR 0x2 -#elif (CONFIG_FEC_ENET_DEV == 1) +#elif (CFG_FEC_ENET_DEV == 1) #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 4a27fd2290..58d1a744ae 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -109,7 +109,7 @@ /* environment organization */ #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 #endif #endif diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index a12e34b6e6..979512c0a0 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -36,7 +36,7 @@ #define CONFIG_FEC_MXC_PHYADDR 0x1 #endif -#define CONFIG_FEC_ENET_DEV 1 +#define CFG_FEC_ENET_DEV 1 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 0d72008bb4..13f0ee62b8 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -31,7 +31,7 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_FEC_ENET_DEV 0 +#define CFG_FEC_ENET_DEV 0 #define CONFIG_FEC_MXC_PHYADDR 0x0 #define CFG_EXTRA_ENV_SETTINGS \ From fa760c3240c1498f20eaf5f4a7d6007d7df0c61a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:53 -0500 Subject: [PATCH 246/424] global: Migrate CONFIG_FEC_MXC_PHYADDR to CFG Perform a simple rename of CONFIG_FEC_MXC_PHYADDR to CFG_FEC_MXC_PHYADDR Signed-off-by: Tom Rini --- board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +- board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 2 +- doc/README.fec_mxc | 2 +- drivers/net/fec_mxc.c | 4 ++-- include/configs/aristainetos2.h | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_icore_mx8mp.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/liteboard.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 4 ++-- include/configs/nitrogen6x.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/somlabs_visionsom_6ull.h | 2 +- include/configs/tqma6_mba6.h | 2 +- include/configs/tqma6_wru4.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vining_2000.h | 2 +- include/configs/xpress.h | 2 +- 38 files changed, 40 insertions(+), 40 deletions(-) diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 9733a33ee2..1b08a2c5ab 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -214,7 +214,7 @@ int board_eth_init(struct bd_info *bis) gpio_set_value(CL_SOM_IMX7_ETH1_PHY_NRST, 1); /* MAC initialization */ return fecmxc_initialize_multi(bis, CL_SOM_IMX7_FEC_DEV_ID_PRI, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); } /* diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 7340a34402..9205d5ef6d 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -104,7 +104,7 @@ int board_eth_init(struct bd_info *bis) setup_fec(); ret = fecmxc_initialize_multi(bis, 1, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + CFG_FEC_MXC_PHYADDR, IMX_FEC_BASE); if (ret) printf("FEC%d MXC: %s:failed\n", 1, __func__); diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index 4e890d348f..2ccd4288d2 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -18,7 +18,7 @@ CONFIG_PHYLIB CONFIG_FEC_MXC_NO_ANEG Relevant only if PHYLIB not used. Skips auto-negotiation restart. -CONFIG_FEC_MXC_PHYADDR +CFG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 9cb235ad5e..ab52cc119f 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1086,8 +1086,8 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) int addr; addr = device_get_phy_addr(priv, dev); -#ifdef CONFIG_FEC_MXC_PHYADDR - addr = CONFIG_FEC_MXC_PHYADDR; +#ifdef CFG_FEC_MXC_PHYADDR + addr = CFG_FEC_MXC_PHYADDR; #endif phydev = phy_connect(priv->bus, addr, dev, priv->interface); diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index a6e9d2bb65..be1478ea8b 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -26,7 +26,7 @@ /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #ifdef CONFIG_IMX_HAB #define HAB_EXTRA_SETTINGS \ diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 63afa6e189..19c7fca03b 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -20,7 +20,7 @@ /* ENET1 connects to base board and MUX with ESAI */ #define CFG_FEC_ENET_DEV 1 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 /* EEPROM */ #define EEPROM_I2C_BUS 0 /* I2C0 */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 263981860e..caa1498ace 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -118,6 +118,6 @@ #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ /* Networking */ -#define CONFIG_FEC_MXC_PHYADDR -1 +#define CFG_FEC_MXC_PHYADDR -1 #endif /* __CGTQMX8_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 2d56d37f06..cde7d3c891 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -13,7 +13,7 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Network */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* ENET1 */ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index c66cf72187..47b76c9371 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -132,7 +132,7 @@ /* APBH DMA is required for NAND support */ /* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 0df61916b7..121b34ae96 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -19,7 +19,7 @@ /* Ethernet Configs */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index b6006c021d..162b0b8a69 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -40,7 +40,7 @@ /* MMC */ /* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 /* USB */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 00ce7fb62a..7785bdc7cb 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -136,7 +136,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index d28f3f1972..c364e06dc4 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -61,6 +61,6 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #endif diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index c6e3b105a8..1fea5b72de 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -13,7 +13,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index c3abcee40e..bbbd91776f 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -14,7 +14,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define DWC_NET_PHYADDR 1 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index ed4da0e69b..38ae5f1370 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -39,7 +39,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 4 +#define CFG_FEC_MXC_PHYADDR 4 #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index c40448715f..d9ce5d5d0f 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -24,7 +24,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #endif #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 8fed3e3196..eb7059f064 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -21,7 +21,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #endif #define CONFIG_MFG_ENV_SETTINGS \ diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index 30dd5af03b..b7397f6038 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -21,7 +21,7 @@ #if defined(CONFIG_FEC_MXC) #define PHY_ANEG_TIMEOUT 20000 -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #endif #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index d909bbbbcf..4dd51c7f1d 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -25,7 +25,7 @@ /* ENET1 Config */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 7200c69bd9..0b8781d7bf 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -102,7 +102,7 @@ #ifdef CONFIG_CMD_NET #define CFG_FEC_ENET_DEV 0 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #endif #endif diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 0deb7672f9..de6928d297 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -54,7 +54,7 @@ * Ethernet on SOC (FEC) */ #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #endif #define CFG_SYS_RTC_BUS_NUM 1 /* I2C2 */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 436f5f0059..6cc49378fe 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -31,7 +31,7 @@ #define CFG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } /* Ethernet Configuration */ -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200 quiet\0" \ diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index ef2111cd20..1cd0b3cf73 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -17,7 +17,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #define PHY_ANEG_TIMEOUT 20000 #endif diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 9d8737c194..3399cdd16f 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -93,7 +93,7 @@ /* Network */ #define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8372f979dc..c99d99abc1 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -115,7 +115,7 @@ /* Network */ -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index efc599f37a..5e3695ecc9 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -124,9 +124,9 @@ #define CFG_FEC_ENET_DEV 1 #if (CFG_FEC_ENET_DEV == 0) -#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CFG_FEC_MXC_PHYADDR 0x2 #elif (CFG_FEC_ENET_DEV == 1) -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 496a3164f4..aca15be64b 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -18,7 +18,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 6 +#define CFG_FEC_MXC_PHYADDR 6 /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 979512c0a0..4b47e4fbb3 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -33,7 +33,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #endif #define CFG_FEC_ENET_DEV 1 diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 66258a3ab7..e1f7b70031 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -98,6 +98,6 @@ /* Environment organization */ /* Ethernet Configuration */ -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #endif /* __CONFIG_H * */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 45fc6126c8..1cb8fa63e7 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -15,7 +15,7 @@ /* Network support */ -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index ac25991703..1d8709180c 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -21,7 +21,7 @@ /* ENET Config */ /* ENET1 */ #if defined(CONFIG_CMD_NET) -#define CONFIG_FEC_MXC_PHYADDR 1 +#define CFG_FEC_MXC_PHYADDR 1 #endif /* Initial environment variables */ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index e132805635..3418d4e2b5 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -66,7 +66,7 @@ #endif #ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CFG_FEC_MXC_PHYADDR 0x1 #endif #endif diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 899c218727..a5f14dc426 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CONFIG_FEC_MXC_PHYADDR 0x03 +#define CFG_FEC_MXC_PHYADDR 0x03 #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 4d8839b6e6..34c9b6a2f9 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -7,7 +7,7 @@ #define __CONFIG_TQMA6_WRU4_H /* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 0x01 +#define CFG_FEC_MXC_PHYADDR 0x01 /* UART */ #define CONFIG_MXC_UART_BASE UART4_BASE diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 0e0b3a7b59..d10b88f157 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -21,7 +21,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_FEC_MXC_PHYADDR 0 +#define CFG_FEC_MXC_PHYADDR 0 /* I2C Configs */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 1a71b300fc..c84353ebea 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -34,7 +34,7 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 13f0ee62b8..96996ac1f0 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -32,7 +32,7 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CFG_FEC_ENET_DEV 0 -#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CFG_FEC_MXC_PHYADDR 0x0 #define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ From 8938f59d545ab6e4ca0f265b008252822e747d30 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:54 -0500 Subject: [PATCH 247/424] global: Migrate CONFIG_FLASH_BR_PRELIM to CFG Perform a simple rename of CONFIG_FLASH_BR_PRELIM to CFG_FLASH_BR_PRELIM Signed-off-by: Tom Rini --- include/configs/p1_p2_rdb_pc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a353c16f74..f328eda416 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -188,7 +188,7 @@ #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE #endif -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ +#define CFG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 From c20d7cc95c512c7a57720c1481619db7baa4a263 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:55 -0500 Subject: [PATCH 248/424] global: Migrate CONFIG_FLASH_OR_PRELIM to CFG Perform a simple rename of CONFIG_FLASH_OR_PRELIM to CFG_FLASH_OR_PRELIM Signed-off-by: Tom Rini --- include/configs/p1_p2_rdb_pc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index f328eda416..41e7f53bd5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -191,7 +191,7 @@ #define CFG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) \ | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 +#define CFG_FLASH_OR_PRELIM 0xfc000ff7 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS} From 452e33efa8c98c5fa3bb11d1a8b66966df253cdc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:56 -0500 Subject: [PATCH 249/424] global: Migrate CONFIG_FM_PLAT_CLK_DIV to CFG Perform a simple rename of CONFIG_FM_PLAT_CLK_DIV to CFG_FM_PLAT_CLK_DIV Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/speed.c | 6 +++--- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a6e352ceab..eec071022e 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) #if defined(CONFIG_ARCH_T1024) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else @@ -377,7 +377,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_FM_PLAT_CLK_DIV +#ifndef CFG_FM_PLAT_CLK_DIV switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) { case 1: sys_info->freq_fman[0] = freq_c_pll[CFG_SYS_FM1_CLK]; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 246bcb9fe4..283181ec2d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -147,8 +147,8 @@ #define CONFIG_PME_PLAT_CLK_DIV 2 #define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_FM_PLAT_CLK_DIV 1 -#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CFG_FM_PLAT_CLK_DIV 1 +#define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV #define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL From 72fc26450493335ae191afdfcbbbb328b1df6b4d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:57 -0500 Subject: [PATCH 250/424] global: Migrate CONFIG_FPGA_DELAY to CFG Perform a simple rename of CONFIG_FPGA_DELAY to CFG_FPGA_DELAY Signed-off-by: Tom Rini --- README | 2 +- drivers/fpga/ACEX1K.c | 22 ++++++++++----------- drivers/fpga/cyclon2.c | 12 ++++++------ drivers/fpga/spartan2.c | 42 ++++++++++++++++++++--------------------- drivers/fpga/spartan3.c | 42 ++++++++++++++++++++--------------------- drivers/fpga/virtex2.c | 24 +++++++++++------------ 6 files changed, 72 insertions(+), 72 deletions(-) diff --git a/README b/README index a278825bbc..84086764d8 100644 --- a/README +++ b/README @@ -1018,7 +1018,7 @@ The following options need to be configured: will require a board or device specific function to be written. - CONFIG_FPGA_DELAY + CFG_FPGA_DELAY If defined, a function that provides delays in the FPGA configuration driver. diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index ca49ee40a7..4c00cdf0b5 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -17,11 +17,11 @@ /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). - * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * If there is a need to operate slower, define CFG_FPGA_DELAY in * the board config file to slow things down. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif #ifndef CFG_SYS_FPGA_WAIT @@ -137,7 +137,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) /* Wait for nSTATUS to be released (i.e. deasserted) */ ts = get_timer (0); /* get current time */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for STATUS to go high.\n"); (*fn->abort) (cookie); @@ -147,7 +147,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } while ((*fn->status) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Load the data */ while (bytecount < bsize) { @@ -172,13 +172,13 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) do { /* Deassert the clock */ (*fn->clk) (false, true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Write data */ (*fn->data) ((val & 0x01), true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (true, true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); val >>= 1; i --; } while (i > 0); @@ -189,7 +189,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) #endif } - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc (' '); /* terminate the dotted line */ @@ -210,9 +210,9 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) */ for (i = 0; i < 12; i++) { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ } diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 3eed461e1e..6e8a313db3 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -15,11 +15,11 @@ /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). - * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * If there is a need to operate slower, define CFG_FPGA_DELAY in * the board config file to slow things down. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif #ifndef CFG_SYS_FPGA_WAIT @@ -129,7 +129,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) /* Wait for nSTATUS to be asserted */ ts = get_timer(0); /* get current time */ do { - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts("** Timeout waiting for STATUS to go high.\n"); @@ -139,7 +139,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } while (!(*fn->status) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); ret = (*fn->write) (buf, bsize, true, cookie); if (ret) { @@ -151,7 +151,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) puts(" OK? ..."); #endif - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc(' '); /* terminate the dotted line */ diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 68971d9347..6eef87b78e 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -12,11 +12,11 @@ /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). - * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * If there is a need to operate slower, define CFG_FPGA_DELAY in * the board config file to slow things down. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif #ifndef CFG_SYS_FPGA_WAIT @@ -140,13 +140,13 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT and BUSY to go high */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ @@ -164,9 +164,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - Check the error bit? */ (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_CHECK_BUSY @@ -175,9 +175,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - we should have a check in here somewhere to * make sure we aren't busy forever... */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ @@ -194,7 +194,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->cs) (false, true, cookie); /* Deassert the chip select */ (*fn->wr) (false, true, cookie); /* Deassert the write pin */ @@ -207,9 +207,9 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) ret_val = FPGA_SUCCESS; while ((*fn->done) (cookie) == FPGA_FAIL) { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ @@ -330,7 +330,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Wait for INIT state (init low) */ ts = get_timer (0); /* get current time */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); return FPGA_FAIL; @@ -338,13 +338,13 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) } while (!(*fn->init) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT to go high */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); return FPGA_FAIL; @@ -365,13 +365,13 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) do { /* Deassert the clock */ (*fn->clk) (false, true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Write data */ (*fn->wr) ((val & 0x80), true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (true, true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); val <<= 1; i --; } while (i > 0); @@ -382,7 +382,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -395,9 +395,9 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) while (! (*fn->done) (cookie)) { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ putc ('*'); diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1d5073cb59..e892fa571f 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -17,11 +17,11 @@ /* Note: The assumption is that we cannot possibly run fast enough to * overrun the device (the Slave Parallel mode can free run at 50MHz). - * If there is a need to operate slower, define CONFIG_FPGA_DELAY in + * If there is a need to operate slower, define CFG_FPGA_DELAY in * the board config file to slow things down. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif #ifndef CFG_SYS_FPGA_WAIT @@ -145,13 +145,13 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT and BUSY to go high */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); (*fn->abort) (cookie); /* abort the burn */ @@ -169,9 +169,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - Check the error bit? */ (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_CHECK_BUSY @@ -180,9 +180,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - we should have a check in here somewhere to * make sure we aren't busy forever... */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ @@ -199,7 +199,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif } - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->cs) (false, true, cookie); /* Deassert the chip select */ (*fn->wr) (false, true, cookie); /* Deassert the write pin */ @@ -214,9 +214,9 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - we should have a check in here somewhere to * make sure we aren't busy forever... */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ @@ -337,7 +337,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* Wait for INIT state (init low) */ ts = get_timer (0); /* get current time */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to start.\n"); if (*fn->abort) @@ -347,13 +347,13 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) } while (!(*fn->init) (cookie)); /* Get ready for the burn */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT to go high */ do { - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); if (get_timer (ts) > CFG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for INIT to clear.\n"); if (*fn->abort) @@ -381,13 +381,13 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) do { /* Deassert the clock */ (*fn->clk) (false, true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Write data */ (*fn->wr) ((val & 0x80), true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); /* Assert the clock */ (*fn->clk) (true, true, cookie); - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); val <<= 1; i --; } while (i > 0); @@ -399,7 +399,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) } } - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -414,9 +414,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) /* XXX - we should have a check in here somewhere to * make sure we aren't busy forever... */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ - CONFIG_FPGA_DELAY (); + CFG_FPGA_DELAY (); (*fn->clk) (true, true, cookie); /* Assert the clock pin */ putc ('*'); diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index ed2a4163f6..fc99a5f483 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -22,13 +22,13 @@ /* * If the SelectMap interface can be overrun by the processor, enable - * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CONFIG_FPGA_DELAY in the board + * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board * configuration file and add board-specific support for checking BUSY status. * By default, assume that the SelectMap interface cannot be overrun. */ -#ifndef CONFIG_FPGA_DELAY -#define CONFIG_FPGA_DELAY() +#ifndef CFG_FPGA_DELAY +#define CFG_FPGA_DELAY() #endif /* @@ -196,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) } while (!(*fn->init)(cookie)); (*fn->pgm)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->clk) (*fn->clk)(true, true, cookie); @@ -205,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie) */ ts = get_timer(0); do { - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) { printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n", __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT); @@ -233,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, /* * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. */ - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); if (fn->cs) (*fn->cs)(false, true, cookie); if (fn->wr) @@ -269,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn, (*fn->wbulkdata)(&dummy, 1, true, cookie); } else { (*fn->wdata)(0xff, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } } @@ -335,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) #endif (*fn->wdata)(data[bytecount++], true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); /* * Cycle the clock pin */ (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); #ifdef CONFIG_SYS_FPGA_CHECK_BUSY @@ -472,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) for (bit = 7; bit >= 0; --bit) { unsigned char curr_bit = (curr_data >> bit) & 1; (*fn->wdata)(curr_bit, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(false, true, cookie); - CONFIG_FPGA_DELAY(); + CFG_FPGA_DELAY(); (*fn->clk)(true, true, cookie); } From e3e4efc04f8f49feb9486f4b5a8a28c917568718 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:58 -0500 Subject: [PATCH 251/424] global: Migrate CONFIG_FSL_PMIC_BITLEN to CFG Perform a simple rename of CONFIG_FSL_PMIC_BITLEN to CFG_FSL_PMIC_BITLEN Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 9bb7e39f2c..eace4dd7e4 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -42,7 +42,7 @@ int pmic_init(unsigned char bus) p->hw.spi.cs = CONFIG_FSL_PMIC_CS; p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; - p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN; + p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END; p->hw.spi.prepare_tx = pmic_spi_prepare_tx; #elif defined(CONFIG_POWER_I2C) diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 8ab1ee79a7..d4cca8d516 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -25,7 +25,7 @@ #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 +#define CFG_FSL_PMIC_BITLEN 32 /* * MMC Configs From eaaca4245e610e90afae88a70307535a48fefcb5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:03:59 -0500 Subject: [PATCH 252/424] global: Migrate CONFIG_FSL_PMIC_BUS to CFG Perform a simple rename of CONFIG_FSL_PMIC_BUS to CFG_FSL_PMIC_BUS Signed-off-by: Tom Rini --- board/freescale/mx51evk/mx51evk.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 86364acf8c..95edb35994 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -86,7 +86,7 @@ static void power_init(void) struct pmic *p; int ret; - ret = pmic_init(CONFIG_FSL_PMIC_BUS); + ret = pmic_init(CFG_FSL_PMIC_BUS); if (ret) return; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index d4cca8d516..1aaa76240d 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ -#define CONFIG_FSL_PMIC_BUS 0 +#define CFG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) From 3a8be4da79b0aafbfff1e1655ac89f9ab4cc4fcc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:00 -0500 Subject: [PATCH 253/424] global: Migrate CONFIG_FSL_PMIC_CLK to CFG Perform a simple rename of CONFIG_FSL_PMIC_CLK to CFG_FSL_PMIC_CLK Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index eace4dd7e4..a576d1570b 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -40,7 +40,7 @@ int pmic_init(unsigned char bus) #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; p->hw.spi.cs = CONFIG_FSL_PMIC_CS; - p->hw.spi.clk = CONFIG_FSL_PMIC_CLK; + p->hw.spi.clk = CFG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 1aaa76240d..ee0782ebfe 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -23,7 +23,7 @@ /* PMIC Controller */ #define CFG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 2500000 +#define CFG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CFG_FSL_PMIC_BITLEN 32 From f200d710d83a78e6309d88c365fc33cd322015df Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:01 -0500 Subject: [PATCH 254/424] global: Migrate CONFIG_FSL_PMIC_CS to CFG Perform a simple rename of CONFIG_FSL_PMIC_CS to CFG_FSL_PMIC_CS Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index a576d1570b..9ead212f38 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -39,7 +39,7 @@ int pmic_init(unsigned char bus) #if defined(CONFIG_POWER_SPI) p->interface = PMIC_SPI; - p->hw.spi.cs = CONFIG_FSL_PMIC_CS; + p->hw.spi.cs = CFG_FSL_PMIC_CS; p->hw.spi.clk = CFG_FSL_PMIC_CLK; p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index ee0782ebfe..15bc4c706f 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -22,7 +22,7 @@ /* PMIC Controller */ #define CFG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS 0 +#define CFG_FSL_PMIC_CS 0 #define CFG_FSL_PMIC_CLK 2500000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CFG_FSL_PMIC_BITLEN 32 From 193d7ab1e3396bac10f00d4b9b2d8dab6158390c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:02 -0500 Subject: [PATCH 255/424] global: Migrate CONFIG_FSL_PMIC_MODE to CFG Perform a simple rename of CONFIG_FSL_PMIC_MODE to CFG_FSL_PMIC_MODE Signed-off-by: Tom Rini --- drivers/power/power_fsl.c | 2 +- include/configs/mx51evk.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index 9ead212f38..9dc930fb30 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -41,7 +41,7 @@ int pmic_init(unsigned char bus) p->interface = PMIC_SPI; p->hw.spi.cs = CFG_FSL_PMIC_CS; p->hw.spi.clk = CFG_FSL_PMIC_CLK; - p->hw.spi.mode = CONFIG_FSL_PMIC_MODE; + p->hw.spi.mode = CFG_FSL_PMIC_MODE; p->hw.spi.bitlen = CFG_FSL_PMIC_BITLEN; p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END; p->hw.spi.prepare_tx = pmic_spi_prepare_tx; diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 15bc4c706f..740e357e00 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -24,7 +24,7 @@ #define CFG_FSL_PMIC_BUS 0 #define CFG_FSL_PMIC_CS 0 #define CFG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) +#define CFG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CFG_FSL_PMIC_BITLEN 32 /* From da495570030b07483af1d84eaba995b9bb43de3f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:03 -0500 Subject: [PATCH 256/424] global: Migrate CONFIG_FSL_SERDES1 to CFG Perform a simple rename of CONFIG_FSL_SERDES1 to CFG_FSL_SERDES1 Signed-off-by: Tom Rini --- board/freescale/mpc837xerdb/mpc837xerdb.c | 4 ++-- include/configs/MPC837XERDB.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 4a14554026..9c08a2bfef 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -146,7 +146,7 @@ int board_early_init_f(void) /* we check only part num, and don't look for CPU revisions */ switch (PARTID_NO_E(spridr)) { case SPR_8377: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); @@ -156,7 +156,7 @@ int board_early_init_f(void) FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index fad161597e..9fc12dabb5 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -149,7 +149,7 @@ #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) /* SERDES */ -#define CONFIG_FSL_SERDES1 0xe3000 +#define CFG_FSL_SERDES1 0xe3000 #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ From 315390e4674e8cff60becca9aa882570d780d8ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:04 -0500 Subject: [PATCH 257/424] global: Migrate CONFIG_FSL_SERDES2 to CFG Perform a simple rename of CONFIG_FSL_SERDES2 to CFG_FSL_SERDES2 Signed-off-by: Tom Rini --- board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +++--- include/configs/MPC837XERDB.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 9c08a2bfef..8b1bfe0a9f 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -148,17 +148,17 @@ int board_early_init_f(void) case SPR_8377: fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CFG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, + fsl_setup_serdes(CFG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 9fc12dabb5..07c989d989 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -150,7 +150,7 @@ /* SERDES */ #define CFG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 +#define CFG_FSL_SERDES2 0xe3100 /* I2C */ #define CFG_SYS_I2C_NOPROBES { {0, 0x51} } From bf095622228e150c49613db510f1f334c9192c19 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:05 -0500 Subject: [PATCH 258/424] global: Migrate CONFIG_FTRTC010_EXTCLK to CFG Perform a simple rename of CONFIG_FTRTC010_EXTCLK to CFG_FTRTC010_EXTCLK Signed-off-by: Tom Rini --- drivers/rtc/ftrtc010.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c index 67c2b6e320..768c8cdd50 100644 --- a/drivers/rtc/ftrtc010.c +++ b/drivers/rtc/ftrtc010.c @@ -82,7 +82,7 @@ int rtc_get(struct rtc_time *tmp) #ifdef CONFIG_FTRTC010_PCLK now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; -#else /* CONFIG_FTRTC010_EXTCLK */ +#else /* CFG_FTRTC010_EXTCLK */ now = ftrtc010_time() + readl(&rtc->record); #endif From d2cd9f4121f5638dae4030f35826f1d6624a2c00 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:06 -0500 Subject: [PATCH 259/424] global: Migrate CONFIG_FTRTC010_PCLK to CFG Perform a simple rename of CONFIG_FTRTC010_PCLK to CFG_FTRTC010_PCLK Signed-off-by: Tom Rini --- drivers/rtc/ftrtc010.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c index 768c8cdd50..e384922f47 100644 --- a/drivers/rtc/ftrtc010.c +++ b/drivers/rtc/ftrtc010.c @@ -80,7 +80,7 @@ int rtc_get(struct rtc_time *tmp) debug("%s(): record register: %x\n", __func__, readl(&rtc->record)); -#ifdef CONFIG_FTRTC010_PCLK +#ifdef CFG_FTRTC010_PCLK now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; #else /* CFG_FTRTC010_EXTCLK */ now = ftrtc010_time() + readl(&rtc->record); From e06b9b8d75f3f367db115fbcd902ee2d22ddcdba Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:08 -0500 Subject: [PATCH 260/424] global: Migrate CONFIG_I2C_MULTI_BUS to CFG Perform a simple rename of CONFIG_I2C_MULTI_BUS to CFG_I2C_MULTI_BUS Signed-off-by: Tom Rini --- README | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/sniper.h | 2 +- include/configs/tqma6.h | 2 +- include/i2c.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/README b/README index 84086764d8..05618352fa 100644 --- a/README +++ b/README @@ -955,7 +955,7 @@ The following options need to be configured: You should define these to the GPIO value as given directly to the generic GPIO functions. - CONFIG_I2C_MULTI_BUS + CFG_I2C_MULTI_BUS This option allows the use of multiple I2C buses, each of which must have a controller. At any point in time, only one bus is diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index efeb7bf100..af7cb3513f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -29,7 +29,7 @@ #endif /* CONFIG_MTD_RAW_NAND */ /* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS +#define CFG_I2C_MULTI_BUS /* DSS Support */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h index eaee8dd373..45a3102aee 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -38,7 +38,7 @@ * I2C */ -#define CONFIG_I2C_MULTI_BUS +#define CFG_I2C_MULTI_BUS /* * Input diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 14d7730f67..cb5f7fc25a 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -28,7 +28,7 @@ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K /* I2C Configs */ -#define CONFIG_I2C_MULTI_BUS +#define CFG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/i2c.h b/include/i2c.h index 51390f8fd8..3811b26c08 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -930,7 +930,7 @@ unsigned int i2c_get_bus_speed(void); * only for backwardcompatibility, should go away if we switched * completely to new multibus support. */ -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CONFIG_I2C_MULTI_BUS) +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) || defined(CFG_I2C_MULTI_BUS) # if !defined(CFG_SYS_MAX_I2C_BUS) # define CFG_SYS_MAX_I2C_BUS 2 # endif From 45ede979e86573e8b9362ceb1bfa9c397979ae1a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:09 -0500 Subject: [PATCH 261/424] global: Migrate CONFIG_I2C_MVTWSI_BASE0 to CFG Perform a simple rename of CONFIG_I2C_MVTWSI_BASE0 to CFG_I2C_MVTWSI_BASE0 Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- arch/arm/mach-kirkwood/include/mach/config.h | 2 +- drivers/i2c/mvtwsi.c | 6 +++--- include/configs/db-88f6720.h | 2 +- include/configs/db-88f6820-gp.h | 2 +- include/configs/db-mv784mp-gp.h | 2 +- include/configs/ds414.h | 2 +- include/configs/maxbcm.h | 2 +- include/configs/theadorable.h | 2 +- 9 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 241b44928a..2c2d6b7d31 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -8,7 +8,7 @@ #include #ifdef CONFIG_I2C0_ENABLE -#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE +#define CFG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE #endif #ifdef CONFIG_I2C1_ENABLE #define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index a6de767629..fbef9c99b1 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -24,7 +24,7 @@ #include -#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 KW_TWSI_BASE #define MV_UART_CONSOLE_BASE KW_UART0_BASE #define MV_SATA_BASE KW_SATA_BASE #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index a9c7d6e1bc..076525d6c4 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -197,9 +197,9 @@ inline uint calc_tick(uint speed) static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { -#ifdef CONFIG_I2C_MVTWSI_BASE0 +#ifdef CFG_I2C_MVTWSI_BASE0 case 0: - return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; + return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE0; #endif #ifdef CONFIG_I2C_MVTWSI_BASE1 case 1: @@ -737,7 +737,7 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 10000); } -#ifdef CONFIG_I2C_MVTWSI_BASE0 +#ifdef CFG_I2C_MVTWSI_BASE0 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_read, twsi_i2c_write, twsi_i2c_set_bus_speed, diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index ef9c457e10..54de2d0d83 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -17,7 +17,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 6dbf582d73..2cbe4eb440 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -11,7 +11,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* Environment in SPI NOR flash */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index bf8b35102a..5c6d7fa1b7 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -13,7 +13,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* USB/EHCI configuration */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h index e69883ba73..9446acba79 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -17,7 +17,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* * mv-common.h should be defined after CMD configs since it used them diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 5ad945b558..413597e09b 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -19,7 +19,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE /* SPI NOR flash default params, used by sf commands */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 9722b0db72..412698d3fe 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -25,7 +25,7 @@ */ /* I2C */ -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE +#define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ From 35661f86eb0e647953d6a588059d1387b5be5ae5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:10 -0500 Subject: [PATCH 262/424] global: Migrate CONFIG_I2C_MVTWSI_BASE1 to CFG Perform a simple rename of CONFIG_I2C_MVTWSI_BASE1 to CFG_I2C_MVTWSI_BASE1 Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-sunxi/i2c.h | 2 +- drivers/i2c/mvtwsi.c | 6 +++--- include/configs/theadorable.h | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h index 2c2d6b7d31..e3dcfdf370 100644 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -11,7 +11,7 @@ #define CFG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE #endif #ifdef CONFIG_I2C1_ENABLE -#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE +#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE #endif #ifdef CONFIG_R_I2C_ENABLE #define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 076525d6c4..2822749971 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -201,9 +201,9 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) case 0: return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE0; #endif -#ifdef CONFIG_I2C_MVTWSI_BASE1 +#ifdef CFG_I2C_MVTWSI_BASE1 case 1: - return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; + return (struct mvtwsi_registers *)CFG_I2C_MVTWSI_BASE1; #endif #ifdef CONFIG_I2C_MVTWSI_BASE2 case 2: @@ -743,7 +743,7 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) #endif -#ifdef CONFIG_I2C_MVTWSI_BASE1 +#ifdef CFG_I2C_MVTWSI_BASE1 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, twsi_i2c_read, twsi_i2c_write, twsi_i2c_set_bus_speed, diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index 412698d3fe..2ce92845f1 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -26,7 +26,7 @@ /* I2C */ #define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE +#define CFG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE /* USB/EHCI configuration */ From cdbf8459d017143dba1e798fecbd1046f98a7ece Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:11 -0500 Subject: [PATCH 263/424] global: Migrate CONFIG_ICS307_REFCLK_HZ to CFG Perform a simple rename of CONFIG_ICS307_REFCLK_HZ to CFG_ICS307_REFCLK_HZ Signed-off-by: Tom Rini --- board/freescale/common/ics307_clk.c | 4 ++-- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 01662d36e9..5f95571d24 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -50,7 +50,7 @@ static u8 ics307_s_to_od[] = { */ unsigned long ics307_sysclk_calculator(unsigned long out_freq) { - const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; unsigned long tmp_out, diff, result = 0; int found = 0; @@ -101,7 +101,7 @@ unsigned long ics307_sysclk_calculator(unsigned long out_freq) */ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) { - const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + const unsigned long input_freq = CFG_ICS307_REFCLK_HZ; unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); unsigned long rdw = cw2 & 0x7F; unsigned long od = ics307_s_to_od[cw0 & 0x7]; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 7f332cf2e3..3b98d25aa4 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -13,7 +13,7 @@ #include -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ /* High Level Configuration Options */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index d6dd9c07b7..60c2947bfc 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -13,7 +13,7 @@ #include -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ /* High Level Configuration Options */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 22cbf92efb..01a9f43cba 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -12,7 +12,7 @@ #include -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SDCARD From e6014294dd5930f3573b9b5883349b209df6f3e2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:12 -0500 Subject: [PATCH 264/424] global: Migrate CONFIG_IMX6_PWM_PER_CLK to CFG Perform a simple rename of CONFIG_IMX6_PWM_PER_CLK to CFG_IMX6_PWM_PER_CLK Signed-off-by: Tom Rini --- drivers/pwm/pwm-imx.c | 2 +- include/configs/vining_2000.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 9b8a8c189d..8fbb40cc27 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -76,7 +76,7 @@ int pwm_imx_get_parms(int period_ns, int duty_ns, unsigned long *period_c, * value here as a define. Replace it when we have the clock * framework. */ - c = CONFIG_IMX6_PWM_PER_CLK; + c = CFG_IMX6_PWM_PER_CLK; c = c * period_ns; do_div(c, 1000000000); *period_c = c; diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index c84353ebea..cdd2eeef0a 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -43,7 +43,7 @@ #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif -#define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CFG_IMX6_PWM_PER_CLK 66000000 #ifdef CONFIG_ENV_IS_IN_MMC /* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ From 7b5f75cffabaa475add3c2f66d5ca0aa95588b5a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:13 -0500 Subject: [PATCH 265/424] global: Migrate CONFIG_IRAM_BASE to CFG Perform a simple rename of CONFIG_IRAM_BASE to CFG_IRAM_BASE Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-rockchip/bootrom.h | 2 +- include/configs/px30_common.h | 2 +- include/configs/rk3066_common.h | 2 +- include/configs/rk3128_common.h | 2 +- include/configs/rk3188_common.h | 2 +- include/configs/rk322x_common.h | 2 +- include/configs/rk3288_common.h | 2 +- include/configs/rk3308_common.h | 2 +- include/configs/rk3328_common.h | 2 +- include/configs/rk3368_common.h | 2 +- include/configs/rk3399_common.h | 2 +- include/configs/rk3568_common.h | 2 +- include/configs/rv1108_common.h | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 0da78f30b6..4276a0f681 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -57,6 +57,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; /** * Locations of the boot-device identifier in SRAM */ -#define BROM_BOOTSOURCE_ID_ADDR (CONFIG_IRAM_BASE + 0x10) +#define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10) #endif diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 003686930a..3f1595cdc9 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -9,7 +9,7 @@ #include "rockchip-common.h" /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ -#define CONFIG_IRAM_BASE 0xff020000 +#define CFG_IRAM_BASE 0xff020000 #define GICD_BASE 0xff131000 #define GICC_BASE 0xff132000 diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h index c4758e148b..1a6d3678df 100644 --- a/include/configs/rk3066_common.h +++ b/include/configs/rk3066_common.h @@ -9,7 +9,7 @@ #include #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (1024UL << 20UL) diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 5b0ec37000..8aa17bfbd3 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -10,7 +10,7 @@ #define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 /* RAW SD card / eMMC locations. */ diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 58f491c2f3..ac9195672f 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -9,7 +9,7 @@ #include #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 /* spl size 32kb sram - 2kb bootrom */ diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index b95268df87..fcaf9c52c4 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -10,7 +10,7 @@ #define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index d3b8a5150f..5f29432be1 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -11,7 +11,7 @@ #define CFG_SYS_HZ_CLOCK 24000000 -#define CONFIG_IRAM_BASE 0xff700000 +#define CFG_IRAM_BASE 0xff700000 /* RAW SD card / eMMC locations. */ diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index bc03e113fe..55a0dfecb2 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xfff80000 +#define CFG_IRAM_BASE 0xfff80000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 85d2186f23..fadcb93a5f 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xff090000 +#define CFG_IRAM_BASE 0xff090000 /* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 1763625051..9aa256b595 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_IRAM_BASE 0xff8c0000 +#define CFG_IRAM_BASE 0xff8c0000 #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00500000\0" \ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 2278b6215d..95cb27c895 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xff8c0000 +#define CFG_IRAM_BASE 0xff8c0000 /* FAT sd card locations. */ #define CFG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 750f16d039..ae360105d5 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -8,7 +8,7 @@ #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0xfdcc0000 +#define CFG_IRAM_BASE 0xfdcc0000 #define CFG_SYS_SDRAM_BASE 0 #define SDRAM_MAX_SIZE 0xf0000000 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 6e17b23b62..63551b47e2 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -8,7 +8,7 @@ #include #include "rockchip-common.h" -#define CONFIG_IRAM_BASE 0x10080000 +#define CFG_IRAM_BASE 0x10080000 #define CFG_SYS_TIMER_RATE (24 * 1000 * 1000) /* TIMER1,initialized by ddr initialize code */ From 7201b769784fd474f7e24c3fd2048588c69fb285 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:14 -0500 Subject: [PATCH 266/424] global: Migrate CONFIG_IRAM_TOP to CFG Perform a simple rename of CONFIG_IRAM_TOP to CFG_IRAM_TOP Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 2 +- arch/arm/mach-exynos/sec_boot.S | 2 +- include/configs/exynos5420-common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 1ff5fcac1b..9225d2cc1f 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -51,7 +51,7 @@ enum { #ifdef CONFIG_EXYNOS5420 /* Address for relocating helper code (Last 4 KB of IRAM) */ -#define EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) +#define EXYNOS_RELOCATE_CODE_BASE (CFG_IRAM_TOP - 0x1000) /* * Power up secondary CPUs. diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S index 40c07209e4..1303544d83 100644 --- a/arch/arm/mach-exynos/sec_boot.S +++ b/arch/arm/mach-exynos/sec_boot.S @@ -21,7 +21,7 @@ relocate_wait_code: .ltorg /* * Secondary core waits here until Primary wake it up. - * Below code is copied to (CONFIG_IRAM_TOP - 0x1000) + * Below code is copied to (CFG_IRAM_TOP - 0x1000) * This is a workaround code which is supposed to act as a * substitute/supplement to the iROM code. * diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 934a4ef9d1..99ab1a174f 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_IRAM_TOP 0x02074000 +#define CFG_IRAM_TOP 0x02074000 #define CONFIG_PHY_IRAM_BASE 0x02020000 From 21bd204239ff6cf62d6aca1f8ac4941702030e51 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:25 -0500 Subject: [PATCH 267/424] global: Migrate CONFIG_KSNET_CPSW_NUM_PORTS to CFG Perform a simple rename of CONFIG_KSNET_CPSW_NUM_PORTS to CFG_KSNET_CPSW_NUM_PORTS Signed-off-by: Tom Rini --- arch/arm/include/asm/ti-common/keystone_net.h | 2 +- include/configs/k2e_evm.h | 2 +- include/configs/k2g_evm.h | 2 +- include/configs/k2hk_evm.h | 2 +- include/configs/k2l_evm.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 0852ce80a6..21cac6ea31 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -117,7 +117,7 @@ struct mac_sl_cfg { #define CPSW_CTL_VLAN_AWARE BIT(1) #define CPSW_CTL_FIFO_LOOPBACK BIT(0) -#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_CPSW_NUM_PORTS CFG_KSNET_CPSW_NUM_PORTS #define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) #ifdef CONFIG_KSNET_NETCP_V1_0 diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 1283f450b3..929c9a26de 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -37,6 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 9 +#define CFG_KSNET_CPSW_NUM_PORTS 9 #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index fd3708ba81..d0634a99f4 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -51,7 +51,7 @@ "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 2 +#define CFG_KSNET_CPSW_NUM_PORTS 2 #define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ #define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 36e3c59d1c..05b4a3c204 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -37,6 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CFG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h index cb7b036781..b1b839b504 100644 --- a/include/configs/k2l_evm.h +++ b/include/configs/k2l_evm.h @@ -37,6 +37,6 @@ #define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS /* Network */ -#define CONFIG_KSNET_CPSW_NUM_PORTS 5 +#define CFG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2L_EVM_H */ From f060d1885c4468f8a2723cd172c2144259b638f0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:26 -0500 Subject: [PATCH 268/424] global: Migrate CONFIG_KSNET_MAC_ID_BASE to CFG Perform a simple rename of CONFIG_KSNET_MAC_ID_BASE to CFG_KSNET_MAC_ID_BASE Signed-off-by: Tom Rini --- arch/arm/include/asm/ti-common/keystone_net.h | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index 21cac6ea31..f191c909f4 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -49,7 +49,7 @@ #define KEYSTONE2_EMAC_GIG_ENABLE -#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE +#define MAC_ID_BASE_ADDR CFG_KSNET_MAC_ID_BASE /* MDIO module input frequency */ #ifdef CONFIG_SOC_K2G diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 479ab46e4e..e46d635ca0 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -47,7 +47,7 @@ #define CFG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) /* Keystone net */ -#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE From d4e4bc898b7d14576f0c3b281d0c552954ee0dda Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:27 -0500 Subject: [PATCH 269/424] global: Migrate CONFIG_KSNET_NETCP_BASE to CFG Perform a simple rename of CONFIG_KSNET_NETCP_BASE to CFG_KSNET_NETCP_BASE Signed-off-by: Tom Rini --- arch/arm/include/asm/ti-common/keystone_net.h | 8 ++++---- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index f191c909f4..bedbcdc8ba 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -18,7 +18,7 @@ /* EMAC */ #ifdef CONFIG_KSNET_NETCP_V1_0 -#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define GBETH_BASE (CFG_KSNET_NETCP_BASE + 0x00090000) #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) @@ -32,7 +32,7 @@ #elif defined CONFIG_KSNET_NETCP_V1_5 -#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define GBETH_BASE (CFG_KSNET_NETCP_BASE + 0x00200000) #define CPGMACSL_REG_RX_PRI_MAP 0x020 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) @@ -190,14 +190,14 @@ struct mac_sl_cfg { /* PSS */ #ifdef CONFIG_KSNET_NETCP_V1_0 -#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_REG_ADDR (CFG_KSNET_NETCP_BASE + 0x604) #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 #define hw_config_streaming_switch()\ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); #elif defined CONFIG_KSNET_NETCP_V1_5 -#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_REG_ADDR (CFG_KSNET_NETCP_BASE + 0x500) #define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 #define hw_config_streaming_switch()\ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index e46d635ca0..c21fabc36e 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -48,7 +48,7 @@ /* Keystone net */ #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR -#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES From d036606142a0164646ace465a20ba5e632de887e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:28 -0500 Subject: [PATCH 270/424] global: Migrate CONFIG_KSNET_SERDES_LANES_PER_SGMII to CFG Perform a simple rename of CONFIG_KSNET_SERDES_LANES_PER_SGMII to CFG_KSNET_SERDES_LANES_PER_SGMII Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 4 ++-- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 679a0450f1..114eb854d7 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -372,12 +372,12 @@ static void keystone2_net_serdes_setup(void) { ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); + CFG_KSNET_SERDES_LANES_PER_SGMII); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, &ks2_serdes_sgmii_156p25mhz, - CONFIG_KSNET_SERDES_LANES_PER_SGMII); + CFG_KSNET_SERDES_LANES_PER_SGMII); #endif /* wait till setup */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index c21fabc36e..cb4ea394eb 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -51,7 +51,7 @@ #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE -#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES +#define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES /* EEPROM definitions */ From 81d239aede3ccab6ccdac70478d99d064baabdb0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:29 -0500 Subject: [PATCH 271/424] global: Migrate CONFIG_KSNET_SERDES_SGMII2_BASE to CFG Perform a simple rename of CONFIG_KSNET_SERDES_SGMII2_BASE to CFG_KSNET_SERDES_SGMII2_BASE Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 114eb854d7..90b8821a2c 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -375,7 +375,7 @@ static void keystone2_net_serdes_setup(void) CFG_KSNET_SERDES_LANES_PER_SGMII); #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + ks2_serdes_init(CFG_KSNET_SERDES_SGMII2_BASE, &ks2_serdes_sgmii_156p25mhz, CFG_KSNET_SERDES_LANES_PER_SGMII); #endif diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index cb4ea394eb..1429faa534 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -50,7 +50,7 @@ #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE -#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE +#define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES /* EEPROM definitions */ From e9f508cf019ae3056747ee2560b66267de6a6bea Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:30 -0500 Subject: [PATCH 272/424] global: Migrate CONFIG_KSNET_SERDES_SGMII_BASE to CFG Perform a simple rename of CONFIG_KSNET_SERDES_SGMII_BASE to CFG_KSNET_SERDES_SGMII_BASE Signed-off-by: Tom Rini --- drivers/net/ti/keystone_net.c | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index 90b8821a2c..89b04b6fbd 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -370,7 +370,7 @@ struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { #ifndef CONFIG_SOC_K2G static void keystone2_net_serdes_setup(void) { - ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + ks2_serdes_init(CFG_KSNET_SERDES_SGMII_BASE, &ks2_serdes_sgmii_156p25mhz, CFG_KSNET_SERDES_LANES_PER_SGMII); diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 1429faa534..7142d30a59 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -49,7 +49,7 @@ /* Keystone net */ #define CFG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CFG_KSNET_NETCP_BASE KS2_NETCP_BASE -#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CFG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE #define CFG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CFG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES From 1cd60b3cc021fb8bfa537a393151871515b512b2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:31 -0500 Subject: [PATCH 273/424] global: Migrate CONFIG_LEGACY_BOOTCMD_ENV to CFG Perform a simple rename of CONFIG_LEGACY_BOOTCMD_ENV to CFG_LEGACY_BOOTCMD_ENV Signed-off-by: Tom Rini --- include/configs/pic32mzdask.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 60c7473275..0ae4fc55a9 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -52,7 +52,7 @@ "fdt_addr_r=0x89d00000\0" \ "scriptaddr=0x88300000\0" \ -#define CONFIG_LEGACY_BOOTCMD_ENV \ +#define CFG_LEGACY_BOOTCMD_ENV \ "legacy_bootcmd= " \ "if load mmc 0 ${scriptaddr} uEnv.txt; then " \ "env import -tr ${scriptaddr} ${filesize}; " \ @@ -71,7 +71,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ - CONFIG_LEGACY_BOOTCMD_ENV \ + CFG_LEGACY_BOOTCMD_ENV \ BOOTENV #endif /* __PIC32MZDASK_CONFIG_H */ From 77db07ce1c8ca359c500f66d38e0d9d572d214a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:32 -0500 Subject: [PATCH 274/424] global: Migrate CONFIG_LOWPOWER_ADDR to CFG Perform a simple rename of CONFIG_LOWPOWER_ADDR to CFG_LOWPOWER_ADDR Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 2 +- include/configs/exynos5420-common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 9225d2cc1f..02a79962af 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -161,7 +161,7 @@ static void secondary_cores_configure(void) /* set lowpower flag and address */ writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); - writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR); + writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 99ab1a174f..164cdb0fa1 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -16,6 +16,6 @@ * Low Power settings */ #define CONFIG_LOWPOWER_FLAG 0x02020028 -#define CONFIG_LOWPOWER_ADDR 0x0202002C +#define CFG_LOWPOWER_ADDR 0x0202002C #endif /* __CONFIG_EXYNOS5420_H */ From 8000ac874c727004958d0fdec250681ba6b236f9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:33 -0500 Subject: [PATCH 275/424] global: Migrate CONFIG_LOWPOWER_FLAG to CFG Perform a simple rename of CONFIG_LOWPOWER_FLAG to CFG_LOWPOWER_FLAG Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 4 ++-- include/configs/exynos5420-common.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 02a79962af..243b5c80c9 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -73,7 +73,7 @@ static void low_power_start(void) reg_val = readl(EXYNOS5420_SPARE_BASE); if (reg_val != CPU_RST_FLAG_VAL) { - writel(0x0, CONFIG_LOWPOWER_FLAG); + writel(0x0, CFG_LOWPOWER_FLAG); branch_bx(0x0); } @@ -160,7 +160,7 @@ static void secondary_cores_configure(void) writel(0x0, (EXYNOS_RELOCATE_CODE_BASE + 0x1C)); /* set lowpower flag and address */ - writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG); + writel(CPU_RST_FLAG_VAL, CFG_LOWPOWER_FLAG); writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index 164cdb0fa1..bd43efa553 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -15,7 +15,7 @@ /* * Low Power settings */ -#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CFG_LOWPOWER_FLAG 0x02020028 #define CFG_LOWPOWER_ADDR 0x0202002C #endif /* __CONFIG_EXYNOS5420_H */ From dff9de5c2c1eb0a4b62f1ea67dee3f0db117bc1a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:34 -0500 Subject: [PATCH 276/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY to CFG_LPC32XX_NAND_MLC_BUSY_DELAY Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index a884c65d18..dd3f35def0 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -142,7 +142,7 @@ static void lpc32xx_nand_init(void) writel( clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | + clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 010da1531f..a1ecd8ceef 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -28,7 +28,7 @@ */ #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 -#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 +#define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 From ea93286e5f068b85dd3a0d05bef534ad86d3d16f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:35 -0500 Subject: [PATCH 277/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_NAND_TA to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_NAND_TA to CFG_LPC32XX_NAND_MLC_NAND_TA Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index dd3f35def0..cd3831b5ff 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -143,7 +143,7 @@ static void lpc32xx_nand_init(void) writel( clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | + clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index a1ecd8ceef..d345382545 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -29,7 +29,7 @@ #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 -#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 +#define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 From ab8c6e370c6407a8b6117d933cc4ece5ad5383be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:36 -0500 Subject: [PATCH 278/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_RD_HIGH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_RD_HIGH to CFG_LPC32XX_NAND_MLC_RD_HIGH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index cd3831b5ff..388be16e2e 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -144,7 +144,7 @@ static void lpc32xx_nand_init(void) clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | + clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index d345382545..3959051a4c 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -30,7 +30,7 @@ #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 -#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 +#define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 From 3c35c036add440f73cfb24cbfab7098e949c2167 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:37 -0500 Subject: [PATCH 279/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_RD_LOW to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_RD_LOW to CFG_LPC32XX_NAND_MLC_RD_LOW Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 388be16e2e..e75ed1f2ae 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -145,7 +145,7 @@ static void lpc32xx_nand_init(void) clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | + clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 3959051a4c..1a4617c5c0 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -31,7 +31,7 @@ #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 -#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 +#define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 From 259ec2ce11f47a1a33675e258d81bbe72429945e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:38 -0500 Subject: [PATCH 280/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY to CFG_LPC32XX_NAND_MLC_TCEA_DELAY Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index e75ed1f2ae..088fdb7981 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -141,7 +141,7 @@ static void lpc32xx_nand_init(void) clk = get_hclk_clk_rate(); writel( - clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | + clkdiv(CFG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) | clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) | clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 1a4617c5c0..34af515037 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -27,7 +27,7 @@ * NAND chip timings for FIXME: which one? */ -#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 +#define CFG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 #define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 From 196690dfdadeb99ee7903e121bce10908b9ec6fb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:39 -0500 Subject: [PATCH 281/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_WR_HIGH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_HIGH to CFG_LPC32XX_NAND_MLC_WR_HIGH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 088fdb7981..31a9a22ba3 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -146,7 +146,7 @@ static void lpc32xx_nand_init(void) clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | + clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); } diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 34af515037..c67a0bb6e1 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -32,7 +32,7 @@ #define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818 #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 -#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 +#define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 /* From 39fa17718f4ccdc252ca96a56186931b4fd6f3fb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:40 -0500 Subject: [PATCH 282/424] global: Migrate CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_MLC_WR_LOW to CFG_LPC32XX_NAND_MLC_WR_LOW Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 2 +- include/configs/work_92105.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index 31a9a22ba3..2854117760 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -147,7 +147,7 @@ static void lpc32xx_nand_init(void) clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) | clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) | clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) | - clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), + clkdiv(CFG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0), &lpc32xx_nand_mlc_registers->time_reg); } diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index c67a0bb6e1..f1a7853a80 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -33,7 +33,7 @@ #define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000 #define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545 #define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000 -#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 +#define CFG_LPC32XX_NAND_MLC_WR_LOW 83333333 /* * NAND From c102eb5ca7281dd3b449fd9eaf50e8f8c6b205fd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:41 -0500 Subject: [PATCH 283/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_RDR_CLKS to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RDR_CLKS to CFG_LPC32XX_NAND_SLC_RDR_CLKS Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index f4f1b22f5e..0f12201aa0 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -130,7 +130,7 @@ static void lpc32xx_nand_init(void) TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | - TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) | + TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index ab10101f20..e178968413 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -45,7 +45,7 @@ #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 -#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 +#define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 From bba52ab080f5446fabaf3c98772a2254064a7adf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:42 -0500 Subject: [PATCH 284/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_RHOLD to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RHOLD to CFG_LPC32XX_NAND_SLC_RHOLD Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 0f12201aa0..1fdc80989f 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -132,7 +132,7 @@ static void lpc32xx_nand_init(void) TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | - TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | + TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); } diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index e178968413..0b815ded73 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -47,7 +47,7 @@ #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 +#define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 /* From 416ef8c7c6c7fb371a3d0acdafbc4c851a229076 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:43 -0500 Subject: [PATCH 285/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_RSETUP to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RSETUP to CFG_LPC32XX_NAND_SLC_RSETUP Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 1fdc80989f..71e8286d1c 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -133,7 +133,7 @@ static void lpc32xx_nand_init(void) TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | - TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), + TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); } diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 0b815ded73..72cf031e05 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -48,7 +48,7 @@ #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 +#define CFG_LPC32XX_NAND_SLC_RSETUP 50000000 /* * USB From fa0e72a34eeb6b82faa4ac0156fd3e5a21750329 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:44 -0500 Subject: [PATCH 286/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_RWIDTH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_RWIDTH to CFG_LPC32XX_NAND_SLC_RWIDTH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 71e8286d1c..fb1fb2d7dc 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -131,7 +131,7 @@ static void lpc32xx_nand_init(void) TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | - TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | + TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP), &lpc32xx_nand_slc_regs->tac); diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 72cf031e05..5ba8c1bb20 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -46,7 +46,7 @@ #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 +#define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 #define CFG_LPC32XX_NAND_SLC_RSETUP 50000000 From fa32dc7d15c576e7bf1a04c44ac993c05e06a081 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:45 -0500 Subject: [PATCH 287/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG_LPC32XX_NAND_SLC_WDR_CLKS Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index fb1fb2d7dc..7de5c840ed 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -126,7 +126,7 @@ static void lpc32xx_nand_init(void) &lpc32xx_nand_slc_regs->icr); /* Configure NAND flash timings */ - writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) | + writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5ba8c1bb20..dc16ed84c5 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -41,7 +41,7 @@ /* * NAND chip timings */ -#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 +#define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 From b0c548273e1e2d20b9b200faae964a0aff348c21 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:46 -0500 Subject: [PATCH 288/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_WHOLD to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WHOLD to CFG_LPC32XX_NAND_SLC_WHOLD Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index 7de5c840ed..dee8fd24b9 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -128,7 +128,7 @@ static void lpc32xx_nand_init(void) /* Configure NAND flash timings */ writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | - TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | + TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index dc16ed84c5..24312c848e 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -43,7 +43,7 @@ */ #define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 +#define CFG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666 From 308ed808399b72de9bd947c26426d6a6f53ab28d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:47 -0500 Subject: [PATCH 289/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_WSETUP to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WSETUP to CFG_LPC32XX_NAND_SLC_WSETUP Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index dee8fd24b9..a070df81d7 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -129,7 +129,7 @@ static void lpc32xx_nand_init(void) writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | - TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | + TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) | TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 24312c848e..5719e422da 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -44,7 +44,7 @@ #define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_WHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 +#define CFG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 #define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_RHOLD 200000000 From bd79d3d616dea43b9d6de6f352144709a62a4090 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:48 -0500 Subject: [PATCH 290/424] global: Migrate CONFIG_LPC32XX_NAND_SLC_WWIDTH to CFG Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WWIDTH to CFG_LPC32XX_NAND_SLC_WWIDTH Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/lpc32xx_nand_slc.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c index a070df81d7..356f8d9440 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_slc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_slc.c @@ -127,7 +127,7 @@ static void lpc32xx_nand_init(void) /* Configure NAND flash timings */ writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) | - TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | + TAC_W_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_WWIDTH) | TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) | TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) | TAC_R_RDY(CFG_LPC32XX_NAND_SLC_RDR_CLKS) | diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 5719e422da..9cfee381d4 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -42,7 +42,7 @@ * NAND chip timings */ #define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 +#define CFG_LPC32XX_NAND_SLC_WWIDTH 66666666 #define CFG_LPC32XX_NAND_SLC_WHOLD 200000000 #define CFG_LPC32XX_NAND_SLC_WSETUP 50000000 #define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14 From dd5b58c49129016a02e41d6fda2213888d13c115 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:49 -0500 Subject: [PATCH 291/424] global: Migrate CONFIG_MALLOC_F_ADDR to CFG Perform a simple rename of CONFIG_MALLOC_F_ADDR to CFG_MALLOC_F_ADDR Signed-off-by: Tom Rini --- arch/sandbox/cpu/start.c | 2 +- common/init/board_init.c | 2 +- common/spl/spl.c | 4 ++-- doc/arch/sandbox/sandbox.rst | 2 +- include/configs/capricorn-common.h | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx8ulp_evk.h | 2 +- include/configs/imx93_evk.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/kontron_sl28.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/sandbox.h | 2 +- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- 28 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 622df41f54..234652872e 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -535,7 +535,7 @@ int sandbox_main(int argc, char *argv[]) } #if CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_base = CONFIG_MALLOC_F_ADDR; + gd->malloc_base = CFG_MALLOC_F_ADDR; #endif #if CONFIG_IS_ENABLED(LOG) gd->default_log_level = state->default_log_level; diff --git a/common/init/board_init.c b/common/init/board_init.c index 6a55026177..96ffb79a98 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -78,7 +78,7 @@ __weak void board_init_f_init_stack_protection(void) ulong board_init_f_alloc_reserve(ulong top) { /* Reserve early malloc arena */ -#ifndef CONFIG_MALLOC_F_ADDR +#ifndef CFG_MALLOC_F_ADDR #if CONFIG_VAL(SYS_MALLOC_F_LEN) top -= CONFIG_VAL(SYS_MALLOC_F_LEN); #endif diff --git a/common/spl/spl.c b/common/spl/spl.c index 1d2e8fda72..4668367b68 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -527,8 +527,8 @@ static int spl_common_init(bool setup_malloc) #if CONFIG_VAL(SYS_MALLOC_F_LEN) if (setup_malloc) { -#ifdef CONFIG_MALLOC_F_ADDR - gd->malloc_base = CONFIG_MALLOC_F_ADDR; +#ifdef CFG_MALLOC_F_ADDR + gd->malloc_base = CFG_MALLOC_F_ADDR; #endif gd->malloc_limit = CONFIG_VAL(SYS_MALLOC_F_LEN); gd->malloc_ptr = 0; diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index e6d8403651..cd7f8a2cb0 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -615,7 +615,7 @@ Addr Config Usage ======= ======================== =============================== 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree c000 CONFIG_BLOBLIST_ADDR Blob list - 10000 CONFIG_MALLOC_F_ADDR Early memory allocation + 10000 CFG_MALLOC_F_ADDR Early memory allocation f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used as the SPL load buffer in spl_test_load(). diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 19c7fca03b..9e7322cdb9 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -14,7 +14,7 @@ /* SPL config */ #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index caa1498ace..a633259738 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -13,7 +13,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 7785bdc7cb..64cdc401d0 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -16,7 +16,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x912000 +#define CFG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index ee524f0e63..d85ae21e23 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -14,7 +14,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 44d74bb1a7..0723d27ab7 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -11,7 +11,7 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index c364e06dc4..d5642b9649 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -24,7 +24,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index e718daa07c..2158b0af74 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -15,7 +15,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -# define CONFIG_MALLOC_F_ADDR 0x930000 +# define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index c490e3829f..5579a05d16 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -14,7 +14,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 #endif /* Enable Distro Boot */ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 38ae5f1370..e4e24b522f 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -24,7 +24,7 @@ 0x5f, 0xd3, 0x6b, 0x9b, 0xe5, 0xb9) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ +#define CFG_MALLOC_F_ADDR 0x184000 /* malloc f used before \ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index f6f356d27b..f7ae1b47d0 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index d9ce5d5d0f..4b46321e85 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -15,7 +15,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index eb7059f064..5158f2cc60 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 7772e71013..a25efbb16b 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -12,7 +12,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 669da591fa..4f55ae4940 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -12,7 +12,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index b7397f6038..d77510e168 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -12,7 +12,7 @@ #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x22040000 +#define CFG_MALLOC_F_ADDR 0x22040000 #endif diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index 5cd6492dd5..7b7bef3ca7 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -14,7 +14,7 @@ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_MALLOC_F_ADDR 0x204D0000 +#define CFG_MALLOC_F_ADDR 0x204D0000 #endif #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index e4d6a8a154..d80238bd02 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -46,7 +46,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 #endif #define CFG_EXTRA_ENV_SETTINGS BOOTENV diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 4dd51c7f1d..5a3c9f76a4 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -16,7 +16,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 0d293f316b..940bfd2b33 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -28,7 +28,7 @@ /* generic timer */ /* early heap for SPL DM */ -#define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE +#define CFG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE /* serial port */ #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 9160c78c04..ce6dc87c69 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -16,7 +16,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 1d8709180c..37ade717ae 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -14,7 +14,7 @@ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 +#define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 8d9af7f088..4e5653dc88 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MALLOC_F_ADDR 0x0010000 +#define CFG_MALLOC_F_ADDR 0x0010000 /* Size of our emulated memory */ #define SB_CONCAT(x, y) x ## y diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 7f3fa795af..27d7efb883 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -14,7 +14,7 @@ #ifdef CONFIG_SPL_BUILD /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CFG_MALLOC_F_ADDR 0x930000 /* For RAW image gives a error info not panic */ #endif diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 2cb076caba..942081ab84 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -16,7 +16,7 @@ /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x184000 +#define CFG_MALLOC_F_ADDR 0x184000 /* For RAW image gives a error info not panic */ #endif /* CONFIG_SPL_BUILD */ From 1d457dbb9151f50176f7548d00ed37e13dc81e00 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:50 -0500 Subject: [PATCH 292/424] global: Migrate CONFIG_MAX_MEM_MAPPED to CFG Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +++--- arch/arm/include/asm/arch-fsl-layerscape/config.h | 14 +++++++------- arch/arm/include/asm/arch-ls102xa/config.h | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 14 +++++++------- arch/powerpc/cpu/mpc85xx/mp.c | 4 ++-- arch/powerpc/cpu/mpc85xx/tlb.c | 8 ++++---- arch/powerpc/cpu/mpc8xxx/pamu_table.c | 2 +- arch/powerpc/include/asm/config.h | 6 +++--- arch/xtensa/include/asm/config.h | 2 +- board/ti/dra7xx/evm.c | 14 +++++++------- common/memsize.c | 6 +++--- drivers/ddr/fsl/util.c | 6 +++--- include/configs/dra7xx_evm.h | 2 +- include/configs/mt7621.h | 2 +- include/configs/rcar-gen3-common.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/xtfpga.h | 8 ++++---- 17 files changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2aeec7dea7..5c45c2a5ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1308,13 +1308,13 @@ phys_size_t get_effective_memsize(void) * allocated from first region. If the memory extends to the second * region (or the third region if applicable), Management Complex (MC) * memory should be put into the highest region, i.e. the end of DDR - * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so + * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so * U-Boot doesn't relocate itself into higher address. Should DDR be * configured to skip the first region, this function needs to be * adjusted. */ - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { - ea_size = CONFIG_MAX_MEM_MAPPED; + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { + ea_size = CFG_MAX_MEM_MAPPED; rem = gd->ram_size - ea_size; } else { ea_size = gd->ram_size; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 57d92f6552..12758c8dd1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -36,7 +36,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -121,7 +121,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* DCFG - GUR */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ @@ -147,7 +147,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -191,7 +191,7 @@ /* DDR */ #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SEC */ @@ -211,7 +211,7 @@ #define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -250,14 +250,14 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #elif defined(CONFIG_ARCH_LS1046A) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE +#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE /* SMMU Defintions */ #define SMMU_BASE 0x09000000 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 4a4d642441..d0abbdadf0 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -70,7 +70,7 @@ /* SATA */ #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #ifdef CONFIG_DDR_SPD -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #endif #define DCU_LAYER_MAX_NUM 16 diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index be85c54e48..0abcc01b85 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -616,12 +616,12 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset) /* * slide the testing window up to test another area * for 32_bit system, the maximum testable memory is limited to - * CONFIG_MAX_MEM_MAPPED + * CFG_MAX_MEM_MAPPED */ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { phys_addr_t test_cap, p_addr; - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED); #if !defined(CONFIG_PHYS_64BIT) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ @@ -632,7 +632,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) #endif p_addr = (*vstart) + (*size) + (*phys_offset); if (p_addr < test_cap - 1) { - p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); + p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED); if (reset_tlb(p_addr, p_size, phys_offset) == -1) return -1; *vstart = CFG_SYS_DDR_SDRAM_BASE; @@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) /* initialization for testing area */ int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) { - phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); + phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED); *vstart = CFG_SYS_DDR_SDRAM_BASE; - *size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ + *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */ *phys_offset = 0; #if !defined(CONFIG_PHYS_64BIT) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) - if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + if (gd->ram_size > CFG_MAX_MEM_MAPPED) { puts("Cannot test more than "); - print_size(CONFIG_MAX_MEM_MAPPED, + print_size(CFG_MAX_MEM_MAPPED, " without proper 36BIT support.\n"); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 44f8ed8a19..7c47e415f0 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -193,8 +193,8 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ - bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : gd->ram_size) + + bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : gd->ram_size) + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index 5d21bef587..2a78f0fe50 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -306,12 +306,12 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr, u64 memsize = (u64)memsize_in_meg << 20; u64 size; - size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); + size = min(memsize, (u64)CFG_MAX_MEM_MAPPED); size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); - if (size || memsize > CONFIG_MAX_MEM_MAPPED) { - print_size(memsize > CONFIG_MAX_MEM_MAPPED ? - memsize - CONFIG_MAX_MEM_MAPPED + size : size, + if (size || memsize > CFG_MAX_MEM_MAPPED) { + print_size(memsize > CFG_MAX_MEM_MAPPED ? + memsize - CFG_MAX_MEM_MAPPED + size : size, " of DDR memory left unmapped in U-Boot\n"); #ifndef CONFIG_SPL_BUILD puts(" "); diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index caad6670cc..b906279226 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -17,7 +17,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) tbl->start_addr[i] = (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); - tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); + tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; i++; diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 983c6f70cf..f0702cab14 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -14,13 +14,13 @@ #define HWCONFIG_BUFFER_SIZE 256 #endif -#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED #if defined(CONFIG_E500) || \ defined(CONFIG_MPC86xx) || \ defined(CONFIG_E300) -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #else -#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#define CFG_MAX_MEM_MAPPED (256 << 20) #endif #endif diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h index 21b334b938..268c5688b3 100644 --- a/arch/xtensa/include/asm/config.h +++ b/arch/xtensa/include/asm/config.h @@ -14,7 +14,7 @@ * restricting used physical memory to the first 128MB. */ #if XCHAL_HAVE_PTP_MMU -#define CONFIG_MAX_MEM_MAPPED (128 << 20) +#define CFG_MAX_MEM_MAPPED (128 << 20) #endif #endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9cb7e21a9f..568c8fb041 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -277,13 +277,13 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) case DRA752_ES2_0: switch (emif_nr) { case 1: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *regs = &emif1_ddr3_532_mhz_1cs_2G; else *regs = &emif1_ddr3_532_mhz_1cs; break; case 2: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *regs = &emif2_ddr3_532_mhz_1cs_2G; else *regs = &emif2_ddr3_532_mhz_1cs; @@ -301,7 +301,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) case DRA722_ES1_0: case DRA722_ES2_0: case DRA722_ES2_1: - if (ram_size < CONFIG_MAX_MEM_MAPPED) + if (ram_size < CFG_MAX_MEM_MAPPED) *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; else *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; @@ -360,7 +360,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: - if (ram_size > CONFIG_MAX_MEM_MAPPED) + if (ram_size > CFG_MAX_MEM_MAPPED) *dmm_lisa_regs = &lisa_map_dra7_2GB; else *dmm_lisa_regs = &lisa_map_dra7_1536MB; @@ -369,7 +369,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) case DRA722_ES2_0: case DRA722_ES2_1: default: - if (ram_size < CONFIG_MAX_MEM_MAPPED) + if (ram_size < CFG_MAX_MEM_MAPPED) *dmm_lisa_regs = &lisa_map_2G_x_2; else *dmm_lisa_regs = &lisa_map_2G_x_4; @@ -644,9 +644,9 @@ int dram_init_banksize(void) gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = get_effective_memsize(); - if (ram_size > CONFIG_MAX_MEM_MAPPED) { + if (ram_size > CFG_MAX_MEM_MAPPED) { gd->bd->bi_dram[1].start = 0x200000000; - gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; + gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED; } return 0; diff --git a/common/memsize.c b/common/memsize.c index 3c80ad2c83..ad9ddf67ac 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -106,11 +106,11 @@ phys_size_t __weak get_effective_memsize(void) if (gd->ram_base + ram_size < gd->ram_base) ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base; -#ifndef CONFIG_MAX_MEM_MAPPED +#ifndef CFG_MAX_MEM_MAPPED return ram_size; #else /* limit stack to what we can reasonable map */ - return ((ram_size > CONFIG_MAX_MEM_MAPPED) ? - CONFIG_MAX_MEM_MAPPED : ram_size); + return ((ram_size > CFG_MAX_MEM_MAPPED) ? + CFG_MAX_MEM_MAPPED : ram_size); #endif } diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index e49cf6e8e3..60051392e7 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -139,10 +139,10 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, } #if !defined(CONFIG_PHYS_64BIT) - if (base >= CONFIG_MAX_MEM_MAPPED) + if (base >= CFG_MAX_MEM_MAPPED) return; - if ((base + size) >= CONFIG_MAX_MEM_MAPPED) - size = CONFIG_MAX_MEM_MAPPED - base; + if ((base + size) >= CFG_MAX_MEM_MAPPED) + size = CFG_MAX_MEM_MAPPED - base; #endif if (set_ddr_laws(base, size, law_memctl) < 0) { printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f8afcc7826..ef1d5a1126 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -13,7 +13,7 @@ #include -#define CONFIG_MAX_MEM_MAPPED 0x80000000 +#define CFG_MAX_MEM_MAPPED 0x80000000 #ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index b6e680bcc7..a9574940d4 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -10,7 +10,7 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_MAX_MEM_MAPPED 0x1c000000 +#define CFG_MAX_MEM_MAPPED 0x1c000000 #define CFG_SYS_INIT_SP_OFFSET 0x800000 diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 8e0837a302..213caa7523 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -28,7 +28,7 @@ #define DRAM_RSV_SIZE 0x08000000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) /* ENV setting */ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index a62d1d3254..e65d623816 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -14,7 +14,7 @@ #define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ -#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE +#define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE #define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 83a0539d8f..9655b666ed 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -27,7 +27,7 @@ #else #define CFG_SYS_MEMORY_BASE 0x60000000 #define CFG_SYS_IO_BASE 0x90000000 -#define CONFIG_MAX_MEM_MAPPED 0x10000000 +#define CFG_MAX_MEM_MAPPED 0x10000000 #endif /* Onboard RAM sizes: @@ -53,10 +53,10 @@ /* Memory test is destructive so default must not overlap vectors or U-Boot*/ -#if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE +#if defined(CFG_MAX_MEM_MAPPED) && \ + CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE #define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) + (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) #else #define XTENSA_SYS_TEXT_ADDR \ (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) From 8a897c4f971ec7ecfd114c5118ccd22e4273a6be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:51 -0500 Subject: [PATCH 293/424] global: Migrate CONFIG_MAX_RAM_BANK_SIZE to CFG Perform a simple rename of CONFIG_MAX_RAM_BANK_SIZE to CFG_MAX_RAM_BANK_SIZE Signed-off-by: Tom Rini --- arch/arm/mach-davinci/misc.c | 2 +- arch/arm/mach-omap2/am33xx/board.c | 4 ++-- arch/arm/mach-omap2/sec-common.c | 2 +- arch/arm/mach-orion5x/dram.c | 4 ++-- arch/arm/mach-orion5x/include/mach/orion5x.h | 2 +- board/phytec/phycore_am335x_r2/board.c | 2 +- board/ti/ks2_evm/board.c | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/bur_am335x_common.h | 2 +- include/configs/cm_t43.h | 2 +- include/configs/da850evm.h | 2 +- include/configs/draco.h | 2 +- include/configs/etamin.h | 2 +- include/configs/legoev3.h | 2 +- include/configs/omapl138_lcdk.h | 2 +- include/configs/pxm2.h | 2 +- include/configs/rastaban.h | 2 +- include/configs/rut.h | 2 +- include/configs/thuban.h | 2 +- include/configs/ti816x_evm.h | 2 +- include/configs/ti_am335x_common.h | 2 +- include/configs/ti_armv7_keystone2.h | 2 +- 22 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 42078b39f8..cfad28c43d 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -27,7 +27,7 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 86755d6d95..a52d04d85c 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -73,7 +73,7 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } @@ -521,7 +521,7 @@ void board_init_f(ulong dummy) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0f9b915ea3..64560b21e3 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -203,7 +203,7 @@ u32 get_sec_mem_start(void) omap_sdram_size() #else get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE) + CFG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); return sec_mem_start; diff --git a/arch/arm/mach-orion5x/dram.c b/arch/arm/mach-orion5x/dram.c index c9a3750e48..5647f847d7 100644 --- a/arch/arm/mach-orion5x/dram.c +++ b/arch/arm/mach-orion5x/dram.c @@ -39,7 +39,7 @@ int dram_init (void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( (long *) orion5x_sdram_bar(0), - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); return 0; } @@ -51,7 +51,7 @@ int dram_init_banksize(void) gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); gd->bd->bi_dram[i].size = get_ram_size( (long *) (gd->bd->bi_dram[i].start), - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); } return 0; diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h index 4b1b0b0f37..e41d07e18c 100644 --- a/arch/arm/mach-orion5x/include/mach/orion5x.h +++ b/arch/arm/mach-orion5x/include/mach/orion5x.h @@ -53,7 +53,7 @@ #define MVCPU_WIN_ENABLE ORION5X_WIN_ENABLE #define MVCPU_WIN_DISABLE ORION5X_WIN_DISABLE -#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024) +#define CFG_MAX_RAM_BANK_SIZE (64*1024*1024) /* include here SoC variants. 5181, 5281, 6183 should go here when adding support for them, and this comment should then be updated. */ diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c index e84dd251c2..eb573d076d 100644 --- a/board/phytec/phycore_am335x_r2/board.c +++ b/board/phytec/phycore_am335x_r2/board.c @@ -167,7 +167,7 @@ void sdram_init(void) /* Detect memory physically present */ gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); /* Reconfigure memory for actual detected size */ switch (gd->ram_size) { diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 1683f780a3..5dcda12105 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -47,7 +47,7 @@ int dram_init(void) ddr3_size = ddr3_init(); gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); + CFG_MAX_RAM_BANK_SIZE); #if defined(CONFIG_TI_AEMIF) if (!(board_is_k2g_ice() || board_is_k2g_i1())) aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 3a6ffd9de0..f43e00e8a2 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_AM43XX_EVM_H #define __CONFIG_AM43XX_EVM_H -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 3e0b425078..ab57e14392 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -19,7 +19,7 @@ #endif /* CONFIG_DM */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Timer information */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index aa17c9cbe2..743c8c8692 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -8,7 +8,7 @@ #ifndef __CONFIG_CM_T43_H #define __CONFIG_CM_T43_H -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ +#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index cfc8330e35..736af88a02 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -31,7 +31,7 @@ */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ /* memtest will be run on 16MB */ diff --git a/include/configs/draco.h b/include/configs/draco.h index b56ba9132a..4c67174572 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -25,7 +25,7 @@ "led1=64,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ /* Default env settings */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 8d8e717b38..d07b4e9536 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -67,7 +67,7 @@ "led5=63,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h index 687ac89b85..ff966586ba 100644 --- a/include/configs/legoev3.h +++ b/include/configs/legoev3.h @@ -27,7 +27,7 @@ */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 5e71ebcba8..af0093511a 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -26,7 +26,7 @@ */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 10eaeb49de..b701e52076 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -23,7 +23,7 @@ "led0=117,0,1\0" \ /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ /* Use common default */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index 777df4c112..2efb4d23cd 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -32,7 +32,7 @@ "led5=63,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/rut.h b/include/configs/rut.h index 99799f8494..4002bc4b6c 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -19,7 +19,7 @@ #define DDR_PLL_FREQ 303 /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ +#define CFG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ /* Watchdog */ #define WATCHDOG_TRIGGER_GPIO 14 diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 1753fa410d..a5913e1e7d 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -25,7 +25,7 @@ "led1=64,0,1\0" /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define EEPROM_ADDR_DDR3 0x90 #define EEPROM_ADDR_CHIP 0x120 diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 2d9d2fd66e..ac6d46f917 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -19,7 +19,7 @@ #define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ +#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ #define CFG_SYS_SDRAM_BASE 0x80000000 /** diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index ed17b42920..20f8643771 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_TI_AM335X_COMMON_H__ #define __CONFIG_TI_AM335X_COMMON_H__ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ +#define CFG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ #define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ #include diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 7142d30a59..a47f0902a2 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -15,7 +15,7 @@ /* Memory Configuration */ #define CFG_SYS_LPAE_SDRAM_BASE 0x800000000 -#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CFG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ #ifdef CONFIG_SYS_MALLOC_F_LEN #define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN From 8f52920a4a36d905725a6945694ab0d2df6fac59 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:52 -0500 Subject: [PATCH 294/424] global: Migrate CONFIG_MFG_ENV_SETTINGS to CFG Perform a simple rename of CONFIG_MFG_ENV_SETTINGS to CFG_MFG_ENV_SETTINGS Signed-off-by: Tom Rini --- include/configs/capricorn-common.h | 4 ++-- include/configs/cgtqmx8.h | 4 ++-- include/configs/colibri-imx8x.h | 4 ++-- include/configs/imx8mq_phanbell.h | 4 ++-- include/configs/imx8qm_rom7720.h | 4 ++-- include/configs/mx7dsabresd.h | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 9e7322cdb9..9dcacad2fc 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -60,7 +60,7 @@ "${loadaddr} ${m4_0_image}\0" \ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ MFG_ENV_SETTINGS_DEFAULT \ "initrd_addr=0x83100000\0" \ "initrd_high=0xffffffffffffffff\0" \ @@ -68,7 +68,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ AHAB_ENV \ ENV_COMMON \ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index a633259738..91454df197 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -42,7 +42,7 @@ #define FEC0_RESET IMX_GPIO_NR(2, 5) #define FEC0_PDOMAIN "conn_enet0" -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ @@ -56,7 +56,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 13bc4e7e68..2de116c59d 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -43,7 +43,7 @@ #undef BOOTENV_RUN_NET_USB_START #define BOOTENV_RUN_NET_USB_START "" -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs ${consoleargs} " \ "rdinit=/linuxrc g_mass_storage.stall=0 " \ "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ @@ -59,7 +59,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV \ BOOTENV \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ MEM_LAYOUT_ENV_SETTINGS \ "boot_file=Image\0" \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 5158f2cc60..6d0c453111 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -24,13 +24,13 @@ #define CFG_FEC_MXC_PHYADDR 0 #endif -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffff\0" \ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ "script=boot.scr\0" \ "image=Image\0" \ "console=ttymxc0,115200\0" \ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 5692e3d000..df2cb8d9ce 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -33,7 +33,7 @@ #define MFG_NAND_PARTITION "" #endif -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ @@ -48,7 +48,7 @@ /* Initial environment variables */ #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ "image=Image\0" \ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index e56083f8e6..9c938f04e9 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -32,7 +32,7 @@ #define UPDATE_M4_ENV "" #endif -#define CONFIG_MFG_ENV_SETTINGS \ +#define CFG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ @@ -52,7 +52,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ - CONFIG_MFG_ENV_SETTINGS \ + CFG_MFG_ENV_SETTINGS \ CFG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ From 55eef1d62958592b363240813b866216797d8141 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:53 -0500 Subject: [PATCH 295/424] global: Migrate CONFIG_MXC_NAND_IP_REGS_BASE to CFG Perform a simple rename of CONFIG_MXC_NAND_IP_REGS_BASE to CFG_MXC_NAND_IP_REGS_BASE Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/mxc_nand.c | 2 +- include/configs/m53menlo.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 8aa5f73421..10679b2aa1 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1175,7 +1175,7 @@ int board_nand_init(struct nand_chip *this) host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 host->ip_regs = - (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; + (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE; #endif host->clk_act = 1; diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index de6928d297..3ac67b0f48 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -46,7 +46,7 @@ #ifdef CONFIG_CMD_NAND #define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CFG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CFG_SYS_NAND_LARGEPAGE #endif From d1c723895bfcc335bd3b674facd38b02586e6cac Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:54 -0500 Subject: [PATCH 296/424] global: Migrate CONFIG_MXC_NAND_REGS_BASE to CFG Perform a simple rename of CONFIG_MXC_NAND_REGS_BASE to CFG_MXC_NAND_REGS_BASE Signed-off-by: Tom Rini --- drivers/mtd/nand/raw/mxc_nand.c | 2 +- include/configs/m53menlo.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c index 10679b2aa1..051ded6a24 100644 --- a/drivers/mtd/nand/raw/mxc_nand.c +++ b/drivers/mtd/nand/raw/mxc_nand.c @@ -1172,7 +1172,7 @@ int board_nand_init(struct nand_chip *this) this->write_buf = mxc_nand_write_buf; this->read_buf = mxc_nand_read_buf; - host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = (struct mxc_nand_regs __iomem *)CFG_MXC_NAND_REGS_BASE; #ifdef MXC_NFC_V3_2 host->ip_regs = (struct mxc_nand_ip_regs __iomem *)CFG_MXC_NAND_IP_REGS_BASE; diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 3ac67b0f48..ee19c8936b 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -45,7 +45,7 @@ */ #ifdef CONFIG_CMD_NAND #define CFG_SYS_NAND_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CFG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CFG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CFG_SYS_NAND_LARGEPAGE #endif From 4db386655a889b6466d2c3f40839ad21205c6d21 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:55 -0500 Subject: [PATCH 297/424] global: Migrate CONFIG_MXC_UART_BASE to CFG Perform a simple rename of CONFIG_MXC_UART_BASE to CFG_MXC_UART_BASE Signed-off-by: Tom Rini --- board/ge/b1x5v2/spl.c | 4 ++-- drivers/serial/serial_mxc.c | 6 +++--- include/configs/apalis_imx6.h | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/cm_fx6.h | 2 +- include/configs/colibri_imx6.h | 2 +- include/configs/dart_6ul.h | 2 +- include/configs/dh_imx6.h | 2 +- include/configs/display5.h | 2 +- include/configs/el6x_common.h | 2 +- include/configs/embestmx6boards.h | 2 +- include/configs/ge_b1x5v2.h | 4 ++-- include/configs/gw_ventana.h | 2 +- include/configs/imx6-engicam.h | 4 ++-- include/configs/imx6_logic.h | 2 +- include/configs/imx6dl-mamoj.h | 2 +- include/configs/imx6ulz_smm_m2.h | 2 +- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm_data_modul_edm_sbc.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/kontron-sl-mx6ul.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/librem5.h | 10 +++++----- include/configs/liteboard.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 2 +- include/configs/msc_sm2s_imx8mp.h | 2 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 6 +++--- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sabresd.h | 2 +- include/configs/mx6slevk.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mys_6ulx.h | 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/novena.h | 2 +- include/configs/npi_imx6ull.h | 2 +- include/configs/pcl063.h | 2 +- include/configs/pcl063_ull.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/tqma6_mba6.h | 2 +- include/configs/tqma6_wru4.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/usbarmory.h | 2 +- include/configs/vining_2000.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/xpress.h | 2 +- 62 files changed, 73 insertions(+), 73 deletions(-) diff --git a/board/ge/b1x5v2/spl.c b/board/ge/b1x5v2/spl.c index 52c80f792d..460d3be1d8 100644 --- a/board/ge/b1x5v2/spl.c +++ b/board/ge/b1x5v2/spl.c @@ -565,9 +565,9 @@ void board_init_f(ulong dummy) timer_init(); /* iomux */ - if (CONFIG_MXC_UART_BASE == UART2_BASE) + if (CFG_MXC_UART_BASE == UART2_BASE) SETUP_IOMUX_PADS(uart2_pads); - else if (CONFIG_MXC_UART_BASE == UART3_BASE) + else if (CFG_MXC_UART_BASE == UART3_BASE) SETUP_IOMUX_PADS(uart3_pads); /* UART clocks enabled and gd valid - init serial console */ diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 82c0d84628..8bcbbf2bbf 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -194,11 +194,11 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk, #if !CONFIG_IS_ENABLED(DM_SERIAL) -#ifndef CONFIG_MXC_UART_BASE -#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver" +#ifndef CFG_MXC_UART_BASE +#error "define CFG_MXC_UART_BASE to use the MXC UART driver" #endif -#define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE) +#define mxc_base ((struct mxc_uart *)CFG_MXC_UART_BASE) static void mxc_serial_setbrg(void) { diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index d46159076f..2fb4cfa5e9 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -15,7 +15,7 @@ #include #include -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index cde7d3c891..b7920c7b30 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* Network */ #define CFG_FEC_MXC_PHYADDR 0 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 47b76c9371..90ebec4a94 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -26,7 +26,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* Serial console */ -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE /* Environment */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index bf2a9bbaaf..3c67aab04c 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -15,7 +15,7 @@ #include #include -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index c2ed9c7c56..fb619105a7 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -28,7 +28,7 @@ #define MMC_ROOTFS_PART 2 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 6aef15c658..348be5a6ec 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -28,7 +28,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 /* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/display5.h b/include/configs/display5.h index 70ad88c907..cd1544be03 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -34,7 +34,7 @@ #define CFG_SYS_SPI_ARGS_OFFS 0x140000 #define CFG_SYS_SPI_ARGS_SIZE 0x10000 -#define CONFIG_MXC_UART_BASE UART5_BASE +#define CFG_MXC_UART_BASE UART5_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index a5e2dc063a..6913a91c4c 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -21,7 +21,7 @@ /* Commands */ -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #define CFG_EXTRA_ENV_SETTINGS \ "board=EL6Q\0" \ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index c1748fc260..81a92c9bb9 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -12,7 +12,7 @@ #ifndef __RIOTBOARD_CONFIG_H #define __RIOTBOARD_CONFIG_H -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 0523ff9a64..529b8fc53e 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -13,9 +13,9 @@ #include "mx6_common.h" /* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE +#define CFG_MXC_UART_BASE UART3_BASE -#if CONFIG_MXC_UART_BASE == UART2_BASE +#if CFG_MXC_UART_BASE == UART2_BASE /* UART2 requires CONFIG_DEBUG_UART_BASE=0x21e8000 */ #define CONSOLE_DEVICE "ttymxc1" /* System on Module debug connector */ #else diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 5a78c68e2f..c6ace9d65e 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -16,7 +16,7 @@ #include "mx6_common.h" /* Serial */ -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* NAND */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index 4208ba9591..786b70fe06 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -116,9 +116,9 @@ /* UART */ #ifdef CONFIG_MXC_UART # ifdef CONFIG_MX6UL -# define CONFIG_MXC_UART_BASE UART1_BASE +# define CFG_MXC_UART_BASE UART1_BASE # else -# define CONFIG_MXC_UART_BASE UART4_BASE +# define CFG_MXC_UART_BASE UART4_BASE # endif #endif diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 121b34ae96..f9544cd430 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -8,7 +8,7 @@ #ifndef __IMX6LOGIC_CONFIG_H #define __IMX6LOGIC_CONFIG_H -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #include "mx6_common.h" diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 162b0b8a69..db08e43f0d 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -35,7 +35,7 @@ #include /* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE +#define CFG_MXC_UART_BASE UART3_BASE /* MMC */ diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index c95038eaa5..9da98d0af2 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -12,7 +12,7 @@ #include #include -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 66cf5b463f..84fb1bfb75 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 0723d27ab7..f7d2b660c1 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -25,7 +25,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* Minimum 1 GiB DDR */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CFG_MXC_UART_BASE UART3_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index b8fdedefa2..d022faaa91 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -18,7 +18,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x20000000 /* Minimum 512 MiB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_BASE_ADDR /* PHY needs a longer autonegotiation timeout after reset */ #define PHY_ANEG_TIMEOUT 20000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index e4e24b522f..495ca313db 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -148,7 +148,7 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CFG_MXC_UART_BASE UART3_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index f7ae1b47d0..828bd67237 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -54,7 +54,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 4b46321e85..a7a51907f5 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -59,7 +59,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 6d0c453111..bfde15e624 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -92,7 +92,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index e3ae91089f..4354f3945e 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -22,7 +22,7 @@ #define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE /* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 5a3c9f76a4..bf590efb43 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -67,7 +67,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(3) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 7417f8582a..9e4d373e56 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -30,23 +30,23 @@ #define CONSOLE_ON_UART1 #ifdef CONSOLE_ON_UART1 -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_BASE_ADDR #define CONSOLE_UART_CLK 0 #define CONSOLE "ttymxc0" #elif defined(CONSOLE_ON_UART2) -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CFG_MXC_UART_BASE UART2_BASE_ADDR #define CONSOLE_UART_CLK 1 #define CONSOLE "ttymxc1" #elif defined(CONSOLE_ON_UART3) -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CFG_MXC_UART_BASE UART3_BASE_ADDR #define CONSOLE_UART_CLK 2 #define CONSOLE "ttymxc2" #elif defined(CONSOLE_ON_UART4) -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR +#define CFG_MXC_UART_BASE UART4_BASE_ADDR #define CONSOLE_UART_CLK 3 #define CONSOLE "ttymxc3" #else -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_BASE_ADDR #define CONSOLE_UART_CLK 0 #define CONSOLE "ttymxc0" #endif diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 0b8781d7bf..63e5dbfab7 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -13,7 +13,7 @@ #include #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index ee19c8936b..9aac5677fb 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -31,7 +31,7 @@ /* * Serial Driver */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* * MMC Driver diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 6cc49378fe..b64bf93bcb 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -17,7 +17,7 @@ * mode from SD card (SD2) */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h index 1cd0b3cf73..c1c1fd5a78 100644 --- a/include/configs/msc_sm2s_imx8mp.h +++ b/include/configs/msc_sm2s_imx8mp.h @@ -55,7 +55,7 @@ #define PHYS_SDRAM_2 0xc0000000 #define PHYS_SDRAM_2_SIZE 0x0 -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CFG_MXC_UART_BASE UART2_BASE_ADDR #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 740e357e00..123b7a533b 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -18,7 +18,7 @@ * Hardware drivers */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* PMIC Controller */ #define CFG_FSL_PMIC_BUS 0 diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index baffe65c36..1a3ec6e0cd 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -14,7 +14,7 @@ #include -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 0ac93d6e04..d87f9e942c 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -11,7 +11,7 @@ #include -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index d4af96b51e..871d52c343 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -19,7 +19,7 @@ /* Command definition */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CFG_EXTRA_ENV_SETTINGS \ "som_rev=undefined\0" \ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index f6d3b2eeb9..b664962a26 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -14,12 +14,12 @@ #ifdef CONFIG_SERIAL_CONSOLE_UART1 #if defined(CONFIG_MX6SL) -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR #else -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #endif #elif defined(CONFIG_SERIAL_CONSOLE_UART2) -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #else #error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) #endif diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 888da7ce36..274c14bbd3 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -8,7 +8,7 @@ #ifndef __MX6SABREAUTO_CONFIG_H #define __MX6SABREAUTO_CONFIG_H -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" /* USB Configs */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 78a554d0cc..af9978e02c 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -8,7 +8,7 @@ #ifndef __MX6SABRESD_CONFIG_H #define __MX6SABRESD_CONFIG_H -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" #include "mx6sabre_common.h" diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 4fbd06783a..f6d9ac2082 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART1_IPS_BASE_ADDR /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index cf4871cbae..aec3e51bff 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CFG_EXTRA_ENV_SETTINGS \ "epdc_waveform=epdc_splash.bin\0" \ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 3399cdd16f..3d0f6e452d 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #define CFG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index c99d99abc1..8c39e6d6cf 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -12,7 +12,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 5e3695ecc9..3f8a90b626 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -15,7 +15,7 @@ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 58d1a744ae..2c3cd32cef 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -16,7 +16,7 @@ #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #ifdef CONFIG_FSL_USDHC diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 43261824d3..0c0235b429 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -13,7 +13,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index aca15be64b..5625771bad 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -11,7 +11,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/novena.h b/include/configs/novena.h index 3ffb44ab72..7243549b68 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -49,7 +49,7 @@ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 4b47e4fbb3..24d7b0c26e 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -13,7 +13,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 146f87e9ce..e8c48cf836 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -22,7 +22,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 0890c11570..bd04268a3e 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -22,7 +22,7 @@ #define MMC_ROOTFS_PART 2 /* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configs */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index e1f7b70031..a1d0dd93c5 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 1cb8fa63e7..64e0a55648 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -17,7 +17,7 @@ #define CFG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR +#define CFG_MXC_UART_BASE UART6_BASE_ADDR /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 7fc6211ff7..dbeaeea77f 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR +#define CFG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 37ade717ae..4b602ea030 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -71,7 +71,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ -#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) +#define CFG_MXC_UART_BASE UART_BASE_ADDR(1) #define CFG_SYS_FSL_USDHC_NUM 2 #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index a5f14dc426..b5871424bc 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,7 +11,7 @@ #define CFG_FEC_MXC_PHYADDR 0x03 -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" #endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 34c9b6a2f9..e06fc7fe15 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -10,7 +10,7 @@ #define CFG_FEC_MXC_PHYADDR 0x01 /* UART */ -#define CONFIG_MXC_UART_BASE UART4_BASE +#define CFG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" /* Watchdog */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h index f0092eff14..d85cf7808c 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART2_BASE +#define CFG_MXC_UART_BASE UART2_BASE /* MMC Configuration */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 5d7d734daa..842abb7b7a 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -16,7 +16,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* Command definition */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* Linux only */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 11706148f1..00b45cc3d2 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -17,7 +17,7 @@ /* U-Boot general configurations */ /* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* SD/MMC */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index cdd2eeef0a..7954ed9910 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -50,7 +50,7 @@ #endif #ifdef CONFIG_SPL_BUILD -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE #endif #endif /* __CONFIG_H */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 1e765439fa..8853bcd7be 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -10,7 +10,7 @@ #include "mx6_common.h" -#define CONFIG_MXC_UART_BASE UART1_BASE +#define CFG_MXC_UART_BASE UART1_BASE /* MMC Configuration */ #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 96996ac1f0..c8ae047e62 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -10,7 +10,7 @@ #include "mx6_common.h" #include -#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR +#define CFG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR From dd11fdc31fb82f63258c1970a6d8d22b8ffd3173 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:04:56 -0500 Subject: [PATCH 298/424] global: Migrate CONFIG_MXC_USB_FLAGS et al to CFG Perform simple renames of: CONFIG_MXC_USB_FLAGS to CFG_MXC_USB_FLAGS CONFIG_MXC_USB_PORT to CFG_MXC_USB_PORT CONFIG_MXC_USB_PORTSC to CFG_MXC_USB_PORTSC Signed-off-by: Tom Rini --- drivers/usb/host/ehci-mx5.c | 4 ++-- drivers/usb/host/ehci-mx6.c | 8 ++++---- include/configs/apalis_imx6.h | 4 ++-- include/configs/aristainetos2.h | 4 ++-- include/configs/brppt2.h | 2 +- include/configs/cl-som-imx7.h | 4 ++-- include/configs/cm_fx6.h | 4 ++-- include/configs/colibri-imx6ull.h | 4 ++-- include/configs/colibri_imx6.h | 4 ++-- include/configs/colibri_imx7.h | 4 ++-- include/configs/dart_6ul.h | 4 ++-- include/configs/dh_imx6.h | 4 ++-- include/configs/display5.h | 2 +- include/configs/embestmx6boards.h | 4 ++-- include/configs/ge_b1x5v2.h | 4 ++-- include/configs/gw_ventana.h | 4 ++-- include/configs/imx6_logic.h | 4 ++-- include/configs/imx6dl-mamoj.h | 4 ++-- include/configs/imx6q-bosch-acc.h | 4 ++-- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/kontron-sl-mx6ul.h | 4 ++-- include/configs/kontron-sl-mx8mm.h | 4 ++-- include/configs/kp_imx53.h | 4 ++-- include/configs/kp_imx6q_tpc.h | 4 ++-- include/configs/liteboard.h | 4 ++-- include/configs/m53menlo.h | 6 +++--- include/configs/meerkat96.h | 2 +- include/configs/mx51evk.h | 6 +++--- include/configs/mx53cx9020.h | 6 +++--- include/configs/mx53loco.h | 6 +++--- include/configs/mx53ppd.h | 6 +++--- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6memcal.h | 2 +- include/configs/mx6sabreauto.h | 4 ++-- include/configs/mx6sabresd.h | 4 ++-- include/configs/mx6slevk.h | 4 ++-- include/configs/mx6sllevk.h | 2 +- include/configs/mx6sxsabreauto.h | 4 ++-- include/configs/mx6sxsabresd.h | 4 ++-- include/configs/mx6ul_14x14_evk.h | 4 ++-- include/configs/mx7dsabresd.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mys_6ulx.h | 4 ++-- include/configs/nitrogen6x.h | 4 ++-- include/configs/novena.h | 4 ++-- include/configs/npi_imx6ull.h | 4 ++-- include/configs/o4-imx6ull-nano.h | 2 +- include/configs/opos6uldev.h | 4 ++-- include/configs/pcl063.h | 4 ++-- include/configs/pcl063_ull.h | 4 ++-- include/configs/pico-imx6.h | 4 ++-- include/configs/pico-imx6ul.h | 4 ++-- include/configs/pico-imx7d.h | 4 ++-- include/configs/somlabs_visionsom_6ull.h | 4 ++-- include/configs/tbs2910.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/usbarmory.h | 6 +++--- include/configs/verdin-imx8mm.h | 2 +- include/configs/vining_2000.h | 4 ++-- include/configs/wandboard.h | 4 ++-- include/configs/warp7.h | 2 +- include/configs/xpress.h | 4 ++-- 63 files changed, 119 insertions(+), 119 deletions(-) diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c index 964a53bb7c..c11279867c 100644 --- a/drivers/usb/host/ehci-mx5.c +++ b/drivers/usb/host/ehci-mx5.c @@ -299,10 +299,10 @@ static int ehci_usb_probe(struct udevice *dev) HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); - __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + __raw_writel(CFG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); - mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS); + mxc_set_usbcontrol(priv->portnr, CFG_MXC_USB_FLAGS); mdelay(10); return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0, diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index fa2ca2a1d9..0a12db614f 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -70,8 +70,8 @@ DECLARE_GLOBAL_DATA_PTR; #define UCMD_RESET (1 << 1) /* controller reset */ /* If this is not defined, assume MX6/MX7/MX8M SoC default */ -#ifndef CONFIG_MXC_USB_PORTSC -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#ifndef CFG_MXC_USB_PORTSC +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* Base address for this IP block is 0x02184800 */ @@ -411,7 +411,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, return 0; setbits_le32(&ehci->usbmode, CM_HOST); - writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(CFG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); @@ -454,7 +454,7 @@ static u32 mx6_portsc(enum usb_phy_interface phy_type) case USBPHY_INTERFACE_MODE_HSIC: return PORT_PTS_HSIC; default: - return CONFIG_MXC_USB_PORTSC; + return CFG_MXC_USB_PORTSC; } } diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 2fb4cfa5e9..8a9f3ef75a 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -26,8 +26,8 @@ /* USB Configs */ /* Host */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Framebuffer and LCD */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index be1478ea8b..286435d6f8 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -413,8 +413,8 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* UBI support */ diff --git a/include/configs/brppt2.h b/include/configs/brppt2.h index 32d9f503d9..38c98c5e21 100644 --- a/include/configs/brppt2.h +++ b/include/configs/brppt2.h @@ -79,6 +79,6 @@ BUR_COMMON_ENV \ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_BRPP2_IMX6_H */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index b7920c7b30..0a667c60b6 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -96,7 +96,7 @@ #endif /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* __CONFIG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 90ebec4a94..7d0f2b6dc1 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -135,8 +135,8 @@ #define CFG_FEC_MXC_PHYADDR 0 /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Boot */ #define CFG_SYS_BOOTMAPSZ (8 << 20) diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 5b802aa92a..ba45ee4efd 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -123,8 +123,8 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 3c67aab04c..4b2841833b 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -23,8 +23,8 @@ /* USB Configs */ /* Host */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 91f87ea283..c568643977 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -167,7 +167,7 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index fb619105a7..c578167086 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -47,8 +47,8 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 348be5a6ec..5cf73274d5 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -32,8 +32,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* USB Gadget (DFU, UMS) */ #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) diff --git a/include/configs/display5.h b/include/configs/display5.h index cd1544be03..3b96fff7d6 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -288,5 +288,5 @@ /* The 0x120000 value corresponds to above SPI-NOR memory MAP */ #endif -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 81a92c9bb9..31c7e104f6 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -18,8 +18,8 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/ge_b1x5v2.h b/include/configs/ge_b1x5v2.h index 529b8fc53e..49b058cb10 100644 --- a/include/configs/ge_b1x5v2.h +++ b/include/configs/ge_b1x5v2.h @@ -24,8 +24,8 @@ #endif /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Memory */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index c6ace9d65e..0a9dfe736f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -36,8 +36,8 @@ /* Various command support */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Miscellaneous configurable options */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index f9544cd430..85c054451f 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -117,8 +117,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* Falcon Mode */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index db08e43f0d..6c61b3f448 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -43,8 +43,8 @@ #define CFG_FEC_MXC_PHYADDR 1 /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Falcon */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index e28185f24d..2c998cdcfc 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -110,7 +110,7 @@ #endif #endif -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* __IMX6Q_ACC_H */ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 84fb1bfb75..106fbdb905 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -79,6 +79,6 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 64cdc401d0..2641d7bc96 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -139,6 +139,6 @@ #define CFG_FEC_MXC_PHYADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /*__IMX8MM_CL_IOT_GATE_H*/ diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index 4354f3945e..1c92cd7876 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -25,8 +25,8 @@ #define CFG_MXC_UART_BASE UART4_BASE #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* Boot order for distro boot */ diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index d80238bd02..eee3d2ddb0 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -25,8 +25,8 @@ /* Board and environment settings */ #ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* GUID for capsule updatable firmware image */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h index da8a67b4ab..6e383cbe75 100644 --- a/include/configs/kp_imx53.h +++ b/include/configs/kp_imx53.h @@ -11,8 +11,8 @@ #include /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h index 99321b320f..1aa4b8ab59 100644 --- a/include/configs/kp_imx6q_tpc.h +++ b/include/configs/kp_imx6q_tpc.h @@ -18,8 +18,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index 63e5dbfab7..5811059c8e 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -95,8 +95,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 9aac5677fb..1ecbba1b58 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -70,9 +70,9 @@ * USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* LVDS display */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h index 9e480fe055..6ffc128241 100644 --- a/include/configs/meerkat96.h +++ b/include/configs/meerkat96.h @@ -24,6 +24,6 @@ /* Environment configs */ /* USB configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 123b7a533b..dff54d04a6 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -33,9 +33,9 @@ #define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC PORT_PTS_ULPI +#define CFG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED /* Framebuffer and LCD */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index 1a3ec6e0cd..e995776d30 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -23,9 +23,9 @@ /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index d87f9e942c..7398804e6b 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -17,9 +17,9 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* PMIC Controller */ #define CFG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h index 94d2191af9..df65dbeea4 100644 --- a/include/configs/mx53ppd.h +++ b/include/configs/mx53ppd.h @@ -12,9 +12,9 @@ #include /* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Command definition */ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 871d52c343..f0d6405d30 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -15,7 +15,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* Command definition */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h index b664962a26..f2edd13eb8 100644 --- a/include/configs/mx6memcal.h +++ b/include/configs/mx6memcal.h @@ -31,6 +31,6 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI +#define CFG_MXC_USB_PORTSC PORT_PTS_UTMI #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 274c14bbd3..da98139d7d 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -12,8 +12,8 @@ #define CONSOLE_DEV "ttymxc3" /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index af9978e02c..2b028e3aa2 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -29,8 +29,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index f6d9ac2082..39c8ef060c 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -90,8 +90,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #define CFG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index aec3e51bff..290996b51b 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -94,7 +94,7 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif #include diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 3d0f6e452d..1c14a6beb0 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -96,8 +96,8 @@ #define CFG_FEC_MXC_PHYADDR 0x0 #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #define CFG_SYS_FSL_USDHC_NUM 2 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8c39e6d6cf..8b02c3b631 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -118,8 +118,8 @@ #define CFG_FEC_MXC_PHYADDR 0x1 #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_PCI diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 3f8a90b626..635ae78abc 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -116,8 +116,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 9c938f04e9..94bee75fde 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -99,6 +99,6 @@ #endif /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index 5ee5129801..a310c64e79 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -51,5 +51,5 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __CONFIG_H */ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 0c0235b429..2571098d06 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -30,8 +30,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 5625771bad..c9c599d076 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -21,8 +21,8 @@ #define CFG_FEC_MXC_PHYADDR 6 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_MMC #define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) diff --git a/include/configs/novena.h b/include/configs/novena.h index 7243549b68..dc5b043129 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -53,8 +53,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* Extra U-Boot environment. */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 24d7b0c26e..5f933391cc 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -29,8 +29,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_NET #define CFG_FEC_MXC_PHYADDR 0x1 diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h index 0e1083a213..9050da8738 100644 --- a/include/configs/o4-imx6ull-nano.h +++ b/include/configs/o4-imx6ull-nano.h @@ -12,7 +12,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE #if IS_ENABLED(CONFIG_CMD_USB) -# define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +# define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 459134b93f..1edb1826c4 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -19,8 +19,8 @@ /* USB */ #ifdef CONFIG_USB_EHCI_MX6 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif /* LCD */ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index e8c48cf836..38dcee0535 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -42,8 +42,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index bd04268a3e..d742201ce4 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -44,8 +44,8 @@ #define CFG_SYS_NAND_BASE 0x40000000 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index a1d0dd93c5..d806d7d9c5 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -16,8 +16,8 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 64e0a55648..4caa823375 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -23,8 +23,8 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index dbeaeea77f..fd8962e9f7 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -107,7 +107,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 3418d4e2b5..041a83b057 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -61,8 +61,8 @@ /* USB Configs */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #endif #ifdef CONFIG_CMD_NET diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 9b396e6e73..535859792d 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -27,7 +27,7 @@ /* USB */ #ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* CONFIG_CMD_USB */ #define CFG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index cb5f7fc25a..af5a474cf3 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -39,7 +39,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #if defined(CONFIG_TQMA6X_MMC_BOOT) diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 00b45cc3d2..27e61f5b8f 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -23,9 +23,9 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORT 1 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 /* Linux boot */ diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 27d7efb883..8cb1f1aff3 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -67,6 +67,6 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif /* __VERDIN_IMX8MM_H */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7954ed9910..6db68c1e70 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -36,8 +36,8 @@ /* Network */ #define CFG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 8853bcd7be..7b8c5cbe7a 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -17,8 +17,8 @@ #define CFG_SYS_FSL_ESDHC_ADDR 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_EXTRA_ENV_SETTINGS \ "console=ttymxc0\0" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 0826e0bbe0..5d2956a596 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -93,7 +93,7 @@ #define CFG_SYS_FSL_USDHC_NUM 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) /* USB Device Firmware Update support */ #define DFU_DEFAULT_POLL_TIMEOUT 300 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index c8ae047e62..a2aa31008e 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -28,8 +28,8 @@ /* Environment is in stored in the eMMC boot partition */ /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CFG_MXC_USB_FLAGS 0 #define CFG_FEC_ENET_DEV 0 #define CFG_FEC_MXC_PHYADDR 0x0 From 1c3ba55798e3552739f06356aaeb18e66ec49a3c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:23 -0500 Subject: [PATCH 299/424] global: Migrate CONFIG_ODROID_REV_AIN to CFG Perform a simple rename of CONFIG_ODROID_REV_AIN to CFG_ODROID_REV_AIN Signed-off-by: Tom Rini --- board/samsung/common/exynos5-dt-types.c | 4 ++-- include/configs/odroid_xu3.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 554fc91cc1..9294d36ba3 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -57,7 +57,7 @@ static int odroid_get_adc_val(unsigned int *adcval) unsigned int adcval_prev = 0; int ret, retries = 20; - ret = adc_channel_single_shot("adc@12D10000", CONFIG_ODROID_REV_AIN, + ret = adc_channel_single_shot("adc@12D10000", CFG_ODROID_REV_AIN, &adcval_prev); if (ret) return ret; @@ -66,7 +66,7 @@ static int odroid_get_adc_val(unsigned int *adcval) mdelay(5); ret = adc_channel_single_shot("adc@12D10000", - CONFIG_ODROID_REV_AIN, adcval); + CFG_ODROID_REV_AIN, adcval); if (ret) return ret; diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 2bac017ea0..7304851d0f 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -52,7 +52,7 @@ #define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ -#define CONFIG_ODROID_REV_AIN 9 +#define CFG_ODROID_REV_AIN 9 /* * Need to override existing one (smdk5420) with odroid so set_board_info will From a2c164cbb46c6400d93d08e634a1987bfce0e79f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:24 -0500 Subject: [PATCH 300/424] global: Migrate CONFIG_OTHBOOTARGS to CFG Perform a simple rename of CONFIG_OTHBOOTARGS to CFG_OTHBOOTARGS Signed-off-by: Tom Rini --- include/configs/x86-common.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 65a1e63e00..5d461e8d0c 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -27,9 +27,9 @@ /* Default environment */ #define CONFIG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) -#define CONFIG_OTHBOOTARGS "othbootargs=\0" +#define CFG_OTHBOOTARGS "othbootargs=\0" #else -#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0" +#define CFG_OTHBOOTARGS "othbootargs=acpi=off\0" #endif #if defined(CONFIG_DISTRO_DEFAULTS) @@ -49,7 +49,7 @@ "pciconfighost=1\0" \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - CONFIG_OTHBOOTARGS \ + CFG_OTHBOOTARGS \ "scriptaddr=0x7000000\0" \ "kernel_addr_r=0x1000000\0" \ "ramdisk_addr_r=0x4000000\0" \ From 7906f91789de1f0ceed87d53a39ca2d7ca80150c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:25 -0500 Subject: [PATCH 301/424] global: Migrate CONFIG_PCIE_IMX_PERST_GPIO to CFG Perform a simple rename of CONFIG_PCIE_IMX_PERST_GPIO to CFG_PCIE_IMX_PERST_GPIO Signed-off-by: Tom Rini --- drivers/pci/pcie_imx.c | 12 ++++++------ include/configs/mx6sabresd.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/novena.h | 2 +- include/configs/tbs2910.h | 2 +- include/configs/vining_2000.h | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 46ac01713f..902507aaae 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -566,7 +566,7 @@ int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) * do self-initialisation. * * In case your #PERST pin is connected to a plain GPIO pin of the - * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's + * CPU, you can define CFG_PCIE_IMX_PERST_GPIO in your board's * configuration file and the condition below will handle the rest * of the reset toggling. * @@ -578,13 +578,13 @@ int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) * Linux at all in the first place since it's in some non-reset * state due to being previously used in U-Boot. */ -#ifdef CONFIG_PCIE_IMX_PERST_GPIO - gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset"); - gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0); +#ifdef CFG_PCIE_IMX_PERST_GPIO + gpio_request(CFG_PCIE_IMX_PERST_GPIO, "pcie_reset"); + gpio_direction_output(CFG_PCIE_IMX_PERST_GPIO, 0); mdelay(20); - gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1); + gpio_set_value(CFG_PCIE_IMX_PERST_GPIO, 1); mdelay(20); - gpio_free(CONFIG_PCIE_IMX_PERST_GPIO); + gpio_free(CFG_PCIE_IMX_PERST_GPIO); #else if (dm_gpio_is_valid(gpio)) { /* Assert PERST# for 20ms then de-assert */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 2b028e3aa2..116a9c6abc 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -20,7 +20,7 @@ #define CFG_SYS_FSL_USDHC_NUM 3 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 8b02c3b631..85e5cfbb58 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -123,7 +123,7 @@ #endif #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif diff --git a/include/configs/novena.h b/include/configs/novena.h index dc5b043129..6f4353e7df 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -41,7 +41,7 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 535859792d..256331ae17 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -22,7 +22,7 @@ /* PCI */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #endif /* USB */ diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 6db68c1e70..7bfc22c043 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -40,7 +40,7 @@ #define CFG_MXC_USB_FLAGS 0 #ifdef CONFIG_CMD_PCI -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) +#define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif #define CFG_IMX6_PWM_PER_CLK 66000000 From 52139620be4084ac00e3c628616599c4a88c4191 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:26 -0500 Subject: [PATCH 302/424] global: Migrate CONFIG_PCIE_IMX_POWER_GPIO to CFG Perform a simple rename of CONFIG_PCIE_IMX_POWER_GPIO to CFG_PCIE_IMX_POWER_GPIO Signed-off-by: Tom Rini --- drivers/pci/pcie_imx.c | 10 +++++----- include/configs/mx6sabresd.h | 2 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/novena.h | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 902507aaae..da48466480 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -534,13 +534,13 @@ static int imx6_pcie_init_phy(void) int imx6_pcie_toggle_power(struct udevice *vpcie) { -#ifdef CONFIG_PCIE_IMX_POWER_GPIO - gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power"); - gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0); +#ifdef CFG_PCIE_IMX_POWER_GPIO + gpio_request(CFG_PCIE_IMX_POWER_GPIO, "pcie_power"); + gpio_direction_output(CFG_PCIE_IMX_POWER_GPIO, 0); mdelay(20); - gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1); + gpio_set_value(CFG_PCIE_IMX_POWER_GPIO, 1); mdelay(20); - gpio_free(CONFIG_PCIE_IMX_POWER_GPIO); + gpio_free(CFG_PCIE_IMX_POWER_GPIO); #endif #if CONFIG_IS_ENABLED(DM_REGULATOR) diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 116a9c6abc..1aa8a56cce 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -21,7 +21,7 @@ #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) +#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif /* PMIC */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 85e5cfbb58..fe0ad34ef9 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -124,7 +124,7 @@ #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) +#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR diff --git a/include/configs/novena.h b/include/configs/novena.h index 6f4353e7df..5e8b7fa621 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -42,7 +42,7 @@ /* PCI express */ #ifdef CONFIG_CMD_PCI #define CFG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) +#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) #endif /* PMIC */ From e9212bffe3cfcfb7baee5233f8de06f2d4e500f6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:27 -0500 Subject: [PATCH 303/424] global: Migrate CONFIG_PHY_ET1011C_TX_CLK_FIX to CFG Perform a simple rename of CONFIG_PHY_ET1011C_TX_CLK_FIX to CFG_PHY_ET1011C_TX_CLK_FIX Signed-off-by: Tom Rini --- drivers/net/phy/et1011c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c index c243c5b72f..7eff5ec7ca 100644 --- a/drivers/net/phy/et1011c.c +++ b/drivers/net/phy/et1011c.c @@ -60,7 +60,7 @@ static int et1011c_parse_status(struct phy_device *phydev) mii_reg | ET1011C_GMII_INTERFACE | ET1011C_SYS_CLK_EN | -#ifdef CONFIG_PHY_ET1011C_TX_CLK_FIX +#ifdef CFG_PHY_ET1011C_TX_CLK_FIX ET1011C_TX_CLK_EN | #endif ET1011C_TX_FIFO_DEPTH_16); From 52d596eabbd3ce80c2e1ce0e860d588cd219bd0b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:28 -0500 Subject: [PATCH 304/424] global: Migrate CONFIG_PHY_ID to CFG Perform a simple rename of CONFIG_PHY_ID to CFG_PHY_ID Signed-off-by: Tom Rini --- board/egnite/ethernut5/ethernut5.c | 2 +- include/configs/ethernut5.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c index ceb0d2cf0a..9953df017e 100644 --- a/board/egnite/ethernut5/ethernut5.c +++ b/board/egnite/ethernut5/ethernut5.c @@ -160,7 +160,7 @@ int board_eth_init(struct bd_info *bis) /* Set peripheral pins. */ at91_macb_hw_init(); /* Basic EMAC initialization. */ - if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID)) + if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CFG_PHY_ID)) return -1; /* * Early board revisions have a pull-down at the PHY's MODE0 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 3fd58d6bd4..182369def9 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -48,7 +48,7 @@ /* JFFS2 */ /* Ethernet */ -#define CONFIG_PHY_ID 0 +#define CFG_PHY_ID 0 /* MMC */ #ifdef CONFIG_CMD_MMC From 830fd095a348d8390c23d93605e438ac24153be9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:29 -0500 Subject: [PATCH 305/424] global: Migrate CONFIG_PHY_IRAM_BASE to CFG Perform a simple rename of CONFIG_PHY_IRAM_BASE to CFG_PHY_IRAM_BASE Signed-off-by: Tom Rini --- arch/arm/mach-exynos/lowlevel_init.c | 6 +++--- include/configs/exynos5420-common.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 243b5c80c9..c57b8aee79 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -77,10 +77,10 @@ static void low_power_start(void) branch_bx(0x0); } - reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4); + reg_val = readl(CFG_PHY_IRAM_BASE + 0x4); if (reg_val != (uint32_t)&low_power_start) { /* Store jump address as low_power_start if not present */ - writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4); + writel((uint32_t)&low_power_start, CFG_PHY_IRAM_BASE + 0x4); dsb(); sev(); } @@ -164,7 +164,7 @@ static void secondary_cores_configure(void) writel((uint32_t)&low_power_start, CFG_LOWPOWER_ADDR); writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE); /* Store jump address for power down */ - writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4); + writel((uint32_t)&power_down_core, CFG_PHY_IRAM_BASE + 0x4); /* Need all core power down check */ dsb(); diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index bd43efa553..b75fe1b0a8 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -10,7 +10,7 @@ #define CFG_IRAM_TOP 0x02074000 -#define CONFIG_PHY_IRAM_BASE 0x02020000 +#define CFG_PHY_IRAM_BASE 0x02020000 /* * Low Power settings From f410d0ac8a90d16870d33cc7944e98445f7e168d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:30 -0500 Subject: [PATCH 306/424] global: Migrate CONFIG_PL011_CLOCK to CFG Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK Signed-off-by: Tom Rini --- README | 2 +- arch/arm/cpu/armv7/s5p4418/cpu.c | 2 +- board/armltd/total_compute/total_compute.c | 2 +- board/armltd/vexpress64/vexpress64.c | 2 +- drivers/serial/serial_pl01x.c | 8 ++++---- include/configs/corstone1000.h | 2 +- include/configs/highbank.h | 2 +- include/configs/lx2160a_common.h | 2 +- include/configs/mxs.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/thunderx_88xx.h | 2 +- include/configs/total_compute.h | 2 +- include/configs/vexpress_aemv8.h | 4 ++-- include/configs/vexpress_common.h | 2 +- 15 files changed, 19 insertions(+), 19 deletions(-) diff --git a/README b/README index 05618352fa..8354cf5699 100644 --- a/README +++ b/README @@ -413,7 +413,7 @@ The following options need to be configured: controller register space - Serial Ports: - CONFIG_PL011_CLOCK + CFG_PL011_CLOCK If you have Amba PrimeCell PL011 UARTs, set this variable to the clock speed of the UARTs. diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 3baa761ec7..7ba9c0b032 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -64,7 +64,7 @@ static void serial_device_init(void) /* set clock */ clk_disable(clk); - clk_set_rate(clk, CONFIG_PL011_CLOCK); + clk_set_rate(clk, CFG_PL011_CLOCK); clk_enable(clk); } #endif diff --git a/board/armltd/total_compute/total_compute.c b/board/armltd/total_compute/total_compute.c index b7772f79a3..53941b5f5f 100644 --- a/board/armltd/total_compute/total_compute.c +++ b/board/armltd/total_compute/total_compute.c @@ -13,7 +13,7 @@ static const struct pl01x_serial_plat serial_plat = { .base = UART0_BASE, .type = TYPE_PL011, - .clock = CONFIG_PL011_CLOCK, + .clock = CFG_PL011_CLOCK, }; U_BOOT_DRVINFO(total_compute_serials) = { diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 4ca544f101..99fb67eced 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pl01x_serial_plat serial_plat = { .base = V2M_UART0, .type = TYPE_PL011, - .clock = CONFIG_PL011_CLOCK, + .clock = CFG_PL011_CLOCK, }; U_BOOT_DRVINFO(vexpress_serials) = { diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index d3c3d3e2d1..dd2881931d 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -193,7 +193,7 @@ static void pl01x_serial_init_baud(int baudrate) #if defined(CONFIG_PL011_SERIAL) pl01x_type = TYPE_PL011; - clock = CONFIG_PL011_CLOCK; + clock = CFG_PL011_CLOCK; #endif base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; @@ -343,8 +343,8 @@ static const struct udevice_id pl01x_serial_id[] ={ {} }; -#ifndef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK 0 +#ifndef CFG_PL011_CLOCK +#define CFG_PL011_CLOCK 0 #endif int pl01x_serial_of_to_plat(struct udevice *dev) @@ -359,7 +359,7 @@ int pl01x_serial_of_to_plat(struct udevice *dev) return -EINVAL; plat->base = addr; - plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK); + plat->clock = dev_read_u32_default(dev, "clock", CFG_PL011_CLOCK); ret = clk_get_by_index(dev, 0, &clk); if (!ret) { ret = clk_enable(&clk); diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h index 8aec52d508..3347c11792 100644 --- a/include/configs/corstone1000.h +++ b/include/configs/corstone1000.h @@ -16,7 +16,7 @@ #define V2M_BASE 0x80000000 -#define CONFIG_PL011_CLOCK 50000000 +#define CFG_PL011_CLOCK 50000000 /* Physical Memory Map */ #define PHYS_SDRAM_1 (V2M_BASE) diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 76e6054b0c..97bb439f73 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -8,7 +8,7 @@ #define CFG_SYS_BOOTMAPSZ (16 << 20) -#define CONFIG_PL011_CLOCK 150000000 +#define CFG_PL011_CLOCK 150000000 /* * Miscellaneous configurable options diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index c1a98fd3e4..f8a20ea16f 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -39,7 +39,7 @@ /* Serial Port */ -#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) +#define CFG_PL011_CLOCK (get_bus_freq(0) / 4) #define CFG_SYS_SERIAL0 0x21c0000 #define CFG_SYS_SERIAL1 0x21d0000 #define CFG_SYS_SERIAL2 0x21e0000 diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 32e0e06617..90cb1a5e4a 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -77,7 +77,7 @@ * DUART Serial Driver. * Conflicts with AUART driver which can be set by board. */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } /* Default baudrate can be overridden by board! */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index bfe559f6e2..0e7d01925e 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -76,7 +76,7 @@ /*----------------------------------------------------------------------- * serial console configuration */ -#define CONFIG_PL011_CLOCK 50000000 +#define CFG_PL011_CLOCK 50000000 #define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ (void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART2, \ diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index e65d623816..350cc69c28 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -31,7 +31,7 @@ /* Serial (pl011) */ #define UART_CLK (62500000) -#define CONFIG_PL011_CLOCK UART_CLK +#define CFG_PL011_CLOCK UART_CLK #define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h index 8ba40546b2..2bca86bed9 100644 --- a/include/configs/thunderx_88xx.h +++ b/include/configs/thunderx_88xx.h @@ -17,7 +17,7 @@ /* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 /* Generic Interrupt Controller Definitions */ #define GICD_BASE (0x801000000000) diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index e007be8e45..436bf622e1 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -14,7 +14,7 @@ #define UART0_BASE 0x7ff80000 /* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 7372800 +#define CFG_PL011_CLOCK 7372800 /* Miscellaneous configurable options */ diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h index 87b8c5d57e..43f7e454d8 100644 --- a/include/configs/vexpress_aemv8.h +++ b/include/configs/vexpress_aemv8.h @@ -86,9 +86,9 @@ /* PL011 Serial Configuration */ #ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_PL011_CLOCK 7372800 +#define CFG_PL011_CLOCK 7372800 #else -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #endif /* Physical Memory Map */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 705a941e36..3fc70de577 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -116,7 +116,7 @@ #define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) /* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 24000000 +#define CFG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1} From b861574bd9e7c480ceec47b77a59ed5a52b57937 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:31 -0500 Subject: [PATCH 307/424] global: Migrate CONFIG_PL01x_PORTS to CFG Perform a simple rename of CONFIG_PL01x_PORTS to CFG_PL01x_PORTS Signed-off-by: Tom Rini --- README | 2 +- drivers/serial/serial_pl01x.c | 2 +- include/configs/lx2160a_common.h | 2 +- include/configs/mxs.h | 2 +- include/configs/s5p4418_nanopi2.h | 2 +- include/configs/synquacer.h | 2 +- include/configs/vexpress_common.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/README b/README index 8354cf5699..12672d2bfb 100644 --- a/README +++ b/README @@ -418,7 +418,7 @@ The following options need to be configured: If you have Amba PrimeCell PL011 UARTs, set this variable to the clock speed of the UARTs. - CONFIG_PL01x_PORTS + CFG_PL01x_PORTS If you have Amba PrimeCell PL010 or PL011 UARTs on your board, define this to a list of base addresses for each (supported) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index dd2881931d..7449e9b904 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_DM_SERIAL -static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; +static volatile unsigned char *const port[] = CFG_PL01x_PORTS; static enum pl01x_type pl01x_type __section(".data"); static struct pl01x_regs *base_regs __section(".data"); #define NUM_PORTS (sizeof(port)/sizeof(port[0])) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index f8a20ea16f..6f46ca78d4 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -45,7 +45,7 @@ #define CFG_SYS_SERIAL2 0x21e0000 #define CFG_SYS_SERIAL3 0x21f0000 /*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ +#define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1, \ (void *)CFG_SYS_SERIAL2, \ (void *)CFG_SYS_SERIAL3 } diff --git a/include/configs/mxs.h b/include/configs/mxs.h index 90cb1a5e4a..6ebfee6927 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -78,7 +78,7 @@ * Conflicts with AUART driver which can be set by board. */ #define CFG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } +#define CFG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } /* Default baudrate can be overridden by board! */ /* NAND */ diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 0e7d01925e..2fa44e65fc 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -77,7 +77,7 @@ * serial console configuration */ #define CFG_PL011_CLOCK 50000000 -#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ +#define CFG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ (void *)PHY_BASEADDR_UART1, \ (void *)PHY_BASEADDR_UART2, \ (void *)PHY_BASEADDR_UART3} diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 350cc69c28..8f44c6f66a 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -32,7 +32,7 @@ /* Serial (pl011) */ #define UART_CLK (62500000) #define CFG_PL011_CLOCK UART_CLK -#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)} +#define CFG_PL01x_PORTS {(void *)(0x2a400000)} /* Support MTD */ #define CFG_SYS_FLASH_BASE (0x08000000) diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 3fc70de577..ba7731bfca 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -117,7 +117,7 @@ /* PL011 Serial Configuration */ #define CFG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ +#define CFG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \ (void *)CFG_SYS_SERIAL1} #define CFG_SYS_SERIAL0 V2M_UART0 From b33953b796ccaafdff903455860b86659c3f44f3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:32 -0500 Subject: [PATCH 308/424] global: Migrate CONFIG_PME_PLAT_CLK_DIV to CFG Perform a simple rename of CONFIG_PME_PLAT_CLK_DIV to CFG_PME_PLAT_CLK_DIV Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/speed.c | 6 +++--- arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index eec071022e..c2e3e00f7b 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -67,7 +67,7 @@ void get_sys_info(sys_info_t *sys_info) [14] = 4, /* CC4 PPL / 4 */ }; uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; -#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV) uint rcw_tmp; #endif uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -206,7 +206,7 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SEL 0x1c000000 #define FM1_CLK_SHIFT 26 #endif -#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if !defined(CFG_FM_PLAT_CLK_DIV) || !defined(CFG_PME_PLAT_CLK_DIV) #if defined(CONFIG_ARCH_T1024) rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; #else @@ -215,7 +215,7 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_PME -#ifndef CONFIG_PME_PLAT_CLK_DIV +#ifndef CFG_PME_PLAT_CLK_DIV switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) { case 1: sys_info->freq_pme = freq_c_pll[CFG_SYS_PME_CLK]; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 283181ec2d..fc584895ee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -144,8 +144,8 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 -#define CONFIG_PME_PLAT_CLK_DIV 2 -#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_PME_PLAT_CLK_DIV 2 +#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_FM_PLAT_CLK_DIV 1 #define CFG_SYS_FM1_CLK CFG_FM_PLAT_CLK_DIV @@ -182,8 +182,8 @@ #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif -#define CONFIG_PME_PLAT_CLK_DIV 1 -#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_PME_PLAT_CLK_DIV 1 +#define CFG_SYS_PME_CLK CFG_PME_PLAT_CLK_DIV #define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FM_MURAM_SIZE 0x28000 From 2adbb297471b39741e3e6e2ef04c56187ccaaf68 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:33 -0500 Subject: [PATCH 309/424] global: Migrate CONFIG_POSTBOOTMENU to CFG Perform a simple rename of CONFIG_POSTBOOTMENU to CFG_POSTBOOTMENU Signed-off-by: Tom Rini --- cmd/bootmenu.c | 4 ++-- include/configs/nokia_rx51.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index 3340be1632..e5a10f5d5c 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -577,8 +577,8 @@ cleanup: free(command); } -#ifdef CONFIG_POSTBOOTMENU - run_command(CONFIG_POSTBOOTMENU, 0); +#ifdef CFG_POSTBOOTMENU + run_command(CFG_POSTBOOTMENU, 0); #endif if (efi_ret != EFI_SUCCESS || cmd_ret != CMD_RET_SUCCESS) diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 97d0868529..a64b7b34dc 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -128,7 +128,7 @@ "bootmenu_delay=30\0" \ "" -#define CONFIG_POSTBOOTMENU \ +#define CFG_POSTBOOTMENU \ "echo;" \ "echo Extra commands:;" \ "echo run sdboot - Boot from SD card slot.;" \ From 6d38c69e835b5a918d324da16c34a697aeb3276f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:34 -0500 Subject: [PATCH 310/424] global: Migrate CONFIG_POWER_LTC3676_I2C_ADDR to CFG Perform a simple rename of CONFIG_POWER_LTC3676_I2C_ADDR to CFG_POWER_LTC3676_I2C_ADDR Signed-off-by: Tom Rini --- board/gateworks/gw_ventana/gw_ventana_spl.c | 4 ++-- drivers/power/pmic/pmic_ltc3676.c | 2 +- include/configs/gw_ventana.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index e85a00954c..6ad994af1c 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -851,8 +851,8 @@ void setup_pmic(void) } /* configure LTC3676 PMIC */ - else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { - debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); + else if (!i2c_probe(CFG_POWER_LTC3676_I2C_ADDR)) { + debug("probed LTC3676@0x%x\n", CFG_POWER_LTC3676_I2C_ADDR); power_ltc3676_init(i2c_pmic); p = pmic_get("LTC3676_PMIC"); if (!p || pmic_probe(p)) diff --git a/drivers/power/pmic/pmic_ltc3676.c b/drivers/power/pmic/pmic_ltc3676.c index 00c3e201cd..af94f37b0f 100644 --- a/drivers/power/pmic/pmic_ltc3676.c +++ b/drivers/power/pmic/pmic_ltc3676.c @@ -23,7 +23,7 @@ int power_ltc3676_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; p->number_of_regs = LTC3676_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_LTC3676_I2C_ADDR; + p->hw.i2c.addr = CFG_POWER_LTC3676_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 0a9dfe736f..85a2ad21dc 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -31,7 +31,7 @@ * PMIC */ #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c +#define CFG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ From aa3efb6c64513ad3d5eb876488a90b2ee2b8ccc0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:35 -0500 Subject: [PATCH 311/424] global: Migrate CONFIG_POWER_PFUZE100_I2C_ADDR to CFG Perform a simple rename of CONFIG_POWER_PFUZE100_I2C_ADDR to CFG_POWER_PFUZE100_I2C_ADDR Signed-off-by: Tom Rini --- board/gateworks/gw_ventana/gw_ventana_spl.c | 4 ++-- drivers/power/pmic/pmic_pfuze100.c | 2 +- include/configs/el6x_common.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sabresd.h | 2 +- include/configs/novena.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/vining_2000.h | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 6ad994af1c..2f046c9c0b 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -791,8 +791,8 @@ void setup_pmic(void) i2c_set_bus_num(i2c_pmic); /* configure PFUZE100 PMIC */ - if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { - debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); + if (!i2c_probe(CFG_POWER_PFUZE100_I2C_ADDR)) { + debug("probed PFUZE100@0x%x\n", CFG_POWER_PFUZE100_I2C_ADDR); power_pfuze100_init(i2c_pmic); p = pmic_get("PFUZE100"); if (p && !pmic_probe(p)) { diff --git a/drivers/power/pmic/pmic_pfuze100.c b/drivers/power/pmic/pmic_pfuze100.c index c646a0c31f..5115b55e49 100644 --- a/drivers/power/pmic/pmic_pfuze100.c +++ b/drivers/power/pmic/pmic_pfuze100.c @@ -23,7 +23,7 @@ int power_pfuze100_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; p->number_of_regs = PFUZE100_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_PFUZE100_I2C_ADDR; + p->hw.i2c.addr = CFG_POWER_PFUZE100_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 6913a91c4c..78af42d045 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -17,7 +17,7 @@ #define CFG_SYS_FSL_USDHC_NUM 2 /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* Commands */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 85a2ad21dc..ebc5d03d0d 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -30,7 +30,7 @@ /* * PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define CFG_POWER_LTC3676_I2C_ADDR 0x3c /* Various command support */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index a7a51907f5..d2de2900c0 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -18,7 +18,7 @@ #define CFG_MALLOC_F_ADDR 0x182000 /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* ENET Config */ diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index bf590efb43..e3a021c987 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -20,7 +20,7 @@ /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* ENET1 Config */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index da98139d7d..05ae2fce1f 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -36,6 +36,6 @@ /* DMA stuff, needed for GPMI/MXS NAND support */ /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 1aa8a56cce..30d3b9d930 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -25,7 +25,7 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/novena.h b/include/configs/novena.h index 5e8b7fa621..39d3afd1c8 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -46,7 +46,7 @@ #endif /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* UART */ #define CFG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index af5a474cf3..8c75a75a9e 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -31,7 +31,7 @@ #define CFG_I2C_MULTI_BUS #if !defined(CONFIG_DM_PMIC) -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 #define TQMA6_PFUZE100_I2C_BUS 2 #endif diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 7bfc22c043..30654191a2 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -31,7 +31,7 @@ #define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 /* Network */ #define CFG_FEC_MXC_PHYADDR 0x0 From 193b3fe1756b7fcb5fa4432ef6642ba5c5004115 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:36 -0500 Subject: [PATCH 312/424] global: Migrate CONFIG_POWER_PFUZE3000_I2C_ADDR to CFG Perform a simple rename of CONFIG_POWER_PFUZE3000_I2C_ADDR to CFG_POWER_PFUZE3000_I2C_ADDR Signed-off-by: Tom Rini --- drivers/power/pmic/pmic_pfuze3000.c | 2 +- include/configs/cl-som-imx7.h | 2 +- include/configs/pico-imx7d.h | 2 +- include/configs/udoo_neo.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/power/pmic/pmic_pfuze3000.c b/drivers/power/pmic/pmic_pfuze3000.c index 1077fa5e9d..a6d97252bc 100644 --- a/drivers/power/pmic/pmic_pfuze3000.c +++ b/drivers/power/pmic/pmic_pfuze3000.c @@ -23,7 +23,7 @@ int power_pfuze3000_init(unsigned char bus) p->name = name; p->interface = PMIC_I2C; p->number_of_regs = PFUZE3000_NUM_OF_REGS; - p->hw.i2c.addr = CONFIG_POWER_PFUZE3000_I2C_ADDR; + p->hw.i2c.addr = CFG_POWER_PFUZE3000_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 0a667c60b6..280ae1e9cc 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -19,7 +19,7 @@ #define IMX_FEC_BASE ENET_IPS_BASE_ADDR /* PMIC */ -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 #define CFG_SYS_I2C_PCA953X_ADDR 0x20 #define CFG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index fd8962e9f7..5774184300 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -98,7 +98,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 /* FLASH and environment organization */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 842abb7b7a..80386414f8 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -62,7 +62,7 @@ #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE /* PMIC */ -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08 #define PFUZE3000_I2C_BUS 0 #endif /* __CONFIG_H */ From 7c5c137c4101c309d5c6ac2d29b202e5450960bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:37 -0500 Subject: [PATCH 313/424] global: Migrate CONFIG_PRAM to CFG Perform a simple rename of CONFIG_PRAM to CFG_PRAM Signed-off-by: Tom Rini --- README | 4 ++-- common/board_f.c | 8 ++++---- common/board_r.c | 6 +++--- include/configs/M5208EVBE.h | 2 +- include/configs/M5235EVB.h | 2 +- include/configs/M5249EVB.h | 2 +- include/configs/M53017EVB.h | 2 +- include/configs/M5329EVB.h | 2 +- include/configs/M5373EVB.h | 2 +- include/configs/am43xx_evm.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/kmcent2.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/stmark2.h | 2 +- include/configs/ti_omap5_common.h | 2 +- 15 files changed, 21 insertions(+), 21 deletions(-) diff --git a/README b/README index 12672d2bfb..2d3a48e88a 100644 --- a/README +++ b/README @@ -1069,11 +1069,11 @@ The following options need to be configured: or define CFG_ENV_FLAGS_LIST_STATIC. - Protected RAM: - CONFIG_PRAM + CFG_PRAM Define this variable to enable the reservation of "protected RAM", i. e. RAM which is not overwritten - by U-Boot. Define CONFIG_PRAM to hold the number of + by U-Boot. Define CFG_PRAM to hold the number of kB you want to reserve for pRAM. You can overwrite this default value by defining an environment variable "pram" to the number of kB you want to diff --git a/common/board_f.c b/common/board_f.c index e027248db5..2b4edf30c9 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -380,19 +380,19 @@ static int setup_dest_addr(void) return arch_setup_dest_addr(); } -#ifdef CONFIG_PRAM +#ifdef CFG_PRAM /* reserve protected RAM */ static int reserve_pram(void) { ulong reg; - reg = env_get_ulong("pram", 10, CONFIG_PRAM); + reg = env_get_ulong("pram", 10, CFG_PRAM); gd->relocaddr -= (reg << 10); /* size is in kB */ debug("Reserving %ldk for protected RAM at %08lx\n", reg, gd->relocaddr); return 0; } -#endif /* CONFIG_PRAM */ +#endif /* CFG_PRAM */ /* Round memory pointer down to next 4 kB limit */ static int reserve_round_4k(void) @@ -925,7 +925,7 @@ static const init_fnc_t init_sequence_f[] = { #ifdef CONFIG_OF_BOARD_FIXUP fix_fdt, #endif -#ifdef CONFIG_PRAM +#ifdef CFG_PRAM reserve_pram, #endif reserve_round_4k, diff --git a/common/board_r.c b/common/board_r.c index 347bb7f7c0..42060ee709 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -533,7 +533,7 @@ static int initr_ide(void) } #endif -#if defined(CONFIG_PRAM) +#if defined(CFG_PRAM) /* * Export available size of memory for Linux, taking into account the * protected RAM at top of memory @@ -543,7 +543,7 @@ int initr_mem(void) ulong pram = 0; char memsz[32]; - pram = env_get_ulong("pram", 10, CONFIG_PRAM); + pram = env_get_ulong("pram", 10, CFG_PRAM); sprintf(memsz, "%ldk", (long int)((gd->ram_size / 1024) - pram)); env_set("mem", memsz); @@ -791,7 +791,7 @@ static init_fnc_t init_sequence_r[] = { */ last_stage_init, #endif -#if defined(CONFIG_PRAM) +#if defined(CFG_PRAM) initr_mem, #endif run_main_loop, diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index f7aba6e417..a4fda551f1 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -29,7 +29,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 166666666 /* CPU Core Clock */ #define CFG_SYS_PLL_ODR 0x36 diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 049516edf4..8939c8e7ab 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -39,7 +39,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 75000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2 diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index c71130909f..4fd539c017 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -57,7 +57,7 @@ #define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE) #if 0 /* test-only */ -#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ +#define CFG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ #endif /* diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index b6d82c730c..6359915e09 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -42,7 +42,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 80000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index d74a636fd7..456135bdc6 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -34,7 +34,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 80000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index fa6f2d23e7..4e8dcb5ef7 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -36,7 +36,7 @@ "save\0" \ "" -#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PRAM 512 /* 512 KB */ #define CFG_SYS_CLK 80000000 #define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3 diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index f43e00e8a2..a2f73c4754 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -152,7 +152,7 @@ #if defined(CONFIG_TI_SECURE_DEVICE) /* Avoid relocating onto firewalled area at end of DRAM */ -#define CONFIG_PRAM (64 * 1024) +#define CFG_PRAM (64 * 1024) #endif /* CONFIG_TI_SECURE_DEVICE */ #endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index ffd394691a..423bb773e9 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -9,7 +9,7 @@ #define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + \ +#define CFG_PRAM ((CONFIG_KM_PNVRAM + \ CONFIG_KM_PHRAM + \ CONFIG_KM_RESERVED_PRAM) >> 10) diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index a4b6a6e555..33ee23ece1 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -170,7 +170,7 @@ /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable * is not valid yet, which is the case for when u-boot copies itself to RAM */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) +#define CFG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) /* * IFC Definitions diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index a64b7b34dc..54eea322dd 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -169,6 +169,6 @@ #define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE) /* Reserve protected RAM for attached kernel */ -#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1) +#define CFG_PRAM ((KERNEL_MAXSIZE >> 10)+1) #endif /* __CONFIG_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index fe2ba9a03b..19589be270 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -36,7 +36,7 @@ /* Input, PCI, Flexbus, and VCO */ -#define CONFIG_PRAM 2048 /* 2048 KB */ +#define CFG_PRAM 2048 /* 2048 KB */ #define CFG_SYS_MBAR 0xFC000000 diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index e9723ed5b3..74a39c4078 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -279,7 +279,7 @@ * firewall violation, we tell u-boot that memory is protected RAM (PRAM) */ #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) -#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 +#define CFG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 #endif #else /* From 62350c72d4bb4142e17bc594715456fa472d6b14 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:38 -0500 Subject: [PATCH 314/424] global: Migrate CONFIG_QBMAN_CLK_DIV to CFG Perform a simple rename of CONFIG_QBMAN_CLK_DIV to CFG_QBMAN_CLK_DIV Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/speed.c | 6 +++--- arch/powerpc/include/asm/config_mpc85xx.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index c2e3e00f7b..9af40310b4 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -249,10 +249,10 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_QBMAN -#ifndef CONFIG_QBMAN_CLK_DIV -#define CONFIG_QBMAN_CLK_DIV 2 +#ifndef CFG_QBMAN_CLK_DIV +#define CFG_QBMAN_CLK_DIV 2 #endif - sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; + sys_info->freq_qman = sys_info->freq_systembus / CFG_QBMAN_CLK_DIV; #endif #if defined(CONFIG_SYS_MAPLE) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index fc584895ee..d731ac3f4d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -163,7 +163,7 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CFG_SYS_FM1_CLK 0 -#define CONFIG_QBMAN_CLK_DIV 1 +#define CFG_QBMAN_CLK_DIV 1 #define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL From d4c8dd1e6f7ca7740acd20eb3c97e051be94c375 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:39 -0500 Subject: [PATCH 315/424] global: Migrate CONFIG_RAMDISK_ADDR to CFG Perform a simple rename of CONFIG_RAMDISK_ADDR to CFG_RAMDISK_ADDR Signed-off-by: Tom Rini --- cmd/qfw.c | 4 ++-- doc/usage/cmd/qfw.rst | 2 +- include/configs/x86-common.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cmd/qfw.c b/cmd/qfw.c index 95ddc4b79e..0c49c6074e 100644 --- a/cmd/qfw.c +++ b/cmd/qfw.c @@ -130,8 +130,8 @@ static int qemu_fwcfg_do_load(struct cmd_tbl *cmdtp, int flag, env = env_get("ramdiskaddr"); initrd_addr = env ? (void *)hextoul(env, NULL) : -#ifdef CONFIG_RAMDISK_ADDR - (void *)CONFIG_RAMDISK_ADDR; +#ifdef CFG_RAMDISK_ADDR + (void *)CFG_RAMDISK_ADDR; #else NULL; #endif diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst index b3704b92d6..cc0e27c277 100644 --- a/doc/usage/cmd/qfw.rst +++ b/doc/usage/cmd/qfw.rst @@ -31,7 +31,7 @@ kernel_addr initrd_addr address to which the file specified by the -initrd parameter of QEMU shall be loaded. Defaults to environment variable *ramdiskaddr* and further to - the value of *CONFIG_RAMDISK_ADDR*. + the value of *CFG_RAMDISK_ADDR*. Examples -------- diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 5d461e8d0c..f421ec5803 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -25,7 +25,7 @@ */ /* Default environment */ -#define CONFIG_RAMDISK_ADDR 0x4000000 +#define CFG_RAMDISK_ADDR 0x4000000 #if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) #define CFG_OTHBOOTARGS "othbootargs=\0" #else From 3db78c830fda7cac7ef1a9b739f1a603bcfb58be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:40 -0500 Subject: [PATCH 316/424] global: Migrate CONFIG_RESET_VECTOR_ADDRESS to CFG Perform a simple rename of CONFIG_RESET_VECTOR_ADDRESS to CFG_RESET_VECTOR_ADDRESS Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/Kconfig | 2 +- arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 ++-- arch/powerpc/dts/kmcent2-u-boot.dtsi | 2 +- arch/powerpc/dts/u-boot.dtsi | 6 +++--- board/freescale/p1_p2_rdb_pc/README | 2 +- board/freescale/p2041rdb/README | 2 +- board/freescale/t104xrdb/README | 2 +- board/freescale/t208xqds/README | 2 +- board/freescale/t208xrdb/README | 2 +- include/configs/P1010RDB.h | 8 ++++---- include/configs/P2041RDB.h | 8 ++++---- include/configs/T102xRDB.h | 10 +++++----- include/configs/T104xRDB.h | 8 ++++---- include/configs/T208xQDS.h | 10 +++++----- include/configs/T208xRDB.h | 10 +++++----- include/configs/T4240RDB.h | 8 ++++---- include/configs/kmcent2.h | 2 +- include/configs/p1_p2_rdb_pc.h | 4 ++-- 18 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 3275d4fa9b..6ab8a5249a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -931,7 +931,7 @@ config ARCH_T4240 imply FSL_SATA config MPC85XX_HAVE_RESET_VECTOR - bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" + bool "Indicate reset vector at CFG_RESET_VECTOR_ADDRESS - 0xffc" depends on MPC85xx config BTB diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index fa3aa954cb..3af0dfdf33 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -5,8 +5,8 @@ #include "config.h" -#ifdef CONFIG_RESET_VECTOR_ADDRESS -#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS +#ifdef CFG_RESET_VECTOR_ADDRESS +#define RESET_VECTOR_ADDRESS CFG_RESET_VECTOR_ADDRESS #else #define RESET_VECTOR_ADDRESS 0xfffffffc #endif diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index 28f303b749..53bac5533f 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -91,7 +91,7 @@ align = <256>; }; powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>; }; }; }; diff --git a/arch/powerpc/dts/u-boot.dtsi b/arch/powerpc/dts/u-boot.dtsi index b4b5257362..6b7375cff2 100644 --- a/arch/powerpc/dts/u-boot.dtsi +++ b/arch/powerpc/dts/u-boot.dtsi @@ -23,11 +23,11 @@ u-boot-dtb-with-ucode { align = <4>; }; -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; + offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>; }; }; }; diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index f542decec7..fd849bfc29 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -57,7 +57,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="p1020rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/board/freescale/p2041rdb/README b/board/freescale/p2041rdb/README index 96612daeeb..ae77027737 100644 --- a/board/freescale/p2041rdb/README +++ b/board/freescale/p2041rdb/README @@ -98,7 +98,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc CPLD command ============ diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index e90dca4166..f312e6a3e3 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -379,7 +379,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index 63953d6b9b..0d80c6901f 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -285,7 +285,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index 60551f6723..533054bfe1 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -281,7 +281,7 @@ enabled in relative defconfig file, 1. CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" (Change default device tree name if required) 2. CONFIG_OF_CONTROL 3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at - CONFIG_RESET_VECTOR_ADDRESS - 0xffc + CFG_RESET_VECTOR_ADDRESS - 0xffc If device tree support is enabled in defconfig, 1. use 'u-boot.bin' for NOR boot. diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b57e8638ab..9efae58ce9 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -24,7 +24,7 @@ #ifdef CONFIG_SPIFLASH #ifdef CONFIG_NXP_ESBC -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc #else #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) @@ -52,11 +52,11 @@ #endif #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc +#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* High Level Configuration Options */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 6e755fc0a8..28f53ae78a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,7 +12,7 @@ #define __CONFIG_H #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE @@ -20,13 +20,13 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif /* High Level Configuration Options */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 063b864f9f..7ee46abffd 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -28,7 +28,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) @@ -36,7 +36,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) #define CFG_SYS_MMC_U_BOOT_START (0x30000000) @@ -45,8 +45,8 @@ #endif /* CONFIG_RAMBOOT_PBL */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* @@ -87,7 +87,7 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif /* diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 9d04d30a53..f196bd76e6 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -29,7 +29,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) @@ -37,7 +37,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC +#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x30000000) #define CFG_SYS_MMC_U_BOOT_START (0x30000000) @@ -48,8 +48,8 @@ /* High Level Configuration Options */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 3b98d25aa4..2023d7497f 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -30,7 +30,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) @@ -38,7 +38,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x00200000) #define CFG_SYS_MMC_U_BOOT_START (0x00200000) @@ -52,11 +52,11 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 60c2947bfc..f213d2de77 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -30,7 +30,7 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) #define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) #define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) @@ -38,7 +38,7 @@ #endif #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST (0x00200000) #define CFG_SYS_MMC_U_BOOT_START (0x00200000) @@ -52,11 +52,11 @@ #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif /* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 01a9f43cba..506f1b7e26 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -16,13 +16,13 @@ #ifdef CONFIG_RAMBOOT_PBL #ifndef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc #else #define RESET_VECTOR_OFFSET 0x27FFC #define BOOT_PAGE_OFFSET 0x27000 #ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC +#define CFG_RESET_VECTOR_ADDRESS 0x200FFC #define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10) #define CFG_SYS_MMC_U_BOOT_DST 0x00200000 #define CFG_SYS_MMC_U_BOOT_START 0x00200000 @@ -34,8 +34,8 @@ /* High Level Configuration Options */ -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 33ee23ece1..58dff495ac 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -122,7 +122,7 @@ /* High Level Configuration Options */ -#define CONFIG_RESET_VECTOR_ADDRESS 0xebfffffc +#define CFG_RESET_VECTOR_ADDRESS 0xebfffffc #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 41e7f53bd5..832ad9c3ec 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -105,8 +105,8 @@ #endif /* not CONFIG_TPL_BUILD */ #endif -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#ifndef CFG_RESET_VECTOR_ADDRESS +#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CFG_SYS_CCSRBAR 0xffe00000 From f9932d38a326e18113cc2daf8449c332e46c97a6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:41 -0500 Subject: [PATCH 317/424] global: Migrate CONFIG_SAR2_REG to CFG Perform a simple rename of CONFIG_SAR2_REG to CFG_SAR2_REG Signed-off-by: Tom Rini --- arch/arm/mach-mvebu/cpu.c | 4 ++-- arch/arm/mach-mvebu/include/mach/soc.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 67ad5e5907..9139df1ae2 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -195,7 +195,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) int i; #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) - val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */ #else val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ #endif @@ -205,7 +205,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) * Shift CPU0 clock frequency select bit from SAR2 register * into correct position */ - freq |= ((readl(CONFIG_SAR2_REG) & SAR2_CPU_FREQ_MASK) + freq |= ((readl(CFG_SAR2_REG) & SAR2_CPU_FREQ_MASK) >> SAR2_CPU_FREQ_OFFS) << 3; #endif for (i = 0; sar_freq_tab[i].val != 0xff; i++) { diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index e6383d4a86..1210d26c74 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -135,7 +135,7 @@ #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) -#define CONFIG_SAR2_REG (MVEBU_REGISTER(0xe8204)) +#define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204)) #define SAR_CPU_FREQ_OFFS 17 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) @@ -174,7 +174,7 @@ #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) -#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) +#define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) #define SAR_CPU_FREQ_OFFS 18 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) @@ -192,7 +192,7 @@ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) -#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234)) +#define CFG_SAR2_REG (MVEBU_REGISTER(0x18234)) #define SAR_CPU_FREQ_OFFS 21 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) From 9dbe356ef4ad07221ca488e48eb1ef604859ca72 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:42 -0500 Subject: [PATCH 318/424] global: Migrate CONFIG_SAR_REG to CFG Perform a simple rename of CONFIG_SAR_REG to CFG_SAR_REG Signed-off-by: Tom Rini --- arch/arm/mach-kirkwood/include/mach/kw88f6281.h | 2 +- arch/arm/mach-kirkwood/include/mach/soc.h | 2 +- arch/arm/mach-mvebu/cpu.c | 4 ++-- arch/arm/mach-mvebu/include/mach/soc.h | 12 ++++++------ 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index 7f8e156a6b..67f0b3ec67 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,7 +15,7 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE /* TCLK Core Clock definition */ -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(21)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(21)) ? \ 166666667 : 200000000) #endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h index 5f545c6f43..4a7efc50f6 100644 --- a/arch/arm/mach-kirkwood/include/mach/soc.h +++ b/arch/arm/mach-kirkwood/include/mach/soc.h @@ -62,7 +62,7 @@ #define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE #define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE -#define CONFIG_SAR_REG (KW_MPP_BASE + 0x0030) +#define CFG_SAR_REG (KW_MPP_BASE + 0x0030) #if defined (CONFIG_KW88F6281) #include diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 9139df1ae2..329d13691f 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -83,7 +83,7 @@ u32 get_boot_device(void) /* * Now check the SAR register for the strapped boot-device */ - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); switch (boot_device) { @@ -197,7 +197,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) #if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) val = readl(CFG_SAR2_REG); /* SAR - Sample At Reset */ #else - val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ + val = readl(CFG_SAR_REG); /* SAR - Sample At Reset */ #endif freq = (val & SAR_CPU_FREQ_MASK) >> SAR_CPU_FREQ_OFFS; #if defined(SAR2_CPU_FREQ_MASK) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 1210d26c74..6edd2e2d79 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -134,7 +134,7 @@ #if defined(CONFIG_ARMADA_375) /* SAR values for Armada 375 */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0xe8200)) +#define CFG_SAR_REG (MVEBU_REGISTER(0xe8200)) #define CFG_SAR2_REG (MVEBU_REGISTER(0xe8204)) #define SAR_CPU_FREQ_OFFS 17 @@ -146,11 +146,11 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(20)) ? \ 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18600)) #define SAR_CPU_FREQ_OFFS 10 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS) @@ -169,11 +169,11 @@ #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 -#define CFG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ +#define CFG_SYS_TCLK ((readl(CFG_SAR_REG) & BIT(15)) ? \ 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ -#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CFG_SAR_REG (MBUS_DFX_BASE + 0xf8200) #define CFG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) #define SAR_CPU_FREQ_OFFS 18 @@ -191,7 +191,7 @@ #define CFG_SYS_TCLK 200000000 /* 200MHz */ #elif defined(CONFIG_ARMADA_XP) /* SAR values for Armada XP */ -#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) +#define CFG_SAR_REG (MVEBU_REGISTER(0x18230)) #define CFG_SAR2_REG (MVEBU_REGISTER(0x18234)) #define SAR_CPU_FREQ_OFFS 21 From dbfaeecf597b1fb1322f357b8253cc6198081f17 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:43 -0500 Subject: [PATCH 319/424] global: Migrate CONFIG_SCIF_A to CFG Perform a simple rename of CONFIG_SCIF_A to CFG_SCIF_A Signed-off-by: Tom Rini --- drivers/serial/serial_sh.c | 2 +- drivers/serial/serial_sh.h | 8 ++++---- include/configs/stout.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index e6c23cedff..4671217b59 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -274,7 +274,7 @@ U_BOOT_DRIVER(serial_sh) = { # error "Default SCIF doesn't set....." #endif -#if defined(CONFIG_SCIF_A) +#if defined(CFG_SCIF_A) #define SCIF_BASE_PORT PORT_SCIFA #elif defined(CONFIG_SCI) #define SCIF_BASE_PORT PORT_SCI diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 11deaa9511..e6ab6f1b9b 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -92,7 +92,7 @@ struct uart_port { # define SCIF_ORER 0x0001 /* overrun error bit */ #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \ defined(CONFIG_R7S72100) -# if defined(CONFIG_SCIF_A) +# if defined(CFG_SCIF_A) # define SCIF_ORER 0x0200 # else # define SCIF_ORER 0x0001 @@ -164,7 +164,7 @@ struct uart_port { # define SCIF2_TXROOM_MAX 16 #elif defined(CONFIG_RCAR_GEN2) # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) -# if defined(CONFIG_SCIF_A) +# if defined(CFG_SCIF_A) # define SCIF_RFDC_MASK 0x007f # else # define SCIF_RFDC_MASK 0x001f @@ -380,7 +380,7 @@ SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) -#if defined(CONFIG_SCIF_A) +#if defined(CFG_SCIF_A) SCIF_FNS(SCLSR, 0, 0, 0x14, 16) #else SCIF_FNS(SCLSR, 0, 0, 0x24, 16) @@ -491,7 +491,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk) #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #elif defined(CONFIG_RCAR_GEN2) #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ - #if defined(CONFIG_SCIF_A) + #if defined(CFG_SCIF_A) #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ #else #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index ee1abe691b..ea5828b950 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -23,7 +23,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SCIF */ -#define CONFIG_SCIF_A +#define CFG_SCIF_A /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 From 77d0870c2901b28e003fa256c00d8570b2066cae Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:44 -0500 Subject: [PATCH 320/424] global: Migrate CONFIG_SCSI_DEV_LIST to CFG Perform a simple rename of CONFIG_SCSI_DEV_LIST to CFG_SCSI_DEV_LIST Signed-off-by: Tom Rini --- drivers/scsi/scsi.c | 4 ++-- include/configs/ls1021aiot.h | 2 +- include/configs/ls1028ardb.h | 2 +- include/configs/ls1043ardb.h | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 3e769b0843..a020a7da23 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -18,8 +18,8 @@ #include #if !defined(CONFIG_DM_SCSI) -# ifdef CONFIG_SCSI_DEV_LIST -# define SCSI_DEV_LIST CONFIG_SCSI_DEV_LIST +# ifdef CFG_SCSI_DEV_LIST +# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST # else # ifdef CONFIG_SATA_ULI5288 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 8b5fba51c6..53d9936f4e 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -61,7 +61,7 @@ #ifndef PCI_DEVICE_ID_FREESCALE_AHCI #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 #endif -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ +#define CFG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ PCI_DEVICE_ID_FREESCALE_AHCI} /* SPI */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 8c53636bea..ee4f885c53 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -52,7 +52,7 @@ /* SATA */ #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} /* Initial environment variables */ #ifndef SPL_NO_ENV diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index c8a6f0146a..60362b6a4d 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -203,7 +203,7 @@ #ifndef SPL_NO_SATA #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} #endif #include From 3cdd6302a5c6cc2f6b59b845f6f1fc31061b1dd2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:45 -0500 Subject: [PATCH 321/424] global: Migrate CONFIG_SC_TIMER_CLK to CFG Perform a simple rename of CONFIG_SC_TIMER_CLK to CFG_SC_TIMER_CLK Signed-off-by: Tom Rini --- arch/arm/mach-imx/syscounter.c | 2 +- include/configs/mx6_common.h | 2 +- include/configs/mx7_common.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index df478a2326..129efac6fa 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -65,7 +65,7 @@ int timer_init(void) struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; unsigned long val, freq; - freq = CONFIG_SC_TIMER_CLK; + freq = CFG_SC_TIMER_CLK; asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); writel(freq, &sctr->cntfid0); diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index dd8cabc2e9..0b8233de8c 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -9,7 +9,7 @@ #include #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */ #else #ifndef CONFIG_SYS_L2CACHE_OFF #define CFG_SYS_PL310_BASE L2_PL310_BASE diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 6e14b4fbf0..a542839ce1 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -14,7 +14,7 @@ #include /* Timer settings */ -#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ +#define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */ /* Miscellaneous configurable options */ From ddc418703353f00215962bc083523784a1c01c32 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:46 -0500 Subject: [PATCH 322/424] global: Migrate CONFIG_SET_DFU_ALT_BUF_LEN to CFG Perform a simple rename of CONFIG_SET_DFU_ALT_BUF_LEN to CFG_SET_DFU_ALT_BUF_LEN Signed-off-by: Tom Rini --- board/samsung/common/misc.c | 2 +- include/configs/odroid.h | 2 +- include/configs/odroid_xu3.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 9c0ec29c93..5ffa216e2e 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SET_DFU_ALT_INFO void set_dfu_alt_info(char *interface, char *devstr) { - size_t buf_size = CONFIG_SET_DFU_ALT_BUF_LEN; + size_t buf_size = CFG_SET_DFU_ALT_BUF_LEN; ALLOC_CACHE_ALIGN_BUFFER(char, buf, buf_size); char *alt_info = "Settings not found!"; char *status = "error!\n"; diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 3ac13a65d6..560a23c23e 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -37,7 +37,7 @@ ""PARTS_BOOT" part 0 1;" \ ""PARTS_ROOT" part 0 2\0" \ -#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) +#define CFG_SET_DFU_ALT_BUF_LEN (SZ_1K) #define CFG_DFU_ALT_BOOT_EMMC \ "u-boot raw 0x3e 0x800 mmcpart 1;" \ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index 7304851d0f..58b5ee6ea0 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -49,7 +49,7 @@ "params.bin raw 0x1880 0x20\0" /* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ -#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) +#define CFG_SET_DFU_ALT_BUF_LEN (SZ_1K) /* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ #define CFG_ODROID_REV_AIN 9 From 24513c3ac85456e8c8256b83ecc44ccaedcee65a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:47 -0500 Subject: [PATCH 323/424] global: Migrate CONFIG_SH_ETHER_ALIGNE_SIZE to CFG Perform a simple rename of CONFIG_SH_ETHER_ALIGNE_SIZE to CFG_SH_ETHER_ALIGNE_SIZE Signed-off-by: Tom Rini --- drivers/net/sh_eth.c | 4 ++-- drivers/net/sh_eth.h | 16 ++++++++-------- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 0c584a23b9..90e47d93aa 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -41,7 +41,7 @@ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define flush_cache_wback(addr, len) \ flush_dcache_range((unsigned long)addr, \ - (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) + (unsigned long)(addr + ALIGN(len, CFG_SH_ETHER_ALIGNE_SIZE))) #else #define flush_cache_wback(...) #endif @@ -49,7 +49,7 @@ #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) #define invalidate_cache(addr, len) \ { \ - unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ unsigned long start, end; \ \ start = (unsigned long)addr; \ diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 520f7f7325..1c07610e1a 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -29,8 +29,8 @@ #endif /* defined(CONFIG_SH) */ /* base padding size is 16 */ -#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 16 +#ifndef CFG_SH_ETHER_ALIGNE_SIZE +#define CFG_SH_ETHER_ALIGNE_SIZE 16 #endif /* Number of supported ports */ @@ -47,7 +47,7 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +#define TX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { @@ -62,9 +62,9 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +#define RX_DESC_PADDING (CFG_SH_ETHER_ALIGNE_SIZE - 12) /* aligned cache line size */ -#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) +#define RX_BUF_ALIGNE_SIZE (CFG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { @@ -388,11 +388,11 @@ enum DMAC_M_BIT { #endif }; -#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 +#if CFG_SH_ETHER_ALIGNE_SIZE == 64 # define EMDR_DESC EDMR_DL1 -#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 +#elif CFG_SH_ETHER_ALIGNE_SIZE == 32 # define EMDR_DESC EDMR_DL0 -#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +#elif CFG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ # define EMDR_DESC 0 #endif diff --git a/include/configs/alt.h b/include/configs/alt.h index 29f4d06b7f..f06ceed47f 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 819184996e..6d7c788163 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -19,7 +19,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ /* XTAL_CLK : 33.33MHz */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 45f0ec6f6a..93157de470 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index dd6b22de7b..5b91e6ff03 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -22,6 +22,6 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 61ff80d2c9..ff02a87501 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 777d5b94d1..83e8705dfe 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 202bd914d5..8f834f2c7e 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -27,7 +27,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 9114a05758..80fce05b39 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -27,7 +27,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index ea5828b950..d8f0fb1856 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -31,7 +31,7 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ From c253cea724555890f533c8446fc53eff01ec39a0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:48 -0500 Subject: [PATCH 324/424] global: Migrate CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG Perform a simple rename of CONFIG_SH_ETHER_CACHE_INVALIDATE to CFG_SH_ETHER_CACHE_INVALIDATE Signed-off-by: Tom Rini --- drivers/net/sh_eth.c | 2 +- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 90e47d93aa..63b21969d5 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -46,7 +46,7 @@ #define flush_cache_wback(...) #endif -#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) +#if defined(CFG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) #define invalidate_cache(addr, len) \ { \ unsigned long line_size = CFG_SH_ETHER_ALIGNE_SIZE; \ diff --git a/include/configs/alt.h b/include/configs/alt.h index f06ceed47f..7a29157ef4 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/condor.h b/include/configs/condor.h index 6d7c788163..fa3edef9b3 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -18,7 +18,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/gose.h b/include/configs/gose.h index 93157de470..e54f4b24e0 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 5b91e6ff03..5ae17f70e9 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -21,7 +21,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 #endif /* __GRPEACH_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index ff02a87501..1d8aa6def8 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/lager.h b/include/configs/lager.h index 83e8705dfe..bb8cc5fecb 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/porter.h b/include/configs/porter.h index 8f834f2c7e..143e9a4672 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/silk.h b/include/configs/silk.h index 80fce05b39..2d1e23c274 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -26,7 +26,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ diff --git a/include/configs/stout.h b/include/configs/stout.h index d8f0fb1856..9e05a7ae6f 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -30,7 +30,7 @@ #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ From ff53ecc3877c6f4b1cc035a44b43b9c50e1fabc8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:49 -0500 Subject: [PATCH 325/424] global: Migrate CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG Perform a simple rename of CONFIG_SH_ETHER_CACHE_WRITEBACK to CFG_SH_ETHER_CACHE_WRITEBACK Signed-off-by: Tom Rini --- README | 2 +- drivers/net/sh_eth.c | 2 +- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/README b/README index 2d3a48e88a..5f688d70f3 100644 --- a/README +++ b/README @@ -547,7 +547,7 @@ The following options need to be configured: CONFIG_SH_ETHER_PHY_ADDR Define the ETH PHY's address - CONFIG_SH_ETHER_CACHE_WRITEBACK + CFG_SH_ETHER_CACHE_WRITEBACK If this option is set, the driver enables cache flush. - TPM Support: diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 63b21969d5..0053733075 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -37,7 +37,7 @@ # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif -#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \ +#if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define flush_cache_wback(addr, len) \ flush_dcache_range((unsigned long)addr, \ diff --git a/include/configs/alt.h b/include/configs/alt.h index 7a29157ef4..2b78325273 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/condor.h b/include/configs/condor.h index fa3edef9b3..3f99cbf9da 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -17,7 +17,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/gose.h b/include/configs/gose.h index e54f4b24e0..45a537341b 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -23,7 +23,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 5ae17f70e9..3fde614070 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -20,7 +20,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 1d8aa6def8..b3b6f03e08 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -23,7 +23,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/lager.h b/include/configs/lager.h index bb8cc5fecb..16d15ccdd9 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -24,7 +24,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/porter.h b/include/configs/porter.h index 143e9a4672..f217141af8 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/silk.h b/include/configs/silk.h index 2d1e23c274..09c23d379e 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -25,7 +25,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/stout.h b/include/configs/stout.h index 9e05a7ae6f..dd44b3e6d0 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -29,7 +29,7 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 From 7c480bab146f830220f1feef00ad1b9a5a64c6cb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:50 -0500 Subject: [PATCH 326/424] global: Migrate CONFIG_SH_ETHER_PHY_ADDR to CFG Perform a simple rename of CONFIG_SH_ETHER_PHY_ADDR to CFG_SH_ETHER_PHY_ADDR Signed-off-by: Tom Rini --- README | 2 +- drivers/net/sh_eth.c | 6 +++--- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) diff --git a/README b/README index 5f688d70f3..217fbaf557 100644 --- a/README +++ b/README @@ -544,7 +544,7 @@ The following options need to be configured: CONFIG_SH_ETHER_USE_PORT Define the number of ports to be used - CONFIG_SH_ETHER_PHY_ADDR + CFG_SH_ETHER_PHY_ADDR Define the ETH PHY's address CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 0053733075..3bf94cb2f7 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -33,8 +33,8 @@ #ifndef CONFIG_SH_ETHER_USE_PORT # error "Please define CONFIG_SH_ETHER_USE_PORT" #endif -#ifndef CONFIG_SH_ETHER_PHY_ADDR -# error "Please define CONFIG_SH_ETHER_PHY_ADDR" +#ifndef CFG_SH_ETHER_PHY_ADDR +# error "Please define CFG_SH_ETHER_PHY_ADDR" #endif #if defined(CFG_SH_ETHER_CACHE_WRITEBACK) && \ @@ -694,7 +694,7 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = miiphy_get_dev_by_name(udev->name); eth->port = CONFIG_SH_ETHER_USE_PORT; - eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; + eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; eth->port_info[eth->port].iobase = (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); diff --git a/include/configs/alt.h b/include/configs/alt.h index 2b78325273..06ab5ce669 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/condor.h b/include/configs/condor.h index 3f99cbf9da..43b88f1272 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -15,7 +15,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/gose.h b/include/configs/gose.h index 45a537341b..5184db4106 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -21,7 +21,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 3fde614070..8ba9b73672 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -18,7 +18,7 @@ /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0 +#define CFG_SH_ETHER_PHY_ADDR 0 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index b3b6f03e08..2910336def 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -21,7 +21,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/lager.h b/include/configs/lager.h index 16d15ccdd9..815239a73b 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/porter.h b/include/configs/porter.h index f217141af8..f732aeb47b 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/silk.h b/include/configs/silk.h index 09c23d379e..005eed1549 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE diff --git a/include/configs/stout.h b/include/configs/stout.h index dd44b3e6d0..cf90e4d464 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -27,7 +27,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CFG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE From 85b55117085fd6912f1c06eb74d864c44f515e66 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:51 -0500 Subject: [PATCH 327/424] global: Migrate CONFIG_SH_ETHER_PHY_MODE to CFG Perform a simple rename of CONFIG_SH_ETHER_PHY_MODE to CFG_SH_ETHER_PHY_MODE Signed-off-by: Tom Rini --- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/configs/alt.h b/include/configs/alt.h index 06ab5ce669..53c31562a5 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/condor.h b/include/configs/condor.h index 43b88f1272..2c9817cf02 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -16,7 +16,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/gose.h b/include/configs/gose.h index 5184db4106..ed7dd70dd9 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 8ba9b73672..6a11aa61f0 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -19,7 +19,7 @@ /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 2910336def..31d0795f07 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -22,7 +22,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/lager.h b/include/configs/lager.h index 815239a73b..991fc9020e 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -23,7 +23,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/porter.h b/include/configs/porter.h index f732aeb47b..1587c5c539 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -24,7 +24,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/silk.h b/include/configs/silk.h index 005eed1549..21100c46b1 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -24,7 +24,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 diff --git a/include/configs/stout.h b/include/configs/stout.h index cf90e4d464..51f4420ed6 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -28,7 +28,7 @@ /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK #define CFG_SH_ETHER_CACHE_INVALIDATE #define CFG_SH_ETHER_ALIGNE_SIZE 64 From 97148cb6142b2507972459b8f578c04717a52c40 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:52 -0500 Subject: [PATCH 328/424] global: Migrate CONFIG_SH_ETHER_USE_PORT to CFG Perform a simple rename of CONFIG_SH_ETHER_USE_PORT to CFG_SH_ETHER_USE_PORT Signed-off-by: Tom Rini --- README | 2 +- drivers/net/sh_eth.c | 6 +++--- include/configs/alt.h | 2 +- include/configs/condor.h | 2 +- include/configs/gose.h | 2 +- include/configs/grpeach.h | 2 +- include/configs/koelsch.h | 2 +- include/configs/lager.h | 2 +- include/configs/porter.h | 2 +- include/configs/silk.h | 2 +- include/configs/stout.h | 2 +- 11 files changed, 13 insertions(+), 13 deletions(-) diff --git a/README b/README index 217fbaf557..a9b225e45e 100644 --- a/README +++ b/README @@ -541,7 +541,7 @@ The following options need to be configured: CONFIG_SH_ETHER Support for Renesas on-chip Ethernet controller - CONFIG_SH_ETHER_USE_PORT + CFG_SH_ETHER_USE_PORT Define the number of ports to be used CFG_SH_ETHER_PHY_ADDR diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 3bf94cb2f7..8f162ca58f 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -30,8 +30,8 @@ #include "sh_eth.h" -#ifndef CONFIG_SH_ETHER_USE_PORT -# error "Please define CONFIG_SH_ETHER_USE_PORT" +#ifndef CFG_SH_ETHER_USE_PORT +# error "Please define CFG_SH_ETHER_USE_PORT" #endif #ifndef CFG_SH_ETHER_PHY_ADDR # error "Please define CFG_SH_ETHER_PHY_ADDR" @@ -693,7 +693,7 @@ static int sh_ether_probe(struct udevice *udev) priv->bus = miiphy_get_dev_by_name(udev->name); - eth->port = CONFIG_SH_ETHER_USE_PORT; + eth->port = CFG_SH_ETHER_USE_PORT; eth->port_info[eth->port].phy_addr = CFG_SH_ETHER_PHY_ADDR; eth->port_info[eth->port].iobase = (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port); diff --git a/include/configs/alt.h b/include/configs/alt.h index 53c31562a5..8f03762583 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -21,7 +21,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/condor.h b/include/configs/condor.h index 2c9817cf02..50c8d17338 100644 --- a/include/configs/condor.h +++ b/include/configs/condor.h @@ -14,7 +14,7 @@ /* Environment compatibility */ /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/gose.h b/include/configs/gose.h index ed7dd70dd9..7ae0726518 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -20,7 +20,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index 6a11aa61f0..8de4a36e93 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -17,7 +17,7 @@ #define CFG_SYS_SDRAM_SIZE (10 * 1024 * 1024) /* Network interface */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index 31d0795f07..d47d70178c 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -20,7 +20,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/lager.h b/include/configs/lager.h index 991fc9020e..2577c7a7da 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -21,7 +21,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/porter.h b/include/configs/porter.h index 1587c5c539..2cb430be8b 100644 --- a/include/configs/porter.h +++ b/include/configs/porter.h @@ -22,7 +22,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/silk.h b/include/configs/silk.h index 21100c46b1..7bed32d855 100644 --- a/include/configs/silk.h +++ b/include/configs/silk.h @@ -22,7 +22,7 @@ #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK diff --git a/include/configs/stout.h b/include/configs/stout.h index 51f4420ed6..1278ba63f4 100644 --- a/include/configs/stout.h +++ b/include/configs/stout.h @@ -26,7 +26,7 @@ #define CFG_SCIF_A /* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_USE_PORT 0 #define CFG_SH_ETHER_PHY_ADDR 0x1 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CFG_SH_ETHER_CACHE_WRITEBACK From 59f3a09a6c86e99f9790f9b534465b035863a5b4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:53 -0500 Subject: [PATCH 329/424] global: Migrate CONFIG_SLIC to CFG Perform a simple rename of CONFIG_SLIC to CFG_SLIC Signed-off-by: Tom Rini --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- include/configs/p1_p2_rdb_pc.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index df9f6ae473..4d7d042eaf 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -187,7 +187,7 @@ void board_gpio_init(void) setbits_be32(&pgpio->gpdat, 0x00080000); #endif -#ifdef CONFIG_SLIC +#ifdef CFG_SLIC /* reset SLIC */ setbits_be32(&pgpio->gpdir, 0x00040000); setbits_be32(&pgpio->gpdat, 0x00040000); diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 832ad9c3ec..be76801982 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -13,7 +13,7 @@ #include #if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_SLIC +#define CFG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x5c #define __SW_BOOT_SPI 0x1c @@ -42,7 +42,7 @@ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ #if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SLIC +#define CFG_SLIC #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0x64 #define __SW_BOOT_SPI 0x34 From 3e204427c8369d6c34c2beaac29a539a55c7be4f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:54 -0500 Subject: [PATCH 330/424] global: Migrate CONFIG_SMP_PEN_ADDR to CFG Perform a simple rename of CONFIG_SMP_PEN_ADDR to CFG_SMP_PEN_ADDR Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- board/samsung/arndale/arndale.c | 4 ++-- include/configs/arndale.h | 2 +- include/configs/km/pg-wcom-ls102xa.h | 2 +- include/configs/ls1021aiot.h | 2 +- include/configs/ls1021aqds.h | 2 +- include/configs/ls1021atwr.h | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index a303039ba5..9004074da2 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -205,11 +205,11 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) -#ifdef CONFIG_SMP_PEN_ADDR +#ifdef CFG_SMP_PEN_ADDR /* void __weak smp_waitloop(unsigned previous_address); */ WEAK(smp_waitloop) wfi - ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address + ldr r1, =CFG_SMP_PEN_ADDR @ load start address ldr r1, [r1] #ifdef CONFIG_PEN_ADDR_BIG_ENDIAN rev r1, r1 diff --git a/board/samsung/arndale/arndale.c b/board/samsung/arndale/arndale.c index a992dc6842..3ebf600e1d 100644 --- a/board/samsung/arndale/arndale.c +++ b/board/samsung/arndale/arndale.c @@ -112,10 +112,10 @@ int checkboard(void) } #endif -#ifdef CONFIG_SMP_PEN_ADDR +#ifdef CFG_SMP_PEN_ADDR void smp_set_core_boot_addr(unsigned long addr, int corenr) { - writel(addr, CONFIG_SMP_PEN_ADDR); + writel(addr, CFG_SMP_PEN_ADDR); /* make sure this write is really executed */ __asm__ volatile ("dsb\n"); diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 8acc525b11..b56effcd41 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -16,7 +16,7 @@ /* Miscellaneous configurable options */ -#define CONFIG_SMP_PEN_ADDR 0x02020000 +#define CFG_SMP_PEN_ADDR 0x02020000 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CFG_ARM_GIC_BASE_ADDRESS 0x10480000 diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 423bb773e9..15ef68a050 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -158,7 +158,7 @@ {1, {I2C_NULL_HOP} }, \ } -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 53d9936f4e..83ab94ec44 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -68,7 +68,7 @@ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 78432e5581..e4e5522a23 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -242,7 +242,7 @@ * MMC */ -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a387eeab47..eb8fb04272 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -133,7 +133,7 @@ /* GPIO */ -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CFG_SMP_PEN_ADDR 0x01ee0200 #define HWCONFIG_BUFFER_SIZE 256 From 6786ce1ce14feb4d02854a0c04bc0cce505be46e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:55 -0500 Subject: [PATCH 331/424] global: Migrate CONFIG_STACKBASE to CFG Perform a simple rename of CONFIG_STACKBASE to CFG_STACKBASE Signed-off-by: Tom Rini --- include/configs/tegra-common.h | 2 +- include/configs/tegra114-common.h | 2 +- include/configs/tegra124-common.h | 2 +- include/configs/tegra20-common.h | 2 +- include/configs/tegra30-common.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 66cf7ae584..bde7ffce00 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -45,7 +45,7 @@ #define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ #ifndef CONFIG_ARM64 -#define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE +#define CFG_SYS_INIT_RAM_ADDR CFG_STACKBASE #define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN /* Defines for SPL */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 87ec1f5a99..ab4fa5504c 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -15,7 +15,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ +#define CFG_STACKBASE 0x83800000 /* 56MB */ /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 0485fea6cc..b413e25121 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -17,7 +17,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ +#define CFG_STACKBASE 0x83800000 /* 56MB */ /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 617bfb2197..a313ac2041 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -16,7 +16,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x03800000 /* 56MB */ +#define CFG_STACKBASE 0x03800000 /* 56MB */ /*----------------------------------------------------------------------- * Physical Memory Map diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 04fcf11ed8..c57d2d157e 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -16,7 +16,7 @@ /* * Miscellaneous configurable options */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ +#define CFG_STACKBASE 0x83800000 /* 56MB */ /* * Memory layout for where various images get loaded by boot scripts: From e02e5e5188b94a084e46fccf455026cef4c6d01a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:56 -0500 Subject: [PATCH 332/424] global: Migrate CONFIG_STD_DEVICES_SETTINGS to CFG Perform a simple rename of CONFIG_STD_DEVICES_SETTINGS to CFG_STD_DEVICES_SETTINGS Signed-off-by: Tom Rini --- include/configs/bayleybay.h | 2 +- include/configs/cherryhill.h | 2 +- include/configs/chromebook_coral.h | 4 ++-- include/configs/chromebook_samus.h | 4 ++-- include/configs/conga-qeval20-qa3-e3845.h | 2 +- include/configs/coreboot.h | 2 +- include/configs/cougarcanyon2.h | 2 +- include/configs/crownbay.h | 2 +- include/configs/dfi-bt700.h | 2 +- include/configs/efi-x86_app.h | 2 +- include/configs/efi-x86_payload.h | 2 +- include/configs/galileo.h | 2 +- include/configs/minnowmax.h | 2 +- include/configs/qemu-x86.h | 2 +- include/configs/slimbootloader.h | 4 ++-- include/configs/som-db5800-som-6867.h | 2 +- include/configs/theadorable-x86-common.h | 2 +- include/configs/x86-chromebook.h | 2 +- include/configs/x86-common.h | 2 +- 19 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index b347125f2f..b0df328cd8 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h index 726c43d35e..d6ce70a96a 100644 --- a/include/configs/cherryhill.h +++ b/include/configs/cherryhill.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index d14c1d445b..43fdc39441 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -13,8 +13,8 @@ #include #include -#undef CONFIG_STD_DEVICES_SETTINGS -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ +#undef CFG_STD_DEVICES_SETTINGS +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h index e29be3fda4..03a1033c57 100644 --- a/include/configs/chromebook_samus.h +++ b/include/configs/chromebook_samus.h @@ -15,8 +15,8 @@ #include #include -#undef CONFIG_STD_DEVICES_SETTINGS -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ +#undef CFG_STD_DEVICES_SETTINGS +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 6f43172526..60617e6fec 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index f73004386f..b4f49bf528 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -15,7 +15,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h index b64c7df1b2..31639e48da 100644 --- a/include/configs/cougarcanyon2.h +++ b/include/configs/cougarcanyon2.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vga\0" \ "stderr=serial,vga\0" diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index ff74deb3d4..387bb8800e 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index d10422b6c1..05389a435b 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -16,7 +16,7 @@ /* Use BayTrail internal HS UART which is memory-mapped */ #endif -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h index 17a7851402..843ed8b9d1 100644 --- a/include/configs/efi-x86_app.h +++ b/include/configs/efi-x86_app.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=vidconsole\0" \ "stderr=vidconsole\0" diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h index f50c2ce4dd..c72b067c36 100644 --- a/include/configs/efi-x86_payload.h +++ b/include/configs/efi-x86_payload.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 472f236b9b..0380ac287b 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -14,7 +14,7 @@ /* ns16550 UART is memory-mapped in Quark SoC */ -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 6c15c72efd..4a12c2f72c 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" \ "usb_pgood_delay=40\0" diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 5cd1388708..33263a46a4 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -22,7 +22,7 @@ #include #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h index 748a423b08..20b99a1021 100644 --- a/include/configs/slimbootloader.h +++ b/include/configs/slimbootloader.h @@ -8,7 +8,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS \ +#define CFG_STD_DEVICES_SETTINGS \ "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial\0" \ "stderr=serial\0" @@ -18,7 +18,7 @@ */ #undef CFG_EXTRA_ENV_SETTINGS #define CFG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS \ + CFG_STD_DEVICES_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=0x4000000\0" \ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index f097092136..b2e7aa1514 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -12,7 +12,7 @@ #include -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index 746995179f..b23b878307 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -11,7 +11,7 @@ #ifndef __THEADORABLE_X86_COMMON_H #define __THEADORABLE_X86_COMMON_H -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 9df3bfd527..41fb499ae4 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -12,7 +12,7 @@ #define VIDEO_IO_OFFSET 0 -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ +#define CFG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index f421ec5803..c1c5a09a35 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -44,7 +44,7 @@ #define CFG_EXTRA_ENV_SETTINGS \ DISTRO_BOOTENV \ - CONFIG_STD_DEVICES_SETTINGS \ + CFG_STD_DEVICES_SETTINGS \ SPLASH_SETTINGS \ "pciconfighost=1\0" \ "netdev=eth0\0" \ From d8964b3e1d7233a1b45679c57985575ec0056022 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:57 -0500 Subject: [PATCH 333/424] global: Migrate CONFIG_SYS_I2C_DIRECT_BUS to CFG Perform a simple rename of CONFIG_SYS_I2C_DIRECT_BUS to CFG_SYS_I2C_DIRECT_BUS Signed-off-by: Tom Rini --- README | 4 ++-- cmd/i2c.c | 4 ++-- drivers/i2c/i2c_core.c | 10 +++++----- include/i2c.h | 8 ++++---- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/README b/README index a9b225e45e..fe571f7ef0 100644 --- a/README +++ b/README @@ -843,7 +843,7 @@ The following options need to be configured: CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. - CONFIG_SYS_I2C_DIRECT_BUS + CFG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. if CFG_SYS_I2C_MAX_HOPS is not defined or == 0 you can omit this define. @@ -855,7 +855,7 @@ The following options need to be configured: CFG_SYS_I2C_BUSES hold a list of buses you want to use, only used if - CONFIG_SYS_I2C_DIRECT_BUS is not defined, for example + CFG_SYS_I2C_DIRECT_BUS is not defined, for example a board with CFG_SYS_I2C_MAX_HOPS = 1 and CFG_SYS_NUM_I2C_BUSES = 9: diff --git a/cmd/i2c.c b/cmd/i2c.c index f204061cf0..dd803ee227 100644 --- a/cmd/i2c.c +++ b/cmd/i2c.c @@ -1699,7 +1699,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, for (i = 0; i < CFG_SYS_NUM_I2C_BUSES; i++) { printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS int j; for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { @@ -1735,7 +1735,7 @@ static int do_i2c_show_bus(struct cmd_tbl *cmdtp, int flag, int argc, return -1; } printf("Bus %d:\t%s", i, I2C_ADAP_NR(i)->name); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS int j; for (j = 0; j < CFG_SYS_I2C_MAX_HOPS; j++) { if (i2c_bus[i].next_hop[j].chip == 0) diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 7f65db2320..fe0cd75d94 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -33,14 +33,14 @@ struct i2c_adapter *i2c_get_adapter(int index) return i2c_adap_p; } -#if !defined(CONFIG_SYS_I2C_DIRECT_BUS) +#if !defined(CFG_SYS_I2C_DIRECT_BUS) struct i2c_bus_hose i2c_bus[CFG_SYS_NUM_I2C_BUSES] = CFG_SYS_I2C_BUSES; #endif DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS /* * i2c_mux_set() * ------------- @@ -237,7 +237,7 @@ int i2c_set_bus_num(unsigned int bus) if ((bus == I2C_BUS) && (I2C_ADAP->init_done > 0)) return 0; -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS if (bus >= CFG_SYS_NUM_I2C_BUSES) return -1; #endif @@ -249,7 +249,7 @@ int i2c_set_bus_num(unsigned int bus) return -2; } -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS i2c_mux_disconnect_all(); #endif @@ -257,7 +257,7 @@ int i2c_set_bus_num(unsigned int bus) if (I2C_ADAP->init_done == 0) i2c_init_bus(bus, I2C_ADAP->speed, I2C_ADAP->slaveaddr); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS i2c_mux_set_all(); #endif return 0; diff --git a/include/i2c.h b/include/i2c.h index 3811b26c08..ef3820eaba 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -635,12 +635,12 @@ void i2c_early_init_f(void); #if !defined(CFG_SYS_I2C_MAX_HOPS) /* no muxes used bus = i2c adapters */ -#define CONFIG_SYS_I2C_DIRECT_BUS 1 +#define CFG_SYS_I2C_DIRECT_BUS 1 #define CFG_SYS_I2C_MAX_HOPS 0 #define CFG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c) #else /* we use i2c muxes */ -#undef CONFIG_SYS_I2C_DIRECT_BUS +#undef CFG_SYS_I2C_DIRECT_BUS #endif /* define the I2C bus number for RTC and DTT if not already done */ @@ -691,7 +691,7 @@ struct i2c_adapter { struct i2c_adapter *i2c_get_adapter(int index); -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS struct i2c_mux { int id; char name[16]; @@ -720,7 +720,7 @@ extern struct i2c_bus_hose i2c_bus[]; #define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus) #define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr) -#ifndef CONFIG_SYS_I2C_DIRECT_BUS +#ifndef CFG_SYS_I2C_DIRECT_BUS #define I2C_MUX_PCA9540_ID 1 #define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"} #define I2C_MUX_PCA9542_ID 2 From e660e972c44f53c8d90dfcb2d6b3564b325bec66 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:58 -0500 Subject: [PATCH 334/424] global: Migrate CONFIG_TEGRA_BOARD_STRING to CFG Perform a simple rename of CONFIG_TEGRA_BOARD_STRING to CFG_TEGRA_BOARD_STRING Signed-off-by: Tom Rini --- arch/arm/mach-tegra/board2.c | 2 +- include/configs/beaver.h | 2 +- include/configs/cardhu.h | 2 +- include/configs/cei-tk1-som.h | 2 +- include/configs/dalmore.h | 2 +- include/configs/harmony.h | 2 +- include/configs/jetson-tk1.h | 2 +- include/configs/medcom-wide.h | 2 +- include/configs/nyan-big.h | 2 +- include/configs/p2371-0000.h | 2 +- include/configs/p2371-2180.h | 2 +- include/configs/p2571.h | 2 +- include/configs/p2771-0000.h | 2 +- include/configs/p3450-0000.h | 2 +- include/configs/paz00.h | 2 +- include/configs/plutux.h | 2 +- include/configs/seaboard.h | 2 +- include/configs/tec-ng.h | 2 +- include/configs/tec.h | 2 +- include/configs/trimslice.h | 2 +- include/configs/venice2.h | 2 +- include/configs/ventana.h | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 54bbd8a776..c7a45f4ff8 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -89,7 +89,7 @@ int checkboard(void) { int board_id = tegra_board_id(); - printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); + printf("Board: %s", CFG_TEGRA_BOARD_STRING); if (board_id != -1) printf(", ID: %d\n", board_id); printf("\n"); diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 7e0e477960..e622b7127e 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -11,7 +11,7 @@ #include "tegra30-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 64d713a196..82729eb95c 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -11,7 +11,7 @@ #include "tegra30-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" #define BOARD_EXTRA_ENV_SETTINGS \ "board_name=cardhu-a04\0" \ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index e49eb60208..fbd38b77fe 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -16,7 +16,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" +#define CFG_TEGRA_BOARD_STRING "CEI tk1-som" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index c9009e3962..095554157f 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -11,7 +11,7 @@ #include "tegra114-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/harmony.h b/include/configs/harmony.h index a1a66bfb64..cae7acdb70 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -11,7 +11,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" /* Board-specific serial config */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index aa9e1d811a..9858f8ff2b 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -12,7 +12,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index efac0febdf..8dbe741278 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index e885526e62..c04d402deb 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -12,7 +12,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" +#define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index f426889e1c..a29d7135d0 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -12,7 +12,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" /* Board-specific serial config */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 24adf4e13f..0b077aba65 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -12,7 +12,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" /* Board-specific serial config */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 8a1e7d9b96..5155aa7b1d 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -12,7 +12,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2571" /* Board-specific serial config */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index 84cdd57196..e409cc3896 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -11,7 +11,7 @@ #include "tegra186-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" /* Environment in eMMC, at the end of 2nd "boot sector" */ diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index 078d35dde2..e60f42eaa7 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -11,7 +11,7 @@ #include "tegra210-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" +#define CFG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" /* Board-specific serial config */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 898167009f..950b321764 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -13,7 +13,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" +#define CFG_TEGRA_BOARD_STRING "Compal Paz00" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 1d8ac618c0..30bfce9f50 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index e5d672746b..8e98620422 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index ae879abe3f..5e49abb49f 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -10,7 +10,7 @@ #include "tegra30-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/tec.h b/include/configs/tec.h index e8a9df756d..05dd7c96f6 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -12,7 +12,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" +#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index b5bf991220..7d1ff2afd1 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -11,7 +11,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" +#define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 970893ca17..353b5ea67c 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -12,7 +12,7 @@ #include "tegra124-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/ventana.h b/include/configs/ventana.h index e7b7b911d9..1d9c60ca7c 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -11,7 +11,7 @@ #include "tegra20-common.h" /* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" +#define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" /* Board-specific serial config */ #define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE From 77cfb3d345651fa1cf78c8f30eca9d6d285f1e0b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:13:59 -0500 Subject: [PATCH 335/424] global: Migrate CONFIG_TESTPIN_MASK to CFG Perform a simple rename of CONFIG_TESTPIN_MASK to CFG_TESTPIN_MASK Signed-off-by: Tom Rini --- board/keymile/km83xx/km83xx.c | 2 +- include/configs/kmcoge5ne.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 88afc76bbb..73e3709bbb 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -217,7 +217,7 @@ int post_hotkeys_pressed(void) struct km_bec_fpga *base = (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); - testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; + testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); return testpin; } diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index e0f94aead7..d9c2f4fc4f 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -31,6 +31,6 @@ #define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END #define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ -#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ +#define CFG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ #endif /* CONFIG */ From 39d4e7b0b060c47879d1f2727853a3e7e38191b5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:00 -0500 Subject: [PATCH 336/424] global: Migrate CONFIG_TESTPIN_REG to CFG Perform a simple rename of CONFIG_TESTPIN_REG to CFG_TESTPIN_REG Signed-off-by: Tom Rini --- board/keymile/km83xx/km83xx.c | 2 +- include/configs/kmcoge5ne.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 73e3709bbb..9ec1dbc6f9 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -216,7 +216,7 @@ int post_hotkeys_pressed(void) int testpin = 0; struct km_bec_fpga *base = (struct km_bec_fpga *)CFG_SYS_KMBEC_FPGA_BASE; - int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); + int testpin_reg = in_8(&base->CFG_TESTPIN_REG); testpin = (testpin_reg & CFG_TESTPIN_MASK) != 0; debug("post_hotkeys_pressed: %d\n", !testpin); return testpin; diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index d9c2f4fc4f..d52f45ba91 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -30,7 +30,7 @@ #define CFG_POST (CFG_SYS_POST_MEMORY|CFG_SYS_POST_MEM_REGIONS) #define CFG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ #define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END -#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ +#define CFG_TESTPIN_REG gprt3 /* for kmcoge5ne */ #define CFG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ #endif /* CONFIG */ From e7cebff656527f624be796d7a80fcc7493e3e986 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:01 -0500 Subject: [PATCH 337/424] global: Migrate CONFIG_TSEC_TBICR_SETTINGS to CFG Perform a simple rename of CONFIG_TSEC_TBICR_SETTINGS to CFG_TSEC_TBICR_SETTINGS Signed-off-by: Tom Rini --- drivers/net/tsec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e583b9a178..6e90359759 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -29,14 +29,14 @@ ) /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */ -#ifndef CONFIG_TSEC_TBICR_SETTINGS -#define CONFIG_TSEC_TBICR_SETTINGS ( \ +#ifndef CFG_TSEC_TBICR_SETTINGS +#define CFG_TSEC_TBICR_SETTINGS ( \ TBICR_PHY_RESET \ | TBICR_ANEG_ENABLE \ | TBICR_FULL_DUPLEX \ | TBICR_SPEED1_SET \ ) -#endif /* CONFIG_TSEC_TBICR_SETTINGS */ +#endif /* CFG_TSEC_TBICR_SETTINGS */ /* Configure the TBI for SGMII operation */ static void tsec_configure_serdes(struct tsec_private *priv) @@ -50,7 +50,7 @@ static void tsec_configure_serdes(struct tsec_private *priv) tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), 0, TBI_TBICON, TBICON_CLK_SELECT); tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa), - 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS); + 0, TBI_CR, CFG_TSEC_TBICR_SETTINGS); } /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c From 805482d1874d1d06da89d71fcf0f9a46945f7836 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:02 -0500 Subject: [PATCH 338/424] global: Migrate CONFIG_USART_BASE to CFG Perform a simple rename of CONFIG_USART_BASE to CFG_USART_BASE Signed-off-by: Tom Rini --- drivers/serial/atmel_usart.c | 10 +++++----- include/configs/corvus.h | 2 +- include/configs/sam9x60_curiosity.h | 2 +- include/configs/sam9x60ek.h | 2 +- include/configs/smartweb.h | 2 +- include/configs/taurus.h | 2 +- include/configs/vinco.h | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 90ccdf6b29..56655427b0 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -72,13 +72,13 @@ static void atmel_serial_activate(atmel_usart3_t *usart) static void atmel_serial_setbrg(void) { - atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE, + atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE, CONFIG_USART_ID, gd->baudrate); } static int atmel_serial_init(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; atmel_serial_init_internal(usart); serial_setbrg(); @@ -89,7 +89,7 @@ static int atmel_serial_init(void) static void atmel_serial_putc(char c) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; if (c == '\n') serial_putc('\r'); @@ -100,7 +100,7 @@ static void atmel_serial_putc(char c) static int atmel_serial_getc(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; while (!(readl(&usart->csr) & USART3_BIT(RXRDY))) schedule(); @@ -109,7 +109,7 @@ static int atmel_serial_getc(void) static int atmel_serial_tstc(void) { - atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE; + atmel_usart3_t *usart = (atmel_usart3_t *)CFG_USART_BASE; return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0; } diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 8a61086ecc..c9eb75d930 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -28,7 +28,7 @@ #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ /* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* SDRAM */ diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index f44ce909b9..204020d5ee 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -13,7 +13,7 @@ #define CFG_SYS_AT91_SLOW_CLOCK 32768 #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ /* SDRAM */ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 27b39ebf41..800b98ff98 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -14,7 +14,7 @@ #define CFG_SYS_AT91_SLOW_CLOCK 32768 #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID 0 /* ignored in arm */ /* diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 762f61470b..f9a5aa9e32 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -61,7 +61,7 @@ #define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13 /* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* DFU class support */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 855218a890..88870d6fdf 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -34,7 +34,7 @@ /* Misc CPU related */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS /* diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 0698ae1d1c..3b4032301f 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -17,7 +17,7 @@ /* The value in the common file is too far away for the VInCo platform */ /* serial console */ -#define CONFIG_USART_BASE 0xfc00c000 +#define CFG_USART_BASE 0xfc00c000 #define CONFIG_USART_ID 30 /* Timer */ From 61693acbce16dd674de9d6193fbfaffc739f4829 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:03 -0500 Subject: [PATCH 339/424] global: Migrate CONFIG_USART_ID to CFG Perform a simple rename of CONFIG_USART_ID to CFG_USART_ID Signed-off-by: Tom Rini --- drivers/serial/atmel_usart.c | 2 +- include/configs/corvus.h | 2 +- include/configs/sam9x60_curiosity.h | 2 +- include/configs/sam9x60ek.h | 2 +- include/configs/smartweb.h | 2 +- include/configs/taurus.h | 2 +- include/configs/vinco.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 56655427b0..9d97bc8654 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -73,7 +73,7 @@ static void atmel_serial_activate(atmel_usart3_t *usart) static void atmel_serial_setbrg(void) { atmel_serial_setbrg_internal((atmel_usart3_t *)CFG_USART_BASE, - CONFIG_USART_ID, gd->baudrate); + CFG_USART_ID, gd->baudrate); } static int atmel_serial_init(void) diff --git a/include/configs/corvus.h b/include/configs/corvus.h index c9eb75d930..f2675e0ec8 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -29,7 +29,7 @@ /* serial console */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS +#define CFG_USART_ID ATMEL_ID_SYS /* SDRAM */ #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 diff --git a/include/configs/sam9x60_curiosity.h b/include/configs/sam9x60_curiosity.h index 204020d5ee..e79f80f17f 100644 --- a/include/configs/sam9x60_curiosity.h +++ b/include/configs/sam9x60_curiosity.h @@ -14,7 +14,7 @@ #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0 /* ignored in arm */ +#define CFG_USART_ID 0 /* ignored in arm */ /* SDRAM */ #define CFG_SYS_SDRAM_BASE 0x20000000 diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index 800b98ff98..2c761821ef 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -15,7 +15,7 @@ #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0 /* ignored in arm */ +#define CFG_USART_ID 0 /* ignored in arm */ /* * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index f9a5aa9e32..75a1670e33 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -62,7 +62,7 @@ /* serial console */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS +#define CFG_USART_ID ATMEL_ID_SYS /* DFU class support */ #define DFU_MANIFEST_POLL_TIMEOUT 25000 diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 88870d6fdf..174b848e25 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -35,7 +35,7 @@ /* Misc CPU related */ #define CFG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS +#define CFG_USART_ID ATMEL_ID_SYS /* * SDRAM: 1 bank, min 32, max 128 MB diff --git a/include/configs/vinco.h b/include/configs/vinco.h index 3b4032301f..68c56df543 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -18,7 +18,7 @@ /* serial console */ #define CFG_USART_BASE 0xfc00c000 -#define CONFIG_USART_ID 30 +#define CFG_USART_ID 30 /* Timer */ #define CFG_SYS_TIMER_COUNTER 0xfc06863c From 1d0eaf2f32353424063686478a34a56dfa251416 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:04 -0500 Subject: [PATCH 340/424] global: Migrate CONFIG_USB_ISP1301_I2C_ADDR to CFG Perform a simple rename of CONFIG_USB_ISP1301_I2C_ADDR to CFG_USB_ISP1301_I2C_ADDR Signed-off-by: Tom Rini --- drivers/usb/host/ohci-lpc32xx.c | 2 +- include/configs/devkit3250.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/ohci-lpc32xx.c b/drivers/usb/host/ohci-lpc32xx.c index 3be0b311a3..a04b2961b9 100644 --- a/drivers/usb/host/ohci-lpc32xx.c +++ b/drivers/usb/host/ohci-lpc32xx.c @@ -69,7 +69,7 @@ struct otg_regs { #define OTG1_DM_PULLDOWN (1 << 3) #define OTG1_VBUS_DRV (1 << 5) -#define ISP1301_I2C_ADDR CONFIG_USB_ISP1301_I2C_ADDR +#define ISP1301_I2C_ADDR CFG_USB_ISP1301_I2C_ADDR #define ISP1301_I2C_MODE_CONTROL_1_SET 0x04 #define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 9cfee381d4..d85aeaafe5 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -53,7 +53,7 @@ /* * USB */ -#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d +#define CFG_USB_ISP1301_I2C_ADDR 0x2d /* * U-Boot General Configurations From 438654c87c0ec20019c2489ecce02919005b91bc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:05 -0500 Subject: [PATCH 341/424] global: Migrate CONFIG_VSC7385_IMAGE et al to CFG Perform simple renames of: CONFIG_VSC7385_IMAGE to CFG_VSC7385_IMAGE CONFIG_VSC7385_IMAGE_SIZE to CFG_VSC7385_IMAGE_SIZE Signed-off-by: Tom Rini --- board/freescale/mpc837xerdb/mpc837xerdb.c | 6 +++--- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- include/configs/MPC837XERDB.h | 4 ++-- include/configs/p1_p2_rdb_pc.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index 8b1bfe0a9f..97884a3979 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -206,9 +206,9 @@ int misc_init_r(void) { int rc = 0; -#ifdef CONFIG_VSC7385_IMAGE - if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, - CONFIG_VSC7385_IMAGE_SIZE)) { +#ifdef CFG_VSC7385_IMAGE + if (vsc7385_upload_firmware((void *) CFG_VSC7385_IMAGE, + CFG_VSC7385_IMAGE_SIZE)) { puts("Failure uploading VSC7385 microcode.\n"); rc = 1; } diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4d7d042eaf..602b7f0156 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -355,7 +355,7 @@ int board_early_init_r(void) vscfw_addr = hextoul(tmp, NULL); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *)vscfw_addr, - CONFIG_VSC7385_IMAGE_SIZE)) + CFG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else { puts("No address specified for VSC7385 microcode.\n"); diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 07c989d989..70b1c39924 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -42,8 +42,8 @@ #ifdef CONFIG_VSC7385_ENET /* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#define CFG_VSC7385_IMAGE 0xFE7FE000 +#define CFG_VSC7385_IMAGE_SIZE 8192 #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index be76801982..f5bd091344 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -270,7 +270,7 @@ #endif /* The size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE_SIZE 8192 +#define CFG_VSC7385_IMAGE_SIZE 8192 #endif #ifndef __VSCFW_ADDR From bb34410509205e70ab7c9830f9c17277e8dd54ad Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:06 -0500 Subject: [PATCH 342/424] global: Migrate CONFIG_WATCHDOG_PRESC et al to CFG Perform simple renames of: CONFIG_WATCHDOG_PRESC to CFG_WATCHDOG_PRESC CONFIG_WATCHDOG_RC to CFG_WATCHDOG_RC Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- include/configs/kmcent2.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 0abcc01b85..e8a3e82765 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -357,7 +357,7 @@ void init_85xx_watchdog(void) { mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | - TCR_WP(CONFIG_WATCHDOG_PRESC) | TCR_WRC(CONFIG_WATCHDOG_RC)); + TCR_WP(CFG_WATCHDOG_PRESC) | TCR_WRC(CFG_WATCHDOG_RC)); } void diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 58dff495ac..60fea59dee 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -364,8 +364,8 @@ int get_scl(void); /* * Hardware Watchdog */ -#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ -#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ +#define CFG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) ~10min */ +#define CFG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ /* * For booting Linux, the board info and command line data From fa2fd534b5d80d59b9043f2d8291fcb1c6c75a5b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:07 -0500 Subject: [PATCH 343/424] global: Migrate CONFIG_X86_MRC_ADDR to CFG Perform a simple rename of CONFIG_X86_MRC_ADDR to CFG_X86_MRC_ADDR Signed-off-by: Tom Rini --- arch/x86/cpu/intel_common/mrc.c | 2 +- arch/x86/dts/u-boot.dtsi | 2 +- include/configs/x86-chromebook.h | 2 +- tools/binman/binman.rst | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c index a4918fbad6..69405d740b 100644 --- a/arch/x86/cpu/intel_common/mrc.c +++ b/arch/x86/cpu/intel_common/mrc.c @@ -200,7 +200,7 @@ static int sdram_initialise(struct udevice *dev, struct udevice *me_dev, debug("PEI data at %p:\n", pei_data); - data = (char *)CONFIG_X86_MRC_ADDR; + data = (char *)CFG_X86_MRC_ADDR; if (data) { int rv; ulong start; diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 24e692f988..454efc1761 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -86,7 +86,7 @@ #endif #ifdef CONFIG_HAVE_MRC intel-mrc { - offset = ; + offset = ; }; #endif #ifdef CONFIG_FSP_VERSION1 diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 41fb499ae4..059e3a0d8a 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -6,7 +6,7 @@ #ifndef _X86_CHROMEBOOK_H #define _X86_CHROMEBOOK_H -#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CFG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst index e7b231e071..69e4b00239 100644 --- a/tools/binman/binman.rst +++ b/tools/binman/binman.rst @@ -298,7 +298,7 @@ C preprocessor:: #ifdef CONFIG_HAVE_MRC intel-mrc { - offset = ; + offset = ; }; #endif From d4143373f161984426f0bd1fda1cbced21e57272 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:08 -0500 Subject: [PATCH 344/424] global: Migrate CONFIG_X86_REFCODE_ADDR to CFG Perform a simple rename of CONFIG_X86_REFCODE_ADDR to CFG_X86_REFCODE_ADDR Signed-off-by: Tom Rini --- arch/x86/cpu/broadwell/refcode.c | 2 +- arch/x86/dts/u-boot.dtsi | 2 +- include/configs/x86-chromebook.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 94c2e05346..3b7ec2b74e 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -78,7 +78,7 @@ static int cpu_run_reference_code(void) int ret, dummy; int size; - hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR; + hdr = (struct rmodule_header *)CFG_X86_REFCODE_ADDR; debug("Extracting code from rmodule at %p\n", hdr); if (hdr->magic != RMODULE_MAGIC) { debug("Invalid rmodule magic\n"); diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 454efc1761..e0de331809 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -149,7 +149,7 @@ #endif #ifdef CONFIG_HAVE_REFCODE intel-refcode { - offset = ; + offset = ; }; #endif #ifdef CONFIG_TPL diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 059e3a0d8a..8bbbe51ecb 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -7,7 +7,7 @@ #define _X86_CHROMEBOOK_H #define CFG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_X86_REFCODE_ADDR 0xffea0000 +#define CFG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 #define VIDEO_IO_OFFSET 0 From 92a5c899987301f6b53ef37e46ea96ce9abb752e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:09 -0500 Subject: [PATCH 345/424] global: Migrate CONFIG_X86_REFCODE_RUN_ADDR to CFG Perform a simple rename of CONFIG_X86_REFCODE_RUN_ADDR to CFG_X86_REFCODE_RUN_ADDR Signed-off-by: Tom Rini --- arch/x86/cpu/broadwell/refcode.c | 4 ++-- include/configs/x86-chromebook.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 3b7ec2b74e..df2df7972e 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -99,7 +99,7 @@ static int cpu_run_reference_code(void) pei_data->saved_data = (void *)&dummy; src = (char *)hdr + hdr->payload_begin_offset; - dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR; + dest = (char *)CFG_X86_REFCODE_RUN_ADDR; size = hdr->payload_end_offset - hdr->payload_begin_offset; debug("Copying refcode from %p to %p, size %x\n", src, dest, size); @@ -112,7 +112,7 @@ static int cpu_run_reference_code(void) func = (asmlinkage int (*)(void *))dest; debug("Running reference code at %p\n", func); #ifdef DEBUG - print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0); + print_buffer(CFG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0); #endif ret = func(pei_data); if (ret != 0) { diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 8bbbe51ecb..98abb00927 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -8,7 +8,7 @@ #define CFG_X86_MRC_ADDR 0xfffa0000 #define CFG_X86_REFCODE_ADDR 0xffea0000 -#define CONFIG_X86_REFCODE_RUN_ADDR 0 +#define CFG_X86_REFCODE_RUN_ADDR 0 #define VIDEO_IO_OFFSET 0 From e1d6c16d80cbe510f524d68a1879ed0fab26a80b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:10 -0500 Subject: [PATCH 346/424] librem5: Rename CONFIG_POWER_BD71837 symbols Rename the CONFIG_POWER_BD71837_I2C_* symbols to not have the CONFIG prefix and be local to the file they are used in. Signed-off-by: Tom Rini --- board/purism/librem5/spl.c | 8 +++++--- include/configs/librem5.h | 4 ---- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index 1bfd948806..1a203b4599 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -322,6 +322,8 @@ void disable_charger_bq25895(void) } #define I2C_PMIC 0 +#define POWER_BD71837_I2C_BUS 0 +#define POWER_BD71837_I2C_ADDR 0x4B int power_bd71837_init(unsigned char bus) { @@ -336,7 +338,7 @@ int power_bd71837_init(unsigned char bus) p->name = name; p->interface = I2C_PMIC; p->number_of_regs = BD718XX_MAX_REGISTER; - p->hw.i2c.addr = CONFIG_POWER_BD71837_I2C_ADDR; + p->hw.i2c.addr = POWER_BD71837_I2C_ADDR; p->hw.i2c.tx_num = 1; p->bus = bus; @@ -357,10 +359,10 @@ int power_init_board(void) /* * Init PMIC */ - rv = power_bd71837_init(CONFIG_POWER_BD71837_I2C_BUS); + rv = power_bd71837_init(POWER_BD71837_I2C_BUS); if (rv) { log_err("%s: power_bd71837_init(%d) error %d\n", __func__, - CONFIG_POWER_BD71837_I2C_BUS, rv); + POWER_BD71837_I2C_BUS, rv); goto out; } diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 9e4d373e56..e17190ce9c 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -19,10 +19,6 @@ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ -#define CONFIG_POWER_BD71837 -#define CONFIG_POWER_BD71837_I2C_BUS 0 -#define CONFIG_POWER_BD71837_I2C_ADDR 0x4B - #endif /* CONFIG_SPL_BUILD*/ #define CFG_SYS_FSL_USDHC_NUM 2 From f5dd0c5e19cf587c744e234e8a7e47f63642e113 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:11 -0500 Subject: [PATCH 347/424] configs: Remove unused or redundant CONFIG symbols A number of CONFIG symbols have crept in that are never referenced in code, so drop them here. Further, we have two symbols being enabled in headers while already enabled correctly in Kconfig, so these lines can also be removed. Signed-off-by: Tom Rini --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 - arch/arm/mach-mvebu/include/mach/config.h | 3 --- include/configs/cgtqmx8.h | 1 - include/configs/imx8mp_rsb3720.h | 9 --------- include/configs/imx8mq_cm.h | 1 - include/configs/imx8mq_evk.h | 1 - include/configs/imx8mq_phanbell.h | 1 - include/configs/imx8qm_mek.h | 1 - include/configs/imx8qxp_mek.h | 1 - include/configs/kontron_pitx_imx8m.h | 1 - include/configs/librem5.h | 6 ------ include/configs/pico-imx8mq.h | 1 - 13 files changed, 1 insertion(+), 27 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2862257e1f..9656c52e95 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -29,6 +29,7 @@ config ARCH_LS1028A select ESBC_HDR_LS if CHAIN_OF_TRUST select FSL_LAYERSCAPE select FSL_LSCH3 + select FSL_TZASC_400 select GICV3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 12758c8dd1..516c9eab04 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -160,7 +160,6 @@ #elif defined(CONFIG_ARCH_LS1028A) #define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_FSL_TZASC_400 /* TZ Protection Controller Definitions */ #define TZPC_BASE 0x02200000 diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 96a08104ff..6102747548 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -27,7 +27,4 @@ #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE -/* Needed for SPI NOR booting in SPL */ -#define CONFIG_DM_SEQ_ALIAS 1 - #endif /* __MVEBU_CONFIG_H */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 91454df197..98d4d8cf4b 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -12,7 +12,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 495ca313db..d4ab6a6207 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -28,12 +28,6 @@ * GD_FLG_FULL_MALLOC_INIT \ * set \ */ - - -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_SPL_NAND_MXS -#endif - #endif /* ENET Config */ @@ -158,9 +152,6 @@ #define FSL_FSPI_FLASH_NUM 1 #define FSPI0_BASE_ADDR 0x30bb0000 #define FSPI0_AMBA_BASE 0x0 -#define CONFIG_FSPI_QUAD_SUPPORT - -#define CONFIG_SYS_FSL_FSPI_AHB #endif #ifdef CONFIG_NAND_MXS diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 828bd67237..7cf482d6de 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -11,7 +11,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index d2de2900c0..d2e1649400 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -12,7 +12,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index bfde15e624..b66fc18fa5 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -11,7 +11,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index a25efbb16b..4d5abe2d07 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -11,7 +11,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 4f55ae4940..9399950994 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -11,7 +11,6 @@ #include #ifdef CONFIG_SPL_BUILD -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CFG_MALLOC_F_ADDR 0x00120000 #endif diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index e3a021c987..5cf6b5a6dd 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -13,7 +13,6 @@ 0x40, 0xd4, 0x5c, 0xca, 0x13, 0x99) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/librem5.h b/include/configs/librem5.h index e17190ce9c..ce0a340ba2 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -15,12 +15,6 @@ #include #include -#ifdef CONFIG_SPL_BUILD - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ - -#endif /* CONFIG_SPL_BUILD*/ - #define CFG_SYS_FSL_USDHC_NUM 2 #define CONSOLE_ON_UART1 diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 4b602ea030..be31f8a23c 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -11,7 +11,6 @@ #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CFG_MALLOC_F_ADDR 0x182000 From e95bcfb56c6599ba6d00a54fc2f857b6680481c4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:12 -0500 Subject: [PATCH 348/424] bcmcygnus: Convert CONFIG_IPROC to Kconfig Select this symbol as needed. Signed-off-by: Tom Rini --- arch/arm/Kconfig | 4 ++++ arch/arm/include/asm/iproc-common/configs.h | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6e191e41d5..bbf1d5227b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -553,6 +553,9 @@ config ARM64_SUPPORT_AARCH32 help This ARM64 system supports AArch32 execution state. +config IPROC + bool + config S5P def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX @@ -658,6 +661,7 @@ config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7A select GPIO_EXTRA_HEADER + select IPROC imply BCM_SF2_ETH imply BCM_SF2_ETH_GMAC imply CMD_HASH diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index c63c27dac7..ce831bc13a 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -8,9 +8,6 @@ #include -/* Architecture, CPU, chip, etc */ -#define CONFIG_IPROC - /* Memory Info */ #define CFG_SYS_SDRAM_BASE 0x61000000 From 0478dac62a9add8c73981a900ceaa6da732ae2bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:13 -0500 Subject: [PATCH 349/424] kbuild: Remove uncmd_spl logic At this point in the conversion there should be no need to have logic to disable some symbol during the SPL build as all symbols should have an SPL counterpart. The main real changes done here are that we now must make proper use of CONFIG_IS_ENABLED(DM_SERIAL) rather than many of the odd tricks we developed prior to CONFIG_IS_ENABLED() being available. Signed-off-by: Tom Rini --- board/freescale/common/i2c_common.c | 2 +- board/freescale/common/i2c_common.h | 2 +- drivers/misc/gsc.c | 2 +- drivers/serial/Makefile | 17 +---------------- drivers/serial/atmel_usart.c | 8 +++----- drivers/serial/serial-uclass.c | 6 +++--- drivers/serial/serial_mtk.c | 3 +-- drivers/serial/serial_pl01x.c | 11 +++-------- drivers/serial/serial_pl01x_internal.h | 2 +- include/config_uncmd_spl.h | 21 --------------------- include/configs/kmcent2.h | 2 +- include/configs/mv-common.h | 2 +- include/configs/sunxi-common.h | 2 +- include/configs/ti_omap4_common.h | 2 +- include/configs/x530.h | 2 +- include/ns16550.h | 10 +++++----- scripts/Makefile.autoconf | 1 - scripts/Makefile.build | 1 - scripts/Makefile.uncmd_spl | 14 -------------- 19 files changed, 25 insertions(+), 85 deletions(-) delete mode 100644 include/config_uncmd_spl.h delete mode 100644 scripts/Makefile.uncmd_spl diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c index 0f09ed7d34..119ed3c617 100644 --- a/board/freescale/common/i2c_common.c +++ b/board/freescale/common/i2c_common.c @@ -9,7 +9,7 @@ #include #include "i2c_common.h" -#ifdef CONFIG_DM_I2C +#if CONFIG_IS_ENABLED(DM_I2C) /* If DM is in use, retrieve the chip for the specified bus number */ int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) diff --git a/board/freescale/common/i2c_common.h b/board/freescale/common/i2c_common.h index 840ad66183..77a7b6aedd 100644 --- a/board/freescale/common/i2c_common.h +++ b/board/freescale/common/i2c_common.h @@ -9,7 +9,7 @@ #define __NXP_I2C_COMMON_H__ /* Common functionality shared by the I2C drivers for VID and the mux. */ -#ifdef CONFIG_DM_I2C +#if CONFIG_IS_ENABLED(DM_I2C) #define DEVICE_HANDLE_T struct udevice * #define I2C_READ(dev, register, data, length) \ diff --git a/drivers/misc/gsc.c b/drivers/misc/gsc.c index ec24ca807b..65c9c2c6ce 100644 --- a/drivers/misc/gsc.c +++ b/drivers/misc/gsc.c @@ -77,7 +77,7 @@ enum { GSC_SC_RST_CAUSE_MAX = 10, }; -#if (IS_ENABLED(CONFIG_DM_I2C)) +#if CONFIG_IS_ENABLED(DM_I2C) struct gsc_priv { int gscver; diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 33fa568221..37d3f82dbd 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -3,30 +3,15 @@ # (C) Copyright 2006-2009 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -ifdef CONFIG_SPL_BUILD - -ifeq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)DM_SERIAL),yy) +ifeq ($(CONFIG_$(SPL_TPL_)DM_SERIAL),y) obj-y += serial-uclass.o else obj-y += serial.o endif -else - -ifdef CONFIG_DM_SERIAL -obj-y += serial-uclass.o -else -obj-y += serial.o -endif - -endif - -ifdef CONFIG_DM_SERIAL obj-$(CONFIG_PL01X_SERIAL) += serial_pl01x.o -else obj-$(CONFIG_PL011_SERIAL) += serial_pl01x.o obj-$(CONFIG_$(SPL_)SYS_NS16550_SERIAL) += serial_ns16550.o -endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index 9d97bc8654..9853f49c94 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -18,7 +18,7 @@ #include #include -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) #include #endif #include @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id, int baudrate) { @@ -133,9 +133,7 @@ __weak struct serial_device *default_serial_console(void) { return &atmel_serial_drv; } -#endif - -#ifdef CONFIG_DM_SERIAL +#else enum serial_clk_type { CLK_TYPE_NORMAL = 0, CLK_TYPE_DBGU, diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index c02106747a..7240d763d1 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -407,7 +407,7 @@ void serial_stdio_init(void) { } -#if defined(CONFIG_DM_STDIO) +#if CONFIG_IS_ENABLED(DM_STDIO) #if CONFIG_IS_ENABLED(SERIAL_PRESENT) static void serial_stub_putc(struct stdio_dev *sdev, const char ch) @@ -505,7 +505,7 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); static int serial_post_probe(struct udevice *dev) { struct dm_serial_ops *ops = serial_get_ops(dev); -#ifdef CONFIG_DM_STDIO +#if CONFIG_IS_ENABLED(DM_STDIO) struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); struct stdio_dev sdev; #endif @@ -540,7 +540,7 @@ static int serial_post_probe(struct udevice *dev) return ret; } -#ifdef CONFIG_DM_STDIO +#if CONFIG_IS_ENABLED(DM_STDIO) if (!(gd->flags & GD_FLG_RELOC)) return 0; memset(&sdev, '\0', sizeof(sdev)); diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c index 6fb4cb65c2..ded7346a13 100644 --- a/drivers/serial/serial_mtk.c +++ b/drivers/serial/serial_mtk.c @@ -173,8 +173,7 @@ static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input) return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1; } -#if defined(CONFIG_DM_SERIAL) && \ - (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM)) +#if CONFIG_IS_ENABLED(DM_SERIAL) static int mtk_serial_setbrg(struct udevice *dev, int baudrate) { struct mtk_serial_priv *priv = dev_get_priv(dev); diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 7449e9b904..f5468353e1 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DM_SERIAL - +#if !CONFIG_IS_ENABLED(DM_SERIAL) static volatile unsigned char *const port[] = CFG_PL01x_PORTS; static enum pl01x_type pl01x_type __section(".data"); static struct pl01x_regs *base_regs __section(".data"); @@ -186,7 +185,7 @@ static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, return 0; } -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) static void pl01x_serial_init_baud(int baudrate) { int clock = 0; @@ -273,11 +272,7 @@ __weak struct serial_device *default_serial_console(void) { return &pl01x_serial_drv; } - -#endif /* nCONFIG_DM_SERIAL */ - -#ifdef CONFIG_DM_SERIAL - +#else int pl01x_serial_setbrg(struct udevice *dev, int baudrate) { struct pl01x_serial_plat *plat = dev_get_plat(dev); diff --git a/drivers/serial/serial_pl01x_internal.h b/drivers/serial/serial_pl01x_internal.h index dfd95a0b77..71c52bb531 100644 --- a/drivers/serial/serial_pl01x_internal.h +++ b/drivers/serial/serial_pl01x_internal.h @@ -38,7 +38,7 @@ struct pl01x_regs { u32 pl011_cr; /* 0x30 Control register */ }; -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) int pl01x_serial_of_to_plat(struct udevice *dev); int pl01x_serial_probe(struct udevice *dev); diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h deleted file mode 100644 index a59b9bbafb..0000000000 --- a/include/config_uncmd_spl.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Ilya Yanok, ilya.yanok@gmail.com - */ - -#ifndef __CONFIG_UNCMD_SPL_H__ -#define __CONFIG_UNCMD_SPL_H__ - -#ifdef CONFIG_SPL_BUILD -/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */ - -#ifndef CONFIG_SPL_DM -#undef CONFIG_DM_SERIAL -#undef CONFIG_DM_I2C -#endif - -#undef CONFIG_DM_STDIO - -#endif /* CONFIG_SPL_BUILD */ -#endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 60fea59dee..e7ae18ec5f 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -314,7 +314,7 @@ * shorted - index 1 * Retain non-DM serial port for debug purposes. */ -#if !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR + 0x11C500) #endif diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index fa275d61d1..3dfcb138b4 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -33,7 +33,7 @@ * NS16550 Configuration */ #define CFG_SYS_NS16550_CLK CFG_SYS_TCLK -#if !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index eae107fe5e..8032abe769 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -23,7 +23,7 @@ #else #define CFG_SYS_NS16550_CLK 24000000 #endif -#ifndef CONFIG_DM_SERIAL +#if !CONFIG_IS_ENABLED(DM_SERIAL) # define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 49f4263e16..9e312ac16d 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -28,7 +28,7 @@ * Hardware drivers */ #define CFG_SYS_NS16550_CLK 48000000 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_COM3 UART3_BASE #endif diff --git a/include/configs/x530.h b/include/configs/x530.h index fddf00d3d1..e1678e79e4 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -14,7 +14,7 @@ * NS16550 Configuration */ #define CFG_SYS_NS16550_CLK CFG_SYS_TCLK -#if !defined(CONFIG_DM_SERIAL) +#if !CONFIG_IS_ENABLED(DM_SERIAL) #define CFG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE #endif diff --git a/include/ns16550.h b/include/ns16550.h index 0ee5c4d6de..f45fc8cecc 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) +#if CONFIG_IS_ENABLED(DM_SERIAL) && !defined(CONFIG_SYS_NS16550_REG_SIZE) /* * For driver model we always use one byte per register, and sort out the * differences in the driver @@ -37,10 +37,10 @@ #ifdef CONFIG_NS16550_DYNAMIC #define UART_REG(x) unsigned char x #else -#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) -#error "Please define NS16550 registers size." -#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) +#if defined(CONFIG_SYS_NS16550_MEM32) && !CONFIG_IS_ENABLED(DM_SERIAL) #define UART_REG(x) u32 x +#elif !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) +#error "Please define NS16550 registers size." #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) #define UART_REG(x) \ unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ @@ -113,7 +113,7 @@ struct ns16550 { UART_REG(scr); /* 10*/ UART_REG(ssr); /* 11*/ #endif -#ifdef CONFIG_DM_SERIAL +#if CONFIG_IS_ENABLED(DM_SERIAL) struct ns16550_plat *plat; #endif }; diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index f5f5e4a4d5..0ade91642a 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -113,7 +113,6 @@ vpl/include/autoconf.mk: vpl/u-boot.cfg define filechk_config_h (echo "/* Automatically generated - do not edit */"; \ echo \#define CFG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ - echo \#include \; \ echo \#include \; \ echo \#include \; \ echo \#include \; \ diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 3b8c9d8c31..97dd4a64f6 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -48,7 +48,6 @@ subdir-ccflags-y := # Modified for U-Boot -include include/config/auto.conf -include $(prefix)/include/autoconf.mk -include scripts/Makefile.uncmd_spl include scripts/Kbuild.include diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl deleted file mode 100644 index 6ea097d36d..0000000000 --- a/scripts/Makefile.uncmd_spl +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Makefile version of include/config_uncmd_spl.h -# TODO: Invent a better way - -ifdef CONFIG_SPL_BUILD - -ifndef CONFIG_SPL_DM -CONFIG_DM_SERIAL= -CONFIG_DM_I2C= -CONFIG_DM_SPI= -CONFIG_DM_SPI_FLASH= -endif - -endif From 2a06da08e7897deb08c204df1c2f7853c4e61806 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:14 -0500 Subject: [PATCH 350/424] checkpatch.pl: Update CONFIG logic in U-Boot section Now that all CONFIG symbols are in Kconfig, checkpatch.pl should check for and error on any case of define/undef CONFIG_*. Signed-off-by: Tom Rini --- scripts/checkpatch.pl | 8 ++++---- tools/patman/test_checkpatch.py | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index fe13e265a3..ccfcbb3e12 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -2630,10 +2630,10 @@ sub u_boot_line { "strl$1 is preferred over strn$1 because it always produces a nul-terminated string\n" . $herecurr); } - # use defconfig to manage CONFIG_CMD options - if ($line =~ /\+\s*#\s*(define|undef)\s+(CONFIG_CMD\w*)\b/) { - ERROR("DEFINE_CONFIG_CMD", - "All commands are managed by Kconfig\n" . $herecurr); + # use Kconfig for all CONFIG symbols + if ($line =~ /\+\s*#\s*(define|undef)\s+(CONFIG_\w*)\b/) { + ERROR("DEFINE_CONFIG_SYM", + "All CONFIG symbols are managed by Kconfig\n" . $herecurr); } # Don't put common.h and dm.h in header files diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py index 8960cd505f..4c2ab6e590 100644 --- a/tools/patman/test_checkpatch.py +++ b/tools/patman/test_checkpatch.py @@ -396,7 +396,7 @@ index 0000000..2234c87 """Test for enabling/disabling commands using preprocesor""" pm = PatchMaker() pm.add_line('common/main.c', '#undef CONFIG_CMD_WHICH') - self.check_single_message(pm, 'DEFINE_CONFIG_CMD', 'error') + self.check_single_message(pm, 'DEFINE_CONFIG_SYM', 'error') def test_barred_include_in_hdr(self): """Test for using a barred include in a header file""" From bb9b9c1e207744fc2ea5163688e9379530a3057b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:15 -0500 Subject: [PATCH 351/424] CI: Replace unmigrated symbol test with non-Kconfig introduction test Now that all symbols have been migrated to Kconfig, or are part of the CFG namespace we do not need a complex check for unmigrated CONFIG symbols. Any instance of #define (or #undef) or a CONFIG value is wrong, so cause CI to fail. This test is not as strict as possible yet as we have more symbols that were not previously caught to deal with. Signed-off-by: Tom Rini --- .azure-pipelines.yml | 31 ++++++------------------------- .gitlab-ci.yml | 29 ++++++----------------------- 2 files changed, 12 insertions(+), 48 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d31b183ba6..8a63b1f434 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -53,37 +53,18 @@ stages: -j$(sysctl -n hw.logicalcpu) displayName: 'Perform tools-only build' - - job: check_for_migrated_symbols_in_board_header - displayName: 'Check for migrated symbols in board header' + - job: check_for_new_CONFIG_symbols_outside_Kconfig + displayName: 'Check for new CONFIG symbols outside Kconfig' pool: vmImage: $(ubuntu_vm) container: image: $(ci_runner_image) options: $(container_option) steps: - - script: | - KSYMLST=`mktemp` - KUSEDLST=`mktemp` - RET=0 - cat `find . -name "Kconfig*"` | \ - sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \ - -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \ - | sort -u > $KSYMLST - for CFG in `find include/configs -name "*.h"`; do - (grep '#define[[:blank:]]CONFIG_' $CFG | \ - sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; \ - grep '#undef[[:blank:]]CONFIG_' $CFG | \ - sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | \ - sort -u > ${KUSEDLST} || true - NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | \ - cut -d , -f 3` - if [[ $NUM -ne 0 ]]; then - echo "Unmigrated symbols found in $CFG:" - comm -12 ${KSYMLST} ${KUSEDLST} - RET=1 - fi - done - exit $RET + # If grep succeeds and finds a match the test fails as we should + # have no matches. + - script: git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_' + include/configs `find arch -name config.h` && exit 1 || exit 0 - job: cppcheck displayName: 'Static code analysis with cppcheck' diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e14b57a5e0..afd83948c1 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -124,31 +124,14 @@ build all other platforms: exit $ret; fi; -check for migrated symbols in board header: +check for new CONFIG symbols outside Kconfig: stage: testsuites script: - - KSYMLST=`mktemp`; - KUSEDLST=`mktemp`; - RET=0; - cat `find . -name "Kconfig*"` | - sed -n -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' - -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' - | sort -u > $KSYMLST; - for CFG in `find include/configs -name "*.h"`; do - (grep '#define[[:blank:]]CONFIG_' $CFG | - sed -n 's/#define.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' ; - grep '#undef[[:blank:]]CONFIG_' $CFG | - sed -n 's/#undef.\(CONFIG_[A-Za-z0-9_]*\).*/\1/p') | - sort -u > ${KUSEDLST} || true; - NUM=`comm -123 --total --output-delimiter=, ${KSYMLST} ${KUSEDLST} | - cut -d , -f 3`; - if [[ $NUM -ne 0 ]]; then - echo "Unmigrated symbols found in $CFG:"; - comm -12 ${KSYMLST} ${KUSEDLST}; - RET=1; - fi; - done; - exit $RET + - git config --global --add safe.directory "${CI_PROJECT_DIR}" + # If grep succeeds and finds a match the test fails as we should + # have no matches. + - git grep -E '^#[[:blank:]]*(define|undef)[[:blank:]]*CONFIG_' + include/configs `find arch -name config.h` && exit 1 || exit 0 # QA jobs for code analytics # static code analysis with cppcheck (we can add --enable=all later) From 9ef3ba85bf38289a3e3b0dcb92fad9480a0b1834 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:16 -0500 Subject: [PATCH 352/424] kbuild: Remove checking for adhoc CONFIG symbols At this point all listed adhoc CONFIG symbols have been migrated to Kconfig or removed from the tree or renamed to CFG (or similar). We also now have CI tests that will error on any new introductions, and checkpatch.pl also looks. We can now remove these hooks and related scripts. Signed-off-by: Tom Rini --- Makefile | 8 -- scripts/build-whitelist.sh | 45 ------- scripts/check-config.sh | 63 --------- scripts/config_whitelist.txt | 245 ----------------------------------- tools/moveconfig.py | 32 +---- 5 files changed, 2 insertions(+), 391 deletions(-) delete mode 100755 scripts/build-whitelist.sh delete mode 100755 scripts/check-config.sh delete mode 100644 scripts/config_whitelist.txt diff --git a/Makefile b/Makefile index 8cd873fd5f..5610f7b492 100644 --- a/Makefile +++ b/Makefile @@ -1075,10 +1075,6 @@ cmd_lzma = lzma -c -z -k -9 $< > $@ cfg: u-boot.cfg -quiet_cmd_cfgcheck = CFGCHK $2 -cmd_cfgcheck = $(srctree)/scripts/check-config.sh $2 \ - $(srctree)/scripts/config_whitelist.txt $(srctree) - quiet_cmd_ofcheck = OFCHK $2 cmd_ofcheck = $(srctree)/scripts/check-of.sh $2 \ $(srctree)/scripts/of_allowlist.txt @@ -1146,10 +1142,6 @@ endif $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) - @# Check that this build does not use CONFIG options that we do not - @# know about unless they are in Kconfig. All the existing CONFIG - @# options are whitelisted, so new ones should not be added. - $(call cmd,cfgcheck,u-boot.cfg) @# Check that this build does not override OF_HAS_PRIOR_STAGE by @# disabling OF_BOARD. $(call cmd,ofcheck,$(KCONFIG_CONFIG)) diff --git a/scripts/build-whitelist.sh b/scripts/build-whitelist.sh deleted file mode 100755 index 37630c0271..0000000000 --- a/scripts/build-whitelist.sh +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh -# Copyright (c) 2016 Google, Inc -# Written by Simon Glass -# - -# This script creates the configuration whitelist file. This file contains -# all the config options which are allowed to be used outside Kconfig. -# Please do not add things to the whitelist. Instead, add your new option -# to Kconfig. -# -export LC_ALL=C LC_COLLATE=C - -# Looks for the rest of the CONFIG options, but exclude those in Kconfig and -# defconfig files. -# -git grep CONFIG_ | \ - egrep -vi "(Kconfig:|defconfig:|README|\.py|\.pl:)" \ - | tr ' \t' '\n\n' \ - | sed -n 's/^\(CONFIG_[A-Za-z0-9_]*\).*/\1/p' \ - |sort |uniq >scripts/config_whitelist.txt.tmp1; - -# Finally, we need a list of the valid Kconfig options to exclude these from -# the whitelist. -cat `find . -name "Kconfig*"` |sed -n \ - -e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \ - -e 's/^\s*menuconfig *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \ - |sort |uniq >scripts/config_whitelist.txt.tmp2 - -# Use only the options that are present in the first file but not the second. -comm -23 scripts/config_whitelist.txt.tmp1 scripts/config_whitelist.txt.tmp2 \ - |sort |uniq >scripts/config_whitelist.txt.tmp3 - -# If scripts/config_whitelist.txt already exists, take the intersection of the -# current list and the new one. We do not want to increase whitelist options. -if [ -r scripts/config_whitelist.txt ]; then - comm -12 scripts/config_whitelist.txt.tmp3 scripts/config_whitelist.txt \ - > scripts/config_whitelist.txt.tmp4 - mv scripts/config_whitelist.txt.tmp4 scripts/config_whitelist.txt -else - mv scripts/config_whitelist.txt.tmp3 scripts/config_whitelist.txt -fi - -rm scripts/config_whitelist.txt.tmp* - -unset LC_ALL LC_COLLATE diff --git a/scripts/check-config.sh b/scripts/check-config.sh deleted file mode 100755 index cc1c9a54d9..0000000000 --- a/scripts/check-config.sh +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh -# Copyright (c) 2016 Google, Inc -# Written by Simon Glass -# -# Check that the u-boot.cfg file provided does not introduce any new -# ad-hoc CONFIG options -# -# Use scripts/build-whitelist.sh to generate the list of current ad-hoc -# CONFIG options (those which are not in Kconfig). - -# Usage -# check-config.sh -# -# For example: -# scripts/check-config.sh b/chromebook_link/u-boot.cfg kconfig_whitelist.txt . - -set -e -set -u - -PROG_NAME="${0##*/}" - -usage() { - echo "$PROG_NAME " - exit 1 -} - -[ $# -ge 3 ] || usage - -path="$1" -whitelist="$2" -srctree="$3" - -# Temporary files -configs="${path}.configs" -suspects="${path}.suspects" -ok="${path}.ok" -new_adhoc="${path}.adhoc" - -export LC_ALL=C -export LC_COLLATE=C - -cat ${path} |sed -nr 's/^#define (CONFIG_[A-Za-z0-9_]*).*/\1/p' |sort |uniq \ - >${configs} - -comm -23 ${configs} ${whitelist} > ${suspects} - -cat `find ${srctree} -name "Kconfig*"` |sed -nr \ - -e 's/^[[:blank:]]*config *([A-Za-z0-9_]*).*$/CONFIG_\1/p' \ - -e 's/^[[:blank:]]*menuconfig ([A-Za-z0-9_]*).*$/CONFIG_\1/p' \ - |sort |uniq > ${ok} -comm -23 ${suspects} ${ok} >${new_adhoc} -if [ -s ${new_adhoc} ]; then - echo >&2 "Error: You must add new CONFIG options using Kconfig" - echo >&2 "The following new ad-hoc CONFIG options were detected:" - cat >&2 ${new_adhoc} - echo >&2 - echo >&2 "Please add these via Kconfig instead. Find a suitable Kconfig" - echo >&2 "file and add a 'config' or 'menuconfig' option." - # Don't delete the temporary files in case they are useful - exit 1 -else - rm ${suspects} ${ok} ${new_adhoc} -fi diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt deleted file mode 100644 index 9e346fbc44..0000000000 --- a/scripts/config_whitelist.txt +++ /dev/null @@ -1,245 +0,0 @@ -CONFIG_ARM_GIC_BASE_ADDRESS -CONFIG_BOARDDIR -CONFIG_DFU_ALT -CONFIG_DFU_ALT_BOOT_EMMC -CONFIG_DFU_ALT_BOOT_SD -CONFIG_DFU_ALT_SYSTEM -CONFIG_DFU_ENV_SETTINGS -CONFIG_DM9000_BASE -CONFIG_DM9000_BYTE_SWAPPED -CONFIG_DM9000_NO_SROM -CONFIG_DM9000_USE_16BIT -CONFIG_DW_WDT_CLOCK_KHZ -CONFIG_ENV_FLAGS_LIST_STATIC -CONFIG_ENV_IS_EMBEDDED -CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS -CONFIG_ENV_SETTINGS_NAND_V1 -CONFIG_ENV_SETTINGS_NAND_V2 -CONFIG_ENV_SETTINGS_V1 -CONFIG_ENV_SETTINGS_V2 -CONFIG_ENV_SROM_BANK -CONFIG_ENV_TOTAL_SIZE -CONFIG_ET1100_BASE -CONFIG_ETHBASE -CONFIG_EXTRA_ENV_SETTINGS -CONFIG_FB_ADDR -CONFIG_FDTADDR -CONFIG_FDTFILE -CONFIG_FEC_ENET_DEV -CONFIG_FEC_FIXED_SPEED -CONFIG_FEC_MXC_PHYADDR -CONFIG_FLASH_BR_PRELIM -CONFIG_FLASH_OR_PRELIM -CONFIG_FLASH_SECTOR_SIZE -CONFIG_FLASH_SHOW_PROGRESS -CONFIG_FLASH_SPANSION_S29WS_N -CONFIG_FLASH_VERIFY -CONFIG_FM_PLAT_CLK_DIV -CONFIG_FSL_CPLD -CONFIG_FSL_ESDHC_PIN_MUX -CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -CONFIG_FSL_ISBC_KEY_EXT -CONFIG_FSL_PMIC_BITLEN -CONFIG_FSL_PMIC_BUS -CONFIG_FSL_PMIC_CLK -CONFIG_FSL_PMIC_CS -CONFIG_FSL_PMIC_MODE -CONFIG_FSL_SDHC_V2_3 -CONFIG_FSL_SERDES1 -CONFIG_FSL_SERDES2 -CONFIG_GATEWAYIP -CONFIG_GMII -CONFIG_G_DNL_THOR_PRODUCT_NUM -CONFIG_G_DNL_THOR_VENDOR_NUM -CONFIG_G_DNL_UMS_PRODUCT_NUM -CONFIG_G_DNL_UMS_VENDOR_NUM -CONFIG_HDMI_ENCODER_I2C_ADDR -CONFIG_HOSTNAME -CONFIG_HSMMC2_8BIT -CONFIG_HW_ENV_SETTINGS -CONFIG_I2C_ENV_EEPROM_BUS -CONFIG_I2C_MULTI_BUS -CONFIG_I2C_MVTWSI -CONFIG_I2C_MVTWSI_BASE0 -CONFIG_I2C_MVTWSI_BASE1 -CONFIG_I2C_RTC_ADDR -CONFIG_ICS307_REFCLK_HZ -CONFIG_IMX6_PWM_PER_CLK -CONFIG_IPADDR -CONFIG_IRAM_BASE -CONFIG_IRAM_END -CONFIG_IRAM_SIZE -CONFIG_IRAM_TOP -CONFIG_KSNET_CPSW_NUM_PORTS -CONFIG_KSNET_MAC_ID_BASE -CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -CONFIG_KSNET_NETCP_BASE -CONFIG_KSNET_NETCP_V1_0 -CONFIG_KSNET_NETCP_V1_5 -CONFIG_KSNET_SERDES_LANES_PER_SGMII -CONFIG_KSNET_SERDES_SGMII2_BASE -CONFIG_KSNET_SERDES_SGMII_BASE -CONFIG_L1_INIT_RAM -CONFIG_L2_CACHE -CONFIG_LEGACY_BOOTCMD_ENV -CONFIG_LOWPOWER_ADDR -CONFIG_LOWPOWER_FLAG -CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY -CONFIG_LPC32XX_NAND_MLC_NAND_TA -CONFIG_LPC32XX_NAND_MLC_RD_HIGH -CONFIG_LPC32XX_NAND_MLC_RD_LOW -CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY -CONFIG_LPC32XX_NAND_MLC_WR_HIGH -CONFIG_LPC32XX_NAND_MLC_WR_LOW -CONFIG_LPC32XX_NAND_SLC_RDR_CLKS -CONFIG_LPC32XX_NAND_SLC_RHOLD -CONFIG_LPC32XX_NAND_SLC_RSETUP -CONFIG_LPC32XX_NAND_SLC_RWIDTH -CONFIG_LPC32XX_NAND_SLC_WDR_CLKS -CONFIG_LPC32XX_NAND_SLC_WHOLD -CONFIG_LPC32XX_NAND_SLC_WSETUP -CONFIG_LPC32XX_NAND_SLC_WWIDTH -CONFIG_MACB_SEARCH_PHY -CONFIG_MALLOC_F_ADDR -CONFIG_MALTA -CONFIG_MAX_DSP_CPUS -CONFIG_MAX_MEM_MAPPED -CONFIG_MAX_RAM_BANK_SIZE -CONFIG_MEMSIZE_IN_BYTES -CONFIG_MEM_INIT_VALUE -CONFIG_MFG_ENV_SETTINGS -CONFIG_MII_DEFAULT_TSEC -CONFIG_MIU_2BIT_21_7_INTERLEAVED -CONFIG_MIU_2BIT_INTERLEAVED -CONFIG_MMC_DEFAULT_DEV -CONFIG_MONITOR_IS_IN_RAM -CONFIG_MTD_NAND_VERIFY_WRITE -CONFIG_MVGBE_PORTS -CONFIG_MXC_GPT_HCLK -CONFIG_MXC_NAND_HWECC -CONFIG_MXC_NAND_IP_REGS_BASE -CONFIG_MXC_NAND_REGS_BASE -CONFIG_MXC_UART_BASE -CONFIG_MXC_USB_FLAGS -CONFIG_MXC_USB_PORT -CONFIG_MXC_USB_PORTSC -CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC -CONFIG_NAND_CS_INIT -CONFIG_NETDEV -CONFIG_NETMASK -CONFIG_NORBOOT -CONFIG_NUM_DSP_CPUS -CONFIG_ODROID_REV_AIN -CONFIG_OTHBOOTARGS -CONFIG_OVERWRITE_ETHADDR_ONCE -CONFIG_PCIE_IMX_PERST_GPIO -CONFIG_PCIE_IMX_POWER_GPIO -CONFIG_PEN_ADDR_BIG_ENDIAN -CONFIG_PHY_BASE_ADR -CONFIG_PHY_ET1011C_TX_CLK_FIX -CONFIG_PHY_ID -CONFIG_PHY_INTERFACE_MODE -CONFIG_PHY_IRAM_BASE -CONFIG_PL011_CLOCK -CONFIG_PL01x_PORTS -CONFIG_PME_PLAT_CLK_DIV -CONFIG_POST -CONFIG_POSTBOOTMENU -CONFIG_POST_EXTERNAL_WORD_FUNCS -CONFIG_POWER_LTC3676_I2C_ADDR -CONFIG_POWER_PFUZE100_I2C_ADDR -CONFIG_POWER_PFUZE3000_I2C_ADDR -CONFIG_PPC_SPINTABLE_COMPATIBLE -CONFIG_PRAM -CONFIG_PSRAM_SCFG -CONFIG_QBMAN_CLK_DIV -CONFIG_RAMBOOT_SPIFLASH -CONFIG_RAMBOOT_TEXT_BASE -CONFIG_RAMDISK_ADDR -CONFIG_RD_LVL -CONFIG_RESET_VECTOR_ADDRESS -CONFIG_ROCKCHIP_SDHCI_MAX_FREQ -CONFIG_ROOTPATH -CONFIG_SANDBOX_ARCH -CONFIG_SANDBOX_SDL -CONFIG_SANDBOX_SPI_MAX_BUS -CONFIG_SANDBOX_SPI_MAX_CS -CONFIG_SAR2_REG -CONFIG_SAR_REG -CONFIG_SCIF_A -CONFIG_SCSI_DEV_LIST -CONFIG_SC_TIMER_CLK -CONFIG_SERIAL_BOOT -CONFIG_SERVERIP -CONFIG_SETUP_INITRD_TAG -CONFIG_SET_DFU_ALT_BUF_LEN -CONFIG_SH_ETHER_ALIGNE_SIZE -CONFIG_SH_ETHER_CACHE_INVALIDATE -CONFIG_SH_ETHER_CACHE_WRITEBACK -CONFIG_SH_ETHER_PHY_ADDR -CONFIG_SH_ETHER_PHY_MODE -CONFIG_SH_ETHER_USE_PORT -CONFIG_SH_QSPI_BASE -CONFIG_SLIC -CONFIG_SMDK5420 -CONFIG_SMP_PEN_ADDR -CONFIG_SOCRATES -CONFIG_SPI_ADDR -CONFIG_SPI_BOOTING -CONFIG_SPI_FLASH_QUAD -CONFIG_SPI_FLASH_SIZE -CONFIG_SPI_HALF_DUPLEX -CONFIG_SPI_N25Q256A_RESET -CONFIG_STACKBASE -CONFIG_STANDALONE_LOAD_ADDR -CONFIG_STD_DEVICES_SETTINGS -CONFIG_SYS_BAUDRATE_TABLE -CONFIG_TEGRA_BOARD_STRING -CONFIG_TEGRA_ENABLE_UARTA -CONFIG_TEGRA_ENABLE_UARTD -CONFIG_TEGRA_SLINK_CTRLS -CONFIG_TEGRA_SPI -CONFIG_TEGRA_UARTA_GPU -CONFIG_TEGRA_UARTA_SDIO1 -CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 -CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 -CONFIG_TESTPIN_MASK -CONFIG_TESTPIN_REG -CONFIG_THOR_RESET_OFF -CONFIG_TPM_TIS_BASE_ADDRESS -CONFIG_TSEC1 -CONFIG_TSEC1_NAME -CONFIG_TSEC2 -CONFIG_TSEC2_NAME -CONFIG_TSEC3 -CONFIG_TSEC3_NAME -CONFIG_TSEC4 -CONFIG_TSEC4_NAME -CONFIG_TSECV2 -CONFIG_TSECV2_1 -CONFIG_TSEC_TBICR_SETTINGS -CONFIG_UBIFS_VOLUME -CONFIG_UBI_PART -CONFIG_UBOOTPATH -CONFIG_UBOOT_SECTOR_COUNT -CONFIG_UBOOT_SECTOR_START -CONFIG_UEC_ETH -CONFIG_USART_BASE -CONFIG_USART_ID -CONFIG_USBD_HS -CONFIG_USB_BOOTING -CONFIG_USB_EXT2_BOOT -CONFIG_USB_FAT_BOOT -CONFIG_USB_ISP1301_I2C_ADDR -CONFIG_U_BOOT_HDR_SIZE -CONFIG_VAR_SIZE_SPL -CONFIG_VERY_BIG_RAM -CONFIG_VSC7385_IMAGE -CONFIG_VSC7385_IMAGE_SIZE -CONFIG_WATCHDOG_PRESC -CONFIG_WATCHDOG_RC -CONFIG_WATCHDOG_TIMEOUT -CONFIG_X86EMU_RAW_IO -CONFIG_X86_MRC_ADDR -CONFIG_X86_REFCODE_ADDR -CONFIG_X86_REFCODE_RUN_ADDR diff --git a/tools/moveconfig.py b/tools/moveconfig.py index 09617a07f9..8f084a6070 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -443,22 +443,6 @@ def cleanup_headers(configs, args): cleanup_one_header(header_path, patterns, args) cleanup_empty_blocks(header_path, args) -def cleanup_whitelist(configs, args): - """Delete config whitelist entries - - Args: - configs: A list of CONFIGs to remove. - args (Namespace): program arguments - """ - if not confirm(args, 'Clean up whitelist entries?'): - return - - lines = read_file(os.path.join('scripts', 'config_whitelist.txt')) - - lines = [x for x in lines if x.strip() not in configs] - - write_file(os.path.join('scripts', 'config_whitelist.txt'), lines) - def find_matching(patterns, line): for pat in patterns: if pat.search(line): @@ -1558,14 +1542,10 @@ def do_find_config(config_list): """ all_configs, all_defconfigs, config_db, defconfig_db = read_database() - # Get the whitelist - adhoc_configs = set(read_file('scripts/config_whitelist.txt')) - # Start with all defconfigs out = all_defconfigs # Work through each config in turn - adhoc = [] for item in config_list: # Get the real config name and whether we want this config or not cfg = item @@ -1574,10 +1554,6 @@ def do_find_config(config_list): want = False cfg = cfg[1:] - if cfg in adhoc_configs: - adhoc.append(cfg) - continue - # Search everything that is still in the running. If it has a config # that we want, or doesn't have one that we don't, add it into the # running for the next stage @@ -1588,11 +1564,8 @@ def do_find_config(config_list): has_cfg = defconfig_matches(config_db[defc], re_match) if has_cfg == want: out.add(defc) - if adhoc: - print(f"Error: Not in Kconfig: %s" % ' '.join(adhoc)) - else: - print(f'{len(out)} matches') - print(' '.join(item.split('_defconfig')[0] for item in out)) + print(f'{len(out)} matches') + print(' '.join(item.split('_defconfig')[0] for item in out)) def prefix_config(cfg): @@ -1739,7 +1712,6 @@ doc/develop/moveconfig.rst for documentation.''' if configs: cleanup_headers(configs, args) - cleanup_whitelist(configs, args) cleanup_readme(configs, args) if args.commit: From 1e019503330585e892be057cca3ed4eb1b9c9344 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:17 -0500 Subject: [PATCH 353/424] post: Move CONFIG_SYS_POST to CFG_SYS_POST Migrate the rest of the CONFIG_SYS_POST macros over to CFG_SYS_POST namespace. Signed-off-by: Tom Rini --- doc/README.POST | 12 +-- drivers/serial/serial-uclass.c | 2 +- drivers/serial/serial.c | 2 +- include/post.h | 50 ++++++------ include/serial.h | 4 +- post/cpu/mpc83xx/ecc.c | 8 +- post/drivers/flash.c | 14 ++-- post/drivers/i2c.c | 20 ++--- post/drivers/rtc.c | 4 +- post/lib_powerpc/andi.c | 2 +- post/lib_powerpc/asm.S | 2 +- post/lib_powerpc/b.c | 2 +- post/lib_powerpc/cmp.c | 2 +- post/lib_powerpc/cmpi.c | 2 +- post/lib_powerpc/complex.c | 2 +- post/lib_powerpc/cpu.c | 4 +- post/lib_powerpc/cr.c | 2 +- post/lib_powerpc/fpu/20001122-1.c | 4 +- post/lib_powerpc/fpu/20010114-2.c | 4 +- post/lib_powerpc/fpu/20010226-1.c | 4 +- post/lib_powerpc/fpu/980619-1.c | 4 +- post/lib_powerpc/fpu/acc1.c | 4 +- post/lib_powerpc/fpu/compare-fp-1.c | 4 +- post/lib_powerpc/fpu/fpu.c | 4 +- post/lib_powerpc/fpu/mul-subnormal-single-1.c | 4 +- post/lib_powerpc/load.c | 2 +- post/lib_powerpc/multi.c | 2 +- post/lib_powerpc/rlwimi.c | 2 +- post/lib_powerpc/rlwinm.c | 2 +- post/lib_powerpc/rlwnm.c | 2 +- post/lib_powerpc/srawi.c | 2 +- post/lib_powerpc/store.c | 2 +- post/lib_powerpc/string.c | 2 +- post/lib_powerpc/three.c | 2 +- post/lib_powerpc/threei.c | 2 +- post/lib_powerpc/threex.c | 2 +- post/lib_powerpc/two.c | 2 +- post/lib_powerpc/twox.c | 2 +- post/post.c | 6 +- post/tests.c | 78 +++++++++---------- 40 files changed, 138 insertions(+), 138 deletions(-) diff --git a/doc/README.POST b/doc/README.POST index 5d92f3fe6e..1366f95c66 100644 --- a/doc/README.POST +++ b/doc/README.POST @@ -649,15 +649,15 @@ not need any modifications for porting them to another board/CPU. For verifying the I2C bus, a full I2C bus scanning will be performed using the i2c_probe() routine. If a board defines -CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices -listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional -devices are detected. If CONFIG_SYS_POST_I2C_ADDRS is not defined +CFG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices +listed in CFG_SYS_POST_I2C_ADDRS are found, and no additional +devices are detected. If CFG_SYS_POST_I2C_ADDRS is not defined the test will pass if any I2C device is found. -The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C +The CFG_SYS_POST_I2C_IGNORES define can be used to list I2C devices which may or may not be present when using -CONFIG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless -if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not. +CFG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless +if the devices in CFG_SYS_POST_I2C_IGNORES are found or not. This is useful in cases when I2C devices are optional (eg on a daughtercard that may or may not be present) or not critical to board operation. diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 7240d763d1..77d3f37372 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -526,7 +526,7 @@ static int serial_post_probe(struct udevice *dev) ops->getconfig += gd->reloc_off; if (ops->setconfig) ops->setconfig += gd->reloc_off; -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART if (ops->loop) ops->loop += gd->reloc_off; #endif diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 369a8e38e3..9a380d7c5e 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -458,7 +458,7 @@ void default_serial_puts(const char *s) dev->putc(*s++); } -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART static const int bauds[] = CFG_SYS_BAUDRATE_TABLE; /** diff --git a/include/post.h b/include/post.h index e68d5c8902..4112069506 100644 --- a/include/post.h +++ b/include/post.h @@ -17,8 +17,8 @@ #if defined(CONFIG_POST) #ifndef CFG_POST_EXTERNAL_WORD_FUNCS -#ifdef CONFIG_SYS_POST_WORD_ADDR -#define _POST_WORD_ADDR CONFIG_SYS_POST_WORD_ADDR +#ifdef CFG_SYS_POST_WORD_ADDR +#define _POST_WORD_ADDR CFG_SYS_POST_WORD_ADDR #else #if defined(CONFIG_ARCH_MPC8360) @@ -34,7 +34,7 @@ #ifndef _POST_WORD_ADDR #error "_POST_WORD_ADDR currently not implemented for this platform!" #endif -#endif /* CONFIG_SYS_POST_WORD_ADDR */ +#endif /* CFG_SYS_POST_WORD_ADDR */ static inline ulong post_word_load (void) { @@ -140,29 +140,29 @@ extern int memory_post_test(int flags); #endif /* __GNUC__ */ #endif /* __ASSEMBLY__ */ -#define CONFIG_SYS_POST_RTC 0x00000001 -#define CONFIG_SYS_POST_WATCHDOG 0x00000002 +#define CFG_SYS_POST_RTC 0x00000001 +#define CFG_SYS_POST_WATCHDOG 0x00000002 #define CFG_SYS_POST_MEMORY 0x00000004 -#define CONFIG_SYS_POST_CPU 0x00000008 -#define CONFIG_SYS_POST_I2C 0x00000010 -#define CONFIG_SYS_POST_CACHE 0x00000020 -#define CONFIG_SYS_POST_UART 0x00000040 -#define CONFIG_SYS_POST_ETHER 0x00000080 -#define CONFIG_SYS_POST_USB 0x00000200 -#define CONFIG_SYS_POST_SPR 0x00000400 -#define CONFIG_SYS_POST_SYSMON 0x00000800 -#define CONFIG_SYS_POST_DSP 0x00001000 -#define CONFIG_SYS_POST_OCM 0x00002000 -#define CONFIG_SYS_POST_FPU 0x00004000 -#define CONFIG_SYS_POST_ECC 0x00008000 -#define CONFIG_SYS_POST_BSPEC1 0x00010000 -#define CONFIG_SYS_POST_BSPEC2 0x00020000 -#define CONFIG_SYS_POST_BSPEC3 0x00040000 -#define CONFIG_SYS_POST_BSPEC4 0x00080000 -#define CONFIG_SYS_POST_BSPEC5 0x00100000 -#define CONFIG_SYS_POST_CODEC 0x00200000 -#define CONFIG_SYS_POST_COPROC 0x00400000 -#define CONFIG_SYS_POST_FLASH 0x00800000 +#define CFG_SYS_POST_CPU 0x00000008 +#define CFG_SYS_POST_I2C 0x00000010 +#define CFG_SYS_POST_CACHE 0x00000020 +#define CFG_SYS_POST_UART 0x00000040 +#define CFG_SYS_POST_ETHER 0x00000080 +#define CFG_SYS_POST_USB 0x00000200 +#define CFG_SYS_POST_SPR 0x00000400 +#define CFG_SYS_POST_SYSMON 0x00000800 +#define CFG_SYS_POST_DSP 0x00001000 +#define CFG_SYS_POST_OCM 0x00002000 +#define CFG_SYS_POST_FPU 0x00004000 +#define CFG_SYS_POST_ECC 0x00008000 +#define CFG_SYS_POST_BSPEC1 0x00010000 +#define CFG_SYS_POST_BSPEC2 0x00020000 +#define CFG_SYS_POST_BSPEC3 0x00040000 +#define CFG_SYS_POST_BSPEC4 0x00080000 +#define CFG_SYS_POST_BSPEC5 0x00100000 +#define CFG_SYS_POST_CODEC 0x00200000 +#define CFG_SYS_POST_COPROC 0x00400000 +#define CFG_SYS_POST_FLASH 0x00800000 #define CFG_SYS_POST_MEM_REGIONS 0x01000000 #endif /* CONFIG_POST */ diff --git a/include/serial.h b/include/serial.h index f4d7dc58a9..42bdf3759c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -14,7 +14,7 @@ struct serial_device { int (*tstc)(void); void (*putc)(const char c); void (*puts)(const char *s); -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART void (*loop)(int); #endif struct serial_device *next; @@ -242,7 +242,7 @@ struct dm_serial_ops { * @return 0 if OK, -ve on error */ int (*clear)(struct udevice *dev); -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART /** * loop() - Control serial device loopback mode * diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c index 45263e6b44..68da8ff417 100644 --- a/post/cpu/mpc83xx/ecc.c +++ b/post/cpu/mpc83xx/ecc.c @@ -17,7 +17,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CFG_SYS_POST_ECC /* * We use the RAW I/O accessors where possible in order to * achieve performance goal, since the test's execution time @@ -51,7 +51,7 @@ int ecc_post_test(int flags) int errbit; u32 pattern[2], writeback[2], retval[2]; ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; - volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR; + volatile u64 *addr = (u64 *)CFG_SYS_POST_ECC_START_ADDR; /* The pattern is written into memory to generate error */ pattern[0] = 0xfedcba98UL; @@ -70,8 +70,8 @@ int ecc_post_test(int flags) int_state = disable_interrupts(); icache_enable(); - for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0; - addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { + for (addr = (u64*)CFG_SYS_POST_ECC_START_ADDR, errbit=0; + addr < (u64*)CFG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) { schedule(); diff --git a/post/drivers/flash.c b/post/drivers/flash.c index e157d36911..a1fcf1f135 100644 --- a/post/drivers/flash.c +++ b/post/drivers/flash.c @@ -6,7 +6,7 @@ * Licensed under the GPL-2 or later. */ -#if CFG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CFG_SYS_POST_FLASH #include #include #include @@ -23,10 +23,10 @@ * - better seed pattern than 0x00..0xff */ -#ifndef CONFIG_SYS_POST_FLASH_NUM -# define CONFIG_SYS_POST_FLASH_NUM 0 +#ifndef CFG_SYS_POST_FLASH_NUM +# define CFG_SYS_POST_FLASH_NUM 0 #endif -#if CONFIG_SYS_POST_FLASH_START >= CONFIG_SYS_POST_FLASH_END +#if CFG_SYS_POST_FLASH_START >= CFG_SYS_POST_FLASH_END # error "invalid flash block start/end" #endif @@ -59,9 +59,9 @@ int flash_post_test(int flags) len = 0; src = NULL; - info = &flash_info[CONFIG_SYS_POST_FLASH_NUM]; - n_start = CONFIG_SYS_POST_FLASH_START; - n_end = CONFIG_SYS_POST_FLASH_END; + info = &flash_info[CFG_SYS_POST_FLASH_NUM]; + n_start = CFG_SYS_POST_FLASH_START; + n_end = CFG_SYS_POST_FLASH_END; for (n = n_start; n < n_end; ++n) { ulong s_start, s_len, s_off; diff --git a/post/drivers/i2c.c b/post/drivers/i2c.c index 057454ffd8..557d6329a4 100644 --- a/post/drivers/i2c.c +++ b/post/drivers/i2c.c @@ -9,14 +9,14 @@ * * For verifying the I2C bus, a full I2C bus scanning is performed. * - * #ifdef CONFIG_SYS_POST_I2C_ADDRS + * #ifdef CFG_SYS_POST_I2C_ADDRS * The test is considered as passed if all the devices and only the devices * in the list are found. - * #ifdef CONFIG_SYS_POST_I2C_IGNORES - * Ignore devices listed in CONFIG_SYS_POST_I2C_IGNORES. These devices + * #ifdef CFG_SYS_POST_I2C_IGNORES + * Ignore devices listed in CFG_SYS_POST_I2C_IGNORES. These devices * are optional or not vital to board functionality. * #endif - * #else [ ! CONFIG_SYS_POST_I2C_ADDRS ] + * #else [ ! CFG_SYS_POST_I2C_ADDRS ] * The test is considered as passed if any I2C device is found. * #endif */ @@ -26,12 +26,12 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CFG_SYS_POST_I2C static int i2c_ignore_device(unsigned int chip) { -#ifdef CONFIG_SYS_POST_I2C_IGNORES - const unsigned char i2c_ignore_list[] = CONFIG_SYS_POST_I2C_IGNORES; +#ifdef CFG_SYS_POST_I2C_IGNORES + const unsigned char i2c_ignore_list[] = CFG_SYS_POST_I2C_IGNORES; int i; for (i = 0; i < sizeof(i2c_ignore_list); i++) @@ -45,7 +45,7 @@ static int i2c_ignore_device(unsigned int chip) int i2c_post_test (int flags) { unsigned int i; -#ifndef CONFIG_SYS_POST_I2C_ADDRS +#ifndef CFG_SYS_POST_I2C_ADDRS /* Start at address 1, address 0 is the general call address */ for (i = 1; i < 128; i++) { if (i2c_ignore_device(i)) @@ -59,7 +59,7 @@ int i2c_post_test (int flags) #else unsigned int ret = 0; int j; - unsigned char i2c_addr_list[] = CONFIG_SYS_POST_I2C_ADDRS; + unsigned char i2c_addr_list[] = CFG_SYS_POST_I2C_ADDRS; /* Start at address 1, address 0 is the general call address */ for (i = 1; i < 128; i++) { @@ -94,4 +94,4 @@ int i2c_post_test (int flags) #endif } -#endif /* CFG_POST & CONFIG_SYS_POST_I2C */ +#endif /* CFG_POST & CFG_SYS_POST_I2C */ diff --git a/post/drivers/rtc.c b/post/drivers/rtc.c index cfed56b680..cc7a49847c 100644 --- a/post/drivers/rtc.c +++ b/post/drivers/rtc.c @@ -26,7 +26,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CFG_SYS_POST_RTC static int rtc_post_skip (ulong * diff) { @@ -189,4 +189,4 @@ int rtc_post_test (int flags) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_RTC */ +#endif /* CFG_POST & CFG_SYS_POST_RTC */ diff --git a/post/lib_powerpc/andi.c b/post/lib_powerpc/andi.c index d69d61396b..4f30216688 100644 --- a/post/lib_powerpc/andi.c +++ b/post/lib_powerpc/andi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/asm.S b/post/lib_powerpc/asm.S index 13302d7968..93c7856393 100644 --- a/post/lib_powerpc/asm.S +++ b/post/lib_powerpc/asm.S @@ -10,7 +10,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ .global cpu_post_exec_02 diff --git a/post/lib_powerpc/b.c b/post/lib_powerpc/b.c index eb9371fa6b..0ec032dcb1 100644 --- a/post/lib_powerpc/b.c +++ b/post/lib_powerpc/b.c @@ -24,7 +24,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, diff --git a/post/lib_powerpc/cmp.c b/post/lib_powerpc/cmp.c index e4d0931fc9..57f2b9694c 100644 --- a/post/lib_powerpc/cmp.c +++ b/post/lib_powerpc/cmp.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/cmpi.c b/post/lib_powerpc/cmpi.c index 983892d006..6e2bd636d7 100644 --- a/post/lib_powerpc/cmpi.c +++ b/post/lib_powerpc/cmpi.c @@ -23,7 +23,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); diff --git a/post/lib_powerpc/complex.c b/post/lib_powerpc/complex.c index d2ec21b0cb..751bce6737 100644 --- a/post/lib_powerpc/complex.c +++ b/post/lib_powerpc/complex.c @@ -18,7 +18,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); extern int cpu_post_complex_2_asm (int x, int n); diff --git a/post/lib_powerpc/cpu.c b/post/lib_powerpc/cpu.c index 77c2538172..98a8c6392c 100644 --- a/post/lib_powerpc/cpu.c +++ b/post/lib_powerpc/cpu.c @@ -20,7 +20,7 @@ #include #include -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern int cpu_post_test_cmp (void); extern int cpu_post_test_cmpi (void); @@ -118,4 +118,4 @@ int cpu_post_test (int flags) return ret; } -#endif /* CFG_POST & CONFIG_SYS_POST_CPU */ +#endif /* CFG_POST & CFG_SYS_POST_CPU */ diff --git a/post/lib_powerpc/cr.c b/post/lib_powerpc/cr.c index 077fb0f2da..3c7b611384 100644 --- a/post/lib_powerpc/cr.c +++ b/post/lib_powerpc/cr.c @@ -33,7 +33,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); diff --git a/post/lib_powerpc/fpu/20001122-1.c b/post/lib_powerpc/fpu/20001122-1.c index eddd3f915e..9c1c886fc4 100644 --- a/post/lib_powerpc/fpu/20001122-1.c +++ b/post/lib_powerpc/fpu/20001122-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU int fpu_post_test_math1 (void) { @@ -40,4 +40,4 @@ int fpu_post_test_math1 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010114-2.c b/post/lib_powerpc/fpu/20010114-2.c index 9e3e54661f..01bac50038 100644 --- a/post/lib_powerpc/fpu/20010114-2.c +++ b/post/lib_powerpc/fpu/20010114-2.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU static float rintf (float x) { @@ -45,4 +45,4 @@ int fpu_post_test_math2 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/20010226-1.c b/post/lib_powerpc/fpu/20010226-1.c index 5bb3860900..cc4aa0dca6 100644 --- a/post/lib_powerpc/fpu/20010226-1.c +++ b/post/lib_powerpc/fpu/20010226-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU int fpu_post_test_math3 (void) { @@ -33,4 +33,4 @@ int fpu_post_test_math3 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/980619-1.c b/post/lib_powerpc/fpu/980619-1.c index 415cd50c85..111a2013fb 100644 --- a/post/lib_powerpc/fpu/980619-1.c +++ b/post/lib_powerpc/fpu/980619-1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU int fpu_post_test_math4 (void) { @@ -39,4 +39,4 @@ int fpu_post_test_math4 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/acc1.c b/post/lib_powerpc/fpu/acc1.c index 4cf3b7cef7..63cc3eeafc 100644 --- a/post/lib_powerpc/fpu/acc1.c +++ b/post/lib_powerpc/fpu/acc1.c @@ -13,7 +13,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU static double func (const double *array) { @@ -36,4 +36,4 @@ int fpu_post_test_math5 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/compare-fp-1.c b/post/lib_powerpc/fpu/compare-fp-1.c index 029600fd2b..4b4589664f 100644 --- a/post/lib_powerpc/fpu/compare-fp-1.c +++ b/post/lib_powerpc/fpu/compare-fp-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU static int failed; @@ -204,4 +204,4 @@ int fpu_post_test_math6 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/fpu.c b/post/lib_powerpc/fpu/fpu.c index 8993b36e80..59109f71e3 100644 --- a/post/lib_powerpc/fpu/fpu.c +++ b/post/lib_powerpc/fpu/fpu.c @@ -21,7 +21,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU #include @@ -71,4 +71,4 @@ int fpu_post_test (int flags) return ret; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/fpu/mul-subnormal-single-1.c b/post/lib_powerpc/fpu/mul-subnormal-single-1.c index 87b882c6b2..891aa95685 100644 --- a/post/lib_powerpc/fpu/mul-subnormal-single-1.c +++ b/post/lib_powerpc/fpu/mul-subnormal-single-1.c @@ -15,7 +15,7 @@ GNU_FPOST_ATTR -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU union uf { @@ -82,4 +82,4 @@ int fpu_post_test_math7 (void) return 0; } -#endif /* CFG_POST & CONFIG_SYS_POST_FPU */ +#endif /* CFG_POST & CFG_SYS_POST_FPU */ diff --git a/post/lib_powerpc/load.c b/post/lib_powerpc/load.c index ece0b2756e..e4ac6bf186 100644 --- a/post/lib_powerpc/load.c +++ b/post/lib_powerpc/load.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); diff --git a/post/lib_powerpc/multi.c b/post/lib_powerpc/multi.c index 0e9ee88eb5..4df45790ab 100644 --- a/post/lib_powerpc/multi.c +++ b/post/lib_powerpc/multi.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_02(ulong *code, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwimi.c b/post/lib_powerpc/rlwimi.c index d24a3f665c..da21913225 100644 --- a/post/lib_powerpc/rlwimi.c +++ b/post/lib_powerpc/rlwimi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/rlwinm.c b/post/lib_powerpc/rlwinm.c index 9f4a3edb3e..b0b976f98a 100644 --- a/post/lib_powerpc/rlwinm.c +++ b/post/lib_powerpc/rlwinm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/rlwnm.c b/post/lib_powerpc/rlwnm.c index 224e6bdd45..22cd4568fc 100644 --- a/post/lib_powerpc/rlwnm.c +++ b/post/lib_powerpc/rlwnm.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/srawi.c b/post/lib_powerpc/srawi.c index 713d4f2276..a103df75eb 100644 --- a/post/lib_powerpc/srawi.c +++ b/post/lib_powerpc/srawi.c @@ -19,7 +19,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/store.c b/post/lib_powerpc/store.c index 2dbcccf098..71a4b6aba4 100644 --- a/post/lib_powerpc/store.c +++ b/post/lib_powerpc/store.c @@ -28,7 +28,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index 9b54847632..21e02bcb26 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -20,7 +20,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, diff --git a/post/lib_powerpc/three.c b/post/lib_powerpc/three.c index 55f0ff8a88..68339b05ef 100644 --- a/post/lib_powerpc/three.c +++ b/post/lib_powerpc/three.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/threei.c b/post/lib_powerpc/threei.c index ec52d238e6..885dd8cb09 100644 --- a/post/lib_powerpc/threei.c +++ b/post/lib_powerpc/threei.c @@ -21,7 +21,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/threex.c b/post/lib_powerpc/threex.c index 6f5f0b8eb7..62ac713ecf 100644 --- a/post/lib_powerpc/threex.c +++ b/post/lib_powerpc/threex.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, ulong op2); diff --git a/post/lib_powerpc/two.c b/post/lib_powerpc/two.c index b44dd4e208..7985669ba6 100644 --- a/post/lib_powerpc/two.c +++ b/post/lib_powerpc/two.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/lib_powerpc/twox.c b/post/lib_powerpc/twox.c index 320cc0a64e..33d1a1d8d9 100644 --- a/post/lib_powerpc/twox.c +++ b/post/lib_powerpc/twox.c @@ -22,7 +22,7 @@ #include #include "cpu_asm.h" -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); extern ulong cpu_post_makecr (long v); diff --git a/post/post.c b/post/post.c index 9964b41080..4db862c0db 100644 --- a/post/post.c +++ b/post/post.c @@ -16,7 +16,7 @@ #include #include -#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO +#ifdef CFG_SYS_POST_HOTKEYS_GPIO #include #endif @@ -55,9 +55,9 @@ int post_init_f(void) */ __weak int post_hotkeys_pressed(void) { -#ifdef CONFIG_SYS_POST_HOTKEYS_GPIO +#ifdef CFG_SYS_POST_HOTKEYS_GPIO int ret; - unsigned gpio = CONFIG_SYS_POST_HOTKEYS_GPIO; + unsigned gpio = CFG_SYS_POST_HOTKEYS_GPIO; ret = gpio_request(gpio, "hotkeys"); if (ret) { diff --git a/post/tests.c b/post/tests.c index d61ea74d51..8cea428fcd 100644 --- a/post/tests.c +++ b/post/tests.c @@ -45,7 +45,7 @@ extern void sysmon_reloc (void); struct post_test post_list[] = { -#if CFG_POST & CONFIG_SYS_POST_OCM +#if CFG_POST & CFG_SYS_POST_OCM { "OCM test", "ocm", @@ -54,10 +54,10 @@ struct post_test post_list[] = &ocm_post_test, NULL, NULL, - CONFIG_SYS_POST_OCM + CFG_SYS_POST_OCM }, #endif -#if CFG_POST & CONFIG_SYS_POST_CACHE +#if CFG_POST & CFG_SYS_POST_CACHE { "Cache test", "cache", @@ -66,10 +66,10 @@ struct post_test post_list[] = &cache_post_test, NULL, NULL, - CONFIG_SYS_POST_CACHE + CFG_SYS_POST_CACHE }, #endif -#if CFG_POST & CONFIG_SYS_POST_WATCHDOG +#if CFG_POST & CFG_SYS_POST_WATCHDOG #if defined(CFG_POST_WATCHDOG) CFG_POST_WATCHDOG, #else @@ -81,11 +81,11 @@ struct post_test post_list[] = &watchdog_post_test, NULL, NULL, - CONFIG_SYS_POST_WATCHDOG + CFG_SYS_POST_WATCHDOG }, #endif #endif -#if CFG_POST & CONFIG_SYS_POST_I2C +#if CFG_POST & CFG_SYS_POST_I2C { "I2C test", "i2c", @@ -94,10 +94,10 @@ struct post_test post_list[] = &i2c_post_test, NULL, NULL, - CONFIG_SYS_POST_I2C + CFG_SYS_POST_I2C }, #endif -#if CFG_POST & CONFIG_SYS_POST_RTC +#if CFG_POST & CFG_SYS_POST_RTC { "RTC test", "rtc", @@ -106,7 +106,7 @@ struct post_test post_list[] = &rtc_post_test, NULL, NULL, - CONFIG_SYS_POST_RTC + CFG_SYS_POST_RTC }, #endif #if CFG_POST & CFG_SYS_POST_MEMORY @@ -121,7 +121,7 @@ struct post_test post_list[] = CFG_SYS_POST_MEMORY }, #endif -#if CFG_POST & CONFIG_SYS_POST_CPU +#if CFG_POST & CFG_SYS_POST_CPU { "CPU test", "cpu", @@ -131,10 +131,10 @@ struct post_test post_list[] = &cpu_post_test, NULL, NULL, - CONFIG_SYS_POST_CPU + CFG_SYS_POST_CPU }, #endif -#if CFG_POST & CONFIG_SYS_POST_FPU +#if CFG_POST & CFG_SYS_POST_FPU { "FPU test", "fpu", @@ -144,10 +144,10 @@ struct post_test post_list[] = &fpu_post_test, NULL, NULL, - CONFIG_SYS_POST_FPU + CFG_SYS_POST_FPU }, #endif -#if CFG_POST & CONFIG_SYS_POST_UART +#if CFG_POST & CFG_SYS_POST_UART #if defined(CFG_POST_UART) CFG_POST_UART, #else @@ -159,11 +159,11 @@ struct post_test post_list[] = &uart_post_test, NULL, NULL, - CONFIG_SYS_POST_UART + CFG_SYS_POST_UART }, #endif /* CFG_POST_UART */ #endif -#if CFG_POST & CONFIG_SYS_POST_ETHER +#if CFG_POST & CFG_SYS_POST_ETHER { "ETHERNET test", "ethernet", @@ -172,10 +172,10 @@ struct post_test post_list[] = ðer_post_test, NULL, NULL, - CONFIG_SYS_POST_ETHER + CFG_SYS_POST_ETHER }, #endif -#if CFG_POST & CONFIG_SYS_POST_USB +#if CFG_POST & CFG_SYS_POST_USB { "USB test", "usb", @@ -184,10 +184,10 @@ struct post_test post_list[] = &usb_post_test, NULL, NULL, - CONFIG_SYS_POST_USB + CFG_SYS_POST_USB }, #endif -#if CFG_POST & CONFIG_SYS_POST_SPR +#if CFG_POST & CFG_SYS_POST_SPR { "SPR test", "spr", @@ -196,10 +196,10 @@ struct post_test post_list[] = &spr_post_test, NULL, NULL, - CONFIG_SYS_POST_SPR + CFG_SYS_POST_SPR }, #endif -#if CFG_POST & CONFIG_SYS_POST_SYSMON +#if CFG_POST & CFG_SYS_POST_SYSMON { "SYSMON test", "sysmon", @@ -208,10 +208,10 @@ struct post_test post_list[] = &sysmon_post_test, &sysmon_init_f, &sysmon_reloc, - CONFIG_SYS_POST_SYSMON + CFG_SYS_POST_SYSMON }, #endif -#if CFG_POST & CONFIG_SYS_POST_DSP +#if CFG_POST & CFG_SYS_POST_DSP { "DSP test", "dsp", @@ -220,10 +220,10 @@ struct post_test post_list[] = &dsp_post_test, NULL, NULL, - CONFIG_SYS_POST_DSP + CFG_SYS_POST_DSP }, #endif -#if CFG_POST & CONFIG_SYS_POST_CODEC +#if CFG_POST & CFG_SYS_POST_CODEC { "CODEC test", "codec", @@ -232,10 +232,10 @@ struct post_test post_list[] = &codec_post_test, NULL, NULL, - CONFIG_SYS_POST_CODEC + CFG_SYS_POST_CODEC }, #endif -#if CFG_POST & CONFIG_SYS_POST_ECC +#if CFG_POST & CFG_SYS_POST_ECC { "ECC test", "ecc", @@ -244,25 +244,25 @@ struct post_test post_list[] = &ecc_post_test, NULL, NULL, - CONFIG_SYS_POST_ECC + CFG_SYS_POST_ECC }, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC1 +#if CFG_POST & CFG_SYS_POST_BSPEC1 CFG_POST_BSPEC1, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC2 +#if CFG_POST & CFG_SYS_POST_BSPEC2 CFG_POST_BSPEC2, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC3 +#if CFG_POST & CFG_SYS_POST_BSPEC3 CFG_POST_BSPEC3, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC4 +#if CFG_POST & CFG_SYS_POST_BSPEC4 CFG_POST_BSPEC4, #endif -#if CFG_POST & CONFIG_SYS_POST_BSPEC5 +#if CFG_POST & CFG_SYS_POST_BSPEC5 CFG_POST_BSPEC5, #endif -#if CFG_POST & CONFIG_SYS_POST_COPROC +#if CFG_POST & CFG_SYS_POST_COPROC { "Coprocessors communication test", "coproc_com", @@ -271,10 +271,10 @@ struct post_test post_list[] = &coprocessor_post_test, NULL, NULL, - CONFIG_SYS_POST_COPROC + CFG_SYS_POST_COPROC }, #endif -#if CFG_POST & CONFIG_SYS_POST_FLASH +#if CFG_POST & CFG_SYS_POST_FLASH { "Parallel NOR flash test", "flash", @@ -283,7 +283,7 @@ struct post_test post_list[] = &flash_post_test, NULL, NULL, - CONFIG_SYS_POST_FLASH + CFG_SYS_POST_FLASH }, #endif #if CFG_POST & CFG_SYS_POST_MEM_REGIONS From 50e88c0fea36cccaeec75e790540721a3a62c349 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:18 -0500 Subject: [PATCH 354/424] pci-rcar-gen3: Rename CONFIG_SEND_ENABLE We rename the symbol CONFIG_SEND_ENABLE to just SEND_ENABLE, and remove the second whitespace following the define. Signed-off-by: Tom Rini --- drivers/pci/pci-rcar-gen3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 49029238d3..1252ef74c5 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -27,7 +27,7 @@ #define PCIECAR 0x000010 #define PCIECCTLR 0x000018 -#define CONFIG_SEND_ENABLE BIT(31) +#define SEND_ENABLE BIT(31) #define TYPE0 (0 << 8) #define TYPE1 BIT(8) #define PCIECDR 0x000020 @@ -170,9 +170,9 @@ static int rcar_pcie_config_access(const struct udevice *udev, /* Enable the configuration access */ if (!PCI_BUS(bdf)) - writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR); + writel(SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR); else - writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR); + writel(SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR); /* Check for errors */ if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST) From 648d675a2fa2cd14526da676c020590fd546ac63 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:19 -0500 Subject: [PATCH 355/424] cf_spi.c: Rename CONFIG_SPI_IDLE_VAL to SPI_IDLE_VAL This value is never changed by boards, so just rename it to SPI_IDLE_VAL to fit with the rest of the code. Signed-off-by: Tom Rini --- drivers/spi/cf_spi.c | 12 ++++++------ drivers/spi/sandbox_spi.c | 4 ---- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index ea23357090..1a841b5dce 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -32,11 +32,11 @@ struct coldfire_spi_priv { DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_SPI_IDLE_VAL +#ifndef SPI_IDLE_VAL #if defined(CONFIG_SPI_MMC) -#define CONFIG_SPI_IDLE_VAL 0xFFFF +#define SPI_IDLE_VAL 0xFFFF #else -#define CONFIG_SPI_IDLE_VAL 0x0 +#define SPI_IDLE_VAL 0x0 #endif #endif @@ -184,7 +184,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, } if (din) { - cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL); if (cfspi->charbit == 16) *spi_rd16++ = cfspi_rx(cfspi); else @@ -208,7 +208,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, } if (din) { - cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL); if (cfspi->charbit == 16) *spi_rd16 = cfspi_rx(cfspi); else @@ -216,7 +216,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, } } else { /* dummy read */ - cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + cfspi_tx(cfspi, ctrl, SPI_IDLE_VAL); cfspi_rx(cfspi); } diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c index 0564d8b55e..f844597d04 100644 --- a/drivers/spi/sandbox_spi.c +++ b/drivers/spi/sandbox_spi.c @@ -24,10 +24,6 @@ #include #include -#ifndef CONFIG_SPI_IDLE_VAL -# define CONFIG_SPI_IDLE_VAL 0xFF -#endif - /** * struct sandbox_spi_priv - Sandbox SPI private data * From 90c7888c9d6b3223c32f068668f3bc5a81010f8e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Sun, 4 Dec 2022 10:14:20 -0500 Subject: [PATCH 356/424] common/spl/spl_ram: Remove unused default We ask for CONFIG_SPL_LOAD_FIT_ADDRESS in Kconfig, so we cannot define it in C as a fall-back. However, this option previously was buried under "if ... endif" Kconfig logic. Rework a number of config options to now have more robust dependency lines so that we can ask this address when needed. With that done, we can remove the fallback in spl_ram.c. Signed-off-by: Tom Rini --- boot/Kconfig | 29 +++++++++++++++-------------- common/spl/spl_ram.c | 4 ---- 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/boot/Kconfig b/boot/Kconfig index 668270cc66..65613a0149 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -36,10 +36,9 @@ config TIMESTAMP loaded that does not, the message 'Wrong FIT format: no timestamp' is shown. -if FIT - config FIT_EXTERNAL_OFFSET hex "FIT external data offset" + depends on FIT default 0x0 help This specifies a data offset in fit image. @@ -50,6 +49,7 @@ config FIT_EXTERNAL_OFFSET config FIT_FULL_CHECK bool "Do a full check of the FIT before using it" + depends on FIT default y help Enable this do a full check of the FIT to make sure it is valid. This @@ -59,7 +59,7 @@ config FIT_FULL_CHECK config FIT_SIGNATURE bool "Enable signature verification of FIT uImages" - depends on DM + depends on DM && FIT select HASH imply RSA imply RSA_VERIFY @@ -97,7 +97,7 @@ config FIT_RSASSA_PSS config FIT_CIPHER bool "Enable ciphering data in a FIT uImages" - depends on DM + depends on DM && FIT select AES help Enable the feature of data ciphering/unciphering in the tool mkimage @@ -105,6 +105,7 @@ config FIT_CIPHER config FIT_VERBOSE bool "Show verbose messages when FIT images fail" + depends on FIT help Generally a system will have valid FIT images so debug messages are a waste of code space. If you are debugging your images then @@ -113,6 +114,7 @@ config FIT_VERBOSE config FIT_BEST_MATCH bool "Select the best match for the kernel device tree" + depends on FIT help When no configuration is explicitly selected, default to the one whose fdt's compatibility field best matches that of @@ -122,6 +124,7 @@ config FIT_BEST_MATCH config FIT_IMAGE_POST_PROCESS bool "Enable post-processing of FIT artifacts after loading by U-Boot" + depends on FIT depends on TI_SECURE_DEVICE || SOCFPGA_SECURE_VAB_AUTH default y if TI_SECURE_DEVICE help @@ -137,15 +140,14 @@ config FIT_IMAGE_POST_PROCESS config FIT_PRINT bool "Support FIT printing" + depends on FIT default y help Support printing the content of the fitImage in a verbose manner. -if SPL - config SPL_FIT bool "Support Flattened Image Tree within SPL" - depends on SPL + depends on SPL && FIT select SPL_HASH select SPL_OF_LIBFDT @@ -157,13 +159,13 @@ config SPL_FIT_PRINT config SPL_FIT_FULL_CHECK bool "Do a full check of the FIT before using it" + depends on SPL_FIT help Enable this do a full check of the FIT to make sure it is valid. This helps to protect against carefully crafted FITs which take advantage of bugs or omissions in the code. This includes a bad structure, multiple root nodes and the like. - config SPL_FIT_SIGNATURE bool "Enable signature verification of FIT firmware within SPL" depends on SPL_DM @@ -196,6 +198,7 @@ config SPL_FIT_RSASSA_PSS config SPL_LOAD_FIT bool "Enable SPL loading U-Boot as a FIT (basic fitImage features)" + depends on SPL && FIT select SPL_FIT help Normally with the SPL framework a legacy image is generated as part @@ -217,7 +220,7 @@ config SPL_LOAD_FIT config SPL_LOAD_FIT_ADDRESS hex "load address of fit image" - depends on SPL_LOAD_FIT + depends on SPL_LOAD_FIT || SPL_RAM_SUPPORT || TPL_RAM_SUPPORT default 0x0 help Specify the load address of the fit image that will be loaded @@ -243,6 +246,7 @@ config SPL_LOAD_FIT_APPLY_OVERLAY_BUF_SZ config SPL_LOAD_FIT_FULL bool "Enable SPL loading U-Boot as a FIT (full fitImage features)" + depends on FIT select SPL_FIT help Normally with the SPL framework a legacy image is generated as part @@ -277,7 +281,8 @@ config SPL_FIT_SOURCE config USE_SPL_FIT_GENERATOR bool "Use a script to generate the .its script" - default y if SPL_FIT && (!ARCH_SUNXI && !RISCV) + depends on SPL_FIT + default y if !ARCH_SUNXI && !RISCV config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" @@ -290,8 +295,6 @@ config SPL_FIT_GENERATOR passed a list of supported device tree file stub names to include in the generated image. -endif # SPL - if VPL config VPL_FIT @@ -342,8 +345,6 @@ config VPL_FIT_SIGNATURE_MAX_SIZE endif # VPL -endif # FIT - config PXE_UTILS bool select MENU diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 2b1ac19152..5753bd228f 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -17,10 +17,6 @@ #include #include -#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS -# define CONFIG_SPL_LOAD_FIT_ADDRESS 0 -#endif - static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { From b5fd7b4a31e5098ff024ebc63bccfcb2b4429c82 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:07 -0500 Subject: [PATCH 357/424] image: Add fallback for fit_config_verify Add a fallback for this function so it can be used without regard to whether FIT_SIGNATURE is enabled or not. Signed-off-by: Sean Anderson Reviewed-by: Tom Rini Reviewed-by: Simon Glass --- include/image.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/image.h b/include/image.h index b6a809834a..6f9c5a486b 100644 --- a/include/image.h +++ b/include/image.h @@ -1259,7 +1259,14 @@ int fit_image_verify_with_data(const void *fit, int image_noffset, size_t size); int fit_image_verify(const void *fit, int noffset); +#if CONFIG_IS_ENABLED(FIT_SIGNATURE) int fit_config_verify(const void *fit, int conf_noffset); +#else +static inline int fit_config_verify(const void *fit, int conf_noffset) +{ + return 0; +} +#endif int fit_all_image_verify(const void *fit); int fit_config_decrypt(const void *fit, int conf_noffset); int fit_image_check_os(const void *fit, int noffset, uint8_t os); From 895999261ca02882813d477f28ba06c8060d9c43 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:08 -0500 Subject: [PATCH 358/424] test: Add test for source command This adds a basic test for FIT image handling by the source command. It's a python test becase we need to run mkimage. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- test/py/tests/source.its | 43 ++++++++++++++++++++++++++++++++++++ test/py/tests/test_source.py | 28 +++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 test/py/tests/source.its create mode 100644 test/py/tests/test_source.py diff --git a/test/py/tests/source.its b/test/py/tests/source.its new file mode 100644 index 0000000000..3c62f777f1 --- /dev/null +++ b/test/py/tests/source.its @@ -0,0 +1,43 @@ +/dts-v1/; + +/ { + description = "FIT image to test the source command"; + #address-cells = <1>; + + images { + default = "script-1"; + + script-1 { + data = "echo 1"; + type = "script"; + arch = "sandbox"; + compression = "none"; + }; + + script-2 { + data = "echo 2"; + type = "script"; + arch = "sandbox"; + compression = "none"; + }; + + not-a-script { + data = "echo 3"; + type = "kernel"; + arch = "sandbox"; + compression = "none"; + }; + }; + + configurations { + default = "conf-2"; + + conf-1 { + script = "script-1"; + }; + + conf-2 { + script = "script-2"; + }; + }; +}; diff --git a/test/py/tests/test_source.py b/test/py/tests/test_source.py new file mode 100644 index 0000000000..e5ffdfe3fc --- /dev/null +++ b/test/py/tests/test_source.py @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022 Sean Anderson + +import os +import pytest +import u_boot_utils as util + +@pytest.mark.boardspec('sandbox') +@pytest.mark.buildconfigspec('cmd_echo') +@pytest.mark.buildconfigspec('cmd_source') +@pytest.mark.buildconfigspec('fit') +def test_source(u_boot_console): + # Compile our test script image + cons = u_boot_console + mkimage = os.path.join(cons.config.build_dir, 'tools/mkimage') + its = os.path.join(cons.config.source_dir, 'test/py/tests/source.its') + fit = os.path.join(cons.config.build_dir, 'source.itb') + util.run_and_log(cons, (mkimage, '-f', its, fit)) + cons.run_command(f'host load hostfs - $loadaddr {fit}') + + assert '1' in cons.run_command('source') + assert '1' in cons.run_command('source :script-1') + assert '2' in cons.run_command('source :script-2') + assert 'Fail' in cons.run_command('source :not-a-script || echo Fail') + + cons.run_command('fdt addr $loadaddr') + cons.run_command('fdt rm /images default') + assert 'Fail' in cons.run_command('source || echo Fail') From 30fb045f2dccf1a58153bae2183121a1ae8fe05b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:09 -0500 Subject: [PATCH 359/424] treewide: Use NULL for script image name Two callers of image_source_script specify an image name. However, both use the deprecated @ syntax, indicating that they have not been updated in a while. If CONFIG_FIT_SIGNATURE is enabled, we will reject such names outright. Back in commit 152576a598c ("stm32mp: stm32prog: handle U-Boot script in flashlayout alternate"), we even renamed one of the nodes. Instead of hard-coding a script image name, just use the default image. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 2 +- drivers/usb/gadget/f_sdp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 007f713130..3627b4c35c 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -154,7 +154,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, do_bootz(cmdtp, 0, 4, bootm_argv); } if (data->script) - image_source_script(data->script, "script@stm32prog"); + image_source_script(data->script, NULL); if (reset) { puts("Reset...\n"); diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index af4b167e17..1643d28947 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -868,7 +868,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ - image_source_script(sdp_func->jmp_address, "script@1"); + image_source_script(sdp_func->jmp_address, NULL); #endif } From c4f5738e690487dc59c8234782e792e57dac9a22 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:10 -0500 Subject: [PATCH 360/424] cmd: source: Clean up a few lines This simplifies a few lines and corrects an error message. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- cmd/source.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/cmd/source.c b/cmd/source.c index 698d9f86d9..5973824601 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -128,16 +128,14 @@ int image_source_script(ulong addr, const char *fit_uname) } if (!fit_image_check_type (fit_hdr, noffset, IH_TYPE_SCRIPT)) { - puts ("Not a image image\n"); + puts("Not a script image\n"); return 1; } /* verify integrity */ - if (verify) { - if (!fit_image_verify(fit_hdr, noffset)) { - puts ("Bad Data Hash\n"); - return 1; - } + if (verify && !fit_image_verify(fit_hdr, noffset)) { + puts("Bad Data Hash\n"); + return 1; } /* get script subimage data address and length */ From bcc85b96b5ffbbce19a89747138feb873d918915 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 12 Dec 2022 14:12:11 -0500 Subject: [PATCH 361/424] cmd: source: Support specifying config name As discussed previously [1,2], the source command is not safe to use with verified boot unless there is a key with required = "images" (which has its own problems). This is because if such a key is absent, signatures are verified but not required. It is assumed that configuration nodes will provide the signature. Because the source command does not use configurations to determine the image to source, effectively no verification takes place. To address this, allow specifying configuration nodes. We use the same syntax as the bootm command (helpfully provided for us by fit_parse_conf). By default, we first try the default config and then the default image. To force using a config, # must be present in the command (e.g. `source $loadaddr#my-conf`). For convenience, the config may be omitted, just like the address may be (e.g. `source \#`). This also works for images (`source :` behaves exactly like `source` currently does). [1] https://lore.kernel.org/u-boot/7d711133-d513-5bcb-52f2-a9dbaa9eeded@prevas.dk/ [2] https://lore.kernel.org/u-boot/042dcb34-f85f-351e-1b0e-513f89005fdd@gmail.com/ Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- .../cmd_stm32prog/cmd_stm32prog.c | 2 +- boot/bootmeth_script.c | 2 +- cmd/source.c | 74 +++++++++++++------ doc/uImage.FIT/source_file_format.txt | 3 + drivers/usb/gadget/f_sdp.c | 2 +- include/image.h | 15 +++- test/py/tests/test_source.py | 11 ++- 7 files changed, 81 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index 3627b4c35c..cb13a14d82 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -154,7 +154,7 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, do_bootz(cmdtp, 0, 4, bootm_argv); } if (data->script) - image_source_script(data->script, NULL); + image_source_script(data->script, NULL, NULL); if (reset) { puts("Reset...\n"); diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c index d1c3f94003..6c84721d1c 100644 --- a/boot/bootmeth_script.c +++ b/boot/bootmeth_script.c @@ -101,7 +101,7 @@ static int script_boot(struct udevice *dev, struct bootflow *bflow) log_debug("mmc_bootdev: %s\n", env_get("mmc_bootdev")); addr = map_to_sysmem(bflow->buf); - ret = image_source_script(addr, NULL); + ret = image_source_script(addr, NULL, NULL); if (ret) return log_msg_ret("boot", ret); diff --git a/cmd/source.c b/cmd/source.c index 5973824601..94da5d8d6a 100644 --- a/cmd/source.c +++ b/cmd/source.c @@ -42,7 +42,7 @@ static const char *get_default_image(const void *fit) } #endif -int image_source_script(ulong addr, const char *fit_uname) +int image_source_script(ulong addr, const char *fit_uname, const char *confname) { ulong len; #if defined(CONFIG_LEGACY_IMAGE_FORMAT) @@ -112,19 +112,47 @@ int image_source_script(ulong addr, const char *fit_uname) return 1; } - if (!fit_uname) - fit_uname = get_default_image(fit_hdr); - if (!fit_uname) { - puts("No FIT subimage unit name\n"); - return 1; - } + /* If confname is empty, use the default */ + if (confname && *confname) + noffset = fit_conf_get_node(fit_hdr, confname); + else + noffset = fit_conf_get_node(fit_hdr, NULL); + if (noffset < 0) { + if (!confname) + goto fallback; + printf("Could not find config %s\n", confname); + return 1; + } - /* get script component image node offset */ - noffset = fit_image_get_node (fit_hdr, fit_uname); - if (noffset < 0) { - printf ("Can't find '%s' FIT subimage\n", fit_uname); - return 1; + if (verify && fit_config_verify(fit_hdr, noffset)) + return 1; + + noffset = fit_conf_get_prop_node(fit_hdr, noffset, + FIT_SCRIPT_PROP, + IH_PHASE_NONE); + if (noffset < 0) { + if (!confname) + goto fallback; + printf("Could not find script in %s\n", confname); + return 1; + } + } else { +fallback: + if (!fit_uname || !*fit_uname) + fit_uname = get_default_image(fit_hdr); + if (!fit_uname) { + puts("No FIT subimage unit name\n"); + return 1; + } + + /* get script component image node offset */ + noffset = fit_image_get_node(fit_hdr, fit_uname); + if (noffset < 0) { + printf("Can't find '%s' FIT subimage\n", + fit_uname); + return 1; + } } if (!fit_image_check_type (fit_hdr, noffset, IH_TYPE_SCRIPT)) { @@ -164,7 +192,7 @@ static int do_source(struct cmd_tbl *cmdtp, int flag, int argc, { ulong addr; int rcode; - const char *fit_uname = NULL; + const char *fit_uname = NULL, *confname = NULL; /* Find script image */ if (argc < 2) { @@ -175,6 +203,9 @@ static int do_source(struct cmd_tbl *cmdtp, int flag, int argc, &fit_uname)) { debug("* source: subimage '%s' from FIT image at 0x%08lx\n", fit_uname, addr); + } else if (fit_parse_conf(argv[1], image_load_addr, &addr, &confname)) { + debug("* source: config '%s' from FIT image at 0x%08lx\n", + confname, addr); #endif } else { addr = hextoul(argv[1], NULL); @@ -182,21 +213,22 @@ static int do_source(struct cmd_tbl *cmdtp, int flag, int argc, } printf ("## Executing script at %08lx\n", addr); - rcode = image_source_script(addr, fit_uname); + rcode = image_source_script(addr, fit_uname, confname); return rcode; } #ifdef CONFIG_SYS_LONGHELP static char source_help_text[] = - "[addr]\n" - "\t- run script starting at addr\n" - "\t- A valid image header must be present" #if defined(CONFIG_FIT) - "\n" - "For FIT format uImage addr must include subimage\n" - "unit name in the form of addr:" + "[][:[]|#[]]\n" + "\t- Run script starting at addr\n" + "\t- A FIT config name or subimage name may be specified with : or #\n" + "\t (like bootm). If the image or config name is omitted, the\n" + "\t default is used."; +#else + "[]\n" + "\t- Run script starting at addr"; #endif - ""; #endif U_BOOT_CMD( diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 4640e38e3c..269e1fa0b5 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -247,6 +247,7 @@ o config-1 |- kernel = "kernel sub-node unit name" |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...] |- loadables = "loadables sub-node unit-name" + |- script = " |- compatible = "vendor,board-style device tree compatible string" @@ -268,6 +269,8 @@ o config-1 of strings. U-Boot will load each binary at its given start-address and may optionally invoke additional post-processing steps on this binary based on its component image node type. + - script : The image to use when loading a U-Boot script (for use with the + source command). - compatible : The root compatible string of the U-Boot device tree that this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is enabled. If this property is not provided, the compatible string will be diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 1643d28947..5ae5b62741 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -868,7 +868,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, jump_to_image_no_args(&spl_image); #else /* In U-Boot, allow jumps to scripts */ - image_source_script(sdp_func->jmp_address, NULL); + image_source_script(sdp_func->jmp_address, NULL, NULL); #endif } diff --git a/include/image.h b/include/image.h index 6f9c5a486b..bed75ce1b3 100644 --- a/include/image.h +++ b/include/image.h @@ -711,15 +711,23 @@ int fit_image_load(struct bootm_headers *images, ulong addr, /** * image_source_script() - Execute a script + * @addr: Address of script + * @fit_uname: FIT subimage name + * @confname: FIT config name. The subimage is chosen based on FIT_SCRIPT_PROP. * * Executes a U-Boot script at a particular address in memory. The script should * have a header (FIT or legacy) with the script type (IH_TYPE_SCRIPT). * - * @addr: Address of script - * @fit_uname: FIT subimage name + * If @fit_uname is the empty string, then the default image is used. If + * @confname is the empty string, the default config is used. If @confname and + * @fit_uname are both non-%NULL, then @confname is ignored. If @confname and + * @fit_uname are both %NULL, then first the default config is tried, and then + * the default image. + * * Return: result code (enum command_ret_t) */ -int image_source_script(ulong addr, const char *fit_uname); +int image_source_script(ulong addr, const char *fit_uname, + const char *confname); /** * fit_get_node_from_config() - Look up an image a FIT by type @@ -1032,6 +1040,7 @@ int booti_setup(ulong image, ulong *relocated_addr, ulong *size, #define FIT_FPGA_PROP "fpga" #define FIT_FIRMWARE_PROP "firmware" #define FIT_STANDALONE_PROP "standalone" +#define FIT_SCRIPT_PROP "script" #define FIT_PHASE_PROP "phase" #define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE diff --git a/test/py/tests/test_source.py b/test/py/tests/test_source.py index e5ffdfe3fc..bbc311df6d 100644 --- a/test/py/tests/test_source.py +++ b/test/py/tests/test_source.py @@ -18,11 +18,20 @@ def test_source(u_boot_console): util.run_and_log(cons, (mkimage, '-f', its, fit)) cons.run_command(f'host load hostfs - $loadaddr {fit}') - assert '1' in cons.run_command('source') + assert '2' in cons.run_command('source') + assert '1' in cons.run_command('source :') assert '1' in cons.run_command('source :script-1') assert '2' in cons.run_command('source :script-2') assert 'Fail' in cons.run_command('source :not-a-script || echo Fail') + assert '2' in cons.run_command('source \\#') + assert '1' in cons.run_command('source \\#conf-1') + assert '2' in cons.run_command('source \\#conf-2') cons.run_command('fdt addr $loadaddr') + cons.run_command('fdt rm /configurations default') + assert '1' in cons.run_command('source') + assert 'Fail' in cons.run_command('source \\# || echo Fail') + cons.run_command('fdt rm /images default') assert 'Fail' in cons.run_command('source || echo Fail') + assert 'Fail' in cons.run_command('source \\# || echo Fail') From e93efaf9cc8e2b529c6184f5680640e669318616 Mon Sep 17 00:00:00 2001 From: Christian Gmeiner Date: Mon, 5 Dec 2022 12:10:40 +0100 Subject: [PATCH 362/424] arm: dts: ti: k3-am64-mcu: Add pinctrl Add the definition of the pinctrl for the MCU domain. Same as kernel commit 500e6dfbb465531150ac6e2ff0856dd357ddc8a4 Signed-off-by: Christian Gmeiner Reviewed-by: Nishanth Menon --- arch/arm/dts/k3-am64-mcu.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi index 59cc58f7d0..2bb5c9ff17 100644 --- a/arch/arm/dts/k3-am64-mcu.dtsi +++ b/arch/arm/dts/k3-am64-mcu.dtsi @@ -97,4 +97,12 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x4084000 0x00 0x84>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; }; From 6136c85ed04e715fe03e3df0dbd5ad54e46f046f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 6 Dec 2022 10:16:29 -0600 Subject: [PATCH 363/424] dts: synquacer: Drop CPU 'arm,armv8' compatibles 'arm,armv8' compatible is for software models only. so drop it from cpu nodes. Signed-off-by: Rob Herring --- arch/arm/dts/synquacer-sc2a11.dtsi | 48 +++++++++++++++--------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi index 1fe7d214b9..1f8cd9d257 100644 --- a/arch/arm/dts/synquacer-sc2a11.dtsi +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -41,168 +41,168 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4: cpu@200 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x200>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5: cpu@201 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x201>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6: cpu@300 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x300>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7: cpu@301 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x301>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU8: cpu@400 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x400>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU9: cpu@401 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x401>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU10: cpu@500 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x500>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU11: cpu@501 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x501>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU12: cpu@600 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x600>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU13: cpu@601 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x601>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU14: cpu@700 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x700>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU15: cpu@701 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x701>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU16: cpu@800 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x800>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU17: cpu@801 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x801>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU18: cpu@900 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x900>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU19: cpu@901 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x901>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU20: cpu@a00 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xa00>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU21: cpu@a01 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xa01>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU22: cpu@b00 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xb00>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU23: cpu@b01 { device_type = "cpu"; - compatible = "arm,cortex-a53","arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0xb01>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; From cc891c41f2c8a70351da69028df8d262004044e0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 6 Dec 2022 10:16:30 -0600 Subject: [PATCH 364/424] dts: synquacer: Use generic node names DT node names should follow generic names defined in the DT spec. These are also now checked by dtschema tools. Signed-off-by: Rob Herring --- arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 2 +- arch/arm/dts/synquacer-sc2a11-developerbox.dts | 2 +- arch/arm/dts/synquacer-sc2a11.dtsi | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index 7a56116d6f..6b85c05458 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -23,7 +23,7 @@ active_clk_edges; chipselect_num = <1>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox.dts b/arch/arm/dts/synquacer-sc2a11-developerbox.dts index 42b6cbbb82..c8087b99a7 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox.dts +++ b/arch/arm/dts/synquacer-sc2a11-developerbox.dts @@ -18,7 +18,7 @@ compatible = "gpio-keys"; interrupt-parent = <&exiu>; - power { + power-button { label = "Power Button"; linux,code = ; interrupts = ; diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi index 1f8cd9d257..0e1bc16454 100644 --- a/arch/arm/dts/synquacer-sc2a11.dtsi +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -344,7 +344,7 @@ interrupt-controller; interrupts = ; - its: gic-its@30020000 { + its: msi-controller@30020000 { compatible = "arm,gic-v3-its"; reg = <0x0 0x30020000 0x0 0x20000>; #msi-cells = <1>; @@ -361,7 +361,7 @@ ; // HYP }; - mmio-timer@2a810000 { + timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; #address-cells = <2>; @@ -398,7 +398,7 @@ clock-output-names = "apb_pclk"; }; - soc_uart0: uart@2a400000 { + soc_uart0: serial@2a400000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x2a400000 0x0 0x1000>; interrupts = ; @@ -406,7 +406,7 @@ clock-names = "uartclk", "apb_pclk"; }; - fuart: uart@51040000 { + fuart: serial@51040000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x51040000 0x0 0x1000>; interrupts = ; @@ -523,7 +523,7 @@ clock-output-names = "sd_sd4clk"; }; - sdhci: sdhci@52300000 { + sdhci: mmc@52300000 { compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0"; reg = <0 0x52300000 0x0 0x1000>; interrupts = , From 563f238b6714bbd150a2e96cb1d7434e1e9d0e49 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 6 Dec 2022 10:16:31 -0600 Subject: [PATCH 365/424] dts: synquacer: Fix "arm, armv7-timer-mem" node address sizes The "arm,armv7-timer-mem" schema defines the address sizes for child nodes to be 32-bit as there's no need for 64-bit offsets and sizes of the child 'frame' nodes. Signed-off-by: Rob Herring --- arch/arm/dts/synquacer-sc2a11.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi index 0e1bc16454..049afcb0af 100644 --- a/arch/arm/dts/synquacer-sc2a11.dtsi +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -364,13 +364,13 @@ timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - frame@2a830000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2a810000 0x30000>; + frame@20000 { frame-number = <0>; interrupts = ; - reg = <0x0 0x2a830000 0x0 0x10000>; + reg = <0x20000 0x10000>; }; }; From 00723684e4680446d13e054fae7ecd85306a373b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 6 Dec 2022 10:16:32 -0600 Subject: [PATCH 366/424] dts: synquacer: Fix idle-states 'entry-method' value The correct value for 'entry-method' in the idle-states binding is 'psci', not 'arm,psci'. It hasn't mattered because it isn't used by the OS. Signed-off-by: Rob Herring --- arch/arm/dts/synquacer-sc2a11.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi index 049afcb0af..0dd2969b5e 100644 --- a/arch/arm/dts/synquacer-sc2a11.dtsi +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -309,7 +309,7 @@ }; idle-states { - entry-method = "arm,psci"; + entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; From 499fe577c8011dd8a9184548c419db42aef079a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 3 Aug 2022 13:20:49 +0200 Subject: [PATCH 367/424] powerpc: dts: keymile: Deduplicate binman code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit kmcent2-u-boot.dtsi file contains copy of powerpc u-boot.dtsi binman file. So remove code duplication and replace it by including u-boot.dtsi file. Signed-off-by: Pali Rohár Reviewed-by: Christophe Leroy --- arch/powerpc/dts/kmcent2-u-boot.dtsi | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index 53bac5533f..d027762764 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -74,24 +74,6 @@ compatible = "fsl,pcie-t104x"; law_trgt_if = <0>; }; - - binman { - filename = "u-boot.bin"; - skip-at-start = ; - sort-by-offset; - pad-byte = <0xff>; - size = ; - - u-boot-with-ucode-ptr { - offset = ; - optional-ucode; - }; - - u-boot-dtb-with-ucode { - align = <256>; - }; - powerpc-mpc85xx-bootpg-resetvec { - offset = <(CFG_RESET_VECTOR_ADDRESS - 0xffc)>; - }; - }; }; + +#include "u-boot.dtsi" From 36ee37632c5c61ce5cd67b9b0f0ea3cd2280e5d2 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 8 Dec 2022 20:45:08 -0600 Subject: [PATCH 368/424] dts: synquacer: Drop unused and undocumented SPI properties 'active_clk_edges' and 'chipselect_num' SPI controller properties are unused in u-boot and Linux. They are also not documented in the binding. So drop them. Signed-off-by: Rob Herring Reviewed-by: Masahisa Kojima Acked-by: Ilias Apalodimas Acked-by: Jassi Brar --- arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index 6b85c05458..9f9837b33b 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -20,8 +20,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - active_clk_edges; - chipselect_num = <1>; flash@0 { #address-cells = <1>; From bd8851c5b4984ffb26f55872c4e086d91989bc9a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 8 Dec 2022 20:45:09 -0600 Subject: [PATCH 369/424] dts: synquacer: Drop unused and undocumented GPIO 'base' property The 'base' GPIO controller property is unused in u-boot and Linux. It is also not documented in the binding. So drop it. Signed-off-by: Rob Herring Reviewed-by: Masahisa Kojima Acked-by: Ilias Apalodimas Acked-by: Jassi Brar --- arch/arm/dts/synquacer-sc2a11.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/synquacer-sc2a11.dtsi b/arch/arm/dts/synquacer-sc2a11.dtsi index 0dd2969b5e..7ba1cd1bee 100644 --- a/arch/arm/dts/synquacer-sc2a11.dtsi +++ b/arch/arm/dts/synquacer-sc2a11.dtsi @@ -497,7 +497,6 @@ gpio-controller; #gpio-cells = <2>; clocks = <&clk_apb>; - base = <0>; }; exiu: interrupt-controller@510c0000 { From 1e91a0ea326f2005d34921c4bc37a35eeccad368 Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Fri, 9 Dec 2022 20:33:46 +0900 Subject: [PATCH 370/424] pinctrl: uniphier: add check if pins are valid The pinctrl datas of uniphier SoCs are the minimal subsets of kernel's one, and some tables has no data to save the footprint size. If the board dts tries to match a pin name on no pins defined SoC, the footprint magic code causes "Synchronous Abort". This checks if the 'pins' data is valid, and if empty, avoids the abort with the warning as follows: WARNING at drivers/pinctrl/uniphier/pinctrl-uniphier-core.c:36/uniphier_pinctrl_get_pins_count()! pinctrl_select_state_full: pinctrl_config_one: err=-38 Signed-off-by: Dai Okamura --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 631bb1f963..bdca3f2f71 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -33,6 +33,9 @@ static int uniphier_pinctrl_get_pins_count(struct udevice *dev) const struct uniphier_pinctrl_pin *pins = priv->socdata->pins; int pins_count = priv->socdata->pins_count; + if (WARN_ON(!pins_count)) + return 0; /* no table of pins */ + /* * We do not list all pins in the pin table to save memory footprint. * Report the max pin number + 1 to fake the framework. From ef75d482aa9d75d41305e5dddcbc8632f528e6f5 Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Fri, 9 Dec 2022 20:33:47 +0900 Subject: [PATCH 371/424] pinctrl: uniphier: add ethernet TX pin data for PXs3 PXs3 Ref boards need to change the strength of ethernet ports for stability, like LD20's one. This adds the table data and fixes the boot issue on PXs3 Ref board. Fixes: 0852033309 ("ARM: uniphier: sync with Linux 5.8-rc4") Signed-off-by: Dai Okamura --- .../pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 1fc7bdb5c8..8a8f1269bb 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Socionext Inc. + * Copyright (C) 2017-2021 Socionext Inc. * Author: Masahiro Yamada + * Author: Dai Okamura */ #include @@ -10,6 +11,21 @@ #include "pinctrl-uniphier.h" +static const struct uniphier_pinctrl_pin uniphier_pxs3_pins[] = { + UNIPHIER_PINCTRL_PIN(62, "RGMII0_TXCLK", 28, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(63, "RGMII0_TXD0", 29, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(64, "RGMII0_TXD1", 30, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(65, "RGMII0_TXD2", 31, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(66, "RGMII0_TXD3", 32, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(67, "RGMII0_TXCTL", 33, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(78, "RGMII1_TXCLK", 44, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(79, "RGMII1_TXD0", 45, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(80, "RGMII1_TXD1", 46, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(81, "RGMII1_TXD2", 47, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(82, "RGMII1_TXD3", 48, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(83, "RGMII1_TXCTL", 49, UNIPHIER_PIN_DRV_2BIT), +}; + static const unsigned emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38}; static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {39, 40, 41, 42}; @@ -121,6 +137,8 @@ static const char * const uniphier_pxs3_functions[] = { }; static struct uniphier_pinctrl_socdata uniphier_pxs3_pinctrl_socdata = { + .pins = uniphier_pxs3_pins, + .pins_count = ARRAY_SIZE(uniphier_pxs3_pins), .groups = uniphier_pxs3_groups, .groups_count = ARRAY_SIZE(uniphier_pxs3_groups), .functions = uniphier_pxs3_functions, From 872413bb0a03831ffe6f060b40cdb8bcc76f9867 Mon Sep 17 00:00:00 2001 From: Dai Okamura Date: Fri, 9 Dec 2022 20:33:48 +0900 Subject: [PATCH 372/424] arm: uniphier: use DM_TIMER of arm a9 global timer All uniphier v7 SoCs have cortex-a9 and use cortex-a9 global timer in a simple implementation. Now DM_TIMER of it is available on 35751c7f3f ("timer: sti: convert sti-timer to arm a9 global timer"), so let's switch to it. The old driver reads the lower 32bits of counter field and sets the prescaler as 50 with PERIPHCLK(=50MHz), so the global timer works as a 32-bit 1MHz timer. The DM_TIMER uses the whole 64bits with no prescaler, so the global timer works as a 64-bit PERIPHCLK timer. CONFIG_SYS_HZ_CLOCK is set as the default PERIPHCLK frequency, if there is no 'clocks' property in devicetree. Signed-off-by: Dai Okamura --- arch/arm/dts/uniphier-v7-u-boot.dtsi | 4 +++ arch/arm/mach-uniphier/Kconfig | 1 + arch/arm/mach-uniphier/arm32/Makefile | 2 -- arch/arm/mach-uniphier/arm32/timer.c | 39 --------------------------- configs/uniphier_ld4_sld8_defconfig | 2 ++ configs/uniphier_v7_defconfig | 2 ++ include/configs/uniphier.h | 3 +-- 7 files changed, 10 insertions(+), 43 deletions(-) delete mode 100644 arch/arm/mach-uniphier/arm32/timer.c diff --git a/arch/arm/dts/uniphier-v7-u-boot.dtsi b/arch/arm/dts/uniphier-v7-u-boot.dtsi index 9459bf0377..603b33dd2b 100644 --- a/arch/arm/dts/uniphier-v7-u-boot.dtsi +++ b/arch/arm/dts/uniphier-v7-u-boot.dtsi @@ -2,6 +2,10 @@ soc { u-boot,dm-pre-reloc; + timer@60000200 { + u-boot,dm-pre-reloc; + }; + serial@54006800 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 3a8eee7b84..c570fb3294 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -12,6 +12,7 @@ config ARCH_UNIPHIER_V7_MULTI select ARMV7_NONSEC select CPU_V7A select CPU_V7_HAS_NONSEC + select ARM_GLOBAL_TIMER if TIMER config ARCH_UNIPHIER_V8_MULTI bool "UniPhier V8 SoCs" diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index 3cd00b7e5e..b41aba7e29 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -8,5 +8,3 @@ obj-y += late_lowlevel_init.o obj-y += cache-uniphier.o obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o endif - -obj-y += timer.o diff --git a/arch/arm/mach-uniphier/arm32/timer.c b/arch/arm/mach-uniphier/arm32/timer.c deleted file mode 100644 index 58247c2738..0000000000 --- a/arch/arm/mach-uniphier/arm32/timer.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012-2015 Masahiro Yamada - */ - -#include -#include -#include - -#include "arm-mpcore.h" - -#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */ -#define PRESCALER ((PERIPHCLK) / (CFG_SYS_TIMER_RATE) - 1) - -static void *get_global_timer_base(void) -{ - void *val; - - asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory"); - - return val + GLOBAL_TIMER_OFFSET; -} - -unsigned long timer_read_counter(void) -{ - /* - * ARM 64bit Global Timer is too much for our purpose. - * We use only lower 32 bit of the timer counter. - */ - return readl(get_global_timer_base() + GTIMER_CNT_L); -} - -int timer_init(void) -{ - /* enable timer */ - writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL); - - return 0; -} diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index b361e3f403..b11dea593a 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_SYS_MONITOR_LEN=2097152 +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 765d42a3e6..d626968c76 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -13,6 +13,8 @@ CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 CONFIG_SYS_MONITOR_LEN=2097152 +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index ecf0d2ac44..0a14d0448c 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -36,8 +36,7 @@ BOOT_TARGET_DEVICE_USB(func) #if !defined(CONFIG_ARM64) -/* Time clock 1MHz */ -#define CFG_SYS_TIMER_RATE 1000000 +#define CFG_SYS_HZ_CLOCK 50000000 #endif #define CFG_SYS_NAND_REGS_BASE 0x68100000 From fcb624be476e76d5043377a0f0a3c3589bfb4b5f Mon Sep 17 00:00:00 2001 From: Sergei Antonov Date: Fri, 9 Dec 2022 19:15:30 +0300 Subject: [PATCH 373/424] rtc: add ht1380 driver Support Holtek HT1380/HT1381 Serial Timekeeper Chip. It provides seconds , minutes, hours, day of the week, date, month and year information. Datasheet: https://www.holtek.com.tw/documents/10179/11842/ht1380_1v130.pdf Signed-off-by: Sergei Antonov Reviewed-by: Simon Glass --- configs/sandbox_defconfig | 1 + drivers/rtc/Kconfig | 9 ++ drivers/rtc/Makefile | 1 + drivers/rtc/ht1380.c | 329 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 340 insertions(+) create mode 100644 drivers/rtc/ht1380.c diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 404e4a3324..f9c996b429 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -334,3 +334,4 @@ CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_IPV6=y +CONFIG_RTC_HT1380=y diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index b698722569..35b6ed4d7c 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -260,4 +260,13 @@ config RTC_ZYNQMP Say "yes" here to support the on chip real time clock present on Xilinx ZynqMP SoC. +config RTC_HT1380 + bool "Enable Holtek HT1380/HT1381 RTC driver" + depends on DM_RTC && DM_GPIO + help + Say "yes" here to get support for Holtek HT1380/HT1381 + Serial Timekeeper IC which provides seconds, minutes, hours, + day of the week, date, month and year information. It is to be + connected via 3 GPIO pins which work as reset, clock, and data. + endmenu diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2089086551..acfd130bbc 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o +obj-$(CONFIG_RTC_HT1380) += ht1380.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c new file mode 100644 index 0000000000..85fcee3e71 --- /dev/null +++ b/drivers/rtc/ht1380.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Holtek HT1380/HT1381 Serial Timekeeper Chip + * + * Communication with the chip is vendor-specific. + * It is done via 3 GPIO pins: reset, clock, and data. + * Describe in .dts this way: + * + * rtc { + * compatible = "holtek,ht1380"; + * rst-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; + * clk-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; + * dat-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>; + * }; + * + */ + +#include +#include +#include +#include +#include +#include + +struct ht1380_priv { + struct gpio_desc rst_desc; + struct gpio_desc clk_desc; + struct gpio_desc dat_desc; +}; + +enum registers { + SEC, + MIN, + HOUR, + MDAY, + MONTH, + WDAY, + YEAR, + WP, + N_REGS +}; + +enum hour_mode { + AMPM_MODE = 0x80, /* RTC is in AM/PM mode */ + PM_NOW = 0x20, /* set if PM, clear if AM */ +}; + +static const int BURST = 0xbe; +static const int READ = 1; + +static void ht1380_half_period_delay(void) +{ + /* + * Delay for half a period. 1 us complies with the 500 KHz maximum + * input serial clock limit given by the datasheet. + */ + udelay(1); +} + +static int ht1380_send_byte(struct ht1380_priv *priv, int byte) +{ + int ret; + + for (int bit = 0; bit < 8; bit++) { + ret = dm_gpio_set_value(&priv->dat_desc, byte >> bit & 1); + if (ret) + break; + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 1); + if (ret) + break; + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + break; + } + + return ret; +} + +/* + * Leave reset state. The transfer operation can then be started. + */ +static int ht1380_reset_off(struct ht1380_priv *priv) +{ + const unsigned int T_CC = 4; /* us, Reset to Clock Setup */ + int ret; + + /* + * Leave RESET state. + * Make sure we make the minimal delay required by the datasheet. + */ + ret = dm_gpio_set_value(&priv->rst_desc, 0); + udelay(T_CC); + + return ret; +} + +/* + * Enter reset state. Completes the transfer operation. + */ +static int ht1380_reset_on(struct ht1380_priv *priv) +{ + const unsigned int T_CWH = 4; /* us, Reset Inactive Time */ + int ret; + + /* + * Enter RESET state. + * Make sure we make the minimal delay required by the datasheet. + */ + ret = dm_gpio_set_value(&priv->rst_desc, 1); + udelay(T_CWH); + + return ret; +} + +static int ht1380_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + int ret, i, bit, reg[N_REGS]; + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + return ret; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT); + if (ret) + return ret; + + ret = ht1380_reset_off(priv); + if (ret) + goto exit; + + ret = ht1380_send_byte(priv, BURST + READ); + if (ret) + goto exit; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_IN); + if (ret) + goto exit; + + for (i = 0; i < N_REGS; i++) { + reg[i] = 0; + + for (bit = 0; bit < 8; bit++) { + ht1380_half_period_delay(); + + ret = dm_gpio_set_value(&priv->clk_desc, 1); + if (ret) + goto exit; + ht1380_half_period_delay(); + + reg[i] |= dm_gpio_get_value(&priv->dat_desc) << bit; + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + goto exit; + } + } + + ret = -EINVAL; + + /* Correctness check: some bits are always zero */ + if (reg[MIN] & 0x80 || reg[HOUR] & 0x40 || reg[MDAY] & 0xc0 || + reg[MONTH] & 0xe0 || reg[WDAY] & 0xf8 || reg[WP] & 0x7f) + goto exit; + + /* Correctness check: some registers are always non-zero */ + if (!reg[MDAY] || !reg[MONTH] || !reg[WDAY]) + goto exit; + + tm->tm_sec = bcd2bin(reg[SEC]); + tm->tm_min = bcd2bin(reg[MIN]); + if (reg[HOUR] & AMPM_MODE) { + /* AM-PM Mode, range is 01-12 */ + tm->tm_hour = bcd2bin(reg[HOUR] & 0x1f) % 12; + if (reg[HOUR] & PM_NOW) { + /* it is PM (otherwise AM) */ + tm->tm_hour += 12; + } + } else { + /* 24-hour Mode, range is 0-23 */ + tm->tm_hour = bcd2bin(reg[HOUR]); + } + tm->tm_mday = bcd2bin(reg[MDAY]); + tm->tm_mon = bcd2bin(reg[MONTH]); + tm->tm_year = 2000 + bcd2bin(reg[YEAR]); + tm->tm_wday = bcd2bin(reg[WDAY]) - 1; + tm->tm_yday = 0; + tm->tm_isdst = 0; + + ret = 0; + +exit: + ht1380_reset_on(priv); + + return ret; +} + +static int ht1380_write_protection_off(struct ht1380_priv *priv) +{ + int ret; + const int PROTECT = 0x8e; + + ret = ht1380_reset_off(priv); + if (ret) + return ret; + + ret = ht1380_send_byte(priv, PROTECT); + if (ret) + return ret; + ret = ht1380_send_byte(priv, 0); /* WP bit is 0 */ + if (ret) + return ret; + + return ht1380_reset_on(priv); +} + +static int ht1380_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + int ret, i, reg[N_REGS]; + + ret = dm_gpio_set_value(&priv->clk_desc, 0); + if (ret) + return ret; + + ret = dm_gpio_set_dir_flags(&priv->dat_desc, GPIOD_IS_OUT); + if (ret) + goto exit; + + ret = ht1380_write_protection_off(priv); + if (ret) + goto exit; + + reg[SEC] = bin2bcd(tm->tm_sec); + reg[MIN] = bin2bcd(tm->tm_min); + reg[HOUR] = bin2bcd(tm->tm_hour); + reg[MDAY] = bin2bcd(tm->tm_mday); + reg[MONTH] = bin2bcd(tm->tm_mon); + reg[WDAY] = bin2bcd(tm->tm_wday) + 1; + reg[YEAR] = bin2bcd(tm->tm_year - 2000); + reg[WP] = 0x80; /* WP bit is 1 */ + + ret = ht1380_reset_off(priv); + if (ret) + goto exit; + + ret = ht1380_send_byte(priv, BURST); + for (i = 0; i < N_REGS && ret; i++) + ret = ht1380_send_byte(priv, reg[i]); + +exit: + ht1380_reset_on(priv); + + return ret; +} + +static int ht1380_probe(struct udevice *dev) +{ + int ret; + struct ht1380_priv *priv; + + priv = dev_get_priv(dev); + if (!priv) + return -EINVAL; + + ret = gpio_request_by_name(dev, "rst-gpios", 0, + &priv->rst_desc, GPIOD_IS_OUT); + if (ret) + goto fail_rst; + + ret = gpio_request_by_name(dev, "clk-gpios", 0, + &priv->clk_desc, GPIOD_IS_OUT); + if (ret) + goto fail_clk; + + ret = gpio_request_by_name(dev, "dat-gpios", 0, + &priv->dat_desc, 0); + if (ret) + goto fail_dat; + + ret = ht1380_reset_on(priv); + if (ret) + goto fail; + + return 0; + +fail: + dm_gpio_free(dev, &priv->dat_desc); +fail_dat: + dm_gpio_free(dev, &priv->clk_desc); +fail_clk: + dm_gpio_free(dev, &priv->rst_desc); +fail_rst: + return ret; +} + +static int ht1380_remove(struct udevice *dev) +{ + struct ht1380_priv *priv = dev_get_priv(dev); + + dm_gpio_free(dev, &priv->rst_desc); + dm_gpio_free(dev, &priv->clk_desc); + dm_gpio_free(dev, &priv->dat_desc); + + return 0; +} + +static const struct rtc_ops ht1380_rtc_ops = { + .get = ht1380_rtc_get, + .set = ht1380_rtc_set, +}; + +static const struct udevice_id ht1380_rtc_ids[] = { + { .compatible = "holtek,ht1380" }, + { } +}; + +U_BOOT_DRIVER(rtc_ht1380) = { + .name = "rtc-ht1380", + .id = UCLASS_RTC, + .probe = ht1380_probe, + .remove = ht1380_remove, + .of_match = ht1380_rtc_ids, + .ops = &ht1380_rtc_ops, + .priv_auto = sizeof(struct ht1380_priv), +}; From 59440d83d38bfed31931d11aa06a3fb56acbd2f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 11 Dec 2022 00:27:44 +0100 Subject: [PATCH 374/424] serial: Do not write additional \r before \n for dm_serial drivers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit serial-uclass.c code already puts \r before \n for all dm_serial drivers. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- drivers/serial/serial_lpuart.c | 3 --- drivers/serial/serial_mpc8xx.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index ff576da516..07941c29ed 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -349,9 +349,6 @@ static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat, struct lpuart_fsl_reg32 *base = plat->reg; u32 stat; - if (c == '\n') - serial_putc('\r'); - while (true) { lpuart_read32(plat->flags, &base->stat, &stat); diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c index aeae6ae6cd..808a40f503 100644 --- a/drivers/serial/serial_mpc8xx.c +++ b/drivers/serial/serial_mpc8xx.c @@ -176,9 +176,6 @@ static int serial_mpc8xx_putc(struct udevice *dev, const char c) cpm8xx_t __iomem *cpmp = &(im->im_cpm); struct serialbuffer __iomem *rtx; - if (c == '\n') - serial_mpc8xx_putc(dev, '\r'); - rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; /* Wait for last character to go. */ From 1138bbe05e617034cf542ac0bc13cfa804cb09f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 11 Dec 2022 00:31:21 +0100 Subject: [PATCH 375/424] serial: Use -EAGAIN in getc and putc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit U-Boot serial code already handles -EAGAIN value from getc and putc callbacks. So change drivers code to return -EAGAIN when HW is busy instead of doing its own busy loop and waiting until HW is ready. Signed-off-by: Pali Rohár --- drivers/serial/serial_arc.c | 8 +++---- drivers/serial/serial_lpuart.c | 36 ++++++++++++----------------- drivers/serial/serial_mpc8xx.c | 12 ++++------ drivers/serial/serial_mvebu_a3700.c | 8 +++---- 4 files changed, 28 insertions(+), 36 deletions(-) diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index b2d95bdbe1..c2fc8a901e 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -53,8 +53,8 @@ static int arc_serial_putc(struct udevice *dev, const char c) struct arc_serial_plat *plat = dev_get_plat(dev); struct arc_serial_regs *const regs = plat->reg; - while (!(readb(®s->status) & UART_TXEMPTY)) - ; + if (!(readb(®s->status) & UART_TXEMPTY)) + return -EAGAIN; writeb(c, ®s->data); @@ -83,8 +83,8 @@ static int arc_serial_getc(struct udevice *dev) struct arc_serial_plat *plat = dev_get_plat(dev); struct arc_serial_regs *const regs = plat->reg; - while (!arc_serial_tstc(regs)) - ; + if (!arc_serial_tstc(regs)) + return -EAGAIN; /* Check for overflow errors */ if (readb(®s->status) & UART_OVERFLOW_ERR) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 07941c29ed..51e66abdbc 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -168,23 +168,24 @@ static void _lpuart_serial_setbrg(struct udevice *dev, static int _lpuart_serial_getc(struct lpuart_serial_plat *plat) { struct lpuart_fsl *base = plat->reg; - while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) - schedule(); + if (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR))) + return -EAGAIN; barrier(); return __raw_readb(&base->ud); } -static void _lpuart_serial_putc(struct lpuart_serial_plat *plat, +static int _lpuart_serial_putc(struct lpuart_serial_plat *plat, const char c) { struct lpuart_fsl *base = plat->reg; - while (!(__raw_readb(&base->us1) & US1_TDRE)) - schedule(); + if (!(__raw_readb(&base->us1) & US1_TDRE)) + return -EAGAIN; __raw_writeb(c, &base->ud); + return 0; } /* Test whether a character is in the RX buffer */ @@ -328,10 +329,9 @@ static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat) u32 stat, val; lpuart_read32(plat->flags, &base->stat, &stat); - while ((stat & STAT_RDRF) == 0) { + if ((stat & STAT_RDRF) == 0) { lpuart_write32(plat->flags, &base->stat, STAT_FLAGS); - schedule(); - lpuart_read32(plat->flags, &base->stat, &stat); + return -EAGAIN; } lpuart_read32(plat->flags, &base->data, &val); @@ -343,22 +343,18 @@ static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat) return val & 0x3ff; } -static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat, +static int _lpuart32_serial_putc(struct lpuart_serial_plat *plat, const char c) { struct lpuart_fsl_reg32 *base = plat->reg; u32 stat; - while (true) { - lpuart_read32(plat->flags, &base->stat, &stat); - - if ((stat & STAT_TDRE)) - break; - - schedule(); - } + lpuart_read32(plat->flags, &base->stat, &stat); + if (!(stat & STAT_TDRE)) + return -EAGAIN; lpuart_write32(plat->flags, &base->data, c); + return 0; } /* Test whether a character is in the RX buffer */ @@ -453,11 +449,9 @@ static int lpuart_serial_putc(struct udevice *dev, const char c) struct lpuart_serial_plat *plat = dev_get_plat(dev); if (is_lpuart32(dev)) - _lpuart32_serial_putc(plat, c); - else - _lpuart_serial_putc(plat, c); + return _lpuart32_serial_putc(plat, c); - return 0; + return _lpuart_serial_putc(plat, c); } static int lpuart_serial_pending(struct udevice *dev, bool input) diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c index 808a40f503..b8d6a81b65 100644 --- a/drivers/serial/serial_mpc8xx.c +++ b/drivers/serial/serial_mpc8xx.c @@ -178,14 +178,13 @@ static int serial_mpc8xx_putc(struct udevice *dev, const char c) rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; - /* Wait for last character to go. */ + if (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY) + return -EAGAIN; + out_8(&rtx->txbuf, c); out_be16(&rtx->txbd.cbd_datlen, 1); setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY); - while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY) - schedule(); - return 0; } @@ -199,9 +198,8 @@ static int serial_mpc8xx_getc(struct udevice *dev) rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; - /* Wait for character to show up. */ - while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY) - schedule(); + if (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY) + return -EAGAIN; /* the characters are read one by one, * use the rxindex to know the next char to deliver diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c index 0fcd7e88ac..b2017c6455 100644 --- a/drivers/serial/serial_mvebu_a3700.c +++ b/drivers/serial/serial_mvebu_a3700.c @@ -40,8 +40,8 @@ static int mvebu_serial_putc(struct udevice *dev, const char ch) struct mvebu_plat *plat = dev_get_plat(dev); void __iomem *base = plat->base; - while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) - ; + if (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL) + return -EAGAIN; writel(ch, base + UART_TX_REG); @@ -53,8 +53,8 @@ static int mvebu_serial_getc(struct udevice *dev) struct mvebu_plat *plat = dev_get_plat(dev); void __iomem *base = plat->base; - while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)) - ; + if (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)) + return -EAGAIN; return readl(base + UART_RX_REG) & 0xff; } From 357c352cdccbd09a92924b1a5c0cb841a18aa832 Mon Sep 17 00:00:00 2001 From: "Lokanathan, Raaj" Date: Sun, 11 Dec 2022 23:37:42 +0800 Subject: [PATCH 376/424] Add CONFIG_SYS_NAND_SELF_INIT to Kconfig for NAND DENALI driver Add the CONFIG_SYS_NAND_SELF_INIT to the Kconfig to follow the changes from mainline. Signed-off-by: Lokanathan, Raaj Signed-off-by: Jit Loon Lim --- drivers/mtd/nand/raw/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1e4e5c9206..f8b79e5456 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -197,6 +197,7 @@ config NAND_DENALI config NAND_DENALI_DT bool "Support Denali NAND controller as a DT device" select NAND_DENALI + select SPL_SYS_NAND_SELF_INIT depends on OF_CONTROL && DM_MTD help Enable the driver for NAND flash on platforms using a Denali NAND From 9f393a2d7af89fa1be076e79091e5481f96c3c3f Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Tue, 13 Dec 2022 11:57:34 +0530 Subject: [PATCH 377/424] board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte EEPROM detection logic in ti_i2c_eeprom_get() involves figuring out whether addressing is 1-byte or 2-byte. There are currently different behaviours seen across boards as documented in commit bf6376642fe8 ("board: ti: common: board_detect: Fix EEPROM read quirk"). Adding to the list, we see that there are 2-byte EEPROMs that read properly with 1-byte addressing with no offset. For ti_i2c_eeprom_am6_get where eeprom parse operation is dynamic, the earlier commit d2ab2a2bafd5 ("board: ti: common: board_detect: Fix EEPROM read quirk for AM6 style data") tried to resolve this by running ti_i2c_eeprom_get() twice. However this commit along with its former commit fails on J7 platforms where EEPROM successfully return back the header on 1-byte addressing and continues to do so until an offset is introduced. So the second read incorrectly determines the EEPROM as 1-byte addressing. A more generic solution is introduced here to solve this issue: 1-byte read without offset and 1-byte read with offset. If both passes, it follows 1-byte addressing else we proceed with 2-byte addressing check. Tested on J721E, J7200, DRA7xx, AM64x Signed-off-by: Neha Malcom Francis Fixes: d2ab2a2bafd5 (board: ti: common: board_detect: Fix EEPROM read quirk for AM6 style data) Fixes: bf6376642fe8 (board: ti: common: board_detect: Fix EEPROM read quirk) Tested-By: Matwey V. Kornilov --- board/ti/common/board_detect.c | 46 +++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/board/ti/common/board_detect.c b/board/ti/common/board_detect.c index c37629fe8a..9a53884c98 100644 --- a/board/ti/common/board_detect.c +++ b/board/ti/common/board_detect.c @@ -87,6 +87,8 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, u32 header, u32 size, uint8_t *ep) { int rc; + uint8_t offset_test; + bool one_byte_addressing = true; #if CONFIG_IS_ENABLED(DM_I2C) struct udevice *dev; @@ -114,8 +116,23 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, */ (void)dm_i2c_read(dev, 0, ep, size); + if (*((u32 *)ep) != header) + one_byte_addressing = false; + + /* + * Handle case of bad 2 byte eeproms that responds to 1 byte addressing + * but gets stuck in const addressing when read requests are performed + * on offsets. We perform an offset test to make sure it is not a 2 byte + * eeprom that works with 1 byte addressing but just without an offset + */ + + rc = dm_i2c_read(dev, 0x1, &offset_test, sizeof(offset_test)); + + if (*((u32 *)ep) != (header & 0xFF)) + one_byte_addressing = false; + /* Corrupted data??? */ - if (*((u32 *)ep) != header) { + if (!one_byte_addressing) { /* * read the eeprom header using i2c again, but use only a * 2 byte address (some newer boards need this..) @@ -151,8 +168,23 @@ static int __maybe_unused ti_i2c_eeprom_get(int bus_addr, int dev_addr, */ (void)i2c_read(dev_addr, 0x0, byte, ep, size); + if (*((u32 *)ep) != header) + one_byte_addressing = false; + + /* + * Handle case of bad 2 byte eeproms that responds to 1 byte addressing + * but gets stuck in const addressing when read requests are performed + * on offsets. We perform an offset test to make sure it is not a 2 byte + * eeprom that works with 1 byte addressing but just without an offset + */ + + rc = i2c_read(dev_addr, 0x1, byte, &offset_test, sizeof(offset_test)); + + if (*((u32 *)ep) != (header & 0xFF)) + one_byte_addressing = false; + /* Corrupted data??? */ - if (*((u32 *)ep) != header) { + if (!one_byte_addressing) { /* * read the eeprom header using i2c again, but use only a * 2 byte address (some newer boards need this..) @@ -444,16 +476,6 @@ int __maybe_unused ti_i2c_eeprom_am6_get(int bus_addr, int dev_addr, if (rc) return rc; - /* - * Handle case of bad 2 byte eeproms that responds to 1 byte addressing - * but gets stuck in const addressing when read requests are performed - * on offsets. We re-read the board ID to ensure we have sane data back - */ - rc = ti_i2c_eeprom_get(bus_addr, dev_addr, TI_EEPROM_HEADER_MAGIC, - sizeof(board_id), (uint8_t *)&board_id); - if (rc) - return rc; - if (board_id.header.id != TI_AM6_EEPROM_RECORD_BOARD_ID) { pr_err("%s: Invalid board ID record!\n", __func__); return -EINVAL; From bfd4e660dec103a69e7a6dd9f856581ba6e57954 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Wed, 14 Dec 2022 11:30:07 +0100 Subject: [PATCH 378/424] board/pg_wcom: rework defconfig Switch off SCSI related config options to get rid of the board removal warning. We don't use this interface. Also disable UBIFS to decrease the image size, as this is also not used. Signed-off-by: Holger Brunck --- configs/pg_wcom_expu1_defconfig | 6 ++++-- configs/pg_wcom_expu1_update_defconfig | 6 ++++-- configs/pg_wcom_seli8_defconfig | 6 ++++-- configs/pg_wcom_seli8_update_defconfig | 6 ++++-- 4 files changed, 16 insertions(+), 8 deletions(-) diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index b7c0b0d1e8..acbef25d04 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_CLK_FREQ=66666666 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60060000 -CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_COMMON_ETH_INIT=y @@ -62,6 +61,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set CONFIG_OF_CONTROL=y CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_OVERWRITE=y @@ -73,6 +73,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y +# CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 @@ -98,8 +99,9 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_QE_FW_ADDR=0x60020000 -CONFIG_SCSI_AHCI_PLAT=y +# CONFIG_SCSI is not set CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_POST=y +CONFIG_LZO=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index a5193cb463..3d9581abd6 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60220000 -CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_COMMON_ETH_INIT=y @@ -60,6 +59,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set CONFIG_OF_CONTROL=y CONFIG_ENV_SOURCE_FILE="pg-wcom-expu1" CONFIG_ENV_OVERWRITE=y @@ -71,6 +71,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="EXPU1" CONFIG_VERSION_VARIABLE=y +# CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 @@ -96,8 +97,9 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_QE_FW_ADDR=0x60020000 -CONFIG_SCSI_AHCI_PLAT=y +# CONFIG_SCSI is not set CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_POST=y +CONFIG_LZO=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 1b9e0b6c91..0d7299efad 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -17,7 +17,6 @@ CONFIG_SYS_CLK_FREQ=66666666 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60060000 -CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_COMMON_ETH_INIT=y @@ -62,6 +61,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set CONFIG_OF_CONTROL=y CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_OVERWRITE=y @@ -73,6 +73,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y +# CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 @@ -98,8 +99,9 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_QE_FW_ADDR=0x60020000 -CONFIG_SCSI_AHCI_PLAT=y +# CONFIG_SCSI is not set CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_POST=y +CONFIG_LZO=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index c193f7bb40..d677b13a59 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -16,7 +16,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020 # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_ENV_ADDR=0x60220000 -CONFIG_AHCI=y # CONFIG_DEEP_SLEEP is not set CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_KM_COMMON_ETH_INIT=y @@ -60,6 +59,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=60000000.nor,nand0=68000000.flash" CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),128k(redenvred),128k(redenv),1m(redu-boot),-(ubi0);68000000.flash:-(ubi1)" CONFIG_CMD_UBI=y +# CONFIG_CMD_UBIFS is not set CONFIG_OF_CONTROL=y CONFIG_ENV_SOURCE_FILE="pg-wcom-seli8" CONFIG_ENV_OVERWRITE=y @@ -71,6 +71,7 @@ CONFIG_ETHPRIME="ethernet@2d90000" CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="SELI8" CONFIG_VERSION_VARIABLE=y +# CONFIG_SCSI_AHCI is not set CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DDR_CLK_FREQ=50000000 @@ -96,8 +97,9 @@ CONFIG_PHY_GIGE=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_QE_FW_ADDR=0x60020000 -CONFIG_SCSI_AHCI_PLAT=y +# CONFIG_SCSI is not set CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y CONFIG_POST=y +CONFIG_LZO=y From 5ec6cbcc7fb9604fd70587215123b77fdc326032 Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Sun, 18 Dec 2022 12:20:49 +0000 Subject: [PATCH 379/424] arm: s5p4418: dm_serial: add driver source code Add dm_serial driver source code for S5P4418 SOC. Extend the "arm,pl011" driver by init of UART-clock and UART-reset. Signed-off-by: Stefan Bosch --- MAINTAINERS | 1 + drivers/serial/serial_s5p4418_pl011.c | 94 +++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 drivers/serial/serial_s5p4418_pl011.c diff --git a/MAINTAINERS b/MAINTAINERS index 3fc4cd0f12..5f9636f4e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -436,6 +436,7 @@ F: drivers/gpio/nx_gpio.c F: drivers/i2c/nx_i2c.c F: drivers/mmc/nexell_dw_mmc_dm.c F: drivers/pinctrl/nexell/ +F: drivers/serial/serial_s5p4418_pl011.c F: drivers/video/nexell/ F: drivers/video/nexell_display.c F: include/configs/s5p4418_nanopi2.h diff --git a/drivers/serial/serial_s5p4418_pl011.c b/drivers/serial/serial_s5p4418_pl011.c new file mode 100644 index 0000000000..e4492e662e --- /dev/null +++ b/drivers/serial/serial_s5p4418_pl011.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Stefan Bosch + */ + +#include +#include +#include +#include +#include + +#include +#include +#include "serial_pl01x_internal.h" + +int s5p4418_pl011_serial_probe(struct udevice *dev) +{ + struct pl01x_serial_plat *plat = dev_get_plat(dev); + struct clk *nx_clk; + ulong rate_act; + char uart_clk_name[10]; + int uart_num = -1; + int rst_id, ret; + + if (!plat->skip_init) { + uart_num = dev->seq_; + rst_id = RESET_ID_UART0 + uart_num; + + if (uart_num < 0 || rst_id > RESET_ID_UART5) { + /* invalid UART-number */ + debug("%s: sequence/uart number %d is invalid!\n", __func__, uart_num); + return -ENODEV; + } + + sprintf(uart_clk_name, "nx-uart.%d", uart_num); + nx_clk = clk_get(uart_clk_name); + if (!nx_clk) { + debug("%s: clk_get('%s') failed!\n", __func__, uart_clk_name); + return -ENODEV; + } + + /* wait to make sure all pending characters have been sent */ + mdelay(100); + } + + /* + * Note: Unless !plat->skip_init, the UART is disabled here, so printf() + * or debug() must not be used until pl01x_serial_setbrg() has been called + * (enables the UART). Otherwise u-boot is hanging! + */ + ret = pl01x_serial_probe(dev); + if (ret) + return ret; + + if (!plat->skip_init) { + /* do reset UART */ + nx_rstcon_setrst(rst_id, RSTCON_ASSERT); + udelay(10); + nx_rstcon_setrst(rst_id, RSTCON_NEGATE); + udelay(10); + clk_disable(nx_clk); + + rate_act = clk_set_rate(nx_clk, plat->clock); + clk_enable(nx_clk); + + plat->clock = rate_act; + } + + return 0; +} + +static const struct dm_serial_ops s5p4418_pl011_serial_ops = { + .putc = pl01x_serial_putc, + .pending = pl01x_serial_pending, + .getc = pl01x_serial_getc, + .setbrg = pl01x_serial_setbrg, +}; + +static const struct udevice_id s5p4418_pl011_serial_id[] = { + {.compatible = "nexell,s5p4418-pl011", .data = TYPE_PL011}, + {} +}; + +U_BOOT_DRIVER(s5p4418_pl011_uart) = { + .name = "s5p4418_pl011", + .id = UCLASS_SERIAL, + .of_match = of_match_ptr(s5p4418_pl011_serial_id), + .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat), + .plat_auto = sizeof(struct pl01x_serial_plat), + .probe = s5p4418_pl011_serial_probe, + .ops = &s5p4418_pl011_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto = sizeof(struct pl01x_priv), +}; From c8ba27f7603df729cffcb656112fdf3ba0f8a20c Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Sun, 18 Dec 2022 12:24:33 +0000 Subject: [PATCH 380/424] arm: s5p4418: dm_serial: add uarts to dts Add S5P4418 UARTs and appropriate pinctrl to dts. Add UART to s5p4418-nanopi2.dts. Signed-off-by: Stefan Bosch --- arch/arm/dts/s5p4418-nanopi2.dts | 6 +++ arch/arm/dts/s5p4418-pinctrl.dtsi | 71 +++++++++++++++++++++++++++++++ arch/arm/dts/s5p4418.dtsi | 40 +++++++++++++++++ 3 files changed, 117 insertions(+) diff --git a/arch/arm/dts/s5p4418-nanopi2.dts b/arch/arm/dts/s5p4418-nanopi2.dts index 4deaf10a1c..42251e0a05 100644 --- a/arch/arm/dts/s5p4418-nanopi2.dts +++ b/arch/arm/dts/s5p4418-nanopi2.dts @@ -25,6 +25,7 @@ i2c0 = "/i2c@c00a4000"; i2c1 = "/i2c@c00a5000"; i2c2 = "/i2c@c00a6000"; + serial0 = "/uart@c00a1000"; }; mmc0:mmc@c0062000 { @@ -107,4 +108,9 @@ }; }; }; + + uart0:uart@c00a1000 { + skip-init; + status = "okay"; + }; }; diff --git a/arch/arm/dts/s5p4418-pinctrl.dtsi b/arch/arm/dts/s5p4418-pinctrl.dtsi index a7e1c2c381..0768d80fc9 100644 --- a/arch/arm/dts/s5p4418-pinctrl.dtsi +++ b/arch/arm/dts/s5p4418-pinctrl.dtsi @@ -132,4 +132,75 @@ pinctrl@C0010000 { pin-pull = <2>; pin-strength = <0>; }; + + /* UART */ + uart0_rx:uart0-rx { + pins = "gpiod-14"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart0_tx:uart0-tx { + pins = "gpiod-18"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart1_rx:uart1-rx { + pins = "gpiod-15"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart1_tx:uart1-tx { + pins = "gpiod-19"; + pin-function = <2>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart2_rx:uart2-rx { + pins = "gpiod-16"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart2_tx:uart2-tx { + pins = "gpiod-20"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart3_rx:uart3-rx { + pins = "gpiod-17"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart3_tx:uart3-tx { + pins = "gpiod-21"; + pin-function = <1>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart4_rx:uart4-rx { + pins = "gpiob-28"; + pin-function = <3>; + pin-pull = <2>; + pin-strength = <0>; + }; + + uart4_tx:uart4-tx { + pins = "gpiob-29"; + pin-function = <3>; + pin-pull = <2>; + pin-strength = <0>; + }; }; diff --git a/arch/arm/dts/s5p4418.dtsi b/arch/arm/dts/s5p4418.dtsi index a4d1a1bd03..3027cd4bb9 100644 --- a/arch/arm/dts/s5p4418.dtsi +++ b/arch/arm/dts/s5p4418.dtsi @@ -167,4 +167,44 @@ reg = <0xc0010000 0xf000>; u-boot,dm-pre-reloc; }; + + uart0:uart@c00a1000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a1000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_rx>, <&uart0_tx>; + status = "disabled"; + }; + + uart1:uart@c00a0000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a0000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_rx>, <&uart1_tx>; + status = "disabled"; + }; + + uart2:uart@c00a2000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a2000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_rx>, <&uart2_tx>; + status = "disabled"; + }; + + uart3:uart@c00a3000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc00a3000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_rx>, <&uart3_tx>; + status = "disabled"; + }; + + uart4:uart@c006d000 { + compatible = "nexell,s5p4418-pl011", "arm,primecell"; + reg = <0xc006d000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_rx>, <&uart4_tx>; + status = "disabled"; + }; }; From 5745de2c9d4beec60ffd6aa74beef9e4ac415ba5 Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Sun, 18 Dec 2022 12:25:33 +0000 Subject: [PATCH 381/424] arm: s5p4418: dm_serial: switch to DM_SERIAL Switch the S5P4418-SOC and therefore the s5p4418_nanopi2 board to DM_SERIAL. Signed-off-by: Stefan Bosch --- arch/arm/mach-nexell/Kconfig | 4 ++-- drivers/serial/Kconfig | 9 +++++++++ drivers/serial/Makefile | 1 + 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-nexell/Kconfig b/arch/arm/mach-nexell/Kconfig index 86a2398637..16324e1520 100644 --- a/arch/arm/mach-nexell/Kconfig +++ b/arch/arm/mach-nexell/Kconfig @@ -6,8 +6,8 @@ config ARCH_S5P4418 select OF_CONTROL select OF_SEPARATE select NX_GPIO - select PL011_SERIAL - select PL011_SERIAL_FLUSH_ON_INIT + select DM_SERIAL + select PL01X_SERIAL help Enable support for Nexell S5P4418 SoC. diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 14b0febd1a..bb5083201b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -827,6 +827,15 @@ config S5P_SERIAL help Select this to enable Samsung S5P UART support. +config S5P4418_PL011_SERIAL + bool "Extended PL011 driver for S5P4418" + depends on DM_SERIAL && PL01X_SERIAL && ARCH_NEXELL + default y + help + Select this to enable support of the PL011 UARTs in the S5P4418 SOC. + With this driver the UART-clocks are set to the appropriate rate + (if not 'skip-init'). + config SANDBOX_SERIAL bool "Sandbox UART support" depends on SANDBOX diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 37d3f82dbd..01fef3f323 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_MT7620_SERIAL) += serial_mt7620.o obj-$(CONFIG_HTIF_CONSOLE) += serial_htif.o obj-$(CONFIG_SIFIVE_SERIAL) += serial_sifive.o obj-$(CONFIG_XEN_SERIAL) += serial_xen.o +obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o From 28663622cf0767d0c5f31629ab50e34069bf0267 Mon Sep 17 00:00:00 2001 From: Stefan Bosch Date: Sun, 18 Dec 2022 12:26:47 +0000 Subject: [PATCH 382/424] arm: s5p4418: dm_serial: remove old code / add DEBUG_UART Remove init of UART-clock and UART-reset in arch_cpu_init(). Add DEBUG_UART to s5p4418_nanopi2_defconfig. Signed-off-by: Stefan Bosch --- arch/arm/cpu/armv7/s5p4418/cpu.c | 29 ----------------------------- arch/arm/mach-nexell/clock.c | 2 +- configs/s5p4418_nanopi2_defconfig | 6 +++++- include/configs/s5p4418_nanopi2.h | 8 +++----- 4 files changed, 9 insertions(+), 36 deletions(-) diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 7ba9c0b032..fcaafc0ff7 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -13,10 +13,8 @@ #include #include #include -#include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -45,39 +43,12 @@ static void cpu_soc_init(void) nx_tieoff_set(NX_TIEOFF_CORTEXA9MP_TOP_QUADL2C_L2RET1N_1, 1); } -#ifdef CONFIG_PL011_SERIAL -static void serial_device_init(void) -{ - char dev[10]; - int id; - - sprintf(dev, "nx-uart.%d", CONFIG_CONS_INDEX); - id = RESET_ID_UART0 + CONFIG_CONS_INDEX; - - struct clk *clk = clk_get((const char *)dev); - - /* reset control: Low active ___|--- */ - nx_rstcon_setrst(id, RSTCON_ASSERT); - udelay(10); - nx_rstcon_setrst(id, RSTCON_NEGATE); - udelay(10); - - /* set clock */ - clk_disable(clk); - clk_set_rate(clk, CFG_PL011_CLOCK); - clk_enable(clk); -} -#endif - int arch_cpu_init(void) { flush_dcache_all(); cpu_soc_init(); clk_init(); - if (IS_ENABLED(CONFIG_PL011_SERIAL)) - serial_device_init(); - return 0; } diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c index 24fa204ccd..59ffa26255 100644 --- a/arch/arm/mach-nexell/clock.c +++ b/arch/arm/mach-nexell/clock.c @@ -856,7 +856,7 @@ void __init clk_init(void) } /* prevent uart clock disable for low step debug message */ - #ifndef CONFIG_DEBUG_NX_UART + #ifndef CONFIG_DEBUG_UART if (peri->dev_name) { #ifdef CONFIG_BACKLIGHT_PWM if (!strcmp(peri->dev_name, DEV_NAME_PWM)) diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index 35e7c88059..0645b09f78 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -11,12 +11,15 @@ CONFIG_ENV_OFFSET=0x2E0200 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="s5p4418-nanopi2" CONFIG_SYS_PROMPT="nanopi2# " +CONFIG_DEBUG_UART_BASE=0xC00A1000 +CONFIG_DEBUG_UART_CLOCK=150000000 CONFIG_TARGET_NANOPI2=y CONFIG_S5P4418_ONEWIRE=y CONFIG_ROOT_DEV=1 CONFIG_BOOT_PART=1 CONFIG_ROOT_PART=2 CONFIG_SYS_LOAD_ADDR=0x71080000 +CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x71000000 CONFIG_SYS_MEMTEST_END=0xb0000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -54,7 +57,8 @@ CONFIG_MMC_DW=y CONFIG_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y -CONFIG_CONS_INDEX=0 +CONFIG_DEBUG_UART_PL011=y +CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_DISPLAY=y diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index 2fa44e65fc..fec1bfd50e 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -76,11 +76,9 @@ /*----------------------------------------------------------------------- * serial console configuration */ -#define CFG_PL011_CLOCK 50000000 -#define CFG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \ - (void *)PHY_BASEADDR_UART1, \ - (void *)PHY_BASEADDR_UART2, \ - (void *)PHY_BASEADDR_UART3} + +/* 150MHz is the clock rate set by SPL (uart0) */ +#define CFG_PL011_CLOCK 150000000 /*----------------------------------------------------------------------- * BACKLIGHT From ee43b1e744f2a4279668823e8e13a16ec20b4e80 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Fri, 23 Dec 2022 08:47:17 +0200 Subject: [PATCH 383/424] ARM: dts: at91: sam9x60: add sdhci1 node and pinctrl Add node for sdhci1 controller and its pinctrl. Signed-off-by: Mihai Sain --- arch/arm/dts/sam9x60.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 17224ef771..1998bb5195 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -108,6 +108,19 @@ pinctrl-0 = <&pinctrl_sdhci0>; }; + sdhci1: sdhci-host@90000000 { + compatible = "microchip,sam9x60-sdhci"; + reg = <0x90000000 0x300>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */ + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; + }; + apb { compatible = "simple-bus"; #address-cells = <1>; @@ -211,6 +224,18 @@ (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */ }; }; + + sdhci1 { + pinctrl_sdhci1: sdhci1 { + atmel,pins = + ; /* PA4 DAT3 periph B with pullup */ + }; + }; }; pmecc: ecc-engine@ffffe000 { From 77aa6456bf8e9dc9ac1edf7ef22d00bc03a3d6f3 Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Fri, 23 Dec 2022 08:39:36 +0200 Subject: [PATCH 384/424] board: at91: sam9x60: set blue led on at boot time Set blue led on at boot time in order to highlight that u-boot is loaded. This is done for all sam9x60 based boards which contain an RGB led. Signed-off-by: Mihai Sain --- board/atmel/sam9x60_curiosity/sam9x60_curiosity.c | 10 ++++++++++ board/atmel/sam9x60ek/sam9x60ek.c | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c index 8cf67d148d..0fe0de9fde 100644 --- a/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c +++ b/board/atmel/sam9x60_curiosity/sam9x60_curiosity.c @@ -25,6 +25,13 @@ DECLARE_GLOBAL_DATA_PTR; void at91_prepare_cpu_var(void); +static void board_leds_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTD, 17, 0); /* LED RED */ + at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* LED GREEN */ + at91_set_pio_output(AT91_PIO_PORTD, 21, 1); /* LED BLUE */ +} + int board_late_init(void) { at91_prepare_cpu_var(); @@ -62,6 +69,9 @@ int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + board_leds_init(); + return 0; } diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 04bf2bb5c9..3fbfca4acc 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -24,6 +24,13 @@ DECLARE_GLOBAL_DATA_PTR; void at91_prepare_cpu_var(void); +static void board_leds_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTB, 11, 0); /* LED RED */ + at91_set_pio_output(AT91_PIO_PORTB, 12, 0); /* LED GREEN */ + at91_set_pio_output(AT91_PIO_PORTB, 13, 1); /* LED BLUE */ +} + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -66,6 +73,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + board_leds_init(); + return 0; } From 8a2f52f44a0d120e4234c1b83dd4dd731e95e2cb Mon Sep 17 00:00:00 2001 From: Mihai Sain Date: Fri, 23 Dec 2022 08:43:53 +0200 Subject: [PATCH 385/424] configs: sam9x60: add mmc config for sdmmc1 Add new config for storing environment from SDMMC1. Signed-off-by: Mihai Sain --- board/atmel/sam9x60_curiosity/MAINTAINERS | 1 + configs/sam9x60_curiosity_mmc1_defconfig | 92 +++++++++++++++++++++++ 2 files changed, 93 insertions(+) create mode 100644 configs/sam9x60_curiosity_mmc1_defconfig diff --git a/board/atmel/sam9x60_curiosity/MAINTAINERS b/board/atmel/sam9x60_curiosity/MAINTAINERS index 3e1dce2980..0d9369e027 100644 --- a/board/atmel/sam9x60_curiosity/MAINTAINERS +++ b/board/atmel/sam9x60_curiosity/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/atmel/sam9x60_curiosity/ F: include/configs/sam9x60_curiosity.h F: configs/sam9x60_curiosity_mmc_defconfig +F: configs/sam9x60_curiosity_mmc1_defconfig diff --git a/configs/sam9x60_curiosity_mmc1_defconfig b/configs/sam9x60_curiosity_mmc1_defconfig new file mode 100644 index 0000000000..42aba3d630 --- /dev/null +++ b/configs/sam9x60_curiosity_mmc1_defconfig @@ -0,0 +1,92 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_AT91=y +CONFIG_TEXT_BASE=0x23f00000 +CONFIG_SYS_MALLOC_LEN=0x81000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TARGET_SAM9X60_CURIOSITY=y +CONFIG_ATMEL_LEGACY=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity" +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=200000000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_LOAD_ADDR=0x22000000 +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000bf00 +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/mmcblk1p2 rw rootwait" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="fatload mmc 1:1 0x21000000 at91-sam9x60_curiosity.dtb; fatload mmc 1:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_MISC_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=281 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_HASH=y +CONFIG_HASH_VERIFY=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="1:1" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_AT91_SAM9X60_PLL=y +CONFIG_CPU=y +CONFIG_AT91_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_ATMEL_EBI=y +CONFIG_MFD_ATMEL_SMC=y +CONFIG_I2C_EEPROM=y +CONFIG_MICROCHIP_FLEXCOM=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_DM_NAND_ATMEL=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_PHY_MICREL=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_AT91=y +CONFIG_TIMER=y +CONFIG_MCHP_PIT64B_TIMER=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y From 3631be3ed66aa2110adcc8d4ce09d042e6c7e78a Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:10 +0200 Subject: [PATCH 386/424] ARM: dts: sam9x60: Add OHCI and EHCI DT nodes Add the OHCI and EHCI DT nodes for the sam9x60 SoC's. Signed-off-by: Sergiu Moga Reviewed-by: Marek Vasut --- arch/arm/dts/sam9x60.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi index 1998bb5195..2b93d08938 100644 --- a/arch/arm/dts/sam9x60.dtsi +++ b/arch/arm/dts/sam9x60.dtsi @@ -69,6 +69,24 @@ #size-cells = <1>; ranges; + usb1: usb@600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: usb@700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usb_clk", "ehci_clk"; + assigned-clocks = <&pmc PMC_TYPE_CORE 8>; + assigned-clock-rates = <480000000>; + status = "disabled"; + }; + ebi: ebi@10000000 { compatible = "microchip,sam9x60-ebi"; #address-cells = <2>; From 445ff8bb5aeec98df356c4a474a54fb42af8c674 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:11 +0200 Subject: [PATCH 387/424] ARM: dts: sam9x60_curiosity: Add pinctrl and gpio properties for USB Add the required pinctrl and gpio properties needed by the USB DT nodes of the sam9x60_curiosity boards. Signed-off-by: Sergiu Moga --- arch/arm/dts/at91-sam9x60_curiosity.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts index 7c5b6ae2b8..d6ae3d648d 100644 --- a/arch/arm/dts/at91-sam9x60_curiosity.dts +++ b/arch/arm/dts/at91-sam9x60_curiosity.dts @@ -49,6 +49,13 @@ atmel,pins = ; }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = ; + }; + }; }; }; }; @@ -89,3 +96,17 @@ phy-mode = "rmii"; status = "okay"; }; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 15 GPIO_ACTIVE_HIGH + &pioD 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; From 205ecbdccd3d3359f94c4b576992cec3f37fb306 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:12 +0200 Subject: [PATCH 388/424] ARM: dts: sam9x60ek: Add pinctrl and gpio properties for USB Add the required pinctrl and gpio properties required by the USB DT nodes of the sam9x60ek boards. Signed-off-by: Sergiu Moga --- arch/arm/dts/sam9x60ek.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts index 1a02e2cb79..45e2f4cc40 100644 --- a/arch/arm/dts/sam9x60ek.dts +++ b/arch/arm/dts/sam9x60ek.dts @@ -139,6 +139,13 @@ ; }; + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = ; + }; + }; + }; }; }; @@ -213,3 +220,17 @@ phy-mode = "rmii"; status = "okay"; }; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 15 GPIO_ACTIVE_HIGH + &pioD 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; From 7b88887ba78d100bcb74d3e0baa03f87a338e707 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:13 +0200 Subject: [PATCH 389/424] dt-bindings: reset: add sama7g5 definitions Upstream linux commit 5994f58977e0. Add reset bindings for SAMA7G5. At the moment only USB PHYs are included. The three reset USB phy's have their ID's mapped from 4 to 6. There are no USB phy's with ID's numbered from 0 to 3. Signed-off-by: Sergiu Moga --- include/dt-bindings/reset/sama7g5-reset.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 include/dt-bindings/reset/sama7g5-reset.h diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h new file mode 100644 index 0000000000..2116f41d04 --- /dev/null +++ b/include/dt-bindings/reset/sama7g5-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_BINDINGS_RESET_SAMA7G5_H +#define __DT_BINDINGS_RESET_SAMA7G5_H + +#define SAMA7G5_RESET_USB_PHY1 4 +#define SAMA7G5_RESET_USB_PHY2 5 +#define SAMA7G5_RESET_USB_PHY3 6 + +#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ From ee25ed5899b8a7ee125e58298bd1b71feedb79f1 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:14 +0200 Subject: [PATCH 390/424] dt-bindings: clk: at91: Define additional UTMI related clocks Add definitions for an additional main UTMI clock as well as its respective subclocks. Signed-off-by: Sergiu Moga --- include/dt-bindings/clk/at91.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h index e30756b280..a178b94157 100644 --- a/include/dt-bindings/clk/at91.h +++ b/include/dt-bindings/clk/at91.h @@ -18,5 +18,10 @@ #define PMC_TYPE_PERIPHERAL 3 #define PMC_TYPE_GCK 4 #define PMC_TYPE_SLOW 5 +#define USB_UTMI 6 + +#define USB_UTMI1 0 +#define USB_UTMI2 1 +#define USB_UTMI3 2 #endif From 851960e591dcceed89f3a6937603a115f6bcd9c9 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:15 +0200 Subject: [PATCH 391/424] ARM: dts: sama7g5: Add USB and UTMI DT nodes Define the USB and UTMI DT nodes for the sama7g5 SoC's. Since these have not yet been defined in upstream Linux, place them in the U-Boot specific DT file. Signed-off-by: Sergiu Moga Reviewed-by: Marek Vasut --- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 75 ++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index d294ddb54a..f563071fe6 100644 --- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -10,13 +10,87 @@ * */ +#include +#include + / { chosen { u-boot,dm-pre-reloc; }; + utmi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + compatible = "microchip,sama7g5-usb-phy"; + sfr-phandle = <&sfr>; + reg = <0>; + clocks = <&utmi_clk USB_UTMI1>; + clock-names = "utmi_clk"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + compatible = "microchip,sama7g5-usb-phy"; + sfr-phandle = <&sfr>; + reg = <1>; + clocks = <&utmi_clk USB_UTMI2>; + clock-names = "utmi_clk"; + status = "disabled"; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + compatible = "microchip,sama7g5-usb-phy"; + sfr-phandle = <&sfr>; + reg = <2>; + clocks = <&utmi_clk USB_UTMI3>; + clock-names = "utmi_clk"; + status = "disabled"; + #phy-cells = <0>; + }; + }; + + utmi_clk: utmi-clk { + compatible = "microchip,sama7g5-utmi-clk"; + sfr-phandle = <&sfr>; + #clock-cells = <1>; + clocks = <&pmc PMC_TYPE_CORE 27>; + clock-names = "utmi_clk"; + resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>, + <&reset_controller SAMA7G5_RESET_USB_PHY2>, + <&reset_controller SAMA7G5_RESET_USB_PHY3>; + reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; + }; + soc { u-boot,dm-pre-reloc; + + usb2: usb@400000 { + compatible = "microchip,sama7g5-ohci", "usb-ohci"; + reg = <0x00400000 0x100000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb3: usb@500000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00500000 0x100000>; + interrupts = ; + clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + sfr: sfr@e1624000 { + compatible = "microchip,sama7g5-sfr", "syscon"; + reg = <0xe1624000 0x4000>; + }; }; }; @@ -59,4 +133,3 @@ &uart3 { u-boot,dm-pre-reloc; }; - From 3cd06bfa9649841276dd2b07376d6999e178965f Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:16 +0200 Subject: [PATCH 392/424] ARM: dts: sama7g5ek: Add pinctrl, gpio and phy properties for USB Add the required pinctrl, gpio and phy properties required by the USB DT nodes of the sama7g5ek boards. Since these have not yet been defined in upstream Linux, place them in the U-Boot specific DT file. Signed-off-by: Sergiu Moga --- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index f563071fe6..a54cfaccbf 100644 --- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -10,6 +10,7 @@ * */ +#include "sama7g5-pinfunc.h" #include #include @@ -112,6 +113,11 @@ &pioA { u-boot,dm-pre-reloc; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; }; &pit64b0 { @@ -133,3 +139,32 @@ &uart3 { u-boot,dm-pre-reloc; }; + +&usb2 { + num-ports = <3>; + atmel,vbus-gpio = <0 + 0 + &pioA PIN_PC6 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + phys = <&usb_phy2>; + phy-names = "usb"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy1 { + status = "okay"; +}; + +&usb_phy2 { + status = "okay"; +}; From 20bc95f8c837ecf058badb53289262d61f00a05a Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:17 +0200 Subject: [PATCH 393/424] ARM: dts: sama5d2_icp: Add pinctrl nodes for USB related DT nodes Add the pinctrl subnodes required by the USB related DT nodes. Signed-off-by: Sergiu Moga --- arch/arm/dts/at91-sama5d2_icp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts index 2dffae9c5c..4f796c6c94 100644 --- a/arch/arm/dts/at91-sama5d2_icp.dts +++ b/arch/arm/dts/at91-sama5d2_icp.dts @@ -154,7 +154,29 @@ ; bias-disable; }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; }; }; }; }; + +&usb1 { + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; From e4ad98d67bd276bce4431d340517001f9e4516a5 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:04:18 +0200 Subject: [PATCH 394/424] ARM: dts: sama5d27_wlsom1_ek: Add pinctrl nodes for USB DT nodes Add the pinctrl nodes required by the USB related DT nodes. Signed-off-by: Sergiu Moga --- arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts index eec183d5de..6d4b35ea96 100644 --- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts @@ -143,7 +143,32 @@ pinmux = ; bias-pull-up; }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; }; }; }; }; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioA PIN_PA10 GPIO_ACTIVE_HIGH + 0 + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; From 11c037ab920c0cdd1d9c8316a08c939b4253aefe Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 4 Jan 2023 16:03:17 +0200 Subject: [PATCH 395/424] ARM: at91: add sama7 SFR definitions Special Function Registers(SFR) definitions for SAMA7 product family. Signed-off-by: Cristian Birsan Signed-off-by: Sergiu Moga --- arch/arm/mach-at91/include/mach/sama7-sfr.h | 59 +++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/sama7-sfr.h diff --git a/arch/arm/mach-at91/include/mach/sama7-sfr.h b/arch/arm/mach-at91/include/mach/sama7-sfr.h new file mode 100644 index 0000000000..a987ff5465 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7-sfr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Microchip SFR (Special Function Registers) registers for SAMA7 family. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Cristian Birsan + */ + +#ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H +#define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H + +#define SAMA7_SFR_OHCIICR 0x00 /* OHCI INT Configuration Register */ +#define SAMA7_SFR_OHCIISR 0x04 /* OHCI INT Status Register */ +/* 0x08 ~ 0xe3: Reserved */ +#define SAMA7_SFR_WPMR 0xe4 /* Write Protection Mode Register */ +#define SAMA7_SFR_WPSR 0xe4 /* Write Protection Status Register */ +/* 0xec ~ 0x200b: Reserved */ +#define SAMA7_SFR_DEBUG 0x200c /* Debug Register */ + +/* 0x2010 ~ 0x2027: Reserved */ +#define SAMA7_SFR_EHCIOHCI 0x2020 /* EHCI OHCI Clock Configuration Reg */ + +#define SAMA7_SFR_HSS_AXI_QOS 0x2028 /* HSS AXI QOS Register */ +#define SAMA7_SFR_UDDRC 0x202c /* UDDRC Register */ +#define SAMA7_SFR_CAN_SRAM_SEL 0x2030 /* CAN SRAM Select. Register */ +/* 0x2034 ~ 0x203f: Reserved */ + +#define SAMA7_SFR_UTMI0 0x2040 +#define SAMA7_SFR_UTMI0R(x) (SAMA7_SFR_UTMI0 + 4 * (x)) + +#define SAMA7_SFR_UTMI0R0 0x2040 /* UTMI0 Configuration Register */ +#define SAMA7_SFR_UTMI0R1 0x2044 /* UTMI1 Configuration Register */ +#define SAMA7_SFR_UTMI0R2 0x2048 /* UTMI2 Configuration Register */ + +/* Field definitions */ +#define SAMA7_SFR_OHCIICR_ARIE BIT(0) +#define SAMA7_SFR_OHCIICR_APPSTART BIT(1) +#define SAMA7_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define SAMA7_SFR_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define SAMA7_SFR_OHCIISR_RIS(x) BIT(x) + +#define SAMA7_SFR_WPMR_WPEN BIT(0) +#define SAMA7_SFR_WPMR_KEY 0x53465200 /* SFR in ASCII*/ +#define SAMA7_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + +#define SAMA7_SFR_WPSR_WPSRC_MASK GENMASK(23, 8) +#define SAMA7_SFR_WPSR_WPVS_MASK BIT(0) + +#define SAMA7_SFR_CAN_SRAM_UPPER(x) BIT(x) + +#define SAMA7_SFR_UTMI_RX_VBUS BIT(25) /* VBUS Valid bit */ +#define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X BIT(23) /* TXPREEMPAMPTUNE 1x */ +#define SAMA7_SFR_UTMI_COMMONON BIT(3) /* PLL Common ON bit */ + +#define SAMA7_SFR_EHCIOHCI_PHYCLK BIT(1) /* Alternate PHY Clk */ + +#endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */ From 61040097a9d1c8022bae7936c52b729ff1adb163 Mon Sep 17 00:00:00 2001 From: Sergiu Moga Date: Wed, 4 Jan 2023 16:03:18 +0200 Subject: [PATCH 396/424] reset: at91: Add reset driver for basic assert/deassert operations Add support for at91 reset controller's basic assert/deassert operations. Since this driver conflicts with the SYSRESET driver because they both bind to the same RSTC node, implement a custom bind hook that would manually bind the sysreset driver, if enabled, to the same RSTC DT node. Furthermore, delete the no longer needed compatibles from the SYSRESET driver and rename it to make sure than any possible conflicts are avoided. Signed-off-by: Sergiu Moga Tested-by: Mihai Sain Reviewed-by: Claudiu Beznea --- drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-at91.c | 141 +++++++++++++++++++++++++++++++ drivers/sysreset/sysreset_at91.c | 10 +-- 4 files changed, 151 insertions(+), 9 deletions(-) create mode 100644 drivers/reset/reset-at91.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 4cb0ba0850..e4039d7474 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -211,4 +211,12 @@ config RESET_DRA7 help Support for TI DRA7-RESET subsystem. Basic Assert/Deassert is supported. + +config RESET_AT91 + bool "Enable support for Microchip/Atmel Reset Controller driver" + depends on DM_RESET && ARCH_AT91 + help + This enables the Reset Controller driver support for Microchip/Atmel + SoCs. Mainly used to expose assert/deassert methods to other drivers + that require it. endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0620b62809..6c8b45ecba 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o obj-$(CONFIG_RESET_DRA7) += reset-dra7.o +obj-$(CONFIG_RESET_AT91) += reset-at91.o diff --git a/drivers/reset/reset-at91.c b/drivers/reset/reset-at91.c new file mode 100644 index 0000000000..165c87acdc --- /dev/null +++ b/drivers/reset/reset-at91.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Atmel/Microchip Reset Controller. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Sergiu Moga + */ + +#include +#include +#include +#include +#include +#include +#include + +struct at91_reset { + void __iomem *dev_base; + struct at91_reset_data *data; +}; + +struct at91_reset_data { + u32 n_device_reset; + u8 device_reset_min_id; + u8 device_reset_max_id; +}; + +static const struct at91_reset_data sama7g5_data = { + .n_device_reset = 3, + .device_reset_min_id = SAMA7G5_RESET_USB_PHY1, + .device_reset_max_id = SAMA7G5_RESET_USB_PHY3, +}; + +static int at91_rst_update(struct at91_reset *reset, unsigned long id, + bool assert) +{ + u32 val; + + if (!reset->dev_base) + return 0; + + val = readl(reset->dev_base); + if (assert) + val |= BIT(id); + else + val &= ~BIT(id); + writel(val, reset->dev_base); + + return 0; +} + +static int at91_reset_of_xlate(struct reset_ctl *reset_ctl, + struct ofnode_phandle_args *args) +{ + struct at91_reset *reset = dev_get_priv(reset_ctl->dev); + + if (!reset->data->n_device_reset || + args->args[0] < reset->data->device_reset_min_id || + args->args[0] > reset->data->device_reset_max_id) + return -EINVAL; + + reset_ctl->id = args->args[0]; + + return 0; +} + +static int at91_rst_assert(struct reset_ctl *reset_ctl) +{ + struct at91_reset *reset = dev_get_priv(reset_ctl->dev); + + return at91_rst_update(reset, reset_ctl->id, true); +} + +static int at91_rst_deassert(struct reset_ctl *reset_ctl) +{ + struct at91_reset *reset = dev_get_priv(reset_ctl->dev); + + return at91_rst_update(reset, reset_ctl->id, false); +} + +struct reset_ops at91_reset_ops = { + .of_xlate = at91_reset_of_xlate, + .rst_assert = at91_rst_assert, + .rst_deassert = at91_rst_deassert, +}; + +static int at91_reset_probe(struct udevice *dev) +{ + struct at91_reset *reset = dev_get_priv(dev); + struct clk sclk; + int ret; + + reset->data = (struct at91_reset_data *)dev_get_driver_data(dev); + reset->dev_base = dev_remap_addr_index(dev, 1); + if (reset->data && reset->data->n_device_reset && !reset->dev_base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &sclk); + if (ret) + return ret; + + return clk_prepare_enable(&sclk); +} + +static int at91_reset_bind(struct udevice *dev) +{ + struct udevice *at91_sysreset; + + if (CONFIG_IS_ENABLED(SYSRESET_AT91)) + return device_bind_driver_to_node(dev, "at91_sysreset", + "at91_sysreset", + dev_ofnode(dev), + &at91_sysreset); + + return 0; +} + +static const struct udevice_id at91_reset_ids[] = { + { + .compatible = "microchip,sama7g5-rstc", + .data = (ulong)&sama7g5_data, + }, + { + .compatible = "atmel,sama5d3-rstc", + }, + { + .compatible = "microchip,sam9x60-rstc", + }, + { } +}; + +U_BOOT_DRIVER(at91_reset) = { + .name = "at91_reset", + .id = UCLASS_RESET, + .of_match = at91_reset_ids, + .bind = at91_reset_bind, + .probe = at91_reset_probe, + .priv_auto = sizeof(struct at91_reset), + .ops = &at91_reset_ops, +}; diff --git a/drivers/sysreset/sysreset_at91.c b/drivers/sysreset/sysreset_at91.c index 6119a29927..fc85f31ebf 100644 --- a/drivers/sysreset/sysreset_at91.c +++ b/drivers/sysreset/sysreset_at91.c @@ -56,17 +56,9 @@ static struct sysreset_ops at91_sysreset = { .request = at91_sysreset_request, }; -static const struct udevice_id a91_sysreset_ids[] = { - { .compatible = "atmel,sama5d3-rstc" }, - { .compatible = "microchip,sam9x60-rstc" }, - { .compatible = "microchip,sama7g5-rstc" }, - { } -}; - U_BOOT_DRIVER(sysreset_at91) = { .id = UCLASS_SYSRESET, - .name = "at91_reset", + .name = "at91_sysreset", .ops = &at91_sysreset, .probe = at91_sysreset_probe, - .of_match = a91_sysreset_ids, }; From e0ddd895f66a401dd69f561e7960609d7730e5ec Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sun, 27 Nov 2022 16:55:02 -0500 Subject: [PATCH 397/424] patman: Switch to setuptools distutils is about to meet its demise [1]. Switch to setuptools. [1] https://peps.python.org/pep-0632/ Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- tools/patman/setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/setup.py b/tools/patman/setup.py index 43fdc00ce6..5643bf1503 100644 --- a/tools/patman/setup.py +++ b/tools/patman/setup.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -from distutils.core import setup +from setuptools import setup setup(name='patman', version='1.0', license='GPL-2.0+', From 7943ae241c099edc6d0cd7c4dd3c5ee18ecb24f7 Mon Sep 17 00:00:00 2001 From: Yuepeng Xing Date: Fri, 2 Dec 2022 14:23:07 +0800 Subject: [PATCH 398/424] test:dm:fix typo Fix typos in the 'test/dm' directory. Signed-off-by: Yuepeng Xing Reviewed-by: Simon Glass --- test/dm/blk.c | 2 +- test/dm/button.c | 4 ++-- test/dm/gpio.c | 4 ++-- test/dm/host.c | 2 +- test/dm/remoteproc.c | 2 +- test/dm/scmi.c | 2 +- test/dm/spmi.c | 2 +- test/dm/test-fdt.c | 2 +- 8 files changed, 10 insertions(+), 10 deletions(-) diff --git a/test/dm/blk.c b/test/dm/blk.c index 612f3ffb32..0aa04c64ef 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -127,7 +127,7 @@ static int dm_test_blk_devnum(struct unit_test_state *uts) /* * Probe the devices, with the first one being probed last. This is the - * one with no alias / sequence numnber. + * one with no alias / sequence number. */ ut_assertok(uclass_get_device(UCLASS_MMC, 1, &dev)); ut_assertok(uclass_get_device(UCLASS_MMC, 2, &dev)); diff --git a/test/dm/button.c b/test/dm/button.c index f8a7fab61d..e76c1ad030 100644 --- a/test/dm/button.c +++ b/test/dm/button.c @@ -46,7 +46,7 @@ static int dm_test_button_gpio(struct unit_test_state *uts) struct udevice *dev, *gpio; /* - * Check that we can manipulate an BUTTON. BUTTON 1 is connected to GPIO + * Check that we can manipulate a BUTTON. BUTTON 1 is connected to GPIO * bank gpio_a, offset 3. */ ut_assertok(uclass_get_device(UCLASS_BUTTON, 1, &dev)); @@ -64,7 +64,7 @@ static int dm_test_button_gpio(struct unit_test_state *uts) } DM_TEST(dm_test_button_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); -/* Test obtaining an BUTTON by label */ +/* Test obtaining a BUTTON by label */ static int dm_test_button_label(struct unit_test_state *uts) { struct udevice *dev, *cmp; diff --git a/test/dm/gpio.c b/test/dm/gpio.c index a8c35d4370..0d88ec24bd 100644 --- a/test/dm/gpio.c +++ b/test/dm/gpio.c @@ -348,7 +348,7 @@ static int dm_test_gpio_phandles(struct unit_test_state *uts) ut_asserteq(-ENOENT, gpio_request_by_name(dev, "test-gpios", 5, &desc, 0)); - /* Last GPIO is ignord as it comes after <0> */ + /* Last GPIO is ignored as it comes after <0> */ ut_asserteq(3, gpio_request_list_by_name(dev, "test-gpios", desc_list, ARRAY_SIZE(desc_list), 0)); ut_asserteq(-EBUSY, gpio_request_list_by_name(dev, "test-gpios", @@ -377,7 +377,7 @@ static int dm_test_gpio_phandles(struct unit_test_state *uts) ut_asserteq(6, gpio_request_list_by_name(dev, "test2-gpios", desc_list, ARRAY_SIZE(desc_list), 0)); - /* This was set to output previously but flags resetted to 0 = INPUT */ + /* This was set to output previously but flags reset to 0 = INPUT */ ut_asserteq(0, sandbox_gpio_get_flags(gpio_a, 1)); ut_asserteq(GPIOF_INPUT, gpio_get_function(gpio_a, 1, NULL)); diff --git a/test/dm/host.c b/test/dm/host.c index 4dafc24abb..355ba7770a 100644 --- a/test/dm/host.c +++ b/test/dm/host.c @@ -132,7 +132,7 @@ static int dm_test_cmd_host(struct unit_test_state *uts) ut_assertok(run_commandf("host bind fat %s", filename2)); - /* Check it is not removeable (no '-r') */ + /* Check it is not removable (no '-r') */ ut_assertok(uclass_next_device_err(&dev)); ut_assertok(blk_get_from_parent(dev, &blk)); desc = dev_get_uclass_plat(blk); diff --git a/test/dm/remoteproc.c b/test/dm/remoteproc.c index b5e9f9ddc9..7a8ff47fa1 100644 --- a/test/dm/remoteproc.c +++ b/test/dm/remoteproc.c @@ -139,7 +139,7 @@ static int dm_test_remoteproc_elf(struct unit_test_state *uts) 0x20, 0x00, 0x00, 0x00, /* memsz = filesz */ 0x20, 0x00, 0x00, 0x00, - /* flags : readable and exectuable */ + /* flags : readable and executable */ 0x05, 0x00, 0x00, 0x00, /* padding */ 0x00, 0x00, 0x00, 0x00, diff --git a/test/dm/scmi.c b/test/dm/scmi.c index 795f207304..93c7d08f43 100644 --- a/test/dm/scmi.c +++ b/test/dm/scmi.c @@ -6,7 +6,7 @@ * uclass devices probe when a SCMI server exposes resources. * * Note in test.dts the protocol@10 node in scmi node. Protocol 0x10 is not - * implemented in U-Boot SCMI components but the implementation is exepected + * implemented in U-Boot SCMI components but the implementation is expected * to not complain on unknown protocol IDs, as long as it is not used. Note * in test.dts tests that SCMI drivers probing does not fail for such an * unknown SCMI protocol ID. diff --git a/test/dm/spmi.c b/test/dm/spmi.c index 114fd2d22e..9cc284b98c 100644 --- a/test/dm/spmi.c +++ b/test/dm/spmi.c @@ -17,7 +17,7 @@ #include #include -/* Test if bus childs got probed propperly*/ +/* Test if bus children got probed properly*/ static int dm_test_spmi_probe(struct unit_test_state *uts) { const char *name = "spmi@0"; diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c index 8bb868b678..7cd2d04612 100644 --- a/test/dm/test-fdt.c +++ b/test/dm/test-fdt.c @@ -592,7 +592,7 @@ static int dm_test_fdt_translation(struct unit_test_state *uts) ut_asserteq_str("dev@2,200", dev->name); ut_asserteq(0xA000, dev_read_addr(dev)); - /* No translation for busses with #size-cells == 0 */ + /* No translation for buses with #size-cells == 0 */ ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 3, &dev)); ut_asserteq_str("dev@42", dev->name); ut_asserteq(0x42, dev_read_addr(dev)); From 291ab6c74c6d9f063d10fa97e526dd9312c1b746 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Fri, 16 Dec 2022 20:45:27 -0500 Subject: [PATCH 399/424] patman: remove extraneous imports * tools/patman/main.py: Remove extraneous imports and fix indentation. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/main.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/tools/patman/main.py b/tools/patman/main.py index 5a7756a221..8067a288ab 100755 --- a/tools/patman/main.py +++ b/tools/patman/main.py @@ -9,7 +9,6 @@ from argparse import ArgumentParser import os import re -import shutil import sys import traceback @@ -19,7 +18,6 @@ if __name__ == "__main__": sys.path.append(os.path.join(our_path, '..')) # Our modules -from patman import command from patman import control from patman import gitutil from patman import project @@ -136,7 +134,6 @@ if not args.debug: # Run our meagre tests if args.cmd == 'test': - import doctest from patman import func_test result = test_util.run_test_suites( @@ -183,7 +180,7 @@ elif args.cmd == 'status': args.show_comments, args.patchwork_url) except Exception as e: terminal.tprint('patman: %s: %s' % (type(e).__name__, e), - colour=terminal.Color.RED) + colour=terminal.Color.RED) if args.debug: print() traceback.print_exc() From 425bbed247e3361f45f4c83fbfdb432a0bcc2892 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Fri, 16 Dec 2022 20:45:28 -0500 Subject: [PATCH 400/424] patman: fix installation of README.rst data file This fixes a regression introduced in commit 74df491051d6 ("buildman: Convert documentation to rST"). Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/setup.py b/tools/patman/setup.py index 5643bf1503..2ff791da0f 100644 --- a/tools/patman/setup.py +++ b/tools/patman/setup.py @@ -7,6 +7,6 @@ setup(name='patman', scripts=['patman'], packages=['patman'], package_dir={'patman': ''}, - package_data={'patman': ['README']}, + package_data={'patman': ['README.rst']}, classifiers=['Environment :: Console', 'Topic :: Software Development']) From a5197fc9c3329e3559e79dabb5acde9d0dd9e102 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Fri, 16 Dec 2022 20:45:29 -0500 Subject: [PATCH 401/424] patman: locate README.rst via importlib Rationale: this is more robust than assumptions about the file hierarchy layout of the installation of patman, for example on non file-hierarchy standard (FHS) systems such as Guix System or Nix OS. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/main.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tools/patman/main.py b/tools/patman/main.py index 8067a288ab..2a2a7eaa24 100755 --- a/tools/patman/main.py +++ b/tools/patman/main.py @@ -7,6 +7,7 @@ """See README for more information""" from argparse import ArgumentParser +import importlib.resources import os import re import sys @@ -160,11 +161,8 @@ elif args.cmd == 'send': fd.close() elif args.full_help: - tools.print_full_help( - os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), - 'README.rst') - ) - + with importlib.resources.path('patman', 'README.rst') as readme: + tools.print_full_help(str(readme)) else: # If we are not processing tags, no need to warning about bad ones if not args.process_tags: From f9e20e3bff50722d76720a5cd2ce47252bfe553a Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:38 -0500 Subject: [PATCH 402/424] patman: cosmetic: Fix PEP 8 warnings for the gitutil module. This patch fixes all the PEP 8 warnings reported by Pyflake for the gitutil module. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/gitutil.py | 106 ++++++++++++++++++++++++---------------- 1 file changed, 65 insertions(+), 41 deletions(-) diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index ceaf2ce150..74c6e94494 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -2,21 +2,19 @@ # Copyright (c) 2011 The Chromium OS Authors. # -import re import os -import subprocess import sys from patman import command from patman import settings from patman import terminal -from patman import tools # True to use --no-decorate - we check this in setup() use_no_decorate = True + def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False, - count=None): + count=None): """Create a command to perform a 'git log' Args: @@ -49,6 +47,7 @@ def log_cmd(commit_range, git_dir=None, oneline=False, reverse=False, cmd.append('--') return cmd + def count_commits_to_branch(branch): """Returns number of commits between HEAD and the tracking branch. @@ -68,13 +67,14 @@ def count_commits_to_branch(branch): rev_range = '@{upstream}..' pipe = [log_cmd(rev_range, oneline=True)] result = command.run_pipe(pipe, capture=True, capture_stderr=True, - oneline=True, raise_on_error=False) + oneline=True, raise_on_error=False) if result.return_code: raise ValueError('Failed to determine upstream: %s' % result.stderr.strip()) patch_count = len(result.stdout.splitlines()) return patch_count + def name_revision(commit_hash): """Gets the revision name for a commit @@ -91,6 +91,7 @@ def name_revision(commit_hash): name = stdout.split(' ')[1].strip() return name + def guess_upstream(git_dir, branch): """Tries to guess the upstream for a branch @@ -109,7 +110,7 @@ def guess_upstream(git_dir, branch): """ pipe = [log_cmd(branch, git_dir=git_dir, oneline=True, count=100)] result = command.run_pipe(pipe, capture=True, capture_stderr=True, - raise_on_error=False) + raise_on_error=False) if result.return_code: return None, "Branch '%s' not found" % branch for line in result.stdout.splitlines()[1:]: @@ -121,6 +122,7 @@ def guess_upstream(git_dir, branch): return name, "Guessing upstream as '%s'" % name return None, "Cannot find a suitable upstream for branch '%s'" % branch + def get_upstream(git_dir, branch): """Returns the name of the upstream for a branch @@ -135,10 +137,10 @@ def get_upstream(git_dir, branch): """ try: remote = command.output_one_line('git', '--git-dir', git_dir, 'config', - 'branch.%s.remote' % branch) + 'branch.%s.remote' % branch) merge = command.output_one_line('git', '--git-dir', git_dir, 'config', - 'branch.%s.merge' % branch) - except: + 'branch.%s.merge' % branch) + except Exception: upstream, msg = guess_upstream(git_dir, branch) return upstream, msg @@ -149,7 +151,8 @@ def get_upstream(git_dir, branch): return '%s/%s' % (remote, leaf), None else: raise ValueError("Cannot determine upstream branch for branch " - "'%s' remote='%s', merge='%s'" % (branch, remote, merge)) + "'%s' remote='%s', merge='%s'" + % (branch, remote, merge)) def get_range_in_branch(git_dir, branch, include_upstream=False): @@ -168,6 +171,7 @@ def get_range_in_branch(git_dir, branch, include_upstream=False): rstr = '%s%s..%s' % (upstream, '~' if include_upstream else '', branch) return rstr, msg + def count_commits_in_range(git_dir, range_expr): """Returns the number of commits in the given range. @@ -180,12 +184,13 @@ def count_commits_in_range(git_dir, range_expr): """ pipe = [log_cmd(range_expr, git_dir=git_dir, oneline=True)] result = command.run_pipe(pipe, capture=True, capture_stderr=True, - raise_on_error=False) + raise_on_error=False) if result.return_code: return None, "Range '%s' not found or is invalid" % range_expr patch_count = len(result.stdout.splitlines()) return patch_count, None + def count_commits_in_branch(git_dir, branch, include_upstream=False): """Returns the number of commits in the given branch. @@ -201,6 +206,7 @@ def count_commits_in_branch(git_dir, branch, include_upstream=False): return None, msg return count_commits_in_range(git_dir, range_expr) + def count_commits(commit_range): """Returns the number of commits in the given range. @@ -215,6 +221,7 @@ def count_commits(commit_range): patch_count = int(stdout) return patch_count + def checkout(commit_hash, git_dir=None, work_tree=None, force=False): """Checkout the selected commit for this build @@ -231,10 +238,11 @@ def checkout(commit_hash, git_dir=None, work_tree=None, force=False): pipe.append('-f') pipe.append(commit_hash) result = command.run_pipe([pipe], capture=True, raise_on_error=False, - capture_stderr=True) + capture_stderr=True) if result.return_code != 0: raise OSError('git checkout (%s): %s' % (pipe, result.stderr)) + def clone(git_dir, output_dir): """Checkout the selected commit for this build @@ -243,10 +251,11 @@ def clone(git_dir, output_dir): """ pipe = ['git', 'clone', git_dir, '.'] result = command.run_pipe([pipe], capture=True, cwd=output_dir, - capture_stderr=True) + capture_stderr=True) if result.return_code != 0: raise OSError('git clone: %s' % result.stderr) + def fetch(git_dir=None, work_tree=None): """Fetch from the origin repo @@ -263,6 +272,7 @@ def fetch(git_dir=None, work_tree=None): if result.return_code != 0: raise OSError('git fetch: %s' % result.stderr) + def check_worktree_is_available(git_dir): """Check if git-worktree functionality is available @@ -274,9 +284,10 @@ def check_worktree_is_available(git_dir): """ pipe = ['git', '--git-dir', git_dir, 'worktree', 'list'] result = command.run_pipe([pipe], capture=True, capture_stderr=True, - raise_on_error=False) + raise_on_error=False) return result.return_code == 0 + def add_worktree(git_dir, output_dir, commit_hash=None): """Create and checkout a new git worktree for this build @@ -290,10 +301,11 @@ def add_worktree(git_dir, output_dir, commit_hash=None): if commit_hash: pipe.append(commit_hash) result = command.run_pipe([pipe], capture=True, cwd=output_dir, - capture_stderr=True) + capture_stderr=True) if result.return_code != 0: raise OSError('git worktree add: %s' % result.stderr) + def prune_worktrees(git_dir): """Remove administrative files for deleted worktrees @@ -305,7 +317,8 @@ def prune_worktrees(git_dir): if result.return_code != 0: raise OSError('git worktree prune: %s' % result.stderr) -def create_patches(branch, start, count, ignore_binary, series, signoff = True): + +def create_patches(branch, start, count, ignore_binary, series, signoff=True): """Create a series of patches from the top of the current branch. The patch files are written to the current directory using @@ -321,9 +334,7 @@ def create_patches(branch, start, count, ignore_binary, series, signoff = True): Filename of cover letter (None if none) List of filenames of patch files """ - if series.get('version'): - version = '%s ' % series['version'] - cmd = ['git', 'format-patch', '-M' ] + cmd = ['git', 'format-patch', '-M'] if signoff: cmd.append('--signoff') if ignore_binary: @@ -341,9 +352,10 @@ def create_patches(branch, start, count, ignore_binary, series, signoff = True): # We have an extra file if there is a cover letter if series.get('cover'): - return files[0], files[1:] + return files[0], files[1:] else: - return None, files + return None, files + def build_email_list(in_list, tag=None, alias=None, warn_on_error=True): """Build a list of email addresses based on an input list. @@ -385,40 +397,43 @@ def build_email_list(in_list, tag=None, alias=None, warn_on_error=True): raw += lookup_email(item, alias, warn_on_error=warn_on_error) result = [] for item in raw: - if not item in result: + if item not in result: result.append(item) if tag: return ['%s %s%s%s' % (tag, quote, email, quote) for email in result] return result + def check_suppress_cc_config(): """Check if sendemail.suppresscc is configured correctly. Returns: True if the option is configured correctly, False otherwise. """ - suppresscc = command.output_one_line('git', 'config', 'sendemail.suppresscc', - raise_on_error=False) + suppresscc = command.output_one_line( + 'git', 'config', 'sendemail.suppresscc', raise_on_error=False) # Other settings should be fine. if suppresscc == 'all' or suppresscc == 'cccmd': col = terminal.Color() print((col.build(col.RED, "error") + - ": git config sendemail.suppresscc set to %s\n" % (suppresscc)) + - " patman needs --cc-cmd to be run to set the cc list.\n" + - " Please run:\n" + - " git config --unset sendemail.suppresscc\n" + - " Or read the man page:\n" + - " git send-email --help\n" + - " and set an option that runs --cc-cmd\n") + ": git config sendemail.suppresscc set to %s\n" + % (suppresscc)) + + " patman needs --cc-cmd to be run to set the cc list.\n" + + " Please run:\n" + + " git config --unset sendemail.suppresscc\n" + + " Or read the man page:\n" + + " git send-email --help\n" + + " and set an option that runs --cc-cmd\n") return False return True + def email_patches(series, cover_fname, args, dry_run, warn_on_error, cc_fname, - self_only=False, alias=None, in_reply_to=None, thread=False, - smtp_server=None): + self_only=False, alias=None, in_reply_to=None, thread=False, + smtp_server=None): """Email a patch series. Args: @@ -487,9 +502,10 @@ send --cc-cmd cc-fname" cover p1 p2' "git config sendemail.to u-boot@lists.denx.de") return cc = build_email_list(list(set(series.get('cc')) - set(series.get('to'))), - '--cc', alias, warn_on_error) + '--cc', alias, warn_on_error) if self_only: - to = build_email_list([os.getenv('USER')], '--to', alias, warn_on_error) + to = build_email_list([os.getenv('USER')], '--to', + alias, warn_on_error) cc = [] cmd = ['git', 'send-email', '--annotate'] if smtp_server: @@ -565,7 +581,7 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0): if not alias: alias = settings.alias lookup_name = lookup_name.strip() - if '@' in lookup_name: # Perhaps a real email address + if '@' in lookup_name: # Perhaps a real email address return [lookup_name] lookup_name = lookup_name.lower() @@ -581,7 +597,7 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0): return out_list if lookup_name: - if not lookup_name in alias: + if lookup_name not in alias: msg = "Alias '%s' not found" % lookup_name if warn_on_error: print(col.build(col.RED, msg)) @@ -589,11 +605,12 @@ def lookup_email(lookup_name, alias=None, warn_on_error=True, level=0): for item in alias[lookup_name]: todo = lookup_email(item, alias, warn_on_error, level + 1) for new_item in todo: - if not new_item in out_list: + if new_item not in out_list: out_list.append(new_item) return out_list + def get_top_level(): """Return name of top-level directory for this git repo. @@ -608,6 +625,7 @@ def get_top_level(): """ return command.output_one_line('git', 'rev-parse', '--show-toplevel') + def get_alias_file(): """Gets the name of the git alias file. @@ -615,7 +633,7 @@ def get_alias_file(): Filename of git alias file, or None if none """ fname = command.output_one_line('git', 'config', 'sendemail.aliasesfile', - raise_on_error=False) + raise_on_error=False) if not fname: return None @@ -625,6 +643,7 @@ def get_alias_file(): return os.path.join(get_top_level(), fname) + def get_default_user_name(): """Gets the user.name from .gitconfig file. @@ -634,6 +653,7 @@ def get_default_user_name(): uname = command.output_one_line('git', 'config', '--global', 'user.name') return uname + def get_default_user_email(): """Gets the user.email from the global .gitconfig file. @@ -643,17 +663,19 @@ def get_default_user_email(): uemail = command.output_one_line('git', 'config', '--global', 'user.email') return uemail + def get_default_subject_prefix(): """Gets the format.subjectprefix from local .git/config file. Returns: Subject prefix found in local .git/config file, or None if none """ - sub_prefix = command.output_one_line('git', 'config', 'format.subjectprefix', - raise_on_error=False) + sub_prefix = command.output_one_line( + 'git', 'config', 'format.subjectprefix', raise_on_error=False) return sub_prefix + def setup(): """Set up git utils, by reading the alias files.""" # Check for a git alias file also @@ -666,6 +688,7 @@ def setup(): use_no_decorate = (command.run_pipe([cmd], raise_on_error=False) .return_code == 0) + def get_head(): """Get the hash of the current HEAD @@ -674,6 +697,7 @@ def get_head(): """ return command.output_one_line('git', 'show', '-s', '--pretty=format:%H') + if __name__ == "__main__": import doctest From 1c77598402890ef148c5e114bb5a3a475305ced8 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:39 -0500 Subject: [PATCH 403/424] patman: locate test data files via __file__ and pathlib Previously it would rely on the executing script location, which could break for example when running the tests via 'pytest'. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/func_test.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index 7b92bc67be..7fa4a00786 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -7,6 +7,7 @@ """Functional tests for checking that patman behaves correctly""" import os +import pathlib import re import shutil import sys @@ -28,6 +29,10 @@ from patman.test_util import capture_sys_output import pygit2 from patman import status + +TEST_DATA_DIR = pathlib.Path(__file__).parent / 'test/' + + class TestFunctional(unittest.TestCase): """Functional tests for checking that patman behaves correctly""" leb = (b'Lord Edmund Blackadd\xc3\xabr '. @@ -57,8 +62,7 @@ class TestFunctional(unittest.TestCase): Returns: str: Full path to file in the test directory """ - return os.path.join(os.path.dirname(os.path.realpath(sys.argv[0])), - 'test', fname) + return TEST_DATA_DIR / fname @classmethod def _get_text(cls, fname): From 648d8186dd7f9c444fb07f355090d275dcdd4de4 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:40 -0500 Subject: [PATCH 404/424] patman: invoke the checkpatch.pl script with '--u-boot' and '--strict' This resolves 10 out of 11 test failures seen when running './patman test' from the 'tools/patman' subdirectory. This was caused by the .checkpatch.conf configuration file at the root of the project not being picked up. Make the test suite of patman independent from it by always invoking the checkpatch.pl script with the minimally required arguments for the test suite to pass. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/checkpatch.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index d1b902dd96..012c0d895c 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -211,7 +211,7 @@ def check_patch(fname, verbose=False, show_types=False, use_tree=False): stdout: Full output of checkpatch """ chk = find_check_patch() - args = [chk] + args = [chk, '--u-boot', '--strict'] if not use_tree: args.append('--no-tree') if show_types: From 579916beb133ad74377964643c65c57fb3174cc6 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:41 -0500 Subject: [PATCH 405/424] patman: rename main script to __main__.py This allows running the package as a Python module, like e.g.: $ python -m patman It also prevents Pytest from attempting to parse main.py, which would cause errors. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer Fix up main.py in __init__.py: Signed-off-by: Simon Glass --- tools/patman/__init__.py | 2 +- tools/patman/{main.py => __main__.py} | 0 tools/patman/patman | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename tools/patman/{main.py => __main__.py} (100%) diff --git a/tools/patman/__init__.py b/tools/patman/__init__.py index c9d3e35052..1b98ec7fee 100644 --- a/tools/patman/__init__.py +++ b/tools/patman/__init__.py @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ __all__ = ['checkpatch', 'command', 'commit', 'control', 'cros_subprocess', - 'func_test', 'get_maintainer', 'gitutil', 'main', 'patchstream', + 'func_test', 'get_maintainer', 'gitutil', '__main__', 'patchstream', 'project', 'series', 'setup', 'settings', 'terminal', 'test_checkpatch', 'test_util', 'tools', 'tout'] diff --git a/tools/patman/main.py b/tools/patman/__main__.py similarity index 100% rename from tools/patman/main.py rename to tools/patman/__main__.py diff --git a/tools/patman/patman b/tools/patman/patman index 11a5d8e18a..5a427d1942 120000 --- a/tools/patman/patman +++ b/tools/patman/patman @@ -1 +1 @@ -main.py \ No newline at end of file +__main__.py \ No newline at end of file From a3997a0a00a03a85fd0ad4ca147763f17ba88b5b Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:42 -0500 Subject: [PATCH 406/424] patman: add pytest configuration file With this change, a user can run the patman test suite using Pytest the same as when using 'patman test': $ cd tools/patman && pytest [...] 44 passed, 8 warnings in 8.87s $ ./patman test Ran 44 tests in 8.460s Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/pytest.ini | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 tools/patman/pytest.ini diff --git a/tools/patman/pytest.ini b/tools/patman/pytest.ini new file mode 100644 index 0000000000..df3eb518d0 --- /dev/null +++ b/tools/patman/pytest.ini @@ -0,0 +1,2 @@ +[pytest] +addopts = --doctest-modules From 52c1c333eaade606be03a6087a348f8f37843f62 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:43 -0500 Subject: [PATCH 407/424] patman: hide the 'test' command unless test data is available Some tests would fail when the test data is not available, so it doesn't make much sense to expose the action when patman is running outside of the u-boot git checkout. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/__main__.py | 9 ++++++--- tools/patman/patman.rst | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index 2a2a7eaa24..70968f661b 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -20,6 +20,7 @@ if __name__ == "__main__": # Our modules from patman import control +from patman import func_test from patman import gitutil from patman import project from patman import settings @@ -95,9 +96,11 @@ send.add_argument('--smtp-server', type=str, send.add_argument('patchfiles', nargs='*') -test_parser = subparsers.add_parser('test', help='Run tests') -test_parser.add_argument('testname', type=str, default=None, nargs='?', - help="Specify the test to run") +# Only add the 'test' action if the test data files are available. +if os.path.exists(func_test.TEST_DATA_DIR): + test_parser = subparsers.add_parser('test', help='Run tests') + test_parser.add_argument('testname', type=str, default=None, nargs='?', + help="Specify the test to run") status = subparsers.add_parser('status', help='Check status of patches in patchwork') diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index 8c5c9cc2cc..ff4c8b3ed2 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -680,6 +680,10 @@ them: $ tools/patman/patman test +Note that since the test suite depends on data files only available in +the git checkout, the `test` command is hidden unless `patman` is +invoked from the U-Boot git repository. + Error handling doesn't always produce friendly error messages - e.g. putting an incorrect tag in a commit may provide a confusing message. From f393f59e5d222711b9f35a8d2d32f4ba374d4134 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:44 -0500 Subject: [PATCH 408/424] patman: document how to run test suite via pytest Pytest offers useful features such as selecting tests by means of a regular expression, or running the pdb debugger upon encountering a test failure. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/patman.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index ff4c8b3ed2..395fc0cd75 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -684,6 +684,12 @@ Note that since the test suite depends on data files only available in the git checkout, the `test` command is hidden unless `patman` is invoked from the U-Boot git repository. +Alternatively, you can run the test suite via Pytest: + +.. code-block:: bash + + $ cd tools/patman && pytest + Error handling doesn't always produce friendly error messages - e.g. putting an incorrect tag in a commit may provide a confusing message. From 30529307141339d4780bddb3557c115fbf1f51c1 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Mon, 19 Dec 2022 17:32:45 -0500 Subject: [PATCH 409/424] patman: document default 'send' command Document that this command is the default and what it's intended for. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/__main__.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index 70968f661b..ece59c5a62 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -55,7 +55,8 @@ parser.add_argument('-H', '--full-help', action='store_true', dest='full_help', default=False, help='Display the README file') subparsers = parser.add_subparsers(dest='cmd') -send = subparsers.add_parser('send') +send = subparsers.add_parser( + 'send', help='Format, check and email patches (default command)') send.add_argument('-i', '--ignore-errors', action='store_true', dest='ignore_errors', default=False, help='Send patches email even if patch errors are found') From 872f3a4ce245e9573a9572971074a8e57c1f6022 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:38:36 -0500 Subject: [PATCH 410/424] patman: fix pep8 warnings in settings module Remove extraneous imports, variables and comply to PEP 8 maximum line width, among other PEP 8 changes suggested by Pyflake. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/settings.py | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 903d6fcb0b..b6884a073e 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -4,16 +4,13 @@ try: import configparser as ConfigParser -except: +except Exception: import ConfigParser import argparse import os import re -from patman import command -from patman import tools - """Default settings per-project. These are used by _ProjectConfigParser. Settings names should match @@ -32,6 +29,7 @@ _default_settings = { }, } + class _ProjectConfigParser(ConfigParser.SafeConfigParser): """ConfigParser that handles projects. @@ -83,8 +81,8 @@ class _ProjectConfigParser(ConfigParser.SafeConfigParser): def __init__(self, project_name): """Construct _ProjectConfigParser. - In addition to standard SafeConfigParser initialization, this also loads - project defaults. + In addition to standard SafeConfigParser initialization, this + also loads project defaults. Args: project_name: The name of the project. @@ -155,6 +153,7 @@ class _ProjectConfigParser(ConfigParser.SafeConfigParser): item_dict.update(project_items) return {(item, val) for item, val in item_dict.items()} + def ReadGitAliases(fname): """Read a git alias file. This is in the form used by git: @@ -170,7 +169,7 @@ def ReadGitAliases(fname): print("Warning: Cannot find alias file '%s'" % fname) return - re_line = re.compile('alias\s+(\S+)\s+(.*)') + re_line = re.compile(r'alias\s+(\S+)\s+(.*)') for line in fd.readlines(): line = line.strip() if not line or line[0] == '#': @@ -190,6 +189,7 @@ def ReadGitAliases(fname): fd.close() + def CreatePatmanConfigFile(gitutil, config_fname): """Creates a config file under $(HOME)/.patman if it can't find one. @@ -200,12 +200,12 @@ def CreatePatmanConfigFile(gitutil, config_fname): None """ name = gitutil.get_default_user_name() - if name == None: + if name is None: name = input("Enter name: ") email = gitutil.get_default_user_email() - if email == None: + if email is None: email = input("Enter email: ") try: @@ -220,7 +220,8 @@ me: %s <%s> [bounces] nxp = Zhikang Zhang ''' % (name, email), file=f) - f.close(); + f.close() + def _UpdateDefaults(main_parser, config): """Update the given OptionParser defaults based on config. @@ -242,8 +243,8 @@ def _UpdateDefaults(main_parser, config): # Find all the parsers and subparsers parsers = [main_parser] parsers += [subparser for action in main_parser._actions - if isinstance(action, argparse._SubParsersAction) - for _, subparser in action.choices.items()] + if isinstance(action, argparse._SubParsersAction) + for _, subparser in action.choices.items()] # Collect the defaults from each parser defaults = {} @@ -270,8 +271,9 @@ def _UpdateDefaults(main_parser, config): # Set all the defaults and manually propagate them to subparsers main_parser.set_defaults(**defaults) for parser, pdefs in zip(parsers, parser_defaults): - parser.set_defaults(**{ k: v for k, v in defaults.items() - if k in pdefs }) + parser.set_defaults(**{k: v for k, v in defaults.items() + if k in pdefs}) + def _ReadAliasFile(fname): """Read in the U-Boot git alias file if it exists. @@ -298,6 +300,7 @@ def _ReadAliasFile(fname): if bad_line: print(bad_line) + def _ReadBouncesFile(fname): """Read in the bounces file if it exists @@ -311,6 +314,7 @@ def _ReadBouncesFile(fname): continue bounces.add(line.strip()) + def GetItems(config, section): """Get the items from a section of the config. @@ -323,10 +327,9 @@ def GetItems(config, section): """ try: return config.items(section) - except ConfigParser.NoSectionError as e: + except ConfigParser.NoSectionError: return [] - except: - raise + def Setup(gitutil, parser, project_name, config_fname=''): """Set up the settings module by reading config files. @@ -358,6 +361,7 @@ def Setup(gitutil, parser, project_name, config_fname=''): _UpdateDefaults(parser, config) + # These are the aliases we understand, indexed by alias. Each member is a list. alias = {} bounces = set() From 8b73f9bf9e979b47aa4f7dcbd6727945a0da02f8 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:38:37 -0500 Subject: [PATCH 411/424] patman: replace deprecated SafeConfigParser with ConfigParser The SafeConfigParser class has been renamed in Python 3.2 to ConfigParser, and the old alias has been deprecated since. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/settings.py | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/tools/patman/settings.py b/tools/patman/settings.py index b6884a073e..7fb9d6d5a0 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -30,7 +30,7 @@ _default_settings = { } -class _ProjectConfigParser(ConfigParser.SafeConfigParser): +class _ProjectConfigParser(ConfigParser.ConfigParser): """ConfigParser that handles projects. There are two main goals of this class: @@ -81,14 +81,14 @@ class _ProjectConfigParser(ConfigParser.SafeConfigParser): def __init__(self, project_name): """Construct _ProjectConfigParser. - In addition to standard SafeConfigParser initialization, this - also loads project defaults. + In addition to standard ConfigParser initialization, this also + loads project defaults. Args: project_name: The name of the project. """ self._project_name = project_name - ConfigParser.SafeConfigParser.__init__(self) + ConfigParser.ConfigParser.__init__(self) # Update the project settings in the config based on # the _default_settings global. @@ -100,31 +100,31 @@ class _ProjectConfigParser(ConfigParser.SafeConfigParser): self.set(project_settings, setting_name, setting_value) def get(self, section, option, *args, **kwargs): - """Extend SafeConfigParser to try project_section before section. + """Extend ConfigParser to try project_section before section. Args: - See SafeConfigParser. + See ConfigParser. Returns: - See SafeConfigParser. + See ConfigParser. """ try: - val = ConfigParser.SafeConfigParser.get( + val = ConfigParser.ConfigParser.get( self, "%s_%s" % (self._project_name, section), option, *args, **kwargs ) except (ConfigParser.NoSectionError, ConfigParser.NoOptionError): - val = ConfigParser.SafeConfigParser.get( + val = ConfigParser.ConfigParser.get( self, section, option, *args, **kwargs ) return val def items(self, section, *args, **kwargs): - """Extend SafeConfigParser to add project_section to section. + """Extend ConfigParser to add project_section to section. Args: - See SafeConfigParser. + See ConfigParser. Returns: - See SafeConfigParser. + See ConfigParser. """ project_items = [] has_project_section = False @@ -132,7 +132,7 @@ class _ProjectConfigParser(ConfigParser.SafeConfigParser): # Get items from the project section try: - project_items = ConfigParser.SafeConfigParser.items( + project_items = ConfigParser.ConfigParser.items( self, "%s_%s" % (self._project_name, section), *args, **kwargs ) has_project_section = True @@ -141,7 +141,7 @@ class _ProjectConfigParser(ConfigParser.SafeConfigParser): # Get top-level items try: - top_items = ConfigParser.SafeConfigParser.items( + top_items = ConfigParser.ConfigParser.items( self, section, *args, **kwargs ) except ConfigParser.NoSectionError: From 57e3b03fe1ea225eb45ccfa3b0f2d564d95a4717 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:38:38 -0500 Subject: [PATCH 412/424] patman: import gitutil module where it is needed Instead of propagating it from the module entry point (main script). Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/__main__.py | 3 +-- tools/patman/settings.py | 8 +++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index ece59c5a62..8e32655ad2 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -21,7 +21,6 @@ if __name__ == "__main__": # Our modules from patman import control from patman import func_test -from patman import gitutil from patman import project from patman import settings from patman import terminal @@ -118,7 +117,7 @@ status.add_argument('-f', '--force', action='store_true', argv = sys.argv[1:] args, rest = parser.parse_known_args(argv) if hasattr(args, 'project'): - settings.Setup(gitutil, parser, args.project, '') + settings.Setup(parser, args.project, '') args, rest = parser.parse_known_args(argv) # If we have a command, it is safe to parse all arguments diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 7fb9d6d5a0..5efad5ed78 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -11,6 +11,8 @@ import argparse import os import re +from patman import gitutil + """Default settings per-project. These are used by _ProjectConfigParser. Settings names should match @@ -190,7 +192,7 @@ def ReadGitAliases(fname): fd.close() -def CreatePatmanConfigFile(gitutil, config_fname): +def CreatePatmanConfigFile(config_fname): """Creates a config file under $(HOME)/.patman if it can't find one. Args: @@ -331,7 +333,7 @@ def GetItems(config, section): return [] -def Setup(gitutil, parser, project_name, config_fname=''): +def Setup(parser, project_name, config_fname=''): """Set up the settings module by reading config files. Args: @@ -348,7 +350,7 @@ def Setup(gitutil, parser, project_name, config_fname=''): if not os.path.exists(config_fname): print("No config file found ~/.patman\nCreating one...\n") - CreatePatmanConfigFile(gitutil, config_fname) + CreatePatmanConfigFile(config_fname) config.read(config_fname) From 2c58a5e2753e4f0afc4c937b07b9380398bbe8fd Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:38:39 -0500 Subject: [PATCH 413/424] patman: set the default config_fname argument value to None This better matches Python conventions, allowing to easily test whether the optional argument is provided. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/__main__.py | 2 +- tools/patman/settings.py | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index 8e32655ad2..37489304f7 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -117,7 +117,7 @@ status.add_argument('-f', '--force', action='store_true', argv = sys.argv[1:] args, rest = parser.parse_known_args(argv) if hasattr(args, 'project'): - settings.Setup(parser, args.project, '') + settings.Setup(parser, args.project) args, rest = parser.parse_known_args(argv) # If we have a command, it is safe to parse all arguments diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 5efad5ed78..8b846799df 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -333,19 +333,20 @@ def GetItems(config, section): return [] -def Setup(parser, project_name, config_fname=''): +def Setup(parser, project_name, config_fname=None): """Set up the settings module by reading config files. Args: - parser: The parser to update + parser: The parser to update. project_name: Name of project that we're working on; we'll look for sections named "project_section" as well. - config_fname: Config filename to read ('' for default) + config_fname: Config filename to read. """ # First read the git alias file if available _ReadAliasFile('doc/git-mailrc') config = _ProjectConfigParser(project_name) - if config_fname == '': + + if not config_fname: config_fname = '%s/.patman' % os.getenv('HOME') if not os.path.exists(config_fname): From db16edd8ced27c06c075999ef95c6a1a57db98e0 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:38:40 -0500 Subject: [PATCH 414/424] patman: fail early in Setup when provided config file does not exist Rationale: if the user explicitly provide this argument, they probably intend for it to be used. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/settings.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/patman/settings.py b/tools/patman/settings.py index 8b846799df..c05efd2475 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -340,12 +340,16 @@ def Setup(parser, project_name, config_fname=None): parser: The parser to update. project_name: Name of project that we're working on; we'll look for sections named "project_section" as well. - config_fname: Config filename to read. + config_fname: Config filename to read. An error is raised if it + does not exist. """ # First read the git alias file if available _ReadAliasFile('doc/git-mailrc') config = _ProjectConfigParser(project_name) + if config_fname and not os.path.exists(config_fname): + raise Exception(f'provided {config_fname} does not exist') + if not config_fname: config_fname = '%s/.patman' % os.getenv('HOME') From 8f8d3f72f28732bff0dc6362a18e3ec55fba2ac1 Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:38:41 -0500 Subject: [PATCH 415/424] patman: additionally honor a local .patman config file This enables versioning a project specific patman configuration file. It also makes it possible to declare the project name, which is not a useful thing to do in $HOME/.patman. A new test is added, along updated documentation. Signed-off-by: Maxim Cournoyer Reviewed-by: Simon Glass --- tools/patman/patman.rst | 8 ++++- tools/patman/settings.py | 24 ++++++++++--- tools/patman/test_settings.py | 67 +++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 5 deletions(-) create mode 100644 tools/patman/test_settings.py diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index 395fc0cd75..d7994c888b 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -74,7 +74,7 @@ out where to send patches pretty well. During the first run patman creates a config file for you by taking the default user name and email address from the global .gitconfig file. -To add your own, create a file ~/.patman like this:: +To add your own, create a file `~/.patman` like this:: # patman alias file @@ -85,6 +85,12 @@ To add your own, create a file ~/.patman like this:: wolfgang: Wolfgang Denk others: Mike Frysinger , Fred Bloggs +Patman will also look for a `.patman` configuration file at the root +of the current project git repository, which makes it possible to +override the `project` settings variable or anything else in a +project-specific way. The values of this "local" configuration file +take precedence over those of the "global" one. + Aliases are recursive. The checkpatch.pl in the U-Boot tools/ subdirectory will be located and diff --git a/tools/patman/settings.py b/tools/patman/settings.py index c05efd2475..636983e32d 100644 --- a/tools/patman/settings.py +++ b/tools/patman/settings.py @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (c) 2011 The Chromium OS Authors. +# Copyright (c) 2022 Maxim Cournoyer # try: @@ -336,6 +337,12 @@ def GetItems(config, section): def Setup(parser, project_name, config_fname=None): """Set up the settings module by reading config files. + Unless `config_fname` is specified, a `.patman` config file local + to the git repository is consulted, followed by the global + `$HOME/.patman`. If none exists, the later is created. Values + defined in the local config file take precedence over those + defined in the global one. + Args: parser: The parser to update. project_name: Name of project that we're working on; we'll look @@ -352,13 +359,22 @@ def Setup(parser, project_name, config_fname=None): if not config_fname: config_fname = '%s/.patman' % os.getenv('HOME') + has_config = os.path.exists(config_fname) - if not os.path.exists(config_fname): - print("No config file found ~/.patman\nCreating one...\n") + git_local_config_fname = os.path.join(gitutil.get_top_level(), '.patman') + has_git_local_config = os.path.exists(git_local_config_fname) + + # Read the git local config last, so that its values override + # those of the global config, if any. + if has_config: + config.read(config_fname) + if has_git_local_config: + config.read(git_local_config_fname) + + if not (has_config or has_git_local_config): + print("No config file found.\nCreating ~/.patman...\n") CreatePatmanConfigFile(config_fname) - config.read(config_fname) - for name, value in GetItems(config, 'alias'): alias[name] = value.split(',') diff --git a/tools/patman/test_settings.py b/tools/patman/test_settings.py new file mode 100644 index 0000000000..c768a2fc64 --- /dev/null +++ b/tools/patman/test_settings.py @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2022 Maxim Cournoyer +# + +import argparse +import contextlib +import os +import sys +import tempfile + +from patman import settings +from patman import tools + + +@contextlib.contextmanager +def empty_git_repository(): + with tempfile.TemporaryDirectory() as tmpdir: + os.chdir(tmpdir) + tools.run('git', 'init', raise_on_error=True) + yield tmpdir + + +@contextlib.contextmanager +def cleared_command_line_args(): + old_value = sys.argv[:] + sys.argv = [sys.argv[0]] + try: + yield + finally: + sys.argv = old_value + + +def test_git_local_config(): + # Clearing the command line arguments is required, otherwise + # arguments passed to the test running such as in 'pytest -k + # filter' would be processed by _UpdateDefaults and fail. + with cleared_command_line_args(): + with empty_git_repository(): + with tempfile.NamedTemporaryFile() as global_config: + global_config.write(b'[settings]\n' + b'project=u-boot\n') + global_config.flush() + parser = argparse.ArgumentParser() + parser.add_argument('-p', '--project', default='unknown') + subparsers = parser.add_subparsers(dest='cmd') + send = subparsers.add_parser('send') + send.add_argument('--no-check', action='store_false', + dest='check_patch', default=True) + + # Test "global" config is used. + settings.Setup(parser, 'unknown', global_config.name) + args, _ = parser.parse_known_args([]) + assert args.project == 'u-boot' + send_args, _ = send.parse_known_args([]) + assert send_args.check_patch + + # Test local config can shadow it. + with open('.patman', 'w', buffering=1) as f: + f.write('[settings]\n' + 'project: guix-patches\n' + 'check_patch: False\n') + settings.Setup(parser, 'unknown', global_config.name) + args, _ = parser.parse_known_args([]) + assert args.project == 'guix-patches' + send_args, _ = send.parse_known_args([]) + assert not send_args.check_patch From 8c042fb7f9f475367804b26a892fd522ad8fcfcc Mon Sep 17 00:00:00 2001 From: Maxim Cournoyer Date: Tue, 20 Dec 2022 00:28:46 -0500 Subject: [PATCH 416/424] patman: add '--get-maintainer-script' argument This makes it possible to configure a project to use some other location or script than the default scripts/get_maintainer.pl one used in the U-Boot and Linux projects. It can be configured via a .patman configuration file and accepts arguments, as documented. Reviewed-by: Simon Glass Signed-off-by: Maxim Cournoyer --- tools/patman/__main__.py | 7 +++++ tools/patman/control.py | 12 ++++--- tools/patman/func_test.py | 49 +++++++++++++++++++++++++++-- tools/patman/get_maintainer.py | 57 +++++++++++++++++++++------------- tools/patman/gitutil.py | 3 +- tools/patman/patman.rst | 30 +++++++++++++----- tools/patman/series.py | 9 ++++-- 7 files changed, 127 insertions(+), 40 deletions(-) diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index 37489304f7..749e6348b6 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -21,6 +21,7 @@ if __name__ == "__main__": # Our modules from patman import control from patman import func_test +from patman import gitutil from patman import project from patman import settings from patman import terminal @@ -64,6 +65,12 @@ send.add_argument('-l', '--limit-cc', dest='limit', type=int, default=None, send.add_argument('-m', '--no-maintainers', action='store_false', dest='add_maintainers', default=True, help="Don't cc the file maintainers automatically") +send.add_argument( + '--get-maintainer-script', dest='get_maintainer_script', type=str, + action='store', + default=os.path.join(gitutil.get_top_level(), 'scripts', + 'get_maintainer.pl') + ' --norolestats', + help='File name of the get_maintainer.pl (or compatible) script.') send.add_argument('-n', '--dry-run', action='store_true', dest='dry_run', default=False, help="Do a dry run (create but don't email patches)") send.add_argument('-r', '--in-reply-to', type=str, action='store', diff --git a/tools/patman/control.py b/tools/patman/control.py index bf426cf7bc..38e98dab84 100644 --- a/tools/patman/control.py +++ b/tools/patman/control.py @@ -94,8 +94,8 @@ def check_patches(series, patch_files, run_checkpatch, verbose, use_tree): def email_patches(col, series, cover_fname, patch_files, process_tags, its_a_go, - ignore_bad_tags, add_maintainers, limit, dry_run, in_reply_to, - thread, smtp_server): + ignore_bad_tags, add_maintainers, get_maintainer_script, limit, + dry_run, in_reply_to, thread, smtp_server): """Email patches to the recipients This emails out the patches and cover letter using 'git send-email'. Each @@ -123,6 +123,8 @@ def email_patches(col, series, cover_fname, patch_files, process_tags, its_a_go, ignore_bad_tags (bool): True to just print a warning for unknown tags, False to halt with an error add_maintainers (bool): Run the get_maintainer.pl script for each patch + get_maintainer_script (str): The script used to retrieve which + maintainers to cc limit (int): Limit on the number of people that can be cc'd on a single patch or the cover letter (None if no limit) dry_run (bool): Don't actually email the patches, just print out what @@ -134,7 +136,7 @@ def email_patches(col, series, cover_fname, patch_files, process_tags, its_a_go, smtp_server (str): SMTP server to use to send patches (None for default) """ cc_file = series.MakeCcFile(process_tags, cover_fname, not ignore_bad_tags, - add_maintainers, limit) + add_maintainers, limit, get_maintainer_script) # Email the patches out (giving the user time to check / cancel) cmd = '' @@ -174,8 +176,8 @@ def send(args): email_patches( col, series, cover_fname, patch_files, args.process_tags, its_a_go, args.ignore_bad_tags, args.add_maintainers, - args.limit, args.dry_run, args.in_reply_to, args.thread, - args.smtp_server) + args.get_maintainer_script, args.limit, args.dry_run, + args.in_reply_to, args.thread, args.smtp_server) def patchwork_status(branch, count, start, end, dest_branch, force, show_comments, url): diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index 7fa4a00786..c25a47bdeb 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -6,6 +6,7 @@ """Functional tests for checking that patman behaves correctly""" +import contextlib import os import pathlib import re @@ -29,8 +30,19 @@ from patman.test_util import capture_sys_output import pygit2 from patman import status +PATMAN_DIR = pathlib.Path(__file__).parent +TEST_DATA_DIR = PATMAN_DIR / 'test/' -TEST_DATA_DIR = pathlib.Path(__file__).parent / 'test/' + +@contextlib.contextmanager +def directory_excursion(directory): + """Change directory to `directory` for a limited to the context block.""" + current = os.getcwd() + try: + os.chdir(directory) + yield + finally: + os.chdir(current) class TestFunctional(unittest.TestCase): @@ -204,6 +216,8 @@ class TestFunctional(unittest.TestCase): text = self._get_text('test01.txt') series = patchstream.get_metadata_for_test(text) cover_fname, args = self._create_patches_for_test(series) + get_maintainer_script = str(pathlib.Path(__file__).parent.parent.parent + / 'get_maintainer.pl') + ' --norolestats' with capture_sys_output() as out: patchstream.fix_patches(series, args) if cover_fname and series.get('cover'): @@ -211,7 +225,7 @@ class TestFunctional(unittest.TestCase): series.DoChecks() cc_file = series.MakeCcFile(process_tags, cover_fname, not ignore_bad_tags, add_maintainers, - None) + None, get_maintainer_script) cmd = gitutil.email_patches( series, cover_fname, args, dry_run, not ignore_bad_tags, cc_file, in_reply_to=in_reply_to, thread=None) @@ -506,6 +520,37 @@ complicated as possible''') finally: os.chdir(orig_dir) + def test_custom_get_maintainer_script(self): + """Validate that a custom get_maintainer script gets used.""" + self.make_git_tree() + with directory_excursion(self.gitdir): + # Setup git. + os.environ['GIT_CONFIG_GLOBAL'] = '/dev/null' + os.environ['GIT_CONFIG_SYSTEM'] = '/dev/null' + tools.run('git', 'config', 'user.name', 'Dummy') + tools.run('git', 'config', 'user.email', 'dumdum@dummy.com') + tools.run('git', 'branch', 'upstream') + tools.run('git', 'branch', '--set-upstream-to=upstream') + tools.run('git', 'add', '.') + tools.run('git', 'commit', '-m', 'new commit') + + # Setup patman configuration. + with open('.patman', 'w', buffering=1) as f: + f.write('[settings]\n' + 'get_maintainer_script: dummy-script.sh\n' + 'check_patch: False\n') + with open('dummy-script.sh', 'w', buffering=1) as f: + f.write('#!/usr/bin/env python\n' + 'print("hello@there.com")\n') + os.chmod('dummy-script.sh', 0x555) + + # Finally, do the test + with capture_sys_output(): + output = tools.run(PATMAN_DIR / 'patman', '--dry-run') + # Assert the email address is part of the dry-run + # output. + self.assertIn('hello@there.com', output) + def test_tags(self): """Test collection of tags in a patchstream""" text = '''This is a patch diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py index e1d15ff6ab..f7011be1e4 100644 --- a/tools/patman/get_maintainer.py +++ b/tools/patman/get_maintainer.py @@ -1,48 +1,61 @@ # SPDX-License-Identifier: GPL-2.0+ # Copyright (c) 2012 The Chromium OS Authors. +# Copyright (c) 2022 Maxim Cournoyer # import os +import shlex +import shutil from patman import command +from patman import gitutil -def find_get_maintainer(try_list): - """Look for the get_maintainer.pl script. - Args: - try_list: List of directories to try for the get_maintainer.pl script +def find_get_maintainer(script_file_name): + """Try to find where `script_file_name` is. - Returns: - If the script is found we'll return a path to it; else None. + It searches in PATH and falls back to a path relative to the top + of the current git repository. """ - # Look in the list - for path in try_list: - fname = os.path.join(path, 'get_maintainer.pl') - if os.path.isfile(fname): - return fname + get_maintainer = shutil.which(script_file_name) + if get_maintainer: + return get_maintainer - return None + git_relative_script = os.path.join(gitutil.get_top_level(), + script_file_name) + if os.path.exists(git_relative_script): + return git_relative_script -def get_maintainer(dir_list, fname, verbose=False): - """Run get_maintainer.pl on a file if we find it. - We look for get_maintainer.pl in the 'scripts' directory at the top of - git. If we find it we'll run it. If we don't find get_maintainer.pl - then we fail silently. +def get_maintainer(script_file_name, fname, verbose=False): + """Run `script_file_name` on a file. + + `script_file_name` should be a get_maintainer.pl-like script that + takes a patch file name as an input and return the email addresses + of the associated maintainers to standard output, one per line. + + If `script_file_name` does not exist we fail silently. Args: - dir_list: List of directories to try for the get_maintainer.pl script - fname: Path to the patch file to run get_maintainer.pl on. + script_file_name: The file name of the get_maintainer.pl script + (or compatible). + fname: File name of the patch to process with get_maintainer.pl. Returns: A list of email addresses to CC to. """ - get_maintainer = find_get_maintainer(dir_list) + # Expand `script_file_name` into a file name and its arguments, if + # any. + cmd_args = shlex.split(script_file_name) + file_name = cmd_args[0] + arguments = cmd_args[1:] + + get_maintainer = find_get_maintainer(file_name) if not get_maintainer: if verbose: print("WARNING: Couldn't find get_maintainer.pl") return [] - stdout = command.output(get_maintainer, '--norolestats', fname) + stdout = command.output(get_maintainer, *arguments, fname) lines = stdout.splitlines() - return [ x.replace('"', '') for x in lines ] + return [x.replace('"', '') for x in lines] diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index 74c6e94494..5e742102c2 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -433,7 +433,7 @@ def check_suppress_cc_config(): def email_patches(series, cover_fname, args, dry_run, warn_on_error, cc_fname, self_only=False, alias=None, in_reply_to=None, thread=False, - smtp_server=None): + smtp_server=None, get_maintainer_script=None): """Email a patch series. Args: @@ -450,6 +450,7 @@ def email_patches(series, cover_fname, args, dry_run, warn_on_error, cc_fname, thread: True to add --thread to git send-email (make all patches reply to cover-letter or first patch in series) smtp_server: SMTP server to use to send patches + get_maintainer_script: File name of script to get maintainers emails Returns: Git command that was/would be run diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst index d7994c888b..6113962fb4 100644 --- a/tools/patman/patman.rst +++ b/tools/patman/patman.rst @@ -1,6 +1,7 @@ .. SPDX-License-Identifier: GPL-2.0+ .. Copyright (c) 2011 The Chromium OS Authors .. Simon Glass +.. Maxim Cournoyer .. v1, v2, 19-Oct-11 .. revised v3 24-Nov-11 .. revised v4 Independence Day 2020, with Patchwork integration @@ -68,8 +69,23 @@ this once:: git config sendemail.aliasesfile doc/git-mailrc -For both Linux and U-Boot the 'scripts/get_maintainer.pl' handles figuring -out where to send patches pretty well. +For both Linux and U-Boot the 'scripts/get_maintainer.pl' handles +figuring out where to send patches pretty well. For other projects, +you may want to specify a different script to be run, for example via +a project-specific `.patman` file:: + + # .patman configuration file at the root of some project + + [settings] + get_maintainer_script: etc/teams.scm get-maintainer + +The `get_maintainer_script` option corresponds to the +`--get-maintainer-script` argument of the `send` command. It is +looked relatively to the root of the current git repository, as well +as on PATH. It can also be provided arguments, as shown above. The +contract is that the script should accept a patch file name and return +a list of email addresses, one per line, like `get_maintainer.pl` +does. During the first run patman creates a config file for you by taking the default user name and email address from the global .gitconfig file. @@ -85,11 +101,11 @@ To add your own, create a file `~/.patman` like this:: wolfgang: Wolfgang Denk others: Mike Frysinger , Fred Bloggs -Patman will also look for a `.patman` configuration file at the root -of the current project git repository, which makes it possible to -override the `project` settings variable or anything else in a -project-specific way. The values of this "local" configuration file -take precedence over those of the "global" one. +As hinted above, Patman will also look for a `.patman` configuration +file at the root of the current project git repository, which makes it +possible to override the `project` settings variable or anything else +in a project-specific way. The values of this "local" configuration +file take precedence over those of the "global" one. Aliases are recursive. diff --git a/tools/patman/series.py b/tools/patman/series.py index 3075378ac1..2eeeef71dc 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -235,7 +235,7 @@ class Series(dict): print(col.build(col.RED, str)) def MakeCcFile(self, process_tags, cover_fname, warn_on_error, - add_maintainers, limit): + add_maintainers, limit, get_maintainer_script): """Make a cc file for us to use for per-commit Cc automation Also stores in self._generated_cc to make ShowActions() faster. @@ -249,6 +249,8 @@ class Series(dict): True/False to call the get_maintainers to CC maintainers List of maintainers to include (for testing) limit: Limit the length of the Cc list (None if no limit) + get_maintainer_script: The file name of the get_maintainer.pl + script (or compatible). Return: Filename of temp file created """ @@ -267,8 +269,9 @@ class Series(dict): if type(add_maintainers) == type(cc): cc += add_maintainers elif add_maintainers: - dir_list = [os.path.join(gitutil.get_top_level(), 'scripts')] - cc += get_maintainer.get_maintainer(dir_list, commit.patch) + + cc += get_maintainer.get_maintainer(get_maintainer_script, + commit.patch) for x in set(cc) & set(settings.bounces): print(col.build(col.YELLOW, 'Skipping "%s"' % x)) cc = list(set(cc) - set(settings.bounces)) From 04fcd2587321177f18203f23cf3d892cd3c8814e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:21:56 +0200 Subject: [PATCH 417/424] mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction The BCH detection hardware can generate ECC bytes for multiple sectors in one go. Use that feature. correct() only corrects one sector at a time so we need to call it repeatedly for each sector. Signed-off-by: Roger Quadros Reviewed-by: Michael Trimarchi Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-2-rogerq@kernel.org --- drivers/mtd/nand/raw/omap_gpmc.c | 323 +++++++++++++++++++++---------- 1 file changed, 222 insertions(+), 101 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index be3cb3c601..feaa739e78 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -27,6 +27,9 @@ #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 +#define ECCSIZE0_SHIFT 12 +#define ECCSIZE1_SHIFT 22 +#define ECC1RESULTSIZE 0x1 #define ECCCLEAR (0x1 << 8) #define ECCRESULTREG1 (0x1 << 0) /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ @@ -186,72 +189,35 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, __maybe_unused static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { - struct nand_chip *nand = mtd_to_nand(mtd); - struct omap_nand_info *info = nand_get_controller_data(nand); + struct nand_chip *nand = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(nand); unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; - unsigned int ecc_algo = 0; - unsigned int bch_type = 0; - unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; - u32 ecc_size_config_val = 0; - u32 ecc_config_val = 0; - int cs = info->cs; + u32 val; - /* configure GPMC for specific ecc-scheme */ - switch (info->ecc_scheme) { - case OMAP_ECC_HAM1_CODE_SW: - return; - case OMAP_ECC_HAM1_CODE_HW: - ecc_algo = 0x0; - bch_type = 0x0; - bch_wrapmode = 0x00; - eccsize0 = 0xFF; - eccsize1 = 0xFF; - break; - case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: - case OMAP_ECC_BCH8_CODE_HW: - ecc_algo = 0x1; - bch_type = 0x1; - if (mode == NAND_ECC_WRITE) { - bch_wrapmode = 0x01; - eccsize0 = 0; /* extra bits in nibbles per sector */ - eccsize1 = 28; /* OOB bits in nibbles per sector */ - } else { - bch_wrapmode = 0x01; - eccsize0 = 26; /* ECC bits in nibbles per sector */ - eccsize1 = 2; /* non-ECC bits in nibbles per sector */ - } - break; - case OMAP_ECC_BCH16_CODE_HW: - ecc_algo = 0x1; - bch_type = 0x2; - if (mode == NAND_ECC_WRITE) { - bch_wrapmode = 0x01; - eccsize0 = 0; /* extra bits in nibbles per sector */ - eccsize1 = 52; /* OOB bits in nibbles per sector */ - } else { - bch_wrapmode = 0x01; - eccsize0 = 52; /* ECC bits in nibbles per sector */ - eccsize1 = 0; /* non-ECC bits in nibbles per sector */ - } - break; - default: - return; - } /* Clear ecc and enable bits */ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - /* Configure ecc size for BCH */ - ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12); - writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config); - /* Configure device details for BCH engine */ - ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */ - (bch_type << 12) | /* BCH4/BCH8/BCH16 */ - (bch_wrapmode << 8) | /* wrap mode */ - (dev_width << 7) | /* bus width */ - (0x0 << 4) | /* number of sectors */ - (cs << 1) | /* ECC CS */ - (0x1)); /* enable ECC */ - writel(ecc_config_val, &gpmc_cfg->ecc_config); + /* program ecc and result sizes */ + val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | + ECC1RESULTSIZE); + writel(val, &gpmc_cfg->ecc_size_config); + + switch (mode) { + case NAND_ECC_READ: + case NAND_ECC_WRITE: + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + break; + case NAND_ECC_READSYN: + writel(ECCCLEAR, &gpmc_cfg->ecc_control); + break; + default: + printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode); + break; + } + + /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ + val = (dev_width << 7) | (info->cs << 1) | (0x1); + writel(val, &gpmc_cfg->ecc_config); } /* @@ -270,6 +236,124 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) */ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) +{ + u32 val; + + val = readl(&gpmc_cfg->ecc1_result); + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); + + return 0; +} + +/* GPMC ecc engine settings for read */ +#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ +#define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ +#define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ +#define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ +#define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ + +/* GPMC ecc engine settings for write */ +#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ +#define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ +#define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ + +/** + * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation + * @mtd: MTD device structure + * @mode: Read/Write mode + * + * When using BCH with SW correction (i.e. no ELM), sector size is set + * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode + * for both reading and writing with: + * eccsize0 = 0 (no additional protected byte in spare area) + * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) + */ +static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, + int mode) +{ + unsigned int bch_type; + unsigned int dev_width, nsectors; + struct nand_chip *chip = mtd_to_nand(mtd); + struct omap_nand_info *info = nand_get_controller_data(chip); + u32 val, wr_mode; + unsigned int ecc_size1, ecc_size0; + + /* GPMC configurations for calculating ECC */ + switch (info->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + bch_type = 1; + nsectors = 1; + wr_mode = BCH_WRAPMODE_6; + ecc_size0 = BCH_ECC_SIZE0; + ecc_size1 = BCH_ECC_SIZE1; + break; + case OMAP_ECC_BCH8_CODE_HW: + bch_type = 1; + nsectors = chip->ecc.steps; + if (mode == NAND_ECC_READ) { + wr_mode = BCH_WRAPMODE_1; + ecc_size0 = BCH8R_ECC_SIZE0; + ecc_size1 = BCH8R_ECC_SIZE1; + } else { + wr_mode = BCH_WRAPMODE_6; + ecc_size0 = BCH_ECC_SIZE0; + ecc_size1 = BCH_ECC_SIZE1; + } + break; + case OMAP_ECC_BCH16_CODE_HW: + bch_type = 0x2; + nsectors = chip->ecc.steps; + if (mode == NAND_ECC_READ) { + wr_mode = 0x01; + ecc_size0 = 52; /* ECC bits in nibbles per sector */ + ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ + } else { + wr_mode = 0x01; + ecc_size0 = 0; /* extra bits in nibbles per sector */ + ecc_size1 = 52; /* OOB bits in nibbles per sector */ + } + break; + default: + return; + } + + writel(ECCRESULTREG1, &gpmc_cfg->ecc_control); + + /* Configure ecc size for BCH */ + val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); + writel(val, &gpmc_cfg->ecc_size_config); + + dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; + + /* BCH configuration */ + val = ((1 << 16) | /* enable BCH */ + (bch_type << 12) | /* BCH4/BCH8/BCH16 */ + (wr_mode << 8) | /* wrap mode */ + (dev_width << 7) | /* bus width */ + (((nsectors - 1) & 0x7) << 4) | /* number of sectors */ + (info->cs << 1) | /* ECC CS */ + (0x1)); /* enable ECC */ + + writel(val, &gpmc_cfg->ecc_config); + + /* Clear ecc and enable bits */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); +} + +/** + * _omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed + * @ecc_code: The ecc_code buffer + * @sector: The sector number (for a multi sector page) + * + * Support calculating of BCH4/8/16 ECC vectors for one sector + * within a page. Sector number is in @sector. + */ +static int _omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, + u8 *ecc_code, int sector) { struct nand_chip *chip = mtd_to_nand(mtd); struct omap_nand_info *info = nand_get_controller_data(chip); @@ -278,17 +362,11 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, int8_t i = 0, j; switch (info->ecc_scheme) { - case OMAP_ECC_HAM1_CODE_HW: - val = readl(&gpmc_cfg->ecc1_result); - ecc_code[0] = val & 0xFF; - ecc_code[1] = (val >> 16) & 0xFF; - ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); - break; #ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: #endif case OMAP_ECC_BCH8_CODE_HW: - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; + ptr = &gpmc_cfg->bch_result_0_3[sector].bch_result_x[3]; val = readl(ptr); ecc_code[i++] = (val >> 0) & 0xFF; ptr--; @@ -300,23 +378,24 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, ecc_code[i++] = (val >> 0) & 0xFF; ptr--; } + break; case OMAP_ECC_BCH16_CODE_HW: - val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); + val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[2]); ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; - val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); + val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[1]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; - val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); + val = readl(&gpmc_cfg->bch_result_4_6[sector].bch_result_x[0]); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; ecc_code[i++] = (val >> 8) & 0xFF; ecc_code[i++] = (val >> 0) & 0xFF; for (j = 3; j >= 0; j--) { - val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] + val = readl(&gpmc_cfg->bch_result_0_3[sector].bch_result_x[j] ); ecc_code[i++] = (val >> 24) & 0xFF; ecc_code[i++] = (val >> 16) & 0xFF; @@ -329,18 +408,18 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, } /* ECC scheme specific syndrome customizations */ switch (info->ecc_scheme) { - case OMAP_ECC_HAM1_CODE_HW: - break; #ifdef CONFIG_BCH case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: - + /* Add constant polynomial to remainder, so that + * ECC of blank pages results in 0x0 on reading back + */ for (i = 0; i < chip->ecc.bytes; i++) - *(ecc_code + i) = *(ecc_code + i) ^ - bch8_polynomial[i]; + ecc_code[i] ^= bch8_polynomial[i]; break; #endif case OMAP_ECC_BCH8_CODE_HW: - ecc_code[chip->ecc.bytes - 1] = 0x00; + /* Set 14th ECC byte as 0x0 for ROM compatibility */ + ecc_code[chip->ecc.bytes - 1] = 0x0; break; case OMAP_ECC_BCH16_CODE_HW: break; @@ -350,6 +429,22 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, return 0; } +/** + * omap_calculate_ecc_bch - ECC generator for 1 sector + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed + * @ecc_code: The ecc_code buffer + * + * Support calculating of BCH4/8/16 ECC vectors for one sector. This is used + * when SW based correction is required as ECC is required for one sector + * at a time. + */ +static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, + const u_char *dat, u_char *ecc_calc) +{ + return _omap_calculate_ecc_bch(mtd, dat, ecc_calc, 0); +} + static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -474,6 +569,35 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ #ifdef CONFIG_NAND_OMAP_ELM + +/** + * omap_calculate_ecc_bch_multi - Generate ECC for multiple sectors + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed + * @ecc_code: The ecc_code buffer + * + * Support calculating of BCH4/8/16 ecc vectors for the entire page in one go. + */ +static int omap_calculate_ecc_bch_multi(struct mtd_info *mtd, + const u_char *dat, u_char *ecc_calc) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + int eccbytes = chip->ecc.bytes; + unsigned long nsectors; + int i, ret; + + nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; + for (i = 0; i < nsectors; i++) { + ret = _omap_calculate_ecc_bch(mtd, dat, ecc_calc, i); + if (ret) + return ret; + + ecc_calc += eccbytes; + } + + return 0; +} + /* * omap_reverse_list - re-orders list elements in reverse order [internal] * @list: pointer to start of list @@ -626,52 +750,49 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, { int i, eccsize = chip->ecc.size; int eccbytes = chip->ecc.bytes; + int ecctotal = chip->ecc.total; int eccsteps = chip->ecc.steps; uint8_t *p = buf; uint8_t *ecc_calc = chip->buffers->ecccalc; uint8_t *ecc_code = chip->buffers->ecccode; uint32_t *eccpos = chip->ecc.layout->eccpos; uint8_t *oob = chip->oob_poi; - uint32_t data_pos; uint32_t oob_pos; - data_pos = 0; /* oob area start */ oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; oob += chip->ecc.layout->eccpos[0]; - for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, - oob += eccbytes) { - chip->ecc.hwctl(mtd, NAND_ECC_READ); - /* read data */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1); - chip->read_buf(mtd, p, eccsize); + /* Enable ECC engine */ + chip->ecc.hwctl(mtd, NAND_ECC_READ); - /* read respective ecc from oob area */ - chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); - chip->read_buf(mtd, oob, eccbytes); - /* read syndrome */ - chip->ecc.calculate(mtd, p, &ecc_calc[i]); + /* read entire page */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, 0, -1); + chip->read_buf(mtd, buf, mtd->writesize); - data_pos += eccsize; - oob_pos += eccbytes; - } + /* read all ecc bytes from oob area */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); + chip->read_buf(mtd, oob, ecctotal); + + /* Calculate ecc bytes */ + omap_calculate_ecc_bch_multi(mtd, buf, ecc_calc); for (i = 0; i < chip->ecc.total; i++) ecc_code[i] = chip->oob_poi[eccpos[i]]; + /* error detect & correct */ eccsteps = chip->ecc.steps; p = buf; for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { int stat; - stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); if (stat < 0) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; } + return 0; } #endif /* CONFIG_NAND_OMAP_ELM */ @@ -819,9 +940,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 13; - nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch_sw; - nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.calculate = omap_calculate_ecc_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; @@ -860,9 +981,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 14; - nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; @@ -893,9 +1014,9 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 26; nand->ecc.strength = 16; - nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.hwctl = omap_enable_hwecc_bch; nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc; + nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; From fa87360b3ae28639f72e1c665b0631436693f60f Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:21:57 +0200 Subject: [PATCH 418/424] mtd: rawnand: nand_base: Allow base driver to be used in SPL without nand_bbt nand_bbt.c is not being built with the nand_base driver during SPL build. This results in build failures if we try to access any nand_bbt related functions. Don't use any nand_bbt functions for SPL build. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-3-rogerq@kernel.org --- drivers/mtd/nand/raw/nand_base.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index bc61ad03eb..9eba360d55 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -447,7 +447,10 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd_to_nand(mtd); - int res, ret = 0; + int ret = 0; +#ifndef CONFIG_SPL_BUILD + int res; +#endif if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { struct erase_info einfo; @@ -465,12 +468,14 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) nand_release_device(mtd); } +#ifndef CONFIG_SPL_BUILD /* Mark block bad in BBT */ if (chip->bbt) { res = nand_markbad_bbt(mtd, ofs); if (!ret) ret = res; } +#endif if (!ret) mtd->ecc_stats.badblocks++; @@ -517,7 +522,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) if (!chip->bbt) return 0; /* Return info from the table */ +#ifndef CONFIG_SPL_BUILD return nand_isreserved_bbt(mtd, ofs); +#else + return 0; +#endif } /** @@ -543,7 +552,11 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) return chip->block_bad(mtd, ofs); /* Return info from the table */ +#ifndef CONFIG_SPL_BUILD return nand_isbad_bbt(mtd, ofs, allowbbt); +#else + return 0; +#endif } /** @@ -3752,8 +3765,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; + +#ifndef CONFIG_SPL_BUILD if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; +#endif if (!chip->controller) { chip->controller = &chip->hwcontrol; From dbb8711530160554823ccb8770dc6c570f482569 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:21:58 +0200 Subject: [PATCH 419/424] dt-bindings: mtd: Add ti, gpmc-nand DT binding documentation Add DT binding documentation for the TI GPMC NAND controller. This is picked up from the Linux Kernel. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-4-rogerq@kernel.org --- .../mtd/ti,gpmc-nand.yaml | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml diff --git a/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml new file mode 100644 index 0000000000..4ac198814b --- /dev/null +++ b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments GPMC NAND Flash controller. + +maintainers: + - Tony Lindgren + - Roger Quadros + +description: + GPMC NAND controller/Flash is represented as a child of the + GPMC controller node. + +properties: + compatible: + items: + - enum: + - ti,am64-nand + - ti,omap2-nand + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for fifoevent + - description: Interrupt for termcount + + "#address-cells": true + + "#size-cells": true + + ti,nand-ecc-opt: + description: Desired ECC algorithm + $ref: /schemas/types.yaml#/definitions/string + enum: [sw, ham1, bch4, bch8, bch16] + + ti,nand-xfer-type: + description: Data transfer method between controller and chip. + $ref: /schemas/types.yaml#/definitions/string + enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq] + default: prefetch-polled + + ti,elm-id: + description: + phandle to the ELM (Error Location Module). + $ref: /schemas/types.yaml#/definitions/phandle + + nand-bus-width: + description: + Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 + + rb-gpios: + description: + GPIO connection to R/B signal from NAND chip + maxItems: 1 + +patternProperties: + "@[0-9a-f]+$": + $ref: "/schemas/mtd/partitions/partition.yaml" + +allOf: + - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml" + +required: + - compatible + - reg + - ti,nand-ecc-opt + +unevaluatedProperties: false + +examples: + - | + #include + #include + + gpmc: memory-controller@50000000 { + compatible = "ti,am3352-gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = ; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + #address-cells = <1>; + #size-cells = <1>; + + /* NAND generic properties */ + nand-bus-width = <8>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + + /* GPMC properties*/ + gpmc,device-width = <1>; + + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + }; + }; From ff0d078942382ffdcbcfe44083427385dface1eb Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:21:59 +0200 Subject: [PATCH 420/424] mtd: rawnand: omap_gpmc: support u-boot driver model Adds driver model support. We need to be able to self initialize the NAND controller/chip at probe and so enable CONFIG_SYS_NAND_SELF_INIT. Doing so requires nand_register() API which is provided by nand.c and needs to be enabled during SPL build via CONFIG_SPL_NAND_INIT. But nand.c also provides nand_init() so we need to get rid of nand_init() in omap_gpmc driver if CONFIG_SPL_NAND_INIT is set. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-5-rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 1 + drivers/mtd/nand/raw/omap_gpmc.c | 64 +++++++++++++++++++++++++++++++- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index f8b79e5456..87ed4a22d6 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -253,6 +253,7 @@ config NAND_LPC32XX_SLC config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 + select SYS_NAND_SELF_INIT if ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index feaa739e78..fa60c371c2 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #ifdef CONFIG_ARCH_OMAP2PLUS @@ -1121,7 +1122,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) * nand_scan about special functionality. See the defines for further * explanation */ -int board_nand_init(struct nand_chip *nand) +int gpmc_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; int cs = cs_next++; @@ -1201,3 +1202,64 @@ int board_nand_init(struct nand_chip *nand) return 0; } + +/* First NAND chip for SPL use only */ +static __maybe_unused struct nand_chip *nand_chip; + +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) + +static int gpmc_nand_probe(struct udevice *dev) +{ + struct nand_chip *nand = dev_get_priv(dev); + struct mtd_info *mtd = nand_to_mtd(nand); + int ret; + + gpmc_nand_init(nand); + + ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); + if (ret) + return ret; + + ret = nand_register(0, mtd); + if (ret) + return ret; + + if (!nand_chip) + nand_chip = nand; + + return 0; +} + +static const struct udevice_id gpmc_nand_ids[] = { + { .compatible = "ti,am64-nand" }, + { .compatible = "ti,omap2-nand" }, + { } +}; + +U_BOOT_DRIVER(gpmc_nand) = { + .name = "gpmc-nand", + .id = UCLASS_MTD, + .of_match = gpmc_nand_ids, + .probe = gpmc_nand_probe, + .priv_auto = sizeof(struct nand_chip), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(gpmc_nand), &dev); + if (ret && ret != -ENODEV) + pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret); +} + +#else + +int board_nand_init(struct nand_chip *nand) +{ + return gpmc_nand_init(nand); +} + +#endif /* CONFIG_SYS_NAND_SELF_INIT */ From b747090705ec1eaa7c841334d4566f45966bf8ca Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:22:00 +0200 Subject: [PATCH 421/424] mtd: rawnand: omap_gpmc: Add SPL NAND support Enables SPL NAND support for ARCH_K3 by enabling SPL_NAND_INIT and SPL_SYS_NAND_SELF_INIT. Legacy OMAP2plus platforms still rely on SPL_NAND_AM33XX_BCH instead. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-6-rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 5 ++++ drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/omap_gpmc.c | 40 ++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 87ed4a22d6..7f2f49c560 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -26,6 +26,9 @@ config TPL_SYS_NAND_SELF_INIT config TPL_NAND_INIT bool +config SPL_NAND_INIT + bool + config SYS_MAX_NAND_DEVICE int "Maximum number of NAND devices to support" default 1 @@ -254,6 +257,8 @@ config NAND_OMAP_GPMC bool "Support OMAP GPMC NAND controller" depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 select SYS_NAND_SELF_INIT if ARCH_K3 + select SPL_NAND_INIT if ARCH_K3 + select SPL_SYS_NAND_SELF_INIT if ARCH_K3 help Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. GPMC controller is used for parallel NAND flash devices, and can diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index a398aa9d88..6fe33d2485 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o nand_amd.o nand_hynix.o \ nand_macronix.o nand_micron.o \ nand_samsung.o nand_toshiba.o obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o -obj-$(CONFIG_TPL_NAND_INIT) += nand.o +obj-$(CONFIG_$(SPL_TPL_)NAND_INIT) += nand.o ifeq ($(CONFIG_SPL_ENV_SUPPORT),y) obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o endif diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index fa60c371c2..4d5f2455df 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -1263,3 +1263,43 @@ int board_nand_init(struct nand_chip *nand) } #endif /* CONFIG_SYS_NAND_SELF_INIT */ + +#if defined(CONFIG_SPL_NAND_INIT) + +/* nand_init() is provided by nand.c */ + +/* Unselect after operation */ +void nand_deselect(void) +{ + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + if (nand_chip->select_chip) + nand_chip->select_chip(mtd, -1); +} + +static int nand_is_bad_block(int block) +{ + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE; + + return nand_chip->block_bad(mtd, ofs); +} + +static int nand_read_page(int block, int page, uchar *dst) +{ + int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page; + loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE; + int ret; + size_t len = CONFIG_SYS_NAND_PAGE_SIZE; + struct mtd_info *mtd = nand_to_mtd(nand_chip); + + ret = nand_read(mtd, ofs, &len, dst); + if (ret) + printf("nand_read failed %d\n", ret); + + return ret; +} + +#include "nand_spl_loaders.c" +#endif /* CONFIG_SPL_NAND_INIT */ From c2147bc7ece232b86c3d715f1c6c4ac4d6ab3b2b Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:22:01 +0200 Subject: [PATCH 422/424] mtd: rawnand: omap_gpmc: Enable SYS_NAND_PAGE_COUNT for OMAP_GPMC The symbol is required for NAND support in SPL when using OMAP_GPMC driver. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-7-rogerq@kernel.org --- drivers/mtd/nand/raw/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 7f2f49c560..92e8ac0a67 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -638,7 +638,8 @@ config SYS_NAND_ONFI_DETECTION config SYS_NAND_PAGE_COUNT hex "NAND chip page count" depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ - SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE) + SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \ + NAND_OMAP_GPMC) help Number of pages in the NAND chip. From 8993d5f2ac0280ff2a452387b35a5c89bdc42bdf Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:22:02 +0200 Subject: [PATCH 423/424] dt-bindings: mtd: Add ti, elm DT binding documentation Adds DT binding documentation for the TI Error Location Module. This is picked up from the Linux Kernel. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20221220102203.52398-8-rogerq@kernel.org --- doc/device-tree-bindings/mtd/ti,elm.yaml | 72 ++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 doc/device-tree-bindings/mtd/ti,elm.yaml diff --git a/doc/device-tree-bindings/mtd/ti,elm.yaml b/doc/device-tree-bindings/mtd/ti,elm.yaml new file mode 100644 index 0000000000..87128c0045 --- /dev/null +++ b/doc/device-tree-bindings/mtd/ti,elm.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,elm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Error Location Module (ELM). + +maintainers: + - Roger Quadros + +description: + ELM module is used together with GPMC and NAND Flash to detect + errors and the location of the error based on BCH algorithms + so they can be corrected if possible. + +properties: + compatible: + enum: + - ti,am3352-elm + - ti,am64-elm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Functional clock. + + clock-names: + items: + - const: fck + + power-domains: + maxItems: 1 + + ti,hwmods: + description: + Name of the HWMOD associated with ELM. This is for legacy + platforms only. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am64-elm + then: + required: + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + elm: ecc@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = <4>; + }; From 7363cf0581a3e70b3dbd346dec8b7ae652776f80 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 20 Dec 2022 12:22:03 +0200 Subject: [PATCH 424/424] mtd: rawnand: omap_elm: u-boot driver model support Support u-boot driver model. We still retain support legacy way of doing things if ELM_BASE is defined in We could completely get rid of that if all platforms defining ELM_BASE get rid of that definition and enable CONFIG_SYS_NAND_SELF_INIT and are verified to work. Signed-off-by: Roger Quadros Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Tom Rini Link: https://lore.kernel.org/all/20221220102203.52398-9-rogerq@kernel.org Link: https://lore.kernel.org/all/CABGWkvrvKiVA_yaDnHJcHEKwc+pEuLdz=i6HQEY0oJQvohCUsw@mail.gmail.com --- drivers/mtd/nand/raw/omap_elm.c | 38 ++++++++++++++++++- .../mtd => drivers/mtd/nand/raw}/omap_elm.h | 6 +++ drivers/mtd/nand/raw/omap_gpmc.c | 12 +++++- 3 files changed, 54 insertions(+), 2 deletions(-) rename {include/linux/mtd => drivers/mtd/nand/raw}/omap_elm.h (97%) diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 35c6dd1f1b..56a2c39e4f 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -15,9 +15,14 @@ #include #include #include -#include #include +#include +#include +#include + +#include "omap_elm.h" + #define DRIVER_NAME "omap-elm" #define ELM_DEFAULT_POLY (0) @@ -180,6 +185,7 @@ void elm_reset(void) ; } +#ifdef ELM_BASE /** * elm_init - Initialize ELM module * @@ -191,3 +197,33 @@ void elm_init(void) elm_cfg = (struct elm *)ELM_BASE; elm_reset(); } +#endif + +#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) + +static int elm_probe(struct udevice *dev) +{ +#ifndef ELM_BASE + struct resource res; + + dev_read_resource(dev, 0, &res); + elm_cfg = devm_ioremap(dev, res.start, resource_size(&res)); + elm_reset(); +#endif + + return 0; +} + +static const struct udevice_id elm_ids[] = { + { .compatible = "ti,am3352-elm" }, + { .compatible = "ti,am64-elm" }, + { } +}; + +U_BOOT_DRIVER(gpmc_elm) = { + .name = DRIVER_NAME, + .id = UCLASS_MTD, + .of_match = elm_ids, + .probe = elm_probe, +}; +#endif /* CONFIG_SYS_NAND_SELF_INIT */ diff --git a/include/linux/mtd/omap_elm.h b/drivers/mtd/nand/raw/omap_elm.h similarity index 97% rename from include/linux/mtd/omap_elm.h rename to drivers/mtd/nand/raw/omap_elm.h index f3db00d55d..a7f7bacb15 100644 --- a/include/linux/mtd/omap_elm.h +++ b/drivers/mtd/nand/raw/omap_elm.h @@ -74,6 +74,12 @@ int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count, u32 *error_locations); int elm_config(enum bch_level level); void elm_reset(void); +#ifdef ELM_BASE void elm_init(void); +#else +static inline void elm_init(void) +{ +} +#endif #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_ELM_H */ diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 4d5f2455df..1a5ed0de31 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -20,7 +20,8 @@ #include #include #include -#include + +#include "omap_elm.h" #ifndef GPMC_MAX_CS #define GPMC_MAX_CS 4 @@ -1249,6 +1250,15 @@ void board_nand_init(void) struct udevice *dev; int ret; +#ifdef CONFIG_NAND_OMAP_ELM + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(gpmc_elm), &dev); + if (ret && ret != -ENODEV) { + pr_err("%s: Failed to get ELM device: %d\n", __func__, ret); + return; + } +#endif + ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(gpmc_nand), &dev); if (ret && ret != -ENODEV)