imx8mq: synchronise device tree with linux
Synchronise device tree with linux v6.1-rc3. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler
Stefano Babic
parent
ed7bda5710
commit
cb9b70fd2f
7 changed files with 281 additions and 70 deletions
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@ -71,12 +71,36 @@
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linux,autosuspend-period = <125>;
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};
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audio_codec_bt_sco: audio-codec-bt-sco {
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compatible = "linux,bt-sco";
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#sound-dai-cells = <1>;
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};
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wm8524: audio-codec {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8524";
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wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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};
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sound-bt-sco {
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compatible = "simple-audio-card";
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simple-audio-card,name = "bt-sco-audio";
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simple-audio-card,format = "dsp_a";
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simple-audio-card,bitclock-inversion;
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simple-audio-card,frame-master = <&btcpu>;
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simple-audio-card,bitclock-master = <&btcpu>;
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btcpu: simple-audio-card,cpu {
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sound-dai = <&sai3>;
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dai-tdm-slot-num = <2>;
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dai-tdm-slot-width = <16>;
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};
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simple-audio-card,codec {
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sound-dai = <&audio_codec_bt_sco 1>;
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};
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};
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sound-wm8524 {
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compatible = "simple-audio-card";
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simple-audio-card,name = "wm8524-audio";
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@ -386,6 +410,16 @@
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status = "okay";
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};
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&sai3 {
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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@ -548,6 +582,15 @@
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>;
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};
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pinctrl_sai3: sai3grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
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MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
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MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
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MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
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>;
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};
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pinctrl_spdif1: spdif1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
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45
arch/arm/dts/imx8mq-librem5-r3.dtsi
Normal file
45
arch/arm/dts/imx8mq-librem5-r3.dtsi
Normal file
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@ -0,0 +1,45 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
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/dts-v1/;
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/*
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* This file describes hardware that is shared among r3 ("Dogwood") and
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* later revisions of the Librem 5 so it has to be included in dts there.
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*/
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#include "imx8mq-librem5.dtsi"
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/ {
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model = "Purism Librem 5r3";
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compatible = "purism,librem5r3", "purism,librem5", "fsl,imx8mq";
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};
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&accel_gyro {
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mount-matrix = "1", "0", "0",
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"0", "1", "0",
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"0", "0", "-1";
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};
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&bq25895 {
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ti,battery-regulation-voltage = <4200000>; /* uV */
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ti,charge-current = <1500000>; /* uA */
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ti,termination-current = <144000>; /* uA */
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};
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&camera_front {
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pinctrl-0 = <&pinctrl_csi1>, <&pinctrl_r3_camera_pwr>;
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shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
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};
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&iomuxc {
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pinctrl_r3_camera_pwr: r3camerapwrgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x83
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>;
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};
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};
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&proximity {
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proximity-near-level = <25>;
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};
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@ -1,35 +1,27 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2020 Purism SPC <kernel@puri.sm>
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// Copyright (C) 2021 Purism SPC <kernel@puri.sm>
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/dts-v1/;
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#include "imx8mq-librem5.dtsi"
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#include "imx8mq-librem5-r3.dtsi"
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/ {
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model = "Purism Librem 5r4";
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compatible = "purism,librem5r4", "purism,librem5", "fsl,imx8mq";
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};
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&accel_gyro {
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mount-matrix = "1", "0", "0",
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"0", "1", "0",
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"0", "0", "-1";
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};
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&bat {
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maxim,rsns-microohm = <1667>;
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};
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&bq25895 {
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ti,battery-regulation-voltage = <4200000>; /* uV */
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ti,charge-current = <1500000>; /* uA */
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ti,termination-current = <144000>; /* uA */
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};
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&led_backlight {
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led-max-microamp = <25000>;
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};
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&lcd_panel {
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compatible = "ys,ys57pss36bh5gq";
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};
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&proximity {
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proximity-near-level = <10>;
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};
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@ -7,6 +7,7 @@
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#include "dt-bindings/input/input.h"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/leds/common.h>
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#include "dt-bindings/pwm/pwm.h"
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#include "dt-bindings/usb/pd.h"
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#include "imx8mq.dtsi"
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@ -14,6 +15,7 @@
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/ {
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model = "Purism Librem 5";
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compatible = "purism,librem5", "fsl,imx8mq";
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chassis-type = "handset";
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backlight_dsi: backlight-dsi {
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compatible = "led-backlight";
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@ -36,18 +38,45 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_keys>;
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vol-down {
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key-vol-down {
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label = "VOL_DOWN";
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gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEDOWN>;
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debounce-interval = <50>;
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wakeup-source;
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};
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vol-up {
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key-vol-up {
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label = "VOL_UP";
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gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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debounce-interval = <50>;
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wakeup-source;
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};
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};
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led-controller {
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compatible = "pwm-leds";
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led-0 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_BLUE>;
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max-brightness = <248>;
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pwms = <&pwm2 0 50000 0>;
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};
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led-1 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_GREEN>;
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max-brightness = <248>;
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pwms = <&pwm4 0 50000 0>;
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};
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led-2 {
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function = LED_FUNCTION_STATUS;
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color = <LED_COLOR_ID_RED>;
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max-brightness = <248>;
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pwms = <&pwm3 0 50000 0>;
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};
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};
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@ -62,6 +91,40 @@
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enable-active-high;
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};
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/*
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* the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC
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* since we can't have it twice in the 2 different regulator nodes.
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*/
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reg_csi_1v8: regulator-csi-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "CAMERA_VDDIO_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <®_vdd_3v3>;
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gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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/* controlled by the CAMERA_POWER_KEY HKS */
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reg_vcam_1v2: regulator-vcam-1v2 {
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compatible = "regulator-fixed";
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regulator-name = "CAMERA_VDDD_1V2";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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vin-supply = <®_vdd_1v8>;
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enable-active-high;
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};
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reg_vcam_2v8: regulator-vcam-2v8 {
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compatible = "regulator-fixed";
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regulator-name = "CAMERA_VDDA_2V8";
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regulator-min-microvolt = <2800000>;
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regulator-max-microvolt = <2800000>;
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vin-supply = <®_vdd_3v3>;
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gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_gnss: regulator-gnss {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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@ -237,8 +300,13 @@
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cpu-supply = <&buck2_reg>;
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};
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&csi1 {
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status = "okay";
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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status = "okay";
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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@ -283,15 +351,10 @@
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};
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partition@30000 {
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label = "protected1";
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reg = <0x30000 0x10000>;
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label = "firmware";
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reg = <0x30000 0x1d0000>;
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read-only;
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};
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partition@40000 {
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label = "rw";
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reg = <0x40000 0x1C0000>;
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};
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};
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};
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@ -329,12 +392,24 @@
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>;
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};
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pinctrl_camera_pwr: camerapwrgrp {
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fsl,pins = <
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/* CAMERA_PWR_EN_3V3 */
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MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x83
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>;
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};
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pinctrl_csi1: csi1grp {
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fsl,pins = <
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/* CSI1_NRST */
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MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x83
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>;
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};
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pinctrl_charger_in: chargeringrp {
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fsl,pins = <
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/* CHRG_INT */
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MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80
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/* CHG_STATUS_B */
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MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80
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>;
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};
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@ -698,6 +773,10 @@
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interrupt-names = "irq";
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connector {
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compatible = "usb-c-connector";
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label = "USB-C";
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data-role = "dual";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -725,7 +804,7 @@
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compatible = "rohm,bd71837";
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reg = <0x4b>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>;
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clocks = <&pmic_osc>;
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clock-names = "osc";
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clock-output-names = "pmic_clk";
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@ -958,6 +1037,31 @@
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>;
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};
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camera_front: camera@20 {
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compatible = "hynix,hi846";
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reg = <0x20>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_csi1>;
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clocks = <&clk IMX8MQ_CLK_CLKO2>;
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assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
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assigned-clock-rates = <25000000>;
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reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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vdda-supply = <®_vcam_2v8>;
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vddd-supply = <®_vcam_1v2>;
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vddio-supply = <®_csi_1v8>;
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rotation = <90>;
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orientation = <0>;
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port {
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camera1_ep: endpoint {
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data-lanes = <1 2>;
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link-frequencies = /bits/ 64
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<80000000 200000000 300000000>;
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remote-endpoint = <&mipi1_sensor_ep>;
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};
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};
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};
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backlight@36 {
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compatible = "ti,lm36922";
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reg = <0x36>;
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@ -996,6 +1100,12 @@
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pinctrl-0 = <&pinctrl_i2c4>;
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status = "okay";
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vcm@c {
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compatible = "dongwoon,dw9714";
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reg = <0x0c>;
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vcc-supply = <®_csi_1v8>;
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};
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bat: fuel-gauge@36 {
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compatible = "maxim,max17055";
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reg = <0x36>;
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@ -1003,6 +1113,7 @@
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interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gauge>;
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power-supplies = <&bq25895>;
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maxim,over-heat-temp = <700>;
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maxim,over-volt = <4500>;
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maxim,rsns-microohm = <5000>;
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@ -1019,7 +1130,7 @@
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ti,precharge-current = <130000>; /* uA */
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ti,minimum-sys-voltage = <3700000>; /* uV */
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ti,boost-voltage = <5000000>; /* uV */
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ti,boost-max-current = <500000>; /* uA */
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ti,boost-max-current = <1500000>; /* uA */
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ti,use-vinmin-threshold = <1>; /* enable VINDPM */
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ti,vinmin-threshold = <3900000>; /* uV */
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monitored-battery = <&bat>;
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@ -1031,6 +1142,21 @@
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status = "okay";
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};
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&mipi_csi1 {
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status = "okay";
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ports {
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port@0 {
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reg = <0>;
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mipi1_sensor_ep: endpoint {
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remote-endpoint = <&camera1_ep>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&mipi_dsi {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1174,6 +1300,7 @@
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#size-cells = <0>;
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dr_mode = "otg";
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snps,dis_u3_susphy_quirk;
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usb-role-switch;
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status = "okay";
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port@0 {
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@ -10,23 +10,23 @@
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};
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&{/soc@0} {
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&soc {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30000000} {
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&aips1 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30400000} {
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&aips2 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@30800000} {
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&aips3 {
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u-boot,dm-spl;
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};
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&{/soc@0/bus@32c00000} {
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&aips4 {
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u-boot,dm-spl;
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};
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@ -94,7 +94,7 @@
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clk_ext4: clock-ext4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency= <133000000>;
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clock-frequency = <133000000>;
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clock-output-names = "clk_ext4";
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};
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@ -320,7 +320,7 @@
|
|||
arm,no-tick-in-suspend;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
soc: soc@0 {
|
||||
compatible = "fsl,imx8mq-soc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
@ -329,7 +329,7 @@
|
|||
nvmem-cells = <&imx8mq_uid>;
|
||||
nvmem-cell-names = "soc_unique_id";
|
||||
|
||||
bus@30000000 { /* AIPS1 */
|
||||
aips1: bus@30000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30000000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -507,7 +507,7 @@
|
|||
<0x00030005 0x00000053>,
|
||||
<0x00030006 0x0000005f>,
|
||||
<0x00030007 0x00000071>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
wdog1: watchdog@30280000 {
|
||||
|
|
@ -534,7 +534,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma2: sdma@302c0000 {
|
||||
sdma2: dma-controller@302c0000 {
|
||||
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
|
||||
reg = <0x302c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -784,7 +784,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
bus@30400000 { /* AIPS2 */
|
||||
aips2: bus@30400000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30400000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -844,7 +844,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
bus@30800000 { /* AIPS3 */
|
||||
aips3: bus@30800000 { /* AIPS3 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x30800000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
|
|
@ -1018,6 +1018,7 @@
|
|||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
|
|
@ -1301,7 +1302,7 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma1: sdma@30bd0000 {
|
||||
sdma1: dma-controller@30bd0000 {
|
||||
compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
|
||||
reg = <0x30bd0000 0x10000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -1369,7 +1370,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
bus@32c00000 { /* AIPS4 */
|
||||
aips4: bus@32c00000 { /* AIPS4 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
reg = <0x32c00000 0x400000>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -28,37 +28,40 @@
|
|||
#define IMX8MQ_RESET_A53_L2RESET 17
|
||||
#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
|
||||
#define IMX8MQ_RESET_OTG1_PHY_RESET 19
|
||||
#define IMX8MQ_RESET_OTG2_PHY_RESET 20
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
|
||||
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23
|
||||
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24
|
||||
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25
|
||||
#define IMX8MQ_RESET_PCIEPHY 26
|
||||
#define IMX8MQ_RESET_PCIEPHY_PERST 27
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
|
||||
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DISP_RESET 31
|
||||
#define IMX8MQ_RESET_GPU_RESET 32
|
||||
#define IMX8MQ_RESET_VPU_RESET 33
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */
|
||||
#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
|
||||
#define IMX8MQ_RESET_SW_M4C_RST 50
|
||||
#define IMX8MQ_RESET_SW_M4P_RST 51
|
||||
#define IMX8MQ_RESET_M4_ENABLE 52
|
||||
|
||||
#define IMX8MQ_RESET_NUM 50
|
||||
#define IMX8MQ_RESET_NUM 53
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue