spi: mxs: Drop nondm code
Deadline for DM migration already passed by months and no response on full dm conversation hence removed the nondm code. Note: Look like there is no user for nondm code for this driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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be79009f3b
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c9a9823f26
2 changed files with 6 additions and 129 deletions
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@ -207,6 +207,12 @@ config MVEBU_A3700_SPI
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used to access the SPI NOR flash on platforms embedding this
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Marvell IP core.
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config MXS_SPI
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bool "MXS SPI Driver"
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help
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Enable the MXS SPI controller driver. This driver can be used
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on the i.MX23 and i.MX28 SoCs.
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config NXP_FSPI
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bool "NXP FlexSPI driver"
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depends on SPI_MEM
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@ -424,12 +430,6 @@ config MXC_SPI
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Enable the MXC SPI controller driver. This driver can be used
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on various i.MX SoCs such as i.MX31/35/51/6/7.
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config MXS_SPI
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bool "MXS SPI Driver"
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help
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Enable the MXS SPI controller driver. This driver can be used
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on the i.MX23 and i.MX28 SoCs.
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config OMAP3_SPI
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bool "McSPI driver for OMAP"
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help
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@ -46,19 +46,6 @@ static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
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writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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struct mxs_spi_slave {
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struct spi_slave slave;
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uint32_t max_khz;
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uint32_t mode;
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struct mxs_ssp_regs *regs;
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};
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static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxs_spi_slave, slave);
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}
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#else
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#include <dm.h>
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#include <errno.h>
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#include <dt-structs.h>
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@ -87,20 +74,12 @@ struct mxs_spi_priv {
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unsigned int clk_id;
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unsigned int mode;
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};
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#endif
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#if !CONFIG_IS_ENABLED(DM_SPI)
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static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
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char *data, int length, int write, unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = slave->regs;
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#else
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static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
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char *data, int length, int write,
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unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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#endif
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if (flags & SPI_XFER_BEGIN)
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mxs_spi_start_xfer(ssp_regs);
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@ -156,17 +135,10 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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char *data, int length, int write, unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = slave->regs;
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#else
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static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
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char *data, int length, int write,
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unsigned long flags)
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{ struct mxs_ssp_regs *ssp_regs = priv->regs;
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#endif
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const int xfer_max_sz = 0xff00;
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const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
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struct mxs_dma_desc *dp;
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@ -207,11 +179,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
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/* Invalidate the area, so no writeback into the RAM races with DMA */
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invalidate_dcache_range(dstart, dstart + cache_data_count);
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#if !CONFIG_IS_ENABLED(DM_SPI)
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dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
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#else
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dmach = priv->dma_channel;
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#endif
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dp = desc;
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while (length) {
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@ -288,20 +256,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
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return ret;
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
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#else
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int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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#endif
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int len = bitlen / 8;
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char dummy;
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int write = 0;
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@ -345,95 +305,13 @@ int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
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if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
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#if !CONFIG_IS_ENABLED(DM_SPI)
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return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
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#else
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return mxs_spi_xfer_pio(priv, data, len, write, flags);
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#endif
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} else {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
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#if !CONFIG_IS_ENABLED(DM_SPI)
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return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
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#else
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return mxs_spi_xfer_dma(priv, data, len, write, flags);
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#endif
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}
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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/* MXS SPI: 4 ports and 3 chip selects maximum */
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if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
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return 0;
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else
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return 1;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct mxs_spi_slave *mxs_slave;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
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return NULL;
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}
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mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
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if (!mxs_slave)
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return NULL;
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if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
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goto err_init;
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mxs_slave->max_khz = max_hz / 1000;
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mxs_slave->mode = mode;
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mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
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return &mxs_slave->slave;
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err_init:
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free(mxs_slave);
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return NULL;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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free(mxs_slave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
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u32 reg = 0;
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mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
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writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
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SSP_CTRL0_BUS_WIDTH_ONE_BIT,
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&ssp_regs->hw_ssp_ctrl0);
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reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
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reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
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reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
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writel(reg, &ssp_regs->hw_ssp_ctrl1);
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writel(0, &ssp_regs->hw_ssp_cmd0);
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mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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#else /* CONFIG_DM_SPI */
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/* Base numbers of i.MX2[38] clk for ssp0 IP block */
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#define MXS_SSP_IMX23_CLKID_SSP0 33
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#define MXS_SSP_IMX28_CLKID_SSP0 46
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@ -625,4 +503,3 @@ U_BOOT_DRIVER(mxs_spi) = {
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.priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
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.probe = mxs_spi_probe,
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};
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#endif
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