Difuse/u-boot
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: OMAP4+: Make control module register structure generic

Browse source 
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
This commit is contained in:
Lokesh Vutla 2013-02-04 04:22:04 +00:00 committed by Tom Rini
parent e05a4f1f54
commit c43c8339fe
11 changed files with 269 additions and 206 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View file

@ -238,10 +238,7 @@ int checkboard(void)
*/
u32 get_device_type(void)
{
struct omap_sys_ctrl_regs *ctrl =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
return (readl(&ctrl->control_status) &
return (readl((*ctrl)->control_status) &
(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
}

3
arch/arm/cpu/armv7/omap4/hw_data.c
View file

@ -39,6 +39,8 @@ struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
/*
* The M & N values in the following tables are created using the
@ -470,4 +472,5 @@ void hw_data_init(void)
printf("\n INVALID OMAP REVISION ");
}
*ctrl = &omap4_ctrl;
}

36
arch/arm/cpu/armv7/omap4/hwinit.c
View file

@ -57,10 +57,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
void do_io_settings(void)
{
u32 lpddr2io;
struct control_lpddr2io_regs *lpddr2io_regs =
(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
struct omap_sys_ctrl_regs *const ctrl =
(struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
@ -72,20 +68,20 @@ void do_io_settings(void)
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
(*ctrl)->control_lpddr2io1_2);
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
/* EMIF2 */
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
&lpddr2io_regs->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
(*ctrl)->control_lpddr2io2_2);
writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
@ -93,16 +89,16 @@ void do_io_settings(void)
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_iva_voltage_ctrl);
(*ctrl)->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_mpu_voltage_ctrl);
(*ctrl)->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
&ctrl->control_ldosram_core_voltage_ctrl);
(*ctrl)->control_ldosram_core_voltage_ctrl);
}
/*
@ -110,11 +106,11 @@ void do_io_settings(void)
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
if (!readl(&ctrl->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
if (!readl((*ctrl)->control_efuse_1))
writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
}
#endif /* CONFIG_SPL_BUILD */

20
arch/arm/cpu/armv7/omap4/prcm-regs.c
View file

@ -293,3 +293,23 @@ struct prcm_regs const omap4_prcm = {
.prm_vc_cfg_i2c_mode = 0x4a307ba8,
.prm_vc_cfg_i2c_clk = 0x4a307bac,
};
struct omap_sys_ctrl_regs const omap4_ctrl = {
.control_id_code = 0x4A002204,
.control_std_fuse_opp_bgap = 0x4a002260,
.control_status = 0x4a0022c4,
.control_ldosram_iva_voltage_ctrl = 0x4A002320,
.control_ldosram_mpu_voltage_ctrl = 0x4A002324,
.control_ldosram_core_voltage_ctrl = 0x4A002328,
.control_pbiaslite = 0x4A100600,
.control_lpddr2io1_0 = 0x4A100638,
.control_lpddr2io1_1 = 0x4A10063C,
.control_lpddr2io1_2 = 0x4A100640,
.control_lpddr2io1_3 = 0x4A100644,
.control_lpddr2io2_0 = 0x4A100648,
.control_lpddr2io2_1 = 0x4A10064C,
.control_lpddr2io2_2 = 0x4A100650,
.control_lpddr2io2_3 = 0x4A100654,
.control_efuse_1 = 0x4A100700,
.control_efuse_2 = 0x4A100704,
};

4
arch/arm/cpu/armv7/omap5/hw_data.c
View file

@ -39,6 +39,8 @@ struct dplls const **dplls_data =
(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
struct vcores_data const **omap_vcores =
(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
struct omap_sys_ctrl_regs const **ctrl =
(struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
@ -433,4 +435,6 @@ void hw_data_init(void)
default:
printf("\n INVALID OMAP REVISION ");
}
*ctrl = &omap5_ctrl;
}

102
arch/arm/cpu/armv7/omap5/hwinit.c
View file

@ -56,76 +56,71 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_0));
(*ctrl)->control_ddrch1_0);
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch1_1));
(*ctrl)->control_ddrch1_1);
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_0));
(*ctrl)->control_ddrch2_0);
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
&(ioregs_base->control_ddrch2_1));
(*ctrl)->control_ddrch2_1);
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_0));
(*ctrl)->control_lpddr2ch1_0);
writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
&(ioregs_base->control_lpddr2ch1_1));
(*ctrl)->control_lpddr2ch1_1);
writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
&(ioregs_base->control_ddrio_0));
(*ctrl)->control_ddrio_0);
writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
&(ioregs_base->control_ddrio_1));
(*ctrl)->control_ddrio_1);
writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
&(ioregs_base->control_ddrio_2));
(*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddr3ch1_0));
(*ctrl)->control_ddr3ch1_0);
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch1_0));
(*ctrl)->control_ddrch1_0);
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch1_1));
(*ctrl)->control_ddrch1_1);
writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddr3ch2_0));
(*ctrl)->control_ddr3ch2_0);
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch2_0));
(*ctrl)->control_ddrch2_0);
writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
&(ioregs_base->control_ddrch2_1));
(*ctrl)->control_ddrch2_1);
writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_0));
(*ctrl)->control_ddrio_0);
writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_1));
(*ctrl)->control_ddrio_1);
writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
&(ioregs_base->control_ddrio_2));
(*ctrl)->control_ddrio_2);
/* omap5432 does not use lpddr2 */
writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
writel(0x0, (*ctrl)->control_lpddr2ch1_0);
writel(0x0, (*ctrl)->control_lpddr2ch1_1);
writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
&(ioregs_base->control_emif1_sdram_config_ext));
(*ctrl)->control_emif1_sdram_config_ext);
writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
&(ioregs_base->control_emif2_sdram_config_ext));
(*ctrl)->control_emif2_sdram_config_ext);
/* Disable DLL select */
io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
&(ioregs_base->control_port_emif1_sdram_config));
(*ctrl)->control_port_emif1_sdram_config);
io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
&(ioregs_base->control_port_emif2_sdram_config));
(*ctrl)->control_port_emif2_sdram_config);
}
/*
@ -134,62 +129,60 @@ static void io_settings_ddr3(void)
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(ds_mask << 16) | (ds_mask << 18);
io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
(~mask);
io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
(ds_45_ohm << 18) | (ds_60_ohm << 2);
writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
/* Impedance settings Mcspi2 */
mask = (ds_mask << 30);
io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 30);
writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
/* Impedance settings C2C 3,4 */
mask = (ds_mask << 14) | (ds_mask << 16);
io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
(~mask);
io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
/* Slew rate settings EMMC, C2C 1,2 */
mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
(~mask);
io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
/* Slew rate settings hsi2, Mcspi2 */
mask = (sc_mask << 24) | (sc_mask << 28);
io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
(~mask);
io_settings |= (sc_fast << 28) | (sc_fast << 24);
writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
/* Slew rate settings C2C 3,4 */
mask = (sc_mask << 16) | (sc_mask << 18);
io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
(~mask);
io_settings |= (sc_na << 16) | (sc_na << 18);
writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
/* impedance and slew rate settings for usb */
mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
(ds_60_ohm << 23) | (sc_fast << 20) |
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
@ -197,25 +190,22 @@ void do_io_settings(void)
io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, &(ioregs_base->control_efuse_1));
writel(EFUSE_2, &(ioregs_base->control_efuse_2));
writel(EFUSE_3, &(ioregs_base->control_efuse_3));
writel(EFUSE_4, &(ioregs_base->control_efuse_4));
writel(EFUSE_1, (*ctrl)->control_efuse_1);
writel(EFUSE_2, (*ctrl)->control_efuse_2);
writel(EFUSE_3, (*ctrl)->control_efuse_3);
writel(EFUSE_4, (*ctrl)->control_efuse_4);
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
struct omap_sys_ctrl_regs *ioregs_base =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
&(ioregs_base->control_emif1_sdram_config_ext));
(*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
&(ioregs_base->control_emif2_sdram_config_ext));
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_omap_revision(void)

74
arch/arm/cpu/armv7/omap5/prcm-regs.c
View file

@ -304,3 +304,77 @@ struct prcm_regs const omap5_es1_prcm = {
.prm_sldo_mm_setup = 0x4ae07bd4,
.prm_sldo_mm_ctrl = 0x4ae07bd8,
};
struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
.control_smart1io_padconf_1 = 0x4A002DAC,
.control_smart1io_padconf_2 = 0x4A002DB0,
.control_smart2io_padconf_0 = 0x4A002DB4,
.control_smart2io_padconf_1 = 0x4A002DB8,
.control_smart2io_padconf_2 = 0x4A002DBC,
.control_smart3io_padconf_0 = 0x4A002DC0,
.control_smart3io_padconf_1 = 0x4A002DC4,
.control_pbias = 0x4A002E00,
.control_i2c_0 = 0x4A002E04,
.control_camera_rx = 0x4A002E08,
.control_hdmi_tx_phy = 0x4A002E0C,
.control_uniportm = 0x4A002E10,
.control_dsiphy = 0x4A002E14,
.control_mcbsplp = 0x4A002E18,
.control_usb2phycore = 0x4A002E1C,
.control_hdmi_1 = 0x4A002E20,
.control_hsi = 0x4A002E24,
.control_ddr3ch1_0 = 0x4A002E30,
.control_ddr3ch2_0 = 0x4A002E34,
.control_ddrch1_0 = 0x4A002E38,
.control_ddrch1_1 = 0x4A002E3C,
.control_ddrch2_0 = 0x4A002E40,
.control_ddrch2_1 = 0x4A002E44,
.control_lpddr2ch1_0 = 0x4A002E48,
.control_lpddr2ch1_1 = 0x4A002E4C,
.control_ddrio_0 = 0x4A002E50,
.control_ddrio_1 = 0x4A002E54,
.control_ddrio_2 = 0x4A002E58,
.control_hyst_1 = 0x4A002E5C,
.control_usbb_hsic_control = 0x4A002E60,
.control_c2c = 0x4A002E64,
.control_core_control_spare_rw = 0x4A002E68,
.control_core_control_spare_r = 0x4A002E6C,
.control_core_control_spare_r_c0 = 0x4A002E70,
.control_srcomp_north_side = 0x4A002E74,
.control_srcomp_south_side = 0x4A002E78,
.control_srcomp_east_side = 0x4A002E7C,
.control_srcomp_west_side = 0x4A002E80,
.control_srcomp_code_latch = 0x4A002E84,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118,
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
.control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
.control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
.control_padconf_mode = 0x4AE0CDA8,
.control_xtal_oscillator = 0x4AE0CDAC,
.control_i2c_2 = 0x4AE0CDB0,
.control_ckobuffer = 0x4AE0CDB4,
.control_wkup_control_spare_rw = 0x4AE0CDB8,
.control_wkup_control_spare_r = 0x4AE0CDBC,
.control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
.control_srcomp_east_side_wkup = 0x4AE0CDC4,
.control_efuse_1 = 0x4AE0CDC8,
.control_efuse_2 = 0x4AE0CDCC,
.control_efuse_3 = 0x4AE0CDD0,
.control_efuse_4 = 0x4AE0CDD4,
.control_efuse_5 = 0x4AE0CDD8,
.control_efuse_6 = 0x4AE0CDDC,
.control_efuse_7 = 0x4AE0CDE0,
.control_efuse_8 = 0x4AE0CDE4,
.control_efuse_9 = 0x4AE0CDE8,
.control_efuse_10 = 0x4AE0CDEC,
.control_efuse_11 = 0x4AE0CDF0,
.control_efuse_12 = 0x4AE0CDF4,
.control_efuse_13 = 0x4AE0CDF8,
};

31
arch/arm/include/asm/arch-omap4/omap.h
View file

@ -132,34 +132,6 @@ struct s32ktimer {
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
struct omap_sys_ctrl_regs {
unsigned int pad1[129];
unsigned int control_id_code; /* 0x4A002204 */
unsigned int pad11[22];
unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
unsigned int pad2[24]; /* 0x4a002264 */
unsigned int control_status; /* 0x4a0022c4 */
unsigned int pad3[22]; /* 0x4a0022c8 */
unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
unsigned int pad4[260277];
unsigned int control_pbiaslite; /* 0x4A100600 */
unsigned int pad5[63];
unsigned int control_efuse_1; /* 0x4A100700 */
unsigned int control_efuse_2; /* 0x4A100704 */
};
struct control_lpddr2io_regs {
unsigned int control_lpddr2io1_0;
unsigned int control_lpddr2io1_1;
unsigned int control_lpddr2io1_2;
unsigned int control_lpddr2io1_3;
unsigned int control_lpddr2io2_0;
unsigned int control_lpddr2io2_1;
unsigned int control_lpddr2io2_2;
unsigned int control_lpddr2io2_3;
};
#endif /* __ASSEMBLY__ */
/*
@ -181,7 +153,8 @@ struct control_lpddr2io_regs {
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* ROM code defines */
/* Boot device */

84
arch/arm/include/asm/arch-omap5/omap.h
View file

@ -131,87 +131,6 @@ struct s32ktimer {
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
struct omap_sys_ctrl_regs {
u32 pad0[77]; /* 0x4A002000 */
u32 control_status; /* 0x4A002134 */
u32 pad1[794]; /* 0x4A002138 */
u32 control_paconf_global; /* 0x4A002DA0 */
u32 control_paconf_mode; /* 0x4A002DA4 */
u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
u32 control_smart1io_padconf_1; /* 0x4A002DAC */
u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
u32 control_smart2io_padconf_2; /* 0x4A002DBC */
u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
u32 pad2[14];
u32 control_pbias; /* 0x4A002E00 */
u32 control_i2c_0; /* 0x4A002E04 */
u32 control_camera_rx; /* 0x4A002E08 */
u32 control_hdmi_tx_phy; /* 0x4A002E0C */
u32 control_uniportm; /* 0x4A002E10 */
u32 control_dsiphy; /* 0x4A002E14 */
u32 control_mcbsplp; /* 0x4A002E18 */
u32 control_usb2phycore; /* 0x4A002E1C */
u32 control_hdmi_1; /*0x4A002E20*/
u32 control_hsi; /*0x4A002E24*/
u32 pad3[2];
u32 control_ddr3ch1_0; /*0x4A002E30*/
u32 control_ddr3ch2_0; /*0x4A002E34*/
u32 control_ddrch1_0; /*0x4A002E38*/
u32 control_ddrch1_1; /*0x4A002E3C*/
u32 control_ddrch2_0; /*0x4A002E40*/
u32 control_ddrch2_1; /*0x4A002E44*/
u32 control_lpddr2ch1_0; /*0x4A002E48*/
u32 control_lpddr2ch1_1; /*0x4A002E4C*/
u32 control_ddrio_0; /*0x4A002E50*/
u32 control_ddrio_1; /*0x4A002E54*/
u32 control_ddrio_2; /*0x4A002E58*/
u32 control_hyst_1; /*0x4A002E5C*/
u32 control_usbb_hsic_control; /*0x4A002E60*/
u32 control_c2c; /*0x4A002E64*/
u32 control_core_control_spare_rw; /*0x4A002E68*/
u32 control_core_control_spare_r; /*0x4A002E6C*/
u32 control_core_control_spare_r_c0; /*0x4A002E70*/
u32 control_srcomp_north_side; /*0x4A002E74*/
u32 control_srcomp_south_side; /*0x4A002E78*/
u32 control_srcomp_east_side; /*0x4A002E7C*/
u32 control_srcomp_west_side; /*0x4A002E80*/
u32 control_srcomp_code_latch; /*0x4A002E84*/
u32 pad4[3679394];
u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
u32 pad5[10];
u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
u32 pad6[789];
u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
u32 control_padconf_mode; /* 0x4AE0CDA8 */
u32 control_xtal_oscillator; /* 0x4AE0CDAC */
u32 control_i2c_2; /* 0x4AE0CDB0 */
u32 control_ckobuffer; /* 0x4AE0CDB4 */
u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
u32 control_efuse_1; /* 0x4AE0CDC8 */
u32 control_efuse_2; /* 0x4AE0CDCC */
u32 control_efuse_3; /* 0x4AE0CDD0 */
u32 control_efuse_4; /* 0x4AE0CDD4 */
u32 control_efuse_5; /* 0x4AE0CDD8 */
u32 control_efuse_6; /* 0x4AE0CDDC */
u32 control_efuse_7; /* 0x4AE0CDE0 */
u32 control_efuse_8; /* 0x4AE0CDE4 */
u32 control_efuse_9; /* 0x4AE0CDE8 */
u32 control_efuse_10; /* 0x4AE0CDEC */
u32 control_efuse_11; /* 0x4AE0CDF0 */
u32 control_efuse_12; /* 0x4AE0CDF4 */
u32 control_efuse_13; /* 0x4AE0CDF8 */
};
/* Output impedance control */
#define ds_120_ohm 0x0
#define ds_60_ohm 0x1
@ -274,7 +193,8 @@ struct omap_sys_ctrl_regs {
#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF

91
arch/arm/include/asm/omap_common.h
View file

@ -326,6 +326,94 @@ struct prcm_regs {
u32 prm_vc_cfg_channel;
};
struct omap_sys_ctrl_regs {
u32 control_status;
u32 control_id_code;
u32 control_std_fuse_opp_bgap;
u32 control_ldosram_iva_voltage_ctrl;
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
u32 control_paconf_global;
u32 control_paconf_mode;
u32 control_smart1io_padconf_0;
u32 control_smart1io_padconf_1;
u32 control_smart1io_padconf_2;
u32 control_smart2io_padconf_0;
u32 control_smart2io_padconf_1;
u32 control_smart2io_padconf_2;
u32 control_smart3io_padconf_0;
u32 control_smart3io_padconf_1;
u32 control_pbias;
u32 control_i2c_0;
u32 control_camera_rx;
u32 control_hdmi_tx_phy;
u32 control_uniportm;
u32 control_dsiphy;
u32 control_mcbsplp;
u32 control_usb2phycore;
u32 control_hdmi_1;
u32 control_hsi;
u32 control_ddr3ch1_0;
u32 control_ddr3ch2_0;
u32 control_ddrch1_0;
u32 control_ddrch1_1;
u32 control_ddrch2_0;
u32 control_ddrch2_1;
u32 control_lpddr2ch1_0;
u32 control_lpddr2ch1_1;
u32 control_ddrio_0;
u32 control_ddrio_1;
u32 control_ddrio_2;
u32 control_lpddr2io1_0;
u32 control_lpddr2io1_1;
u32 control_lpddr2io1_2;
u32 control_lpddr2io1_3;
u32 control_lpddr2io2_0;
u32 control_lpddr2io2_1;
u32 control_lpddr2io2_2;
u32 control_lpddr2io2_3;
u32 control_hyst_1;
u32 control_usbb_hsic_control;
u32 control_c2c;
u32 control_core_control_spare_rw;
u32 control_core_control_spare_r;
u32 control_core_control_spare_r_c0;
u32 control_srcomp_north_side;
u32 control_srcomp_south_side;
u32 control_srcomp_east_side;
u32 control_srcomp_west_side;
u32 control_srcomp_code_latch;
u32 control_pbiaslite;
u32 control_port_emif1_sdram_config;
u32 control_port_emif1_lpddr2_nvm_config;
u32 control_port_emif2_sdram_config;
u32 control_emif1_sdram_config_ext;
u32 control_emif2_sdram_config_ext;
u32 control_smart1nopmio_padconf_0;
u32 control_smart1nopmio_padconf_1;
u32 control_padconf_mode;
u32 control_xtal_oscillator;
u32 control_i2c_2;
u32 control_ckobuffer;
u32 control_wkup_control_spare_rw;
u32 control_wkup_control_spare_r;
u32 control_wkup_control_spare_r_c0;
u32 control_srcomp_east_side_wkup;
u32 control_efuse_1;
u32 control_efuse_2;
u32 control_efuse_3;
u32 control_efuse_4;
u32 control_efuse_5;
u32 control_efuse_6;
u32 control_efuse_7;
u32 control_efuse_8;
u32 control_efuse_9;
u32 control_efuse_10;
u32 control_efuse_11;
u32 control_efuse_12;
u32 control_efuse_13;
};
struct dpll_params {
u32 m;
u32 n;
@ -390,6 +478,9 @@ extern struct prcm_regs const omap4_prcm;
extern struct dplls const **dplls_data;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
extern struct omap_sys_ctrl_regs const omap4_ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
void hw_data_init(void);

25
drivers/mmc/omap_hsmmc.c
View file

@ -95,18 +95,15 @@ static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
u32 value = 0;
struct omap_sys_ctrl_regs *const ctrl =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
value = readl(&ctrl->control_pbiaslite);
value = readl((*ctrl)->control_pbiaslite);
value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
writel(value, &ctrl->control_pbiaslite);
writel(value, (*ctrl)->control_pbiaslite);
/* set VMMC to 3V */
twl6030_power_mmc_init();
value = readl(&ctrl->control_pbiaslite);
value = readl((*ctrl)->control_pbiaslite);
value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
writel(value, &ctrl->control_pbiaslite);
writel(value, (*ctrl)->control_pbiaslite);
}
#endif
@ -114,26 +111,24 @@ static void omap4_vmmc_pbias_config(struct mmc *mmc)
static void omap5_pbias_config(struct mmc *mmc)
{
u32 value = 0;
struct omap_sys_ctrl_regs *const ctrl =
(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
value = readl(&ctrl->control_pbias);
value = readl((*ctrl)->control_pbias);
value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
value |= SDCARD_BIAS_HIZ_MODE;
writel(value, &ctrl->control_pbias);
writel(value, (*ctrl)->control_pbias);
twl6035_mmc1_poweron_ldo();
value = readl(&ctrl->control_pbias);
value = readl((*ctrl)->control_pbias);
value &= ~SDCARD_BIAS_HIZ_MODE;
value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
writel(value, &ctrl->control_pbias);
writel(value, (*ctrl)->control_pbias);
value = readl(&ctrl->control_pbias);
value = readl((*ctrl)->control_pbias);
if (value & (1 << 23)) {
value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
value |= SDCARD_BIAS_HIZ_MODE;
writel(value, &ctrl->control_pbias);
writel(value, (*ctrl)->control_pbias);
}
}
#endif