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arm: socfpga: vining: Fix UDC controller phandle in DT

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The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Marek Vasut 2021-09-14 05:25:34 +02:00
parent e21bbffa1d
commit c3880e6597
1 changed files with 1 additions and 1 deletions
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arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
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@ -11,7 +11,7 @@
/{
aliases {
spi0 = "/soc/spi@ff705000";
udc0 = &usb0;
udc0 = &usb1;
};
};