lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX
There's nothing special or unique to the lpc32xx that requires its own config parameter for specifying the console uart index. Therefore instead of using the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the already-available CONFIG_CONS_INDEX from Kconfig. Signed-off-by: Trevor Woerner <twoerner@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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11 changed files with 11 additions and 19 deletions
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@ -12,8 +12,8 @@
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/* Basic CPU architecture */
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/* UART configuration */
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#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
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(CONFIG_SYS_LPC32XX_UART == 7)
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#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
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(CONFIG_CONS_INDEX == 7)
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#if !defined(CONFIG_LPC32XX_HSUART)
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#define CONFIG_LPC32XX_HSUART
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#endif
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@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
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return;
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/* Disable loopback mode, if it is set by S1L bootloader */
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clrbits_le32(&ctrl->loop,
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UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
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clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
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if (uart_id < 3 || uart_id > 6)
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return;
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@ -38,7 +38,7 @@ void reset_periph(void)
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int board_early_init_f(void)
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{
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lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
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lpc32xx_uart_init(CONFIG_CONS_INDEX);
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lpc32xx_i2c_init(1);
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lpc32xx_i2c_init(2);
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lpc32xx_ssp_init();
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@ -49,7 +49,7 @@ void spl_board_init(void)
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/* First of all silence buzzer controlled by GPO_20 */
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writel((1 << 20), &gpio->p3_outp_clr);
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lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
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lpc32xx_uart_init(CONFIG_CONS_INDEX);
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preloader_console_init();
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ddr_init(&dram_64mb);
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@ -37,7 +37,7 @@ void reset_periph(void)
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int board_early_init_f(void)
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{
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/* initialize serial port for console */
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lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
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lpc32xx_uart_init(CONFIG_CONS_INDEX);
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/* enable I2C, SSP, MAC, NAND */
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lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
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lpc32xx_ssp_init();
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@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = {
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void spl_board_init(void)
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{
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/* initialize serial port for console */
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lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
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lpc32xx_uart_init(CONFIG_CONS_INDEX);
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/* initialize console */
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preloader_console_init();
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/* init DDR and NAND to chainload U-Boot */
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@ -51,6 +51,8 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_ADDR=31
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CONFIG_PHY_SMSC=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_CONS_INDEX=5
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_USB=y
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@ -48,5 +48,7 @@ CONFIG_MTD_RAW_NAND=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_SMSC=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_CONS_INDEX=5
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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@ -30,11 +30,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
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- GENERATED_GBL_DATA_SIZE)
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/*
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* Serial Driver
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*/
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#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
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/*
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* DMA
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*/
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@ -35,11 +35,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
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- GENERATED_GBL_DATA_SIZE)
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/*
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* Serial Driver
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*/
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#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
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/*
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* Ethernet Driver
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*/
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@ -2734,7 +2734,6 @@ CONFIG_SYS_LOW
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CONFIG_SYS_LOWMEM_BASE
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CONFIG_SYS_LOW_RES_TIMER
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CONFIG_SYS_LPAE_SDRAM_BASE
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CONFIG_SYS_LPC32XX_UART
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CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
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CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
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CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
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