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imx: imx8mn_var_som: enable DM_SERIAL

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Enable CONFIG_DM_SERIAL. uart and its pinmux was already
marked with u-boot,dm-spl.
Move preloader_console_init after spl_init to make sure driver
model work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
This commit is contained in:
Peng Fan 2022-06-11 20:20:59 +08:00 committed by Stefano Babic
parent 64d118b27f
commit bb9e14cfd0
3 changed files with 3 additions and 11 deletions
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11
board/variscite/imx8mn_var_som/spl.c
View file

@ -40,14 +40,8 @@ void spl_board_init(void)
puts("Failed to find clock node. Check device tree\n");
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t uart_pads[] = {
IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
@ -59,7 +53,6 @@ int board_early_init_f(void)
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(3);
return 0;
@ -78,14 +71,14 @@ void board_init_f(ulong dummy)
timer_init();
preloader_console_init();
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
preloader_console_init();
/* DDR initialization */
spl_dram_init();

1
configs/imx8mn_var_som_defconfig
View file

@ -96,6 +96,7 @@ CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y

2
include/configs/imx8mn_var_som.h
View file

@ -53,8 +53,6 @@
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4)
/* USDHC */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0