From c93ad777b86c40497cf29d88e3a91381fc8ebe5c Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 12:54:07 +0530 Subject: [PATCH 01/31] treewide: Remove unused FSL QSPI config options for Layerscape platforms Some of these options are not used by the driver anymore and some of them are obsolete as the information is gathered from the dt. Also consolidating defines in common headers. Signed-off-by: Frieder Schrempf Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- .../include/asm/arch-fsl-layerscape/config.h | 1 - arch/arm/include/asm/arch-ls102xa/config.h | 1 - include/configs/ls1012a_common.h | 16 +--------------- include/configs/ls1012afrwy.h | 3 --- include/configs/ls1012ardb.h | 3 --- include/configs/ls1021aiot.h | 6 ------ include/configs/ls1021aqds.h | 11 ----------- include/configs/ls1021atwr.h | 10 ---------- include/configs/ls1043aqds.h | 2 -- include/configs/ls1046afrwy.h | 9 --------- include/configs/ls1046aqds.h | 11 ----------- include/configs/ls1046ardb.h | 13 ------------- include/configs/ls1088a_common.h | 6 ------ include/configs/ls1088aqds.h | 8 -------- include/configs/ls1088ardb.h | 18 ------------------ include/configs/ls2080aqds.h | 5 ----- include/configs/ls2080ardb.h | 6 +----- 17 files changed, 2 insertions(+), 127 deletions(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index ddd9390df4..cf2abda133 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -306,7 +306,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_PEX_LUT_BE diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 970537870d..3884948a2c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -94,7 +94,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE #define CONFIG_SYS_FSL_SEC_MON_LE #define CONFIG_SYS_FSL_SFP_VER_3_2 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index e9baa2a8b6..14d2483986 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -37,23 +37,9 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) /*SPI device */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT) #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 #define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_FSL_SPI_INTERFACE -#define CONFIG_SF_DATAFLASH - -#define QSPI0_AMBA_BASE 0x40000000 -#define CONFIG_SPI_FLASH_SPANSION - -#define FSL_QSPI_FLASH_SIZE SZ_64M -#define FSL_QSPI_FLASH_NUM 2 - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE -#endif /* SATA */ #define CONFIG_SCSI_AHCI_PLAT diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 97d3eb2f3d..1ea6548015 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -34,9 +34,6 @@ func(DHCP, dhcp, na) #endif -#undef FSL_QSPI_FLASH_SIZE -#define FSL_QSPI_FLASH_SIZE SZ_16M - /* MMC */ #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index c9d116d4d5..8fb75650e2 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -15,9 +15,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x40000000 #define CONFIG_CMD_MEMINFO - -/* ENV */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 /* * I2C IO expander */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 912345b2ef..3eff1be023 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -138,12 +138,6 @@ /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SPI_FLASH_SPANSION - -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_SPANSION #endif /* DM SPI */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 031bc6f172..e069467b53 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -363,20 +363,9 @@ unsigned long get_board_ddr_clk(void); * MMC */ -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* DSPI */ - /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) #define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_DATAFLASH -#endif #endif /* diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index cb56037a41..53a10ba4dd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -234,16 +234,6 @@ * MMC */ -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* DSPI */ -#endif - /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) #define CONFIG_DM_SPI_FLASH diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 95bf5fa102..84e7d5d1c6 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -381,8 +381,6 @@ unsigned long get_board_ddr_clk(void); (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 #endif #endif diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 4ccd3b0560..88d06ce7e4 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -96,10 +96,7 @@ /* * Environment */ -#define CONFIG_ENV_OVERWRITE - #define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 /* FMan */ @@ -117,12 +114,6 @@ #endif -/* QSPI device */ -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE SZ_64M -#define FSL_QSPI_FLASH_NUM 1 -#endif - #undef CONFIG_BOOTCOMMAND #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;;" diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index ff0d5fad9c..974aff1d4e 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -46,8 +46,6 @@ unsigned long get_board_ddr_clk(void); defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 #endif #endif @@ -419,16 +417,7 @@ unsigned long get_board_ddr_clk(void); /* * Environment */ -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_TFABOOT #define CONFIG_SYS_MMC_ENV_DEV 0 -#else -#ifdef CONFIG_NAND_BOOT -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif #define CONFIG_CMDLINE_TAG diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 1093761992..32a11ad0b9 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -153,19 +153,8 @@ /* * Environment */ -#ifndef SPL_NO_ENV -#define CONFIG_ENV_OVERWRITE -#endif - -#ifdef CONFIG_TFABOOT #define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#else -#if defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif #define AQR105_IRQ_MASK 0x80000000 /* FMan */ @@ -190,8 +179,6 @@ #ifndef SPL_NO_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 #endif #endif diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index ab5b396e1a..a7373429ba 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -35,13 +35,7 @@ #endif /* Link Definitions */ -#ifdef CONFIG_TFABOOT #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#else -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#endif -#endif #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 3bfd1d2a86..2bc910a3fc 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -358,14 +358,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 - -#endif - #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_SST diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index dec1ff9d7d..475207358f 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -8,16 +8,7 @@ #include "ls1088a_common.h" -#ifdef CONFIG_TFABOOT #define CONFIG_SYS_MMC_ENV_DEV 0 -#else -#if defined(CONFIG_QSPI_BOOT) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#else -#define CONFIG_ENV_IS_IN_FLASH -#endif -#endif /* CONFIG_TFABOOT */ #if defined(CONFIG_TFABOOT) || \ defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) @@ -268,15 +259,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#ifndef SPL_NO_QSPI -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 -#endif -#endif - #define CONFIG_CMD_MEMINFO #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 8ab892b5c3..751325ad69 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -276,7 +276,6 @@ unsigned long get_board_ddr_clk(void); #define I2C_MUX_CH_DEFAULT 0x8 /* SPI */ -#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_SST @@ -285,8 +284,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ -#define FSL_QSPI_FLASH_NUM 4 #endif /* * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. @@ -295,8 +292,6 @@ unsigned long get_board_ddr_clk(void); */ #define FSL_QIXIS_BRDCFG9_QSPI 0x1 -#endif - /* * MMC */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index c1819d22a8..a35bb0f36c 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -273,13 +273,9 @@ unsigned long get_board_sys_clk(void); #define I2C_MUX_CH_DEFAULT 0x8 /* SPI */ -#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) -#ifdef CONFIG_FSL_DSPI +#if defined(CONFIG_FSL_DSPI) #define CONFIG_SPI_FLASH_STMICRO #endif -#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ -#define FSL_QSPI_FLASH_NUM 2 -#endif /* * RTC configuration From 6146f75b22eb5e92a096fe12f77670a299f01200 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 14:28:56 +0530 Subject: [PATCH 02/31] configs: ls1043a: Move CONFIG_FSL_QSPI and SPI_FLASH_SPANSION to defconfig Move CONFIG_FSL_QSPI to the board defconfigs and while at it also move CONFIG_SPI_FLASH_SPANSION for LS1043AQDS. Signed-off-by: Frieder Schrempf Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 ++ configs/ls1043aqds_tfa_defconfig | 1 + include/configs/ls1043aqds.h | 8 -------- 5 files changed, 5 insertions(+), 8 deletions(-) diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 9ea003e735..a018b22fa9 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index c5887cce44..a7252ac115 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index f10d4d9425..3ee5d2869c 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -48,6 +48,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y @@ -62,6 +63,7 @@ CONFIG_DM_SCSI=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index 4fcdca83e7..297788b648 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -58,6 +58,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=1 # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 84e7d5d1c6..46baeb0d0d 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -376,14 +376,6 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MIN 819 #define VDD_MV_MAX 1212 -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#endif -#endif - /* * Miscellaneous configurable options */ From fe6ab29290b69ecc9c836c88aeb9ac469e0c104d Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 14:31:07 +0530 Subject: [PATCH 03/31] configs: ls1012a: Enable CONFIG_SPI_FLASH_SPANSION in defconfigs Since CONFIG_FSL_QSPI is already enabled for LS1012A in defconfigs. Also enable CONFIG_SPI_FLASH_SPANSION for LS1012A boards having spansion flashes. Signed-off-by: Ashish Kumar Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1012a2g5rdb_qspi_defconfig | 1 + configs/ls1012a2g5rdb_tfa_defconfig | 1 + configs/ls1012afrdm_qspi_defconfig | 1 + configs/ls1012afrdm_tfa_defconfig | 1 + configs/ls1012aqds_qspi_defconfig | 1 + configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012aqds_tfa_defconfig | 1 + configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_qspi_defconfig | 1 + configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1012ardb_tfa_defconfig | 1 + include/configs/ls1012a_common.h | 1 - 12 files changed, 11 insertions(+), 1 deletion(-) diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 18b72b465c..0dd358a12c 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 4ca57d1deb..ababb3ac14 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 1a4cc37555..8dfbbe5b23 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_I2C=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 177fcd4ff6..bdea547cbd 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -41,6 +41,7 @@ CONFIG_DM_I2C=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 1c3d7bcd75..7924d03602 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -60,6 +60,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 0833a2ae5e..3db97c9601 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -49,6 +49,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 7fc9e15bc4..8830259b3b 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -60,6 +60,7 @@ CONFIG_SF_DEFAULT_BUS=1 CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=10000000 # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index b6110c022a..af86efd72a 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -44,6 +44,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_E1000=y CONFIG_PCI=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 9c2a308e73..92a364f7b1 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -46,6 +46,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 736810d773..0017675299 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -43,6 +43,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index fc3dc4a0e7..63d5580a68 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -46,6 +46,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_ETH=y diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 14d2483986..6aa88c1c64 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -39,7 +39,6 @@ /*SPI device */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_SPI_FLASH_SPANSION /* SATA */ #define CONFIG_SCSI_AHCI_PLAT From 160e3b38e9c91abe8718f9281fcc8661e9d88ea2 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 14:32:39 +0530 Subject: [PATCH 04/31] configs: ls1046a: Move SPI_FLASH_SPANSION to defconfig Enable CONFIG_SPI_FLASH_SPANSION in defconfigs of LS1046ARDB and LS1046AQDS which have two spansion flases i.e s25fs512s each of size 64M. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_qspi_defconfig | 1 + configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + include/configs/ls1046aqds.h | 8 -------- include/configs/ls1046ardb.h | 7 ------- 10 files changed, 8 insertions(+), 15 deletions(-) diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index b98101d0b5..c31c37446b 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -42,6 +42,7 @@ CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 616e420e0d..a66b1bdca9 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 03cd17feb6..2b84a6bee5 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index d50a8ebd7f..07cdf8d5f5 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -57,6 +57,7 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_SF_DEFAULT_BUS=1 # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 1f8922293f..f29e86b8f9 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 8b1b6950fb..6c2b157e21 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -40,6 +40,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 140da79d0b..7db5174111 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -37,6 +37,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index eab34cd717..0185d8c423 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -42,6 +42,7 @@ CONFIG_FSL_ESDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y # CONFIG_SPI_FLASH_BAR is not set +CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 974aff1d4e..969d2c540b 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -41,14 +41,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPI_FLASH_EON /* cs2 */ #endif -/* QSPI */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#endif -#endif - #ifdef CONFIG_SYS_DPAA_FMAN #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 32a11ad0b9..fe8108dae0 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -175,13 +175,6 @@ #endif -/* QSPI device */ -#ifndef SPL_NO_QSPI -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#endif -#endif - #ifndef SPL_NO_MISC #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT From b480bcca805c350bf875f026ee816db502c88765 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 12 Dec 2019 11:49:24 +0530 Subject: [PATCH 05/31] treewide: Update fsl qspi node dt properties as per spi-mem driver According to new qspi driver, some properties like "bus-num, num-cs, big-endian" are no longer used. Device endiannes can be determined from device-type data in driver. Now use board specific compatibles, generic node names and specific labels to align with linux device-tree properties. Also consolidate spi-max-frequency to 50Mhz treewide. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-ls1012a-2g5rdb.dts | 5 ++--- arch/arm/dts/fsl-ls1012a-frdm.dtsi | 5 ++--- arch/arm/dts/fsl-ls1012a-qds.dtsi | 5 ++--- arch/arm/dts/fsl-ls1012a-rdb.dtsi | 5 ++--- arch/arm/dts/fsl-ls1012a.dtsi | 4 +--- arch/arm/dts/fsl-ls1043a-qds.dtsi | 5 ++--- arch/arm/dts/fsl-ls1043a.dtsi | 6 ++---- arch/arm/dts/fsl-ls1046a-frwy.dts | 5 ++--- arch/arm/dts/fsl-ls1046a-qds.dtsi | 5 ++--- arch/arm/dts/fsl-ls1046a-rdb.dts | 5 ++--- arch/arm/dts/fsl-ls1046a.dtsi | 4 +--- arch/arm/dts/fsl-ls1088a-qds.dts | 5 ++--- arch/arm/dts/fsl-ls1088a-rdb.dts | 5 ++--- arch/arm/dts/fsl-ls1088a.dtsi | 2 +- arch/arm/dts/fsl-ls2080a-qds.dts | 5 ++--- arch/arm/dts/fsl-ls2080a.dtsi | 4 ++-- arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 5 ++--- arch/arm/dts/ls1021a-twr.dtsi | 5 ++--- arch/arm/dts/ls1021a.dtsi | 6 ++---- 19 files changed, 35 insertions(+), 56 deletions(-) diff --git a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts index fecef88e08..6402cf5aca 100644 --- a/arch/arm/dts/fsl-ls1012a-2g5rdb.dts +++ b/arch/arm/dts/fsl-ls1012a-2g5rdb.dts @@ -21,14 +21,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi index a357793bfa..88aa24a6d2 100644 --- a/arch/arm/dts/fsl-ls1012a-frdm.dtsi +++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi @@ -15,14 +15,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi index a330597b6c..910d2a5c77 100644 --- a/arch/arm/dts/fsl-ls1012a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi @@ -43,14 +43,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi index 55155fd321..3757051b78 100644 --- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi @@ -19,14 +19,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 1125e5753b..2d70c82a72 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -107,14 +107,12 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x4000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <1>; - big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 70e1a6a53f..884bdad196 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -53,14 +53,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fl128s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 0a959f0f2d..f7db44c0fa 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -210,14 +210,12 @@ status = "disabled"; }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, - <0x0 0x40000000 0x0 0x4000000>; + <0x0 0x40000000 0x0 0x1000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <2>; - big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts index d39159322a..cda05411d8 100644 --- a/arch/arm/dts/fsl-ls1046a-frwy.dts +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -19,13 +19,12 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: mt25qu512abb8esf@0 { + mt25qu512a0: flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "spi-flash"; + compatible = "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; }; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index 76dc397328..fec5c8ddb2 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -53,14 +53,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fl128s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index cac65a7afa..464129291c 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -21,10 +21,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -32,7 +31,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 4e91d5c995..8673a5db2a 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -211,14 +211,12 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x1550000 0x0 0x10000>, <0x0 0x40000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <4>; - big-endian; status = "disabled"; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index f07d0c6f27..4f37a28992 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -108,10 +108,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -119,7 +118,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts index 46a5780547..de92bf22e2 100644 --- a/arch/arm/dts/fsl-ls1088a-rdb.dts +++ b/arch/arm/dts/fsl-ls1088a-rdb.dts @@ -143,10 +143,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -154,7 +153,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 133cacb93e..bf303c6ad3 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -92,7 +92,7 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1088a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 13461b5c45..f91a48d9fd 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -72,14 +72,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs256s@0 { + s25fs256s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index fb5777e268..90a0a3f8fb 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -96,13 +96,13 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls2080a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <4>; + status = "disabled"; }; esdhc: esdhc@0 { diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 16b9aeec96..179ed19bf2 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -125,10 +125,9 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: s25fs512s@0 { + s25fs512s0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -136,7 +135,7 @@ reg = <0>; }; - qflash1: s25fs512s@1 { + s25fs512s1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index 27c96f9540..bf96af7e36 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -24,14 +24,13 @@ }; &qspi { - bus-num = <0>; status = "okay"; - qflash0: n25q128a13@0 { + n25q128a130: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; + spi-max-frequency = <50000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index e419d9c44f..0eeec43ccc 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -169,14 +169,12 @@ }; qspi: quadspi@1550000 { - compatible = "fsl,vf610-qspi"; + compatible = "fsl,ls1021a-qspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x1550000 0x10000>, - <0x40000000 0x4000000>; + <0x40000000 0x1000000>; reg-names = "QuadSPI", "QuadSPI-memory"; - num-cs = <2>; - big-endian; status = "disabled"; }; From d06fa06e091df6ea31d24e8f5bfe75e2edd857d2 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 11 Feb 2020 14:51:35 +0530 Subject: [PATCH 06/31] configs: ls1088a: Correct ENV_ADDR value CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. QSPI region starts from 0x20000000 offset. Correct the config value i.e 0x80500000 -> 0x20500000. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1088aqds_tfa_defconfig | 2 +- configs/ls1088ardb_tfa_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index e66a61c089..e4e20affec 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -39,7 +39,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x80500000 +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 1c36801e65..53b236ce9e 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x80500000 +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y From 59071804c1ac1167716509d138296e228eaea692 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 11 Feb 2020 14:56:42 +0530 Subject: [PATCH 07/31] configs: ls2080a: Correct ENV_ADDR value CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. QSPI region in LS2088ARDB and LS2088AQDS starts from 0x20000000 offset. Correct the config value i.e 0x80500000 -> 0x20500000. Also, define config value as 0x20300000 in qspi defconfig. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls2088aqds_tfa_defconfig | 2 +- configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 7c7bb345e1..4d8b0119ec 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -37,7 +37,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x80500000 +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index d312cc9628..f2eb8d765a 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 2a82fda0bf..4f5a98e77e 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -39,7 +39,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi" CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x80500000 +CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y From fa4d6a2a23fd86a543027a864bedbcd752fc7345 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 14:39:46 +0530 Subject: [PATCH 08/31] configs: ls1046a: Define ENV_ADDR value CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. The macro value is already defined in ls1046ardb_tfa_defconfig, also define the value as 0x40300000 in qspi_defconfig. ls1046aqds has one spansion flash "S25FL128S_64K" of size 16M with sector size 64K. Correct ENV_ADDR and ENV_SECT_SIZE value for QSPI and TFA defconfigs of the board. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 4 ++-- configs/ls1046ardb_qspi_defconfig | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index c31c37446b..00b3568276 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -34,6 +34,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)" CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x40300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 07cdf8d5f5..e412c05b53 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -4,7 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 -CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -42,7 +42,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_ADDR=0x60500000 +CONFIG_ENV_ADDR=0x40500000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 6c2b157e21..51978686b5 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -30,6 +30,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.i CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x40300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y From 6596e2e6fa4c82c02da5c7e6af50ace175226847 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 7 Feb 2020 22:09:09 +0530 Subject: [PATCH 09/31] configs: ls2080ardb: Make MC_INIT access flash memory as per spi-mem MC_INIT command currently access spi-nor flash memory directly. As per spi-mem framework, flash memory access via absolute addresses is no more possible. Use flash APIs to access memory instead of directly using it. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- include/configs/ls2080ardb.h | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index a35bb0f36c..2bf890c263 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -317,11 +317,15 @@ unsigned long get_board_sys_clk(void); #include #ifdef CONFIG_TFABOOT -#define QSPI_MC_INIT_CMD \ - "env exists secureboot && " \ - "esbc_validate 0x20640000 && " \ - "esbc_validate 0x20680000;" \ - "fsl_mc start mc 0x20a00000 0x20e00000 \0" +#define QSPI_MC_INIT_CMD \ + "sf probe 0:0; " \ + "sf read 0x80640000 0x640000 0x80000; " \ + "env exists secureboot && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000; " \ + "sf read 0x80a00000 0xa00000 0x300000; " \ + "sf read 0x80e00000 0xe00000 0x100000; " \ + "fsl_mc start mc 0x80a00000 0x80e00000 \0" #define SD_MC_INIT_CMD \ "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ "mmc read 0x80e00000 0x7000 0x800;" \ @@ -338,11 +342,15 @@ unsigned long get_board_sys_clk(void); "fsl_mc start mc 0x580a00000 0x580e00000 \0" #else #ifdef CONFIG_QSPI_BOOT -#define MC_INIT_CMD \ - "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x20640000 && " \ - "esbc_validate 0x20680000;" \ - "fsl_mc start mc 0x20a00000 0x20e00000 \0" +#define MC_INIT_CMD \ + "mcinitcmd=sf probe 0:0; " \ + "sf read 0x80640000 0x640000 0x80000; " \ + "env exists secureboot && " \ + "esbc_validate 0x80640000 && " \ + "esbc_validate 0x80680000; " \ + "sf read 0x80a00000 0xa00000 0x300000; " \ + "sf read 0x80e00000 0xe00000 0x100000; " \ + "fsl_mc start mc 0x80a00000 0x80e00000 \0" #elif defined(CONFIG_SD_BOOT) #define MC_INIT_CMD \ "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ From 934eb607adf74f8cc88c3e7f2ffe9c56e479f612 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Fri, 7 Feb 2020 22:15:18 +0530 Subject: [PATCH 10/31] configs: ls2080ardb: Make BOOT command access flash memory as per spi-mem BOOT command currently access spi-nor flash memory directly. As per spi-mem framework, flash memory access via absolute addresses is no more possible. Use flash APIs to access memory instead of directly using it. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- include/configs/ls2080ardb.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 2bf890c263..006a4c97fb 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -504,10 +504,13 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_TFABOOT #define QSPI_NOR_BOOTCOMMAND \ + "sf probe 0:0; " \ + "sf read 0x806c0000 0x6c0000 0x40000; " \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x206C0000; " \ + "&& esbc_validate 0x806c0000; " \ + "sf read 0x80d00000 0xd00000 0x100000; " \ "env exists mcinitcmd && " \ - "fsl_mc lazyapply dpl 0x20d00000; " \ + "fsl_mc lazyapply dpl 0x80d00000; " \ "run distro_bootcmd;run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -534,10 +537,13 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_QSPI_BOOT /* Try to boot an on-QSPI kernel first, then do normal distro boot */ #define CONFIG_BOOTCOMMAND \ + "sf probe 0:0; " \ + "sf read 0x806c0000 0x6c0000 0x40000; " \ "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x206C0000; " \ + "&& esbc_validate 0x806C0000; " \ + "sf read 0x80d00000 0xd00000 0x100000; " \ "env exists mcinitcmd && " \ - "fsl_mc lazyapply dpl 0x20d00000; " \ + "fsl_mc lazyapply dpl 0x80d00000; " \ "run distro_bootcmd;run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" #elif defined(CONFIG_SD_BOOT) From c084a8edf4e2b05ea0608ab2e97a9a22aff8013e Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Tue, 12 May 2020 14:58:51 +0530 Subject: [PATCH 11/31] configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size CONFIG_SYS_MALLOC_LEN is currently set to low value and leaves very less space to do malloc in flash environmet. Increase the value to get more memory and also make it align with other boards(ls1046a, ls1043a etc.) config values. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- include/configs/ls1012a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 6aa88c1c64..3bea9a9186 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -34,7 +34,7 @@ #define CONFIG_LAYERSCAPE_NS_ACCESS /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) /*SPI device */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 From 4364f018f03f036a0203f5714950bf5e259dcb82 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Wed, 29 Apr 2020 17:42:03 +0530 Subject: [PATCH 12/31] configs: ls1012a: Reduce CONFIG_ENV_SIZE to 0x2000 All LS1012A board variants have same CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE values. If both config values are same, flash environment cannot be saved. Since, CONFIG_ENV_SECT_SIZE needs to be same as that of flash sector size, this entry cannot be changed. Reduce CONFIG_ENV_SIZE value to 0x2000. This also helps in making config value aligned with other boards environemt size. Signed-off-by: Kuldeep Singh Signed-off-by: Ashish Kumar Reviewed-by: Priyanka Jain --- configs/ls1012a2g5rdb_qspi_defconfig | 2 +- configs/ls1012a2g5rdb_tfa_defconfig | 2 +- configs/ls1012afrdm_qspi_defconfig | 2 +- configs/ls1012afrdm_tfa_defconfig | 2 +- configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_qspi_defconfig | 2 +- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012afrwy_tfa_defconfig | 2 +- configs/ls1012aqds_qspi_defconfig | 2 +- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012aqds_tfa_defconfig | 2 +- configs/ls1012ardb_qspi_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_qspi_defconfig | 2 +- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1012ardb_tfa_defconfig | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig index 0dd358a12c..07ba4d6472 100644 --- a/configs/ls1012a2g5rdb_qspi_defconfig +++ b/configs/ls1012a2g5rdb_qspi_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012A2G5RDB=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index ababb3ac14..8999d01f66 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012A2G5RDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index 8dfbbe5b23..541cbb07ce 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRDM=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index bdea547cbd..b5043d7a18 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRDM=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig index a702cc82b9..f105aaf2bc 100644 --- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 187015c2b2..5b98bb4a01 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x1D0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 5071bb75df..9c89064150 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=2 diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index c5ed91a7d3..c514332bbb 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AFRWY=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x1D0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 7924d03602..65e8e5c791 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 3db97c9601..529cd08b12 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 8830259b3b..79d196c77b 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig index af86efd72a..1483e64d8c 100644 --- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_FSL_LS_PPA=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index 92a364f7b1..e39de4caf5 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_SYS_TEXT_BASE=0x40100000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x300000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index 0017675299..8b67798429 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y CONFIG_DM_GPIO=y CONFIG_QSPI_AHB_INIT=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 63d5580a68..3837d323be 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1012ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y From c43a4f827691c7cc3d23a693cd189ee5fd5d955f Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sat, 14 Dec 2019 19:32:56 +0530 Subject: [PATCH 13/31] configs: nxp: Enable CONFIG_SYS_RELOC_GD_ENV_ADDR Commit 323d3af59fe4 ("configs: ls1012ardb: Enable CONFIG_SYS_RELOC_GD_ENV_ADDR") enables the config only for LS1012ARDB. Apart from LS1012A-RDB, other platforms such as LS1012A-FRWY, LS2088A and LS1046A-RDB/FRWY also require this config to be enabled. This also helps in resolving booting crash observed in flash environment. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1012afrwy_qspi_defconfig | 1 + configs/ls1012afrwy_tfa_defconfig | 1 + configs/ls1046afrwy_tfa_defconfig | 1 + configs/ls1046ardb_tfa_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig index 5b98bb4a01..492276439e 100644 --- a/configs/ls1012afrwy_qspi_defconfig +++ b/configs/ls1012afrwy_qspi_defconfig @@ -35,6 +35,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x401D0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index c514332bbb..f4cbbf2751 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -35,6 +35,7 @@ CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x401D0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 48dc7acf9f..68271c35b2 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -32,6 +32,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x40500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 0185d8c423..06bedd66ff 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x40500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 4d8b0119ec..a3486e4a50 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 4f5a98e77e..b64e3dc1d2 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y From b84519cbd56f46d4acd8ef3e334145b2021fcd17 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 4 May 2020 11:34:55 +0530 Subject: [PATCH 14/31] configs: ls1012a: Unset ENV_ADDR value LS1012A-FRWY and LS1012A-RDB crashes in flash environment when CONFIG_ENV_ADDR value is set. Unset the config value in *_tfa_defconfig* to resolve booting crash. Following crash is observed: Using SERDES1 Protocol: 13576 (0x3508) "Synchronous Abort" handler, esr 0x96000006 elr: 00000000820452c0 lr : 0000000082013f54 (reloc) elr: 00000000b7b932c0 lr : 00000000b7b61f54 x0 : 0000000000000000 x1 : 000000007604e004 x2 : 0000000000000001 x3 : 0000000000000000 ... Code: 54ffff80 9100c000 17fffff7 f9402241 (3860c820) Resetting CPU ... Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- configs/ls1012afrwy_tfa_defconfig | 1 - configs/ls1012ardb_tfa_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index f4cbbf2751..2948fd57ec 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -34,7 +34,6 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x401D0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 3837d323be..e0d203d442 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -35,7 +35,6 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x40500000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y From 9b2e892eb6e30913ee8ca95f1a360d61785d0912 Mon Sep 17 00:00:00 2001 From: Madalin Bucur Date: Mon, 4 May 2020 13:09:12 +0300 Subject: [PATCH 15/31] driver: net: fm: minor fix in DM ETH support Bus callback functions for read/write/reset need to be set only for DM_ETH, moving endif a bit lower. Signed-off-by: Madalin Bucur Reviewed-by: Priyanka Jain --- drivers/net/fm/eth.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 5f1a023352..371c5d2de7 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -54,10 +54,10 @@ static void dtsec_configure_serdes(struct fm_eth *priv) bus.priv = priv->mac->phyregs; #else bus.priv = priv->pcs_mdio; -#endif bus.read = memac_mdio_read; bus.write = memac_mdio_write; bus.reset = memac_mdio_reset; +#endif qsgmii_loop: /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */ From 21a00d130e5f6290924657b8576b545fac8e0a5c Mon Sep 17 00:00:00 2001 From: Laurentiu Tudor Date: Mon, 4 May 2020 14:47:11 +0300 Subject: [PATCH 16/31] drivers: net: fsl-mc: fixup msi-map property Similarly to iommu-map, the msi-map property must also be fixed up in the device tree, in order for the icid -> streamid translation be possible in the MSI case as well. Signed-off-by: Laurentiu Tudor Reviewed-by: Diana Craciun Reviewed-by: Priyanka Jain --- drivers/net/fsl-mc/mc.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index fee372968a..9c4ba7dbda 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -317,7 +317,7 @@ void fdt_fixup_mc_ddr(u64 *base, u64 *size) void fdt_fsl_mc_fixup_iommu_map_entry(void *blob) { u32 *prop; - u32 iommu_map[4]; + u32 iommu_map[4], phandle; int offset; int lenp; @@ -346,6 +346,21 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob) fdt_setprop_inplace(blob, offset, "iommu-map", iommu_map, sizeof(iommu_map)); + + /* get phandle to MSI controller */ + prop = (u32 *)fdt_getprop(blob, offset, "msi-parent", 0); + if (!prop) { + debug("\n%s: ERROR: missing msi-parent\n", __func__); + return; + } + phandle = fdt32_to_cpu(*prop); + + /* also set msi-map property */ + fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START); + fdt_appendprop_u32(blob, offset, "msi-map", phandle); + fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_START); + fdt_appendprop_u32(blob, offset, "msi-map", FSL_DPAA2_STREAM_ID_END - + FSL_DPAA2_STREAM_ID_START + 1); } static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, From 237b26200964c4d0ff34d1bffc70127274a68571 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:12 +0300 Subject: [PATCH 17/31] arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6 Add nodes for DPMACs 1, 2 and 5-6 which were missing from the description. These will be later used on the LX2160AQDS specific DTS. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a.dtsi | 86 ++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index 73d04db7e4..1789da8638 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -2,7 +2,7 @@ /* * NXP lx2160a SOC common device tree source * - * Copyright 2018 NXP + * Copyright 2018-2020 NXP * */ @@ -383,6 +383,18 @@ #address-cells = <1>; #size-cells = <0>; + dpmac1: dpmac@1 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x1>; + status = "disabled"; + }; + + dpmac2: dpmac@2 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x2>; + status = "disabled"; + }; + dpmac3: dpmac@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; @@ -395,6 +407,78 @@ status = "disabled"; }; + dpmac5: dpmac@5 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x5>; + status = "disabled"; + }; + + dpmac6: dpmac@6 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x6>; + status = "disabled"; + }; + + dpmac7: dpmac@7 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x7>; + status = "disabled"; + }; + + dpmac8: dpmac@8 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x8>; + status = "disabled"; + }; + + dpmac9: dpmac@9 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x9>; + status = "disabled"; + }; + + dpmac10: dpmac@a { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xa>; + status = "disabled"; + }; + + dpmac11: dpmac@b { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xb>; + status = "disabled"; + }; + + dpmac12: dpmac@c { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xc>; + status = "disabled"; + }; + + dpmac13: dpmac@d { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xd>; + status = "disabled"; + }; + + dpmac14: dpmac@e { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xe>; + status = "disabled"; + }; + + dpmac15: dpmac@f { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0xf>; + status = "disabled"; + }; + + dpmac16: dpmac@10 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x10>; + status = "disabled"; + }; + dpmac17: dpmac@11 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x11>; From 3695e4ccfdd3baa29a0d64e4ed08ff1f0d602d09 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:13 +0300 Subject: [PATCH 18/31] arm: dts: lx2160aqds: add MDIO slots The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 8 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, DPMAC 17 and 18 are updated to reference the on-board PHYs. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- arch/arm/dts/fsl-lx2160a-qds.dts | 115 ++++++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 592fd5977e..4946ce8dfb 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -2,7 +2,7 @@ /* * NXP LX2160AQDS device tree source * - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ @@ -18,6 +18,26 @@ }; }; +&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + &esdhc0 { status = "okay"; }; @@ -30,6 +50,99 @@ status = "okay"; u-boot,dm-pre-reloc; + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@08 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ + reg = <0xC0>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ + reg = <0xC8>; + device-name = "emdio1_slot2"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ + reg = <0xD0>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ + reg = <0xD8>; + device-name = "emdio1_slot4"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ + reg = <0xE0>; + device-name = "emdio1_slot5"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ + reg = <0xE8>; + device-name = "emdio1_slot6"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ + reg = <0xF0>; + device-name = "emdio1_slot7"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ + reg = <0xF8>; + device-name = "emdio1_slot8"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; + i2c-mux@77 { compatible = "nxp,pca9547"; reg = <0x77>; From 74f04490f22428531f9fd5fcd9ca61b6e145a12b Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:14 +0300 Subject: [PATCH 19/31] arm: dts: lx2160aqds: add nodes describing possible mezzanine cards Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/dts/Makefile | 10 +- arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts | 19 +++ arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts | 17 +++ arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi | 75 ++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi | 39 +++++ arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi | 55 +++++++ arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi | 100 +++++++++++++ arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi | 76 ++++++++++ arch/arm/dts/fsl-lx2160a-qds.dts | 180 +---------------------- arch/arm/dts/fsl-lx2160a-qds.dtsi | 169 +++++++++++++++++++++ 16 files changed, 670 insertions(+), 178 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi create mode 100644 arch/arm/dts/fsl-lx2160a-qds.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ca663a86f2..f28fc371c3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -383,7 +383,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls1028a-qds-duart.dtb \ fsl-ls1028a-qds-lpuart.dtb \ fsl-lx2160a-rdb.dtb \ - fsl-lx2160a-qds.dtb + fsl-lx2160a-qds.dtb \ + fsl-lx2160a-qds-3-x-x.dtb \ + fsl-lx2160a-qds-3-11-x.dtb \ + fsl-lx2160a-qds-7-x-x.dtb \ + fsl-lx2160a-qds-7-11-x.dtb \ + fsl-lx2160a-qds-19-x-x.dtb \ + fsl-lx2160a-qds-19-11-x.dtb \ + fsl-lx2160a-qds-20-x-x.dtb \ + fsl-lx2160a-qds-20-11-x.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts new file mode 100644 index 0000000000..585759162f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 19.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-19.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts new file mode 100644 index 0000000000..ebe11396a6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 19.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-19.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts new file mode 100644 index 0000000000..d9f0918967 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 20.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-20.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts new file mode 100644 index 0000000000..735d440d37 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 20.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-20.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts new file mode 100644 index 0000000000..3b21c87b93 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 3.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-3.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts new file mode 100644 index 0000000000..ede40563f7 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 3.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-3.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts new file mode 100644 index 0000000000..8100af4727 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 7.11.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-7.dtsi" + +#include "fsl-lx2160a-qds-sd2-11.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts new file mode 100644 index 0000000000..15dee3587f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for SERDES protocol 7.x.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds-sd1-7.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)"; + compatible = "fsl,lx2160aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi new file mode 100644 index 0000000000..a31ff8a1bd --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy0>; + phy-connection-type = "xlaui4"; +}; + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot2 { + cortina_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi new file mode 100644 index 0000000000..42e149691d --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 20 + * + * Some assumptions are made: + * * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2 + * (xlaui4 for DPMAC 1,2) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&cortina_phy1_0>; + phy-connection-type = "xlaui4"; +}; + +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy2_0>; + phy-connection-type = "xlaui4"; +}; + +&emdio1_slot1 { + cortina_phy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + +&emdio1_slot2 { + cortina_phy2_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi new file mode 100644 index 0000000000..256d784aca --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&aquantia_phy3>; + phy-connection-type = "usxgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&aquantia_phy4>; + phy-connection-type = "usxgmii"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + aquantia_phy3: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + aquantia_phy4: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi new file mode 100644 index 0000000000..5fcf846c10 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6) + * * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10) + * + * Copyright 2020 NXP + * + */ +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&aquantia_phy3>; + phy-connection-type = "usxgmii"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&aquantia_phy4>; + phy-connection-type = "usxgmii"; +}; + +&dpmac7 { + status = "okay"; + phy-handle = <&sgmii_phy1>; + phy-connection-type = "sgmii"; +}; + +&dpmac8 { + status = "okay"; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; +}; + +&dpmac9 { + status = "okay"; + phy-handle = <&sgmii_phy3>; + phy-connection-type = "sgmii"; +}; + +&dpmac10 { + status = "okay"; + phy-handle = <&sgmii_phy4>; + phy-connection-type = "sgmii"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + aquantia_phy3: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + aquantia_phy4: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; + +&emdio1_slot2 { + sgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + sgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi new file mode 100644 index 0000000000..cf09f98aa6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11 + * + * Some assumptions are made: + * * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8 + * (sgmii for DPMAC 12, 13, 14, 16, 17, 18) + * + * Copyright 2020 NXP + * + */ +#include "fsl-lx2160a-qds.dtsi" + +&dpmac12 { + status = "okay"; + phy-handle = <&sgmii_phy7_2>; + phy-connection-type = "sgmii"; +}; + +&dpmac17 { + status = "okay"; + phy-handle = <&sgmii_phy7_3>; + phy-connection-type = "sgmii"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&sgmii_phy7_4>; + phy-connection-type = "sgmii"; +}; + +&dpmac16 { + status = "okay"; + phy-handle = <&sgmii_phy8_2>; + phy-connection-type = "sgmii"; +}; + +&dpmac13 { + status = "okay"; + phy-handle = <&sgmii_phy8_3>; + phy-connection-type = "sgmii"; +}; + +&dpmac14 { + status = "okay"; + phy-handle = <&sgmii_phy8_4>; + phy-connection-type = "sgmii"; +}; + +&emdio1_slot7 { + sgmii_phy7_2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy7_3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy7_4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&emdio1_slot8 { + sgmii_phy8_2: ethernet-phy@1d { + reg = <0x1d>; + }; + + sgmii_phy8_3: ethernet-phy@1e { + reg = <0x1e>; + }; + + sgmii_phy8_4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index 4946ce8dfb..e0f5d5e2d3 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * NXP LX2160AQDS device tree source + * NXP LX2160AQDS default device tree source * - * Copyright 2018-2020 NXP + * Copyright 2020 NXP * */ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-qds.dtsi" / { model = "NXP Layerscape LX2160AQDS Board"; @@ -17,177 +17,3 @@ spi0 = &fspi; }; }; - -&dpmac17 { - status = "okay"; - phy-handle = <&rgmii_phy1>; - phy-connection-type = "rgmii-id"; -}; - -&dpmac18 { - status = "okay"; - phy-handle = <&rgmii_phy2>; - phy-connection-type = "rgmii-id"; -}; - -&emdio1 { - status = "okay"; -}; - -&emdio2 { - status = "okay"; -}; - -&esdhc0 { - status = "okay"; -}; - -&esdhc1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - fpga@66 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-mfd"; - reg = <0x66>; - - mux-mdio@54 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "mdio-mux-i2creg"; - reg = <0x54>; - #mux-control-cells = <1>; - mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 - mdio-parent-bus = <&emdio1>; - - mdio@00 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - - rgmii_phy1: ethernet-phy@1 { - reg = <0x1>; - }; - }; - mdio@08 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40>; - - rgmii_phy2: ethernet-phy@2 { - reg = <0x2>; - }; - }; - - emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ - reg = <0xC0>; - device-name = "emdio1_slot1"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ - reg = <0xC8>; - device-name = "emdio1_slot2"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ - reg = <0xD0>; - device-name = "emdio1_slot3"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ - reg = <0xD8>; - device-name = "emdio1_slot4"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ - reg = <0xE0>; - device-name = "emdio1_slot5"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ - reg = <0xE8>; - device-name = "emdio1_slot6"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ - reg = <0xF0>; - device-name = "emdio1_slot7"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ - reg = <0xF8>; - device-name = "emdio1_slot8"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - }; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; - }; - }; -}; - -&fspi { - status = "okay"; - - mt35xu512aba0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-rx-bus-width = <8>; - spi-tx-bus-width = <1>; - }; -}; - -&sata0 { - status = "okay"; -}; - -&sata1 { - status = "okay"; -}; - -&sata2 { - status = "okay"; -}; - -&sata3 { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi new file mode 100644 index 0000000000..129cf82a8f --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2160AQDS common device tree source + * + * Copyright 2018-2019 NXP + * + */ + +#include "fsl-lx2160a.dtsi" + +&dpmac17 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@08 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@c0 { /* I/O Slot #1 */ + reg = <0xC0>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot2: mdio@c8 { /* I/O Slot #2 */ + reg = <0xC8>; + device-name = "emdio1_slot2"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@d0 { /* I/O Slot #3 */ + reg = <0xD0>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot4: mdio@d8 { /* I/O Slot #4 */ + reg = <0xD8>; + device-name = "emdio1_slot4"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot5: mdio@e0 { /* I/O Slot #5 */ + reg = <0xE0>; + device-name = "emdio1_slot5"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot6: mdio@e8 { /* I/O Slot #6 */ + reg = <0xE8>; + device-name = "emdio1_slot6"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot7: mdio@f0 { /* I/O Slot #7 */ + reg = <0xF0>; + device-name = "emdio1_slot7"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot8: mdio@f8 { /* I/O Slot #8 */ + reg = <0xF8>; + device-name = "emdio1_slot8"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; From 4057bddaa230de0d77ec6357fd556ea192ab1412 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:15 +0300 Subject: [PATCH 20/31] board: lx2160aqds: transition to DM_ETH In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/eth_lx2160aqds.c | 12 +++++++++++- board/freescale/lx2160a/lx2160a.c | 5 +++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 0e928ebd86..3b7830343d 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_DM_ETH #define EMI_NONE 0 #define EMI1 1 /* Mdio Bus 1 */ #define EMI2 2 /* Mdio Bus 2 */ @@ -439,9 +440,11 @@ static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, } #endif +#endif /* !CONFIG_DM_ETH */ int board_eth_init(bd_t *bis) { +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) struct memac_mdio_info mdio_info; struct memac_mdio_controller *regs; @@ -564,6 +567,7 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ +#endif /* !CONFIG_DM_ETH */ #ifdef CONFIG_PHY_AQUANTIA /* @@ -577,7 +581,12 @@ int board_eth_init(bd_t *bis) gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; #endif + +#ifdef CONFIG_DM_ETH + return 0; +#else return pci_eth_init(bis); +#endif } #if defined(CONFIG_RESET_PHY_R) @@ -589,6 +598,7 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) { @@ -837,4 +847,4 @@ int fdt_fixup_board_phy(void *fdt) return ret; } #endif // CONFIG_FSL_MC_ENET - +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 0d94107def..4be9882994 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -584,6 +584,9 @@ int board_init(void) sec_init(); #endif +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif return 0; } @@ -629,7 +632,9 @@ void fdt_fixup_board_enet(void *fdt) if (get_mc_boot_status() == 0 && (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); +#ifndef CONFIG_DM_ETH fdt_fixup_board_phy(fdt); +#endif } else { fdt_status_fail(fdt, offset); } From f49613f4aa19c41051b9a5436898d7a2e459b3e4 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:16 +0300 Subject: [PATCH 21/31] board: lx2160aqds: implement board_fit_config_name_match In case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS for the current SERDES protocol configuration. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/eth_lx2160aqds.c | 109 +++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 3b7830343d..d90b5c3e3a 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -848,3 +848,112 @@ int fdt_fixup_board_phy(void *fdt) } #endif // CONFIG_FSL_MC_ENET #endif + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 3, true}, + {1, 7, true}, + {1, 19, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 11, true}, + + /* Serdes block #3 */ + {3, 2, false}, + {3, 3, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2]; + u32 srds_s1, srds_s2, srds_s3; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK; + srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2) || + !protocol_supported(3, srds_s3)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + get_str_protocol(3, srds_s3, srds_s3_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s", + srds_s1_str, srds_s2_str, srds_s3_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif From c0be08a577567eb10230934b5fa9de6a9a106824 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:17 +0300 Subject: [PATCH 22/31] configs: lx2160aqds_tfa_defconfig: enable DM_ETH and related Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LX2160AQDS board. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 8 ++++++++ configs/lx2160aqds_tfa_defconfig | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index cd7b413bfc..51d5dc356e 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -31,6 +32,8 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y @@ -53,7 +56,12 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 9b6ce38554..716c089ba9 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -23,6 +23,7 @@ CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x2 CONFIG_MISC_INIT_R=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -33,6 +34,8 @@ CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_OF_BOARD_FIXUP=y CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 @@ -57,7 +60,12 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y From 62d3a58dcef90aeb2e2aae7349ecf6d7bce8d54a Mon Sep 17 00:00:00 2001 From: Pankit Garg Date: Thu, 30 Apr 2020 15:54:05 +0530 Subject: [PATCH 23/31] board_r: Detect ifc-nor flash at run-time CONFIG_MTD_NOR_FLASH flag needs to be enable for all boot sources,as all flash drivers need to compile in TFA Boot.Probe ifc nor flash only when there is nor flash available on board.So needs to detect ifc-nor flash at run-time for probing. Signed-off-by: Pankit Garg Reviewed-by: Priyanka Jain --- common/board_r.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/common/board_r.c b/common/board_r.c index 96034b874e..b04e6ad2a9 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -369,11 +369,19 @@ static int initr_binman(void) } #if defined(CONFIG_MTD_NOR_FLASH) +__weak int is_flash_available(void) +{ + return 1; +} + static int initr_flash(void) { ulong flash_size = 0; bd_t *bd = gd->bd; + if (!is_flash_available()) + return 0; + puts("Flash: "); if (board_flash_wp_on()) From d5b0af047a942b21ea86476e3931df28445b1ca4 Mon Sep 17 00:00:00 2001 From: Razvan Ionut Cirjan Date: Tue, 28 Apr 2020 16:09:59 +0300 Subject: [PATCH 24/31] net: fsl-mc: fixup DPC: add /board/ports node if missing The DPC fixup for MAC address and enet_if is not made if /board/ports node is missing in DPC file. Add /board/ports or /ports nodes if them are missing. Signed-off-by: Razvan Ionut Cirjan Reviewed-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- drivers/net/fsl-mc/mc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 9c4ba7dbda..3621842016 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2020 NXP */ #include #include @@ -478,8 +478,19 @@ static int mc_fixup_dpc(u64 dpc_addr) /* fixup MAC addresses for dpmac ports */ nodeoffset = fdt_path_offset(blob, "/board_info/ports"); - if (nodeoffset < 0) - goto out; + if (nodeoffset < 0) { + err = fdt_increase_size(blob, 512); + if (err) { + printf("fdt_increase_size: err=%s\n", + fdt_strerror(err)); + goto out; + } + nodeoffset = fdt_path_offset(blob, "/board_info"); + if (nodeoffset < 0) + nodeoffset = fdt_add_subnode(blob, 0, "board_info"); + + nodeoffset = fdt_add_subnode(blob, nodeoffset, "ports"); + } err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC); From 1ff0c9d59c7a151956aaac0fc72c85e927617ce3 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Wed, 29 Apr 2020 15:00:41 +0530 Subject: [PATCH 25/31] include/configs: ls1046afrwy: add support for boot targets. ls1046afrwy does not support sata boot. So Override default BOOT_TARGET_DEVICES and support only mmc, usb and dhcp as boot targets. Signed-off-by: Pramod Kumar [Rebased] Signed-off-by: Priyanka Jain --- include/configs/ls1046afrwy.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 88d06ce7e4..44e7fc3a72 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __LS1046AFRWY_H__ @@ -99,6 +99,14 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#ifndef CONFIG_SPL_BUILD +#undef BOOT_TARGET_DEVICES +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#endif + /* FMan */ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET From b62526282ab2e505148d8c962dfb888f155ec7e9 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 15 May 2020 09:56:48 +0300 Subject: [PATCH 26/31] arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei Signed-off-by: Priyanka Jain --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-ls1088a-qds-21-x.dts | 16 ++ arch/arm/dts/fsl-ls1088a-qds-29-x.dts | 16 ++ arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 30 ++++ arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 18 +++ arch/arm/dts/fsl-ls1088a-qds.dts | 123 +-------------- arch/arm/dts/fsl-ls1088a-qds.dtsi | 186 +++++++++++++++++++++++ board/freescale/ls1088a/eth_ls1088aqds.c | 87 +++++++++++ 8 files changed, 358 insertions(+), 120 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-21-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-29-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f28fc371c3..d6f799635d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -379,6 +379,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ fsl-ls1088a-qds.dtb \ + fsl-ls1088a-qds-21-x.dtb \ + fsl-ls1088a-qds-29-x.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds-duart.dtb \ fsl-ls1028a-qds-lpuart.dtb \ diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x.dts b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts new file mode 100644 index 0000000000..a877964511 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES protocol 21.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1088a-qds-sd1-21.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board (DTS 21-x)"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x.dts b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts new file mode 100644 index 0000000000..29c4ec59fe --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES protocol 29.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1088a-qds-sd1-29.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board (DTS 29-x)"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi new file mode 100644 index 0000000000..e0a6c04835 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls1088a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi new file mode 100644 index 0000000000..65e95300ab --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls1088a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 4f37a28992..8e64e713aa 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -1,132 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * NXP ls1088a QDS board device tree source + * NXP ls1088a QDS default board device tree source * - * Copyright 2017 NXP + * Copyright 2020 NXP */ /dts-v1/; -#include "fsl-ls1088a.dtsi" +#include "fsl-ls1088a-qds.dtsi" / { model = "NXP Layerscape 1088a QDS Board"; compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - aliases { - spi0 = &qspi; - spi1 = &dspi; - }; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus", "fsl,ls1088aqds-fpga", - "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 2 0 0x100>; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; /* input clock */ - }; - - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3500000>; - reg = <1>; - }; - - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3500000>; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi new file mode 100644 index 0000000000..a7d0edcf0a --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1088a QDS common board device tree source + * + * Copyright 2017-2020 NXP + */ + +#include "fsl-ls1088a.dtsi" + +/ { + aliases { + spi0 = &qspi; + spi1 = &dspi; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@20 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x20>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@40 { /* I/O Slot #1 */ + reg = <0x40>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@60 { /* I/O Slot #3 */ + reg = <0x60>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus", "fsl,ls1088aqds-fpga", + "fsl,fpga-qixis"; + reg = <0x2 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 2 0 0x100>; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + s25fs512s1: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 54ef75347f..c0bcf71299 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -742,3 +742,90 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 21, true}, + {1, 29, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + char expected_dts[100]; + char srds_s1_str[2]; + u32 srds_s1, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + + sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif From 791ec1b9e0adaf00750256497c567b74dde3b176 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 15 May 2020 09:56:49 +0300 Subject: [PATCH 27/31] board: ls1088aqds: transition to DM_ETH In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- board/freescale/ls1088a/eth_ls1088aqds.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index c0bcf71299..7456f67f3d 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -24,6 +24,7 @@ #include "ls1088a_qixis.h" +#ifndef CONFIG_DM_ETH #ifdef CONFIG_FSL_MC_ENET #define SFP_TX 0 @@ -735,6 +736,7 @@ int board_eth_init(bd_t *bis) error = pci_eth_init(bis); return error; } +#endif // !CONFIG_DM_ETH #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) From e58ac2dd7bb9cc74f9538dc71349a444bf8e2cda Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 15 May 2020 09:56:50 +0300 Subject: [PATCH 28/31] configs: ls1088aqds_tfa_defconfig: enable DM_ETH and related Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LS1088AQDS board. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- configs/ls1088aqds_tfa_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index e4e20affec..c184843a6d 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -35,6 +36,8 @@ CONFIG_CMD_USB=y CONFIG_MP=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-qds" +CONFIG_OF_LIST="fsl-ls1088a-qds-21-x fsl-ls1088a-qds-29-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y @@ -66,8 +69,13 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y From 8cbef912ee8e73fccf2543428e73ecd25d386dba Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 18 May 2020 14:48:35 +0300 Subject: [PATCH 29/31] board: ls2080aqds: transition to DM_ETH In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- board/freescale/ls2080aqds/eth.c | 15 ++++++++++++--- board/freescale/ls2080aqds/ls2080aqds.c | 4 ++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index bbb70a859a..2b1b106b07 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -24,6 +24,8 @@ #define MC_BOOT_ENV_VAR "mcinitcmd" +#ifndef CONFIG_DM_ETH + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H @@ -889,10 +891,11 @@ void ls2080a_handle_phy_interface_xsgmii(int i) } } #endif +#endif // !CONFIG_DM_ETH int board_eth_init(bd_t *bis) { - int error; +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -906,6 +909,7 @@ int board_eth_init(bd_t *bis) struct memac_mdio_info *memac_mdio1_info; unsigned int i; char *env_hwconfig; + int error; env_hwconfig = env_get("hwconfig"); @@ -970,8 +974,13 @@ int board_eth_init(bd_t *bis) sgmii_configure_repeater(2); } #endif - error = pci_eth_init(bis); - return error; +#endif // !CONFIG_DM_ETH + +#ifdef CONFIG_DM_ETH + return 0; +#else + return pci_eth_init(bis); +#endif } #if defined(CONFIG_RESET_PHY_R) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 4034bdee28..1c91c5b7f0 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -251,6 +251,10 @@ int board_init(void) ppa_init(); #endif +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif + return 0; } From 020ed9c666748b103e0740622ca4128a2bd40f29 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 18 May 2020 14:48:36 +0300 Subject: [PATCH 30/31] arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls2080a-qds-42-x.dts | 16 ++++ arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 48 ++++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 72 +----------------- arch/arm/dts/fsl-ls2080a-qds.dtsi | 77 +++++++++++++++++++ board/freescale/ls2080aqds/eth.c | 97 ++++++++++++++++++++++++ 6 files changed, 241 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-qds-42-x.dts create mode 100644 arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi create mode 100644 arch/arm/dts/fsl-ls2080a-qds.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d6f799635d..2404eaa5ee 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ diff --git a/arch/arm/dts/fsl-ls2080a-qds-42-x.dts b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts new file mode 100644 index 0000000000..bd46c395d4 --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080AQDS device tree source for SERDES protocol 42.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls2080a-qds-sd1-42.dtsi" + +/ { + model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi new file mode 100644 index 0000000000..ccbb5de1ea --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac3 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac5 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac6 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac7 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac8 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index f91a48d9fd..a1196f9292 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a QDS board device tree source + * Freescale ls2080a QDS defaul board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. */ /dts-v1/; -#include "fsl-ls2080a.dtsi" +#include "fsl-ls2080a-qds.dtsi" / { model = "Freescale Layerscape 2080a QDS Board"; @@ -18,71 +18,3 @@ spi1 = &dspi; }; }; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs256s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi new file mode 100644 index 0000000000..cb7851f2cc --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Freescale ls2080a QDS common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a.dtsi" + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs256s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 2b1b106b07..0d6eec377f 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -989,3 +989,100 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 42, true}, + + /* Serdes block #2 */ + {2, 65, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + printf("expected_dts %s\n", expected_dts); + sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + printf("this is not!\n"); + return -1; +} + +#endif From 13bc860727ee406f073c8176dd2d6b9dacf35443 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 18 May 2020 14:48:37 +0300 Subject: [PATCH 31/31] configs: ls2080aqds_tfa_defconfig: enable DM_ETH and related Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LS2080AQDS board. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- configs/ls2088aqds_tfa_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index a3486e4a50..ad17ef1703 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -22,6 +22,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -34,6 +35,8 @@ CONFIG_MP=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_OF_LIST="fsl-ls2080a-qds-42-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -62,9 +65,14 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_REALTEK=y CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y