Difuse/u-boot
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

clk: sunxi: h3: Implement EPHY CLK and RESET

Browse source 
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Jagan Teki 2019-02-28 00:26:59 +05:30
parent 68620c9698
commit aefc0b7a60
1 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/clk/sunxi/clk_h3.c
View file

@ -34,6 +34,8 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
[CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
@ -69,6 +71,8 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
[RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),