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Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig

Browse source 
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
Introduce select statements for other architectures based on current
usage.  For MIPS, we take the existing arch-specific symbol and migrate
to the generic symbol.  This lets us remove a little bit of otherwise
unused code.

Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Leo <ycliang@andestech.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Tom Rini 2021-08-26 11:47:59 -04:00
parent e4ddf14305
commit ab92b38a01
35 changed files with 68 additions and 103 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
arch/Kconfig
View file

@ -7,6 +7,27 @@ config HAVE_ARCH_IOREMAP
config NEEDS_MANUAL_RELOC config NEEDS_MANUAL_RELOC
bool bool
config SYS_CACHE_SHIFT_4
bool
config SYS_CACHE_SHIFT_5
bool
config SYS_CACHE_SHIFT_6
bool
config SYS_CACHE_SHIFT_7
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
default 16 if SYS_CACHE_SHIFT_4
# Fall-back for MIPS
default 32 if MIPS
config LINKER_LIST_ALIGN config LINKER_LIST_ALIGN
int int
default 32 if SANDBOX default 32 if SANDBOX
@ -29,6 +50,7 @@ config ARC
select DM select DM
select HAVE_PRIVATE_LIBGCC select HAVE_PRIVATE_LIBGCC
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_7
select TIMER select TIMER
config ARM config ARM
@ -44,6 +66,7 @@ config M68K
select NEEDS_MANUAL_RELOC select NEEDS_MANUAL_RELOC
select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_CMDLINE
select SYS_BOOT_GET_KBD select SYS_BOOT_GET_KBD
select SYS_CACHE_SHIFT_4
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
config MICROBLAZE config MICROBLAZE
@ -122,6 +145,7 @@ config SANDBOX
select SPI select SPI
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF select SYSRESET_CMD_POWEROFF
select SYS_CACHE_SHIFT_4
select IRQ select IRQ
select SUPPORT_EXTENSION_SCAN select SUPPORT_EXTENSION_SCAN
imply BITREVERSE imply BITREVERSE
@ -188,6 +212,7 @@ config X86
select OF_CONTROL select OF_CONTROL
select PCI select PCI
select SUPPORT_OF_CONTROL select SUPPORT_OF_CONTROL
select SYS_CACHE_SHIFT_6
select TIMER select TIMER
select USE_PRIVATE_LIBGCC select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER select X86_TSC_TIMER

3
arch/arc/include/asm/cache.h
View file

@ -16,9 +16,6 @@
*/ */
#define ARCH_DMA_MINALIGN 128 #define ARCH_DMA_MINALIGN 128
/* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#if defined(ARC_MMU_ABSENT) #if defined(ARC_MMU_ABSENT)
#define CONFIG_ARC_MMU_VER 0 #define CONFIG_ARC_MMU_VER 0
#elif defined(CONFIG_ARC_MMU_V2) #elif defined(CONFIG_ARC_MMU_V2)

15
arch/arm/Kconfig
View file

@ -338,21 +338,6 @@ config SYS_ARM_ARCH
default 4 if CPU_SA1100 default 4 if CPU_SA1100
default 8 if ARM64 default 8 if ARM64
config SYS_CACHE_SHIFT_5
bool
config SYS_CACHE_SHIFT_6
bool
config SYS_CACHE_SHIFT_7
bool
config SYS_CACHELINE_SIZE
int
default 128 if SYS_CACHE_SHIFT_7
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
choice choice
prompt "Select the ARM data write cache policy" prompt "Select the ARM data write cache policy"
default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \

26
arch/mips/Kconfig
View file

@ -22,7 +22,7 @@ config TARGET_MALTA
select DYNAMIC_IO_PORT_BASE select DYNAMIC_IO_PORT_BASE
select MIPS_CM select MIPS_CM
select MIPS_INSERT_BOOT_CONFIG select MIPS_INSERT_BOOT_CONFIG
select MIPS_L1_CACHE_SHIFT_6 select SYS_CACHE_SHIFT_6
select MIPS_L2_CACHE select MIPS_L2_CACHE
select OF_CONTROL select OF_CONTROL
select OF_ISA_BUS select OF_ISA_BUS
@ -132,7 +132,7 @@ config TARGET_BOSTON
select DM select DM
select DM_SERIAL select DM_SERIAL
select MIPS_CM select MIPS_CM
select MIPS_L1_CACHE_SHIFT_6 select SYS_CACHE_SHIFT_6
select MIPS_L2_CACHE select MIPS_L2_CACHE
select OF_BOARD_SETUP select OF_BOARD_SETUP
select OF_CONTROL select OF_CONTROL
@ -153,7 +153,7 @@ config TARGET_XILFPGA
select DM_ETH select DM_ETH
select DM_GPIO select DM_GPIO
select DM_SERIAL select DM_SERIAL
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select OF_CONTROL select OF_CONTROL
select ROM_EXCEPTION_VECTORS select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -566,26 +566,6 @@ config SYS_CACHE_SIZE_AUTO
so if you know the cache configuration for your system at compile so if you know the cache configuration for your system at compile
time it would be beneficial to configure it. time it would be beneficial to configure it.
config MIPS_L1_CACHE_SHIFT_4
bool
config MIPS_L1_CACHE_SHIFT_5
bool
config MIPS_L1_CACHE_SHIFT_6
bool
config MIPS_L1_CACHE_SHIFT_7
bool
config MIPS_L1_CACHE_SHIFT
int
default "7" if MIPS_L1_CACHE_SHIFT_7
default "6" if MIPS_L1_CACHE_SHIFT_6
default "5" if MIPS_L1_CACHE_SHIFT_5
default "4" if MIPS_L1_CACHE_SHIFT_4
default "5"
config MIPS_L2_CACHE config MIPS_L2_CACHE
bool bool
help help

12
arch/mips/include/asm/cache.h
View file

@ -6,17 +6,7 @@
#ifndef __MIPS_CACHE_H__ #ifndef __MIPS_CACHE_H__
#define __MIPS_CACHE_H__ #define __MIPS_CACHE_H__
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
/*
* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
* of ARCH_DMA_MINALIGN for now.
*/
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/** /**

20
arch/mips/mach-bmips/Kconfig
View file

@ -21,7 +21,7 @@ choice
config SOC_BMIPS_BCM3380 config SOC_BMIPS_BCM3380
bool "BMIPS BCM3380 family" bool "BMIPS BCM3380 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -31,7 +31,7 @@ config SOC_BMIPS_BCM3380
config SOC_BMIPS_BCM6318 config SOC_BMIPS_BCM6318
bool "BMIPS BCM6318 family" bool "BMIPS BCM6318 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -41,7 +41,7 @@ config SOC_BMIPS_BCM6318
config SOC_BMIPS_BCM6328 config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family" bool "BMIPS BCM6328 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -51,7 +51,7 @@ config SOC_BMIPS_BCM6328
config SOC_BMIPS_BCM6338 config SOC_BMIPS_BCM6338
bool "BMIPS BCM6338 family" bool "BMIPS BCM6338 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -61,7 +61,7 @@ config SOC_BMIPS_BCM6338
config SOC_BMIPS_BCM6348 config SOC_BMIPS_BCM6348
bool "BMIPS BCM6348 family" bool "BMIPS BCM6348 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -71,7 +71,7 @@ config SOC_BMIPS_BCM6348
config SOC_BMIPS_BCM6358 config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family" bool "BMIPS BCM6358 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -81,7 +81,7 @@ config SOC_BMIPS_BCM6358
config SOC_BMIPS_BCM6368 config SOC_BMIPS_BCM6368
bool "BMIPS BCM6368 family" bool "BMIPS BCM6368 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -91,7 +91,7 @@ config SOC_BMIPS_BCM6368
config SOC_BMIPS_BCM6362 config SOC_BMIPS_BCM6362
bool "BMIPS BCM6362 family" bool "BMIPS BCM6362 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -101,7 +101,7 @@ config SOC_BMIPS_BCM6362
config SOC_BMIPS_BCM63268 config SOC_BMIPS_BCM63268
bool "BMIPS BCM63268 family" bool "BMIPS BCM63268 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
@ -112,7 +112,7 @@ config SOC_BMIPS_BCM63268
config SOC_BMIPS_BCM6838 config SOC_BMIPS_BCM6838
bool "BMIPS BCM6838 family" bool "BMIPS BCM6838 family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select MIPS_TUNE_4KC select MIPS_TUNE_4KC
select SUPPORTS_BIG_ENDIAN select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1

4
arch/mips/mach-mtmips/Kconfig
View file

@ -39,7 +39,7 @@ choice
config SOC_MT7620 config SOC_MT7620
bool "MT7620" bool "MT7620"
select MIPS_L1_CACHE_SHIFT_5 select SYS_CACHE_SHIFT_5
select SYS_MIPS_CACHE_INIT_RAM_LOAD select SYS_MIPS_CACHE_INIT_RAM_LOAD
select PINCTRL_MT7620 select PINCTRL_MT7620
select MT7620_SERIAL select MT7620_SERIAL
@ -54,7 +54,7 @@ config SOC_MT7620
config SOC_MT7628 config SOC_MT7628
bool "MT7628" bool "MT7628"
select MIPS_L1_CACHE_SHIFT_5 select SYS_CACHE_SHIFT_5
select MIPS_INIT_STACK_IN_SRAM select MIPS_INIT_STACK_IN_SRAM
select MIPS_SRAM_INIT select MIPS_SRAM_INIT
select SYS_MIPS_CACHE_INIT_RAM_LOAD select SYS_MIPS_CACHE_INIT_RAM_LOAD

2
arch/mips/mach-pic32/Kconfig
View file

@ -9,7 +9,7 @@ choice
config SOC_PIC32MZDA config SOC_PIC32MZDA
bool "Microchip PIC32MZ[DA] family" bool "Microchip PIC32MZ[DA] family"
select MIPS_L1_CACHE_SHIFT_4 select SYS_CACHE_SHIFT_4
select ROM_EXCEPTION_VECTORS select ROM_EXCEPTION_VECTORS
select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS32_R2

6
arch/powerpc/cpu/mpc83xx/Kconfig
View file

@ -131,6 +131,7 @@ config MPC83XX_LDP_PIN
config ARCH_MPC830X config ARCH_MPC830X
bool bool
select MPC83XX_SDHC_SUPPORT select MPC83XX_SDHC_SUPPORT
select SYS_CACHE_SHIFT_5
config ARCH_MPC8308 config ARCH_MPC8308
bool bool
@ -154,6 +155,7 @@ config ARCH_MPC831X
select MPC83XX_PCI_SUPPORT select MPC83XX_PCI_SUPPORT
select MPC83XX_TSEC1_SUPPORT select MPC83XX_TSEC1_SUPPORT
select MPC83XX_TSEC2_SUPPORT select MPC83XX_TSEC2_SUPPORT
select SYS_CACHE_SHIFT_5
config ARCH_MPC8313 config ARCH_MPC8313
bool bool
@ -165,9 +167,11 @@ config ARCH_MPC832X
bool bool
select MPC83XX_QUICC_ENGINE select MPC83XX_QUICC_ENGINE
select MPC83XX_PCI_SUPPORT select MPC83XX_PCI_SUPPORT
select SYS_CACHE_SHIFT_5
config ARCH_MPC834X config ARCH_MPC834X
bool bool
select SYS_CACHE_SHIFT_5
config ARCH_MPC8349 config ARCH_MPC8349
bool bool
@ -184,6 +188,7 @@ config ARCH_MPC8360
select MPC83XX_PCI_SUPPORT select MPC83XX_PCI_SUPPORT
select MPC83XX_LDP_PIN select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C select MPC83XX_SECOND_I2C
select SYS_CACHE_SHIFT_5
config ARCH_MPC837X config ARCH_MPC837X
bool bool
@ -196,6 +201,7 @@ config ARCH_MPC837X
select MPC83XX_SATA_SUPPORT select MPC83XX_SATA_SUPPORT
select MPC83XX_LDP_PIN select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C select MPC83XX_SECOND_I2C
select SYS_CACHE_SHIFT_5
select FSL_ELBC select FSL_ELBC
config SYS_IMMR config SYS_IMMR

15
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -48,6 +48,7 @@ config TARGET_MPC8548CDS
bool "Support MPC8548CDS" bool "Support MPC8548CDS"
select ARCH_MPC8548 select ARCH_MPC8548
select FSL_VIA select FSL_VIA
select SYS_CACHE_SHIFT_5
config TARGET_P1010RDB_PA config TARGET_P1010RDB_PA
bool "Support P1010RDB_PA" bool "Support P1010RDB_PA"
@ -322,6 +323,7 @@ config ARCH_MPC8540
config ARCH_MPC8544 config ARCH_MPC8544
bool bool
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_A005125
select FSL_PCIE_RESET select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR2 select SYS_FSL_HAS_DDR2
@ -356,6 +358,7 @@ config ARCH_MPC8560
config ARCH_P1010 config ARCH_P1010
bool bool
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_A005125
@ -401,6 +404,7 @@ config ARCH_P1011
config ARCH_P1020 config ARCH_P1020
bool bool
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_A005125
select SYS_FSL_ERRATUM_ELBC_A001 select SYS_FSL_ERRATUM_ELBC_A001
@ -496,6 +500,7 @@ config ARCH_P1025
config ARCH_P2020 config ARCH_P2020
bool bool
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_5
select SYS_FSL_ERRATUM_A004477 select SYS_FSL_ERRATUM_A004477
select SYS_FSL_ERRATUM_A004508 select SYS_FSL_ERRATUM_A004508
select SYS_FSL_ERRATUM_A005125 select SYS_FSL_ERRATUM_A005125
@ -516,6 +521,7 @@ config ARCH_P2041
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005275 select SYS_FSL_ERRATUM_A005275
@ -540,6 +546,7 @@ config ARCH_P3041
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44 select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849 select SYS_FSL_ERRATUM_A004849
@ -569,6 +576,7 @@ config ARCH_P4080
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44 select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004580 select SYS_FSL_ERRATUM_A004580
@ -607,6 +615,7 @@ config ARCH_P5040
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_44 select SYS_FSL_DDR_VER_44
select SYS_FSL_ERRATUM_A004510 select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004699 select SYS_FSL_ERRATUM_A004699
@ -630,11 +639,13 @@ config ARCH_P5040
config ARCH_QEMU_E500 config ARCH_QEMU_E500
bool bool
select SYS_CACHE_SHIFT_5
config ARCH_T1024 config ARCH_T1024
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109 select SYS_FSL_ERRATUM_A008109
@ -657,6 +668,7 @@ config ARCH_T1040
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008378
@ -679,6 +691,7 @@ config ARCH_T1042
bool bool
select E500MC select E500MC
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_50 select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044 select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008378
@ -702,6 +715,7 @@ config ARCH_T2080
select E500MC select E500MC
select E6500 select E6500
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47 select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379 select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593 select SYS_FSL_ERRATUM_A006593
@ -731,6 +745,7 @@ config ARCH_T4240
select E500MC select E500MC
select E6500 select E6500
select FSL_LAW select FSL_LAW
select SYS_CACHE_SHIFT_6
select SYS_FSL_DDR_VER_47 select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468 select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871 select SYS_FSL_ERRATUM_A005871

2
arch/powerpc/cpu/mpc8xx/Kconfig
View file

@ -19,9 +19,11 @@ choice
config MPC866 config MPC866
bool "MPC866" bool "MPC866"
select SYS_CACHE_SHIFT_4
config MPC885 config MPC885
bool "MPC885" bool "MPC885"
select SYS_CACHE_SHIFT_4
endchoice endchoice

7
arch/powerpc/include/asm/cache.h
View file

@ -25,13 +25,6 @@
*/ */
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
/*
* For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8 #define L1_CACHE_PAGES 8

2
arch/riscv/Kconfig
View file

@ -22,9 +22,11 @@ config TARGET_SIFIVE_UNLEASHED
config TARGET_SIFIVE_UNMATCHED config TARGET_SIFIVE_UNMATCHED
bool "Support SiFive Unmatched Board" bool "Support SiFive Unmatched Board"
select SYS_CACHE_SHIFT_6
config TARGET_SIPEED_MAIX config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board" bool "Support Sipeed Maix Board"
select SYS_CACHE_SHIFT_6
config TARGET_OPENPITON_RISCV64 config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC" bool "Support RISC-V cores on OpenPiton SoC"

1
arch/sandbox/include/asm/cache.h
View file

@ -19,6 +19,5 @@
#else #else
#define ARCH_DMA_MINALIGN 16 #define ARCH_DMA_MINALIGN 16
#endif #endif
#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
#endif /* __SANDBOX_CACHE_H__ */ #endif /* __SANDBOX_CACHE_H__ */

7
arch/x86/include/asm/cache.h
View file

@ -7,13 +7,8 @@
#define __X86_CACHE_H__ #define __X86_CACHE_H__
/* /*
* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment.
* use 64-bytes, a safe default for x86.
*/ */
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
static inline void wbinvd(void) static inline void wbinvd(void)

1
include/configs/M5208EVBE.h
View file

@ -131,7 +131,6 @@
env/embedded.o(.text*); env/embedded.o(.text*);
/* Cache Configuration */ /* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5235EVB.h
View file

@ -147,7 +147,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5249EVB.h
View file

@ -102,7 +102,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5253DEMO.h
View file

@ -153,7 +153,6 @@
#endif #endif
/* Cache Configuration */ /* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5272C3.h
View file

@ -133,7 +133,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5275EVB.h
View file

@ -140,7 +140,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5282EVB.h
View file

@ -140,7 +140,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M53017EVB.h
View file

@ -151,7 +151,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5329EVB.h
View file

@ -158,7 +158,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/M5373EVB.h
View file

@ -160,7 +160,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/amcore.h
View file

@ -71,7 +71,6 @@
* This is a single unified instruction/data cache. * This is a single unified instruction/data cache.
* sdram - single region - no masks * sdram - single region - no masks
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/astro_mcf5373l.h
View file

@ -264,7 +264,6 @@
#endif #endif
/* Cache Configuration */ /* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/cobra5272.h
View file

@ -234,7 +234,6 @@ enter a valid image address in flash */
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

1
include/configs/eb_cpu5282.h
View file

@ -133,7 +133,6 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Cache Configuration * Cache Configuration
*/ */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)

2
include/configs/mx7ulp_evk.h
View file

@ -33,8 +33,6 @@
/* UART */ /* UART */
#define LPUART_BASE LPUART4_RBASE #define LPUART_BASE LPUART4_RBASE
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Miscellaneous configurable options */ /* Miscellaneous configurable options */
#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 512 #define CONFIG_SYS_CBSIZE 512

2
include/configs/rk3188_common.h
View file

@ -6,8 +6,6 @@
#ifndef __CONFIG_RK3188_COMMON_H #ifndef __CONFIG_RK3188_COMMON_H
#define __CONFIG_RK3188_COMMON_H #define __CONFIG_RK3188_COMMON_H
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/hardware.h>
#include "rockchip-common.h" #include "rockchip-common.h"

2
include/configs/rk3368_common.h
View file

@ -8,8 +8,6 @@
#include "rockchip-common.h" #include "rockchip-common.h"
#define CONFIG_SYS_CACHELINE_SIZE 64
#include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/hardware.h>
#include <linux/sizes.h> #include <linux/sizes.h>

2
include/configs/sifive-unmatched.h
View file

@ -36,8 +36,6 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Environment options */ /* Environment options */
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD

1
include/configs/sipeed-maix.h
View file

@ -11,7 +11,6 @@
/* Start just below the second bank so we don't clobber it during reloc */ /* Start just below the second bank so we don't clobber it during reloc */
#define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF #define CONFIG_SYS_INIT_SP_ADDR 0x803FFFFF
#define CONFIG_SYS_MALLOC_LEN SZ_128K #define CONFIG_SYS_MALLOC_LEN SZ_128K
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_SIZE SZ_8M #define CONFIG_SYS_SDRAM_SIZE SZ_8M

1
include/configs/stmark2.h
View file

@ -131,7 +131,6 @@
#endif #endif
/* Cache Configuration */ /* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8) CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \