Blackfin: pull io funcs from linux
Some common code uses more of the io.h funcs than we currently provide, so pull in all of the ones from the linux kernel. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
5eefe7e995
commit
a52ad4f994
5 changed files with 298 additions and 43 deletions
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@ -71,4 +71,7 @@ static inline const char *get_bfin_boot_mode(int bfin_boot)
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# define BFIN_BOOT_SPI_SSEL 1
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#endif
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/* We rarely use interrupts, so favor throughput over latency */
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#define CONFIG_BFIN_INS_LOWOVERHEAD
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#endif
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@ -1,25 +1,9 @@
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/*
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* U-boot - io.h IO routines
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*
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* Copyright (c) 2005-2007 Analog Devices Inc.
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _BLACKFIN_IO_H
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@ -29,6 +13,8 @@
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#include <asm/blackfin.h>
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#define __iomem
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static inline void sync(void)
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{
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SSYNC();
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@ -70,70 +56,154 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
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*
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* readX/writeX() are used to access memory mapped devices. On some
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* architectures the memory mapped IO stuff needs to be accessed
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* differently. On the m68k architecture, we just read/write the
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* differently. On the bfin architecture, we just read/write the
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* memory location directly.
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*/
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#ifndef __ASSEMBLY__
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static inline unsigned char readb(const volatile void *addr)
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static inline unsigned char readb(const volatile void __iomem *addr)
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{
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unsigned int val;
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int tmp;
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__asm__ __volatile__ ("cli %1;\n\t"
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"NOP; NOP; SSYNC;\n\t"
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"%0 = b [%2] (z);\n\t"
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"sti %1;\n\t"
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: "=d"(val), "=d"(tmp): "a"(addr));
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__asm__ __volatile__ (
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"cli %1;"
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"NOP; NOP; SSYNC;"
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"%0 = b [%2] (z);"
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"sti %1;"
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: "=d"(val), "=d"(tmp)
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: "a"(addr)
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);
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return (unsigned char) val;
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}
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static inline unsigned short readw(const volatile void *addr)
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static inline unsigned short readw(const volatile void __iomem *addr)
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{
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unsigned int val;
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int tmp;
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__asm__ __volatile__ ("cli %1;\n\t"
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"NOP; NOP; SSYNC;\n\t"
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"%0 = w [%2] (z);\n\t"
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"sti %1;\n\t"
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: "=d"(val), "=d"(tmp): "a"(addr));
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__asm__ __volatile__ (
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"cli %1;"
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"NOP; NOP; SSYNC;"
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"%0 = w [%2] (z);"
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"sti %1;"
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: "=d"(val), "=d"(tmp)
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: "a"(addr)
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);
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return (unsigned short) val;
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}
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static inline unsigned int readl(const volatile void *addr)
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static inline unsigned int readl(const volatile void __iomem *addr)
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{
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unsigned int val;
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int tmp;
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__asm__ __volatile__ ("cli %1;\n\t"
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"NOP; NOP; SSYNC;\n\t"
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"%0 = [%2];\n\t"
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"sti %1;\n\t"
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: "=d"(val), "=d"(tmp): "a"(addr));
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__asm__ __volatile__ (
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"cli %1;"
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"NOP; NOP; SSYNC;"
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"%0 = [%2];"
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"sti %1;"
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: "=d"(val), "=d"(tmp)
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: "a"(addr)
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);
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return val;
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}
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#endif /* __ASSEMBLY__ */
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#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
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#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
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#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
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#define __raw_readb readb
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#define __raw_readw readw
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#define __raw_readl readl
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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#define memset_io(a, b, c) memset((void *)(a), (b), (c))
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#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
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#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
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/* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */
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#define __io(port) ((void *)(unsigned long)(port))
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#define inb(port) readb(__io(port))
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#define inw(port) readw(__io(port))
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#define inl(port) readl(__io(port))
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#define outb(x, port) writeb(x, __io(port))
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#define outw(x, port) writew(x, __io(port))
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#define outl(x, port) writel(x, __io(port))
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#define inb_p(port) inb(__io(port))
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#define inw_p(port) inw(__io(port))
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#define inl_p(port) inl(__io(port))
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#define outb_p(x, port) outb(x, __io(port))
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#define outw_p(x, port) outw(x, __io(port))
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#define outl_p(x, port) outl(x, __io(port))
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#define ioread8_rep(a, d, c) readsb(a, d, c)
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#define ioread16_rep(a, d, c) readsw(a, d, c)
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#define ioread32_rep(a, d, c) readsl(a, d, c)
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#define iowrite8_rep(a, s, c) writesb(a, s, c)
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#define iowrite16_rep(a, s, c) writesw(a, s, c)
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#define iowrite32_rep(a, s, c) writesl(a, s, c)
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#define ioread8(x) readb(x)
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#define ioread16(x) readw(x)
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#define ioread32(x) readl(x)
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#define iowrite8(val, x) writeb(val, x)
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#define iowrite16(val, x) writew(val, x)
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#define iowrite32(val, x) writel(val, x)
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#define mmiowb() wmb()
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#ifndef __ASSEMBLY__
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extern void outsb(unsigned long port, const void *addr, unsigned long count);
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extern void outsw(unsigned long port, const void *addr, unsigned long count);
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extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
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extern void outsl(unsigned long port, const void *addr, unsigned long count);
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extern void insb(unsigned long port, void *addr, unsigned long count);
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extern void insw(unsigned long port, void *addr, unsigned long count);
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extern void insw_8(unsigned long port, void *addr, unsigned long count);
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extern void insl(unsigned long port, void *addr, unsigned long count);
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extern void insl_16(unsigned long port, void *addr, unsigned long count);
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static inline void readsl(const void __iomem *addr, void *buf, int len)
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{
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insl((unsigned long)addr, buf, len);
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}
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static inline void readsw(const void __iomem *addr, void *buf, int len)
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{
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insw((unsigned long)addr, buf, len);
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}
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static inline void readsb(const void __iomem *addr, void *buf, int len)
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{
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insb((unsigned long)addr, buf, len);
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}
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static inline void writesl(const void __iomem *addr, const void *buf, int len)
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{
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outsl((unsigned long)addr, buf, len);
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}
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static inline void writesw(const void __iomem *addr, const void *buf, int len)
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{
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outsw((unsigned long)addr, buf, len);
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}
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static inline void writesb(const void __iomem *addr, const void *buf, int len)
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{
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outsb((unsigned long)addr, buf, len);
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}
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#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
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/* This hack for CF/IDE needs to be addressed at some point */
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extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
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@ -151,4 +221,7 @@ extern void cf_outb(unsigned char val, volatile unsigned char *addr);
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#endif
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#endif
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#endif /* __KERNEL__ */
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#endif
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@ -31,10 +31,12 @@ CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"'
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LIB = $(obj)lib$(ARCH).a
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SOBJS-y += ins.o
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SOBJS-y += memcmp.o
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SOBJS-y += memcpy.o
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SOBJS-y += memmove.o
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SOBJS-y += memset.o
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SOBJS-y += outs.o
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COBJS-y += board.o
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COBJS-y += boot.o
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117
lib_blackfin/ins.S
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117
lib_blackfin/ins.S
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@ -0,0 +1,117 @@
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/*
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* arch/blackfin/lib/ins.S - ins{bwl} using hardware loops
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*
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* Copyright 2004-2008 Analog Devices Inc.
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* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/blackfin.h>
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.align 2
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#ifdef CONFIG_IPIPE
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# define DO_CLI \
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[--sp] = rets; \
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[--sp] = (P5:0); \
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sp += -12; \
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call ___ipipe_disable_root_irqs_hw; \
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sp += 12; \
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(P5:0) = [sp++];
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# define CLI_INNER_NOP
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#else
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# define DO_CLI cli R3;
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# define CLI_INNER_NOP nop; nop; nop;
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#endif
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#ifdef CONFIG_IPIPE
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# define DO_STI \
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sp += -12; \
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call ___ipipe_enable_root_irqs_hw; \
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sp += 12; \
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2: rets = [sp++];
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#else
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# define DO_STI 2: sti R3;
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#endif
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#ifdef CONFIG_BFIN_INS_LOWOVERHEAD
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# define CLI_OUTER DO_CLI;
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# define STI_OUTER DO_STI;
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# define CLI_INNER 1:
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# if ANOMALY_05000416
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# define STI_INNER nop; 2: nop;
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# else
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# define STI_INNER 2:
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# endif
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#else
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# define CLI_OUTER
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# define STI_OUTER
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# define CLI_INNER 1: DO_CLI; CLI_INNER_NOP;
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# define STI_INNER DO_STI;
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#endif
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/*
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* Reads on the Blackfin are speculative. In Blackfin terms, this means they
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* can be interrupted at any time (even after they have been issued on to the
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* external bus), and re-issued after the interrupt occurs.
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*
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* If a FIFO is sitting on the end of the read, it will see two reads,
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* when the core only sees one. The FIFO receives the read which is cancelled,
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* and not delivered to the core.
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*
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* To solve this, interrupts are turned off before reads occur to I/O space.
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* There are 3 versions of all these functions
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* - turns interrupts off every read (higher overhead, but lower latency)
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* - turns interrupts off every loop (low overhead, but longer latency)
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* - DMA version, which do not suffer from this issue. DMA versions have
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* different name (prefixed by dma_ ), and are located in
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* ../kernel/bfin_dma_5xx.c
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* Using the dma related functions are recommended for transfering large
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* buffers in/out of FIFOs.
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*/
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#define COMMON_INS(func, ops) \
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ENTRY(_ins##func) \
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P0 = R0; /* P0 = port */ \
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CLI_OUTER; /* 3 instructions before first read access */ \
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P1 = R1; /* P1 = address */ \
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P2 = R2; /* P2 = count */ \
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SSYNC; \
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\
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LSETUP(1f, 2f) LC0 = P2; \
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CLI_INNER; \
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ops; \
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STI_INNER; \
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\
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STI_OUTER; \
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RTS; \
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ENDPROC(_ins##func)
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COMMON_INS(l, \
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R0 = [P0]; \
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[P1++] = R0; \
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)
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COMMON_INS(w, \
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R0 = W[P0]; \
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W[P1++] = R0; \
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)
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COMMON_INS(w_8, \
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R0 = W[P0]; \
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B[P1++] = R0; \
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R0 = R0 >> 8; \
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B[P1++] = R0; \
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)
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COMMON_INS(b, \
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R0 = B[P0]; \
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B[P1++] = R0; \
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)
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COMMON_INS(l_16, \
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R0 = [P0]; \
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W[P1++] = R0; \
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R0 = R0 >> 16; \
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W[P1++] = R0; \
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)
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60
lib_blackfin/outs.S
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60
lib_blackfin/outs.S
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@ -0,0 +1,60 @@
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/*
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* Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
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*
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* Copyright 2005-2009 Analog Devices Inc.
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* 2005 BuyWays BV
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* Bas Vermeulen <bas@buyways.nl>
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*
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* Licensed under the GPL-2.
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*/
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#include <asm/linkage.h>
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.align 2
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ENTRY(_outsl)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
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.Llong_loop_s: R0 = [P1++];
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.Llong_loop_e: [P0] = R0;
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RTS;
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ENDPROC(_outsl)
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ENTRY(_outsw)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
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.Lword_loop_s: R0 = W[P1++];
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.Lword_loop_e: W[P0] = R0;
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RTS;
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ENDPROC(_outsw)
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ENTRY(_outsb)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
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.Lbyte_loop_s: R0 = B[P1++];
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.Lbyte_loop_e: B[P0] = R0;
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RTS;
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ENDPROC(_outsb)
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ENTRY(_outsw_8)
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P0 = R0; /* P0 = port */
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P1 = R1; /* P1 = address */
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P2 = R2; /* P2 = count */
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LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
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.Lword8_loop_s: R1 = B[P1++];
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R0 = B[P1++];
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R0 = R0 << 8;
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R0 = R0 + R1;
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.Lword8_loop_e: W[P0] = R0;
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RTS;
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ENDPROC(_outsw_8)
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