Difuse/u-boot
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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-08-17 18:24:13 +02:00
commit 9ed887caec
28 changed files with 603 additions and 1968 deletions
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2
MAINTAINERS
View file

@ -602,7 +602,6 @@ Jason Liu <r64343@freescale.com>
mx53evk i.MX53
mx53loco i.MX53
mx6qarm2 i.MX6Q
mx6qsabrelite i.MX6Q
Enric Balletbo i Serra <eballetbo@iseebcn.com>
@ -1072,6 +1071,7 @@ Pali Rohár <pali.rohar@gmail.com>
nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
Eric Nelson <eric.nelson@boundarydevices.com>
mx6qsabrelite i.MX6Q 1GB
nitrogen6dl i.MX6DL 1GB
nitrogen6dl2g i.MX6DL 2GB
nitrogen6q i.MX6Q/6D 1GB

15
README
View file

@ -2629,6 +2629,21 @@ CBFS (Coreboot Filesystem) support
Note: There is also a sha1sum command, which should perhaps
be deprecated in favour of 'hash sha1'.
- Freescale i.MX specific commands:
CONFIG_CMD_HDMIDETECT
This enables 'hdmidet' command which returns true if an
HDMI monitor is detected. This command is i.MX 6 specific.
CONFIG_CMD_BMODE
This enables the 'bmode' (bootmode) command for forcing
a boot from specific media.
This is useful for forcing the ROM's usb downloader to
activate upon a watchdog reset which is nice when iterating
on U-Boot. Using the reset button or running bmode normal
will set it back to normal. This command currently
supports i.MX53 and i.MX6.
- Signing support:
CONFIG_RSA

8
arch/arm/cpu/armv7/mx6/clock.c
View file

@ -452,6 +452,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
void enable_ipu_clock(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
writel(reg, &mxc_ccm->CCGR3);
}
/***************************************************/
U_BOOT_CMD(

43
arch/arm/cpu/armv7/mx6/soc.c
View file

@ -16,6 +16,8 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/dma.h>
#include <stdbool.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
struct scu_regs {
u32 ctrl;
@ -212,3 +214,44 @@ const struct boot_mode soc_boot_modes[] = {
void s_init(void)
{
}
#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg;
reg = readb(&hdmi->phy_conf0);
reg |= HDMI_PHY_CONF0_PDZ_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
writeb(reg, &hdmi->phy_conf0);
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}
void imx_setup_hdmi(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
/* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
writel(reg, &mxc_ccm->CCGR2);
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
reg = readl(&mxc_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_PODF_DIVIDE_BY_3
<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
}
#endif

3
arch/arm/imx-common/cmd_hdmidet.c
View file

@ -11,8 +11,7 @@
static int do_hdmidet(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg = readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
return (reg&HDMI_PHY_HPD) ? 0 : 1;
return (readb(&hdmi->phy_stat0) & HDMI_DVI_STAT) ? 0 : 1;
}
U_BOOT_CMD(hdmidet, 1, 1, do_hdmidet,

2
arch/arm/include/asm/arch-mx6/clock.h
View file

@ -49,5 +49,5 @@ void enable_ocotp_clk(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_ipu_clock(void);
#endif /* __ASM_ARCH_CLOCK_H */

8
arch/arm/include/asm/arch-mx6/mxc_hdmi.h
View file

@ -9,6 +9,11 @@
#ifndef __MXC_HDMI_H__
#define __MXC_HDMI_H__
#ifdef CONFIG_IMX_HDMI
void imx_enable_hdmi_phy(void);
void imx_setup_hdmi(void);
#endif
/*
* Hdmi controller registers
*/
@ -884,6 +889,9 @@ enum {
HDMI_PHY_HPD = 0x02,
HDMI_PHY_TX_PHY_LOCK = 0x01,
/* Convenience macro RX_SENSE | HPD */
HDMI_DVI_STAT = 0xF2,
/* PHY_I2CM_SLAVE_ADDR field values */
HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,

0
board/freescale/mx6qsabrelite/README → board/boundary/nitrogen6x/README.mx6qsabrelite
View file

46
board/boundary/nitrogen6x/nitrogen6x.c
View file

@ -461,25 +461,12 @@ struct display_info_t {
static int detect_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
}
static void enable_hdmi(struct display_info_t const *dev)
static void do_enable_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg;
printf("%s: setup HDMI monitor\n", __func__);
reg = readb(&hdmi->phy_conf0);
reg |= HDMI_PHY_CONF0_PDZ_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
writeb(reg, &hdmi->phy_conf0);
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
imx_enable_hdmi_phy();
}
static int detect_i2c(struct display_info_t const *dev)
@ -512,7 +499,7 @@ static struct display_info_t const displays[] = {{
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = enable_hdmi,
.enable = do_enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
@ -637,25 +624,15 @@ static void setup_display(void)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
enable_ipu_clock();
imx_setup_hdmi();
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
|MXC_CCM_CCGR3_LDB_DI0_MASK;
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
/* Turn on HDMI PHY clock */
reg = __raw_readl(&mxc_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
writel(reg, &mxc_ccm->CCGR2);
/* clear HDMI PHY reset */
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@ -673,15 +650,8 @@ static void setup_display(void)
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
|(CHSCCDR_PODF_DIVIDE_BY_3
<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

28
board/freescale/mx6qsabrelite/Makefile
View file

@ -1,28 +0,0 @@
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := mx6qsabrelite.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

832
board/freescale/mx6qsabrelite/mx6qsabrelite.c
View file

@ -1,832 +0,0 @@
/*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6q_pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <malloc.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1, SGTL5000 */
struct i2c_pads_info i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
.gpio_mode = MX6_PAD_EIM_D21__GPIO_3_21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
.gpio_mode = MX6_PAD_EIM_D28__GPIO_3_28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
/* I2C2 Camera, MIPI */
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6_PAD_KEY_COL3__GPIO_4_12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6_PAD_KEY_ROW3__GPIO_4_13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3, J15 - RGB connector */
struct i2c_pads_info i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
.gpio_mode = MX6_PAD_GPIO_5__GPIO_1_5 | PC,
.gp = IMX_GPIO_NR(1, 5)
},
.sda = {
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
.gpio_mode = MX6_PAD_GPIO_16__GPIO_7_11 | PC,
.gp = IMX_GPIO_NR(7, 11)
}
};
iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
iomux_v3_cfg_t const enet_pads1[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* pin 35 - 1 (PHY_AD2) on reset */
MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 32 - 1 - (MODE0) all */
MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 31 - 1 - (MODE1) all */
MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 28 - 1 - (MODE2) all */
MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 27 - 1 - (MODE3) all */
MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* pin 42 PHY nRST */
MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
iomux_v3_cfg_t const enet_pads2[] = {
MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
/* Button assignments for J14 */
static iomux_v3_cfg_t const button_pads[] = {
/* Menu */
MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Back */
MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Labelled Search (mapped to Power under Android) */
MX6_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Home */
MX6_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Down */
MX6_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
/* Volume Up */
MX6_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
};
static void setup_iomux_enet(void)
{
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
/* Need delay 10ms according to KSZ9021 spec */
udelay(1000 * 10);
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
}
iomux_v3_cfg_t const usb_pads[] = {
MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_hcd_init(int port)
{
imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
/* Reset USB hub */
gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(7, 12), 1);
return 0;
}
#endif
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
gpio_direction_input(IMX_GPIO_NR(7, 0));
ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
} else {
gpio_direction_input(IMX_GPIO_NR(2, 6));
ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
usdhc_cfg[0].max_bus_width = 4;
usdhc_cfg[1].max_bus_width = 4;
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
}
return status;
}
#endif
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
MX6_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
};
void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
ARRAY_SIZE(ecspi1_pads));
}
#endif
int board_phy_config(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
#ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
return 0;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
return 0;
}
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret) {
printf("FEC MXC: %s:failed\n", __func__);
free(phydev);
free(bus);
}
#endif
return 0;
}
static void setup_buttons(void)
{
imx_iomux_v3_setup_multiple_pads(button_pads,
ARRAY_SIZE(button_pads));
}
#ifdef CONFIG_CMD_SATA
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
int ret = enable_sata_clock();
if (ret)
return ret;
clrsetbits_le32(&iomuxc_regs->gpr[13],
IOMUXC_GPR13_SATA_MASK,
IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
|IOMUXC_GPR13_SATA_PHY_7_SATA2M
|IOMUXC_GPR13_SATA_SPEED_3G
|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
|IOMUXC_GPR13_SATA_PHY_1_SLOW);
return 0;
}
#endif
#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight on RGB connector: J15 */
MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
/* Backlight on LVDS connector: J6 */
MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
};
static iomux_v3_cfg_t const rgb_pads[] = {
MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2,
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3,
MX6_PAD_DI0_PIN4__GPIO_4_20,
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
};
struct display_info_t {
int bus;
int addr;
int pixfmt;
int (*detect)(struct display_info_t const *dev);
void (*enable)(struct display_info_t const *dev);
struct fb_videomode mode;
};
static int detect_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
}
static void enable_hdmi(struct display_info_t const *dev)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg;
printf("%s: setup HDMI monitor\n", __func__);
reg = readb(&hdmi->phy_conf0);
reg |= HDMI_PHY_CONF0_PDZ_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
writeb(reg, &hdmi->phy_conf0);
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}
static int detect_i2c(struct display_info_t const *dev)
{
return ((0 == i2c_set_bus_num(dev->bus))
&&
(0 == i2c_probe(dev->addr)));
}
static void enable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
writel(reg, &iomux->gpr[2]);
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
}
static void enable_rgb(struct display_info_t const *dev)
{
imx_iomux_v3_setup_multiple_pads(
rgb_pads,
ARRAY_SIZE(rgb_pads));
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
static struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
.enable = enable_hdmi,
.mode = {
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x4,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = detect_i2c,
.enable = enable_lvds,
.mode = {
.name = "Hannstar-XGA",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x38,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = detect_i2c,
.enable = enable_lvds,
.mode = {
.name = "wsvga-lvds",
.refresh = 60,
.xres = 1024,
.yres = 600,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = 2,
.addr = 0x48,
.pixfmt = IPU_PIX_FMT_RGB666,
.detect = detect_i2c,
.enable = enable_rgb,
.mode = {
.name = "wvga-rgb",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
} } };
int board_video_skip(void)
{
int i;
int ret;
char const *panel = getenv("panel");
if (!panel) {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
struct display_info_t const *dev = displays+i;
if (dev->detect(dev)) {
panel = dev->mode.name;
printf("auto-detected panel %s\n", panel);
break;
}
}
if (!panel) {
panel = displays[0].mode.name;
printf("No panel detected: default to %s\n", panel);
}
} else {
for (i = 0; i < ARRAY_SIZE(displays); i++) {
if (!strcmp(panel, displays[i].mode.name))
break;
}
}
if (i < ARRAY_SIZE(displays)) {
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
displays[i].enable(displays+i);
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
displays[i].mode.yres);
} else
printf("LCD %s cannot be configured: %d\n",
displays[i].mode.name, ret);
} else {
printf("unsupported panel %s\n", panel);
ret = -EINVAL;
}
return (0 != ret);
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
/* Turn on LDB0,IPU,IPU DI0 clocks */
reg = __raw_readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
|MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
/* Turn on HDMI PHY clock */
reg = __raw_readl(&mxc_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
|MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
writel(reg, &mxc_ccm->CCGR2);
/* clear HDMI PHY reset */
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
/* set LDB0, LDB1 clk select to 011/011 */
reg = readl(&mxc_ccm->cs2cdr);
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
|(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cs2cdr);
reg = readl(&mxc_ccm->cscmr2);
reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
writel(reg, &mxc_ccm->cscmr2);
reg = readl(&mxc_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
|(CHSCCDR_PODF_DIVIDE_BY_3
<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
|(CHSCCDR_IPU_PRE_CLK_540M_PFD
<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
|IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
|IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
|IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
|IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
|IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
|IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
|IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
|IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
writel(reg, &iomux->gpr[2]);
reg = readl(&iomux->gpr[3]);
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
/* backlights off until needed */
imx_iomux_v3_setup_multiple_pads(backlight_pads,
ARRAY_SIZE(backlight_pads));
gpio_direction_input(LVDS_BACKLIGHT_GP);
gpio_direction_input(RGB_BACKLIGHT_GP);
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_buttons();
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
return 0;
}
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif
return 0;
}
int checkboard(void)
{
puts("Board: MX6Q-Sabre Lite\n");
return 0;
}
struct button_key {
char const *name;
unsigned gpnum;
char ident;
};
static struct button_key const buttons[] = {
{"back", IMX_GPIO_NR(2, 2), 'B'},
{"home", IMX_GPIO_NR(2, 4), 'H'},
{"menu", IMX_GPIO_NR(2, 1), 'M'},
{"search", IMX_GPIO_NR(2, 3), 'S'},
{"volup", IMX_GPIO_NR(7, 13), 'V'},
{"voldown", IMX_GPIO_NR(4, 5), 'v'},
};
/*
* generate a null-terminated string containing the buttons pressed
* returns number of keys pressed
*/
static int read_keys(char *buf)
{
int i, numpressed = 0;
for (i = 0; i < ARRAY_SIZE(buttons); i++) {
if (!gpio_get_value(buttons[i].gpnum))
buf[numpressed++] = buttons[i].ident;
}
buf[numpressed] = '\0';
return numpressed;
}
static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char envvalue[ARRAY_SIZE(buttons)+1];
int numpressed = read_keys(envvalue);
setenv("keybd", envvalue);
return numpressed == 0;
}
U_BOOT_CMD(
kbd, 1, 1, do_kbd,
"Tests for keypresses, sets 'keybd' environment variable",
"Returns 0 (true) to shell if key is pressed."
);
#ifdef CONFIG_PREBOOT
static char const kbd_magic_prefix[] = "key_magic";
static char const kbd_command_prefix[] = "key_cmd";
static void preboot_keys(void)
{
int numpressed;
char keypress[ARRAY_SIZE(buttons)+1];
numpressed = read_keys(keypress);
if (numpressed) {
char *kbd_magic_keys = getenv("magic_keys");
char *suffix;
/*
* loop over all magic keys
*/
for (suffix = kbd_magic_keys; *suffix; ++suffix) {
char *keys;
char magic[sizeof(kbd_magic_prefix) + 1];
sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
keys = getenv(magic);
if (keys) {
if (!strcmp(keys, keypress))
break;
}
}
if (*suffix) {
char cmd_name[sizeof(kbd_command_prefix) + 1];
char *cmd;
sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv(cmd_name);
if (cmd) {
setenv("preboot", cmd);
return;
}
}
}
}
#endif
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
{"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
{NULL, 0},
};
#endif
int misc_init_r(void)
{
#ifdef CONFIG_PREBOOT
preboot_keys();
#endif
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
return 0;
}

64
board/freescale/mx6sabresd/mx6sabresd.c
View file

@ -18,7 +18,12 @@
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
@ -228,6 +233,60 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
#if defined(CONFIG_VIDEO_IPUV3)
static struct fb_videomode const hdmi = {
.name = "HDMI",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
};
int board_video_skip(void)
{
int ret;
ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
if (ret)
printf("HDMI cannot be configured: %d\n", ret);
imx_enable_hdmi_phy();
return ret;
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
int reg;
enable_ipu_clock();
imx_setup_hdmi();
reg = readl(&mxc_ccm->chsccdr);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
}
#endif /* CONFIG_VIDEO_IPUV3 */
/*
* Do not overwrite the console
* Use always serial for U-Boot console
*/
int overwrite_console(void)
{
return 1;
}
int board_eth_init(bd_t *bis)
{
int ret;
@ -244,6 +303,9 @@ int board_eth_init(bd_t *bis)
int board_early_init_f(void)
{
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
return 0;
}

44
board/wandboard/wandboard.c
View file

@ -208,23 +208,6 @@ int board_phy_config(struct phy_device *phydev)
}
#if defined(CONFIG_VIDEO_IPUV3)
static void enable_hdmi(void)
{
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
u8 reg;
reg = readb(&hdmi->phy_conf0);
reg |= HDMI_PHY_CONF0_PDZ_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
writeb(reg, &hdmi->phy_conf0);
udelay(3000);
reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
writeb(reg, &hdmi->phy_conf0);
writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
}
static struct fb_videomode const hdmi = {
.name = "HDMI",
.refresh = 60,
@ -250,7 +233,7 @@ int board_video_skip(void)
if (ret)
printf("HDMI cannot be configured: %d\n", ret);
enable_hdmi();
imx_enable_hdmi_phy();
return ret;
}
@ -258,33 +241,14 @@ int board_video_skip(void)
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
int reg;
/* Turn on IPU clock */
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
writel(reg, &mxc_ccm->CCGR3);
/* Turn on HDMI PHY clock */
reg = readl(&mxc_ccm->CCGR2);
reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
writel(reg, &mxc_ccm->CCGR2);
/* clear HDMI PHY reset */
writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
enable_ipu_clock();
imx_setup_hdmi();
reg = readl(&mxc_ccm->chsccdr);
reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
| (CHSCCDR_PODF_DIVIDE_BY_3
<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
| (CHSCCDR_IPU_PRE_CLK_540M_PFD
<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->chsccdr);
}
#endif /* CONFIG_VIDEO_IPUV3 */

2
boards.cfg
View file

@ -274,7 +274,7 @@ vision2 arm armv7 vision2 ttcontr
cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q
mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
mx6qsabrelite arm armv7 nitrogen6x boundary mx6 nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE
mx6dlsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL
mx6qsabresd arm armv7 mx6sabresd freescale mx6 mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
mx6slevk arm armv7 mx6slevk freescale mx6 mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL

4
drivers/gpio/mxc_gpio.c
View file

@ -127,10 +127,10 @@ int gpio_direction_input(unsigned gpio)
int gpio_direction_output(unsigned gpio, int value)
{
int ret = mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
int ret = gpio_set_value(gpio, value);
if (ret < 0)
return ret;
return gpio_set_value(gpio, value);
return mxc_gpio_direction(gpio, MXC_GPIO_DIRECTION_OUT);
}

5
drivers/video/mxc_ipuv3_fb.c
View file

@ -399,8 +399,9 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
fbi->fix.smem_len = fbi->var.yres_virtual *
fbi->fix.line_length;
}
fbi->screen_base = (char *)malloc(fbi->fix.smem_len);
fbi->fix.smem_len = roundup(fbi->fix.smem_len, ARCH_DMA_MINALIGN);
fbi->screen_base = (char *)memalign(ARCH_DMA_MINALIGN,
fbi->fix.smem_len);
fbi->fix.smem_start = (unsigned long)fbi->screen_base;
if (fbi->screen_base == 0) {
puts("Unable to allocate framebuffer memory\n");

120
include/configs/apx4devkit.h
View file

@ -11,34 +11,16 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#ifndef __CONFIGS_APX4DEVKIT_H__
#define __CONFIGS_APX4DEVKIT_H__
/* SoC configurations */
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define MACH_TYPE_APX4DEVKIT 3712
#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT
#include <asm/arch/regs-base.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
@ -58,78 +40,26 @@
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_USB
/* Memory configurations */
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/* Environment */
#define CONFIG_ENV_OVERWRITE
/* U-Boot general configurations */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-Boot version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc. */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_OF_LIBFDT
#define CONFIG_ENV_IS_IN_NAND
/* Serial Driver */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* DMA */
#define CONFIG_APBH_DMA
/* MMC Driver */
#ifdef CONFIG_ENV_IS_IN_MMC
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
/* NAND Driver */
#ifdef CONFIG_ENV_IS_IN_NAND
/* Environment is in NAND */
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
@ -139,12 +69,8 @@
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#endif
/* UBI and NAND partitioning */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
@ -159,43 +85,30 @@
#define MTDPARTS_DEFAULT ""
#endif
/* Ethernet on SOC (FEC) */
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_NET_MULTI
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0
#define IMX_FEC_BASE MXS_ENET0_BASE
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
/* I2C */
#ifdef CONFIG_CMD_I2C
#define CONFIG_I2C_MXS
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#endif
/* RTC */
#if defined(CONFIG_CMD_DATE)
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
#endif
/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTCOMMAND "run bootcmd_nand"
@ -225,4 +138,7 @@
"ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
""
#endif /* __CONFIG_H */
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_APX4DEVKIT_H__ */

192
include/configs/m28evk.h
View file

@ -4,43 +4,17 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __M28EVK_CONFIG_H__
#define __M28EVK_CONFIG_H__
#ifndef __CONFIGS_M28EVK_H__
#define __CONFIGS_M28EVK_H__
/*
* SoC configurations
*/
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
/*
* Define M28EVK machine type by hand until it lands in mach-types
*/
#define MACH_TYPE_M28EVK 3613
#define CONFIG_MACH_TYPE MACH_TYPE_M28EVK
#include <asm/arch/regs-base.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/*
* SPL
*/
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
@ -69,86 +43,18 @@
#define CONFIG_REGEX /* Enable regular expression support */
/*
* Memory configurations
*/
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
/*
* Serial Driver
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
/*
* APBH DMA
*/
#define CONFIG_APBH_DMA
/*
* NAND
*/
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_ENV_IS_IN_NAND
/* Environment is in NAND */
#define CONFIG_ENV_IS_IN_NAND
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_RANGE (512 * 1024)
@ -177,40 +83,22 @@
#define CONFIG_ENV_IS_NOWHERE
#endif
/*
* Ethernet on SOC (FEC)
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_ETHPRIME "FEC0"
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#endif
/*
* I2C
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_I2C_MXS
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#endif
/*
* EEPROM
*/
#ifdef CONFIG_CMD_EEPROM
/* EEPROM */
#ifdef CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#endif
/*
* RTC
*/
#ifdef CONFIG_CMD_DATE
/* RTC */
#ifdef CONFIG_CMD_DATE
/* Use the internal RTC in the MXS chip */
#define CONFIG_RTC_INTERNAL
#ifdef CONFIG_RTC_INTERNAL
#ifdef CONFIG_RTC_INTERNAL
#define CONFIG_RTC_MXS
#else
#define CONFIG_RTC_M41T62
@ -219,32 +107,22 @@
#endif
#endif
/*
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_EHCI_MXS_PORT1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
/*
* SPI
*/
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
#define CONFIG_SPI_HALF_DUPLEX
/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_DEFAULT_SPI_BUS 2
#define CONFIG_DEFAULT_SPI_CS 0
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI FLASH */
#ifdef CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SF_DEFAULT_BUS 2
@ -257,18 +135,12 @@
#define CONFIG_ENV_SPI_MAX_HZ 40000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#endif
#endif
/*
* LCD
*/
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
/* LCD */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
@ -277,22 +149,15 @@
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
#endif
/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
#define CONFIG_BOOTCOMMAND "run bootcmd_net"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
/*
* Extra Environments
*/
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_nand_full_filename=u-boot.nand\0" \
"update_nand_firmware_filename=u-boot.sb\0" \
@ -333,4 +198,7 @@
"fi ; " \
"fi\0"
#endif /* __M28EVK_CONFIG_H__ */
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_M28EVK_H__ */

142
include/configs/mx23_olinuxino.h
View file

@ -3,40 +3,15 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX23_OLINUXINO_CONFIG_H__
#define __MX23_OLINUXINO_CONFIG_H__
#ifndef __CONFIGS_MX23_OLINUXINO_H__
#define __CONFIGS_MX23_OLINUXINO_H__
#include <asm/arch/iomux-mx23.h>
/*
* SoC configurations
*/
/* System configurations */
#define CONFIG_MX23 /* i.MX23 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_MACH_TYPE 4105
#include <asm/arch/regs-base.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/*
* SPL
*/
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
@ -51,92 +26,36 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_USB
/*
* Memory configurations
*/
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
/* Environment */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
/*
* Serial Driver
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*
* Status LED
*/
/* Status LED */
#define CONFIG_STATUS_LED
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_BOOT 0
#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1
#define STATUS_LED_BOOT 0
#define STATUS_LED_BIT MX23_PAD_SSP1_DETECT__GPIO_2_1
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
/*
* APBH DMA
*/
#define CONFIG_APBH_DMA
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
@ -146,31 +65,13 @@
#define CONFIG_USB_ETHER_SMSC95XX
#endif
/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
* Extra Environments
*/
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_sd_firmware_filename=u-boot.sd\0" \
"update_sd_firmware=" /* Update the SD firmware partition */ \
@ -252,4 +153,7 @@
"fi; " \
"else run netboot; fi"
#endif /* __MX23_OLINUXINO_CONFIG_H__ */
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_MX23_OLINUXINO_H__ */

115
include/configs/mx23evk.h
View file

@ -6,33 +6,15 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX23EVK_CONFIG_H__
#define __MX23EVK_CONFIG_H__
#ifndef __CONFIGS_MX23EVK_H__
#define __CONFIGS_MX23EVK_H__
/* SoC configurations */
/* System configurations */
#define CONFIG_MX23 /* i.MX23 SoC */
#include <asm/arch/regs-base.h>
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
@ -49,86 +31,33 @@
#define CONFIG_CMD_BOOTZ
#define CONFIG_VIDEO
/* Memory configurations */
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/* Environment */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_MMC
/* U-Boot general configurations */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* Serial Driver */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/* DMA */
#define CONFIG_APBH_DMA
/* MMC Driver */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
/* Framebuffer support */
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
@ -138,21 +67,10 @@
#endif
/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
/* Environment */
#define CONFIG_ENV_IS_IN_MMC
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/* Extra Environments */
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -211,4 +129,7 @@
"fi; " \
"else exit; fi"
#endif /* __MX23EVK_CONFIG_H__ */
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_MX23EVK_H__ */

177
include/configs/mx28evk.h
View file

@ -8,33 +8,16 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MX28EVK_CONFIG_H__
#define __MX28EVK_CONFIG_H__
#ifndef __CONFIGS_MX28EVK_H__
#define __CONFIGS_MX28EVK_H__
/* SoC configurations */
/* System configurations */
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
#include <asm/arch/regs-base.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > "
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
@ -49,6 +32,7 @@
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
@ -58,81 +42,24 @@
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_VIDEO
/* Memory configurations */
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
#define CONFIG_ENV_OVERWRITE
/* U-Boot general configurations */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "MX28EVK U-Boot > "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
/* Serial Driver */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/* DMA */
#define CONFIG_APBH_DMA
/* MMC Driver */
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
#define CONFIG_CMD_SAVEENV
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
/* NAND Driver */
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_ENV_OVERWRITE
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/* Environment is in NAND */
#ifdef CONFIG_ENV_IS_IN_NAND
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_RANGE (512 * 1024)
@ -141,6 +68,21 @@
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#endif
/* Environemnt is in SPI flash */
#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
#define CONFIG_ENV_OFFSET 0x40000 /* 256K */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_BUS 2
#define CONFIG_ENV_SPI_MAX_HZ 24000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#endif
/* UBI and NAND partitioning */
#ifdef CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
@ -160,13 +102,10 @@
"-(filesystem)"
#endif
/* Ethernet on SOC (FEC) */
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_NET_MULTI
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_NET_MULTI
#define CONFIG_MX28_FEC_MAC_IN_OCOTP
#endif
@ -177,65 +116,35 @@
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
#endif
/* I2C */
#ifdef CONFIG_CMD_I2C
#define CONFIG_I2C_MXS
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#endif
/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
#define CONFIG_SPI_HALF_DUPLEX
#define CONFIG_DEFAULT_SPI_BUS 2
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
/* SPI Flash */
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_BUS 2
#define CONFIG_SF_DEFAULT_CS 0
/* this may vary and depends on the installed chip */
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#endif
/* (redundant) environemnt in SPI flash */
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
#define CONFIG_ENV_OFFSET 0x40000 /* 256K */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_BUS 2
#define CONFIG_ENV_SPI_MAX_HZ 24000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
#endif
#endif
#endif
/* Framebuffer support */
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
@ -245,15 +154,12 @@
#endif
/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
/* Extra Environments */
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_nand_full_filename=u-boot.nand\0" \
"update_nand_firmware_filename=u-boot.sb\0" \
@ -364,4 +270,7 @@
"fi; " \
"else run netboot; fi"
#endif /* __MX28EVK_CONFIG_H__ */
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_MX28EVK_H__ */

284
include/configs/mx6qsabrelite.h
View file

@ -1,284 +0,0 @@
/*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
*
* Configuration settings for the Freescale i.MX6Q Sabre Lite board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX6
#define CONFIG_MX6Q
#include "mx6_common.h"
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MACH_TYPE 3769
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
#endif
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 19)<<8))
#define CONFIG_SF_DEFAULT_SPEED 25000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#endif
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_SATA
/*
* SATA Configs
*/
#ifdef CONFIG_CMD_SATA
#define CONFIG_DWC_AHSATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
#define CONFIG_LBA48
#define CONFIG_LIBATA
#endif
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_CMD_FAT
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_IPUV3_CLK 260000000
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#define CONFIG_BOOTDELAY 1
#define CONFIG_PREBOOT ""
#define CONFIG_LOADADDR 0x12000000
#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttymxc1\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=imx6q-sabrelite.dtb\0" \
"fdt_addr=0x11000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootm; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootm; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${uimage}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootm; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootm; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "MX6QSABRELITE U-Boot > "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_ENV_OFFSET (768 * 1024)
#define CONFIG_ENV_SECT_SIZE (8 * 1024)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
#endif /* __CONFIG_H */

3
include/configs/mx6sabre_common.h
View file

@ -12,6 +12,7 @@
#define CONFIG_MX6
#include "mx6_common.h"
#include <asm/sizes.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@ -24,7 +25,7 @@
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT

19
include/configs/mx6sabresd.h
View file

@ -9,6 +9,9 @@
#ifndef __MX6QSABRESD_CONFIG_H
#define __MX6QSABRESD_CONFIG_H
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
@ -23,4 +26,20 @@
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
#endif
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#endif /* __MX6QSABRESD_CONFIG_H */

191
include/configs/mxs.h Normal file
View file

@ -0,0 +1,191 @@
/*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIGS_MXS_H__
#define __CONFIGS_MXS_H__
/*
* Includes
*/
#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
#error Select one of CONFIG_MX23 or CONFIG_MX28 !
#endif
#include <asm/arch/regs-base.h>
#if defined(CONFIG_MX23)
#include <asm/arch/iomux-mx23.h>
#elif defined(CONFIG_MX28)
#include <asm/arch/iomux-mx28.h>
#endif
/*
* CPU specifics
*/
/* Ticks per second */
#define CONFIG_SYS_HZ 1000
/* MXS uses FDT */
#define CONFIG_OF_LIBFDT
/* Startup hooks */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#if defined(CONFIG_MX23)
#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024)
#elif defined(CONFIG_MX28)
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#endif
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/* U-Boot general configuration */
#define CONFIG_SYS_LONGHELP
#ifndef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "=> "
#endif
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* Booting Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/*
* Drivers
*/
/* APBH DMA */
#define CONFIG_APBH_DMA
/* GPIO */
#define CONFIG_MXS_GPIO
/* DUART Serial Driver */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
/* Default baudrate can be overriden by board! */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#endif
/* FEC Ethernet on SoC */
#ifdef CONFIG_FEC_MXC
#define CONFIG_MII
#ifndef CONFIG_ETHPRIME
#define CONFIG_ETHPRIME "FEC0"
#endif
#ifndef CONFIG_FEC_XCV_TYPE
#define CONFIG_FEC_XCV_TYPE RMII
#endif
#endif
/* I2C */
#ifdef CONFIG_CMD_I2C
#define CONFIG_I2C_MXS
#define CONFIG_HARD_I2C
#ifndef CONFIG_SYS_I2C_SPEED
#define CONFIG_SYS_I2C_SPEED 400000
#endif
#endif
/* LCD */
#ifdef CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MXS
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#endif
/* MMC */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
/* NAND */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MXS
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x60000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#endif
/* SPI */
#ifdef CONFIG_CMD_SPI
#define CONFIG_HARD_SPI
#define CONFIG_MXS_SPI
#define CONFIG_SPI_HALF_DUPLEX
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_IS_TDI
#endif
#endif /* __CONFIGS_MXS_H__ */

81
include/configs/nitrogen6x.h
View file

@ -141,6 +141,7 @@
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_CMD_HDMIDETECT
#define CONFIG_CONSOLE_MUX
#define CONFIG_IMX_HDMI
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
@ -173,6 +174,80 @@
#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
#if defined(CONFIG_SABRELITE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttymxc1\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=imx6q-sabrelite.dtb\0" \
"fdt_addr=0x11000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootm; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootm; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${uimage}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootm; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootm; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc1\0" \
"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
@ -206,6 +281,7 @@
"done ; " \
"done\0" \
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
@ -245,8 +321,11 @@
#define CONFIG_ENV_SIZE (8 * 1024)
/* #define CONFIG_ENV_IS_IN_MMC */
#if defined(CONFIG_SABRELITE)
#define CONFIG_ENV_IS_IN_MMC
#else
#define CONFIG_ENV_IS_IN_SPI_FLASH
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)

139
include/configs/sc_sps_1.h
View file

@ -6,48 +6,16 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __SC_SPS_1_H__
#define __SC_SPS_1_H__
#ifndef __CONFIGS_SC_SPS_1_H__
#define __CONFIGS_SC_SPS_1_H__
/*
* SoC configurations
*/
/* System configuration */
#define CONFIG_MX28 /* i.MX28 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
/*
* Define SC_SPS_1 machine type by hand until it lands in mach-types
*/
#define MACH_TYPE_SC_SPS_1 4172
#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1
#include <asm/arch/regs-base.h>
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_OF_LIBFDT
/*
* SPL
*/
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
@ -65,119 +33,47 @@
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_USB
/*
* Memory configurations
*/
/* Memory configuration */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */
#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Serial Driver
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_APBH_DMA
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
/* Environment */
#define CONFIG_ENV_SIZE (16 * 1024)
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_IS_IN_MMC
/* Environment is in MMC */
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
/*
* Ethernet on SOC (FEC)
*/
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif
/*
* USB
*/
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MXS
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyAMA0,115200"
#define CONFIG_BOOTCOMMAND "bootm "
#define CONFIG_BOOTCOMMAND "bootm"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/*
* Extra Environments
*/
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_sd_firmware_filename=u-boot.sd\0" \
"update_sd_firmware=" /* Update the SD firmware partition */ \
@ -189,4 +85,7 @@
"fi ; " \
"fi\0"
#endif /* __SC_SPS_1_H__ */
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_SC_SPS_1_H__ */

2
include/configs/wandboard.h
View file

@ -97,6 +97,7 @@
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IPUV3_CLK 260000000
#define CONFIG_IMX_HDMI
#if defined(CONFIG_MX6DL)
#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
@ -110,6 +111,7 @@
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \