Update ARM Integrator boards:
Correct addessing errors in platform files. Split off common core module data from Integrator header files to include/armcoremodule.h. Patch by Peter Pearse, 04 Oct 2005
This commit is contained in:
Wolfgang Denk
parent
1820d4c73b
commit
9b880bd4d8
19 changed files with 223 additions and 134 deletions
12
CHANGELOG
12
CHANGELOG
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@ -2,16 +2,24 @@
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Changes for U-Boot 1.1.4:
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======================================================================
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* Cleanup
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* Update ARM Integrator boards:
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Correct addessing errors in platform files.
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Split off common core module data from Integrator header files to
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include/armcoremodule.h.
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Patch by Peter Pearse, 04 Oct 2005
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* Make sure only supported compiler options are used
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Import "cc-option" shell function from kernel and
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use it to get the correct ARM GCC options for individual CPUs
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Patch by Peter Pearse, 30 Jun 2005
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* Fix 440GR to print correct cpu revision
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Patch by Stefan Roese, 4 Oct 2005
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Patch by Stefan Roese, 04 Oct 2005
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* Change board message on AMCC Yosemite & Yellowstone to common style
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Patch by Stefan Roese, 3 Oct 2005
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Patch by Stefan Roese, 03 Oct 2005
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* Fix compiler warning
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@ -649,3 +649,8 @@ ulong get_tbclk (void)
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{
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return CFG_HZ_CLOCK/div_clock;
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}
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/* The Integrator/AP timer1 is clocked at 24MHz
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* can be divided by 16 or 256
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* and is a 16-bit counter
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*/
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@ -32,7 +32,7 @@ reset_cpu:
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mov r0, #CM_BASE
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ldr r1,[r0,#OS_CTRL]
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orr r1,r1,#CMMASK_RESET
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str r1,[r0]
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str r1,[r0,#OS_CTRL]
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reset_failed:
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b reset_failed
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@ -98,8 +98,8 @@ platformsetup:
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beq init_reg_OK
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/* lock for change */
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mov r3, #CMVAL_LOCK
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and r3,r3,#CMMASK_LOCK
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mov r3, #CMVAL_LOCK1
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add r3,r3,#CMVAL_LOCK2
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str r3, [r0, #OS_LOCK]
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/* set desired value */
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orr r1,r1,r2
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@ -32,7 +32,7 @@ reset_cpu:
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mov r0, #CM_BASE
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ldr r1,[r0,#OS_CTRL]
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orr r1,r1,#CMMASK_RESET
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str r1,[r0]
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str r1,[r0,#OS_CTRL]
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reset_failed:
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b reset_failed
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@ -65,6 +65,7 @@ platformsetup:
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#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
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!defined (CONFIG_CM940T)
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/* CMxx6 code */
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#ifdef CONFIG_CM_MULTIPLE_SSRAM
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/* set simple mapping */
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@ -98,8 +99,8 @@ platformsetup:
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beq init_reg_OK
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/* lock for change */
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mov r3, #CMVAL_LOCK
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and r3,r3,#CMMASK_LOCK
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mov r3, #CMVAL_LOCK1
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and r3, r3, #CMVAL_LOCK2
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str r3, [r0, #OS_LOCK]
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/* set desired value */
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orr r1,r1,r2
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@ -91,7 +91,7 @@ HOSTSTRIP = strip
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# only supported compiler options are used
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#
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cc-option = $(shell if $(CC) $(CFLAGS) $(1) -S -o /dev/null -xc /dev/null \
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> /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
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> /dev/null 2>&1; then echo "$(1)"; else echo "$(2)"; fi ;)
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#
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# Include the make variables (CC, etc...)
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@ -32,4 +32,3 @@ PLATFORM_CPPFLAGS += -march=armv5
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# =========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -33,4 +33,3 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
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# =========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -32,4 +32,3 @@ PLATFORM_CPPFLAGS += -march=armv4
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# =========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -32,4 +32,3 @@ PLATFORM_CPPFLAGS += -march=armv4
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# =========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -32,4 +32,3 @@ PLATFORM_CPPFLAGS += -march=armv4
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# =========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -35,4 +35,3 @@ PLATFORM_CPPFLAGS += -mbig-endian -march=armv4 -mtune=strongarm1100
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# =========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -32,4 +32,3 @@ PLATFORM_CPPFLAGS += -march=armv4
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# ========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -34,4 +34,3 @@ PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
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# ========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -33,4 +33,3 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
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# ========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -33,4 +33,3 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
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# ========================================================================
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PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
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PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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@ -18,6 +18,7 @@ Each CM consists of a ARM processor core and associated hardware e.g
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SDRAM
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RAM controllers
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clock generators etc.
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CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
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Boot Methods :
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------------
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92
include/armcoremodule.h
Normal file
92
include/armcoremodule.h
Normal file
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@ -0,0 +1,92 @@
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/*
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* (C) Copyright 2005
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* ARM Ltd.
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* Peter Pearse, <Peter.Pearse@arm.com>
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* Configuration for ARM Core Modules.
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* No standalonw port yet available
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* - this file is included by both integratorap.h & integratorcp.h
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ARMCOREMODULE_H
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#define __ARMCOREMODULE_H
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#define CM_BASE 0x10000000
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/* CM registers common to all CMs */
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/* Note that observed values after reboot into the ARM Boot Monitor
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have been used as defaults, rather than the POR values */
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#define OS_CTRL 0x0000000C
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#define CMMASK_REMAP 0x00000005 /* set remap & led */
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#define CMMASK_RESET 0x00000008
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#define OS_LOCK 0x00000014
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#define CMVAL_LOCK1 0x0000A000 /* locking value */
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#define CMVAL_LOCK2 0x0000005F /* locking value */
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#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
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#define OS_SDRAM 0x00000020
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#define OS_INIT 0x00000024
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#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
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#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
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#define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */
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#define CMMASK_LE 0xFFFFFFF7 /* little endian */
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#define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */
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/* - observed reset value of */
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/* CM926EJ-S */
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/* CM1136-EJ-S */
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#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
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#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */
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/* - PLL test clock bypassed */
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/* - bus clock ratio 2 */
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/* - little endian */
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/* - vectors at zero */
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#endif /* CM1022xx */
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/* Determine CM characteristics */
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#undef CONFIG_CM_MULTIPLE_SSRAM
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#undef CONFIG_CM_SPD_DETECT
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#undef CONFIG_CM_REMAP
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#undef CONFIG_CM_INIT
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#undef CONFIG_CM_TCRAM
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#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
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#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
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#endif
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/* Excalibur core module has reduced functionality */
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#ifndef CONFIG_CM922T_XA10
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#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
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#define OS_SPD 0x00000100 /* Address of SPD data */
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#define CONFIG_CM_REMAP /* CM supports remapping */
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#define CONFIG_CM_INIT /* CM has initialization reg */
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#endif /* NOT EXCALIBUR */
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#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
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defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
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defined(CONFIG_CM1136JF_S)
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#define CONFIG_CM_TCRAM /* CM has TCRAM */
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#endif
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#ifdef CONFIG_CM_SPD_DETECT
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#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
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#endif
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#endif /* __ARMCOREMODULE_H */
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@ -275,42 +275,6 @@
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* to define the necessary CONFIG_ s for the CM involved
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* see e.g. integratorcp_CM926EJ-S_config
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*/
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#include "armcoremodule.h"
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#define CM_BASE 0x10000000
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/* CM registers common to all integrator/CP CMs */
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#define OS_CTRL 0x0000000C
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#define CMMASK_REMAP 0x00000005 /* Set remap & led */
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#define CMMASK_RESET 0x00000008
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#define OS_LOCK 0x00000014
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#define CMVAL_LOCK 0x0000A000 /* Locking value */
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#define CMMASK_LOCK 0x0000005F /* Locking value */
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#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */
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#define OS_SDRAM 0x00000020
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#define OS_INIT 0x00000024
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#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
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#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
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#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
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#ifdef CONFIG_CM_SPD_DETECT
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#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */
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#endif
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#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
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#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
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* - PLL test clock bypassed
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* - bus clock ratio 2
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* - little endian
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* - vectors at zero
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*/
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#endif /* CM1022xx */
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#define CMMASK_LE 0x00000008 /* little endian */
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#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
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* - divisor/ratio b00000001
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* bx
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* - HCLKDIV b000
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* bxx
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* - PLL BYPASS b00
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*/
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#endif /* __CONFIG_H */
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@ -66,7 +66,7 @@
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#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
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#define CONFIG_CONS_INDEX 0
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#define CONFIG_BAUDRATE 38400
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_SERIAL0 0x16000000
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#define CFG_SERIAL1 0x17000000
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@ -84,30 +84,31 @@
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#if 0
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
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#define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=<IP address>:/<exported rootfs> mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
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#define CONFIG_BOOTCOMMAND "bootp ; bootm"
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#endif
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/* The kernel command line & boot command below are for a platform flashed with afu.axf
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Image 666 Block 0 End Block 0 address 0x24000000 exec 0x24000000- name u-boot
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Image 667 Block 1 End Block 13 address 0x24040000 exec 0x24040000- name u-linux
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Image 668 Block 14 End Block 33 address 0x24380000 exec 0x24380000- name rootfs
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SIB at Block62 End Block62 address 0x24f80000
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/* Flash loaded
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- U-Boot
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- u-linux
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- system.cramfs
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*/
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0, \
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0xfc800000,0xfc800010,eth0 video=clcdfb:0"
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#define CONFIG_BOOTCOMMAND "cp 0x24040000 0x7fc0 0x80000; bootm"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0 console=ttyAMA0"
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#define CONFIG_BOOTCOMMAND "cp 0x24080000 0x7fc0 0x100000; bootm"
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size*/
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/* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size*/
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
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@ -126,90 +127,117 @@
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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* Top varies according to amount fitted
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* Reserve top 4 blocks of flash
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* - ARM Boot Monitor
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* - Unused
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* - SIB block
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* - U-Boot environment
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*
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* Base is always 0x24000000
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*/
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#define CFG_FLASH_BASE 0x24000000
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#define CFG_FLASH_BASE 0x24000000
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#define CFG_MAX_FLASH_SECT 64
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
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#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
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#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
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#define CFG_MONITOR_BASE 0x24F40000
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_MONITOR_LEN 0x00100000
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#define CFG_ENV_IS_IN_FLASH (1)
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/*
|
||||
* Move up the U-Boot & monitor area if more flash is fitted.
|
||||
* If this U-Boot is to be run on Integrators with varying flash sizes,
|
||||
* drivers/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
|
||||
* register and dynamically assign CFG_ENV_ADDR & CFG_MONITOR_BASE
|
||||
* - CFG_MONITOR_BASE is set to indicate that the environment is not
|
||||
* embedded in the boot monitor(s) area
|
||||
*/
|
||||
#if ( PHYS_FLASH_SIZE == 0x04000000 )
|
||||
|
||||
#define CFG_ENV_ADDR 0x27F00000
|
||||
#define CFG_MONITOR_BASE 0x27F40000
|
||||
|
||||
#elif (PHYS_FLASH_SIZE == 0x02000000 )
|
||||
|
||||
#define CFG_ENV_ADDR 0x25F00000
|
||||
#define CFG_MONITOR_BASE 0x25F40000
|
||||
|
||||
#else
|
||||
|
||||
#define CFG_ENV_ADDR 0x24F00000
|
||||
#define CFG_MONITOR_BASE 0x27F40000
|
||||
|
||||
#endif
|
||||
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
|
||||
#define CFG_ENV_SIZE 8192 /* 8KB */
|
||||
/*-----------------------------------------------------------------------
|
||||
* CP control registers
|
||||
*/
|
||||
#define CPCR_BASE 0xCB000000 /* CP Registers*/
|
||||
#define OS_FLASHPROG 0x00000004 /* Flash register*/
|
||||
#define CPMASK_EXTRABANK 0x8
|
||||
#define CPMASK_FLASHSIZE 0x4
|
||||
#define CPMASK_FLWREN 0x2
|
||||
#define CPMASK_FLVPPEN 0x1
|
||||
|
||||
/*
|
||||
* The ARM boot monitor initializes the board.
|
||||
* However, the default U-Boot code also performs the initialization.
|
||||
* If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
|
||||
* - see documentation supplied with board for details of how to choose the
|
||||
* image to run at reset/power up
|
||||
* e.g. whether the ARM Boot Monitor runs before U-Boot
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* The ARM boot monitor does not relocate U-Boot.
|
||||
* However, the default U-Boot code performs the relocation check,
|
||||
* and may relocate the code if the memory map is changed.
|
||||
* If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
|
||||
|
||||
#define SKIP_CONFIG_RELOCATE_UBOOT
|
||||
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* There are various dependencies on the core module (CM) fitted
|
||||
* Users should refer to their CM user guide
|
||||
* - when porting adjust u-boot/Makefile accordingly
|
||||
* to define the necessary CONFIG_ s for the CM involved
|
||||
* see e.g. integratorcp_CM926EJ-S_config
|
||||
* to define the necessary CONFIG_ s for the CM involved
|
||||
* see e.g. cp_926ejs_config
|
||||
*/
|
||||
|
||||
#define CM_BASE 0x10000000
|
||||
#include "armcoremodule.h"
|
||||
|
||||
/* CM registers common to all integrator/CP CMs */
|
||||
#define OS_CTRL 0x0000000C
|
||||
#define CMMASK_REMAP 0x00000005 /* set remap & led */
|
||||
#define CMMASK_RESET 0x00000008
|
||||
#define OS_LOCK 0x00000014
|
||||
#define CMVAL_LOCK 0x0000A000 /* locking value */
|
||||
#define CMMASK_LOCK 0x0000005F /* locking value */
|
||||
#define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */
|
||||
#define OS_SDRAM 0x00000020
|
||||
#define OS_INIT 0x00000024
|
||||
#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */
|
||||
#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */
|
||||
#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */
|
||||
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
|
||||
#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual
|
||||
* - PLL test clock bypassed
|
||||
* - bus clock ratio 2
|
||||
* - little endian
|
||||
* - vectors at zero
|
||||
*/
|
||||
#endif /* CM1022xx */
|
||||
|
||||
#define CMMASK_LE 0x00000008 /* little endian */
|
||||
#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6
|
||||
* - divisor/ratio b00000001
|
||||
* bx
|
||||
* - HCLKDIV b000
|
||||
* bxx
|
||||
* - PLL BYPASS b00
|
||||
*/
|
||||
|
||||
/* Determine CM characteristics */
|
||||
|
||||
#undef CONFIG_CM_MULTIPLE_SSRAM
|
||||
#undef CONFIG_CM_SPD_DETECT
|
||||
#undef CONFIG_CM_REMAP
|
||||
/*
|
||||
* If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
|
||||
* the core module has a CM_INIT register
|
||||
* then the U-Boot initialisation code will
|
||||
* e.g. ARM Boot Monitor or pre-loader is repeated once
|
||||
* (to re-initialise any existing CM_INIT settings to safe values).
|
||||
*
|
||||
* This is usually not the desired behaviour since the platform
|
||||
* will either reboot into the ARM monitor (or pre-loader)
|
||||
* or continuously cycle thru it without U-Boot running,
|
||||
* depending upon the setting of Integrator/CP switch S2-4.
|
||||
*
|
||||
* However it may be needed if Integrator/CP switch S2-1
|
||||
* is set OFF to boot direct into U-Boot.
|
||||
* In that case comment out the line below.
|
||||
#undef CONFIG_CM_INIT
|
||||
#undef CONFIG_CM_TCRAM
|
||||
|
||||
#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
|
||||
#define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_CM922t_XA10
|
||||
#define CONFIG_CM_SPD_DETECT /* CM supports SPD query */
|
||||
#define OS_SPD 0x00000100 /* Address of SPD data */
|
||||
#define CONFIG_CM_REMAP /* CM supports remapping */
|
||||
#define CONFIG_CM_INIT /* CM has initialization reg */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \
|
||||
defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \
|
||||
defined(CONFIG_CM1136JF_S)
|
||||
#define CONFIG_CM_TCRAM /* CM has TCRAM */
|
||||
#endif
|
||||
*/
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue