ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
Fix a bug in the auto calibration routine. This driver now runs more reliable with the tested modules. It's also tested with 167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
430f1b0f9a
commit
94f54703c3
1 changed files with 81 additions and 48 deletions
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@ -107,10 +107,11 @@
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#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
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/* Defines for the Read Cycle Delay test */
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#define NUMMEMTESTS 8
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#define NUMMEMWORDS 8
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#define NUMMEMTESTS 8
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#define NUMMEMWORDS 8
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#define NUMLOOPS 256 /* memory test loops */
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#define CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
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#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
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@ -584,10 +585,16 @@ static void get_spd_info(unsigned long *dimm_populated,
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#ifdef CONFIG_ADD_RAM_INFO
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void board_add_ram_info(int use_default)
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{
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u32 val;
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if (is_ecc_enabled())
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puts(" (ECC enabled)");
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puts(" (ECC enabled, ");
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else
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puts(" (ECC not enabled)");
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puts(" (ECC not enabled, ");
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mfsdram(SDRAM_MMODE, val);
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val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
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printf("CL=%d)", val);
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}
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#endif
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@ -731,6 +738,7 @@ static void check_frequency(unsigned long *dimm_populated,
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else
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cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
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((tcyc_reg & 0x0F)*10);
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debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
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if (cycle_time > (calc_cycle_time + 10)) {
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/*
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@ -1486,6 +1494,9 @@ static void program_mode(unsigned long *dimm_populated,
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hang();
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}
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} else { /* DDR2 */
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debug("cas_3_0_available=%d\n", cas_3_0_available);
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debug("cas_4_0_available=%d\n", cas_4_0_available);
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debug("cas_5_0_available=%d\n", cas_5_0_available);
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if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
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mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
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*selected_cas = DDR_CAS_3;
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@ -2137,6 +2148,18 @@ static unsigned long is_ecc_enabled(void)
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return ecc;
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}
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static void blank_string(int size)
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{
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int i;
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for (i=0; i<size; i++)
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putc('\b');
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for (i=0; i<size; i++)
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putc(' ');
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for (i=0; i<size; i++)
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putc('\b');
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}
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#ifdef CONFIG_DDR_ECC
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/*-----------------------------------------------------------------------------+
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* program_ecc.
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@ -2233,8 +2256,10 @@ static void program_ecc_addr(unsigned long start_address,
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unsigned long end_address;
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unsigned long address_increment;
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unsigned long mcopt1;
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char str[] = "ECC generation...";
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int i;
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char str[] = "ECC generation -";
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char slash[] = "\\|/-\\|/-";
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int loop = 0;
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int loopi = 0;
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current_address = start_address;
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mfsdram(SDRAM_MCOPT1, mcopt1);
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@ -2257,14 +2282,20 @@ static void program_ecc_addr(unsigned long start_address,
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while (current_address < end_address) {
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*((unsigned long *)current_address) = 0x00000000;
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current_address += address_increment;
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if ((loop++ % (2 << 20)) == 0) {
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putc('\b');
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putc(slash[loopi++ % 8]);
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}
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}
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} else {
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/* ECC bit set method for cached memory */
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dcbz_area(start_address, num_bytes);
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dflush();
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}
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for (i=0; i<strlen(str); i++)
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putc('\b');
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blank_string(strlen(str));
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sync();
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eieio();
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@ -2347,7 +2378,7 @@ static void program_DQS_calibration(unsigned long *dimm_populated,
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#endif
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}
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static u32 short_mem_test(void)
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static int short_mem_test(void)
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{
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u32 *membase;
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u32 bxcr_num;
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@ -2371,42 +2402,41 @@ static u32 short_mem_test(void)
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0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
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{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
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0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
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int l;
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for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
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mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
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/* Banks enabled */
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if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
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/* Bank is enabled */
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membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
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/*------------------------------------------------------------------
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* Run the short memory test.
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*-----------------------------------------------------------------*/
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membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
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for (i = 0; i < NUMMEMTESTS; i++) {
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for (j = 0; j < NUMMEMWORDS; j++) {
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membase[j] = test[i][j];
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ppcDcbf((u32)&(membase[j]));
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}
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sync();
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for (j = 0; j < NUMMEMWORDS; j++) {
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if (membase[j] != test[i][j]) {
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for (l=0; l<NUMLOOPS; l++) {
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for (j = 0; j < NUMMEMWORDS; j++) {
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if (membase[j] != test[i][j]) {
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ppcDcbf((u32)&(membase[j]));
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return 0;
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}
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ppcDcbf((u32)&(membase[j]));
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break;
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}
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ppcDcbf((u32)&(membase[j]));
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sync();
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}
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sync();
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if (j < NUMMEMWORDS)
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break;
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}
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if (i < NUMMEMTESTS)
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break;
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} /* if bank enabled */
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} /* for bxcf_num */
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return bxcr_num;
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return 1;
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}
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#ifndef HARD_CODED_DQS
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@ -2415,12 +2445,10 @@ static u32 short_mem_test(void)
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*-----------------------------------------------------------------------------*/
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static void DQS_calibration_process(void)
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{
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unsigned long ecc_temp;
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unsigned long rfdc_reg;
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unsigned long rffd;
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unsigned long rqdc_reg;
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unsigned long rqfd;
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unsigned long bxcr_num;
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unsigned long val;
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long rqfd_average;
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long rffd_average;
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@ -2440,6 +2468,10 @@ static void DQS_calibration_process(void)
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long max_end;
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unsigned char fail_found;
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unsigned char pass_found;
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u32 rqfd_start;
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char str[] = "Auto calibration -";
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char slash[] = "\\|/-\\|/-";
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int loopi = 0;
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/*------------------------------------------------------------------
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* Test to determine the best read clock delay tuning bits.
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@ -2464,11 +2496,16 @@ static void DQS_calibration_process(void)
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* we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
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* from experimentation it is safe to say you will always have a failure.
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*-----------------------------------------------------------------*/
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mfsdram(SDRAM_MCOPT1, ecc_temp);
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ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
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mfsdram(SDRAM_MCOPT1, val);
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mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
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SDRAM_MCOPT1_MCHK_NON);
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/* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
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rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
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puts(str);
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calibration_loop:
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mfsdram(SDRAM_RQDC, rqdc_reg);
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mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
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SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
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max_start = 0;
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min_end = 0;
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@ -2492,9 +2529,6 @@ static void DQS_calibration_process(void)
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fail_found = FALSE;
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pass_found = FALSE;
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/* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
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/* rqdc_reg = mfsdram(SDRAM_RQDC) & ~(SDRAM_RQDC_RQFD_MASK); */
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/*
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* get the delay line calibration register value
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*/
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@ -2510,13 +2544,10 @@ static void DQS_calibration_process(void)
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*-----------------------------------------------------------------*/
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mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
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/* do the small memory test */
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bxcr_num = short_mem_test();
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/*------------------------------------------------------------------
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* See if the rffd value passed.
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*-----------------------------------------------------------------*/
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if (bxcr_num == MAXBXCF) {
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if (short_mem_test()) {
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if (fail_found == TRUE) {
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pass_found = TRUE;
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if (current_pass_length == 0)
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@ -2578,13 +2609,10 @@ static void DQS_calibration_process(void)
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*-----------------------------------------------------------------*/
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mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
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/* do the small memory test */
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bxcr_num = short_mem_test();
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/*------------------------------------------------------------------
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* See if the rffd value passed.
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*-----------------------------------------------------------------*/
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if (bxcr_num == MAXBXCF) {
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if (short_mem_test()) {
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if (fail_found == TRUE) {
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pass_found = TRUE;
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if (current_pass_length == 0)
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@ -2612,17 +2640,28 @@ static void DQS_calibration_process(void)
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}
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}
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rqfd_average = ((max_start + max_end) >> 1);
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/*------------------------------------------------------------------
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* Make sure we found the valid read passing window. Halt if not
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*-----------------------------------------------------------------*/
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if (window_found == FALSE) {
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printf("ERROR: Cannot determine a common read delay for the "
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if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
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putc('\b');
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putc(slash[loopi++ % 8]);
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/* try again from with a different RQFD start value */
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rqfd_start++;
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goto calibration_loop;
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}
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printf("\nERROR: Cannot determine a common read delay for the "
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"DIMM(s) installed.\n");
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debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
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hang();
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}
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rqfd_average = ((max_start + max_end) >> 1);
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blank_string(strlen(str));
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if (rqfd_average < 0)
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rqfd_average = 0;
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@ -2630,12 +2669,6 @@ static void DQS_calibration_process(void)
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if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
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rqfd_average = SDRAM_RQDC_RQFD_MAX;
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/*------------------------------------------------------------------
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* Restore the ECC variable to what it originally was
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*-----------------------------------------------------------------*/
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mfsdram(SDRAM_MCOPT1, val);
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mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | ecc_temp);
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mtsdram(SDRAM_RQDC,
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(rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
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SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
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