sh: ms7750se: Remove the board
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
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@ -21,10 +21,6 @@ choice
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prompt "Target select"
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optional
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config TARGET_MS7750SE
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bool "SolutionEngine 7750"
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select CPU_SH4
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config TARGET_AP_SH4A_4A
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bool "ALPHAPROJECT AP-SH4A-4A"
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select CPU_SH4A
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@ -76,7 +72,6 @@ config SYS_CPU
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source "arch/sh/lib/Kconfig"
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source "board/alphaproject/ap_sh4a_4a/Kconfig"
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source "board/ms7750se/Kconfig"
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source "board/renesas/MigoR/Kconfig"
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source "board/renesas/ap325rxa/Kconfig"
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source "board/renesas/r0p7734/Kconfig"
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@ -1,9 +0,0 @@
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if TARGET_MS7750SE
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config SYS_BOARD
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default "ms7750se"
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config SYS_CONFIG_NAME
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default "ms7750se"
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endif
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@ -1,7 +0,0 @@
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MS7750SE BOARD
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M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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S: Maintained
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F: board/ms7750se/
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F: include/configs/ms7750se.h
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F: configs/ms7750se_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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obj-y := ms7750se.o
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extra-y += lowlevel_init.o
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@ -1,141 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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modified from SH-IPL+g
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Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
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Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
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Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#ifdef CONFIG_CPU_SH7751
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#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
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#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
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#ifdef CONFIG_MARUBUN_PCCARD
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#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#else /* CONFIG_MARUBUN_PCCARD */
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#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#endif /* CONFIG_MARUBUN_PCCARD */
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#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
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#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
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#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
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#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
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#else /* CONFIG_CPU_SH7751 */
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#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
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#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
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#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:15 A0B:7 */
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#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
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#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
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#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
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#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
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#endif /* CONFIG_CPU_SH7751 */
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 CCR_A, CCR_D_DISABLE
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init_bsc:
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write16 FRQCR_A, FRQCR_D
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write32 BCR1_A, BCR1_D
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write16 BCR2_A, BCR2_D
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write32 WCR1_A, WCR1_D
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write32 WCR2_A, WCR2_D
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write32 WCR3_A, WCR3_D
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write32 MCR_A, MCR_D1
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/* Set SDRAM mode */
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write8 SDMR3_A, SDMR3_D
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! Do you need PCMCIA setting?
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! If so, please add the lines here...
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write16 RTCNT_A, RTCNT_D
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write16 RTCOR_A, RTCOR_D
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write16 RTCSR_A, RTCSR_D
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write16 RFCR_A, RFCR_D
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/* Wait DRAM refresh 30 times */
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mov #30, r3
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1:
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mov.w @r1, r0
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extu.w r0, r2
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cmp/hi r3, r2
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bf 1b
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write32 MCR_A, MCR_D2
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/* Set SDRAM mode */
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write8 SDMR3_A, SDMR3_D
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rts
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nop
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.align 2
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CCR_A: .long CCR
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CCR_D_DISABLE: .long 0x0808
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FRQCR_A: .long FRQCR
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FRQCR_D:
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#ifdef CONFIG_CPU_TYPE_R
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.word 0x0e1a /* 12:3:3 */
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#else /* CONFIG_CPU_TYPE_R */
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#ifdef CONFIG_GOOD_SESH4
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.word 0x00e13 /* 6:2:1 */
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#else
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.word 0x00e23 /* 6:1:1 */
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#endif
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.align 2
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#endif /* CONFIG_CPU_TYPE_R */
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BCR1_A: .long BCR1
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BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
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BCR2_A: .long BCR2
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BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
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WCR1_A: .long WCR1
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WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
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WCR2_A: .long WCR2
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WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
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WCR3_A: .long WCR3
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WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
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RTCSR_A: .long RTCSR
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RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
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.align 2
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RTCNT_A: .long RTCNT
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RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
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.align 2
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RTCOR_A: .long RTCOR
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RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
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.align 2
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SDMR3_A: .long SDMR3_ADDRESS
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SDMR3_D: .long 0x00
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MCR_A: .long MCR
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MCR_D1: .long MCR_D1_VALUE
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MCR_D2: .long MCR_D2_VALUE
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RFCR_A: .long RFCR
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RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
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.align 2
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@ -1,24 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <common.h>
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#include <asm/processor.h>
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int checkboard(void)
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{
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puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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@ -1,32 +0,0 @@
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CONFIG_SH=y
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CONFIG_SYS_TEXT_BASE=0x8FFC0000
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CONFIG_TARGET_MS7750SE=y
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CONFIG_BOOTDELAY=-1
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttySC0,38400"
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# CONFIG_CMDLINE_EDITING is not set
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# CONFIG_AUTO_COMPLETE is not set
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_RUN is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_MEMORY is not set
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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# CONFIG_CMD_ECHO is not set
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SOURCE is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_MISC is not set
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CONFIG_ENV_IS_IN_FLASH=y
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# CONFIG_NET is not set
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_BAUDRATE=38400
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -1,65 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Hitachi Solution Engine 7750
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#ifndef __MS7750SE_H
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#define __MS7750SE_H
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#define CONFIG_CPU_SH7750 1
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/* #define CONFIG_CPU_SH7751 1 */
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/* #define CONFIG_CPU_TYPE_R 1 */
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#define __LITTLE_ENDIAN__ 1
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#define CONFIG_DISPLAY_BOARDINFO
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/*
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* Command line configuration.
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*/
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#define CONFIG_CONS_SCIF1 1
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#define CONFIG_ENV_OVERWRITE 1
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
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/* NOR Flash */
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/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
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#define CONFIG_SYS_FLASH_BASE (0xA0000000)
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#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
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* Flash memory banks
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*/
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#define CONFIG_SYS_MAX_FLASH_SECT 142
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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#define CONFIG_SYS_RX_ETH_BUFFER (8)
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#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#endif /* __MS7750SE_H */
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