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u-boot-imx-next-20230331 for next

Browse source 
---------------------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819
 
 i.MX patches queued for next:
 
 - Conversions to DM_SERIAL
 - Fixes for Toradex boards
 - Gateworks Boards
 - i.MX8ULP
 - EQoS support / fixes, changes in boards
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Merge tag 'u-boot-imx-next-20230331' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next

u-boot-imx-next-20230331 for next
---------------------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/15819

i.MX patches queued for next:

- Conversions to DM_SERIAL
- Fixes for Toradex boards
- Gateworks Boards
- i.MX8ULP
- EQoS support / fixes, changes in boards
This commit is contained in:
Tom Rini 2023-03-31 12:50:34 -04:00
commit 942ac73afc
101 changed files with 4568 additions and 2205 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/dts/Makefile
View file

@ -996,6 +996,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-dhcom-pdk3.dtb \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-msc-sm2s.dtb \

2
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
View file

@ -3,8 +3,6 @@
* Copyright 2019 Toradex AG
*/
#include "imx8qxp-u-boot.dtsi"
&{/imx8qx-pm} {
bootph-some-ram;

7
arch/arm/dts/imx6dl-pico-u-boot.dtsi Normal file
View file

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/ {
aliases {
mmc0 = &usdhc3;
};
};

14
arch/arm/dts/imx8mp-dhcom-pdk2.dts
View file

@ -104,20 +104,10 @@
};
};
/*
* PDK2 carrier board uses SoM with KSZ9131 populated and connected to
* SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node.
*/
/delete-node/ &ethphy0f;
/*
* PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC
* ethernet RGMII interface. The SoM is not populated with second FEC PHY.
*/
/delete-node/ &ethphy1f;
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <&ethphypdk>;
phy-mode = "rgmii";
mdio {
ethphypdk: ethernet-phy@7 { /* KSZ 9021 */

6
arch/arm/dts/imx8mp-dhcom-pdk3-u-boot.dtsi Normal file
View file

@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
*/
#include "imx8mp-dhcom-u-boot.dtsi"

321
arch/arm/dts/imx8mp-dhcom-pdk3.dts Normal file
View file

@ -0,0 +1,321 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023 Marek Vasut <marex@denx.de>
*
* DHCOM iMX8MP variant:
* DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
* DHCOM PCB number: 660-100 or newer
* PDK3 PCB number: 669-100 or newer
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-dhcom-som.dtsi"
/ {
model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)";
compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
"fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
clk_ext_audio_codec: clock-codec {
#clock-cells = <0>;
clock-frequency = <24000000>;
compatible = "fixed-clock";
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_c_0_hs_ep: endpoint {
remote-endpoint = <&dwc3_0_hs_ep>;
};
};
port@1 {
reg = <1>;
usb_c_0_ss_ep: endpoint {
remote-endpoint = <&ptn5150_in_ep>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
button-0 {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */
label = "TA1-GPIO-A";
linux,code = <KEY_A>;
pinctrl-0 = <&pinctrl_dhcom_a>;
pinctrl-names = "default";
wakeup-source;
};
button-1 {
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */
label = "TA2-GPIO-B";
linux,code = <KEY_B>;
pinctrl-0 = <&pinctrl_dhcom_b>;
pinctrl-names = "default";
wakeup-source;
};
button-2 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */
label = "TA3-GPIO-C";
linux,code = <KEY_C>;
pinctrl-0 = <&pinctrl_dhcom_c>;
pinctrl-names = "default";
wakeup-source;
};
button-3 {
gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */
label = "TA4-GPIO-E";
linux,code = <KEY_E>;
pinctrl-0 = <&pinctrl_dhcom_e>;
pinctrl-names = "default";
wakeup-source;
};
};
led {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <0>;
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */
pinctrl-0 = <&pinctrl_dhcom_d>;
pinctrl-names = "default";
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */
pinctrl-0 = <&pinctrl_dhcom_f>;
pinctrl-names = "default";
};
led-2 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */
pinctrl-0 = <&pinctrl_dhcom_g>;
pinctrl-names = "default";
};
led-3 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";
};
};
reg_avdd: regulator-avdd { /* AUDIO_VDD */
compatible = "regulator-fixed";
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "AUDIO_VDD";
};
};
&i2c5 {
i2cmux@70 {
compatible = "nxp,pca9540";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2cmuxed0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
interrupt-parent = <&gpio4>;
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
ptn5150_in_ep: endpoint {
remote-endpoint = <&usb_c_0_ss_ep>;
};
};
port@1 {
reg = <1>;
ptn5150_out_ep: endpoint {
remote-endpoint = <&dwc3_0_ss_ep>;
};
};
};
};
power-sensor@40 {
compatible = "ti,ina238";
reg = <0x40>;
shunt-resistor = <20000>; /* 0.02 R */
ti,shunt-gain = <1>; /* Drop cca. 40mV */
};
eeprom_board: eeprom@54 {
compatible = "atmel,24c04";
pagesize = <16>;
reg = <0x54>;
};
pcieclk: clk@6b {
compatible = "skyworks,si52144";
reg = <0x6b>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
i2cmuxed1: i2c@1 { /* HDMI DDC I2C */
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
&ethphy0g {
reg = <7>;
};
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rgmii>;
phy-handle = <&ethphypdk>;
phy-mode = "rgmii-id";
mdio {
ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */
compatible = "ethernet-phy-id0022.1642",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reg = <7>;
reset-assert-us = <1000>;
/* RESET_N signal rise time ~100ms */
reset-deassert-us = <120000>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
&flexcan1 {
status = "okay";
};
&pcie_phy {
clocks = <&pcieclk 1>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
};
&pcie {
fsl,max-link-speed = <3>;
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb_dwc3_0 {
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_hs_ep: endpoint@0 {
reg = <0>;
remote-endpoint = <&usb_c_0_hs_ep>;
};
dwc3_0_ss_ep: endpoint@1 {
reg = <1>;
remote-endpoint = <&ptn5150_out_ep>;
};
};
};
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
};
&usb_dwc3_1 {
/* This port has USB5734 Hub connected to it, PWR/OC pins are unused */
/delete-property/ pinctrl-names;
/delete-property/ pinctrl-0;
};
&iomuxc {
/*
* GPIO_A,B,C,E are connected to buttons.
* GPIO_D,F,G,I are connected to LEDs.
* GPIO_H is connected to USB Hub RESET_N.
* GPIO_M is connected to CLKOUT2.
*/
pinctrl-0 = <&pinctrl_hog_base
&pinctrl_dhcom_h &pinctrl_dhcom_j &pinctrl_dhcom_k
&pinctrl_dhcom_l
&pinctrl_dhcom_int>;
pinctrl_ptn5150: ptn5150grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000
>;
};
};

46
arch/arm/dts/imx8mp-dhcom-som.dtsi
View file

@ -83,7 +83,7 @@
&eqos { /* First ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-0 = <&pinctrl_eqos_rgmii>;
phy-handle = <&ethphy0g>;
phy-mode = "rgmii-id";
status = "okay";
@ -94,14 +94,14 @@
#size-cells = <0>;
/* Up to one of these two PHYs may be populated. */
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reg = <1>;
reg = <0>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
@ -129,9 +129,9 @@
&fec { /* Second ethernet */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-0 = <&pinctrl_fec_rmii>;
phy-handle = <&ethphy1f>;
phy-mode = "rgmii";
phy-mode = "rmii";
fsl,magic-packet;
status = "okay";
@ -664,7 +664,7 @@
>;
};
pinctrl_eqos: dhcom-eqos-grp { /* RGMII */
pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
@ -683,6 +683,22 @@
>;
};
pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
/* Clock */
MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f
>;
};
pinctrl_enet_vio: dhcom-enet-vio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22
@ -707,7 +723,7 @@
>;
};
pinctrl_fec: dhcom-fec-grp {
pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
@ -728,6 +744,22 @@
>;
};
pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
/* Clock */
MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f
>;
};
pinctrl_flexcan1: dhcom-flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154

6
arch/arm/dts/imx8mp-dhcom-u-boot.dtsi
View file

@ -33,12 +33,6 @@
bootph-pre-ram;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
bootph-pre-ram;
};

6
arch/arm/dts/imx8mp-evk-u-boot.dtsi
View file

@ -131,12 +131,6 @@
bootph-pre-ram;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&ethphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;

6
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
View file

@ -130,12 +130,6 @@
bootph-pre-ram;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&ethphy0 {
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <15000>;

6
arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi
View file

@ -20,12 +20,6 @@
};
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&ethphy0 {
reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;

6
arch/arm/dts/imx8mp-verdin-wifi-dev-u-boot.dtsi
View file

@ -39,12 +39,6 @@
bootph-pre-ram;
};
&eqos {
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
bootph-pre-ram;
};

1
arch/arm/include/asm/arch-imx8m/clock.h
View file

@ -276,5 +276,4 @@ int set_clk_qspi(void);
void enable_ocotp_clk(unsigned char enable);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type);
void hab_caam_clock_enable(unsigned char enable);

10
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -89,7 +89,15 @@
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
#define IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN BIT(22)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16)
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL BIT(13)
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_ARMV8_PSCI /* Final jump location */

3
arch/arm/include/asm/arch-imx8ulp/imx-regs.h
View file

@ -10,6 +10,7 @@
#include <linux/bitops.h>
#include <linux/sizes.h>
#define SRAM0_BASE 0x22010000
#define PBRIDGE0_BASE 0x28000000
#define CMC0_RBASE 0x28025000
@ -62,6 +63,8 @@
#define FEC_QUIRK_ENET_MAC
#define IMG_CONTAINER_BASE (0x22010000UL)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>

1
arch/arm/include/asm/arch-imx8ulp/rdc.h
View file

@ -23,5 +23,6 @@ int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_en
void xrdc_init_mda(void);
void xrdc_init_mrc(void);
void xrdc_init_pdac_msc(void);
#endif

2
arch/arm/include/asm/arch-imx8ulp/sys_proto.h
View file

@ -14,5 +14,7 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
bool is_m33_handshake_necessary(void);
int m33_image_handshake(ulong timeout_ms);
int imx8ulp_dm_post_init(void);
#endif

2
arch/arm/include/asm/arch-imx9/imx-regs.h
View file

@ -40,6 +40,8 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define IMG_CONTAINER_BASE (0x80000000UL)
#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)

3
arch/arm/include/asm/global_data.h
View file

@ -97,6 +97,9 @@ struct arch_global_data {
u32 uid[4];
#endif
#ifdef CONFIG_ARCH_IMX8ULP
bool m33_handshake_done;
#endif
};
#include <asm-generic/global_data.h>

114
arch/arm/include/asm/mach-imx/s400_api.h
View file

@ -10,19 +10,104 @@
#define AHAB_CMD_TAG 0x17
#define AHAB_RESP_TAG 0xe1
#define AHAB_LOG_CID 0x21
#define AHAB_AUTH_OEM_CTNR_CID 0x87
#define AHAB_VERIFY_IMG_CID 0x88
#define AHAB_RELEASE_CTNR_CID 0x89
#define AHAB_WRITE_SECURE_FUSE_REQ_CID 0x91
#define AHAB_FWD_LIFECYCLE_UP_REQ_CID 0x95
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_GET_FW_VERSION_CID 0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_GET_FW_STATUS_CID 0xC5
#define AHAB_WRITE_FUSE_REQ_CID 0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
#define AHAB_GET_INFO_CID 0xDA
/* ELE commands */
#define ELE_PING_REQ (0x01)
#define ELE_FW_AUTH_REQ (0x02)
#define ELE_RESTART_RST_TIMER_REQ (0x04)
#define ELE_DUMP_DEBUG_BUFFER_REQ (0x21)
#define ELE_OEM_CNTN_AUTH_REQ (0x87)
#define ELE_VERIFY_IMAGE_REQ (0x88)
#define ELE_RELEASE_CONTAINER_REQ (0x89)
#define ELE_WRITE_SECURE_FUSE_REQ (0x91)
#define ELE_FWD_LIFECYCLE_UP_REQ (0x95)
#define ELE_READ_FUSE_REQ (0x97)
#define ELE_GET_FW_VERSION_REQ (0x9D)
#define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
#define ELE_GET_EVENTS_REQ (0xA2)
#define ELE_ENABLE_PATCH_REQ (0xC3)
#define ELE_RELEASE_RDC_REQ (0xC4)
#define ELE_GET_FW_STATUS_REQ (0xC5)
#define ELE_ENABLE_OTFAD_REQ (0xC6)
#define ELE_RESET_REQ (0xC7)
#define ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)
#define ELE_POWER_DOWN_REQ (0xD1)
#define ELE_ENABLE_APC_REQ (0xD2)
#define ELE_ENABLE_RTC_REQ (0xD3)
#define ELE_DEEP_POWER_DOWN_REQ (0xD4)
#define ELE_STOP_RST_TIMER_REQ (0xD5)
#define ELE_WRITE_FUSE_REQ (0xD6)
#define ELE_RELEASE_CAAM_REQ (0xD7)
#define ELE_RESET_A35_CTX_REQ (0xD8)
#define ELE_MOVE_TO_UNSECURED_REQ (0xD9)
#define ELE_GET_INFO_REQ (0xDA)
#define ELE_ATTEST_REQ (0xDB)
#define ELE_RELEASE_PATCH_REQ (0xDC)
#define ELE_OTP_SEQ_SWITH_REQ (0xDD)
/* ELE failure indications */
#define ELE_ROM_PING_FAILURE_IND (0x0A)
#define ELE_FW_PING_FAILURE_IND (0x1A)
#define ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)
#define ELE_BAD_HASH_FAILURE_IND (0xF1)
#define ELE_INVALID_LIFECYCLE_IND (0xF2)
#define ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)
#define ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)
#define ELE_BAD_VALUE_FAILURE_IND (0xF5)
#define ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)
#define ELE_BAD_CONTAINER_FAILURE_IND (0xF7)
#define ELE_BAD_VERSION_FAILURE_IND (0xF8)
#define ELE_INVALID_KEY_FAILURE_IND (0xF9)
#define ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)
#define ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)
#define ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)
#define ELE_BAD_UID_FAILURE_IND (0xFD)
#define ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)
#define ELE_MUST_SIGNED_FAILURE_IND (0xE0)
#define ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)
#define ELE_BAD_SRK_SET_FAILURE_IND (0xEF)
#define ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)
#define ELE_WRONG_SIZE_FAILURE_IND (0xA7)
#define ELE_ENCRYPTION_FAILURE_IND (0xA8)
#define ELE_DECRYPTION_FAILURE_IND (0xA9)
#define ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)
#define ELE_OTP_LOCKED_FAILURE_IND (0xAB)
#define ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)
#define ELE_TIME_OUT_FAILURE_IND (0xB0)
#define ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)
#define ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)
#define ELE_DMA_FAILURE_IND (0xB5)
#define ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)
#define ELE_MUST_ATTEST_FAILURE_IND (0xB7)
#define ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)
#define ELE_CRC_ERROR_IND (0xB9)
#define ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)
#define ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)
#define ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)
#define ELE_LOCKED_REG_FAILURE_IND (0xBE)
#define ELE_BAD_ID_FAILURE_IND (0xBF)
#define ELE_INVALID_OPERATION_FAILURE_IND (0xC0)
#define ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)
#define ELE_MSG_TRUNCATED_IND (0xC2)
#define ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)
#define ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)
#define ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)
#define ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)
#define ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)
#define ELE_OUT_OF_MEMORY_IND (0xD1)
#define ELE_CSTM_FAILURE_IND (0xCF)
#define ELE_OLD_VERSION_FAILURE_IND (0xCE)
#define ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)
#define ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)
#define ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)
#define ELE_ABORT_IND (0xFF)
/* ELE IPC identifier */
#define ELE_IPC_MU_RTD (0x1)
#define ELE_IPC_MU_APD (0x2)
/* ELE Status*/
#define ELE_SUCCESS_IND (0xD6)
#define ELE_FAILURE_IND (0x29)
#define S400_MAX_MSG 255U
@ -41,6 +126,8 @@ struct sentinel_get_info_data {
u32 uid[4];
u32 sha256_rom_patch[8];
u32 sha_fw[8];
u32 oem_srkh[16];
u32 state;
};
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
@ -56,5 +143,6 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
int ahab_release_m33_trout(void);
int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response);
#endif

7
arch/arm/include/asm/mach-imx/sys_proto.h
View file

@ -172,6 +172,13 @@ enum boot_dev_type_e {
BT_DEV_TYPE_INVALID = 0xFF
};
enum boot_stage_type {
BT_STAGE_PRIMARY = 0x6,
BT_STAGE_SECONDARY = 0x9,
BT_STAGE_RECOVERY = 0xa,
BT_STAGE_USB = 0x5,
};
#define QUERY_ROM_VER 1
#define QUERY_BT_DEV 2
#define QUERY_PAGE_SZ 3

4
arch/arm/mach-imx/Makefile
View file

@ -77,6 +77,10 @@ ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o
endif
ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9))
obj-$(CONFIG_AHAB_BOOT) += ele_ahab.o
endif
PLUGIN = board/$(BOARDDIR)/plugin
ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)

586
arch/arm/mach-imx/ele_ahab.c Normal file
View file

@ -0,0 +1,586 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
#include <common.h>
#include <command.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include <asm/mach-imx/ahab.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
#define AHAB_MAX_EVENTS 8
static char *ele_ipc_str[] = {
"IPC = MU RTD (0x1)\n",
"IPC = MU APD (0x2)\n",
"IPC = INVALID\n",
NULL
};
static char *ele_status_str[] = {
"STA = ELE_SUCCESS_IND (0xD6)\n",
"STA = ELE_FAILURE_IND (0x29)\n",
"STA = INVALID\n",
NULL
};
static char *ele_cmd_str[] = {
"CMD = ELE_PING_REQ (0x01)\n",
"CMD = ELE_FW_AUTH_REQ (0x02)\n",
"CMD = ELE_RESTART_RST_TIMER_REQ (0x04)\n",
"CMD = ELE_DUMP_DEBUG_BUFFER_REQ (0x21)\n",
"CMD = ELE_OEM_CNTN_AUTH_REQ (0x87)\n",
"CMD = ELE_VERIFY_IMAGE_REQ (0x88)\n",
"CMD = ELE_RELEASE_CONTAINER_REQ (0x89)\n",
"CMD = ELE_WRITE_SECURE_FUSE_REQ (0x91)\n",
"CMD = ELE_FWD_LIFECYCLE_UP_REQ (0x95)\n",
"CMD = ELE_READ_FUSE_REQ (0x97)\n",
"CMD = ELE_GET_FW_VERSION_REQ (0x9D)\n",
"CMD = ELE_RET_LIFECYCLE_UP_REQ (0xA0)\n",
"CMD = ELE_GET_EVENTS_REQ (0xA2)\n",
"CMD = ELE_ENABLE_PATCH_REQ (0xC3)\n",
"CMD = ELE_RELEASE_RDC_REQ (0xC4)\n",
"CMD = ELE_GET_FW_STATUS_REQ (0xC5)\n",
"CMD = ELE_ENABLE_OTFAD_REQ (0xC6)\n",
"CMD = ELE_RESET_REQ (0xC7)\n",
"CMD = ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)\n",
"CMD = ELE_POWER_DOWN_REQ (0xD1)\n",
"CMD = ELE_ENABLE_APC_REQ (0xD2)\n",
"CMD = ELE_ENABLE_RTC_REQ (0xD3)\n",
"CMD = ELE_DEEP_POWER_DOWN_REQ (0xD4)\n",
"CMD = ELE_STOP_RST_TIMER_REQ (0xD5)\n",
"CMD = ELE_WRITE_FUSE_REQ (0xD6)\n",
"CMD = ELE_RELEASE_CAAM_REQ (0xD7)\n",
"CMD = ELE_RESET_A35_CTX_REQ (0xD8)\n",
"CMD = ELE_MOVE_TO_UNSECURED_REQ (0xD9)\n",
"CMD = ELE_GET_INFO_REQ (0xDA)\n",
"CMD = ELE_ATTEST_REQ (0xDB)\n",
"CMD = ELE_RELEASE_PATCH_REQ (0xDC)\n",
"CMD = ELE_OTP_SEQ_SWITH_REQ (0xDD)\n",
"CMD = INVALID\n",
NULL
};
static char *ele_ind_str[] = {
"IND = ELE_ROM_PING_FAILURE_IND (0x0A)\n",
"IND = ELE_FW_PING_FAILURE_IND (0x1A)\n",
"IND = ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)\n",
"IND = ELE_BAD_HASH_FAILURE_IND (0xF1)\n",
"IND = ELE_INVALID_LIFECYCLE_IND (0xF2)\n",
"IND = ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)\n",
"IND = ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)\n",
"IND = ELE_BAD_VALUE_FAILURE_IND (0xF5)\n",
"IND = ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)\n",
"IND = ELE_BAD_CONTAINER_FAILURE_IND (0xF7)\n",
"IND = ELE_BAD_VERSION_FAILURE_IND (0xF8)\n",
"IND = ELE_INVALID_KEY_FAILURE_IND (0xF9)\n",
"IND = ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)\n",
"IND = ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)\n",
"IND = ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)\n",
"IND = ELE_BAD_UID_FAILURE_IND (0xFD)\n",
"IND = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)\n",
"IND = ELE_MUST_SIGNED_FAILURE_IND (0xE0)\n",
"IND = ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)\n",
"IND = ELE_BAD_SRK_SET_FAILURE_IND (0xEF)\n",
"IND = ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)\n",
"IND = ELE_WRONG_SIZE_FAILURE_IND (0xA7)\n",
"IND = ELE_ENCRYPTION_FAILURE_IND (0xA8)\n",
"IND = ELE_DECRYPTION_FAILURE_IND (0xA9)\n",
"IND = ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)\n",
"IND = ELE_OTP_LOCKED_FAILURE_IND (0xAB)\n",
"IND = ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)\n",
"IND = ELE_TIME_OUT_FAILURE_IND (0xB0)\n",
"IND = ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)\n",
"IND = ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)\n",
"IND = ELE_DMA_FAILURE_IND (0xB5)\n",
"IND = ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)\n",
"IND = ELE_MUST_ATTEST_FAILURE_IND (0xB7)\n",
"IND = ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)\n",
"IND = ELE_CRC_ERROR_IND (0xB9)\n",
"IND = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)\n",
"IND = ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)\n",
"IND = ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)\n",
"IND = ELE_LOCKED_REG_FAILURE_IND (0xBE)\n",
"IND = ELE_BAD_ID_FAILURE_IND (0xBF)\n",
"IND = ELE_INVALID_OPERATION_FAILURE_IND (0xC0)\n",
"IND = ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)\n",
"IND = ELE_MSG_TRUNCATED_IND (0xC2)\n",
"IND = ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)\n",
"IND = ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)\n",
"IND = ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)\n",
"IND = ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)\n",
"IND = ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)\n",
"IND = ELE_OUT_OF_MEMORY_IND (0xD1)\n",
"IND = ELE_CSTM_FAILURE_IND (0xCF)\n",
"IND = ELE_OLD_VERSION_FAILURE_IND (0xCE)\n",
"IND = ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)\n",
"IND = ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)\n",
"IND = ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)\n",
"IND = ELE_ABORT_IND (0xFF)\n",
"IND = INVALID\n",
NULL
};
static u8 ele_cmd[] = {
ELE_PING_REQ,
ELE_FW_AUTH_REQ,
ELE_RESTART_RST_TIMER_REQ,
ELE_DUMP_DEBUG_BUFFER_REQ,
ELE_OEM_CNTN_AUTH_REQ,
ELE_VERIFY_IMAGE_REQ,
ELE_RELEASE_CONTAINER_REQ,
ELE_WRITE_SECURE_FUSE_REQ,
ELE_FWD_LIFECYCLE_UP_REQ,
ELE_READ_FUSE_REQ,
ELE_GET_FW_VERSION_REQ,
ELE_RET_LIFECYCLE_UP_REQ,
ELE_GET_EVENTS_REQ,
ELE_ENABLE_PATCH_REQ,
ELE_RELEASE_RDC_REQ,
ELE_GET_FW_STATUS_REQ,
ELE_ENABLE_OTFAD_REQ,
ELE_RESET_REQ,
ELE_UPDATE_OTP_CLKDIV_REQ,
ELE_POWER_DOWN_REQ,
ELE_ENABLE_APC_REQ,
ELE_ENABLE_RTC_REQ,
ELE_DEEP_POWER_DOWN_REQ,
ELE_STOP_RST_TIMER_REQ,
ELE_WRITE_FUSE_REQ,
ELE_RELEASE_CAAM_REQ,
ELE_RESET_A35_CTX_REQ,
ELE_MOVE_TO_UNSECURED_REQ,
ELE_GET_INFO_REQ,
ELE_ATTEST_REQ,
ELE_RELEASE_PATCH_REQ,
ELE_OTP_SEQ_SWITH_REQ
};
static u8 ele_ind[] = {
ELE_ROM_PING_FAILURE_IND,
ELE_FW_PING_FAILURE_IND,
ELE_BAD_SIGNATURE_FAILURE_IND,
ELE_BAD_HASH_FAILURE_IND,
ELE_INVALID_LIFECYCLE_IND,
ELE_PERMISSION_DENIED_FAILURE_IND,
ELE_INVALID_MESSAGE_FAILURE_IND,
ELE_BAD_VALUE_FAILURE_IND,
ELE_BAD_FUSE_ID_FAILURE_IND,
ELE_BAD_CONTAINER_FAILURE_IND,
ELE_BAD_VERSION_FAILURE_IND,
ELE_INVALID_KEY_FAILURE_IND,
ELE_BAD_KEY_HASH_FAILURE_IND,
ELE_NO_VALID_CONTAINER_FAILURE_IND,
ELE_BAD_CERTIFICATE_FAILURE_IND,
ELE_BAD_UID_FAILURE_IND,
ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND,
ELE_MUST_SIGNED_FAILURE_IND,
ELE_NO_AUTHENTICATION_FAILURE_IND,
ELE_BAD_SRK_SET_FAILURE_IND,
ELE_UNALIGNED_PAYLOAD_FAILURE_IND,
ELE_WRONG_SIZE_FAILURE_IND,
ELE_ENCRYPTION_FAILURE_IND,
ELE_DECRYPTION_FAILURE_IND,
ELE_OTP_PROGFAIL_FAILURE_IND,
ELE_OTP_LOCKED_FAILURE_IND,
ELE_OTP_INVALID_IDX_FAILURE_IND,
ELE_TIME_OUT_FAILURE_IND,
ELE_BAD_PAYLOAD_FAILURE_IND,
ELE_WRONG_ADDRESS_FAILURE_IND,
ELE_DMA_FAILURE_IND,
ELE_DISABLED_FEATURE_FAILURE_IND,
ELE_MUST_ATTEST_FAILURE_IND,
ELE_RNG_NOT_STARTED_FAILURE_IND,
ELE_CRC_ERROR_IND,
ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND,
ELE_INCONSISTENT_PAR_FAILURE_IND,
ELE_RNG_INST_FAILURE_FAILURE_IND,
ELE_LOCKED_REG_FAILURE_IND,
ELE_BAD_ID_FAILURE_IND,
ELE_INVALID_OPERATION_FAILURE_IND,
ELE_NON_SECURE_STATE_FAILURE_IND,
ELE_MSG_TRUNCATED_IND,
ELE_BAD_IMAGE_NUM_FAILURE_IND,
ELE_BAD_IMAGE_ADDR_FAILURE_IND,
ELE_BAD_IMAGE_PARAM_FAILURE_IND,
ELE_BAD_IMAGE_TYPE_FAILURE_IND,
ELE_CORRUPTED_SRK_FAILURE_IND,
ELE_OUT_OF_MEMORY_IND,
ELE_CSTM_FAILURE_IND,
ELE_OLD_VERSION_FAILURE_IND,
ELE_WRONG_BOOT_MODE_FAILURE_IND,
ELE_APC_ALREADY_ENABLED_FAILURE_IND,
ELE_RTC_ALREADY_ENABLED_FAILURE_IND,
ELE_ABORT_IND
};
static u8 ele_ipc[] = {
ELE_IPC_MU_RTD,
ELE_IPC_MU_APD
};
static u8 ele_status[] = {
ELE_SUCCESS_IND,
ELE_FAILURE_IND
};
static inline u32 get_idx(u8 *list, u8 tgt, u32 size)
{
u32 i;
for (i = 0; i < size; i++) {
if (list[i] == tgt)
return i;
}
return i; /* last str is invalid */
}
static void display_ahab_auth_ind(u32 event)
{
u8 resp_ind = (event >> 8) & 0xff;
printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]);
}
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
u32 resp;
memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
flush_dcache_range(IMG_CONTAINER_BASE,
IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
if (err) {
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
display_ahab_auth_ind(resp);
}
return err;
}
int ahab_auth_release(void)
{
int err;
u32 resp;
err = ahab_release_container(&resp);
if (err) {
printf("Error: release container failed, resp 0x%x!\n", resp);
display_ahab_auth_ind(resp);
}
return err;
}
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
{
int err;
u32 resp;
err = ahab_verify_image(image_index, &resp);
if (err) {
printf("Authenticate img %d failed, return %d, resp 0x%x\n",
image_index, err, resp);
display_ahab_auth_ind(resp);
return -EIO;
}
return 0;
}
static inline bool check_in_dram(ulong addr)
{
int i;
struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
if (addr >= bd->bi_dram[i].start &&
addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
return true;
}
}
return false;
}
int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
if (addr % 4) {
puts("Error: Image's address is not 4 byte aligned\n");
return -EINVAL;
}
if (!check_in_dram(addr)) {
puts("Error: Image's address is invalid\n");
return -EINVAL;
}
phdr = (struct container_hdr *)addr;
if (phdr->tag != 0x87 || phdr->version != 0x0) {
printf("Error: Wrong container header\n");
return -EFAULT;
}
if (!phdr->num_images) {
printf("Error: Wrong container, no image found\n");
return -EFAULT;
}
length = phdr->length_lsb + (phdr->length_msb << 8);
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
ret = -EIO;
goto exit;
}
debug("Verify images\n");
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));
debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
i, (uint32_t)img->dst, img->offset + addr, img->size);
memcpy((void *)img->dst, (const void *)(img->offset + addr),
img->size);
s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
flush_dcache_range(s, e);
ret = ahab_verify_cntr_image(img, i);
if (ret)
goto exit;
}
exit:
debug("ahab_auth_release, 0x%x\n", ret);
ahab_auth_release();
return ret;
}
static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
ulong addr;
if (argc < 2)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
printf("Authenticate OS container at 0x%lx\n", addr);
if (authenticate_os_container(addr))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static void display_life_cycle(u32 lc)
{
printf("Lifecycle: 0x%08X, ", lc);
switch (lc) {
case 0x1:
printf("BLANK\n\n");
break;
case 0x2:
printf("FAB\n\n");
break;
case 0x4:
printf("NXP Provisioned\n\n");
break;
case 0x8:
printf("OEM Open\n\n");
break;
case 0x20:
printf("OEM closed\n\n");
break;
case 0x40:
printf("Field Return OEM\n\n");
break;
case 0x80:
printf("Field Return NXP\n\n");
break;
case 0x100:
printf("OEM Locked\n\n");
break;
case 0x200:
printf("BRICKED\n\n");
break;
default:
printf("Unknown\n\n");
break;
}
}
static int confirm_close(void)
{
puts("Warning: Please ensure your sample is in NXP closed state, "
"OEM SRK hash has been fused, \n"
" and you are able to boot a signed image successfully "
"without any SECO events reported.\n"
" If not, your sample will be unrecoverable.\n"
"\nReally perform this operation? <y/N>\n");
if (confirm_yesno())
return 1;
puts("Ahab close aborted\n");
return 0;
}
static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int err;
u32 resp;
u32 lc;
if (!confirm_close())
return -EACCES;
lc = readl(FSB_BASE_ADDR + 0x41c);
lc &= 0x3ff;
if (lc != 0x8) {
puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n");
display_life_cycle(lc);
return -EPERM;
}
err = ahab_forward_lifecycle(8, &resp);
if (err != 0) {
printf("Error in forward lifecycle to OEM closed\n");
return -EIO;
}
printf("Change to OEM closed successfully\n");
return 0;
}
int ahab_dump(void)
{
u32 buffer[32];
int ret, i = 0;
do {
ret = ahab_dump_buffer(buffer, 32);
if (ret < 0) {
printf("Error in dump AHAB log\n");
return -EIO;
}
if (ret == 1)
break;
for (i = 0; i < ret; i++)
printf("0x%x\n", buffer[i]);
} while (ret >= 21);
return 0;
}
static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
return ahab_dump();
}
static void display_event(u32 event)
{
printf("\n\t0x%08x\n", event);
printf("\t%s", ele_ipc_str[get_idx(ele_ipc,
(event >> 24) & 0xFF, ARRAY_SIZE(ele_ipc))]);
printf("\t%s", ele_cmd_str[get_idx(ele_cmd,
(event >> 16) & 0xFF, ARRAY_SIZE(ele_cmd))]);
printf("\t%s", ele_ind_str[get_idx(ele_ind,
(event >> 8) & 0xFF, ARRAY_SIZE(ele_ind))]);
printf("\t%s", ele_status_str[get_idx(ele_status,
event & 0xFF, ARRAY_SIZE(ele_status))]);
}
static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
u32 lc, i;
u32 events[AHAB_MAX_EVENTS];
u32 cnt = AHAB_MAX_EVENTS;
int ret;
lc = readl(FSB_BASE_ADDR + 0x41c);
lc &= 0x3ff;
display_life_cycle(lc);
ret = ahab_get_events(events, &cnt, NULL);
if (ret) {
printf("Get ELE EVENTS error %d\n", ret);
return CMD_RET_FAILURE;
}
if (!cnt) {
puts("\n\tNo Events Found!\n");
return 0;
}
for (i = 0; i < cnt; i++)
display_event(events[i]);
return 0;
}
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
"addr - OS container hex address\n"
);
U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
"Change AHAB lifecycle to OEM closed",
""
);
U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
"Dump AHAB log for debug",
""
);
U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
"display AHAB lifecycle only",
""
);

1
arch/arm/mach-imx/imx8/Kconfig
View file

@ -51,7 +51,6 @@ config TARGET_APALIS_IMX8
config TARGET_COLIBRI_IMX8X
bool "Support Colibri iMX8X module"
select BINMAN
select BOARD_LATE_INIT
select IMX8QXP

192
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View file

@ -15,6 +15,7 @@
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@ -36,14 +37,14 @@ void enable_ocotp_clk(unsigned char enable)
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u8 i2c_ccgr[6] = {
u8 i2c_ccgr[] = {
CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
#if (IS_ENABLED(CONFIG_IMX8MP))
CCGR_I2C5_8MP, CCGR_I2C6_8MP
#endif
};
if (i2c_num > ARRAY_SIZE(i2c_ccgr))
if (i2c_num >= ARRAY_SIZE(i2c_ccgr))
return -EINVAL;
clock_enable(i2c_ccgr[i2c_num], !!enable);
@ -825,141 +826,108 @@ u32 mxc_get_clock(enum mxc_clock clk)
return 0;
}
#ifdef CONFIG_DWC_ETH_QOS
int set_clk_eqos(enum enet_freq type)
#if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
static int imx8mp_eqos_interface_init(struct udevice *dev,
phy_interface_t interface_type)
{
u32 target;
u32 enet1_ref;
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
switch (type) {
case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
clrbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
switch (interface_type) {
case PHY_INTERFACE_MODE_MII:
setbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
break;
case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
case PHY_INTERFACE_MODE_RMII:
setbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
break;
case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
setbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
break;
default:
return -EINVAL;
}
/* disable the clock first */
clock_enable(CCGR_QOS_ETHENET, 0);
clock_enable(CCGR_SDMA2, 0);
/* set enet axi clock 266Mhz */
target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_AXI_CLK_ROOT, target);
target = CLK_ROOT_ON | enet1_ref |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_QOS_CLK_ROOT, target);
target = CLK_ROOT_ON |
ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
/* enable clock */
clock_enable(CCGR_QOS_ETHENET, 1);
clock_enable(CCGR_SDMA2, 1);
return 0;
}
int imx_eqos_txclk_set_rate(ulong rate)
#else
static int imx8mp_eqos_interface_init(struct udevice *dev,
phy_interface_t interface_type)
{
u32 val;
u32 eqos_post_div;
/* disable the clock first */
clock_enable(CCGR_QOS_ETHENET, 0);
clock_enable(CCGR_SDMA2, 0);
switch (rate) {
case 125000000:
eqos_post_div = 1;
break;
case 25000000:
eqos_post_div = 125000000 / 25000000;
break;
case 2500000:
eqos_post_div = 125000000 / 2500000;
break;
default:
return -EINVAL;
}
clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(eqos_post_div - 1);
clock_set_target_val(ENET_QOS_CLK_ROOT, val);
/* enable clock */
clock_enable(CCGR_QOS_ETHENET, 1);
clock_enable(CCGR_SDMA2, 1);
return 0;
}
u32 imx_get_eqos_csr_clk(void)
{
return get_root_clk(ENET_AXI_CLK_ROOT);
}
#endif
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type)
static int imx8mp_fec_interface_init(struct udevice *dev,
phy_interface_t interface_type,
bool mx8mp)
{
u32 target;
u32 enet1_ref;
/* i.MX8MP has extra RGMII_EN bit in IOMUXC GPR1 register */
const u32 rgmii_en = mx8mp ? IOMUXC_GPR_GPR1_GPR_ENET1_RGMII_EN : 0;
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
switch (type) {
case ENET_125MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
clrbits_le32(&gpr->gpr[1],
rgmii_en |
IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
switch (interface_type) {
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_RMII:
setbits_le32(&gpr->gpr[1], IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL);
break;
case ENET_50MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
break;
case ENET_25MHZ:
enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
setbits_le32(&gpr->gpr[1], rgmii_en);
break;
default:
return -EINVAL;
}
/* disable the clock first */
clock_enable(CCGR_ENET1, 0);
clock_enable(CCGR_SIM_ENET, 0);
/* set enet axi clock 266Mhz */
target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_AXI_CLK_ROOT, target);
target = CLK_ROOT_ON | enet1_ref |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
clock_set_target_val(ENET_REF_CLK_ROOT, target);
target = CLK_ROOT_ON |
ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
/* enable clock */
clock_enable(CCGR_SIM_ENET, 1);
clock_enable(CCGR_ENET1, 1);
return 0;
}
#endif
int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
{
if (IS_ENABLED(CONFIG_IMX8MM) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx8mm-fec"))
return imx8mp_fec_interface_init(dev, interface_type, false);
if (IS_ENABLED(CONFIG_IMX8MN) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx8mn-fec"))
return imx8mp_fec_interface_init(dev, interface_type, false);
if (IS_ENABLED(CONFIG_IMX8MP) &&
IS_ENABLED(CONFIG_FEC_MXC) &&
device_is_compatible(dev, "fsl,imx8mp-fec"))
return imx8mp_fec_interface_init(dev, interface_type, true);
if (IS_ENABLED(CONFIG_IMX8MP) &&
IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
return imx8mp_eqos_interface_init(dev, interface_type);
return -EINVAL;
}

1
arch/arm/mach-imx/imx8ulp/Kconfig
View file

@ -20,6 +20,7 @@ config TARGET_IMX8ULP_EVK
bool "imx8ulp_evk"
select IMX8ULP
select SUPPORT_SPL
select IMX8ULP_DRAM
endchoice

345
arch/arm/mach-imx/imx8ulp/ahab.c
View file

@ -1,345 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 NXP
*/
#include <common.h>
#include <command.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include <asm/mach-imx/ahab.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define IMG_CONTAINER_BASE (0x22010000UL)
#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
#define AHAB_NO_AUTHENTICATION_IND 0xee
#define AHAB_BAD_KEY_HASH_IND 0xfa
#define AHAB_INVALID_KEY_IND 0xf9
#define AHAB_BAD_SIGNATURE_IND 0xf0
#define AHAB_BAD_HASH_IND 0xf1
static void display_ahab_auth_ind(u32 event)
{
u8 resp_ind = (event >> 8) & 0xff;
switch (resp_ind) {
case AHAB_NO_AUTHENTICATION_IND:
printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_BAD_KEY_HASH_IND:
printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_INVALID_KEY_IND:
printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_BAD_SIGNATURE_IND:
printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_BAD_HASH_IND:
printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
break;
default:
printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
break;
}
}
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
u32 resp;
memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
flush_dcache_range(IMG_CONTAINER_BASE,
IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
if (err) {
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
display_ahab_auth_ind(resp);
}
return err;
}
int ahab_auth_release(void)
{
int err;
u32 resp;
err = ahab_release_container(&resp);
if (err) {
printf("Error: release container failed, resp 0x%x!\n", resp);
display_ahab_auth_ind(resp);
}
return err;
}
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
{
int err;
u32 resp;
err = ahab_verify_image(image_index, &resp);
if (err) {
printf("Authenticate img %d failed, return %d, resp 0x%x\n",
image_index, err, resp);
display_ahab_auth_ind(resp);
return -EIO;
}
return 0;
}
static inline bool check_in_dram(ulong addr)
{
int i;
struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
if (addr >= bd->bi_dram[i].start &&
addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
return true;
}
}
return false;
}
int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
if (addr % 4) {
puts("Error: Image's address is not 4 byte aligned\n");
return -EINVAL;
}
if (!check_in_dram(addr)) {
puts("Error: Image's address is invalid\n");
return -EINVAL;
}
phdr = (struct container_hdr *)addr;
if (phdr->tag != 0x87 || phdr->version != 0x0) {
printf("Error: Wrong container header\n");
return -EFAULT;
}
if (!phdr->num_images) {
printf("Error: Wrong container, no image found\n");
return -EFAULT;
}
length = phdr->length_lsb + (phdr->length_msb << 8);
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
ret = -EIO;
goto exit;
}
debug("Verify images\n");
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));
debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
i, (uint32_t)img->dst, img->offset + addr, img->size);
memcpy((void *)img->dst, (const void *)(img->offset + addr), img->size);
s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
flush_dcache_range(s, e);
ret = ahab_verify_cntr_image(img, i);
if (ret)
goto exit;
}
exit:
debug("ahab_auth_release, 0x%x\n", ret);
ahab_auth_release();
return ret;
}
static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
ulong addr;
if (argc < 2)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
printf("Authenticate OS container at 0x%lx\n", addr);
if (authenticate_os_container(addr))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static void display_life_cycle(u32 lc)
{
printf("Lifecycle: 0x%08X, ", lc);
switch (lc) {
case 0x1:
printf("BLANK\n\n");
break;
case 0x2:
printf("FAB\n\n");
break;
case 0x4:
printf("NXP Provisioned\n\n");
break;
case 0x8:
printf("OEM Open\n\n");
break;
case 0x10:
printf("OEM Secure World Closed\n\n");
break;
case 0x20:
printf("OEM closed\n\n");
break;
case 0x40:
printf("Field Return OEM\n\n");
break;
case 0x80:
printf("Field Return NXP\n\n");
break;
case 0x100:
printf("OEM Locked\n\n");
break;
case 0x200:
printf("BRICKED\n\n");
break;
default:
printf("Unknown\n\n");
break;
}
}
static int confirm_close(void)
{
puts("Warning: Please ensure your sample is in NXP closed state, "
"OEM SRK hash has been fused, \n"
" and you are able to boot a signed image successfully "
"without any SECO events reported.\n"
" If not, your sample will be unrecoverable.\n"
"\nReally perform this operation? <y/N>\n");
if (confirm_yesno())
return 1;
puts("Ahab close aborted\n");
return 0;
}
static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int err;
u32 resp;
if (!confirm_close())
return -EACCES;
err = ahab_forward_lifecycle(8, &resp);
if (err != 0) {
printf("Error in forward lifecycle to OEM closed\n");
return -EIO;
}
printf("Change to OEM closed successfully\n");
return 0;
}
int ahab_dump(void)
{
u32 buffer[32];
int ret, i = 0;
do {
ret = ahab_dump_buffer(buffer, 32);
if (ret < 0) {
printf("Error in dump AHAB log\n");
return -EIO;
}
if (ret == 1)
break;
for (i = 0; i < ret; i++)
printf("0x%x\n", buffer[i]);
} while (ret >= 21);
return 0;
}
static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
return ahab_dump();
}
static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
u32 lc;
lc = readl(FSB_BASE_ADDR + 0x41c);
lc &= 0x3f;
display_life_cycle(lc);
return 0;
}
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
"addr - OS container hex address\n"
);
U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
"Change AHAB lifecycle to OEM closed",
""
);
U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
"Dump AHAB log for debug",
""
);
U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
"display AHAB lifecycle only",
""
);

70
arch/arm/mach-imx/imx8ulp/cgc.c
View file

@ -136,39 +136,34 @@ void cgc1_pll3_init(ulong freq)
clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */
} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0);
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */
} else {
setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */
}
setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* PFD0 324M */
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8); /* PFD1 389M */
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16);
setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 16); /* PFD2 324M */
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24);
setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 24); /* PFD3 389M */
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
;
clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x03010000); /* Set PFD3 DIV1 to 194M, PFD3 DIV2 to 97M */
else
clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x01000000); /* Set PFD3 DIV1 to 389M, PFD3 DIV2 to 194M */
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
@ -179,6 +174,17 @@ void cgc1_pll3_init(ulong freq)
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
/* NIC_AP:
* OD source PLL3 PFD0, 324M
* ND source FRO192, 192M
* LD source FRO192, 96M
*/
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21);
} else {
clrbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21));
}
if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
/* nicclk select pll3 pfd0 */
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28));
@ -219,20 +225,9 @@ void cgc2_pll4_init(bool pll4_reset)
/* Enable all 4 PFDs */
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
/* 99Mhz for NIC_LPAV */
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21);
} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
/* 198Mhz for NIC_LPAV */
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
} else {
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
}
setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 16); /* 316.8Mhz */
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396Mhz */
clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
@ -244,9 +239,22 @@ void cgc2_pll4_init(bool pll4_reset)
clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
;
/* NIC_LPAV:
* OD source PLL4 PFD1, 316.8M
* ND source FRO192, 192M
* LD source FRO192, 96M
*/
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
} else {
clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
}
if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
;
}
}
void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)

46
arch/arm/mach-imx/imx8ulp/clock.c
View file

@ -182,37 +182,20 @@ void clock_init_late(void)
*/
cgc1_pll3_init(540672000);
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD3_DIV1); /* 389M for OD, 194M for LD/ND*/
pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND */
pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
} else {
pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
}
pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND*/
pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
/* enable MU0_MUB clock before access the register of MU0_MUB */
pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
@ -425,6 +408,8 @@ void reset_lcdclk(void)
pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true);
}
/* PLL4 PFD0 max frequency */
#define PLL4_PFD0_MAX_RATE 600000 /*khz*/
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
{
u8 pcd, best_pcd = 0;
@ -443,6 +428,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
for (div = 1; div <= 64; div++) {
parent_rate = pll4_rate;
parent_rate = parent_rate * 18 / pfd;
if (parent_rate > PLL4_PFD0_MAX_RATE)
continue;
parent_rate = parent_rate / div;
for (pcd = 0; pcd < 8; pcd++) {

73
arch/arm/mach-imx/imx8ulp/rdc.c
View file

@ -181,6 +181,25 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
return 0;
}
int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
{
ulong w0_addr;
u32 val;
if (msc > 2)
return -EINVAL;
w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
val = readl(w0_addr);
writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);
val = readl(w0_addr + 4);
writel(val | BIT(31), w0_addr + 4);
return 0;
}
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x27020000UL;
@ -191,7 +210,7 @@ int release_rdc(enum rdc_type type)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
mu_hal_init(s_mu_base);
@ -276,6 +295,36 @@ void xrdc_init_mda(void)
void xrdc_init_mrc(void)
{
/* Re-config MRC3 for SRAM0 in case protected by S400 */
xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
xrdc_config_mrc_dx_perm(3, 0, 0, 1);
xrdc_config_mrc_dx_perm(3, 0, 1, 1);
xrdc_config_mrc_dx_perm(3, 0, 4, 1);
xrdc_config_mrc_dx_perm(3, 0, 5, 1);
xrdc_config_mrc_dx_perm(3, 0, 6, 1);
xrdc_config_mrc_dx_perm(3, 0, 7, 1);
xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF);
/* Clear other 3 regions of MRC3 to invalid */
xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0);
xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0);
xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0);
/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(4, 0, 1, 1);
xrdc_config_mrc_dx_perm(4, 0, 7, 1);
xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(5, 0, 1, 1);
xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
/* Set MRC6 for DDR access from Sentinel */
xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
xrdc_config_mrc_dx_perm(6, 0, 4, 1);
xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
/* The MRC8 is for SRAM1 */
xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
@ -295,6 +344,28 @@ void xrdc_init_mrc(void)
xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
}
void xrdc_init_pdac_msc(void)
{
/* Init LPAV PDAC and MSC for DDR init */
xrdc_config_pdac(5, 36, 6, 0x7); /* CMC2*/
xrdc_config_pdac(5, 36, 7, 0x7);
xrdc_config_pdac(5, 37, 6, 0x7); /* SIM2 */
xrdc_config_pdac(5, 37, 7, 0x7);
xrdc_config_pdac(5, 38, 6, 0x7); /* CGC2 */
xrdc_config_pdac(5, 38, 7, 0x7);
xrdc_config_pdac(5, 39, 6, 0x7); /* PCC5 */
xrdc_config_pdac(5, 39, 7, 0x7);
xrdc_config_msc(0, 0, 6, 0x7); /* GPIOE */
xrdc_config_msc(0, 0, 7, 0x7);
xrdc_config_msc(0, 1, 6, 0x7); /* GPIOF */
xrdc_config_msc(0, 1, 7, 0x7);
xrdc_config_msc(1, 0, 6, 0x7); /* GPIOD */
xrdc_config_msc(1, 0, 7, 0x7);
xrdc_config_msc(2, 6, 6, 0x7); /* DDR controller */
xrdc_config_msc(2, 6, 7, 0x7);
}
int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access)
{
struct trdc *trdc_base = (struct trdc *)0x28031000U;

206
arch/arm/mach-imx/imx8ulp/soc.c
View file

@ -70,9 +70,18 @@ int mmc_get_env_dev(void)
}
#endif
static void set_cpu_info(struct sentinel_get_info_data *info)
{
gd->arch.soc_rev = info->soc;
gd->arch.lifecycle = info->lc;
memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
}
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev);
}
enum bt_mode get_boot_mode(void)
@ -95,14 +104,70 @@ enum bt_mode get_boot_mode(void)
bool m33_image_booted(void)
{
u32 gp6;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
u32 gp6 = 0;
/* DGO_GP6 */
gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
if (gp6 & BIT(5))
return true;
/* DGO_GP6 */
gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
if (gp6 & BIT(5))
return true;
return false;
return false;
} else {
u32 gpr0 = readl(SIM1_BASE_ADDR);
if (gpr0 & BIT(0))
return true;
return false;
}
}
bool rdc_enabled_in_boot(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
u32 val = 0;
int ret;
bool rdc_en = true; /* Default assume DBD_EN is set */
/* Read DBD_EN fuse */
ret = fuse_read(8, 1, &val);
if (!ret)
rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/
return rdc_en;
} else {
u32 gpr0 = readl(SIM1_BASE_ADDR);
if (gpr0 & 0x2)
return true;
return false;
}
}
static void spl_pass_boot_info(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
bool m33_booted = m33_image_booted();
bool rdc_en = rdc_enabled_in_boot();
u32 val = 0;
if (m33_booted)
val |= 0x1;
if (rdc_en)
val |= 0x2;
writel(val, SIM1_BASE_ADDR);
}
}
bool is_m33_handshake_necessary(void)
{
/* Only need handshake in u-boot */
if (!IS_ENABLED(CONFIG_SPL_BUILD))
return (m33_image_booted() || rdc_enabled_in_boot());
else
return false;
}
int m33_image_handshake(ulong timeout_ms)
@ -547,33 +612,65 @@ static void set_core0_reset_vector(u32 entry)
setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
}
static int trdc_set_access(void)
/* Not used now */
int trdc_set_access(void)
{
/*
* TRDC mgr + 4 MBC + 2 MRC.
* S400 should already configure when release RDC
* A35 only map non-secure region for pbridge0 and 1, set sec_access to false
*/
trdc_mbc_set_access(2, 7, 0, 49, false);
trdc_mbc_set_access(2, 7, 0, 50, false);
trdc_mbc_set_access(2, 7, 0, 51, false);
trdc_mbc_set_access(2, 7, 0, 52, false);
trdc_mbc_set_access(2, 7, 0, 53, false);
trdc_mbc_set_access(2, 7, 0, 54, false);
trdc_mbc_set_access(2, 7, 0, 49, true);
trdc_mbc_set_access(2, 7, 0, 50, true);
trdc_mbc_set_access(2, 7, 0, 51, true);
trdc_mbc_set_access(2, 7, 0, 52, true);
trdc_mbc_set_access(2, 7, 0, 53, true);
trdc_mbc_set_access(2, 7, 0, 54, true);
/* CGC0: PBridge0 slot 47 */
/* 0x1fff8000 used for resource table by remoteproc */
trdc_mbc_set_access(0, 7, 2, 31, false);
/* CGC0: PBridge0 slot 47 and PCC0 slot 48 */
trdc_mbc_set_access(2, 7, 0, 47, false);
trdc_mbc_set_access(2, 7, 0, 48, false);
/* PCC1 */
trdc_mbc_set_access(2, 7, 1, 17, false);
trdc_mbc_set_access(2, 7, 1, 34, false);
/* Iomuxc0: : PBridge1 slot 33 */
trdc_mbc_set_access(2, 7, 1, 33, false);
/* flexspi0 */
trdc_mbc_set_access(2, 7, 0, 57, false);
trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
/* tpm0: PBridge1 slot 21 */
trdc_mbc_set_access(2, 7, 1, 21, false);
/* lpi2c0: PBridge1 slot 24 */
trdc_mbc_set_access(2, 7, 1, 24, false);
/* Allow M33 to access TRDC MGR */
trdc_mbc_set_access(2, 6, 0, 49, true);
trdc_mbc_set_access(2, 6, 0, 50, true);
trdc_mbc_set_access(2, 6, 0, 51, true);
trdc_mbc_set_access(2, 6, 0, 52, true);
trdc_mbc_set_access(2, 6, 0, 53, true);
trdc_mbc_set_access(2, 6, 0, 54, true);
/* Set SAI0 for eDMA 0, NS */
trdc_mbc_set_access(2, 0, 1, 28, false);
/* Set SSRAM for eDMA0 access */
trdc_mbc_set_access(0, 0, 2, 0, false);
trdc_mbc_set_access(0, 0, 2, 1, false);
trdc_mbc_set_access(0, 0, 2, 2, false);
trdc_mbc_set_access(0, 0, 2, 3, false);
trdc_mbc_set_access(0, 0, 2, 4, false);
trdc_mbc_set_access(0, 0, 2, 5, false);
trdc_mbc_set_access(0, 0, 2, 6, false);
trdc_mbc_set_access(0, 0, 2, 7, false);
writel(0x800000a0, 0x28031840);
return 0;
}
@ -620,10 +717,6 @@ void set_lpav_qos(void)
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
u32 val = 0;
int ret;
bool rdc_en = true; /* Default assume DBD_EN is set */
/* Enable System Reset Interrupt using WDOG_AD */
setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
@ -640,52 +733,82 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
/* Read DBD_EN fuse */
ret = fuse_read(8, 1, &val);
if (!ret)
rdc_en = !!(val & 0x4000);
if (get_boot_mode() == SINGLE_BOOT) {
if (rdc_en)
release_rdc(RDC_TRDC);
trdc_set_access();
if (get_boot_mode() == SINGLE_BOOT)
lpav_configure(false);
} else {
else
lpav_configure(true);
}
/* Release xrdc, then allow A35 to write SRAM2 */
if (rdc_en)
if (rdc_enabled_in_boot())
release_rdc(RDC_XRDC);
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init_early();
spl_pass_boot_info();
} else {
int ret;
/* reconfigure core0 reset vector to ROM */
set_core0_reset_vector(0x1000);
if (is_m33_handshake_necessary()) {
/* Start handshake with M33 to ensure TRDC configuration completed */
ret = m33_image_handshake(1000);
if (!ret)
gd->arch.m33_handshake_done = true;
else /* Skip and go through to panic in checkcpu as console is ready then */
gd->arch.m33_handshake_done = false;
}
}
return 0;
}
static int imx8ulp_check_mu(void *ctx, struct event *event)
int checkcpu(void)
{
if (is_m33_handshake_necessary()) {
if (!gd->arch.m33_handshake_done) {
puts("M33 Sync: Timeout, Boot Stop!\n");
hang();
} else {
puts("M33 Sync: OK\n");
}
}
return 0;
}
int imx8ulp_dm_post_init(void)
{
struct udevice *devp;
int node, ret;
int ret;
u32 res;
struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu");
ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
if (ret) {
printf("could not get S400 mu %d\n", ret);
return ret;
}
ret = ahab_get_info(info, &res);
if (ret) {
printf("ahab_get_info failed %d\n", ret);
/* fallback to A0.1 revision */
memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
info->soc = 0xa000084d;
}
set_cpu_info(info);
return 0;
}
EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu);
static int imx8ulp_evt_dm_post_init(void *ctx, struct event *event)
{
return imx8ulp_dm_post_init();
}
EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_evt_dm_post_init);
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
@ -737,7 +860,8 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
{
/* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */
if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en())
if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC &&
card_emmc_is_boot_part_en())
image_offset = 0;
return image_offset;

116
arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
View file

@ -11,6 +11,25 @@
#include "upower_api.h"
#define UPOWER_AP_MU1_ADDR 0x29280000
#define PS_RTD BIT(0)
#define PS_DSP BIT(1)
#define PS_A35_0 BIT(2)
#define PS_A35_1 BIT(3)
#define PS_L2 BIT(4)
#define PS_FAST_NIC BIT(5)
#define PS_APD_PERIPH BIT(6)
#define PS_GPU3D BIT(7)
#define PS_HIFI4 BIT(8)
#define PS_DDR GENMASK(12, 9)
#define PS_PXP_EPDC BIT(13)
#define PS_MIPI_DSI BIT(14)
#define PS_MIPI_CSI BIT(15)
#define PS_NIC_LPAV BIT(16)
#define PS_FUSION_AO BIT(17)
#define PS_FUSE BIT(18)
#define PS_UPOWER BIT(19)
static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR;
void upower_wait_resp(void)
@ -110,6 +129,7 @@ int upower_init(void)
u32 fw_major, fw_minor, fw_vfixes;
u32 soc_id;
int status;
enum upwr_resp err_code;
u32 swton;
u64 memon;
@ -140,27 +160,92 @@ int upower_init(void)
}
} while (0);
swton = 0xfff80;
swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR |
PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI;
ret = upwr_pwm_power_on(&swton, NULL, NULL);
if (ret)
printf("Turn on switches fail %d\n", ret);
else
printf("Turn on switches ok\n");
upower_wait_resp();
ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
if (ret != UPWR_REQ_OK)
printf("Failure %d\n", ret);
printf("Turning on switches...\n");
memon = 0x3FFFFFFFFFFFFCUL;
ret = upwr_pwm_power_on(NULL, (const u32 *)&memon, NULL);
upower_wait_resp();
ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
if (ret != UPWR_REQ_OK)
printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
else
printf("Turn on switches ok\n");
/*
* Ascending Order -> bit [0:54)
* CA35 Core 0 L1 cache
* CA35 Core 1 L1 cache
* L2 Cache 0
* L2 Cache 1
* L2 Cache victim/tag
* CAAM Secure RAM
* DMA1 RAM
* FlexSPI2 FIFO, Buffer
* SRAM0
* AD ROM
* USB0 TX/RX RAM
* uSDHC0 FIFO RAM
* uSDHC1 FIFO RAM
* uSDHC2 FIFO and USB1 TX/RX RAM
* GIC RAM
* ENET TX FIXO
* Reserved(Brainshift)
* DCNano Tile2Linear and RGB Correction
* DCNano Cursor and FIFO
* EPDC LUT
* EPDC FIFO
* DMA2 RAM
* GPU2D RAM Group 1
* GPU2D RAM Group 2
* GPU3D RAM Group 1
* GPU3D RAM Group 2
* HIFI4 Caches, IRAM, DRAM
* ISI Buffers
* MIPI-CSI FIFO
* MIPI-DSI FIFO
* PXP Caches, Buffers
* SRAM1
* Casper RAM
* DMA0 RAM
* FlexCAN RAM
* FlexSPI0 FIFO, Buffer
* FlexSPI1 FIFO, Buffer
* CM33 Cache
* PowerQuad RAM
* ETF RAM
* Sentinel PKC, Data RAM1, Inst RAM0/1
* Sentinel ROM
* uPower IRAM/DRAM
* uPower ROM
* CM33 ROM
* SSRAM Partition 0
* SSRAM Partition 1
* SSRAM Partition 2,3,4
* SSRAM Partition 5
* SSRAM Partition 6
* SSRAM Partition 7_a(128KB)
* SSRAM Partition 7_b(64KB)
* SSRAM Partition 7_c(64KB)
* Sentinel Data RAM0, Inst RAM2
*/
/* MIPI-CSI FIFO BIT28 not set */
memon = 0x3FFFFFEFFFFFFCUL;
ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon, NULL);
if (ret)
printf("Turn on memories fail %d\n", ret);
else
printf("Turn on memories ok\n");
printf("Turning on memories...\n");
upower_wait_resp();
ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
if (ret != UPWR_REQ_OK)
printf("Failure %d\n", ret);
printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
else
printf("Turn on memories ok\n");
mdelay(1);
@ -168,13 +253,14 @@ int upower_init(void)
if (ret)
printf("Clear DDR retention fail %d\n", ret);
else
printf("Clear DDR retention ok\n");
printf("Clearing DDR retention...\n");
upower_wait_resp();
ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000);
ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
if (ret != UPWR_REQ_OK)
printf("Failure %d\n", ret);
printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
else
printf("Clear DDR retention ok\n");
return 0;
}

1
arch/arm/mach-imx/imx9/Makefile
View file

@ -4,7 +4,6 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
#ifndef CONFIG_SPL_BUILD
obj-y += imx_bootaux.o

346
arch/arm/mach-imx/imx9/ahab.c
View file

@ -1,346 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*/
#include <common.h>
#include <command.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/mach-imx/s400_api.h>
#include <asm/mach-imx/sys_proto.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/image.h>
#include <console.h>
#include <cpu_func.h>
#include <asm/mach-imx/ahab.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
#define IMG_CONTAINER_BASE (0x80000000UL)
#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
#define AHAB_NO_AUTHENTICATION_IND 0xee
#define AHAB_BAD_KEY_HASH_IND 0xfa
#define AHAB_INVALID_KEY_IND 0xf9
#define AHAB_BAD_SIGNATURE_IND 0xf0
#define AHAB_BAD_HASH_IND 0xf1
static void display_ahab_auth_ind(u32 event)
{
u8 resp_ind = (event >> 8) & 0xff;
switch (resp_ind) {
case AHAB_NO_AUTHENTICATION_IND:
printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_BAD_KEY_HASH_IND:
printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_INVALID_KEY_IND:
printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_BAD_SIGNATURE_IND:
printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
break;
case AHAB_BAD_HASH_IND:
printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
break;
default:
printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
break;
}
}
int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
{
int err;
u32 resp;
memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
flush_dcache_range(IMG_CONTAINER_BASE,
IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
if (err) {
printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
err, resp);
display_ahab_auth_ind(resp);
}
return err;
}
int ahab_auth_release(void)
{
int err;
u32 resp;
err = ahab_release_container(&resp);
if (err) {
printf("Error: release container failed, resp 0x%x!\n", resp);
display_ahab_auth_ind(resp);
}
return err;
}
int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
{
int err;
u32 resp;
err = ahab_verify_image(image_index, &resp);
if (err) {
printf("Authenticate img %d failed, return %d, resp 0x%x\n",
image_index, err, resp);
display_ahab_auth_ind(resp);
return -EIO;
}
return 0;
}
static inline bool check_in_dram(ulong addr)
{
int i;
struct bd_info *bd = gd->bd;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
if (addr >= bd->bi_dram[i].start &&
addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
return true;
}
}
return false;
}
int authenticate_os_container(ulong addr)
{
struct container_hdr *phdr;
int i, ret = 0;
int err;
u16 length;
struct boot_img_t *img;
unsigned long s, e;
if (addr % 4) {
puts("Error: Image's address is not 4 byte aligned\n");
return -EINVAL;
}
if (!check_in_dram(addr)) {
puts("Error: Image's address is invalid\n");
return -EINVAL;
}
phdr = (struct container_hdr *)addr;
if (phdr->tag != 0x87 || phdr->version != 0x0) {
printf("Error: Wrong container header\n");
return -EFAULT;
}
if (!phdr->num_images) {
printf("Error: Wrong container, no image found\n");
return -EFAULT;
}
length = phdr->length_lsb + (phdr->length_msb << 8);
debug("container length %u\n", length);
err = ahab_auth_cntr_hdr(phdr, length);
if (err) {
ret = -EIO;
goto exit;
}
debug("Verify images\n");
/* Copy images to dest address */
for (i = 0; i < phdr->num_images; i++) {
img = (struct boot_img_t *)(addr +
sizeof(struct container_hdr) +
i * sizeof(struct boot_img_t));
debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
i, (uint32_t)img->dst, img->offset + addr, img->size);
memcpy((void *)img->dst, (const void *)(img->offset + addr),
img->size);
s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
flush_dcache_range(s, e);
ret = ahab_verify_cntr_image(img, i);
if (ret)
goto exit;
}
exit:
debug("ahab_auth_release, 0x%x\n", ret);
ahab_auth_release();
return ret;
}
static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
ulong addr;
if (argc < 2)
return CMD_RET_USAGE;
addr = simple_strtoul(argv[1], NULL, 16);
printf("Authenticate OS container at 0x%lx\n", addr);
if (authenticate_os_container(addr))
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static void display_life_cycle(u32 lc)
{
printf("Lifecycle: 0x%08X, ", lc);
switch (lc) {
case 0x1:
printf("BLANK\n\n");
break;
case 0x2:
printf("FAB\n\n");
break;
case 0x4:
printf("NXP Provisioned\n\n");
break;
case 0x8:
printf("OEM Open\n\n");
break;
case 0x10:
printf("OEM Secure World Closed\n\n");
break;
case 0x20:
printf("OEM closed\n\n");
break;
case 0x40:
printf("Field Return OEM\n\n");
break;
case 0x80:
printf("Field Return NXP\n\n");
break;
case 0x100:
printf("OEM Locked\n\n");
break;
case 0x200:
printf("BRICKED\n\n");
break;
default:
printf("Unknown\n\n");
break;
}
}
static int confirm_close(void)
{
puts("Warning: Please ensure your sample is in NXP closed state, "
"OEM SRK hash has been fused, \n"
" and you are able to boot a signed image successfully "
"without any SECO events reported.\n"
" If not, your sample will be unrecoverable.\n"
"\nReally perform this operation? <y/N>\n");
if (confirm_yesno())
return 1;
puts("Ahab close aborted\n");
return 0;
}
static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int err;
u32 resp;
if (!confirm_close())
return -EACCES;
err = ahab_forward_lifecycle(8, &resp);
if (err != 0) {
printf("Error in forward lifecycle to OEM closed\n");
return -EIO;
}
printf("Change to OEM closed successfully\n");
return 0;
}
int ahab_dump(void)
{
u32 buffer[32];
int ret, i = 0;
do {
ret = ahab_dump_buffer(buffer, 32);
if (ret < 0) {
printf("Error in dump AHAB log\n");
return -EIO;
}
if (ret == 1)
break;
for (i = 0; i < ret; i++)
printf("0x%x\n", buffer[i]);
} while (ret >= 21);
return 0;
}
static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
return ahab_dump();
}
static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
u32 lc;
lc = readl(FSB_BASE_ADDR + 0x41c);
lc &= 0x3ff;
display_life_cycle(lc);
return 0;
}
U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
"autenticate OS container via AHAB",
"addr\n"
"addr - OS container hex address\n"
);
U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
"Change AHAB lifecycle to OEM closed",
""
);
U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
"Dump AHAB log for debug",
""
);
U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
"display AHAB lifecycle only",
""
);

2
arch/arm/mach-imx/imx9/trdc.c
View file

@ -339,7 +339,7 @@ int release_rdc(u8 xrdc)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
msg.command = ELE_RELEASE_RDC_REQ;
msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
mu_hal_init(s_mu_base);

22
arch/arm/mach-imx/spl_imx_romapi.c
View file

@ -341,15 +341,35 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
int ret;
u32 boot;
u32 boot, bstage;
ret = rom_api_query_boot_infor(QUERY_BT_DEV, &boot);
ret |= rom_api_query_boot_infor(QUERY_BT_STAGE, &bstage);
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
return -1;
}
printf("Boot Stage: ");
switch (bstage) {
case BT_STAGE_PRIMARY:
printf("Primary boot\n");
break;
case BT_STAGE_SECONDARY:
printf("Secondary boot\n");
break;
case BT_STAGE_RECOVERY:
printf("Recovery boot\n");
break;
case BT_STAGE_USB:
printf("USB boot\n");
break;
default:
printf("Unknow (0x%x)\n", bstage);
}
if (is_boot_from_stream_device(boot))
return spl_romapi_load_image_stream(spl_image, bootdev);

17
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
View file

@ -113,7 +113,7 @@ static const iomux_v3_cfg_t eqos_rst_pads[] = {
MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_eqos(void)
static void setup_eqos(void)
{
imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
ARRAY_SIZE(eqos_rst_pads));
@ -124,21 +124,6 @@ static void setup_iomux_eqos(void)
gpio_direction_output(EQOS_RST_PAD, 1);
mdelay(100);
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_eqos();
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#endif /* CONFIG_DWC_ETH_QOS */
int board_phy_config(struct phy_device *phydev)

4
board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
View file

@ -25,7 +25,7 @@ struct lpddr4_tcm_desc {
u32 cl_eeprom_get_ddrinfo(void);
u32 cl_eeprom_set_ddrinfo(u32 ddrinfo);
u32 cl_eeprom_get_subind(void);
u32 cl_eeprom_set_subind(u32 subind);
u8 cl_eeprom_get_subind(void);
u8 cl_eeprom_set_subind(u8 subind);
u32 cl_eeprom_get_osize(void);
#endif

2
board/dhelectronics/dh_imx8mp/Makefile
View file

@ -5,7 +5,7 @@
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o lpddr4_timing_4G_32.o
obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o
else
obj-y += imx8mp_dhcom_pdk2.o
endif

254
board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
View file

@ -5,12 +5,16 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/imx8mp_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <dm.h>
#include <dt-bindings/clock/imx8mp-clock.h>
#include <env.h>
#include <env_internal.h>
#include <i2c_eeprom.h>
#include <linux/bitfield.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
@ -37,30 +41,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
static void setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Set INTF as RGMII, enable RGMII TXC clock. */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
set_clk_eqos(ENET_125MHZ);
}
static void setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Enable RGMII TX clk output. */
setbits_le32(&gpr->gpr[1], BIT(22));
set_clk_enet(ENET_125MHZ);
}
static int dh_imx8_setup_ethaddr(void)
{
unsigned char enetaddr[6];
@ -127,8 +107,6 @@ int dh_setup_mac_address(void)
int board_init(void)
{
setup_eqos();
setup_fec();
return 0;
}
@ -142,3 +120,227 @@ enum env_location env_get_location(enum env_operation op, int prio)
{
return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
}
static const char *iomuxc_compat = "fsl,imx8mp-iomuxc";
static const char *lan_compat = "ethernet-phy-id0007.c110";
static const char *ksz_compat = "ethernet-phy-id0022.1642";
static int dh_dt_patch_som_eqos(const void *fdt_blob)
{
const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24);
int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode;
const char *mac_compat = "nxp,imx8mp-dwmac-eqos";
void *blob = (void *)fdt_blob;
const fdt32_t *clk_prop;
bool is_gigabit;
u32 handle;
u32 clk[6];
setbits_le32(mux, IOMUX_CONFIG_SION);
is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24));
clrbits_le32(mux, IOMUX_CONFIG_SION);
/* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */
mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
if (mac_node < 0)
return 0;
mdio_node = fdt_first_subnode(blob, mac_node);
if (mdio_node < 0)
return 0;
/* KSZ9131RNXI */
ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
if (ksz_node < 0)
return 0;
/* LAN8740Ai */
lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
if (lan_node < 0)
return 0;
iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
if (iomuxc_node < 0)
return 0;
/*
* The code below adjusts the following DT properties:
* - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock
* - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock
* - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII
* - phy-mode ................ RGMII / RMII
* - pinctrl-0 ............... RGMII / RMII
* - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII
*/
/* Perform all inplace changes first, string changes last. */
clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
if (!clk_prop)
return 0;
clk[0] = clk_prop[0];
clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
clk[2] = clk_prop[2];
clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
clk[4] = clk_prop[4];
clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) :
cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
clk, 6 * sizeof(u32));
clk[0] = cpu_to_fdt32(0);
clk[1] = cpu_to_fdt32(100000000);
clk[2] = is_gigabit ? cpu_to_fdt32(125000000) :
cpu_to_fdt32(50000000);
fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
clk, 3 * sizeof(u32));
handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node);
fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
fdt_for_each_subnode(subnode, blob, iomuxc_node) {
if (!strstr(fdt_get_name(blob, subnode, NULL),
is_gigabit ? "eqos-rgmii" : "eqos-rmii"))
continue;
handle = fdt_get_phandle(blob, subnode);
fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
break;
}
fdt_setprop_string(blob, mac_node, "phy-mode",
is_gigabit ? "rgmii-id" : "rmii");
mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
mdio_node = fdt_first_subnode(blob, mac_node);
ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
fdt_setprop_string(blob, ksz_node, "status",
is_gigabit ? "okay" : "disabled");
mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
mdio_node = fdt_first_subnode(blob, mac_node);
lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
fdt_setprop_string(blob, lan_node, "status",
is_gigabit ? "disabled" : "okay");
return 0;
}
static int dh_dt_patch_som_fec(const void *fdt_blob)
{
const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10);
int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode;
const char *mac_compat = "fsl,imx8mp-fec";
void *blob = (void *)fdt_blob;
const fdt32_t *clk_prop;
bool is_gigabit;
u32 handle;
u32 clk[8];
setbits_le32(mux, IOMUX_CONFIG_SION);
is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10));
clrbits_le32(mux, IOMUX_CONFIG_SION);
/* Test for non-default SoM with 100/Full PHY attached to FEC */
if (is_gigabit)
return 0;
/* Adjust FEC node for Fast LAN8740Ai PHY */
mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
if (mac_node < 0)
return 0;
/* Optional PHY pointed to by phy-handle, possibly on carrier board */
phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle");
if (phy_node > 0) {
fdt_setprop_string(blob, phy_node, "status", "disabled");
mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
}
mdio_node = fdt_first_subnode(blob, mac_node);
if (mdio_node < 0)
return 0;
/* LAN8740Ai */
lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
if (lan_node < 0)
return 0;
iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
if (iomuxc_node < 0)
return 0;
/*
* The code below adjusts the following DT properties:
* - assigned-clock-parents .. 50 MHz RMII ref clock
* - assigned-clock-rates .... 50 MHz RMII ref clock
* - phy-handle .............. LAN8740Ai RMII
* - phy-mode ................ RMII
* - pinctrl-0 ............... RMII
* - PHY subnode status ...... "okay" for RMII PHY
*/
/* Perform all inplace changes first, string changes last. */
clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
if (!clk_prop)
return 0;
clk[0] = clk_prop[0];
clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
clk[2] = clk_prop[2];
clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
clk[4] = clk_prop[4];
clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
clk[6] = clk_prop[6];
clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
clk, 8 * sizeof(u32));
clk[0] = cpu_to_fdt32(0);
clk[1] = cpu_to_fdt32(100000000);
clk[2] = cpu_to_fdt32(50000000);
clk[3] = cpu_to_fdt32(0);
fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
clk, 4 * sizeof(u32));
handle = fdt_get_phandle(blob, lan_node);
fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
fdt_for_each_subnode(subnode, blob, iomuxc_node) {
if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii"))
continue;
handle = fdt_get_phandle(blob, subnode);
fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
break;
}
fdt_setprop_string(blob, mac_node, "phy-mode", "rmii");
mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
mdio_node = fdt_first_subnode(blob, mac_node);
lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
fdt_setprop_string(blob, lan_node, "status", "okay");
return 0;
}
static int dh_dt_patch_som(const void *fdt_blob)
{
int ret;
/* Do nothing if not i.MX8MP DHCOM SoM */
ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som");
if (ret)
return 0;
ret = dh_dt_patch_som_eqos(fdt_blob);
if (ret)
return ret;
return dh_dt_patch_som_fec(fdt_blob);
}
int fdtdec_board_setup(const void *fdt_blob)
{
return dh_dt_patch_som(fdt_blob);
}

1
board/dhelectronics/dh_imx8mp/lpddr4_timing.h
View file

@ -6,6 +6,7 @@
#ifndef __LPDDR4_TIMING_H__
#define __LPDDR4_TIMING_H__
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;
extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;
u8 dh_get_memcfg(void);

1845
board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c Normal file
View file

File diff suppressed because it is too large Load diff

2
board/dhelectronics/dh_imx8mp/spl.c
View file

@ -99,7 +99,7 @@ static struct dram_timing_info *dram_timing_info[8] = {
NULL, /* 512 MiB */
NULL, /* 1024 MiB */
NULL, /* 1536 MiB */
NULL, /* 2048 MiB */
&dh_imx8mp_dhcom_dram_timing_16g_x32, /* 2048 MiB */
NULL, /* 3072 MiB */
&dh_imx8mp_dhcom_dram_timing_32g_x32, /* 4096 MiB */
NULL, /* 6144 MiB */

15
board/engicam/imx8mm/icore_mx8mm.c
View file

@ -29,7 +29,7 @@ static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
static void setup_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
@ -40,19 +40,6 @@ static void setup_iomux_fec(void)
gpio_direction_output(FEC_RST_PAD, 1);
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 13, 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
/* enable rgmii rxc skew and phy mode select to RGMII copper */

16
board/engicam/imx8mp/icore_mx8mp.c
View file

@ -34,19 +34,6 @@ static void setup_fec(void)
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if CONFIG_IS_ENABLED(NET)
int board_phy_config(struct phy_device *phydev)
{
@ -61,9 +48,6 @@ int board_init(void)
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
setup_eqos();
return 0;
}

17
board/freescale/imx8mp_evk/imx8mp_evk.c
View file

@ -29,19 +29,6 @@ static void setup_fec(void)
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if CONFIG_IS_ENABLED(NET)
int board_phy_config(struct phy_device *phydev)
{
@ -59,10 +46,6 @@ int board_init(void)
setup_fec();
}
if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
ret = setup_eqos();
}
return ret;
}

2
board/freescale/imx8ulp_evk/Makefile
View file

@ -3,7 +3,7 @@
obj-y += imx8ulp_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o ddr_init.o
obj-y += spl.o
ifdef CONFIG_IMX8ULP_ND_MODE
obj-y += lpddr4_timing_264.o
else

207
board/freescale/imx8ulp_evk/ddr_init.c
View file

@ -1,207 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2021 NXP
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx-regs.h>
#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR)
#define CTL_START 0x1
#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
#define DFI_INIT_COMPLETE 0x2
#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
#define DENALI_PI_00 (DDR_PI_BASE_ADDR)
#define PI_START 0x1
#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4)
#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11)
#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12)
#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624)
#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537)
#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547)
#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555)
#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564)
#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565)
int ddr_calibration(unsigned int fsp_table[3])
{
u32 reg_val;
u32 int_status_init, phy_freq_req, phy_freq_type;
u32 lock_0, lock_1, lock_2;
u32 freq_chg_pt, freq_chg_cnt;
reg_val = readl(DENALI_CTL_250);
if (((reg_val >> 16) & 0x3) == 1)
freq_chg_cnt = 2;
else
freq_chg_cnt = 3;
reg_val = readl(DENALI_PI_12);
if (reg_val == 0x3) {
freq_chg_pt = 1;
} else if (reg_val == 0x7) {
freq_chg_pt = 2;
} else {
printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
return -1;
}
debug("%s\n", __func__);
/* Assert PI_START parameter and then assert START parameter in Controller. */
reg_val = readl(DENALI_PI_00) | PI_START;
writel(reg_val, DENALI_PI_00);
reg_val = readl(DENALI_CTL_00) | CTL_START;
writel(reg_val, DENALI_CTL_00);
/* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */
do {
if (!freq_chg_cnt) {
int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
/* DDR subsystem is ready for traffic. */
if (int_status_init & DFI_INIT_COMPLETE) {
printf("complete\n");
break;
}
}
/*
* During leveling, PHY will request for freq change and SoC clock
* logic should provide requested frequency, Polling SIM LPDDR_CTRL2
* Bit phy_freq_chg_req until be 1'b1
*/
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
phy_freq_req = (reg_val >> 7) & 0x1;
if (phy_freq_req) {
phy_freq_type = reg_val & 0x1F;
if (!phy_freq_type) {
printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n");
set_ddr_clk(fsp_table[phy_freq_type] >> 1);
/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
} else if (phy_freq_type == 0x01) {
printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n");
set_ddr_clk(fsp_table[phy_freq_type] >> 1);
/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
if (freq_chg_pt == 1)
freq_chg_cnt--;
} else if (phy_freq_type == 0x02) {
printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n");
set_ddr_clk(fsp_table[phy_freq_type] >> 1);
/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
if (freq_chg_pt == 2)
freq_chg_cnt--;
}
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
}
} while (1);
/* Check PLL lock status */
lock_0 = readl(DENALI_PHY_1564) & 0xffff;
lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff;
lock_2 = readl(DENALI_PHY_1565) & 0xffff;
if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) {
printf("De-Skew PLL failed to lock\n");
printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2);
return -1;
}
printf("De-Skew PLL is locked and ready\n");
return 0;
}
int ddr_init(struct dram_timing_info2 *dram_timing)
{
int i;
debug("%s\n", __func__);
set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */
/* Initialize CTL registers */
for (i = 0; i < dram_timing->ctl_cfg_num; i++)
writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
/* Initialize PI registers */
for (i = 0; i < dram_timing->pi_cfg_num; i++)
writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg);
/* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */
writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
for (i = 0; i < dram_timing->phy_f1_cfg_num; i++)
writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg);
/* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */
writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537);
for (i = 0; i < dram_timing->phy_f2_cfg_num; i++)
writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg);
/* Re-enable MULTICAST mode */
writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
return ddr_calibration(dram_timing->fsp_table);
}
void enable_bypass_mode(void)
{
u32 reg_val;
/* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
reg_val = readl(DENALI_PI_04) & ~0x1;
writel(reg_val, DENALI_PI_04);
/* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
writel(0x1, DENALI_PI_12);
/* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
writel(reg_val, DENALI_PI_11);
/* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
writel(reg_val, DENALI_CTL_23);
/* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
writel(reg_val, DENALI_PHY_1547);
/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
reg_val = readl(DENALI_PHY_1624) | 0x1;
writel(reg_val, DENALI_PHY_1624);
/* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */
reg_val = readl(DENALI_PHY_1555) | 0x1;
writel(reg_val, DENALI_PHY_1555);
/* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */
reg_val = 0x020100;
writel(reg_val, DENALI_CTL_25);
}

16
board/freescale/imx8ulp_evk/imx8ulp_evk.c
View file

@ -101,18 +101,12 @@ void mipi_dsi_panel_backlight(void)
int board_init(void)
{
int sync = -ENODEV;
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (m33_image_booted()) {
sync = m33_image_handshake(1000);
printf("M33 Sync: %s\n", sync ? "Timeout" : "OK");
}
/* When sync with M33 is failed, use local driver to set for video */
if (sync != 0 && IS_ENABLED(CONFIG_VIDEO)) {
if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_VIDEO)) {
mipi_dsi_mux_panel();
mipi_dsi_panel_backlight();
}
@ -127,8 +121,16 @@ int board_early_init_f(void)
int board_late_init(void)
{
ulong addr;
#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
board_late_mmc_env_init();
#endif
/* clear fdtaddr to avoid obsolete data */
addr = env_get_hex("fdt_addr_r", 0);
if (addr)
memset((void *)addr, 0, 0x400);
return 0;
}

210
board/freescale/imx8ulp_evk/lpddr4_timing.c
View file

@ -2,7 +2,7 @@
/*
* Copyright 2021 NXP
*
* Generated code from MX8M_DDR_tool
* Generated code from MX8ULP_DDR_tool
*
*/
@ -16,10 +16,10 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e06002c, 0x17702 }, /* 11 */
{ 0x2e060030, 0x5 }, /* 12 */
{ 0x2e060034, 0x61 }, /* 13 */
{ 0x2e060038, 0xce3f }, /* 14 */
{ 0x2e06003c, 0x80e70 }, /* 15 */
{ 0x2e060038, 0x4b00 }, /* 14 */
{ 0x2e06003c, 0x2edfa }, /* 15 */
{ 0x2e060040, 0x5 }, /* 16 */
{ 0x2e060044, 0x210 }, /* 17 */
{ 0x2e060044, 0xc0 }, /* 17 */
{ 0x2e060048, 0x19c7d }, /* 18 */
{ 0x2e06004c, 0x101cdf }, /* 19 */
{ 0x2e060050, 0x5 }, /* 20 */
@ -31,56 +31,56 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e060068, 0xa }, /* 26 */
{ 0x2e06006c, 0x19 }, /* 27 */
{ 0x2e060078, 0x2020200 }, /* 30 */
{ 0x2e06007c, 0x160b }, /* 31 */
{ 0x2e06007c, 0x1604 }, /* 31 */
{ 0x2e060090, 0x10 }, /* 36 */
{ 0x2e0600a4, 0x40c040c }, /* 41 */
{ 0x2e0600a8, 0x8040614 }, /* 42 */
{ 0x2e0600ac, 0x604 }, /* 43 */
{ 0x2e0600b0, 0x3090003 }, /* 44 */
{ 0x2e0600b4, 0x40002 }, /* 45 */
{ 0x2e0600b8, 0xc0011 }, /* 46 */
{ 0x2e0600bc, 0xb0509 }, /* 47 */
{ 0x2e0600b8, 0x50008 }, /* 46 */
{ 0x2e0600bc, 0x40309 }, /* 47 */
{ 0x2e0600c0, 0x2106 }, /* 48 */
{ 0x2e0600c4, 0xa090017 }, /* 49 */
{ 0x2e0600c8, 0x8200016 }, /* 50 */
{ 0x2e0600cc, 0xa0a }, /* 51 */
{ 0x2e0600d0, 0x4000694 }, /* 52 */
{ 0x2e0600d4, 0xa0a0804 }, /* 53 */
{ 0x2e0600d8, 0x4002432 }, /* 54 */
{ 0x2e0600d8, 0x4000d29 }, /* 54 */
{ 0x2e0600dc, 0xa0a0804 }, /* 55 */
{ 0x2e0600e0, 0x4004864 }, /* 56 */
{ 0x2e0600e4, 0x2030404 }, /* 57 */
{ 0x2e0600e8, 0x5040400 }, /* 58 */
{ 0x2e0600ec, 0x80b0a06 }, /* 59 */
{ 0x2e0600e8, 0x4040400 }, /* 58 */
{ 0x2e0600ec, 0x80b0a04 }, /* 59 */
{ 0x2e0600f0, 0x7010100 }, /* 60 */
{ 0x2e0600f4, 0x4150b }, /* 61 */
{ 0x2e0600f4, 0x41507 }, /* 61 */
{ 0x2e0600fc, 0x1010000 }, /* 63 */
{ 0x2e060100, 0x1000000 }, /* 64 */
{ 0x2e060104, 0xe0403 }, /* 65 */
{ 0x2e060108, 0xb3 }, /* 66 */
{ 0x2e06010c, 0x4a }, /* 67 */
{ 0x2e060110, 0x3fd }, /* 68 */
{ 0x2e06010c, 0x1b }, /* 67 */
{ 0x2e060110, 0x16e }, /* 68 */
{ 0x2e060114, 0x94 }, /* 69 */
{ 0x2e060118, 0x803 }, /* 70 */
{ 0x2e06011c, 0x5 }, /* 71 */
{ 0x2e060120, 0x70000 }, /* 72 */
{ 0x2e060124, 0x25000f }, /* 73 */
{ 0x2e060128, 0x4a0078 }, /* 74 */
{ 0x2e060124, 0xe000f }, /* 73 */
{ 0x2e060128, 0x4a0026 }, /* 74 */
{ 0x2e06012c, 0x4000f9 }, /* 75 */
{ 0x2e060130, 0x120103 }, /* 76 */
{ 0x2e060134, 0x50005 }, /* 77 */
{ 0x2e060138, 0x8070005 }, /* 78 */
{ 0x2e060138, 0x7070005 }, /* 78 */
{ 0x2e06013c, 0x505010d }, /* 79 */
{ 0x2e060140, 0x101030a }, /* 80 */
{ 0x2e060144, 0x30a0505 }, /* 81 */
{ 0x2e060148, 0x5050101 }, /* 82 */
{ 0x2e06014c, 0x1030a }, /* 83 */
{ 0x2e060150, 0xe000e }, /* 84 */
{ 0x2e060154, 0x4c004c }, /* 85 */
{ 0x2e060154, 0x1c001c }, /* 85 */
{ 0x2e060158, 0x980098 }, /* 86 */
{ 0x2e06015c, 0x3050505 }, /* 87 */
{ 0x2e060160, 0x3010403 }, /* 88 */
{ 0x2e060164, 0x4050505 }, /* 89 */
{ 0x2e060164, 0x3050505 }, /* 89 */
{ 0x2e060168, 0x3010403 }, /* 90 */
{ 0x2e06016c, 0x8050505 }, /* 91 */
{ 0x2e060170, 0x3010403 }, /* 92 */
@ -101,12 +101,12 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0601b4, 0x2cc0 }, /* 109 */
{ 0x2e0601b8, 0x2cc0 }, /* 110 */
{ 0x2e0601c0, 0x4e5 }, /* 112 */
{ 0x2e0601c4, 0xff40 }, /* 113 */
{ 0x2e0601c8, 0xff40 }, /* 114 */
{ 0x2e0601cc, 0xff40 }, /* 115 */
{ 0x2e0601d0, 0xff40 }, /* 116 */
{ 0x2e0601d4, 0xff40 }, /* 117 */
{ 0x2e0601dc, 0x1beb }, /* 119 */
{ 0x2e0601c4, 0x5b80 }, /* 113 */
{ 0x2e0601c8, 0x5b80 }, /* 114 */
{ 0x2e0601cc, 0x5b80 }, /* 115 */
{ 0x2e0601d0, 0x5b80 }, /* 116 */
{ 0x2e0601d4, 0x5b80 }, /* 117 */
{ 0x2e0601dc, 0xa02 }, /* 119 */
{ 0x2e0601e0, 0x200c0 }, /* 120 */
{ 0x2e0601e4, 0x200c0 }, /* 121 */
{ 0x2e0601e8, 0x200c0 }, /* 122 */
@ -138,9 +138,9 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0602a8, 0xd0005 }, /* 170 */
{ 0x2e0602ac, 0x404 }, /* 171 */
{ 0x2e0602b0, 0xd }, /* 172 */
{ 0x2e0602b4, 0x1b0035 }, /* 173 */
{ 0x2e0602b8, 0x4040042 }, /* 174 */
{ 0x2e0602bc, 0x42 }, /* 175 */
{ 0x2e0602b4, 0xa0014 }, /* 173 */
{ 0x2e0602b8, 0x4040018 }, /* 174 */
{ 0x2e0602bc, 0x18 }, /* 175 */
{ 0x2e0602c0, 0x35006a }, /* 176 */
{ 0x2e0602c4, 0x4040084 }, /* 177 */
{ 0x2e0602c8, 0x84 }, /* 178 */
@ -168,13 +168,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e060390, 0x30000 }, /* 228 */
{ 0x2e060394, 0x1000200 }, /* 229 */
{ 0x2e060398, 0x310040 }, /* 230 */
{ 0x2e06039c, 0x20002 }, /* 231 */
{ 0x2e06039c, 0x20008 }, /* 231 */
{ 0x2e0603a0, 0x400100 }, /* 232 */
{ 0x2e0603a4, 0x80108 }, /* 233 */
{ 0x2e0603a4, 0x80060 }, /* 233 */
{ 0x2e0603a8, 0x1000200 }, /* 234 */
{ 0x2e0603ac, 0x2100040 }, /* 235 */
{ 0x2e0603b0, 0x10 }, /* 236 */
{ 0x2e0603b4, 0xe0003 }, /* 237 */
{ 0x2e0603b4, 0x50003 }, /* 237 */
{ 0x2e0603b8, 0x100001b }, /* 238 */
{ 0x2e0603d8, 0xffff0b00 }, /* 246 */
{ 0x2e0603dc, 0x1010001 }, /* 247 */
@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
{ 0x2e0604d4, 0x102 }, /* 309 */
{ 0x2e0604d8, 0x404 }, /* 310 */
{ 0x2e0604d4, 0x01000102 }, /* 309 */
{ 0x2e0604d8, 0x00000101 }, /* 310 */
{ 0x2e0604dc, 0x40400 }, /* 311 */
{ 0x2e0604e0, 0x4040000 }, /* 312 */
{ 0x2e0604e4, 0x4000000 }, /* 313 */
@ -396,10 +396,10 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0608e0, 0x30f0f }, /* 568 */
{ 0x2e0608e4, 0xffffffff }, /* 569 */
{ 0x2e0608e8, 0x32070f0f }, /* 570 */
{ 0x2e0608ec, 0x1320001 }, /* 571 */
{ 0x2e0608ec, 0x1320000 }, /* 571 */
{ 0x2e0608f0, 0x13200 }, /* 572 */
{ 0x2e0608f4, 0x132 }, /* 573 */
{ 0x2e0608fc, 0x1d1b0000 }, /* 575 */
{ 0x2e0608fc, 0x1b1b0000 }, /* 575 */
{ 0x2e060900, 0x21 }, /* 576 */
{ 0x2e060904, 0xa }, /* 577 */
{ 0x2e060908, 0x166 }, /* 578 */
@ -410,13 +410,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e06091c, 0x432 }, /* 583 */
{ 0x2e060920, 0xdfc }, /* 584 */
{ 0x2e060924, 0x204 }, /* 585 */
{ 0x2e060928, 0x7fa }, /* 586 */
{ 0x2e060928, 0x2dc }, /* 586 */
{ 0x2e06092c, 0x200 }, /* 587 */
{ 0x2e060930, 0x200 }, /* 588 */
{ 0x2e060934, 0x200 }, /* 589 */
{ 0x2e060938, 0x200 }, /* 590 */
{ 0x2e06093c, 0x17ee }, /* 591 */
{ 0x2e060940, 0x4fc4 }, /* 592 */
{ 0x2e06093c, 0x894 }, /* 591 */
{ 0x2e060940, 0x1c98 }, /* 592 */
{ 0x2e060944, 0x204 }, /* 593 */
{ 0x2e060948, 0x1006 }, /* 594 */
{ 0x2e06094c, 0x200 }, /* 595 */
@ -438,7 +438,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e06098c, 0x2010000 }, /* 611 */
{ 0x2e060990, 0x6000200 }, /* 612 */
{ 0x2e060994, 0x3000a06 }, /* 613 */
{ 0x2e060998, 0x2000c06 }, /* 614 */
{ 0x2e060998, 0x2000c03 }, /* 614 */
};
/** PI settings **/
@ -518,22 +518,22 @@ struct dram_cfg_param ddr_pi_cfg[] = {
{ 0x2e062260, 0x10001 }, /* 152 */
{ 0x2e062274, 0x401 }, /* 157 */
{ 0x2e06227c, 0x10000 }, /* 159 */
{ 0x2e062284, 0x6010000 }, /* 161 */
{ 0x2e062284, 0x2010000 }, /* 161 */
{ 0x2e062288, 0xb }, /* 162 */
{ 0x2e06228c, 0x34 }, /* 163 */
{ 0x2e062290, 0x36 }, /* 164 */
{ 0x2e062290, 0x34 }, /* 164 */
{ 0x2e062294, 0x2003c }, /* 165 */
{ 0x2e062298, 0x2000200 }, /* 166 */
{ 0x2e06229c, 0xc040c04 }, /* 167 */
{ 0x2e0622a0, 0xe1406 }, /* 168 */
{ 0x2e0622a4, 0xb3 }, /* 169 */
{ 0x2e0622a8, 0x4a }, /* 170 */
{ 0x2e0622ac, 0x3fd }, /* 171 */
{ 0x2e0622a8, 0x1b }, /* 170 */
{ 0x2e0622ac, 0x16e }, /* 171 */
{ 0x2e0622b0, 0x94 }, /* 172 */
{ 0x2e0622b4, 0x4000803 }, /* 173 */
{ 0x2e0622b8, 0x1010404 }, /* 174 */
{ 0x2e0622bc, 0x1501 }, /* 175 */
{ 0x2e0622c0, 0x1a0018 }, /* 176 */
{ 0x2e0622c0, 0x1a0016 }, /* 176 */
{ 0x2e0622c4, 0x1000100 }, /* 177 */
{ 0x2e0622c8, 0x100 }, /* 178 */
{ 0x2e0622d0, 0x5040303 }, /* 180 */
@ -542,15 +542,15 @@ struct dram_cfg_param ddr_pi_cfg[] = {
{ 0x2e0622e8, 0x2060404 }, /* 186 */
{ 0x2e0622ec, 0x2020402 }, /* 187 */
{ 0x2e0622f0, 0x3102 }, /* 188 */
{ 0x2e0622f4, 0x340009 }, /* 189 */
{ 0x2e0622f8, 0x36000c }, /* 190 */
{ 0x2e0622f4, 0x320009 }, /* 189 */
{ 0x2e0622f8, 0x36000a }, /* 190 */
{ 0x2e0622fc, 0x101000e }, /* 191 */
{ 0x2e062300, 0xd0101 }, /* 192 */
{ 0x2e062304, 0x1004201 }, /* 193 */
{ 0x2e062304, 0x1001801 }, /* 193 */
{ 0x2e062308, 0x1000084 }, /* 194 */
{ 0x2e06230c, 0xe000e }, /* 195 */
{ 0x2e062310, 0x430100 }, /* 196 */
{ 0x2e062314, 0x1000043 }, /* 197 */
{ 0x2e062310, 0x190100 }, /* 196 */
{ 0x2e062314, 0x1000019 }, /* 197 */
{ 0x2e062318, 0x850085 }, /* 198 */
{ 0x2e06231c, 0x220f220f }, /* 199 */
{ 0x2e062320, 0x101220f }, /* 200 */
@ -561,8 +561,8 @@ struct dram_cfg_param ddr_pi_cfg[] = {
{ 0x2e062334, 0xc01000 }, /* 205 */
{ 0x2e062338, 0xc01000 }, /* 206 */
{ 0x2e06233c, 0x21000 }, /* 207 */
{ 0x2e062340, 0x11000d }, /* 208 */
{ 0x2e062344, 0x140042 }, /* 209 */
{ 0x2e062340, 0x2000d }, /* 208 */
{ 0x2e062344, 0x140018 }, /* 209 */
{ 0x2e062348, 0x190084 }, /* 210 */
{ 0x2e06234c, 0x220f0056 }, /* 211 */
{ 0x2e062350, 0x101 }, /* 212 */
@ -575,40 +575,40 @@ struct dram_cfg_param ddr_pi_cfg[] = {
{ 0x2e06236c, 0x5eb }, /* 219 */
{ 0x2e062370, 0x20010003 }, /* 220 */
{ 0x2e062374, 0x80a0a03 }, /* 221 */
{ 0x2e062378, 0x6090506 }, /* 222 */
{ 0x2e06237c, 0x2093 }, /* 223 */
{ 0x2e062380, 0x2001000c }, /* 224 */
{ 0x2e062384, 0x80a0a04 }, /* 225 */
{ 0x2e062378, 0x4090403 }, /* 222 */
{ 0x2e06237c, 0xbd8 }, /* 223 */
{ 0x2e062380, 0x20010005 }, /* 224 */
{ 0x2e062384, 0x80a0a03 }, /* 225 */
{ 0x2e062388, 0xb090a0c }, /* 226 */
{ 0x2e06238c, 0x4126 }, /* 227 */
{ 0x2e062390, 0x20020017 }, /* 228 */
{ 0x2e062394, 0xa0a08 }, /* 229 */
{ 0x2e062398, 0x166 }, /* 230 */
{ 0x2e06239c, 0xdfc }, /* 231 */
{ 0x2e0623a0, 0x7fa }, /* 232 */
{ 0x2e0623a4, 0x4fc4 }, /* 233 */
{ 0x2e0623a0, 0x2dc }, /* 232 */
{ 0x2e0623a4, 0x1c98 }, /* 233 */
{ 0x2e0623a8, 0x1006 }, /* 234 */
{ 0x2e0623ac, 0xa03c }, /* 235 */
{ 0x2e0623b0, 0x4c000e }, /* 236 */
{ 0x2e0623b0, 0x1c000e }, /* 236 */
{ 0x2e0623b4, 0x3030098 }, /* 237 */
{ 0x2e0623b8, 0x258103 }, /* 238 */
{ 0x2e0623bc, 0x17702 }, /* 239 */
{ 0x2e0623c0, 0x5 }, /* 240 */
{ 0x2e0623c4, 0x61 }, /* 241 */
{ 0x2e0623c8, 0xe }, /* 242 */
{ 0x2e0623cc, 0xce3f }, /* 243 */
{ 0x2e0623d0, 0x80e70 }, /* 244 */
{ 0x2e0623cc, 0x4b00 }, /* 243 */
{ 0x2e0623d0, 0x17702 }, /* 244 */
{ 0x2e0623d4, 0x5 }, /* 245 */
{ 0x2e0623d8, 0x210 }, /* 246 */
{ 0x2e0623dc, 0x4c }, /* 247 */
{ 0x2e0623d8, 0xc0 }, /* 246 */
{ 0x2e0623dc, 0x1c }, /* 247 */
{ 0x2e0623e0, 0x19c7d }, /* 248 */
{ 0x2e0623e4, 0x101cdf }, /* 249 */
{ 0x2e0623e4, 0x17702 }, /* 249 */
{ 0x2e0623e8, 0x5 }, /* 250 */
{ 0x2e0623ec, 0x420 }, /* 251 */
{ 0x2e0623f0, 0x1000098 }, /* 252 */
{ 0x2e0623f4, 0x310040 }, /* 253 */
{ 0x2e0623f8, 0x10002 }, /* 254 */
{ 0x2e0623fc, 0x1080040 }, /* 255 */
{ 0x2e0623f8, 0x10008 }, /* 254 */
{ 0x2e0623fc, 0x600040 }, /* 255 */
{ 0x2e062400, 0x10008 }, /* 256 */
{ 0x2e062404, 0x2100040 }, /* 257 */
{ 0x2e062408, 0x310 }, /* 258 */
@ -706,18 +706,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e064168, 0x1000000 }, /* 90 */
{ 0x2e06416c, 0x10001000 }, /* 91 */
{ 0x2e064170, 0xc043242 }, /* 92 */
{ 0x2e064174, 0xf0c1201 }, /* 93 */
{ 0x2e064174, 0xf0c0e01 }, /* 93 */
{ 0x2e064178, 0x1000140 }, /* 94 */
{ 0x2e06417c, 0xc000120 }, /* 95 */
{ 0x2e064180, 0x143 }, /* 96 */
{ 0x2e064180, 0x118 }, /* 96 */
{ 0x2e064184, 0x1000203 }, /* 97 */
{ 0x2e064188, 0x56417032 }, /* 98 */
{ 0x2e06418c, 0x8 }, /* 99 */
{ 0x2e064190, 0x2c302c3 }, /* 100 */
{ 0x2e064194, 0x2c302c3 }, /* 101 */
{ 0x2e064198, 0x2c302c3 }, /* 102 */
{ 0x2e06419c, 0x2c302c3 }, /* 103 */
{ 0x2e0641a0, 0x2c3 }, /* 104 */
{ 0x2e064190, 0x2980298 }, /* 100 */
{ 0x2e064194, 0x2980298 }, /* 101 */
{ 0x2e064198, 0x2980298 }, /* 102 */
{ 0x2e06419c, 0x2980298 }, /* 103 */
{ 0x2e0641a0, 0x298 }, /* 104 */
{ 0x2e0641a4, 0x8000 }, /* 105 */
{ 0x2e0641a8, 0x800080 }, /* 106 */
{ 0x2e0641ac, 0x800080 }, /* 107 */
@ -727,7 +727,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e0641bc, 0x800080 }, /* 111 */
{ 0x2e0641c0, 0x800080 }, /* 112 */
{ 0x2e0641c4, 0x800080 }, /* 113 */
{ 0x2e0641c8, 0x6b0080 }, /* 114 */
{ 0x2e0641c8, 0x1940080 }, /* 114 */
{ 0x2e0641cc, 0x1a00001 }, /* 115 */
{ 0x2e0641d4, 0x10000 }, /* 117 */
{ 0x2e0641d8, 0x80200 }, /* 118 */
@ -782,18 +782,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e064568, 0x1000000 }, /* 346 */
{ 0x2e06456c, 0x10001000 }, /* 347 */
{ 0x2e064570, 0xc043242 }, /* 348 */
{ 0x2e064574, 0xf0c1201 }, /* 349 */
{ 0x2e064574, 0xf0c0e01 }, /* 349 */
{ 0x2e064578, 0x1000140 }, /* 350 */
{ 0x2e06457c, 0xc000120 }, /* 351 */
{ 0x2e064580, 0x143 }, /* 352 */
{ 0x2e064580, 0x118 }, /* 352 */
{ 0x2e064584, 0x1000203 }, /* 353 */
{ 0x2e064588, 0x30217465 }, /* 354 */
{ 0x2e06458c, 0x8 }, /* 355 */
{ 0x2e064590, 0x2c302c3 }, /* 356 */
{ 0x2e064594, 0x2c302c3 }, /* 357 */
{ 0x2e064598, 0x2c302c3 }, /* 358 */
{ 0x2e06459c, 0x2c302c3 }, /* 359 */
{ 0x2e0645a0, 0x2c3 }, /* 360 */
{ 0x2e064590, 0x2980298 }, /* 356 */
{ 0x2e064594, 0x2980298 }, /* 357 */
{ 0x2e064598, 0x2980298 }, /* 358 */
{ 0x2e06459c, 0x2980298 }, /* 359 */
{ 0x2e0645a0, 0x298 }, /* 360 */
{ 0x2e0645a4, 0x8000 }, /* 361 */
{ 0x2e0645a8, 0x800080 }, /* 362 */
{ 0x2e0645ac, 0x800080 }, /* 363 */
@ -803,7 +803,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e0645bc, 0x800080 }, /* 367 */
{ 0x2e0645c0, 0x800080 }, /* 368 */
{ 0x2e0645c4, 0x800080 }, /* 369 */
{ 0x2e0645c8, 0x6b0080 }, /* 370 */
{ 0x2e0645c8, 0x1940080 }, /* 370 */
{ 0x2e0645cc, 0x1a00001 }, /* 371 */
{ 0x2e0645d4, 0x10000 }, /* 373 */
{ 0x2e0645d8, 0x80200 }, /* 374 */
@ -859,18 +859,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e064968, 0x1000000 }, /* 602 */
{ 0x2e06496c, 0x10001000 }, /* 603 */
{ 0x2e064970, 0xc043242 }, /* 604 */
{ 0x2e064974, 0xf0c1201 }, /* 605 */
{ 0x2e064974, 0xf0c0e01 }, /* 605 */
{ 0x2e064978, 0x1000140 }, /* 606 */
{ 0x2e06497c, 0xc000120 }, /* 607 */
{ 0x2e064980, 0x143 }, /* 608 */
{ 0x2e064980, 0x118 }, /* 608 */
{ 0x2e064984, 0x1000203 }, /* 609 */
{ 0x2e064988, 0x75436012 }, /* 610 */
{ 0x2e06498c, 0x8 }, /* 611 */
{ 0x2e064990, 0x2c302c3 }, /* 612 */
{ 0x2e064994, 0x2c302c3 }, /* 613 */
{ 0x2e064998, 0x2c302c3 }, /* 614 */
{ 0x2e06499c, 0x2c302c3 }, /* 615 */
{ 0x2e0649a0, 0x2c3 }, /* 616 */
{ 0x2e064990, 0x2980298 }, /* 612 */
{ 0x2e064994, 0x2980298 }, /* 613 */
{ 0x2e064998, 0x2980298 }, /* 614 */
{ 0x2e06499c, 0x2980298 }, /* 615 */
{ 0x2e0649a0, 0x298 }, /* 616 */
{ 0x2e0649a4, 0x8000 }, /* 617 */
{ 0x2e0649a8, 0x800080 }, /* 618 */
{ 0x2e0649ac, 0x800080 }, /* 619 */
@ -880,7 +880,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e0649bc, 0x800080 }, /* 623 */
{ 0x2e0649c0, 0x800080 }, /* 624 */
{ 0x2e0649c4, 0x800080 }, /* 625 */
{ 0x2e0649c8, 0x6b0080 }, /* 626 */
{ 0x2e0649c8, 0x1940080 }, /* 626 */
{ 0x2e0649cc, 0x1a00001 }, /* 627 */
{ 0x2e0649d4, 0x10000 }, /* 629 */
{ 0x2e0649d8, 0x80200 }, /* 630 */
@ -935,18 +935,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e064d68, 0x1000000 }, /* 858 */
{ 0x2e064d6c, 0x10001000 }, /* 859 */
{ 0x2e064d70, 0xc043242 }, /* 860 */
{ 0x2e064d74, 0xf0c1201 }, /* 861 */
{ 0x2e064d74, 0xf0c0e01 }, /* 861 */
{ 0x2e064d78, 0x1000140 }, /* 862 */
{ 0x2e064d7c, 0xc000120 }, /* 863 */
{ 0x2e064d80, 0x143 }, /* 864 */
{ 0x2e064d80, 0x118 }, /* 864 */
{ 0x2e064d84, 0x1000203 }, /* 865 */
{ 0x2e064d88, 0x32017465 }, /* 866 */
{ 0x2e064d8c, 0x8 }, /* 867 */
{ 0x2e064d90, 0x2c302c3 }, /* 868 */
{ 0x2e064d94, 0x2c302c3 }, /* 869 */
{ 0x2e064d98, 0x2c302c3 }, /* 870 */
{ 0x2e064d9c, 0x2c302c3 }, /* 871 */
{ 0x2e064da0, 0x2c3 }, /* 872 */
{ 0x2e064d90, 0x2980298 }, /* 868 */
{ 0x2e064d94, 0x2980298 }, /* 869 */
{ 0x2e064d98, 0x2980298 }, /* 870 */
{ 0x2e064d9c, 0x2980298 }, /* 871 */
{ 0x2e064da0, 0x298 }, /* 872 */
{ 0x2e064da4, 0x8000 }, /* 873 */
{ 0x2e064da8, 0x800080 }, /* 874 */
{ 0x2e064dac, 0x800080 }, /* 875 */
@ -956,7 +956,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e064dbc, 0x800080 }, /* 879 */
{ 0x2e064dc0, 0x800080 }, /* 880 */
{ 0x2e064dc4, 0x800080 }, /* 881 */
{ 0x2e064dc8, 0x6b0080 }, /* 882 */
{ 0x2e064dc8, 0x1940080 }, /* 882 */
{ 0x2e064dcc, 0x1a00001 }, /* 883 */
{ 0x2e064dd4, 0x10000 }, /* 885 */
{ 0x2e064dd8, 0x80200 }, /* 886 */
@ -1034,7 +1034,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e065868, 0xf0f0f }, /* 1562 */
{ 0x2e06586c, 0x241342 }, /* 1563 */
{ 0x2e065874, 0x1020000 }, /* 1565 */
{ 0x2e065878, 0x701 }, /* 1566 */
{ 0x2e065878, 0x10701 }, /* 1566 */
{ 0x2e06587c, 0x54 }, /* 1567 */
{ 0x2e065880, 0x4102000 }, /* 1568 */
{ 0x2e065884, 0x24410 }, /* 1569 */
@ -1047,7 +1047,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e0658a0, 0x4410 }, /* 1576 */
{ 0x2e0658a4, 0x4410 }, /* 1577 */
{ 0x2e0658b0, 0x60000 }, /* 1580 */
{ 0x2e0658b8, 0x66 }, /* 1582 */
{ 0x2e0658b8, 0x64 }, /* 1582 */
{ 0x2e0658bc, 0x10000 }, /* 1583 */
{ 0x2e0658c0, 0x8 }, /* 1584 */
{ 0x2e0658d8, 0x3000000 }, /* 1590 */
@ -1064,8 +1064,8 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
{ 0x2e065934, 0x40700 }, /* 1613 */
{ 0x2e06594c, 0x2 }, /* 1619 */
{ 0x2e065958, 0xf3c3 }, /* 1622 */
{ 0x2e065964, 0x11542 }, /* 1625 */
{ 0x2e065968, 0x30209bf }, /* 1626 */
{ 0x2e065964, 0x11742 }, /* 1625 */
{ 0x2e065968, 0x3020600 }, /* 1626 */
{ 0x2e06596c, 0x30000 }, /* 1627 */
{ 0x2e065970, 0x3000300 }, /* 1628 */
{ 0x2e065974, 0x3000300 }, /* 1629 */
@ -1098,7 +1098,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
{ 0x2e064170, 0xc043e42 }, /* 92 */
{ 0x2e064174, 0xf0c1701 }, /* 93 */
{ 0x2e064180, 0x187 }, /* 96 */
{ 0x2e064184, 0x3010203 }, /* 97 */
{ 0x2e064184, 0x3200203 }, /* 97 */
{ 0x2e064190, 0x3070307 }, /* 100 */
{ 0x2e064194, 0x3070307 }, /* 101 */
{ 0x2e064198, 0x3070307 }, /* 102 */
@ -1109,7 +1109,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
{ 0x2e064570, 0xc043e42 }, /* 348 */
{ 0x2e064574, 0xf0c1701 }, /* 349 */
{ 0x2e064580, 0x187 }, /* 352 */
{ 0x2e064584, 0x3010203 }, /* 353 */
{ 0x2e064584, 0x3200203 }, /* 353 */
{ 0x2e064590, 0x3070307 }, /* 356 */
{ 0x2e064594, 0x3070307 }, /* 357 */
{ 0x2e064598, 0x3070307 }, /* 358 */
@ -1120,7 +1120,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
{ 0x2e064970, 0xc043e42 }, /* 604 */
{ 0x2e064974, 0xf0c1701 }, /* 605 */
{ 0x2e064980, 0x187 }, /* 608 */
{ 0x2e064984, 0x3010203 }, /* 609 */
{ 0x2e064984, 0x3200203 }, /* 609 */
{ 0x2e064990, 0x3070307 }, /* 612 */
{ 0x2e064994, 0x3070307 }, /* 613 */
{ 0x2e064998, 0x3070307 }, /* 614 */
@ -1131,7 +1131,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
{ 0x2e064d70, 0xc043e42 }, /* 860 */
{ 0x2e064d74, 0xf0c1701 }, /* 861 */
{ 0x2e064d80, 0x187 }, /* 864 */
{ 0x2e064d84, 0x3010203 }, /* 865 */
{ 0x2e064d84, 0x3200203 }, /* 865 */
{ 0x2e064d90, 0x3070307 }, /* 868 */
{ 0x2e064d94, 0x3070307 }, /* 869 */
{ 0x2e064d98, 0x3070307 }, /* 870 */
@ -1154,5 +1154,5 @@ struct dram_timing_info2 dram_timing = {
.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
.phy_f2_cfg = ddr_phy_f2_cfg,
.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
.fsp_table = { 96, 528, 1056 },
.fsp_table = { 96, 192, 1056 },
};

6
board/freescale/imx8ulp_evk/lpddr4_timing_266.c
View file

@ -197,8 +197,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0604c8, 0x8000f00 }, /* 306 */
{ 0x2e0604cc, 0xa08 }, /* 307 */
{ 0x2e0604d0, 0x1010101 }, /* 308 */
{ 0x2e0604d4, 0x102 }, /* 309 */
{ 0x2e0604d8, 0x404 }, /* 310 */
{ 0x2e0604d4, 0x01000102 }, /* 309 */
{ 0x2e0604d8, 0x00000101 }, /* 310 */
{ 0x2e0604dc, 0x40400 }, /* 311 */
{ 0x2e0604e0, 0x4040000 }, /* 312 */
{ 0x2e0604e4, 0x4000000 }, /* 313 */
@ -395,7 +395,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
{ 0x2e0608e0, 0x30f0f }, /* 568 */
{ 0x2e0608e4, 0xffffffff }, /* 569 */
{ 0x2e0608e8, 0x32070f0f }, /* 570 */
{ 0x2e0608ec, 0x1320001 }, /* 571 */
{ 0x2e0608ec, 0x1320000 }, /* 571 */
{ 0x2e0608f0, 0x13200 }, /* 572 */
{ 0x2e0608f4, 0x132 }, /* 573 */
{ 0x2e0608fc, 0x1d1b0000 }, /* 575 */

18
board/freescale/imx8ulp_evk/spl.c
View file

@ -77,16 +77,12 @@ void display_ele_fw_version(void)
void spl_board_init(void)
{
struct udevice *dev;
u32 res;
int ret;
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
ret = imx8ulp_dm_post_init();
if (ret)
return;
board_early_init_f();
@ -108,9 +104,6 @@ void spl_board_init(void)
clock_init_late();
/* DDR initialization */
spl_dram_init();
/* This must place after upower init, so access to MDA and MRC are valid */
/* Init XRDC MDA */
xrdc_init_mda();
@ -118,6 +111,11 @@ void spl_board_init(void)
/* Init XRDC MRC for VIDEO, DSP domains */
xrdc_init_mrc();
xrdc_init_pdac_msc();
/* DDR initialization */
spl_dram_init();
/* Call it after PS16 power up */
set_lpav_qos();

98
board/freescale/mx51evk/mx51evk_video.c
View file

@ -1,98 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Fabio Estevam <fabio.estevam@freescale.com>
*/
#include <common.h>
#include <env.h>
#include <linux/list.h>
#include <asm/gpio.h>
#include <asm/arch/iomux-mx51.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9)
#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10)
#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4)
static struct fb_videomode const claa_wvga = {
.name = "CLAA07LC0ACW",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode const dvi = {
.name = "DVI panel",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 220,
.right_margin = 40,
.upper_margin = 21,
.lower_margin = 7,
.hsync_len = 60,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
void setup_iomux_lcd(void)
{
/* DI2_PIN15 */
imx_iomux_v3_setup_pad(MX51_PAD_DI_GP4__DI2_PIN15);
/* Pad settings for DI2_DISP_CLK */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK,
PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW));
/* Turn on 3.3V voltage for LCD */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D12__GPIO4_9,
NO_PAD_CTRL));
gpio_direction_output(MX51EVK_LCD_3V3, 1);
/* Turn on 5V voltage for LCD */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_CSI2_D13__GPIO4_10,
NO_PAD_CTRL));
gpio_direction_output(MX51EVK_LCD_5V, 1);
/* Turn on GPIO backlight */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_DI1_D1_CS__GPIO3_4,
NO_PAD_CTRL));
gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
}
int board_video_skip(void)
{
int ret;
char const *e = env_get("panel");
if (e) {
if (strcmp(e, "claa") == 0) {
ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
if (ret)
printf("claa cannot be configured: %d\n", ret);
return ret;
}
}
/*
* 'panel' env variable not found or has different value than 'claa'
* Defaulting to dvi output.
*/
ret = ipuv3_fb_init(&dvi, 0, IPU_PIX_FMT_RGB24);
if (ret)
printf("dvi cannot be configured: %d\n", ret);
return ret;
}

36
board/freescale/mx53loco/mx53loco.c
View file

@ -27,6 +27,8 @@
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#include <dm/uclass.h>
#include <dm/device.h>
#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
@ -39,10 +41,16 @@ u32 get_board_rev(void)
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
struct udevice *bus;
struct udevice *dev;
int rev = readl(&fuse->gp[6]);
if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR))
ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
if (ret)
return ret;
if (!dm_i2c_probe(bus, CFG_SYS_DIALOG_PMIC_I2C_ADDR, 0, &dev))
rev = 0;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
@ -62,26 +70,19 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
static void setup_iomux_i2c(void)
{
static const iomux_v3_cfg_t i2c1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
}
static int power_init(void)
{
unsigned int val;
int ret;
struct pmic *p;
struct udevice *bus;
struct udevice *dev;
if (!i2c_probe(CFG_SYS_DIALOG_PMIC_I2C_ADDR)) {
ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus);
if (ret)
return ret;
if (!dm_i2c_probe(bus, CFG_SYS_DIALOG_PMIC_I2C_ADDR, 0, &dev)) {
ret = pmic_dialog_init(I2C_PMIC);
if (ret)
return ret;
@ -124,8 +125,8 @@ static int power_init(void)
return ret;
}
if (!i2c_probe(CFG_SYS_FSL_PMIC_I2C_ADDR)) {
ret = pmic_init(I2C_0);
if (!dm_i2c_probe(bus, CFG_SYS_FSL_PMIC_I2C_ADDR, 0, &dev)) {
ret = pmic_init(0);
if (ret)
return ret;
@ -225,7 +226,6 @@ int board_init(void)
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
mxc_set_sata_internal_clock();
setup_iomux_i2c();
return 0;
}

114
board/freescale/mx53loco/mx53loco_video.c
View file

@ -1,114 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
* Fabio Estevam <fabio.estevam@freescale.com>
*/
#include <common.h>
#include <env.h>
#include <linux/list.h>
#include <asm/gpio.h>
#include <asm/arch/iomux-mx53.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>
#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
static struct fb_videomode const claa_wvga = {
.name = "CLAA07LC0ACW",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode const seiko_wvga = {
.name = "Seiko-43WVF1G",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 29851, /* picosecond (33.5 MHz) */
.left_margin = 89,
.right_margin = 164,
.upper_margin = 23,
.lower_margin = 10,
.hsync_len = 10,
.vsync_len = 10,
.sync = 0,
};
void setup_iomux_lcd(void)
{
static const iomux_v3_cfg_t lcd_pads[] = {
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
};
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
/* Turn on GPIO backlight */
imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);
gpio_direction_output(MX53LOCO_LCD_POWER, 1);
/* Turn on display contrast */
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
gpio_direction_output(IMX_GPIO_NR(1, 1), 1);
}
int board_video_skip(void)
{
int ret;
char const *e = env_get("panel");
if (e) {
if (strcmp(e, "seiko") == 0) {
ret = ipuv3_fb_init(&seiko_wvga, 0, IPU_PIX_FMT_RGB24);
if (ret)
printf("Seiko cannot be configured: %d\n", ret);
return ret;
}
}
/*
* 'panel' env variable not found or has different value than 'seiko'
* Defaulting to claa lcd.
*/
ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
if (ret)
printf("CLAA cannot be configured: %d\n", ret);
return ret;
}

107
board/freescale/mx6sabreauto/mx6sabreauto.c
View file

@ -19,14 +19,12 @@
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/spi.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <input.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/mach-imx/video.h>
@ -49,23 +47,15 @@ DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PMIC 1
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@ -78,70 +68,6 @@ static iomux_v3_cfg_t const uart4_pads[] = {
IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
.gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
.gp = IMX_GPIO_NR(2, 30)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
#ifndef CONFIG_SYS_FLASH_CFI
/*
* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
* Compass Sensor, Accelerometer, Res Touch
*/
static struct i2c_pads_info mx6q_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
.scl = {
.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
.gp = IMX_GPIO_NR(3, 18)
}
};
#endif
static iomux_v3_cfg_t const i2c3_pads[] = {
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const port_exp[] = {
IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
@ -516,21 +442,10 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
if (is_mx6dq() || is_mx6dqp())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
/* I2C 3 Steer */
gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
SETUP_IOMUX_PADS(i2c3_pads);
#ifndef CONFIG_SYS_FLASH_CFI
if (is_mx6dq() || is_mx6dqp())
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
else
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
#endif
gpio_request(IMX_GPIO_NR(1, 15), "expander en");
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
SETUP_IOMUX_PADS(port_exp);
@ -554,22 +469,27 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
unsigned int value;
int ret;
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return 0;
if (ret != 0)
return ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
if (is_mx6dqp()) {
/* set SW2 staby volatage 0.975V*/
pmic_reg_read(p, PFUZE100_SW2STBY, &value);
value = pmic_reg_read(dev, PFUZE100_SW2STBY);
value &= ~0x3f;
value |= 0x17;
pmic_reg_write(p, PFUZE100_SW2STBY, value);
pmic_reg_write(dev, PFUZE100_SW2STBY, value);
}
return pfuze_mode_init(p, APS_PFM);
return pfuze_mode_init(dev, APS_PFM);
}
#ifdef CONFIG_CMD_BMODE
@ -979,7 +899,6 @@ void board_init_f(ulong dummy)
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */

63
board/freescale/mx6sabresd/mx6sabresd.c
View file

@ -17,7 +17,6 @@
#include <env.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
@ -28,7 +27,6 @@
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <input.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
@ -49,14 +47,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define I2C_PMIC 1
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
@ -174,32 +164,6 @@ static void enable_lvds(struct display_info_t const *dev)
enable_backlight();
}
static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static void setup_spi(void)
{
SETUP_IOMUX_PADS(ecspi1_pads);
@ -495,10 +459,7 @@ int board_init(void)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
if (is_mx6dq() || is_mx6dqp())
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
else
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
@ -511,29 +472,32 @@ int board_init(void)
int power_init_board(void)
{
struct pmic *p;
struct udevice *dev;
unsigned int reg;
int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
ret = pmic_get("pfuze100@8", &dev);
if (ret == -ENODEV)
return 0;
ret = pfuze_mode_init(p, APS_PFM);
if (ret != 0)
return ret;
ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
return 0;
}
@ -902,7 +866,6 @@ void board_init_f(ulong dummy)
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
/* setup GP timer */

2
board/freescale/mx6sxsabreauto/MAINTAINERS
View file

@ -1,5 +1,5 @@
MX6SXSABREAUTO BOARD
M: Fabio Estevam <festevam@gmail.com>
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/mx6sxsabreauto/
F: include/configs/mx6sxsabreauto.h

1
board/gateworks/gw_ventana/MAINTAINERS
View file

@ -5,7 +5,6 @@ F: board/gateworks/gw_ventana/
F: include/configs/gw_ventana.h
F: configs/gwventana_nand_defconfig
F: configs/gwventana_emmc_defconfig
F: configs/gwventana_gw5904_defconfig
F: arch/arm/dts/imx6dl-gw51xx.dts
F: arch/arm/dts/imx6dl-gw52xx.dts
F: arch/arm/dts/imx6dl-gw53xx.dts

31
board/gateworks/venice/venice.c
View file

@ -57,24 +57,10 @@ static int __maybe_unused setup_fec(void)
return 0;
}
static int __maybe_unused setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if (IS_ENABLED(CONFIG_NET))
int board_phy_config(struct phy_device *phydev)
{
unsigned short val;
ofnode node;
switch (phydev->phy_id) {
case 0x2000a231: /* TI DP83867 GbE PHY */
@ -85,21 +71,6 @@ int board_phy_config(struct phy_device *phydev)
val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
break;
case 0xd565a401: /* MaxLinear GPY111 */
puts("GPY111 ");
node = phy_get_ofnode(phydev);
if (ofnode_valid(node)) {
u32 rx_delay, tx_delay;
rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
val &= ~((0x7 << 12) | (0x7 << 8));
val |= (rx_delay / 500) << 12;
val |= (tx_delay / 500) << 8;
phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
}
break;
}
if (phydev->drv->config)
@ -115,8 +86,6 @@ int board_init(void)
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
setup_eqos();
return 0;
}

14
board/kontron/pitx_imx8m/pitx_imx8m.c
View file

@ -92,24 +92,12 @@ static iomux_v3_cfg_t const fec1_rst_pads[] = {
IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void setup_iomux_fec(void)
static void setup_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
ARRAY_SIZE(fec1_rst_pads));
}
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
setup_iomux_fec();
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
return set_clk_enet(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
unsigned int val;

15
board/msc/sm2s_imx8mp/sm2s_imx8mp.c
View file

@ -30,19 +30,6 @@ static void setup_fec(void)
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
@ -54,7 +41,5 @@ int board_init(void)
{
setup_fec();
setup_eqos();
return 0;
}

3
board/toradex/colibri-imx8x/Kconfig
View file

@ -12,6 +12,9 @@ config SYS_CONFIG_NAME
config TDX_CFG_BLOCK
default y
config TDX_CFG_BLOCK_2ND_ETHADDR
default y
config TDX_HAVE_MMC
default y

36
board/toradex/colibri-imx8x/colibri-imx8x.c
View file

@ -40,21 +40,25 @@ static void setup_iomux_uart(void)
imx8_iomux_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
static int is_imx8dx(void)
{
u32 val = 0;
sc_err_t sc_err = sc_misc_otp_fuse_read(-1, 6, &val);
if (sc_err == SC_ERR_NONE) {
/* DX has two A35 cores disabled */
return (val & 0xf) != 0x0;
}
return false;
}
void board_mem_get_layout(u64 *phys_sdram_1_start,
u64 *phys_sdram_1_size,
u64 *phys_sdram_2_start,
u64 *phys_sdram_2_size)
{
u32 is_dualx = 0, val = 0;
sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
if (scierr == SC_ERR_NONE) {
/* DX has two A35 cores disabled */
is_dualx = (val & 0xf) != 0x0;
}
*phys_sdram_1_start = PHYS_SDRAM_1;
if (is_dualx)
if (is_imx8dx())
/* Our DX based SKUs only have 1 GB RAM */
*phys_sdram_1_size = SZ_1G;
else
@ -119,6 +123,18 @@ int checkboard(void)
return 0;
}
static void select_dt_from_module_version(void)
{
/*
* The dtb filename is constructed from ${soc}-colibri-${fdt_board}.dtb.
* Set soc depending on the used SoC.
*/
if (is_imx8dx())
env_set("soc", "imx8dx");
else
env_set("soc", "imx8qxp");
}
int board_init(void)
{
board_gpio_init();
@ -154,5 +170,7 @@ int board_late_init(void)
env_set("board_rev", "v1.0");
#endif
select_dt_from_module_version();
return 0;
}

16
board/toradex/verdin-imx8mp/verdin-imx8mp.c
View file

@ -49,19 +49,6 @@ static void setup_fec(void)
setbits_le32(&gpr->gpr[1], BIT(22));
}
static int setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* set INTF as RGMII, enable RGMII TXC clock */
clrsetbits_le32(&gpr->gpr[1],
IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
return set_clk_eqos(ENET_125MHZ);
}
#if IS_ENABLED(CONFIG_NET)
int board_phy_config(struct phy_device *phydev)
{
@ -78,9 +65,6 @@ int board_init(void)
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
ret = setup_eqos();
return ret;
}

13
configs/colibri-imx8x_defconfig
View file

@ -10,14 +10,20 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-colibri"
CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
CONFIG_TARGET_COLIBRI_IMX8X=y
CONFIG_SYS_LOAD_ADDR=0x80280000
CONFIG_SYS_PROMPT="Colibri iMX8X # "
CONFIG_SYS_LOAD_ADDR=0x95c00000
CONFIG_SYS_MEMTEST_START=0x88000000
CONFIG_SYS_MEMTEST_END=0x89000000
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_VERBOSE=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
@ -32,6 +38,7 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -53,6 +60,8 @@ CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.255.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.10.1"
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_FXL6408_GPIO=y

1
configs/colibri_imx7_defconfig
View file

@ -77,6 +77,7 @@ CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS_DT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_MTD_UBI_FASTMAP=y

1
configs/dh_imx6_defconfig
View file

@ -98,6 +98,7 @@ CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

3
configs/gwventana_emmc_defconfig
View file

@ -114,9 +114,12 @@ CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_FIXED=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y
CONFIG_E1000=y
CONFIG_FEC_MXC=y
CONFIG_MV88E6XXX=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PCIE_IMX=y

179
configs/gwventana_gw5904_defconfig
View file

@ -1,179 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_LEN=0xa00000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xB1400
CONFIG_MX6QDL=y
CONFIG_TARGET_GW_VENTANA=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_CMD_EECONFIG=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-gw54xx"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x18000000
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xD1400
CONFIG_CMD_HDMIDETECT=y
CONFIG_AHCI=y
CONFIG_SYS_MONITOR_LEN=409600
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="for btype in ${bootdevs}; do echo; echo Attempting ${btype} boot...; if run ${btype}_boot; then; fi; done"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HWCONFIG=y
CONFIG_MISC_INIT_R=y
CONFIG_PCI_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_SPL_ARGS_ADDR=0x18000000
CONFIG_SPL_FALCON_BOOT_MMCSD=y
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x100
CONFIG_SPL_POWER=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=32
CONFIG_SYS_PBSIZE=539
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_UNZIP=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
# CONFIG_CMD_VIDCONSOLE is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53xx imx6dl-gw53xx imx6q-gw54xx imx6dl-gw54xx imx6q-gw551x imx6dl-gw551x imx6q-gw552x imx6dl-gw552x imx6q-gw553x imx6dl-gw553x imx6q-gw560x imx6dl-gw560x imx6q-gw5903 imx6dl-gw5903 imx6q-gw5904 imx6dl-gw5904 imx6q-gw5907 imx6dl-gw5907 imx6q-gw5910 imx6dl-gw5910 imx6q-gw5912 imx6dl-gw5912 imx6q-gw5913 imx6dl-gw5913"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NETCONSOLE=y
CONFIG_USE_IPADDR=y
CONFIG_IPADDR="192.168.1.1"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.1.146"
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_LBA48=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_FIXED=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y
CONFIG_E1000=y
CONFIG_FEC_MXC=y
CONFIG_MV88E6XXX=y
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PCIE_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_LTC3676=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_POWER_I2C=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_VIDEO=y
CONFIG_VIDEO_LOGO=y
# CONFIG_BACKLIGHT is not set
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP32 is not set
# CONFIG_VIDEO_ANSI is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_I2C_EDID=y
CONFIG_VIDEO_IPUV3=y
CONFIG_IMX_VIDEO_SKIP=y
CONFIG_IMX_HDMI=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_HIDE_LOGO_VERSION=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y

1
configs/imx8mm_venice_defconfig
View file

@ -104,6 +104,7 @@ CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_XWAY=y
CONFIG_PHY_FIXED=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y

1
configs/imx8mn_venice_defconfig
View file

@ -105,6 +105,7 @@ CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_XWAY=y
CONFIG_PHY_FIXED=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y

1
configs/imx8mp_dhcom_pdk2_defconfig
View file

@ -31,6 +31,7 @@ CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_DEBUG_UART=y
CONFIG_LTO=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y

266
configs/imx8mp_dhcom_pdk3_defconfig Normal file
View file

@ -0,0 +1,266 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x1000000
CONFIG_SYS_MALLOC_F_LEN=0x18000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xFE0000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-dhcom-pdk3"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_DH_DHCOM_PDK2=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090
CONFIG_SPL_STACK=0x96fc00
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_DEBUG_UART_BASE=0x30860000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_ENV_OFFSET_REDUND=0xFF0000
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_DEBUG_UART=y
CONFIG_LTO=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_MONITOR_LEN=1048576
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x44000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run dh_update_env distro_bootcmd ; reset"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gpio clear GPIO1_11 ; sleep 0.1 ; gpio set GPIO1_11 ; sleep 0.1 ; i2c dev 4 && i2c mw 0x70 0 4 && i2c probe 0x2d && i2c mw 0x2d 0xaa55.2 0"
CONFIG_DEFAULT_FDT_FILE="imx8mp-dhcom-pdk3.dtb"
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x96fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x4c000000
CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2081
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
CONFIG_SYS_BOOTM_LEN=0x8000000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_EXPORTENV is not set
CONFIG_CMD_ERASEENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=16384
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=20
CONFIG_CMD_MD5SUM=y
CONFIG_MD5SUM_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA1SUM=y
CONFIG_SHA1SUM_VERIFY=y
CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_I2C=y
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MBR=y
CONFIG_CMD_MMC=y
CONFIG_CMD_BKOPS_ENABLE=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_PXE=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_HASH=y
CONFIG_CMD_SMC=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_BTRFS=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_MTDIDS_DEFAULT="nor0=flash@0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=flash@0:-(sf)"
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_ENV_SPI_MAX_HZ=80000000
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_TSIZE=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0xB0C40000
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MP=y
CONFIG_CLK_IMX8MP=y
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DFU_TFTP=y
CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_MTD=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_GPIO_HOG=y
CONFIG_SPL_GPIO_HOG=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
# CONFIG_INPUT is not set
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=50000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_PHY_SMSC=y
CONFIG_DM_MDIO=y
CONFIG_DM_ETH_PHY=y
CONFIG_DWC_ETH_QOS=y
CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PHY_IMX8MQ_USB=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PCA9450=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PCA9450=y
CONFIG_SPL_DM_REGULATOR_PCA9450=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_M41T62=y
CONFIG_CONS_INDEX=2
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="DH electronics"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_SDP_LOADADDR=0x0
CONFIG_USB_FUNCTION_ACM=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_IMX_WATCHDOG=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/imx8mp_venice_defconfig
View file

@ -98,6 +98,7 @@ CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_XWAY=y
CONFIG_PHY_FIXED=y
CONFIG_DM_MDIO=y
CONFIG_DM_DSA=y

1
configs/mx51evk_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_POWER_FSL=y
CONFIG_POWER_SPI=y
CONFIG_RTC_MC13XXX=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y

3
configs/mx53loco_defconfig
View file

@ -44,7 +44,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="FEC0"
CONFIG_ARP_TIMEOUT=200
CONFIG_SYS_I2C_LEGACY=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
@ -61,6 +61,7 @@ CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_POWER_FSL=y
CONFIG_POWER_I2C=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y

13
configs/mx6sabreauto_defconfig
View file

@ -11,9 +11,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6SABREAUTO=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
CONFIG_SPL_TEXT_BASE=0x00908000
@ -37,7 +34,6 @@ CONFIG_SYS_SPL_MALLOC=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
@ -76,7 +72,6 @@ CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
@ -93,10 +88,12 @@ CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_POWER_I2C=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y

11
configs/mx6sabresd_defconfig
View file

@ -11,9 +11,6 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_MX6QDL=y
CONFIG_TARGET_MX6SABRESD=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
CONFIG_SPL_TEXT_BASE=0x00908000
@ -82,7 +79,6 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
@ -100,11 +96,12 @@ CONFIG_PCI_SCAN_SHOW=y
CONFIG_PCIE_IMX=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_POWER_LEGACY=y
CONFIG_POWER_PFUZE100=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PFUZE100=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_POWER_I2C=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y

1
configs/mx6sxsabresd_defconfig
View file

@ -69,6 +69,7 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

1
configs/pico-imx6_defconfig
View file

@ -82,6 +82,7 @@ CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_GADGET=y

1
configs/udoo_defconfig
View file

@ -55,5 +55,6 @@ CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y

1
configs/verdin-imx8mp_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SYS_SPL_MALLOC=y
CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000

2
doc/board/kontron/sl-mx8mm.rst
View file

@ -40,7 +40,7 @@ There are two sources for the TF-A. Mainline and NXP. Get the one you prefer
**NXP's imx-atf**
1. Get TF-A from: https://github.com/nxp-imx/imx-atf, branch: imx_5.4.70_2.3.0
1. Get TF-A from: https://github.com/nxp-imx/imx-atf, branch: lf_v2.6
2. Build
.. code-block:: bash

37
drivers/clk/imx/clk-imx8mp.c
View file

@ -70,6 +70,14 @@ static const char *imx8mp_i2c6_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
static const char *imx8mp_enet_qos_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll1_out", "clk_ext4", };
static const char *imx8mp_enet_qos_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m", "audio_pll1_out",
"clk_ext1", "clk_ext2", "clk_ext3",
"clk_ext4", "video_pll1_out", };
static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m",
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
"audio_pll2_out", "sys_pll1_100m", };
@ -122,6 +130,22 @@ static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_p
"sys_pll2_100m", "sys_pll1_800m",
"sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
static const char *imx8mp_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
static const char *imx8mp_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
static const char *imx8mp_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
static const char *imx8mp_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
"sys_pll1_80m", "video_pll1_out", };
static const char *imx8mp_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
@ -250,6 +274,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, imx8m_clk_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, base + 0xa900));
clk_dm(IMX8MP_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mp_enet_ref_sels, base + 0xa980));
clk_dm(IMX8MP_CLK_ENET_TIMER, imx8m_clk_composite("enet_timer", imx8mp_enet_timer_sels, base + 0xaa00));
clk_dm(IMX8MP_CLK_ENET_PHY_REF, imx8m_clk_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, base + 0xaa80));
@ -270,6 +296,10 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
clk_dm(IMX8MP_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + 0xb280));
clk_dm(IMX8MP_CLK_ECSPI2, imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + 0xb300));
clk_dm(IMX8MP_CLK_PWM1, imx8m_clk_composite_critical("pwm1", imx8mp_pwm1_sels, base + 0xb380));
clk_dm(IMX8MP_CLK_PWM2, imx8m_clk_composite_critical("pwm2", imx8mp_pwm2_sels, base + 0xb400));
clk_dm(IMX8MP_CLK_PWM3, imx8m_clk_composite_critical("pwm3", imx8mp_pwm3_sels, base + 0xb480));
clk_dm(IMX8MP_CLK_PWM4, imx8m_clk_composite_critical("pwm4", imx8mp_pwm4_sels, base + 0xb500));
clk_dm(IMX8MP_CLK_ECSPI3, imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + 0xc180));
clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
@ -292,10 +322,17 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
clk_dm(IMX8MP_CLK_PWM4_ROOT, imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MP_CLK_QOS_ROOT, imx_clk_gate4("qos_root_clk", "ipg_root", base + 0x42c0, 0));
clk_dm(IMX8MP_CLK_QOS_ENET_ROOT, imx_clk_gate4("qos_enet_root_clk", "ipg_root", base + 0x42e0, 0));
clk_dm(IMX8MP_CLK_QSPI_ROOT, imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
clk_dm(IMX8MP_CLK_I2C5_ROOT, imx_clk_gate2("i2c5_root_clk", "i2c5", base + 0x4330, 0));
clk_dm(IMX8MP_CLK_I2C6_ROOT, imx_clk_gate2("i2c6_root_clk", "i2c6", base + 0x4340, 0));
clk_dm(IMX8MP_CLK_SIM_ENET_ROOT, imx_clk_gate4("sim_enet_root_clk", "enet_axi", base + 0x4400, 0));
clk_dm(IMX8MP_CLK_ENET_QOS_ROOT, imx_clk_gate4("enet_qos_root_clk", "sim_enet_root_clk", base + 0x43b0, 0));
clk_dm(IMX8MP_CLK_UART1_ROOT, imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0));
clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));

2
drivers/ddr/imx/imx8ulp/Kconfig
View file

@ -13,6 +13,6 @@ config SAVED_DRAM_TIMING_BASE
help
The DRAM config timing data need to be saved into sram
for low power use.
default 0x2006c000
default 0x20055000
endmenu

53
drivers/ddr/imx/imx8ulp/ddr_init.c
View file

@ -31,6 +31,7 @@
#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624)
#define DENALI_PHY_1625 (DDR_PHY_BASE_ADDR + 4 * 1625)
#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537)
#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
@ -82,25 +83,39 @@ int ddr_calibration(unsigned int fsp_table[3])
u32 int_status_init, phy_freq_req, phy_freq_type;
u32 lock_0, lock_1, lock_2;
u32 freq_chg_pt, freq_chg_cnt;
u32 is_lpddr4 = 0;
if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
ddr_enable_pll_bypass();
freq_chg_cnt = 0;
freq_chg_pt = 0;
} else {
reg_val = readl(DENALI_CTL_250);
if (((reg_val >> 16) & 0x3) == 1)
freq_chg_cnt = 2;
else
freq_chg_cnt = 3;
reg_val = (readl(DENALI_CTL_00)>>8)&0xf;
if(reg_val == 0x7) {
/* LPDDR3 type */
set_ddr_clk(fsp_table[1] >> 1);
freq_chg_cnt = 0;
freq_chg_pt = 0;
} else if(reg_val == 0xb) {
/* LPDDR4/4x type */
is_lpddr4 = 1;
reg_val = readl(DENALI_CTL_250);
if (((reg_val >> 16) & 0x3) == 1)
freq_chg_cnt = 2;
else
freq_chg_cnt = 3;
reg_val = readl(DENALI_PI_12);
if (reg_val == 0x3) {
freq_chg_pt = 1;
} else if (reg_val == 0x7) {
freq_chg_pt = 2;
reg_val = readl(DENALI_PI_12);
if(reg_val == 0x3)
freq_chg_pt = 1;
else if(reg_val == 0x7)
freq_chg_pt = 2;
else {
printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
return -1;
}
} else {
printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
printf("Incorrect DDR type configured!\r\n");
return -1;
}
}
@ -179,6 +194,22 @@ int ddr_calibration(unsigned int fsp_table[3])
}
debug("De-Skew PLL is locked and ready\n");
/* Change LPDDR4 FREQ1 to bypass mode if it is lower than 200MHz */
if(is_lpddr4 && fsp_table[1] < 400) {
/* Set FREQ1 to bypass mode */
reg_val = PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(0);
writel(reg_val, DENALI_PHY_1537);
/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
reg_val =readl(DENALI_PHY_1624) | 0x1;
writel(reg_val, DENALI_PHY_1624);
/* DENALI_PHY_1625: bypass mode in PHY PLL */
reg_val =readl(DENALI_PHY_1625) & ~0xf;
writel(reg_val, DENALI_PHY_1625);
}
return 0;
}

2
drivers/misc/Kconfig
View file

@ -348,7 +348,7 @@ config NPCM_HOST
config SPL_MXC_OCOTP
bool "Enable MXC OCOTP driver in SPL"
depends on SPL_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
default y
help
If you say Y here, you will get support for the One Time

32
drivers/misc/sentinel/fuse.c
View file

@ -60,6 +60,11 @@ struct fsb_map_entry fsb_mapping_table[] = {
{ 46, 8 },
};
/* None ECC banks such like Redundancy or Bit protect */
u32 nonecc_fuse_banks[] = {
0, 1, 8, 12, 16, 22, 24, 25, 26, 27, 36, 41, 51, 56
};
struct s400_map_entry s400_api_mapping_table[] = {
{ 1, 8 }, /* LOCK */
{ 2, 8 }, /* ECID */
@ -67,6 +72,16 @@ struct s400_map_entry s400_api_mapping_table[] = {
{ 15, 8 }, /* OEM SRK HASH */
{ 23, 1, 4, 2 }, /* OTFAD */
{ 25, 8 }, /* Test config2 */
{ 26, 8 }, /* PMU */
{ 27, 8 }, /* Test flow/USB */
{ 32, 8 }, /* GP1 */
{ 33, 8 }, /* GP2 */
{ 34, 8 }, /* GP3 */
{ 35, 8 }, /* GP4 */
{ 36, 8 }, /* GP5 */
{ 49, 8 }, /* GP8 */
{ 50, 8 }, /* GP9 */
{ 51, 8 }, /* GP10 */
};
#elif defined(CONFIG_ARCH_IMX9)
#define FSB_OTP_SHADOW 0x8000
@ -270,11 +285,26 @@ int fuse_prog(u32 bank, u32 word, u32 val)
{
u32 res;
int ret;
bool lock = false;
if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
return -EINVAL;
ret = ahab_write_fuse((bank * 8 + word), val, false, &res);
/* Lock 8ULP ECC fuse word, so second programming will return failure.
* iMX9 OTP can protect ECC fuse, so not need it
*/
#if defined(CONFIG_IMX8ULP)
u32 i;
for (i = 0; i < ARRAY_SIZE(nonecc_fuse_banks); i++) {
if (nonecc_fuse_banks[i] == bank)
break;
}
if (i == ARRAY_SIZE(nonecc_fuse_banks))
lock = true;
#endif
ret = ahab_write_fuse((bank * 8 + word), val, lock, &res);
if (ret) {
printf("ahab write fuse failed %d, 0x%x\n", ret, res);
return ret;

71
drivers/misc/sentinel/s400_api.c
View file

@ -29,7 +29,7 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
msg.command = ELE_RELEASE_RDC_REQ;
switch (xrdc) {
case 0:
msg.data[0] = (0x74 << 8) | core_id;
@ -74,7 +74,7 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 3;
msg.command = AHAB_AUTH_OEM_CTNR_CID;
msg.command = ELE_OEM_CNTN_AUTH_REQ;
msg.data[0] = upper_32_bits(ctnr_addr);
msg.data[1] = lower_32_bits(ctnr_addr);
@ -104,7 +104,7 @@ int ahab_release_container(u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
msg.command = AHAB_RELEASE_CTNR_CID;
msg.command = ELE_RELEASE_CONTAINER_REQ;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
@ -132,7 +132,7 @@ int ahab_verify_image(u32 img_id, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_VERIFY_IMG_CID;
msg.command = ELE_VERIFY_IMAGE_REQ;
msg.data[0] = 1 << img_id;
ret = misc_call(dev, false, &msg, size, &msg, size);
@ -161,7 +161,7 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID;
msg.command = ELE_FWD_LIFECYCLE_UP_REQ;
msg.data[0] = life_cycle;
ret = misc_call(dev, false, &msg, size, &msg, size);
@ -201,7 +201,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_READ_FUSE_REQ_CID;
msg.command = ELE_READ_FUSE_REQ;
msg.data[0] = fuse_id;
ret = misc_call(dev, false, &msg, size, &msg, size);
@ -238,7 +238,7 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 3;
msg.command = AHAB_WRITE_FUSE_REQ_CID;
msg.command = ELE_WRITE_FUSE_REQ;
msg.data[0] = (32 << 16) | (fuse_id << 5);
if (lock)
msg.data[0] |= (1 << 31);
@ -271,7 +271,7 @@ int ahab_release_caam(u32 core_did, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_CAAM_RELEASE_CID;
msg.command = ELE_RELEASE_CAAM_REQ;
msg.data[0] = core_did;
ret = misc_call(dev, false, &msg, size, &msg, size);
@ -310,7 +310,7 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
msg.command = AHAB_GET_FW_VERSION_CID;
msg.command = ELE_GET_FW_VERSION_REQ;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
@ -341,7 +341,7 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
msg.command = AHAB_LOG_CID;
msg.command = ELE_DUMP_DEBUG_BUFFER_REQ;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret) {
@ -375,7 +375,7 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 4;
msg.command = AHAB_GET_INFO_CID;
msg.command = ELE_GET_INFO_REQ;
msg.data[0] = upper_32_bits((ulong)info);
msg.data[1] = lower_32_bits((ulong)info);
msg.data[2] = sizeof(struct sentinel_get_info_data);
@ -406,7 +406,7 @@ int ahab_get_fw_status(u32 *status, u32 *response)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
msg.command = AHAB_GET_FW_STATUS_CID;
msg.command = ELE_GET_FW_STATUS_REQ;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
@ -436,7 +436,7 @@ int ahab_release_m33_trout(void)
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
msg.command = 0xd3;
msg.command = ELE_ENABLE_RTC_REQ;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
@ -445,3 +445,48 @@ int ahab_release_m33_trout(void)
return ret;
}
int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct sentinel_msg);
struct sentinel_msg msg;
int ret, i = 0;
u32 actual_events;
if (!dev) {
printf("s400 dev is not initialized\n");
return -ENODEV;
}
if (!events || !events_cnt || *events_cnt == 0) {
printf("Invalid parameters for %s\n", __func__);
return -EINVAL;
}
msg.version = AHAB_VERSION;
msg.tag = AHAB_CMD_TAG;
msg.size = 1;
msg.command = ELE_GET_EVENTS_REQ;
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
printf("Error: %s: ret %d, response 0x%x\n",
__func__, ret, msg.data[0]);
if (response)
*response = msg.data[0];
if (!ret) {
actual_events = msg.data[1] & 0xffff;
if (*events_cnt < actual_events)
actual_events = *events_cnt;
for (; i < actual_events; i++)
events[i] = msg.data[i + 2];
*events_cnt = actual_events;
}
return ret;
}

21
drivers/net/dwc_eth_qos.c
View file

@ -108,7 +108,7 @@ void eqos_flush_desc_generic(void *desc)
flush_dcache_range(start, end);
}
void eqos_inval_buffer_tegra186(void *buf, size_t size)
static void eqos_inval_buffer_tegra186(void *buf, size_t size)
{
unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev)
eqos->reg_access_ok = true;
/*
* Assert the SWR first, the actually reset the MAC and to latch in
* e.g. i.MX8M Plus GPR[1] content, which selects interface mode.
*/
setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
ret = wait_for_bit_le32(&eqos->dma_regs->mode,
EQOS_DMA_MODE_SWR, false,
eqos->config->swr_wait, false);
@ -1383,7 +1389,6 @@ static int eqos_probe_resources_tegra186(struct udevice *dev)
if (ret) {
pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
goto err_free_clk_rx;
return ret;
}
ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
@ -1412,13 +1417,6 @@ err_free_reset_eqos:
return ret;
}
/* board-specific Ethernet Interface initializations. */
__weak int board_interface_eth_init(struct udevice *dev,
phy_interface_t interface_type)
{
return 0;
}
static int eqos_probe_resources_stm32(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@ -1501,7 +1499,7 @@ static int eqos_remove_resources_tegra186(struct udevice *dev)
static int eqos_remove_resources_stm32(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
struct eqos_priv * __maybe_unused eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
@ -1513,9 +1511,6 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
clk_free(&eqos->clk_ck);
#endif
if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
dm_gpio_free(dev, &eqos->phy_reset_gpio);
debug("%s: OK\n", __func__);
return 0;
}

164
drivers/net/dwc_eth_qos_imx.c
View file

@ -7,6 +7,7 @@
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <errno.h>
#include <eth_phy.h>
#include <log.h>
@ -32,20 +33,18 @@ __weak u32 imx_get_eqos_csr_clk(void)
return 100 * 1000000;
}
__weak int imx_eqos_txclk_set_rate(unsigned long rate)
{
return 0;
}
static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
{
return imx_get_eqos_csr_clk();
struct eqos_priv *eqos = dev_get_priv(dev);
return clk_get_rate(&eqos->clk_master_bus);
}
static int eqos_probe_resources_imx(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
phy_interface_t interface;
int ret;
debug("%s(dev=%p):\n", __func__, dev);
@ -56,6 +55,122 @@ static int eqos_probe_resources_imx(struct udevice *dev)
return -EINVAL;
}
ret = board_interface_eth_init(dev, interface);
if (ret)
return -EINVAL;
eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
dev_dbg(dev, "clk_get_by_name(master_bus) failed: %d", ret);
goto err_probe;
}
ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
if (ret) {
dev_dbg(dev, "clk_get_by_name(ptp_ref) failed: %d", ret);
goto err_free_clk_master_bus;
}
ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
if (ret) {
dev_dbg(dev, "clk_get_by_name(tx) failed: %d", ret);
goto err_free_clk_ptp_ref;
}
ret = clk_get_by_name(dev, "pclk", &eqos->clk_ck);
if (ret) {
dev_dbg(dev, "clk_get_by_name(pclk) failed: %d", ret);
goto err_free_clk_tx;
}
debug("%s: OK\n", __func__);
return 0;
err_free_clk_tx:
clk_free(&eqos->clk_tx);
err_free_clk_ptp_ref:
clk_free(&eqos->clk_ptp_ref);
err_free_clk_master_bus:
clk_free(&eqos->clk_master_bus);
err_probe:
debug("%s: returns %d\n", __func__, ret);
return ret;
}
static int eqos_remove_resources_imx(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clk_free(&eqos->clk_ck);
clk_free(&eqos->clk_tx);
clk_free(&eqos->clk_ptp_ref);
clk_free(&eqos->clk_master_bus);
debug("%s: OK\n", __func__);
return 0;
}
static int eqos_start_clks_imx(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
debug("%s(dev=%p):\n", __func__, dev);
ret = clk_enable(&eqos->clk_master_bus);
if (ret < 0) {
dev_dbg(dev, "clk_enable(clk_master_bus) failed: %d", ret);
goto err;
}
ret = clk_enable(&eqos->clk_ptp_ref);
if (ret < 0) {
dev_dbg(dev, "clk_enable(clk_ptp_ref) failed: %d", ret);
goto err_disable_clk_master_bus;
}
ret = clk_enable(&eqos->clk_tx);
if (ret < 0) {
dev_dbg(dev, "clk_enable(clk_tx) failed: %d", ret);
goto err_disable_clk_ptp_ref;
}
ret = clk_enable(&eqos->clk_ck);
if (ret < 0) {
dev_dbg(dev, "clk_enable(clk_ck) failed: %d", ret);
goto err_disable_clk_tx;
}
debug("%s: OK\n", __func__);
return 0;
err_disable_clk_tx:
clk_disable(&eqos->clk_tx);
err_disable_clk_ptp_ref:
clk_disable(&eqos->clk_ptp_ref);
err_disable_clk_master_bus:
clk_disable(&eqos->clk_master_bus);
err:
debug("%s: FAILED: %d\n", __func__, ret);
return ret;
}
static int eqos_stop_clks_imx(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
clk_disable(&eqos->clk_ck);
clk_disable(&eqos->clk_tx);
clk_disable(&eqos->clk_ptp_ref);
clk_disable(&eqos->clk_master_bus);
debug("%s: OK\n", __func__);
return 0;
}
@ -68,22 +183,29 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
switch (eqos->phy->speed) {
case SPEED_1000:
rate = 125 * 1000 * 1000;
break;
case SPEED_100:
rate = 25 * 1000 * 1000;
break;
case SPEED_10:
rate = 2.5 * 1000 * 1000;
break;
default:
if (eqos->phy->interface == PHY_INTERFACE_MODE_RMII)
rate = 5000; /* 5000 kHz = 5 MHz */
else
rate = 2500; /* 2500 kHz = 2.5 MHz */
if (eqos->phy->speed == SPEED_1000 &&
(eqos->phy->interface == PHY_INTERFACE_MODE_RGMII ||
eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_ID ||
eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
eqos->phy->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
rate *= 50; /* Use 50x base rate i.e. 125 MHz */
} else if (eqos->phy->speed == SPEED_100) {
rate *= 10; /* Use 10x base rate */
} else if (eqos->phy->speed == SPEED_10) {
rate *= 1; /* Use base rate */
} else {
pr_err("invalid speed %d", eqos->phy->speed);
return -EINVAL;
}
ret = imx_eqos_txclk_set_rate(rate);
rate *= 1000; /* clk_set_rate() operates in Hz */
ret = clk_set_rate(&eqos->clk_tx, rate);
if (ret < 0) {
pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
return ret;
@ -107,11 +229,11 @@ static struct eqos_ops eqos_imx_ops = {
.eqos_inval_buffer = eqos_inval_buffer_generic,
.eqos_flush_buffer = eqos_flush_buffer_generic,
.eqos_probe_resources = eqos_probe_resources_imx,
.eqos_remove_resources = eqos_null_ops,
.eqos_remove_resources = eqos_remove_resources_imx,
.eqos_stop_resets = eqos_null_ops,
.eqos_start_resets = eqos_null_ops,
.eqos_stop_clks = eqos_null_ops,
.eqos_start_clks = eqos_null_ops,
.eqos_stop_clks = eqos_stop_clks_imx,
.eqos_start_clks = eqos_start_clks_imx,
.eqos_calibrate_pads = eqos_null_ops,
.eqos_disable_calibration = eqos_null_ops,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,

36
drivers/net/fec_mxc.c
View file

@ -1196,6 +1196,33 @@ static void fec_gpio_reset(struct fec_priv *priv)
}
#endif
static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
{
unsigned int freq;
int ret;
if (!CONFIG_IS_ENABLED(CLK_CCF))
return 0;
if (interface == PHY_INTERFACE_MODE_MII)
freq = 25000000;
else if (interface == PHY_INTERFACE_MODE_RMII)
freq = 50000000;
else if (interface == PHY_INTERFACE_MODE_RGMII ||
interface == PHY_INTERFACE_MODE_RGMII_ID ||
interface == PHY_INTERFACE_MODE_RGMII_RXID ||
interface == PHY_INTERFACE_MODE_RGMII_TXID)
freq = 125000000;
else
return -EINVAL;
ret = clk_set_rate(clk_ref, freq);
if (ret < 0)
return ret;
return 0;
}
static int fecmxc_probe(struct udevice *dev)
{
bool dm_mii_bus = true;
@ -1205,6 +1232,10 @@ static int fecmxc_probe(struct udevice *dev)
uint32_t start;
int ret;
ret = board_interface_eth_init(dev, pdata->phy_interface);
if (ret)
return ret;
if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
if (enet_fused((ulong)priv->eth)) {
printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
@ -1253,6 +1284,11 @@ static int fecmxc_probe(struct udevice *dev)
ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
if (!ret) {
ret = fecmxc_set_ref_clk(&priv->clk_ref,
pdata->phy_interface);
if (ret)
return ret;
ret = clk_enable(&priv->clk_ref);
if (ret)
return ret;

1
drivers/power/pmic/pca9450.c
View file

@ -120,6 +120,7 @@ static const struct udevice_id pca9450_ids[] = {
{ .compatible = "nxp,pca9450a", .data = NXP_CHIP_TYPE_PCA9450A, },
{ .compatible = "nxp,pca9450b", .data = NXP_CHIP_TYPE_PCA9450BC, },
{ .compatible = "nxp,pca9450c", .data = NXP_CHIP_TYPE_PCA9450BC, },
{ .compatible = "nxp,pca9451a", .data = NXP_CHIP_TYPE_PCA9451A, },
{ }
};

11
drivers/power/regulator/pca9450.c
View file

@ -276,7 +276,8 @@ static int pca9450_regulator_probe(struct udevice *dev)
type = dev_get_driver_data(dev_get_parent(dev));
if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC) {
if (type != NXP_CHIP_TYPE_PCA9450A && type != NXP_CHIP_TYPE_PCA9450BC &&
type != NXP_CHIP_TYPE_PCA9451A) {
debug("Unknown PMIC type\n");
return -EINVAL;
}
@ -291,6 +292,14 @@ static int pca9450_regulator_probe(struct udevice *dev)
continue;
}
/* PCA9451A uses BUCK3 in dual-phase and don't have LDO2 and LDO3 */
if (type == NXP_CHIP_TYPE_PCA9451A &&
(!strcmp(pca9450_reg_data[i].name, "BUCK3") ||
!strcmp(pca9450_reg_data[i].name, "LDO2") ||
!strcmp(pca9450_reg_data[i].name, "LDO3"))) {
continue;
}
*plat = pca9450_reg_data[i];
return 0;

78
include/configs/colibri-imx8x.h
View file

@ -8,88 +8,45 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include <linux/stringify.h>
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x83000000\0" \
"kernel_addr_r=0x81000000\0" \
"ramdisk_addr_r=0x83800000\0" \
"scriptaddr=0x80800000\0"
#ifdef CONFIG_AHAB_BOOT
#define AHAB_ENV "sec_boot=yes\0"
#else
#define AHAB_ENV "sec_boot=no\0"
#endif
"fdt_addr_r=0x9d400000\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_comp_addr_r=0xb0000000\0" \
"kernel_comp_size=0x08000000\0" \
"ramdisk_addr_r=0x9d500000\0" \
"scriptaddr=0x9d480000\0"
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
"${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
#define MFG_NAND_PARTITION ""
"loadm4image_0=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0"
/* Enable Distro Boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#undef BOOTENV_RUN_NET_USB_START
#define BOOTENV_RUN_NET_USB_START ""
#define CFG_MFG_ENV_SETTINGS \
"mfgtool_args=setenv bootargs ${consoleargs} " \
"rdinit=/linuxrc g_mass_storage.stall=0 " \
"g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \
"g_mass_storage.idProduct=0x37FF " \
"g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \
"${vidargs} clk_ignore_unused\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffff\0" \
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \
"${fdt_addr};\0" \
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
AHAB_ENV \
BOOTENV \
CFG_MFG_ENV_SETTINGS \
M4_BOOT_ENV \
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"consoleargs=console=ttyLP3,${baudrate} earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
"fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"image=Image\0" \
"console=ttyLP3\0" \
"fdt_board=eval-v3\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcargs=setenv bootargs ${consoleargs} " \
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"panel=NULL\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0" \
"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
/* Link Definitions */
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */
#define CFG_SYS_FSL_USDHC_NUM 2
"${blkcnt}; fi\0"
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
@ -97,9 +54,4 @@
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
/* Generic Timer Definitions */
#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
#endif /* __COLIBRI_IMX8X_H */

1
include/configs/dh_imx6.h
View file

@ -58,6 +58,7 @@
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(USB, usb, 1) \
func(SATA, sata, 0) \

3
include/configs/mx6sabreauto.h
View file

@ -35,7 +35,4 @@
/* DMA stuff, needed for GPMI/MXS NAND support */
/* PMIC */
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#endif /* __MX6SABREAUTO_CONFIG_H */

3
include/configs/mx6sabresd.h
View file

@ -24,9 +24,6 @@
#define CFG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
#endif
/* PMIC */
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

1
include/power/pca9450.h
View file

@ -59,6 +59,7 @@ int power_pca9450_init(unsigned char bus, unsigned char addr);
enum {
NXP_CHIP_TYPE_PCA9450A = 0,
NXP_CHIP_TYPE_PCA9450BC,
NXP_CHIP_TYPE_PCA9451A,
NXP_CHIP_TYPE_AMOUNT
};

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