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powerpc: Drop CONFIG_SYS_ALLOC_DPRAM

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This is not defined anywhere in U-Boot. Drop this dead code.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2017-01-23 13:31:23 -07:00 committed by Tom Rini
parent cbcbf71bf2
commit 8f3086aaac
14 changed files with 7 additions and 166 deletions
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7
arch/powerpc/cpu/mpc8260/spi.c
View file

@ -181,14 +181,7 @@ void spi_init_f (void)
spi->spi_tbc = 0;
spi->spi_txtmp = 0;
/* Allocate space for one transmit and one receive buffer
* descriptor in the DP ram
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = m8260_cpm_dpalloc (sizeof(cbd_t)*2, 8);
#else
dpaddr = CPM_SPI_BASE;
#endif
/* 3 */
/* Set up the SPI parameters in the parameter ram */

1
arch/powerpc/cpu/mpc8xx/Makefile
View file

@ -10,7 +10,6 @@
extra-y += start.o
extra-y += traps.o
obj-y += bedbug_860.o
obj-y += commproc.o
obj-y += cpu.o
obj-y += cpu_init.o
obj-y += fec.o

69
arch/powerpc/cpu/mpc8xx/commproc.c
View file

@ -1,69 +0,0 @@
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <commproc.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_ALLOC_DPRAM
int dpram_init (void)
{
/* Reclaim the DP memory for our use. */
gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
gd->arch.dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
return (0);
}
/* Allocate some memory from the dual ported ram. We may want to
* enforce alignment restrictions, but right now everyone is a good
* citizen.
*/
uint dpram_alloc (uint size)
{
uint addr = gd->arch.dp_alloc_base;
if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top)
return (CPM_DP_NOSPACE);
gd->arch.dp_alloc_base += size;
return addr;
}
uint dpram_base (void)
{
return gd->arch.dp_alloc_base;
}
/* Allocate some memory from the dual ported ram. We may want to
* enforce alignment restrictions, but right now everyone is a good
* citizen.
*/
uint dpram_alloc_align (uint size, uint align)
{
uint addr, mask = align - 1;
addr = (gd->arch.dp_alloc_base + mask) & ~mask;
if ((addr + size) >= gd->arch.dp_alloc_top)
return (CPM_DP_NOSPACE);
gd->arch.dp_alloc_base = addr + size;
return addr;
}
uint dpram_base_align (uint align)
{
uint mask = align - 1;
return (gd->arch.dp_alloc_base + mask) & ~mask;
}
#endif /* CONFIG_SYS_ALLOC_DPRAM */

10
arch/powerpc/cpu/mpc8xx/fec.c
View file

@ -570,14 +570,8 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
rxIdx = 0;
txIdx = 0;
if (!rtx) {
#ifdef CONFIG_SYS_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
#endif
}
if (!rtx)
rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_FEC_BASE);
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:

10
arch/powerpc/cpu/mpc8xx/i2c.c
View file

@ -190,17 +190,7 @@ void i2c_init(int speed, int slaveaddr)
iip->iic_rpbase = 0;
#endif
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = iip->iic_rbase;
if (dpaddr == 0) {
/* need to allocate dual port ram */
dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
(NUM_TX_BDS * sizeof(I2C_BD)) +
MAX_TX_SPACE, 8);
}
#else
dpaddr = CPM_I2C_BASE;
#endif
/*
* initialise data in dual port ram:

10
arch/powerpc/cpu/mpc8xx/scc.c
View file

@ -199,14 +199,8 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
rxIdx = 0;
txIdx = 0;
if (!rtx) {
#ifdef CONFIG_SYS_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif
}
if (!rtx)
rtx = (RTXBD *)(immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
/* Configure port A pins for Txd and Rxd.

17
arch/powerpc/cpu/mpc8xx/serial.c
View file

@ -176,15 +176,7 @@ static int smc_init (void)
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
/* allocate
* size of struct serialbuffer with bd rx/tx, buffer rx/tx and rx index
*/
dpaddr = dpram_alloc_align((sizeof(serialbuffer_t)), 8);
#else
dpaddr = CPM_SERIAL_BASE ;
#endif
dpaddr = CPM_SERIAL_BASE;
rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
/* Allocate space for two buffer descriptors in the DP ram.
@ -421,12 +413,7 @@ static int scc_init (void)
#endif
/* Allocate space for two buffer descriptors in the DP ram. */
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_SERIAL2_BASE ;
#endif
dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8);
/* Enable SDMA. */
im->im_siu_conf.sc_sdcr = 0x0001;

7
arch/powerpc/cpu/mpc8xx/spi.c
View file

@ -187,14 +187,7 @@ void spi_init_f (void)
spi->spi_tbc = 0;
spi->spi_txtmp = 0;
/* Allocate space for one transmit and one receive buffer
* descriptor in the DP ram
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2, 8);
#else
dpaddr = CPM_SPI_BASE;
#endif
/* 3 */
/* Set up the SPI parameters in the parameter ram */

2
arch/powerpc/include/asm/global_data.h
View file

@ -96,7 +96,7 @@ struct arch_global_data {
unsigned long arbiter_event_attributes;
unsigned long arbiter_event_address;
#endif
#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
#if defined(CONFIG_CPM2)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif

5
common/board_f.c
View file

@ -884,11 +884,6 @@ static init_fnc_t init_sequence_f[] = {
defined(CONFIG_SH) || defined(CONFIG_SPARC)
timer_init, /* initialize timer */
#endif
#ifdef CONFIG_SYS_ALLOC_DPRAM
#if !defined(CONFIG_CPM2)
dpram_init,
#endif
#endif
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
#endif

16
include/commproc.h
View file

@ -51,20 +51,6 @@
/*
* DPRAM defines and allocation functions
*/
/* The dual ported RAM is multi-functional. Some areas can be (and are
* being) used for microcode. There is an area that can only be used
* as data ram for buffer descriptors, which is all we use right now.
* Currently the first 512 and last 256 bytes are used for microcode.
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
#define CPM_DATAONLY_BASE ((uint)0x0800)
#define CPM_DATAONLY_SIZE ((uint)0x0700)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#else
#define CPM_SERIAL_BASE 0x0800
#define CPM_I2C_BASE 0x0820
#define CPM_SPI_BASE 0x0840
@ -74,8 +60,6 @@
#define CPM_POST_BASE 0x0980
#define CPM_WLKBD_BASE 0x0a00
#endif
#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
#define CPM_POST_WORD_ADDR 0x07FC
#else

5
post/cpu/mpc8xx/ether.c
View file

@ -119,12 +119,7 @@ static void scc_init (int scc_index)
rxIdx = 0;
txIdx = 0;
#ifdef CONFIG_SYS_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif
#if 0

13
post/cpu/mpc8xx/uart.c
View file

@ -103,12 +103,7 @@ static void smc_init (int smc_index)
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
#else
dpaddr = CPM_POST_BASE;
#endif
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
@ -276,15 +271,7 @@ static void scc_init (int scc_index)
*/
sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/* Allocate space for two buffer descriptors in the DP ram.
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
#else
dpaddr = CPM_POST_BASE;
#endif
/* Enable SDMA.
*/

1
scripts/config_whitelist.txt
View file

@ -3162,7 +3162,6 @@ CONFIG_SYS_ACR_RPTCNT
CONFIG_SYS_ADDRESS_MAP_A
CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_AHB_BASE
CONFIG_SYS_ALLOC_DPRAM
CONFIG_SYS_ALT_BOOT
CONFIG_SYS_ALT_FLASH
CONFIG_SYS_ALT_MEMTEST