Add support for VirtLab2 board
(needed because of differences in the PCMCIA hardware).
This commit is contained in:
Wolfgang Denk
parent
977b50f868
commit
8cba090c58
6 changed files with 643 additions and 5 deletions
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@ -2,6 +2,9 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Add support for VirtLab2 board
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(needed because of differences in the PCMCIA hardware).
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* Minor cleanup.
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* Update yosemite configuration to enable flash write buffer support
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3
Makefile
3
Makefile
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@ -756,7 +756,8 @@ TQM850M_config \
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TQM855M_config \
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TQM860M_config \
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TQM862M_config \
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TQM866M_config: unconfig
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TQM866M_config \
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virtlab2_config: unconfig
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@ >include/config.h
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@[ -z "$(findstring _LCD,$@)" ] || \
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{ echo "#define CONFIG_LCD" >>include/config.h ; \
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2000-2004
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -124,6 +124,9 @@ int checkboard (void)
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break;
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putc (*s);
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}
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#ifdef CONFIG_VIRTLAB2
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puts (" (Virtlab2)");
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#endif
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putc ('\n');
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return (0);
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2000-2004
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -718,7 +718,8 @@ static int hardware_disable(int slot)
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/* SC8xx Boards by SinoVee Microsystems */
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/* -------------------------------------------------------------------- */
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#if defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
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#if (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)) \
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&& !defined(CONFIG_VIRTLAB2)
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#if defined(CONFIG_TQM8xxL)
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#define PCMCIA_BOARD_MSG "TQM8xxL"
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@ -1021,6 +1022,174 @@ done:
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#endif /* TQM8xxL */
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/* -------------------------------------------------------------------- */
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/* Virtlab2 Board by TQ Components */
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/* -------------------------------------------------------------------- */
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#if defined(CONFIG_VIRTLAB2)
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#define PCMCIA_BOARD_MSG "Virtlab2"
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static int hardware_enable(int slot)
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{
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volatile pcmconf8xx_t *pcmp =
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(pcmconf8xx_t *)&(((immap_t *)CFG_IMMR)->im_pcmcia);
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volatile unsigned char *powerctl =
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(volatile unsigned char *)PCMCIA_CTRL;
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unsigned int reg, mask;
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debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
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udelay(10000);
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/* clear interrupt state, and disable interrupts */
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pcmp->pcmc_pscr = PCMCIA_MASK(slot);
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pcmp->pcmc_per &= ~PCMCIA_MASK(slot);
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/*
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* Disable interrupts, DMA, and PCMCIA buffers
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* (isolate the interface) and assert RESET signal
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*/
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = __MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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/* remove all power */
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*powerctl = 0;
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/*
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* Make sure there is a card in the slot, then configure the interface.
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*/
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udelay(10000);
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debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__,
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&(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
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if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
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printf (" No Card found\n");
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return (1);
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}
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/*
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* Power On.
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*/
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mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
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reg = pcmp->pcmc_pipr;
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debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n", reg,
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(reg&PCMCIA_VS1(slot))?"n":"ff",
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(reg&PCMCIA_VS2(slot))?"n":"ff");
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if ((reg & mask) == mask) {
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*powerctl = 2; /* Enable 5V Vccout */
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puts (" 5.0V card found: ");
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} else {
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*powerctl = 1; /* Enable 3.3 V Vccout */
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puts (" 3.3V card found: ");
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}
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udelay(1000);
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debug ("Enable PCMCIA buffers and stop RESET\n");
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reg = PCMCIA_PGCRX(slot);
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reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(slot) = reg;
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udelay(250000); /* some cards need >150 ms to come up :-( */
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debug ("# hardware_enable done\n");
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return (0);
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}
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
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static int hardware_disable(int slot)
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{
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volatile unsigned char *powerctl =
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(volatile unsigned char *)PCMCIA_CTRL;
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unsigned long reg;
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debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
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/* remove all power */
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*powerctl = 0;
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = __MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(slot) = reg;
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udelay(10000);
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return (0);
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}
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#endif
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static int voltage_set(int slot, int vcc, int vpp)
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{
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volatile pcmconf8xx_t *pcmp =
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(pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
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volatile unsigned char *powerctl =
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(volatile unsigned char *)PCMCIA_CTRL;
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unsigned long reg;
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debug ("voltage_set: " PCMCIA_BOARD_MSG
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" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
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'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
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/*
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* Disable PCMCIA buffers (isolate the interface)
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* and assert RESET signal
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*/
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debug ("Disable PCMCIA buffers and assert RESET\n");
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reg = PCMCIA_PGCRX(slot);
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reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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/*
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* Configure pins for 5 Volts Enable and 3 Volts enable,
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* Turn off all power.
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*/
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debug ("PCMCIA power OFF\n");
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reg = 0;
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switch(vcc) {
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case 0: break;
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case 33: reg = 0x0001; break;
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case 50: reg = 0x0002; break;
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default: goto done;
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}
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/* Checking supported voltages */
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debug ("PIPR: 0x%x --> %s\n", pcmp->pcmc_pipr,
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(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
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*powerctl = reg;
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if (reg) {
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debug ("PCMCIA powered at %sV\n", (reg&0x0004) ? "5.0" : "3.3");
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} else {
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debug ("PCMCIA powered down\n");
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}
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done:
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debug ("Enable PCMCIA buffers and stop RESET\n");
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reg = PCMCIA_PGCRX(slot);
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reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
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reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
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PCMCIA_PGCRX(slot) = reg;
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udelay(500);
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debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
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return (0);
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}
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#endif /* CONFIG_VIRTLAB2 */
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/* -------------------------------------------------------------------- */
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/* LWMON Board */
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@ -2,7 +2,7 @@
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* MPC8xx Communication Processor Module.
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
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*
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* (C) Copyright 2000-2004
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This file contains structures and information for the communication
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@ -1412,6 +1412,7 @@ typedef struct scc_enet {
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defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
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defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
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defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
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defined(CONFIG_VIRTLAB2)|| \
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(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC2 use.
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461
include/configs/virtlab2.h
Normal file
461
include/configs/virtlab2.h
Normal file
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@ -0,0 +1,461 @@
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/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
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#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
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#define CONFIG_TQM8xxL 1
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#ifdef CONFIG_LCD /* with LCD controller ? */
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#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
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#endif
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
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#define CONFIG_BOOTCOUNT_LIMIT
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_BOARD_TYPES 1 /* support board types */
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#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"flash_nfs=run nfsargs addip;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"bootfile=/tftpboot/TQM823L/uImage\0" \
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"kernel_addr=40040000\0" \
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"ramdisk_addr=40100000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#if defined(CONFIG_LCD)
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# undef CONFIG_STATUS_LED /* disturbs display */
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#else
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# define CONFIG_STATUS_LED 1 /* Status LED enabled */
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#endif /* CONFIG_LCD */
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#ifdef CONFIG_SPLASH_SCREEN
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# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_BMP | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_IDE | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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#else
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# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_IDE | \
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CFG_CMD_NFS | \
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CFG_CMD_SNTP )
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#endif
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if 0
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#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
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#endif
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFFF00000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block
|
||||
*/
|
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
|
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
|
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#ifndef CONFIG_CAN_DRIVER
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */
|
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*/
|
||||
#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CFG_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||
|
||||
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
|
||||
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
|
||||
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
|
||||
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
#ifndef CONFIG_CAN_DRIVER
|
||||
#define CFG_OR3_PRELIM CFG_OR2_PRELIM
|
||||
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
|
||||
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
|
||||
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
|
||||
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
|
||||
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
|
||||
BR_PS_8 | BR_MS_UPMB | BR_V )
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*
|
||||
* The Divider for PTA (refresh timer) configuration is based on an
|
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
||||
* the number of chip selects (NCS) and the actually needed refresh
|
||||
* rate is done by setting MPTPR.
|
||||
*
|
||||
* PTA is calculated from
|
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock!)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
* --------------------------------------------
|
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
||||
*
|
||||
* 50 MHz => 50.000.000 / Divider = 98
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
|
||||
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
|
||||
#define CFG_MAMR_PTA 98
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
* (= 64 ms / 2K = 125 / quad bursts).
|
||||
* For a simpler initialization, 15.6 us is used instead.
|
||||
*
|
||||
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
||||
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
||||
*/
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/* Map peripheral control registers on CS4 */
|
||||
#define CFG_PERIPHERAL_BASE 0xA0000000
|
||||
#define CFG_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
|
||||
#define CFG_OR4_PRELIM (CFG_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK)
|
||||
#define CFG_BR4_PRELIM ((CFG_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||||
#define PCMCIA_CTRL (CFG_PERIPHERAL_BASE + 0xB00)
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue