ARM: IXP: Remove actux4 board
The board is unmaintained, just like the rest of the IXP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Marek Vasut
parent
38da33f3c1
commit
6ff7aafa4b
6 changed files with 1 additions and 375 deletions
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := actux4.o
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@ -1,129 +0,0 @@
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/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <malloc.h>
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#include <asm/arch/ixp425.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#include <asm/arch/ixp425pci.h>
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#endif
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#include "actux4_hw.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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writel(0xbd113c42, IXP425_EXP_CS1);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x00000100;
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_nPWRON);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_nPWRON);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
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/* led not populated on board*/
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED3);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED3);
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/* middle LED */
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED2);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED2);
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/* right LED */
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/* weak pulldown = LED weak on */
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_LED1);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_LED1);
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/* Setup GPIO's for Interrupt inputs */
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTA);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTB);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_USBINTC);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RTCINT);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
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GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTA);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTB);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_USBINTC);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RTCINT);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
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GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
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/* Setup GPIO's for 33MHz clock output */
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writel(0x011001FF, IXP425_GPIO_GPCLKR);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
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GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
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udelay(10000);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
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udelay(10000);
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GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
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udelay(10000);
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GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
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return 0;
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}
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/* Check Board Identity */
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int checkboard(void)
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{
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puts("Board: AcTux-4\n");
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
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return 0;
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}
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#ifdef CONFIG_PCI
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struct pci_controller hose;
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void pci_init_board(void)
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{
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pci_ixp_init(&hose);
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}
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#endif
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/*
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* Hardcoded flash setup:
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* Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus.
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* Flash 1 is an Intel *16 flash using the CFI driver.
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*/
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = 1;
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info->chipwidth = 1;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else
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return 0;
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}
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@ -1,33 +0,0 @@
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/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* hardware register definitions for the AcTux-4 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ACTUX4_HW_H
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#define _ACTUX4_HW_H
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPIO_USBINTA 0
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#define CONFIG_SYS_GPIO_USBINTB 1
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#define CONFIG_SYS_GPIO_USBINTC 2
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#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */
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#define CONFIG_SYS_GPIO_I2C_SCL 4
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#define CONFIG_SYS_GPIO_I2C_SDA 5
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#define CONFIG_SYS_GPIO_PCI_INTB 6
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#define CONFIG_SYS_GPIO_BUTTON1 7
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#define CONFIG_SYS_GPIO_LED1 8 /* Out */
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#define CONFIG_SYS_GPIO_RTCINT 9
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#define CONFIG_SYS_GPIO_LED2 10 /* Out */
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#define CONFIG_SYS_GPIO_PCI_INTA 11
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#define CONFIG_SYS_GPIO_IORST 12 /* Out */
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#define CONFIG_SYS_GPIO_LED3 13 /* Out */
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#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */
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#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */
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#endif
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@ -377,7 +377,6 @@ Active arm armv7:arm720t tegra20 toradex colibri_t20_iris
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Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
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Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
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Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
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Active arm ixp - - - actux4 - Michael Schwingen <michael@schwingen.org>
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Active arm ixp - - - dvlhost - Michael Schwingen <michael@schwingen.org>
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Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
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Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
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@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
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Board Arch CPU Commit Removed Last known maintainer/contact
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=================================================================================================
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actux4 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
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actux3 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
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actux2 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
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actux1 arm ixp - 2014-01-28 Michael Schwingen <michael@schwingen.org>
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@ -1,204 +0,0 @@
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/*
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* (C) Copyright 2007
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* Michael Schwingen, michael@schwingen.org
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*
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* Configuration settings for the AcTux-4 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_IXP425 1
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#define CONFIG_ACTUX4 1
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#define CONFIG_MACH_TYPE 1532
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#define CONFIG_DISPLAY_CPUINFO 1
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_IXP_SERIAL
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOARD_EARLY_INIT_F 1
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/***************************************************************
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* U-boot generic defines start here.
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***************************************************************/
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Command line configuration */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_PCI
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_IXP_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI_ENUM
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#endif
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#define CONFIG_BOOTCOMMAND "run boot_flash"
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_KGDB_BAUDRATE 230400
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00400000
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#define CONFIG_SYS_MEMTEST_END 0x00800000
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/* timer clock - 2* OSC_IN system clock */
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#define CONFIG_IXP425_TIMER_CLK 66000000
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
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115200, 230400 }
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#define CONFIG_SERIAL_RTS_ACTIVE 1
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/* Expansion bus settings */
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#define CONFIG_SYS_EXP_CS0 0xbd113003
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/* SDRAM settings */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 0x00000000
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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/* 32MB SDRAM */
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#define CONFIG_SYS_SDR_CONFIG 0x18
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#define PHYS_SDRAM_1_SIZE 0x02000000
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#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
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#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
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#define CONFIG_SYS_DRAM_SIZE 0x02000000
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/* FLASH organization */
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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/* max # of sectors per chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 70
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#define PHYS_FLASH_1 0x50000000
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#define PHYS_FLASH_2 0x51000000
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_MONITOR_LEN (252 << 10)
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#define CONFIG_BOARD_SIZE_LIMIT 258048
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/* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* board provides its own flash_init code */
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#define CONFIG_FLASH_CFI_LEGACY 1
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/* no byte writes on IXP4xx */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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/* SST 39VF020 etc. support */
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#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1
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/* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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/* Ethernet */
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/* include IXP4xx NPE support */
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#define CONFIG_IXP4XX_NPE 1
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/* NPE0 PHY address */
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#define CONFIG_PHY_ADDR 0x1C
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/* MII PHY management */
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#define CONFIG_MII 1
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/* Number of ethernet rx buffers & descriptors */
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#undef CONFIG_CMD_NFS
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/* BOOTP options */
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/* environment organization: one complete 4k flash sector */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x1000
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#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"npe_ucode=51000000\0" \
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"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \
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"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \
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"kerneladdr=51020000\0" \
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"kernelfile=actux4/uImage\0" \
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"rootfile=actux4/rootfs\0" \
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"rootaddr=51160000\0" \
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"loadaddr=10000\0" \
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"updateboot_ser=mw.b 10000 ff 40000;" \
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" loady ${loadaddr};" \
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" run eraseboot writeboot\0" \
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"updateboot_net=mw.b 10000 ff 40000;" \
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" tftp ${loadaddr} actux4/u-boot.bin;" \
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" run eraseboot writeboot\0" \
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"eraseboot=protect off 50000000 5003efff;" \
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" erase 50000000 +${filesize}\0" \
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"writeboot=cp.b 10000 50000000 ${filesize}\0" \
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"updateucode=loady;" \
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" era ${npe_ucode} +${filesize};" \
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" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
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"updateroot=tftp ${loadaddr} ${rootfile};" \
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" era ${rootaddr} +${filesize};" \
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" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
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"updatekern=tftp ${loadaddr} ${kernelfile};" \
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" era ${kerneladdr} +${filesize};" \
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" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
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"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
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" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
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"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
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"boot_flash=run flashargs addtty addeth;" \
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" bootm ${kerneladdr}\0" \
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"boot_net=run netargs addtty addeth;" \
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" tftpboot ${loadaddr} ${kernelfile};" \
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" bootm\0"
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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