arm: stm32mp: move code for STM32MP15x
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c when low level init without TFABOOT is supported. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay
parent
3865a7ec95
commit
6df271a70f
6 changed files with 377 additions and 324 deletions
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@ -8,6 +8,8 @@ obj-y += dram_init.o
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obj-y += syscon.o
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obj-y += bsec.o
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obj-$(CONFIG_STM32MP15x) += stm32mp15x.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-y += tzc400.o
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@ -16,7 +16,6 @@
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#include <misc.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/arch/bsec.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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@ -24,67 +23,6 @@
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#include <dm/uclass.h>
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#include <linux/bitops.h>
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/* RCC register */
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#define RCC_TZCR (STM32_RCC_BASE + 0x00)
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#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
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#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
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#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
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#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
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#define RCC_BDCR_VSWRST BIT(31)
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#define RCC_BDCR_RTCSRC GENMASK(17, 16)
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#define RCC_DBGCFGR_DBGCKEN BIT(8)
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/* Security register */
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#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
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#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
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#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
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#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
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#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
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#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
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#define PWR_CR1 (STM32_PWR_BASE + 0x00)
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#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
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#define PWR_CR1_DBP BIT(8)
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#define PWR_MCUCR_SBF BIT(6)
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/* DBGMCU register */
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#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
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#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
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#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
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#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
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#define DBGMCU_IDC_DEV_ID_SHIFT 0
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#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
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#define DBGMCU_IDC_REV_ID_SHIFT 16
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/* GPIOZ registers */
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#define GPIOZ_SECCFGR 0x54004030
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/* boot interface from Bootrom
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* - boot instance = bit 31:16
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* - boot device = bit 15:0
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*/
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#define BOOTROM_PARAM_ADDR 0x2FFC0078
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#define BOOTROM_MODE_MASK GENMASK(15, 0)
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#define BOOTROM_MODE_SHIFT 0
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#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
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#define BOOTROM_INSTANCE_SHIFT 16
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/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
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#define RPN_SHIFT 0
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#define RPN_MASK GENMASK(7, 0)
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/* Package = bit 27:29 of OTP16
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* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
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* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
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* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
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* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
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* - others: Reserved
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*/
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#define PKG_SHIFT 27
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#define PKG_MASK GENMASK(2, 0)
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/*
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* early TLB into the .data section so that it not get cleared
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* with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
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@ -93,121 +31,6 @@ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
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struct lmb lmb;
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static void security_init(void)
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{
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/* Disable the backup domain write protection */
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/* the protection is enable at each reset by hardware */
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/* And must be disable by software */
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setbits_le32(PWR_CR1, PWR_CR1_DBP);
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while (!(readl(PWR_CR1) & PWR_CR1_DBP))
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;
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/* If RTC clock isn't enable so this is a cold boot then we need
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* to reset the backup domain
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*/
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if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
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setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
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;
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clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
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}
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/* allow non secure access in Write/Read for all peripheral */
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writel(GENMASK(25, 0), ETZPC_DECPROT0);
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/* Open SYSRAM for no secure access */
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writel(0x0, ETZPC_TZMA1_SIZE);
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/* enable TZC1 TZC2 clock */
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writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
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/* Region 0 set to no access by default */
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/* bit 0 / 16 => nsaid0 read/write Enable
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* bit 1 / 17 => nsaid1 read/write Enable
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* ...
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* bit 15 / 31 => nsaid15 read/write Enable
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*/
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writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
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/* bit 30 / 31 => Secure Global Enable : write/read */
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/* bit 0 / 1 => Region Enable for filter 0/1 */
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writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
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/* Enable Filter 0 and 1 */
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setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
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/* RCC trust zone deactivated */
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writel(0x0, RCC_TZCR);
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/* TAMP: deactivate the internal tamper
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* Bit 23 ITAMP8E: monotonic counter overflow
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* Bit 20 ITAMP5E: RTC calendar overflow
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* Bit 19 ITAMP4E: HSE monitoring
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* Bit 18 ITAMP3E: LSE monitoring
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* Bit 16 ITAMP1E: RTC power domain supply monitoring
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*/
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writel(0x0, TAMP_CR1);
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/* GPIOZ: deactivate the security */
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writel(BIT(0), RCC_MP_AHB5ENSETR);
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writel(0x0, GPIOZ_SECCFGR);
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}
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/*
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* Debug init
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*/
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static void dbgmcu_init(void)
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{
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/*
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* Freeze IWDG2 if Cortex-A7 is in debug mode
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* done in TF-A for TRUSTED boot and
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* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
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*/
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if (bsec_dbgswenable()) {
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
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}
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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int ret;
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dbgmcu_init();
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/* force probe of BSEC driver to shadow the upper OTP */
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ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
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if (ret)
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log_warning("BSEC probe failed: %d\n", ret);
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}
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/* get bootmode from ROM code boot context: saved in TAMP register */
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static void update_bootmode(void)
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{
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u32 boot_mode;
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u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
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u32 bootrom_device, bootrom_instance;
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/* enable TAMP clock = RTCAPBEN */
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writel(BIT(8), RCC_MP_APB5ENSETR);
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/* read bootrom context */
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bootrom_device =
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(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
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bootrom_instance =
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(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
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boot_mode =
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((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
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((bootrom_instance << BOOT_INSTANCE_SHIFT) &
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BOOT_INSTANCE_MASK);
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/* save the boot mode in TAMP backup register */
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clrsetbits_le32(TAMP_BOOT_CONTEXT,
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TAMP_BOOT_MODE_MASK,
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boot_mode << TAMP_BOOT_MODE_SHIFT);
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}
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u32 get_bootmode(void)
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{
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/* read bootmode from TAMP backup register */
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@ -277,25 +100,24 @@ static void early_enable_caches(void)
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*/
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int arch_cpu_init(void)
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{
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u32 boot_mode;
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early_enable_caches();
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/* early armv7 timer init: needed for polling */
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timer_init();
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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security_init();
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update_bootmode();
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}
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/* reset copro state in SPL, when used, or in U-Boot */
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if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
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/* Reset Coprocessor state unless it wakes up from Standby power mode */
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if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
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writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
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writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
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}
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}
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return 0;
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}
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/* weak function for SOC specific initialization */
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__weak void stm32mp_cpu_init(void)
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{
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}
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int mach_cpu_init(void)
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{
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u32 boot_mode;
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stm32mp_cpu_init();
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boot_mode = get_bootmode();
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@ -324,122 +146,6 @@ void enable_caches(void)
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dcache_enable();
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}
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static u32 read_idc(void)
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{
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/* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
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if (bsec_dbgswenable()) {
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setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
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return readl(DBGMCU_IDC);
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}
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if (CONFIG_IS_ENABLED(STM32MP15x))
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return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
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else
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return 0x0;
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}
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u32 get_cpu_dev(void)
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{
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return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
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}
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u32 get_cpu_rev(void)
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{
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return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
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}
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/* Get Device Part Number (RPN) from OTP */
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static u32 get_cpu_rpn(void)
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{
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return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
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}
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u32 get_cpu_type(void)
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{
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return (get_cpu_dev() << 16) | get_cpu_rpn();
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}
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/* Get Package options from OTP */
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u32 get_cpu_package(void)
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{
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return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
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}
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static const char * const soc_type[] = {
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"????",
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"151C", "151A", "151F", "151D",
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"153C", "153A", "153F", "153D",
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"157C", "157A", "157F", "157D"
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};
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static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
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static const char * const soc_rev[] = { "?", "A", "B", "Z" };
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static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
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unsigned int *rev)
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{
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u32 cpu_type = get_cpu_type();
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u32 ct = cpu_type & ~(BIT(7) | BIT(0));
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u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
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u32 cp = get_cpu_package();
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/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
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switch (ct) {
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case CPU_STM32MP151Cxx:
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*type = cm + 1;
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break;
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case CPU_STM32MP153Cxx:
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*type = cm + 5;
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break;
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case CPU_STM32MP157Cxx:
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*type = cm + 9;
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break;
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default:
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*type = 0;
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break;
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}
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/* Package */
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switch (cp) {
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case PKG_AA_LBGA448:
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case PKG_AB_LBGA354:
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case PKG_AC_TFBGA361:
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case PKG_AD_TFBGA257:
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*pkg = cp;
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break;
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default:
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*pkg = 0;
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break;
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}
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/* Revision */
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switch (get_cpu_rev()) {
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case CPU_REV1:
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*rev = 1;
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break;
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case CPU_REV2:
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*rev = 2;
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break;
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case CPU_REV2_1:
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*rev = 3;
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break;
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default:
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*rev = 0;
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break;
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}
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}
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void get_soc_name(char name[SOC_NAME_SIZE])
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{
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unsigned int type, pkg, rev;
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get_cpu_string_offsets(&type, &pkg, &rev);
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snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
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soc_type[type], soc_pkg[pkg], soc_rev[rev]);
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}
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/* used when CONFIG_DISPLAY_CPUINFO is activated */
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int print_cpuinfo(void)
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{
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@ -645,15 +351,8 @@ static int setup_serial_number(void)
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return 0;
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}
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static void setup_soc_type_pkg_rev(void)
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__weak void stm32mp_misc_init(void)
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{
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unsigned int type, pkg, rev;
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get_cpu_string_offsets(&type, &pkg, &rev);
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env_set("soc_type", soc_type[type]);
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env_set("soc_pkg", soc_pkg[pkg]);
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env_set("soc_rev", soc_rev[rev]);
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}
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int arch_misc_init(void)
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@ -661,7 +360,7 @@ int arch_misc_init(void)
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setup_boot_mode();
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setup_mac_address();
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setup_serial_number();
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setup_soc_type_pkg_rev();
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stm32mp_misc_init();
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return 0;
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}
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@ -312,16 +312,16 @@ int ft_system_setup(void *blob, struct bd_info *bd)
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}
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switch (get_cpu_package()) {
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case PKG_AA_LBGA448:
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case STM32MP15_PKG_AA_LBGA448:
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pkg = STM32MP_PKG_AA;
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break;
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case PKG_AB_LBGA354:
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case STM32MP15_PKG_AB_LBGA354:
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pkg = STM32MP_PKG_AB;
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break;
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case PKG_AC_TFBGA361:
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case STM32MP15_PKG_AC_TFBGA361:
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pkg = STM32MP_PKG_AC;
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break;
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case PKG_AD_TFBGA257:
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case STM32MP15_PKG_AD_TFBGA257:
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pkg = STM32MP_PKG_AD;
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break;
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default:
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@ -36,10 +36,12 @@ u32 get_cpu_rev(void);
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/* Get Package options from OTP */
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u32 get_cpu_package(void);
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#define PKG_AA_LBGA448 4
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#define PKG_AB_LBGA354 3
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#define PKG_AC_TFBGA361 2
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#define PKG_AD_TFBGA257 1
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/* package used for STM32MP15x */
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#define STM32MP15_PKG_AA_LBGA448 4
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#define STM32MP15_PKG_AB_LBGA354 3
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#define STM32MP15_PKG_AC_TFBGA361 2
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#define STM32MP15_PKG_AD_TFBGA257 1
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#define STM32MP15_PKG_UNKNOWN 0
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/* Get SOC name */
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#define SOC_NAME_SIZE 20
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@ -53,5 +55,9 @@ int setup_mac_address(void);
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/* board power management : configure vddcore according OPP */
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void board_vddcore_init(u32 voltage_mv);
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/* weak function */
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void stm32mp_cpu_init(void);
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void stm32mp_misc_init(void);
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/* helper function: read data from OTP */
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u32 get_otp(int index, int shift, int mask);
|
||||
|
|
|
|||
|
|
@ -190,6 +190,7 @@ void board_init_f(ulong dummy)
|
|||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
mach_cpu_init();
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
|
|
|
|||
345
arch/arm/mach-stm32mp/stm32mp15x.c
Normal file
345
arch/arm/mach-stm32mp/stm32mp15x.c
Normal file
|
|
@ -0,0 +1,345 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <log.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/bsec.h>
|
||||
#include <asm/arch/stm32.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass.h>
|
||||
|
||||
/* RCC register */
|
||||
#define RCC_TZCR (STM32_RCC_BASE + 0x00)
|
||||
#define RCC_BDCR (STM32_RCC_BASE + 0x0140)
|
||||
#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
|
||||
#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
|
||||
#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
|
||||
|
||||
#define RCC_BDCR_VSWRST BIT(31)
|
||||
#define RCC_BDCR_RTCSRC GENMASK(17, 16)
|
||||
|
||||
#define RCC_DBGCFGR_DBGCKEN BIT(8)
|
||||
|
||||
/* DBGMCU register */
|
||||
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
|
||||
#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
|
||||
#define DBGMCU_APB4FZ1_IWDG2 BIT(2)
|
||||
|
||||
/* Security register */
|
||||
#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
|
||||
#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
|
||||
|
||||
#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
|
||||
#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
|
||||
#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
|
||||
|
||||
#define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
|
||||
|
||||
#define PWR_CR1 (STM32_PWR_BASE + 0x00)
|
||||
#define PWR_MCUCR (STM32_PWR_BASE + 0x14)
|
||||
#define PWR_CR1_DBP BIT(8)
|
||||
#define PWR_MCUCR_SBF BIT(6)
|
||||
|
||||
/* GPIOZ registers */
|
||||
#define GPIOZ_SECCFGR 0x54004030
|
||||
|
||||
/* DBGMCU register */
|
||||
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
|
||||
#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
|
||||
#define DBGMCU_IDC_DEV_ID_SHIFT 0
|
||||
#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
|
||||
#define DBGMCU_IDC_REV_ID_SHIFT 16
|
||||
|
||||
/* boot interface from Bootrom
|
||||
* - boot instance = bit 31:16
|
||||
* - boot device = bit 15:0
|
||||
*/
|
||||
#define BOOTROM_PARAM_ADDR 0x2FFC0078
|
||||
#define BOOTROM_MODE_MASK GENMASK(15, 0)
|
||||
#define BOOTROM_MODE_SHIFT 0
|
||||
#define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
|
||||
#define BOOTROM_INSTANCE_SHIFT 16
|
||||
|
||||
/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
|
||||
#define RPN_SHIFT 0
|
||||
#define RPN_MASK GENMASK(7, 0)
|
||||
|
||||
/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines
|
||||
* - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
|
||||
* - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
|
||||
* - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
|
||||
* - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
|
||||
* - others: Reserved
|
||||
*/
|
||||
#define PKG_SHIFT 27
|
||||
#define PKG_MASK GENMASK(2, 0)
|
||||
|
||||
static void security_init(void)
|
||||
{
|
||||
/* Disable the backup domain write protection */
|
||||
/* the protection is enable at each reset by hardware */
|
||||
/* And must be disable by software */
|
||||
setbits_le32(PWR_CR1, PWR_CR1_DBP);
|
||||
|
||||
while (!(readl(PWR_CR1) & PWR_CR1_DBP))
|
||||
;
|
||||
|
||||
/* If RTC clock isn't enable so this is a cold boot then we need
|
||||
* to reset the backup domain
|
||||
*/
|
||||
if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
|
||||
setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
||||
while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
|
||||
;
|
||||
clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
|
||||
}
|
||||
|
||||
/* allow non secure access in Write/Read for all peripheral */
|
||||
writel(GENMASK(25, 0), ETZPC_DECPROT0);
|
||||
|
||||
/* Open SYSRAM for no secure access */
|
||||
writel(0x0, ETZPC_TZMA1_SIZE);
|
||||
|
||||
/* enable TZC1 TZC2 clock */
|
||||
writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
|
||||
|
||||
/* Region 0 set to no access by default */
|
||||
/* bit 0 / 16 => nsaid0 read/write Enable
|
||||
* bit 1 / 17 => nsaid1 read/write Enable
|
||||
* ...
|
||||
* bit 15 / 31 => nsaid15 read/write Enable
|
||||
*/
|
||||
writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
|
||||
/* bit 30 / 31 => Secure Global Enable : write/read */
|
||||
/* bit 0 / 1 => Region Enable for filter 0/1 */
|
||||
writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
|
||||
|
||||
/* Enable Filter 0 and 1 */
|
||||
setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
|
||||
|
||||
/* RCC trust zone deactivated */
|
||||
writel(0x0, RCC_TZCR);
|
||||
|
||||
/* TAMP: deactivate the internal tamper
|
||||
* Bit 23 ITAMP8E: monotonic counter overflow
|
||||
* Bit 20 ITAMP5E: RTC calendar overflow
|
||||
* Bit 19 ITAMP4E: HSE monitoring
|
||||
* Bit 18 ITAMP3E: LSE monitoring
|
||||
* Bit 16 ITAMP1E: RTC power domain supply monitoring
|
||||
*/
|
||||
writel(0x0, TAMP_CR1);
|
||||
|
||||
/* GPIOZ: deactivate the security */
|
||||
writel(BIT(0), RCC_MP_AHB5ENSETR);
|
||||
writel(0x0, GPIOZ_SECCFGR);
|
||||
}
|
||||
|
||||
/*
|
||||
* Debug init
|
||||
*/
|
||||
void dbgmcu_init(void)
|
||||
{
|
||||
/*
|
||||
* Freeze IWDG2 if Cortex-A7 is in debug mode
|
||||
* done in TF-A for TRUSTED boot and
|
||||
* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
|
||||
*/
|
||||
if (bsec_dbgswenable()) {
|
||||
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
||||
setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
|
||||
}
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
dbgmcu_init();
|
||||
|
||||
/* force probe of BSEC driver to shadow the upper OTP */
|
||||
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev);
|
||||
if (ret)
|
||||
log_warning("BSEC probe failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/* get bootmode from ROM code boot context: saved in TAMP register */
|
||||
static void update_bootmode(void)
|
||||
{
|
||||
u32 boot_mode;
|
||||
u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
|
||||
u32 bootrom_device, bootrom_instance;
|
||||
|
||||
/* enable TAMP clock = RTCAPBEN */
|
||||
writel(BIT(8), RCC_MP_APB5ENSETR);
|
||||
|
||||
/* read bootrom context */
|
||||
bootrom_device =
|
||||
(bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
|
||||
bootrom_instance =
|
||||
(bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
|
||||
boot_mode =
|
||||
((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
|
||||
((bootrom_instance << BOOT_INSTANCE_SHIFT) &
|
||||
BOOT_INSTANCE_MASK);
|
||||
|
||||
/* save the boot mode in TAMP backup register */
|
||||
clrsetbits_le32(TAMP_BOOT_CONTEXT,
|
||||
TAMP_BOOT_MODE_MASK,
|
||||
boot_mode << TAMP_BOOT_MODE_SHIFT);
|
||||
}
|
||||
|
||||
/* weak function: STM32MP15x mach init for boot without TFA */
|
||||
void stm32mp_cpu_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
security_init();
|
||||
update_bootmode();
|
||||
}
|
||||
|
||||
/* reset copro state in SPL, when used, or in U-Boot */
|
||||
if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
|
||||
/* Reset Coprocessor state unless it wakes up from Standby power mode */
|
||||
if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
|
||||
writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
|
||||
writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static u32 read_idc(void)
|
||||
{
|
||||
/* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
|
||||
if (bsec_dbgswenable()) {
|
||||
setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
|
||||
|
||||
return readl(DBGMCU_IDC);
|
||||
}
|
||||
|
||||
return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
|
||||
}
|
||||
|
||||
u32 get_cpu_dev(void)
|
||||
{
|
||||
return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
|
||||
}
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
|
||||
}
|
||||
|
||||
/* Get Device Part Number (RPN) from OTP */
|
||||
static u32 get_cpu_rpn(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
|
||||
}
|
||||
|
||||
u32 get_cpu_type(void)
|
||||
{
|
||||
return (get_cpu_dev() << 16) | get_cpu_rpn();
|
||||
}
|
||||
|
||||
/* Get Package options from OTP */
|
||||
u32 get_cpu_package(void)
|
||||
{
|
||||
return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
|
||||
}
|
||||
|
||||
static const char * const soc_type[] = {
|
||||
"????",
|
||||
"151C", "151A", "151F", "151D",
|
||||
"153C", "153A", "153F", "153D",
|
||||
"157C", "157A", "157F", "157D"
|
||||
};
|
||||
|
||||
static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
|
||||
static const char * const soc_rev[] = { "?", "A", "B", "Z" };
|
||||
|
||||
static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
|
||||
unsigned int *rev)
|
||||
{
|
||||
u32 cpu_type = get_cpu_type();
|
||||
u32 ct = cpu_type & ~(BIT(7) | BIT(0));
|
||||
u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
|
||||
u32 cp = get_cpu_package();
|
||||
|
||||
/* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
|
||||
switch (ct) {
|
||||
case CPU_STM32MP151Cxx:
|
||||
*type = cm + 1;
|
||||
break;
|
||||
case CPU_STM32MP153Cxx:
|
||||
*type = cm + 5;
|
||||
break;
|
||||
case CPU_STM32MP157Cxx:
|
||||
*type = cm + 9;
|
||||
break;
|
||||
default:
|
||||
*type = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Package */
|
||||
switch (cp) {
|
||||
case STM32MP15_PKG_AA_LBGA448:
|
||||
case STM32MP15_PKG_AB_LBGA354:
|
||||
case STM32MP15_PKG_AC_TFBGA361:
|
||||
case STM32MP15_PKG_AD_TFBGA257:
|
||||
*pkg = cp;
|
||||
break;
|
||||
default:
|
||||
*pkg = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Revision */
|
||||
switch (get_cpu_rev()) {
|
||||
case CPU_REV1:
|
||||
*rev = 1;
|
||||
break;
|
||||
case CPU_REV2:
|
||||
*rev = 2;
|
||||
break;
|
||||
case CPU_REV2_1:
|
||||
*rev = 3;
|
||||
break;
|
||||
default:
|
||||
*rev = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void get_soc_name(char name[SOC_NAME_SIZE])
|
||||
{
|
||||
unsigned int type, pkg, rev;
|
||||
|
||||
get_cpu_string_offsets(&type, &pkg, &rev);
|
||||
|
||||
snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
|
||||
soc_type[type], soc_pkg[pkg], soc_rev[rev]);
|
||||
}
|
||||
|
||||
static void setup_soc_type_pkg_rev(void)
|
||||
{
|
||||
unsigned int type, pkg, rev;
|
||||
|
||||
get_cpu_string_offsets(&type, &pkg, &rev);
|
||||
|
||||
env_set("soc_type", soc_type[type]);
|
||||
env_set("soc_pkg", soc_pkg[pkg]);
|
||||
env_set("soc_rev", soc_rev[rev]);
|
||||
}
|
||||
|
||||
/* weak function called in arch_misc_init */
|
||||
void stm32mp_misc_init(void)
|
||||
{
|
||||
setup_soc_type_pkg_rev();
|
||||
}
|
||||
Loading…
Reference in a new issue