Merge tag 'u-boot-rockchip-20230519' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
rk3588 driver: - Sync the reset driver with kernel code; - Enable pcie controller and phy support; - Enable USB controller and phy support; Board level dts and config update: - boost eMMC performance for some of rk3399 boards; - boot from SPI NOR flash for rk356x boards; - Other board level updates;
This commit is contained in:
Tom Rini
commit
62df7a3944
35 changed files with 1787 additions and 214 deletions
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@ -12,6 +12,12 @@
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};
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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};
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&vdd_log {
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regulator-init-microvolt = <950000>;
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};
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@ -15,6 +15,11 @@
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};
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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};
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&spi1 {
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spi_flash: flash@0 {
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bootph-all;
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@ -120,6 +120,7 @@
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&sdhci {
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max-frequency = <200000000>;
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bootph-all;
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u-boot,spl-fifo-mode;
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};
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&sdmmc {
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@ -11,6 +11,67 @@
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};
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};
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&emmc_bus8 {
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bootph-all;
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};
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&emmc_clk {
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bootph-all;
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};
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&emmc_cmd {
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bootph-all;
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};
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&emmc_datastrobe {
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bootph-all;
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};
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&pinctrl {
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bootph-all;
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};
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&pcfg_pull_none {
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bootph-all;
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};
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&pcfg_pull_up_drv_level_2 {
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bootph-all;
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};
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&pcfg_pull_up {
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bootph-all;
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};
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&sdmmc0_bus4 {
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bootph-all;
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};
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&sdmmc0_clk {
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bootph-all;
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};
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&sdmmc0_cmd {
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bootph-all;
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};
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&sdmmc0_det {
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bootph-all;
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};
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&sdmmc0_pwren {
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bootph-all;
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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};
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&uart2m0_xfer {
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bootph-all;
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};
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&uart2 {
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clock-frequency = <24000000>;
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bootph-all;
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@ -7,11 +7,67 @@
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#include "rk356x-u-boot.dtsi"
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/ {
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aliases {
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spi0 = &sfc;
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};
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chosen {
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stdout-path = &uart2;
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};
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};
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&emmc_bus8 {
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bootph-all;
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};
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&emmc_clk {
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bootph-all;
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};
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&emmc_cmd {
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bootph-all;
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};
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&emmc_datastrobe {
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bootph-all;
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};
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&fspi_pins {
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bootph-all;
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};
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&pinctrl {
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bootph-all;
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};
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&pcfg_pull_none {
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bootph-all;
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};
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&pcfg_pull_up_drv_level_2 {
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bootph-all;
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};
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&pcfg_pull_up {
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bootph-all;
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};
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&sdmmc0_bus4 {
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bootph-all;
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};
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&sdmmc0_clk {
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bootph-all;
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};
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&sdmmc0_cmd {
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bootph-all;
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};
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&sdmmc0_det {
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bootph-all;
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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@ -20,6 +76,23 @@
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mmc-hs400-enhanced-strobe;
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};
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&sfc {
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bootph-pre-ram;
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u-boot,spl-sfc-no-dma;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash@0 {
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bootph-pre-ram;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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};
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};
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&sdmmc2 {
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status = "disabled";
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};
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@ -28,6 +101,10 @@
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status = "disabled";
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};
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&uart2m0_xfer {
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bootph-all;
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};
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&uart2 {
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clock-frequency = <24000000>;
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bootph-all;
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@ -34,6 +34,11 @@
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};
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};
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&xin24m {
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bootph-all;
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status = "okay";
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};
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&cru {
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bootph-all;
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status = "okay";
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@ -63,3 +68,14 @@
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bootph-pre-ram;
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status = "okay";
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};
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#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
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&binman {
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simple-bin-spi {
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mkimage {
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args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
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offset = <0x8000>;
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};
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};
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};
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#endif
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@ -4,15 +4,99 @@
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*/
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#include "rk3588-u-boot.dtsi"
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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mmc1 = &sdmmc;
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spi0 = &sfc;
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};
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
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};
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vcc5v0_host: vcc5v0-host-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_host";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_host_en>;
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vin-supply = <&vcc5v0_sys>;
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};
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};
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&combphy0_ps {
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status = "okay";
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};
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&emmc_bus8 {
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bootph-all;
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};
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&emmc_clk {
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bootph-all;
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};
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&emmc_cmd {
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bootph-all;
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};
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&emmc_data_strobe {
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bootph-all;
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};
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&emmc_rstnout {
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bootph-all;
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};
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&fspim2_pins {
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bootph-all;
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};
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&pcie2x1l2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
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reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pinctrl {
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bootph-all;
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pcie {
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pcie_reset_h: pcie-reset-h {
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rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie2x1l2_pins: pcie2x1l2-pins {
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rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
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<3 RK_PD0 4 &pcfg_pull_none>;
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};
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};
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usb {
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vcc5v0_host_en: vcc5v0-host-en {
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rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pcfg_pull_none {
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bootph-all;
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};
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&pcfg_pull_up_drv_level_2 {
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bootph-all;
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};
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&pcfg_pull_up {
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bootph-all;
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};
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&sdmmc {
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@ -20,6 +104,22 @@
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status = "okay";
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};
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&sdmmc_bus4 {
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bootph-all;
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};
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&sdmmc_clk {
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bootph-all;
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};
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&sdmmc_cmd {
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bootph-all;
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};
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&sdmmc_det {
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bootph-all;
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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@ -27,3 +127,85 @@
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
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};
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&sfc {
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bootph-pre-ram;
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u-boot,spl-sfc-no-dma;
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pinctrl-names = "default";
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pinctrl-0 = <&fspim2_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash@0 {
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bootph-pre-ram;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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};
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};
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&uart2m0_xfer {
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bootph-all;
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};
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&usb_host0_ehci {
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companion = <&usb_host0_ohci>;
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phys = <&u2phy2_host>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usb_host0_ohci {
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phys = <&u2phy2_host>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usb2phy2_grf {
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status = "okay";
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};
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&u2phy2 {
|
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resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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reset-names = "phy", "apb";
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clock-output-names = "usb480m_phy2";
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status = "okay";
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};
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|
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&u2phy2_host {
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phy-supply = <&vcc5v0_host>;
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status = "okay";
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};
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&usb_host1_ehci {
|
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companion = <&usb_host1_ohci>;
|
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phys = <&u2phy3_host>;
|
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phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
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|
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&usb_host1_ohci {
|
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phys = <&u2phy3_host>;
|
||||
phy-names = "usb2-phy";
|
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status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy3_grf {
|
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status = "okay";
|
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};
|
||||
|
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&u2phy3 {
|
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resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
|
||||
reset-names = "phy", "apb";
|
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clock-output-names = "usb480m_phy3";
|
||||
status = "okay";
|
||||
};
|
||||
|
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&u2phy3_host {
|
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phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include "rockchip-u-boot.dtsi"
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
dmc {
|
||||
|
|
@ -12,12 +13,167 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fc800000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xfc800000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host0_ohci: usb@fc840000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xfc840000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ehci: usb@fc880000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x0 0xfc880000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host1_ohci: usb@fc8c0000 {
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x0 0xfc8c0000 0x0 0x40000>;
|
||||
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
|
||||
clock-names = "usbhost", "arbiter";
|
||||
power-domains = <&power RK3588_PD_USB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu1_grf: syscon@fd58a000 {
|
||||
bootph-all;
|
||||
compatible = "rockchip,rk3588-pmu1-grf", "syscon";
|
||||
reg = <0x0 0xfd58a000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
pipe_phy0_grf: syscon@fd5bc000 {
|
||||
compatible = "rockchip,pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfd5bc000 0x0 0x100>;
|
||||
};
|
||||
|
||||
usb2phy2_grf: syscon@fd5d8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
|
||||
"simple-mfd";
|
||||
reg = <0x0 0xfd5d8000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy2: usb2-phy@8000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0x8000 0x10>;
|
||||
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy2_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb2phy3_grf: syscon@fd5dc000 {
|
||||
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
|
||||
"simple-mfd";
|
||||
reg = <0x0 0xfd5dc000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
u2phy3: usb2-phy@c000 {
|
||||
compatible = "rockchip,rk3588-usb2phy";
|
||||
reg = <0xc000 0x10>;
|
||||
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
|
||||
clock-names = "phyclk";
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
u2phy3_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie2x1l2: pcie@fe190000 {
|
||||
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x40 0x4f>;
|
||||
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
|
||||
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
|
||||
<&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk",
|
||||
"aux", "pipe";
|
||||
device_type = "pci";
|
||||
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
|
||||
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
|
||||
<0 0 0 2 &pcie2x1l2_intc 1>,
|
||||
<0 0 0 3 &pcie2x1l2_intc 2>,
|
||||
<0 0 0 4 &pcie2x1l2_intc 3>;
|
||||
linux,pci-domain = <4>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
max-link-speed = <2>;
|
||||
msi-map = <0x4000 &gic 0x4000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3588_PD_PCIE>;
|
||||
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
||||
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
|
||||
<0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
|
||||
reg = <0xa 0x41000000 0x0 0x00400000>,
|
||||
<0x0 0xfe190000 0x0 0x00010000>,
|
||||
<0x0 0xf4000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
|
||||
reset-names = "pcie", "periph";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
status = "disabled";
|
||||
|
||||
pcie2x1l2_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
|
||||
};
|
||||
};
|
||||
|
||||
sfc: spi@fe2b0000 {
|
||||
compatible = "rockchip,sfc";
|
||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
||||
clock-names = "clk_sfc", "hclk_sfc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
otp: nvmem@fecc0000 {
|
||||
compatible = "rockchip,rk3588-otp";
|
||||
reg = <0x0 0xfecc0000 0x0 0x400>;
|
||||
|
|
@ -35,6 +191,22 @@
|
|||
reg = <0x0 0xfe378000 0x0 0x200>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
combphy0_ps: phy@fee00000 {
|
||||
compatible = "rockchip,rk3588-naneng-combphy";
|
||||
reg = <0x0 0xfee00000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
|
||||
<&cru PCLK_PHP_ROOT>;
|
||||
clock-names = "refclk", "apbclk", "phpclk";
|
||||
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
|
||||
reset-names = "combphy-apb", "combphy";
|
||||
rockchip,pipe-grf = <&php_grf>;
|
||||
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&xin24m {
|
||||
|
|
@ -67,6 +239,7 @@
|
|||
|
||||
&sdhci {
|
||||
bootph-pre-ram;
|
||||
u-boot,spl-fifo-mode;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
|
|
@ -78,3 +251,14 @@
|
|||
&ioc {
|
||||
bootph-pre-ram;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
|
||||
&binman {
|
||||
simple-bin-spi {
|
||||
mkimage {
|
||||
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
|
||||
offset = <0x8000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@ enum {
|
|||
BROM_BOOTSOURCE_SPINOR = 3,
|
||||
BROM_BOOTSOURCE_SPINAND = 4,
|
||||
BROM_BOOTSOURCE_SD = 5,
|
||||
BROM_BOOTSOURCE_SPINOR_RK3588 = 6,
|
||||
BROM_BOOTSOURCE_USB = 10,
|
||||
BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
|
||||
};
|
||||
|
|
|
|||
|
|
@ -194,5 +194,26 @@ int rockchip_get_clk(struct udevice **devp);
|
|||
* Return: 0 success, or error value
|
||||
*/
|
||||
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
|
||||
/*
|
||||
* rockchip_reset_bind_lut() - Bind soft reset device as child of clock device
|
||||
* using a dedicated SoC lookup table
|
||||
* @pdev: clock udevice
|
||||
* @lookup_table: register lookup_table dedicated to SoC
|
||||
* @reg_offset: the first offset in cru for softreset registers
|
||||
* @reg_number: the reg numbers of softreset registers
|
||||
* Return: 0 success, or error value
|
||||
*/
|
||||
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
|
||||
u32 reg_offset, u32 reg_number);
|
||||
/*
|
||||
* rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
|
||||
* using dedicated RK3588 lookup table
|
||||
*
|
||||
* @pdev: clock udevice
|
||||
* @reg_offset: the first offset in cru for softreset registers
|
||||
* @reg_number: the reg numbers of softreset registers
|
||||
* Return: 0 success, or error value
|
||||
*/
|
||||
int rk3588_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -311,6 +311,8 @@ config ROCKCHIP_RK3588
|
|||
select REGMAP
|
||||
select SYSCON
|
||||
select BOARD_LATE_INIT
|
||||
select DM_REGULATOR_FIXED
|
||||
select DM_RESET
|
||||
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
|
||||
imply ROCKCHIP_COMMON_BOARD
|
||||
imply OF_LIBFDT_OVERLAY
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
|
|||
[BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
|
||||
[BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0",
|
||||
[BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",
|
||||
[BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b0000/flash@0",
|
||||
};
|
||||
|
||||
static struct mm_region rk3588_mem_map[] = {
|
||||
|
|
|
|||
|
|
@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_TARGET_EVB_RK3568=y
|
||||
|
|
@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
|
|||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
|
|
@ -36,13 +35,17 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
|||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_PMIC=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -57,7 +60,9 @@ CONFIG_MMC_SDHCI_SDMA=y
|
|||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
|
|||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
|
|
@ -22,12 +21,13 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
|
|||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
|
|
@ -36,14 +36,15 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
|||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -63,6 +64,6 @@ CONFIG_PWM_ROCKCHIP=y
|
|||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ CONFIG_NR_DRAM_BANKS=2
|
|||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_DEBUG_UART_BASE=0xff690000
|
|||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_LTO=y
|
||||
CONFIG_SYS_MONITOR_LEN=614400
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_USE_PREBOOT=y
|
||||
|
|
|
|||
|
|
@ -59,6 +59,14 @@ CONFIG_LED=y
|
|||
CONFIG_LED_GPIO=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_SPL_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_SPL_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_SPL_MMC_HS400_SUPPORT=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
|
|
|
|||
|
|
@ -10,9 +10,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3566-radxa-cm3-io"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_TARGET_EVB_RK3568=y
|
||||
|
|
@ -23,11 +21,12 @@ CONFIG_SYS_LOAD_ADDR=0xc00800
|
|||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
|
|
@ -36,6 +35,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
|||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
@ -46,7 +46,7 @@ CONFIG_CMD_REGULATOR=y
|
|||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -63,6 +63,7 @@ CONFIG_ETH_DESIGNWARE=y
|
|||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
|
|
@ -70,6 +71,7 @@ CONFIG_PWM_ROCKCHIP=y
|
|||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
|
|||
|
|
@ -8,26 +8,30 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
|
||||
CONFIG_ROCKCHIP_RK3568=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_ROCKCHIP_SPI_IMAGE=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_TARGET_EVB_RK3568=y
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
|
|
@ -35,7 +39,10 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
|||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
|
|
@ -46,7 +53,7 @@ CONFIG_CMD_REGULATOR=y
|
|||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -59,19 +66,22 @@ CONFIG_MMC_DW_ROCKCHIP=y
|
|||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_DM_PMIC=y
|
||||
CONFIG_PMIC_RK8XX=y
|
||||
CONFIG_SPL_PMIC_RK8XX=y
|
||||
CONFIG_REGULATOR_RK8XX=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
|
|||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
|
|
@ -56,6 +57,7 @@ CONFIG_ROCKCHIP_EFUSE=y
|
|||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
|
|
|
|||
|
|
@ -8,19 +8,22 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_SF_DEFAULT_MODE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3588=y
|
||||
CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
|
||||
CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
|
||||
CONFIG_SPL_MMC=y
|
||||
CONFIG_ROCKCHIP_SPI_IMAGE=y
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_TARGET_ROCK5B_RK3588=y
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_DEBUG_UART_BASE=0xFEB50000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI=y
|
||||
CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
|
|
@ -30,7 +33,7 @@ CONFIG_OF_BOARD_SETUP=y
|
|||
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x20000
|
||||
CONFIG_SPL_MAX_SIZE=0x40000
|
||||
CONFIG_SPL_PAD_TO=0x7f8000
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x4000000
|
||||
|
|
@ -38,15 +41,20 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
|||
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
|
||||
CONFIG_SPL_ATF=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
# CONFIG_SPL_DOS_PARTITION is not set
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
CONFIG_SPL_REGMAP=y
|
||||
CONFIG_SPL_SYSCON=y
|
||||
CONFIG_SPL_CLK=y
|
||||
|
|
@ -58,14 +66,34 @@ CONFIG_MMC_DW=y
|
|||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
# CONFIG_SPL_MMC_SDHCI_SDMA is not set
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_XTX=y
|
||||
CONFIG_ETH_DESIGNWARE=y
|
||||
CONFIG_GMAC_ROCKCHIP=y
|
||||
CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_SPL_RAM=y
|
||||
CONFIG_BAUDRATE=1500000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550_MEM32=y
|
||||
CONFIG_ROCKCHIP_SFC=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_GENERIC=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_ASIX88179=y
|
||||
CONFIG_USB_ETHER_LAN75XX=y
|
||||
CONFIG_USB_ETHER_LAN78XX=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000
|
|||
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_ROCKCHIP_RK3399=y
|
||||
CONFIG_ROCKCHIP_SPI_IMAGE=y
|
||||
CONFIG_TARGET_ROCKPRO64_RK3399=y
|
||||
CONFIG_SPL_STACK=0x400000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
||||
|
|
@ -20,6 +21,8 @@ CONFIG_SPL_SPI=y
|
|||
CONFIG_SYS_LOAD_ADDR=0x800800
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_LTO=y
|
||||
CONFIG_SPL_FIT_SIGNATURE=y
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_BOOTSTAGE_REPORT=y
|
||||
CONFIG_USE_PREBOOT=y
|
||||
|
|
@ -36,6 +39,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
|||
CONFIG_SPL_STACK_R=y
|
||||
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
|
||||
CONFIG_SPL_SPI_LOAD=y
|
||||
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
|
||||
CONFIG_TPL=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPT=y
|
||||
|
|
@ -63,6 +67,7 @@ CONFIG_ROCKCHIP_EFUSE=y
|
|||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_SDMA=y
|
||||
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
|
|
|
|||
|
|
@ -1996,7 +1996,7 @@ static int rk3588_clk_bind(struct udevice *dev)
|
|||
|
||||
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
|
||||
ret = offsetof(struct rk3588_cru, softrst_con[0]);
|
||||
ret = rockchip_reset_bind(dev, ret, 49158);
|
||||
ret = rk3588_reset_bind_lut(dev, ret, 49158);
|
||||
if (ret)
|
||||
debug("Warning: software reset driver bind failed\n");
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -589,12 +589,22 @@ static int rockchip_sdhci_probe(struct udevice *dev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Disable use of DMA and force use of PIO mode in SPL to fix an issue
|
||||
* where loading part of TF-A into SRAM using DMA silently fails.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD) &&
|
||||
dev_read_bool(dev, "u-boot,spl-fifo-mode"))
|
||||
host->flags &= ~USE_DMA;
|
||||
|
||||
/*
|
||||
* Reading more than 4 blocks with a single CMD18 command in PIO mode
|
||||
* triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
|
||||
* max 4 blocks in one command when using PIO mode.
|
||||
*/
|
||||
if (!(host->flags & USE_DMA))
|
||||
if (!(host->flags & USE_DMA) &&
|
||||
(device_is_compatible(dev, "rockchip,rk3568-dwcmshc") ||
|
||||
device_is_compatible(dev, "rockchip,rk3588-dwcmshc")))
|
||||
cfg->b_max = 4;
|
||||
|
||||
return sdhci_probe(dev);
|
||||
|
|
|
|||
|
|
@ -42,6 +42,7 @@ struct rk_pcie {
|
|||
struct clk_bulk clks;
|
||||
struct reset_ctl_bulk rsts;
|
||||
struct gpio_desc rst_gpio;
|
||||
u32 gen;
|
||||
};
|
||||
|
||||
/* Parameters for the waiting for iATU enabled routine */
|
||||
|
|
@ -331,7 +332,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
|
|||
rk_pcie_writel_apb(priv, 0x0, 0xf00040);
|
||||
pcie_dw_setup_host(&priv->dw);
|
||||
|
||||
ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3);
|
||||
ret = rk_pcie_link_up(priv, priv->gen);
|
||||
if (ret < 0)
|
||||
goto err_link_up;
|
||||
|
||||
|
|
@ -397,6 +398,9 @@ static int rockchip_pcie_parse_dt(struct udevice *dev)
|
|||
goto rockchip_pcie_parse_dt_err_phy_get_by_index;
|
||||
}
|
||||
|
||||
priv->gen = dev_read_u32_default(dev, "max-link-speed",
|
||||
LINK_SPEED_GEN_3);
|
||||
|
||||
return 0;
|
||||
|
||||
rockchip_pcie_parse_dt_err_phy_get_by_index:
|
||||
|
|
@ -468,6 +472,7 @@ static const struct dm_pci_ops rockchip_pcie_ops = {
|
|||
|
||||
static const struct udevice_id rockchip_pcie_ids[] = {
|
||||
{ .compatible = "rockchip,rk3568-pcie" },
|
||||
{ .compatible = "rockchip,rk3588-pcie" },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -54,50 +54,12 @@
|
|||
|
||||
struct phy_meson_g12a_usb2_priv {
|
||||
struct regmap *regmap;
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
struct udevice *phy_supply;
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
struct clk clk;
|
||||
#endif
|
||||
struct reset_ctl reset;
|
||||
};
|
||||
|
||||
|
||||
static int phy_meson_g12a_usb2_power_on(struct phy *phy)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
struct udevice *dev = phy->dev;
|
||||
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (priv->phy_supply) {
|
||||
int ret = regulator_set_enable(priv->phy_supply, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb2_power_off(struct phy *phy)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
struct udevice *dev = phy->dev;
|
||||
struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (priv->phy_supply) {
|
||||
int ret = regulator_set_enable(priv->phy_supply, false);
|
||||
if (ret) {
|
||||
pr_err("Error disabling PHY supply\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_g12a_usb2_init(struct phy *phy)
|
||||
{
|
||||
struct udevice *dev = phy->dev;
|
||||
|
|
@ -155,8 +117,6 @@ static int phy_meson_g12a_usb2_exit(struct phy *phy)
|
|||
struct phy_ops meson_g12a_usb2_phy_ops = {
|
||||
.init = phy_meson_g12a_usb2_init,
|
||||
.exit = phy_meson_g12a_usb2_exit,
|
||||
.power_on = phy_meson_g12a_usb2_power_on,
|
||||
.power_off = phy_meson_g12a_usb2_power_off,
|
||||
};
|
||||
|
||||
int meson_g12a_usb2_phy_probe(struct udevice *dev)
|
||||
|
|
@ -193,14 +153,6 @@ int meson_g12a_usb2_phy_probe(struct udevice *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
|
||||
if (ret && ret != -ENOENT) {
|
||||
pr_err("Failed to get PHY regulator\n");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <clk.h>
|
||||
#include <dm.h>
|
||||
#include <generic-phy.h>
|
||||
#include <power/regulator.h>
|
||||
#include <regmap.h>
|
||||
#include <reset.h>
|
||||
#include <linux/bitops.h>
|
||||
|
|
@ -81,9 +80,6 @@
|
|||
struct phy_meson_gxbb_usb2_priv {
|
||||
struct regmap *regmap;
|
||||
struct reset_ctl_bulk resets;
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
struct udevice *phy_supply;
|
||||
#endif
|
||||
};
|
||||
|
||||
static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
|
||||
|
|
@ -92,15 +88,6 @@ static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
|
|||
struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
|
||||
uint val;
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
if (priv->phy_supply) {
|
||||
int ret = regulator_set_enable(priv->phy_supply, true);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
regmap_update_bits(priv->regmap, REG_CONFIG,
|
||||
REG_CONFIG_CLK_32k_ALTSEL,
|
||||
REG_CONFIG_CLK_32k_ALTSEL);
|
||||
|
|
@ -140,26 +127,8 @@ static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_gxbb_usb2_power_off(struct phy *phy)
|
||||
{
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
struct udevice *dev = phy->dev;
|
||||
struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
|
||||
|
||||
if (priv->phy_supply) {
|
||||
int ret = regulator_set_enable(priv->phy_supply, false);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy_ops meson_gxbb_usb2_phy_ops = {
|
||||
.power_on = phy_meson_gxbb_usb2_power_on,
|
||||
.power_off = phy_meson_gxbb_usb2_power_off,
|
||||
};
|
||||
|
||||
static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
|
||||
|
|
@ -192,13 +161,6 @@ static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
|
||||
if (ret && ret != -ENOENT) {
|
||||
pr_err("Failed to get PHY regulator\n");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
ret = reset_get_bulk(dev, &priv->resets);
|
||||
if (!ret) {
|
||||
ret = reset_deassert_bulk(&priv->resets);
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#include <generic-phy.h>
|
||||
#include <regmap.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/regulator.h>
|
||||
#include <clk.h>
|
||||
#include <linux/usb/otg.h>
|
||||
|
||||
|
|
@ -101,9 +100,6 @@
|
|||
|
||||
struct phy_meson_gxl_usb2_priv {
|
||||
struct regmap *regmap;
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
struct udevice *phy_supply;
|
||||
#endif
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
struct clk clk;
|
||||
#endif
|
||||
|
|
@ -167,14 +163,6 @@ static int phy_meson_gxl_usb2_power_on(struct phy *phy)
|
|||
|
||||
phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
if (priv->phy_supply) {
|
||||
int ret = regulator_set_enable(priv->phy_supply, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -189,16 +177,6 @@ static int phy_meson_gxl_usb2_power_off(struct phy *phy)
|
|||
val |= U2P_R0_POWER_ON_RESET;
|
||||
regmap_write(priv->regmap, U2P_R0, val);
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
if (priv->phy_supply) {
|
||||
int ret = regulator_set_enable(priv->phy_supply, false);
|
||||
if (ret) {
|
||||
pr_err("Error disabling PHY supply\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -229,14 +207,6 @@ int meson_gxl_usb2_phy_probe(struct udevice *dev)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||||
ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
|
||||
if (ret && ret != -ENOENT) {
|
||||
pr_err("Failed to get PHY regulator\n");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include <dm/devres.h>
|
||||
#include <generic-phy.h>
|
||||
#include <linux/list.h>
|
||||
#include <power/regulator.h>
|
||||
|
||||
/**
|
||||
* struct phy_counts - Init and power-on counts of a single PHY port
|
||||
|
|
@ -29,12 +30,14 @@
|
|||
* without a matching generic_phy_exit() afterwards
|
||||
* @list: Handle for a linked list of these structures corresponding to
|
||||
* ports of the same PHY provider
|
||||
* @supply: Handle to a phy-supply device
|
||||
*/
|
||||
struct phy_counts {
|
||||
unsigned long id;
|
||||
int power_on_count;
|
||||
int init_count;
|
||||
struct list_head list;
|
||||
struct udevice *supply;
|
||||
};
|
||||
|
||||
static inline struct phy_ops *phy_dev_ops(struct udevice *dev)
|
||||
|
|
@ -58,7 +61,7 @@ static struct phy_counts *phy_get_counts(struct phy *phy)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static int phy_alloc_counts(struct phy *phy)
|
||||
static int phy_alloc_counts(struct phy *phy, struct udevice *supply)
|
||||
{
|
||||
struct list_head *uc_priv;
|
||||
struct phy_counts *counts;
|
||||
|
|
@ -76,6 +79,7 @@ static int phy_alloc_counts(struct phy *phy)
|
|||
counts->id = phy->id;
|
||||
counts->power_on_count = 0;
|
||||
counts->init_count = 0;
|
||||
counts->supply = supply;
|
||||
list_add(&counts->list, uc_priv);
|
||||
|
||||
return 0;
|
||||
|
|
@ -123,7 +127,7 @@ int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy)
|
|||
{
|
||||
struct ofnode_phandle_args args;
|
||||
struct phy_ops *ops;
|
||||
struct udevice *phydev;
|
||||
struct udevice *phydev, *supply = NULL;
|
||||
int i, ret;
|
||||
|
||||
debug("%s(node=%s, index=%d, phy=%p)\n",
|
||||
|
|
@ -172,7 +176,17 @@ int generic_phy_get_by_index_nodev(ofnode node, int index, struct phy *phy)
|
|||
goto err;
|
||||
}
|
||||
|
||||
ret = phy_alloc_counts(phy);
|
||||
if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
|
||||
ret = device_get_supply_regulator(phydev, "phy-supply",
|
||||
&supply);
|
||||
if (ret && ret != -ENOENT) {
|
||||
debug("%s: device_get_supply_regulator failed: %d\n",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
||||
ret = phy_alloc_counts(phy, supply);
|
||||
if (ret) {
|
||||
debug("phy_alloc_counts() failed: %d\n", ret);
|
||||
goto err;
|
||||
|
|
@ -214,24 +228,24 @@ int generic_phy_init(struct phy *phy)
|
|||
|
||||
if (!generic_phy_valid(phy))
|
||||
return 0;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (!ops->init)
|
||||
return 0;
|
||||
|
||||
counts = phy_get_counts(phy);
|
||||
if (counts->init_count > 0) {
|
||||
counts->init_count++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = ops->init(phy);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "PHY: Failed to init %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
else
|
||||
counts->init_count = 1;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (ops->init) {
|
||||
ret = ops->init(phy);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "PHY: Failed to init %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
counts->init_count = 1;
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int generic_phy_reset(struct phy *phy)
|
||||
|
|
@ -260,10 +274,6 @@ int generic_phy_exit(struct phy *phy)
|
|||
|
||||
if (!generic_phy_valid(phy))
|
||||
return 0;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (!ops->exit)
|
||||
return 0;
|
||||
|
||||
counts = phy_get_counts(phy);
|
||||
if (counts->init_count == 0)
|
||||
return 0;
|
||||
|
|
@ -272,14 +282,18 @@ int generic_phy_exit(struct phy *phy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
ret = ops->exit(phy);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
else
|
||||
counts->init_count = 0;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (ops->exit) {
|
||||
ret = ops->exit(phy);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "PHY: Failed to exit %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
counts->init_count = 0;
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int generic_phy_power_on(struct phy *phy)
|
||||
|
|
@ -290,24 +304,32 @@ int generic_phy_power_on(struct phy *phy)
|
|||
|
||||
if (!generic_phy_valid(phy))
|
||||
return 0;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (!ops->power_on)
|
||||
return 0;
|
||||
|
||||
counts = phy_get_counts(phy);
|
||||
if (counts->power_on_count > 0) {
|
||||
counts->power_on_count++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = ops->power_on(phy);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
else
|
||||
counts->power_on_count = 1;
|
||||
ret = regulator_set_enable_if_allowed(counts->supply, true);
|
||||
if (ret && ret != -ENOSYS) {
|
||||
dev_err(phy->dev, "PHY: Failed to enable regulator %s: %d.\n",
|
||||
counts->supply->name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (ops->power_on) {
|
||||
ret = ops->power_on(phy);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "PHY: Failed to power on %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
regulator_set_enable_if_allowed(counts->supply, false);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
counts->power_on_count = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int generic_phy_power_off(struct phy *phy)
|
||||
|
|
@ -318,10 +340,6 @@ int generic_phy_power_off(struct phy *phy)
|
|||
|
||||
if (!generic_phy_valid(phy))
|
||||
return 0;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (!ops->power_off)
|
||||
return 0;
|
||||
|
||||
counts = phy_get_counts(phy);
|
||||
if (counts->power_on_count == 0)
|
||||
return 0;
|
||||
|
|
@ -330,14 +348,23 @@ int generic_phy_power_off(struct phy *phy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
ret = ops->power_off(phy);
|
||||
if (ret)
|
||||
dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
else
|
||||
counts->power_on_count = 0;
|
||||
ops = phy_dev_ops(phy->dev);
|
||||
if (ops->power_off) {
|
||||
ret = ops->power_off(phy);
|
||||
if (ret) {
|
||||
dev_err(phy->dev, "PHY: Failed to power off %s: %d.\n",
|
||||
phy->dev->name, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
counts->power_on_count = 0;
|
||||
|
||||
return ret;
|
||||
ret = regulator_set_enable_if_allowed(counts->supply, false);
|
||||
if (ret && ret != -ENOSYS)
|
||||
dev_err(phy->dev, "PHY: Failed to disable regulator %s: %d.\n",
|
||||
counts->supply->name, ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int generic_phy_configure(struct phy *phy, void *params)
|
||||
|
|
|
|||
|
|
@ -201,14 +201,14 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
|
|||
|
||||
/* find out a proper config which can be matched with dt. */
|
||||
index = 0;
|
||||
while (phy_cfgs[index].reg) {
|
||||
do {
|
||||
if (phy_cfgs[index].reg == reg) {
|
||||
priv->phy_cfg = &phy_cfgs[index];
|
||||
break;
|
||||
}
|
||||
|
||||
++index;
|
||||
}
|
||||
} while (phy_cfgs[index].reg);
|
||||
|
||||
if (!priv->phy_cfg) {
|
||||
dev_err(dev, "failed find proper phy-cfg\n");
|
||||
|
|
@ -348,6 +348,58 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
|
|||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x0000,
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0x000c, 11, 11, 0, 1 },
|
||||
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
.utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
}
|
||||
},
|
||||
},
|
||||
{
|
||||
.reg = 0x4000,
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
.phy_sus = { 0x000c, 11, 11, 0, 0 },
|
||||
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
.utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
}
|
||||
},
|
||||
},
|
||||
{
|
||||
.reg = 0x8000,
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0x0008, 2, 2, 0, 1 },
|
||||
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
.utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
}
|
||||
},
|
||||
},
|
||||
{
|
||||
.reg = 0xc000,
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0x0008, 2, 2, 0, 1 },
|
||||
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
.utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
}
|
||||
},
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct udevice_id rockchip_usb2phy_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3399-usb2phy",
|
||||
|
|
@ -357,6 +409,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
|
|||
.compatible = "rockchip,rk3568-usb2phy",
|
||||
.data = (ulong)&rk3568_phy_cfgs,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3588-usb2phy",
|
||||
.data = (ulong)&rk3588_phy_cfgs,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ struct rockchip_combphy_grfcfg {
|
|||
struct combphy_reg con2_for_sata;
|
||||
struct combphy_reg con3_for_sata;
|
||||
struct combphy_reg pipe_con0_for_sata;
|
||||
struct combphy_reg pipe_con1_for_sata;
|
||||
struct combphy_reg pipe_sgmii_mac_sel;
|
||||
struct combphy_reg pipe_xpcs_phy_ready;
|
||||
struct combphy_reg u3otg0_port_en;
|
||||
|
|
@ -76,7 +77,7 @@ struct rockchip_combphy_priv {
|
|||
struct regmap *pipe_grf;
|
||||
struct regmap *phy_grf;
|
||||
struct phy *phy;
|
||||
struct reset_ctl phy_rst;
|
||||
struct reset_ctl_bulk phy_rsts;
|
||||
struct clk ref_clk;
|
||||
const struct rockchip_combphy_cfg *cfg;
|
||||
};
|
||||
|
|
@ -189,7 +190,7 @@ static int rockchip_combphy_init(struct phy *phy)
|
|||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
reset_deassert(&priv->phy_rst);
|
||||
reset_deassert_bulk(&priv->phy_rsts);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
@ -204,7 +205,7 @@ static int rockchip_combphy_exit(struct phy *phy)
|
|||
struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
|
||||
|
||||
clk_disable(&priv->ref_clk);
|
||||
reset_assert(&priv->phy_rst);
|
||||
reset_assert_bulk(&priv->phy_rsts);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -255,7 +256,7 @@ static int rockchip_combphy_parse_dt(struct udevice *dev,
|
|||
return PTR_ERR(&priv->ref_clk);
|
||||
}
|
||||
|
||||
ret = reset_get_by_index(dev, 0, &priv->phy_rst);
|
||||
ret = reset_get_bulk(dev, &priv->phy_rsts);
|
||||
if (ret) {
|
||||
dev_err(dev, "no phy reset control specified\n");
|
||||
return ret;
|
||||
|
|
@ -423,11 +424,105 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
|
|||
.combphy_cfg = rk3568_combphy_cfg,
|
||||
};
|
||||
|
||||
static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
||||
{
|
||||
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
u32 val;
|
||||
|
||||
switch (priv->mode) {
|
||||
case PHY_TYPE_PCIE:
|
||||
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
||||
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
||||
param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
||||
break;
|
||||
case PHY_TYPE_USB3:
|
||||
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
||||
break;
|
||||
case PHY_TYPE_SATA:
|
||||
param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
||||
param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
||||
param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
||||
param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
|
||||
break;
|
||||
case PHY_TYPE_SGMII:
|
||||
case PHY_TYPE_QSGMII:
|
||||
default:
|
||||
dev_err(priv->dev, "incompatible PHY type\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* 100MHz refclock signal is good */
|
||||
clk_set_rate(&priv->ref_clk, 100000000);
|
||||
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
if (priv->mode == PHY_TYPE_PCIE) {
|
||||
/* PLL KVCO tuning fine */
|
||||
val = readl(priv->mmio + (0x20 << 2));
|
||||
val &= ~GENMASK(4, 2);
|
||||
val |= 0x4 << 2;
|
||||
writel(val, priv->mmio + (0x20 << 2));
|
||||
|
||||
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
|
||||
val = 0x4c;
|
||||
writel(val, priv->mmio + (0x1b << 2));
|
||||
|
||||
/* Set up su_trim: T3 */
|
||||
val = 0xb0;
|
||||
writel(val, priv->mmio + (0xa << 2));
|
||||
val = 0x47;
|
||||
writel(val, priv->mmio + (0xb << 2));
|
||||
val = 0x57;
|
||||
writel(val, priv->mmio + (0xd << 2));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
|
||||
/* pipe-phy-grf */
|
||||
.pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
||||
.usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
||||
.pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
||||
.pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
||||
.pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
||||
.pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
||||
.pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
||||
.pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
||||
.pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
||||
.pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
||||
.pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
||||
.pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
||||
.con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
||||
.con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
.con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
||||
.con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
||||
.con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
|
||||
.con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
|
||||
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
|
||||
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
|
||||
/* pipe-grf */
|
||||
.pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
|
||||
.pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
|
||||
};
|
||||
|
||||
static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
|
||||
.grfcfg = &rk3588_combphy_grfcfgs,
|
||||
.combphy_cfg = rk3588_combphy_cfg,
|
||||
};
|
||||
|
||||
static const struct udevice_id rockchip_combphy_ids[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3568-naneng-combphy",
|
||||
.data = (ulong)&rk3568_combphy_cfgs
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3588-naneng-combphy",
|
||||
.data = (ulong)&rk3588_combphy_cfgs
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
|||
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
||||
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
|
||||
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
|
||||
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
||||
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
||||
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
struct rockchip_reset_priv {
|
||||
void __iomem *base;
|
||||
const int *lut;
|
||||
/* Rockchip reset reg locate at cru controller */
|
||||
u32 reset_reg_offset;
|
||||
/* Rockchip reset reg number */
|
||||
|
|
@ -30,11 +31,15 @@ struct rockchip_reset_priv {
|
|||
static int rockchip_reset_request(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||
unsigned long id = reset_ctl->id;
|
||||
|
||||
if (priv->lut)
|
||||
id = priv->lut[id];
|
||||
|
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_num=%d)\n", __func__,
|
||||
reset_ctl, reset_ctl->dev, reset_ctl->id, priv->reset_reg_num);
|
||||
reset_ctl, reset_ctl->dev, id, priv->reset_reg_num);
|
||||
|
||||
if (reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
|
||||
if (id / ROCKCHIP_RESET_NUM_IN_REG >= priv->reset_reg_num)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
|
|
@ -43,12 +48,17 @@ static int rockchip_reset_request(struct reset_ctl *reset_ctl)
|
|||
static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||
int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
|
||||
int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
|
||||
unsigned long id = reset_ctl->id;
|
||||
int bank, offset;
|
||||
|
||||
if (priv->lut)
|
||||
id = priv->lut[id];
|
||||
|
||||
bank = id / ROCKCHIP_RESET_NUM_IN_REG;
|
||||
offset = id % ROCKCHIP_RESET_NUM_IN_REG;
|
||||
|
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
|
||||
reset_ctl, reset_ctl->dev, reset_ctl->id,
|
||||
priv->base + (bank * 4));
|
||||
reset_ctl, reset_ctl->dev, id, priv->base + (bank * 4));
|
||||
|
||||
rk_setreg(priv->base + (bank * 4), BIT(offset));
|
||||
|
||||
|
|
@ -58,12 +68,17 @@ static int rockchip_reset_assert(struct reset_ctl *reset_ctl)
|
|||
static int rockchip_reset_deassert(struct reset_ctl *reset_ctl)
|
||||
{
|
||||
struct rockchip_reset_priv *priv = dev_get_priv(reset_ctl->dev);
|
||||
int bank = reset_ctl->id / ROCKCHIP_RESET_NUM_IN_REG;
|
||||
int offset = reset_ctl->id % ROCKCHIP_RESET_NUM_IN_REG;
|
||||
unsigned long id = reset_ctl->id;
|
||||
int bank, offset;
|
||||
|
||||
if (priv->lut)
|
||||
id = priv->lut[id];
|
||||
|
||||
bank = id / ROCKCHIP_RESET_NUM_IN_REG;
|
||||
offset = id % ROCKCHIP_RESET_NUM_IN_REG;
|
||||
|
||||
debug("%s(reset_ctl=%p) (dev=%p, id=%lu) (reg_addr=%p)\n", __func__,
|
||||
reset_ctl, reset_ctl->dev, reset_ctl->id,
|
||||
priv->base + (bank * 4));
|
||||
reset_ctl, reset_ctl->dev, id, priv->base + (bank * 4));
|
||||
|
||||
rk_clrreg(priv->base + (bank * 4), BIT(offset));
|
||||
|
||||
|
|
@ -98,7 +113,10 @@ static int rockchip_reset_probe(struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
|
||||
int rockchip_reset_bind_lut(struct udevice *pdev,
|
||||
const int *lookup_table,
|
||||
u32 reg_offset,
|
||||
u32 reg_number)
|
||||
{
|
||||
struct udevice *rst_dev;
|
||||
struct rockchip_reset_priv *priv;
|
||||
|
|
@ -113,11 +131,17 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
|
|||
priv = malloc(sizeof(struct rockchip_reset_priv));
|
||||
priv->reset_reg_offset = reg_offset;
|
||||
priv->reset_reg_num = reg_number;
|
||||
priv->lut = lookup_table;
|
||||
dev_set_priv(rst_dev, priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number)
|
||||
{
|
||||
return rockchip_reset_bind_lut(pdev, NULL, reg_offset, reg_number);
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(rockchip_reset) = {
|
||||
.name = "rockchip_reset",
|
||||
.id = UCLASS_RESET,
|
||||
|
|
|
|||
854
drivers/reset/rst-rk3588.c
Normal file
854
drivers/reset/rst-rk3588.c
Normal file
|
|
@ -0,0 +1,854 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
* Copyright (c) 2022 Collabora Ltd.
|
||||
* Author: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3588-cru.h>
|
||||
|
||||
/* 0xFD7C0000 + 0x0A00 */
|
||||
#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
|
||||
|
||||
/* 0xFD7C8000 + 0x0A00 */
|
||||
#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
|
||||
|
||||
/* 0xFD7D0000 + 0x0A00 */
|
||||
#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
|
||||
|
||||
/* 0xFD7F0000 + 0x0A00 */
|
||||
#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
|
||||
|
||||
/* mapping table for reset ID to register offset */
|
||||
static const int rk3588_register_offset[] = {
|
||||
/* SOFTRST_CON01 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15),
|
||||
|
||||
/* SOFTRST_CON02 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15),
|
||||
|
||||
/* SOFTRST_CON03 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15),
|
||||
|
||||
/* SOFTRST_CON04 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
|
||||
|
||||
/* SOFTRST_CON05 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15),
|
||||
|
||||
/* SOFTRST_CON06 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1),
|
||||
|
||||
/* SOFTRST_CON07 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),
|
||||
|
||||
/* SOFTRST_CON08 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14),
|
||||
|
||||
/* SOFTRST_CON09 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
|
||||
|
||||
/* SOFTRST_CON10 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15),
|
||||
|
||||
/* SOFTRST_CON11 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
|
||||
|
||||
/* SOFTRST_CON12 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13),
|
||||
|
||||
/* SOFTRST_CON13 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15),
|
||||
|
||||
/* SOFTRST_CON14 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15),
|
||||
|
||||
/* SOFTRST_CON15 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15),
|
||||
|
||||
/* SOFTRST_CON16 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15),
|
||||
|
||||
/* SOFTRST_CON17 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15),
|
||||
|
||||
/* SOFTRST_CON18 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11),
|
||||
|
||||
/* SOFTRST_CON19 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5),
|
||||
|
||||
/* SOFTRST_CON20 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15),
|
||||
|
||||
/* SOFTRST_CON21 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15),
|
||||
|
||||
/* SOFTRST_CON22 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8),
|
||||
|
||||
/* SOFTRST_CON23 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15),
|
||||
|
||||
/* SOFTRST_CON24 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15),
|
||||
|
||||
/* SOFTRST_CON25 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8),
|
||||
|
||||
/* SOFTRST_CON26 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8),
|
||||
|
||||
/* SOFTRST_CON27 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3),
|
||||
|
||||
/* SOFTRST_CON28 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3),
|
||||
|
||||
/* SOFTRST_CON29 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14),
|
||||
|
||||
/* SOFTRST_CON30 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9),
|
||||
|
||||
/* SOFTRST_CON31 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11),
|
||||
|
||||
/* SOFTRST_CON32 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15),
|
||||
|
||||
/* SOFTRST_CON33 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15),
|
||||
|
||||
/* SOFTRST_CON34 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9),
|
||||
|
||||
/* SOFTRST_CON35 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7),
|
||||
|
||||
/* SOFTRST_CON37 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15),
|
||||
|
||||
/* SOFTRST_CON40 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9),
|
||||
|
||||
/* SOFTRST_CON41 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8),
|
||||
|
||||
/* SOFTRST_CON42 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15),
|
||||
|
||||
/* SOFTRST_CON43 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2),
|
||||
|
||||
/* SOFTRST_CON44 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15),
|
||||
|
||||
/* SOFTRST_CON45 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12),
|
||||
|
||||
/* SOFTRST_CON47 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6),
|
||||
|
||||
/* SOFTRST_CON48 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6),
|
||||
|
||||
/* SOFTRST_CON49 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11),
|
||||
|
||||
/* SOFTRST_CON50 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9),
|
||||
|
||||
/* SOFTRST_CON51 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13),
|
||||
|
||||
/* SOFTRST_CON52 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15),
|
||||
|
||||
/* SOFTRST_CON53 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9),
|
||||
|
||||
/* SOFTRST_CON55 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15),
|
||||
|
||||
/* SOFTRST_CON56 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14),
|
||||
|
||||
/* SOFTRST_CON57 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11),
|
||||
|
||||
/* SOFTRST_CON59 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13),
|
||||
|
||||
/* SOFTRST_CON60 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11),
|
||||
|
||||
/* SOFTRST_CON61 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11),
|
||||
|
||||
/* SOFTRST_CON62 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15),
|
||||
|
||||
/* SOFTRST_CON63 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15),
|
||||
|
||||
/* SOFTRST_CON64 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15),
|
||||
|
||||
/* SOFTRST_CON65 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8),
|
||||
|
||||
/* SOFTRST_CON66 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15),
|
||||
|
||||
/* SOFTRST_CON67 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4),
|
||||
|
||||
/* SOFTRST_CON68 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5),
|
||||
|
||||
/* SOFTRST_CON69 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14),
|
||||
|
||||
/* SOFTRST_CON70 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12),
|
||||
|
||||
/* SOFTRST_CON72 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM
|
||||
|
||||
/* SOFTRST_CON73 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13),
|
||||
|
||||
/* SOFTRST_CON74 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3),
|
||||
|
||||
/* SOFTRST_CON75 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3),
|
||||
|
||||
/* SOFTRST_CON76 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6),
|
||||
|
||||
/* SOFTRST_CON77 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8),
|
||||
|
||||
/* PHPTOPCRU_SOFTRST_CON00 */
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9),
|
||||
RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10),
|
||||
|
||||
/* PMU1CRU_SOFTRST_CON00 */
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
|
||||
|
||||
/* PMU1CRU_SOFTRST_CON01 */
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13),
|
||||
|
||||
/* PMU1CRU_SOFTRST_CON02 */
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15),
|
||||
|
||||
/* PMU1CRU_SOFTRST_CON03 */
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15),
|
||||
|
||||
/* PMU1CRU_SOFTRST_CON04 */
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10),
|
||||
|
||||
/* PMU1CRU_SOFTRST_CON05 */
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
|
||||
RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),
|
||||
|
||||
/* SECURECRU_SOFTRST_CON00 */
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
|
||||
|
||||
/* SECURECRU_SOFTRST_CON01 */
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15),
|
||||
|
||||
/* SECURECRU_SOFTRST_CON02 */
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15),
|
||||
|
||||
/* SECURECRU_SOFTRST_CON03 */
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5),
|
||||
RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6),
|
||||
};
|
||||
|
||||
int rk3588_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
|
||||
{
|
||||
return rockchip_reset_bind_lut(pdev, rk3588_register_offset,
|
||||
reg_offset, reg_number);
|
||||
}
|
||||
|
|
@ -227,10 +227,10 @@ static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
|
|||
struct rockchip_sfc *sfc = dev_get_plat(bus);
|
||||
|
||||
sfc->regbase = dev_read_addr_ptr(bus);
|
||||
if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
|
||||
sfc->use_dma = false;
|
||||
else
|
||||
sfc->use_dma = true;
|
||||
sfc->use_dma = !dev_read_bool(bus, "rockchip,sfc-no-dma");
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_BUILD) && sfc->use_dma)
|
||||
sfc->use_dma = !dev_read_bool(bus, "u-boot,spl-sfc-no-dma");
|
||||
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
int ret;
|
||||
|
|
|
|||
Loading…
Reference in a new issue