Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-tegra
- Add support for Jetson Nano, plus miscellaneous other fixes found during Nano bringup. - Add Igor's update_uboot wrapper patches.
This commit is contained in:
Tom Rini
commit
60f1cc529c
41 changed files with 757 additions and 1420 deletions
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@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
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"b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
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}
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void __weak board_cleanup_before_linux(void){}
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int cleanup_before_linux(void)
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{
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/*
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@ -40,6 +42,9 @@ int cleanup_before_linux(void)
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*
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* disable interrupt and turn off caches etc ...
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*/
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board_cleanup_before_linux();
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disable_interrupts();
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/*
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@ -180,7 +180,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-e2220-1170.dtb \
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tegra210-p2371-0000.dtb \
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tegra210-p2371-2180.dtb \
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tegra210-p2571.dtb
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tegra210-p2571.dtb \
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tegra210-p3450-0000.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-3720-db.dtb \
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@ -12,6 +12,8 @@
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aliases {
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i2c0 = "/i2c@7000d000";
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i2c2 = "/i2c@7000c400";
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i2c3 = "/i2c@7000c500";
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mmc0 = "/sdhci@700b0600";
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mmc1 = "/sdhci@700b0000";
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usb0 = "/usb@7d000000";
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@ -85,6 +87,16 @@
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non-removable;
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};
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i2c@7000c400 {
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status = "okay";
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clock-frequency = <400000>;
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};
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i2c@7000c500 {
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status = "okay";
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clock-frequency = <400000>;
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};
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <400000>;
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147
arch/arm/dts/tegra210-p3450-0000.dts
Normal file
147
arch/arm/dts/tegra210-p3450-0000.dts
Normal file
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@ -0,0 +1,147 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019-2020 NVIDIA Corporation <www.nvidia.com>
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*/
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/dts-v1/;
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#include "tegra210.dtsi"
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/ {
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model = "NVIDIA Jetson Nano Developer Kit";
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compatible = "nvidia,p3450-0000", "nvidia,tegra210";
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chosen {
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stdout-path = &uarta;
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};
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aliases {
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ethernet = "/pcie@1003000/pci@2,0/ethernet@0,0";
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i2c0 = "/i2c@7000d000";
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i2c2 = "/i2c@7000c400";
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i2c3 = "/i2c@7000c500";
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i2c4 = "/i2c@7000c700";
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mmc0 = "/sdhci@700b0600";
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mmc1 = "/sdhci@700b0000";
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spi0 = "/spi@70410000";
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usb0 = "/usb@7d000000";
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};
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memory {
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reg = <0x0 0x80000000 0x0 0xc0000000>;
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};
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pcie@1003000 {
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status = "okay";
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pci@1,0 {
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status = "okay";
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};
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pci@2,0 {
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status = "okay";
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ethernet@0,0 {
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reg = <0x000000 0 0 0 0>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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};
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};
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};
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serial@70006000 {
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status = "okay";
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};
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padctl@7009f000 {
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pinctrl-0 = <&padctl_default>;
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pinctrl-names = "default";
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padctl_default: pinmux {
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xusb {
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nvidia,lanes = "otg-1", "otg-2";
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nvidia,function = "xusb";
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nvidia,iddq = <0>;
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};
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usb3 {
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nvidia,lanes = "pcie-5", "pcie-6";
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nvidia,function = "usb3";
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nvidia,iddq = <0>;
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};
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pcie-x1 {
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nvidia,lanes = "pcie-0";
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nvidia,function = "pcie-x1";
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nvidia,iddq = <0>;
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};
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pcie-x4 {
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nvidia,lanes = "pcie-1", "pcie-2",
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"pcie-3", "pcie-4";
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nvidia,function = "pcie-x4";
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nvidia,iddq = <0>;
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};
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sata {
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nvidia,lanes = "sata-0";
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nvidia,function = "sata";
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nvidia,iddq = <0>;
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};
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};
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};
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sdhci@700b0000 {
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status = "okay";
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cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
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power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
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bus-width = <4>;
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};
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sdhci@700b0600 {
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status = "okay";
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bus-width = <8>;
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non-removable;
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};
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i2c@7000c400 {
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status = "okay";
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clock-frequency = <400000>;
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};
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i2c@7000c500 {
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status = "okay";
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clock-frequency = <400000>;
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};
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i2c@7000c700 {
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status = "okay";
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clock-frequency = <400000>;
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};
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i2c@7000d000 {
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status = "okay";
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clock-frequency = <400000>;
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};
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spi@70410000 {
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status = "okay";
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spi-max-frequency = <80000000>;
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};
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usb@7d000000 {
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status = "okay";
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dr_mode = "peripheral";
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock@0 {
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compatible = "fixed-clock";
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reg = <0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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};
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@ -2,7 +2,7 @@
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/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Portions Copyright (C) 2011-2012 NVIDIA Corporation
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* Portions Copyright (C) 2011-2012,2019 NVIDIA Corporation
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*/
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#ifndef __TEGRA_MMC_H_
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@ -52,7 +52,7 @@ struct tegra_mmc {
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unsigned char admaerr; /* offset 54h */
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unsigned char res4[3]; /* RESERVED, offset 55h-57h */
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unsigned long admaaddr; /* offset 58h-5Fh */
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unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
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unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
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unsigned short slotintstatus; /* offset FCh */
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unsigned short hcver; /* HOST Version */
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unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
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@ -127,11 +127,23 @@ struct tegra_mmc {
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#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
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/* SDMMC1/3 settings from section 24.6 of T30 TRM */
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/* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */
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#define MEMCOMP_PADCTRL_VREF 7
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#define AUTO_CAL_ENABLED (1 << 29)
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#define AUTO_CAL_ENABLE (1 << 29)
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#define AUTO_CAL_ACTIVE (1 << 31)
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#define AUTO_CAL_START (1 << 31)
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#if defined(CONFIG_TEGRA210)
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#define AUTO_CAL_PD_OFFSET (0x7D << 8)
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#define AUTO_CAL_PU_OFFSET (0 << 0)
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#define IO_TRIM_BYPASS_MASK (1 << 2)
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#define TRIM_VAL_SHIFT 24
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#define TRIM_VAL_MASK (0x1F << TRIM_VAL_SHIFT)
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#define TAP_VAL_SHIFT 16
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#define TAP_VAL_MASK (0xFF << TAP_VAL_SHIFT)
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#else
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#define AUTO_CAL_PD_OFFSET (0x70 << 8)
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#define AUTO_CAL_PU_OFFSET (0x62 << 0)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __TEGRA_MMC_H_ */
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@ -16,6 +16,7 @@ struct tegra_xusb_phy;
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struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
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void tegra_xusb_padctl_init(void);
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void tegra_xusb_padctl_exit(void);
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int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
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int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);
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@ -181,6 +181,12 @@ int board_init(void)
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return nvidia_board_init();
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}
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void board_cleanup_before_linux(void)
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{
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/* power down UPHY PLL */
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tegra_xusb_padctl_exit();
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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static void __gpio_early_init(void)
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{
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@ -211,6 +217,31 @@ int board_early_init_f(void)
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arch_timer_init();
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#endif
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#if defined(CONFIG_DISABLE_SDMMC1_EARLY)
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/*
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* Turn off (reset/disable) SDMMC1 on Nano here, before GPIO INIT.
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* We do this because earlier bootloaders have enabled power to
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* SDMMC1 on Nano, and toggling power-gpio (PZ3) in pinmux_init()
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* results in power being back-driven into the SD-card and SDMMC1
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* HW, which is 'bad' as per the HW team.
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*
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* From the HW team: "LDO2 from the PMIC has already been set to 3.3v in
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* nvtboot/CBoot on Nano (for SD-card boot). So when U-Boot's GPIO_INIT
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* table sets PZ3 to OUT0 as per the pinmux spreadsheet, it turns off
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* the loadswitch. When PZ3 is 0 and not driving, essentially the SDCard
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* voltage turns off. Since the SDCard voltage is no longer there, the
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* SDMMC CLK/DAT lines are backdriving into what essentially is a
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* powered-off SDCard, that's why the voltage drops from 3.3V to ~1.6V"
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*
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* Note that this can probably be removed when we change over to storing
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* all BL components on QSPI on Nano, and U-Boot then becomes the first
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* one to turn on SDMMC1 power. Another fix would be to have CBoot
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* disable power/gate SDMMC1 off before handing off to U-Boot/kernel.
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*/
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reset_set_enable(PERIPH_ID_SDMMC1, 1);
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clock_set_enable(PERIPH_ID_SDMMC1, 0);
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#endif /* CONFIG_DISABLE_SDMMC1_EARLY */
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pinmux_init();
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board_init_uart_f();
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|
|
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@ -35,6 +35,12 @@ config TARGET_P2571
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|||
help
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||||
P2571 is a P2530 married to a P1963 I/O board
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config TARGET_P3450_0000
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bool "NVIDIA Jetson Nano Developer Kit"
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select BOARD_LATE_INIT
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help
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||||
P3450-0000 is a P3448 CPU board married to a P3449 I/O board.
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|
||||
endchoice
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config SYS_SOC
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|
@ -44,5 +50,6 @@ source "board/nvidia/e2220-1170/Kconfig"
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source "board/nvidia/p2371-0000/Kconfig"
|
||||
source "board/nvidia/p2371-2180/Kconfig"
|
||||
source "board/nvidia/p2571/Kconfig"
|
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source "board/nvidia/p3450-0000/Kconfig"
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|
||||
endif
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||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2013-2015
|
||||
# (C) Copyright 2013-2020
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
|
|
@ -7,6 +7,5 @@
|
|||
|
||||
obj-y += clock.o
|
||||
obj-y += funcmux.o
|
||||
obj-y += pinmux.o
|
||||
obj-y += xusb-padctl.o
|
||||
obj-y += ../xusb-padctl-common.o
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* (C) Copyright 2013-2020
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
|
|
@ -333,7 +333,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
|
|||
TYPE(PERIPHC_DMIC3, CLOCK_TYPE_NONE),
|
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TYPE(PERIPHC_APE, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_QSPI, CLOCK_TYPE_PC01C00_C42C41TC40),
|
||||
TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_VI_I2C, CLOCK_TYPE_PC2CC3M_T16),
|
||||
TYPE(PERIPHC_USB2_HSIC_TRK, CLOCK_TYPE_NONE),
|
||||
TYPE(PERIPHC_PEX_SATA_USB_RX_BYP, CLOCK_TYPE_NONE),
|
||||
|
||||
|
|
@ -739,7 +739,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
|
|||
if (!clock_periph_id_isvalid(periph_id))
|
||||
return -1;
|
||||
|
||||
internal_id = periph_id_to_internal_id[periph_id];
|
||||
internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
|
||||
if (!periphc_internal_id_isvalid(internal_id))
|
||||
return -1;
|
||||
|
||||
|
|
@ -765,7 +765,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
|
|||
if (!clock_periph_id_isvalid(periph_id))
|
||||
return CLOCK_ID_NONE;
|
||||
|
||||
internal_id = periph_id_to_internal_id[periph_id];
|
||||
internal_id = INTERNAL_ID(periph_id_to_internal_id[periph_id]);
|
||||
if (!periphc_internal_id_isvalid(internal_id))
|
||||
return CLOCK_ID_NONE;
|
||||
|
||||
|
|
@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
|
|||
value &= ~PLLE_SS_CNTL_INTERP_RESET;
|
||||
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
|
||||
|
||||
/* 7. Enable HW power sequencer for PLLE */
|
||||
|
||||
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
|
||||
value &= ~PLLE_MISC_IDDQ_SWCTL;
|
||||
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
|
||||
|
||||
value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
|
||||
value &= ~PLLE_AUX_SS_SWCTL;
|
||||
value &= ~PLLE_AUX_ENABLE_SWCTL;
|
||||
value |= PLLE_AUX_SS_SEQ_INCLUDE;
|
||||
value |= PLLE_AUX_USE_LOCKDET;
|
||||
writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
|
||||
|
||||
/* 8. Wait 1 us */
|
||||
|
||||
udelay(1);
|
||||
value |= PLLE_AUX_SEQ_ENABLE;
|
||||
writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,194 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
|
||||
#define PIN(pin, f0, f1, f2, f3) \
|
||||
{ \
|
||||
.funcs = { \
|
||||
PMUX_FUNC_##f0, \
|
||||
PMUX_FUNC_##f1, \
|
||||
PMUX_FUNC_##f2, \
|
||||
PMUX_FUNC_##f3, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define PIN_RESERVED {}
|
||||
|
||||
static const struct pmux_pingrp_desc tegra210_pingroups[] = {
|
||||
/* pin, f0, f1, f2, f3 */
|
||||
/* Offset 0x3000 */
|
||||
PIN(SDMMC1_CLK_PM0, SDMMC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_CMD_PM1, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT3_PM2, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT2_PM3, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT1_PM4, SDMMC1, SPI3, RSVD2, RSVD3),
|
||||
PIN(SDMMC1_DAT0_PM5, SDMMC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x301c */
|
||||
PIN(SDMMC3_CLK_PP0, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_CMD_PP1, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT0_PP5, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT1_PP4, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT2_PP3, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SDMMC3_DAT3_PP2, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x3038 */
|
||||
PIN(PEX_L0_RST_N_PA0, PE0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_L0_CLKREQ_N_PA1, PE0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_WAKE_N_PA2, PE, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_L1_RST_N_PA3, PE1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PEX_L1_CLKREQ_N_PA4, PE1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SATA_LED_ACTIVE_PA5, SATA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_MOSI_PC0, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_MISO_PC1, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_SCK_PC2, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_CS0_PC3, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI1_CS1_PC4, SPI1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI2_MOSI_PB4, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_MISO_PB5, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_SCK_PB6, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_CS0_PB7, SPI2, DTV, RSVD2, RSVD3),
|
||||
PIN(SPI2_CS1_PDD0, SPI2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_MOSI_PC7, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_MISO_PD0, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_SCK_PC5, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPI4_CS0_PC6, SPI4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_SCK_PEE0, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_CS_N_PEE1, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO0_PEE2, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO1_PEE3, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO2_PEE4, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(QSPI_IO3_PEE5, QSPI, RSVD1, RSVD2, RSVD3),
|
||||
PIN_RESERVED,
|
||||
/* Offset 0x30a4 */
|
||||
PIN(DMIC1_CLK_PE0, DMIC1, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC1_DAT_PE1, DMIC1, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC2_CLK_PE2, DMIC2, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC2_DAT_PE3, DMIC2, I2S3, RSVD2, RSVD3),
|
||||
PIN(DMIC3_CLK_PE4, DMIC3, I2S5A, RSVD2, RSVD3),
|
||||
PIN(DMIC3_DAT_PE5, DMIC3, I2S5A, RSVD2, RSVD3),
|
||||
PIN(GEN1_I2C_SCL_PJ1, I2C1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN1_I2C_SDA_PJ0, I2C1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN2_I2C_SCL_PJ2, I2C2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN2_I2C_SDA_PJ3, I2C2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN3_I2C_SCL_PF0, I2C3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GEN3_I2C_SDA_PF1, I2C3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM_I2C_SCL_PS2, I2C3, I2CVI, RSVD2, RSVD3),
|
||||
PIN(CAM_I2C_SDA_PS3, I2C3, I2CVI, RSVD2, RSVD3),
|
||||
PIN(PWR_I2C_SCL_PY3, I2CPMU, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PWR_I2C_SDA_PY4, I2CPMU, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_TX_PU0, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_RX_PU1, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_RTS_PU2, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART1_CTS_PU3, UARTA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(UART2_TX_PG0, UARTB, I2S4A, SPDIF, UART),
|
||||
PIN(UART2_RX_PG1, UARTB, I2S4A, SPDIF, UART),
|
||||
PIN(UART2_RTS_PG2, UARTB, I2S4A, RSVD2, UART),
|
||||
PIN(UART2_CTS_PG3, UARTB, I2S4A, RSVD2, UART),
|
||||
PIN(UART3_TX_PD1, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART3_RX_PD2, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART3_RTS_PD3, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART3_CTS_PD4, UARTC, SPI4, RSVD2, RSVD3),
|
||||
PIN(UART4_TX_PI4, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(UART4_RX_PI5, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(UART4_RTS_PI6, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(UART4_CTS_PI7, UARTD, UART, RSVD2, RSVD3),
|
||||
PIN(DAP1_FS_PB0, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP1_DIN_PB1, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP1_DOUT_PB2, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP1_SCLK_PB3, I2S1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_FS_PAA0, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_DIN_PAA2, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_DOUT_PAA3, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP2_SCLK_PAA1, I2S2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_FS_PJ4, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_DIN_PJ5, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_DOUT_PJ6, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DAP4_SCLK_PJ7, I2S4B, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM1_MCLK_PS0, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM2_MCLK_PS1, EXTPERIPH3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(JTAG_RTCK, JTAG, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CLK_32K_IN, CLK, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CLK_32K_OUT_PY5, SOC, BLINK, RSVD2, RSVD3),
|
||||
PIN(BATT_BCL, BCL, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CLK_REQ, SYS, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CPU_PWR_REQ, CPU, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PWR_INT_N, PMI, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SHUTDOWN, SHUTDOWN, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CORE_PWR_REQ, CORE, RSVD1, RSVD2, RSVD3),
|
||||
PIN(AUD_MCLK_PBB0, AUD, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DVFS_PWM_PBB1, RSVD0, CLDVFS, SPI3, RSVD3),
|
||||
PIN(DVFS_CLK_PBB2, RSVD0, CLDVFS, SPI3, RSVD3),
|
||||
PIN(GPIO_X1_AUD_PBB3, RSVD0, RSVD1, SPI3, RSVD3),
|
||||
PIN(GPIO_X3_AUD_PBB4, RSVD0, RSVD1, SPI3, RSVD3),
|
||||
PIN(PCC7, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(HDMI_CEC_PCC0, CEC, RSVD1, RSVD2, RSVD3),
|
||||
PIN(HDMI_INT_DP_HPD_PCC1, DP, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPDIF_OUT_PCC2, SPDIF, RSVD1, RSVD2, RSVD3),
|
||||
PIN(SPDIF_IN_PCC3, SPDIF, RSVD1, RSVD2, RSVD3),
|
||||
PIN(USB_VBUS_EN0_PCC4, USB, RSVD1, RSVD2, RSVD3),
|
||||
PIN(USB_VBUS_EN1_PCC5, USB, RSVD1, RSVD2, RSVD3),
|
||||
PIN(DP_HPD0_PCC6, DP, RSVD1, RSVD2, RSVD3),
|
||||
PIN(WIFI_EN_PH0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(WIFI_RST_PH1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(WIFI_WAKE_AP_PH2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(AP_WAKE_BT_PH3, RSVD0, UARTB, SPDIF, RSVD3),
|
||||
PIN(BT_RST_PH4, RSVD0, UARTB, SPDIF, RSVD3),
|
||||
PIN(BT_WAKE_AP_PH5, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(AP_WAKE_NFC_PH7, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(NFC_EN_PI0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(NFC_INT_PI1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GPS_EN_PI2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(GPS_RST_PI3, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM_RST_PS4, VGP1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM_AF_EN_PS5, VIMCLK, VGP2, RSVD2, RSVD3),
|
||||
PIN(CAM_FLASH_EN_PS6, VIMCLK, VGP3, RSVD2, RSVD3),
|
||||
PIN(CAM1_PWDN_PS7, VGP4, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM2_PWDN_PT0, VGP5, RSVD1, RSVD2, RSVD3),
|
||||
PIN(CAM1_STROBE_PT1, VGP6, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_TE_PY2, DISPLAYA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_BL_PWM_PV0, DISPLAYA, PWM0, SOR0, RSVD3),
|
||||
PIN(LCD_BL_EN_PV1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_RST_PV2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_GPIO1_PV3, DISPLAYB, RSVD1, RSVD2, RSVD3),
|
||||
PIN(LCD_GPIO2_PV4, DISPLAYB, PWM1, RSVD2, SOR1),
|
||||
PIN(AP_READY_PV5, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TOUCH_RST_PV6, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TOUCH_CLK_PV7, TOUCH, RSVD1, RSVD2, RSVD3),
|
||||
PIN(MODEM_WAKE_AP_PX0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TOUCH_INT_PX1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(MOTION_INT_PX2, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(ALS_PROX_INT_PX3, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(TEMP_ALERT_PX4, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_POWER_ON_PX5, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_VOL_UP_PX6, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_VOL_DOWN_PX7, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_SLIDE_SW_PY0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(BUTTON_HOME_PY1, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PA6, SATA, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PE6, RSVD0, I2S5A, PWM2, RSVD3),
|
||||
PIN(PE7, RSVD0, I2S5A, PWM3, RSVD3),
|
||||
PIN(PH6, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK0, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK1, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK2, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK3, IQC0, I2S5B, RSVD2, RSVD3),
|
||||
PIN(PK4, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK5, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK6, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PK7, IQC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PL0, RSVD0, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PL1, SOC, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ0, VIMCLK2, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ1, VIMCLK2, SDMMC1, RSVD2, RSVD3),
|
||||
PIN(PZ2, SDMMC3, CCLA, RSVD2, RSVD3),
|
||||
PIN(PZ3, SDMMC3, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ4, SDMMC1, RSVD1, RSVD2, RSVD3),
|
||||
PIN(PZ5, SOC, RSVD1, RSVD2, RSVD3),
|
||||
};
|
||||
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra210_pingroups;
|
||||
|
|
@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
|
|||
return tegra_xusb_padctl_disable(phy->padctl);
|
||||
}
|
||||
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX 0x28
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
|
||||
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
|
||||
|
||||
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
|
||||
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
|
||||
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
|
||||
|
|
@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
|
|||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
|
||||
|
||||
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
|
||||
value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
|
||||
value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
|
||||
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
|
||||
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
|
||||
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
|
||||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
|
||||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
|
||||
|
||||
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
|
||||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
|
||||
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
|
||||
|
||||
udelay(1);
|
||||
|
||||
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
|
||||
value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
|
||||
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
|
||||
|
||||
debug("< %s()\n", __func__);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
|
|||
ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
|
||||
debug("%s: done, ret=%d\n", __func__, ret);
|
||||
}
|
||||
|
||||
void tegra_xusb_padctl_exit(void)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
debug("> %s\n", __func__);
|
||||
|
||||
value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
|
||||
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
|
||||
padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
|
||||
|
||||
value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
|
||||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
|
||||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
|
||||
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
|
||||
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
|
||||
padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
|
||||
|
||||
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
|
||||
while (padctl.enable)
|
||||
tegra_xusb_padctl_disable(&padctl);
|
||||
|
||||
debug("< %s()\n", __func__);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
|
|||
void __weak tegra_xusb_padctl_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void __weak tegra_xusb_padctl_exit(void)
|
||||
{
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* (C) Copyright 2013-2019
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
#include "pinmux-config-e2220-1170.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
|
|
@ -30,21 +29,3 @@ void pin_mux_mmc(void)
|
|||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(e2220_1170_gpio_inits,
|
||||
ARRAY_SIZE(e2220_1170_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(e2220_1170_pingrps,
|
||||
ARRAY_SIZE(e2220_1170_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(e2220_1170_drvgrps,
|
||||
ARRAY_SIZE(e2220_1170_drvgrps));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,276 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py e2220-1170".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_E2220_1170_H_
|
||||
#define _PINMUX_CONFIG_E2220_1170_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(A, 6, IN),
|
||||
GPIO_INIT(B, 4, IN),
|
||||
GPIO_INIT(E, 6, IN),
|
||||
GPIO_INIT(G, 2, OUT0),
|
||||
GPIO_INIT(G, 3, OUT0),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 1, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(H, 6, OUT0),
|
||||
GPIO_INIT(H, 7, OUT0),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(I, 3, OUT0),
|
||||
GPIO_INIT(K, 0, IN),
|
||||
GPIO_INIT(K, 1, OUT0),
|
||||
GPIO_INIT(K, 2, OUT0),
|
||||
GPIO_INIT(K, 3, OUT0),
|
||||
GPIO_INIT(K, 4, IN),
|
||||
GPIO_INIT(K, 5, OUT0),
|
||||
GPIO_INIT(K, 6, IN),
|
||||
GPIO_INIT(K, 7, OUT0),
|
||||
GPIO_INIT(L, 0, OUT0),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 5, OUT0),
|
||||
GPIO_INIT(S, 6, OUT0),
|
||||
GPIO_INIT(S, 7, OUT0),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, OUT0),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 2, OUT0),
|
||||
GPIO_INIT(V, 3, IN),
|
||||
GPIO_INIT(V, 5, OUT0),
|
||||
GPIO_INIT(V, 6, OUT0),
|
||||
GPIO_INIT(X, 0, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 2, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 5, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 0, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 4, OUT0),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(BB, 4, IN),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 5, OUT0),
|
||||
GPIO_INIT(CC, 6, IN),
|
||||
GPIO_INIT(CC, 7, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config e2220_1170_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_WAKE_N_PA2, PE, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, SPI1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, SPI1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, UARTC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, DMIC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, DMIC2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DMIC3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, DMIC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, UART, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UART, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, SPDIF, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, SPDIF, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, QSPI, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, QSPI, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config e2220_1170_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_E2220_1170_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* (C) Copyright 2013-2019
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
#include "pinmux-config-p2371-0000.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
|
|
@ -30,21 +29,3 @@ void pin_mux_mmc(void)
|
|||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(p2371_0000_gpio_inits,
|
||||
ARRAY_SIZE(p2371_0000_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(p2371_0000_pingrps,
|
||||
ARRAY_SIZE(p2371_0000_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(p2371_0000_drvgrps,
|
||||
ARRAY_SIZE(p2371_0000_drvgrps));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,267 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py p2371-0000".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_P2371_0000_H_
|
||||
#define _PINMUX_CONFIG_P2371_0000_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(E, 4, OUT0),
|
||||
GPIO_INIT(E, 6, IN),
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(G, 3, OUT0),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(H, 6, OUT0),
|
||||
GPIO_INIT(H, 7, OUT0),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(I, 3, OUT0),
|
||||
GPIO_INIT(K, 4, IN),
|
||||
GPIO_INIT(K, 5, OUT0),
|
||||
GPIO_INIT(K, 6, IN),
|
||||
GPIO_INIT(K, 7, OUT0),
|
||||
GPIO_INIT(L, 0, OUT0),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 5, OUT0),
|
||||
GPIO_INIT(S, 6, OUT0),
|
||||
GPIO_INIT(S, 7, OUT0),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, OUT0),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 2, OUT0),
|
||||
GPIO_INIT(V, 5, OUT0),
|
||||
GPIO_INIT(V, 6, OUT0),
|
||||
GPIO_INIT(V, 7, OUT1),
|
||||
GPIO_INIT(X, 0, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 2, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 5, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 4, OUT0),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(BB, 3, OUT0),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 6, IN),
|
||||
GPIO_INIT(CC, 7, OUT0),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config p2371_0000_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, I2S1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, SPI1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, SPI1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, SPI4, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, SPI4, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, DMIC1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, DMIC1, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, DMIC2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, DMIC2, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, I2S5B, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(DP_HPD0_PCC6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config p2371_0000_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_P2371_0000_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* (C) Copyright 2013-2019
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
|
|
@ -13,7 +13,6 @@
|
|||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch-tegra/cboot.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
#include "pinmux-config-p2371-2180.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
|
|
@ -57,24 +56,6 @@ void pin_mux_mmc(void)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(p2371_2180_gpio_inits,
|
||||
ARRAY_SIZE(p2371_2180_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(p2371_2180_pingrps,
|
||||
ARRAY_SIZE(p2371_2180_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(p2371_2180_drvgrps,
|
||||
ARRAY_SIZE(p2371_2180_drvgrps));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -1,278 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py p2371-2180".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_P2371_2180_H_
|
||||
#define _PINMUX_CONFIG_P2371_2180_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(B, 0, IN),
|
||||
GPIO_INIT(B, 1, IN),
|
||||
GPIO_INIT(B, 2, IN),
|
||||
GPIO_INIT(B, 3, IN),
|
||||
GPIO_INIT(C, 0, IN),
|
||||
GPIO_INIT(C, 1, IN),
|
||||
GPIO_INIT(C, 2, IN),
|
||||
GPIO_INIT(C, 3, IN),
|
||||
GPIO_INIT(C, 4, IN),
|
||||
GPIO_INIT(E, 4, IN),
|
||||
GPIO_INIT(E, 5, IN),
|
||||
GPIO_INIT(E, 6, IN),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 1, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(H, 6, IN),
|
||||
GPIO_INIT(H, 7, IN),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(I, 2, OUT0),
|
||||
GPIO_INIT(K, 4, IN),
|
||||
GPIO_INIT(K, 5, OUT0),
|
||||
GPIO_INIT(K, 6, IN),
|
||||
GPIO_INIT(K, 7, IN),
|
||||
GPIO_INIT(L, 1, IN),
|
||||
GPIO_INIT(S, 4, OUT0),
|
||||
GPIO_INIT(S, 5, OUT0),
|
||||
GPIO_INIT(S, 6, OUT0),
|
||||
GPIO_INIT(S, 7, OUT0),
|
||||
GPIO_INIT(T, 0, OUT0),
|
||||
GPIO_INIT(T, 1, OUT0),
|
||||
GPIO_INIT(U, 2, IN),
|
||||
GPIO_INIT(U, 3, IN),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 2, OUT0),
|
||||
GPIO_INIT(V, 3, IN),
|
||||
GPIO_INIT(V, 5, OUT0),
|
||||
GPIO_INIT(V, 6, OUT0),
|
||||
GPIO_INIT(X, 0, IN),
|
||||
GPIO_INIT(X, 1, IN),
|
||||
GPIO_INIT(X, 2, IN),
|
||||
GPIO_INIT(X, 3, IN),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 5, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 0, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 2, IN),
|
||||
GPIO_INIT(Z, 3, OUT0),
|
||||
GPIO_INIT(BB, 0, IN),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(BB, 3, IN),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config p2371_2180_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, PE0, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, PE0, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_WAKE_N_PA2, PE, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_RST_N_PA3, PE1, NORMAL, NORMAL, OUTPUT, DISABLE, HIGH),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, PE1, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, SATA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, SPI2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, SPI4, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, SPI4, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, UARTC, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, UARTC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, UARTB, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, UARTB, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DAP4_FS_PJ4, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, I2S4B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, I2S5B, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, TOUCH, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, DISPLAYA, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DP_HPD0_PCC6, DP, DOWN, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, SPI2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config p2371_2180_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_P2371_2180_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2013-2015
|
||||
* (C) Copyright 2013-2019
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*/
|
||||
|
||||
|
|
@ -10,7 +10,6 @@
|
|||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/gpio.h>
|
||||
#include "max77620_init.h"
|
||||
#include "pinmux-config-p2571.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
|
|
@ -32,24 +31,6 @@ void pin_mux_mmc(void)
|
|||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: pinmux_init
|
||||
* Description: Do individual peripheral pinmux configs
|
||||
*/
|
||||
void pinmux_init(void)
|
||||
{
|
||||
pinmux_clear_tristate_input_clamping();
|
||||
|
||||
gpio_config_table(p2571_gpio_inits,
|
||||
ARRAY_SIZE(p2571_gpio_inits));
|
||||
|
||||
pinmux_config_pingrp_table(p2571_pingrps,
|
||||
ARRAY_SIZE(p2571_pingrps));
|
||||
|
||||
pinmux_config_drvgrp_table(p2571_drvgrps,
|
||||
ARRAY_SIZE(p2571_drvgrps));
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: start_cpu_fan
|
||||
* Description: Enable/start PWM CPU fan on P2571
|
||||
|
|
|
|||
|
|
@ -1,242 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
/*
|
||||
* THIS FILE IS AUTO-GENERATED - DO NOT EDIT!
|
||||
*
|
||||
* To generate this file, use the tegra-pinmux-scripts tool available from
|
||||
* https://github.com/NVIDIA/tegra-pinmux-scripts
|
||||
* Run "board-to-uboot.py p2571".
|
||||
*/
|
||||
|
||||
#ifndef _PINMUX_CONFIG_P2571_H_
|
||||
#define _PINMUX_CONFIG_P2571_H_
|
||||
|
||||
#define GPIO_INIT(_port, _gpio, _init) \
|
||||
{ \
|
||||
.gpio = TEGRA_GPIO(_port, _gpio), \
|
||||
.init = TEGRA_GPIO_INIT_##_init, \
|
||||
}
|
||||
|
||||
static const struct tegra_gpio_config p2571_gpio_inits[] = {
|
||||
/* port, pin, init_val */
|
||||
GPIO_INIT(A, 0, IN),
|
||||
GPIO_INIT(A, 5, IN),
|
||||
GPIO_INIT(D, 4, IN),
|
||||
GPIO_INIT(E, 4, OUT0),
|
||||
GPIO_INIT(G, 0, IN),
|
||||
GPIO_INIT(H, 0, OUT0),
|
||||
GPIO_INIT(H, 2, IN),
|
||||
GPIO_INIT(H, 3, OUT0),
|
||||
GPIO_INIT(H, 4, OUT0),
|
||||
GPIO_INIT(H, 5, IN),
|
||||
GPIO_INIT(I, 0, OUT0),
|
||||
GPIO_INIT(I, 1, IN),
|
||||
GPIO_INIT(V, 1, OUT0),
|
||||
GPIO_INIT(V, 6, OUT1),
|
||||
GPIO_INIT(X, 4, IN),
|
||||
GPIO_INIT(X, 6, IN),
|
||||
GPIO_INIT(X, 7, IN),
|
||||
GPIO_INIT(Y, 1, IN),
|
||||
GPIO_INIT(Z, 0, IN),
|
||||
GPIO_INIT(Z, 4, OUT0),
|
||||
GPIO_INIT(BB, 2, OUT0),
|
||||
GPIO_INIT(CC, 1, IN),
|
||||
GPIO_INIT(CC, 3, IN),
|
||||
};
|
||||
|
||||
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
|
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
}
|
||||
|
||||
static const struct pmux_pingrp_config p2571_pingrps[] = {
|
||||
/* pingrp, mux, pull, tri, e_input, od, e_io_hv */
|
||||
PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
|
||||
PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
|
||||
PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
|
||||
PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
|
||||
};
|
||||
|
||||
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
|
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
}
|
||||
|
||||
static const struct pmux_drvgrp_config p2571_drvgrps[] = {
|
||||
};
|
||||
|
||||
#endif /* PINMUX_CONFIG_P2571_H */
|
||||
12
board/nvidia/p3450-0000/Kconfig
Normal file
12
board/nvidia/p3450-0000/Kconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
if TARGET_P3450_0000
|
||||
|
||||
config SYS_BOARD
|
||||
default "p3450-0000"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "nvidia"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "p3450-0000"
|
||||
|
||||
endif
|
||||
6
board/nvidia/p3450-0000/MAINTAINERS
Normal file
6
board/nvidia/p3450-0000/MAINTAINERS
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
P3450-0000 BOARD
|
||||
M: Tom Warren <twarren@nvidia.com>
|
||||
S: Maintained
|
||||
F: board/nvidia/p3450-0000/
|
||||
F: include/configs/p3450-0000.h
|
||||
F: configs/p3450-0000_defconfig
|
||||
8
board/nvidia/p3450-0000/Makefile
Normal file
8
board/nvidia/p3450-0000/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
#
|
||||
# (C) Copyright 2018
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += p3450-0000.o
|
||||
178
board/nvidia/p3450-0000/p3450-0000.c
Normal file
178
board/nvidia/p3450-0000/p3450-0000.c
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2018-2019
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <i2c.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <pca953x.h>
|
||||
#include <asm/arch-tegra/cboot.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include "../p2571/max77620_init.h"
|
||||
|
||||
void pin_mux_mmc(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO2 to 3.3V for SD card power */
|
||||
debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return;
|
||||
}
|
||||
/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xF2;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret);
|
||||
|
||||
/* Disable LDO4 discharge */
|
||||
ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1);
|
||||
if (ret) {
|
||||
printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret);
|
||||
} else {
|
||||
val &= ~BIT(1); /* ADE */
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret);
|
||||
}
|
||||
|
||||
/* Set MBLPD */
|
||||
ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
|
||||
if (ret) {
|
||||
printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
|
||||
} else {
|
||||
val |= BIT(6); /* MBLPD */
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI_TEGRA
|
||||
int tegra_pcie_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
uchar val;
|
||||
int ret;
|
||||
|
||||
/* Turn on MAX77620 LDO1 to 1.05V for PEX power */
|
||||
debug("%s: Set LDO1 for PEX power to 1.05V\n", __func__);
|
||||
ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find MAX77620 I2C chip\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
/* 0xCA for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
|
||||
val = 0xCA;
|
||||
ret = dm_i2c_write(dev, MAX77620_CNFG1_L1_REG, &val, 1);
|
||||
if (ret)
|
||||
printf("i2c_write 0 0x3c 0x25 failed: %d\n", ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* PCI */
|
||||
|
||||
static void ft_mac_address_setup(void *fdt)
|
||||
{
|
||||
const void *cboot_fdt = (const void *)cboot_boot_x0;
|
||||
uint8_t mac[ETH_ALEN], local_mac[ETH_ALEN];
|
||||
const char *path;
|
||||
int offset, err;
|
||||
|
||||
err = cboot_get_ethaddr(cboot_fdt, local_mac);
|
||||
if (err < 0)
|
||||
memset(local_mac, 0, ETH_ALEN);
|
||||
|
||||
path = fdt_get_alias(fdt, "ethernet");
|
||||
if (!path)
|
||||
return;
|
||||
|
||||
debug("ethernet alias found: %s\n", path);
|
||||
|
||||
offset = fdt_path_offset(fdt, path);
|
||||
if (offset < 0) {
|
||||
printf("ethernet alias points to absent node %s\n", path);
|
||||
return;
|
||||
}
|
||||
|
||||
if (is_valid_ethaddr(local_mac)) {
|
||||
err = fdt_setprop(fdt, offset, "local-mac-address", local_mac,
|
||||
ETH_ALEN);
|
||||
if (!err)
|
||||
debug("Local MAC address set: %pM\n", local_mac);
|
||||
}
|
||||
|
||||
if (eth_env_get_enetaddr("ethaddr", mac)) {
|
||||
if (memcmp(local_mac, mac, ETH_ALEN) != 0) {
|
||||
err = fdt_setprop(fdt, offset, "mac-address", mac,
|
||||
ETH_ALEN);
|
||||
if (!err)
|
||||
debug("MAC address set: %pM\n", mac);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int ft_copy_carveout(void *dst, const void *src, const char *node)
|
||||
{
|
||||
struct fdt_memory fb;
|
||||
int err;
|
||||
|
||||
err = fdtdec_get_carveout(src, node, "memory-region", 0, &fb);
|
||||
if (err < 0) {
|
||||
if (err != -FDT_ERR_NOTFOUND)
|
||||
printf("failed to get carveout for %s: %d\n", node,
|
||||
err);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
err = fdtdec_set_carveout(dst, node, "memory-region", 0, "framebuffer",
|
||||
&fb);
|
||||
if (err < 0) {
|
||||
printf("failed to set carveout for %s: %d\n", node, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ft_carveout_setup(void *fdt)
|
||||
{
|
||||
const void *cboot_fdt = (const void *)cboot_boot_x0;
|
||||
static const char * const nodes[] = {
|
||||
"/host1x@50000000/dc@54200000",
|
||||
"/host1x@50000000/dc@54240000",
|
||||
};
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nodes); i++) {
|
||||
printf("copying carveout for %s...\n", nodes[i]);
|
||||
|
||||
err = ft_copy_carveout(fdt, cboot_fdt, nodes[i]);
|
||||
if (err < 0) {
|
||||
if (err != -FDT_ERR_NOTFOUND)
|
||||
printf("failed to copy carveout for %s: %d\n",
|
||||
nodes[i], err);
|
||||
|
||||
continue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int ft_board_setup(void *fdt, bd_t *bd)
|
||||
{
|
||||
ft_mac_address_setup(fdt);
|
||||
ft_carveout_setup(fdt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -43,3 +43,4 @@ CONFIG_CI_UDC=y
|
|||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
|
|
|
|||
|
|
@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
|
|||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
|
|
|
|||
|
|
@ -52,3 +52,4 @@ CONFIG_CI_UDC=y
|
|||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
|
|
|
|||
|
|
@ -44,3 +44,4 @@ CONFIG_CI_UDC=y
|
|||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
|
|
|
|||
|
|
@ -36,3 +36,5 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
|
|
|
|||
|
|
@ -36,3 +36,5 @@ CONFIG_TEGRA186_POWER_DOMAIN=y
|
|||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
|
|
|
|||
64
configs/p3450-0000_defconfig
Normal file
64
configs/p3450-0000_defconfig
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TEGRA=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80080000
|
||||
CONFIG_TEGRA210=y
|
||||
CONFIG_TARGET_P3450_0000=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_CONSOLE_MUX=y
|
||||
CONFIG_SYS_STDIO_DEREGISTER=y
|
||||
CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # "
|
||||
# CONFIG_CMD_IMI is not set
|
||||
CONFIG_CMD_DFU=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_OF_LIVE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000"
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_SYS_I2C_TEGRA=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_RTL8169=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCI_TEGRA=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_TEGRA114_SPI=y
|
||||
CONFIG_TEGRA210_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_TEGRA=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0x701a
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
# CONFIG_ENV_IS_IN_MMC is not set
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x1000
|
||||
CONFIG_ENV_OFFSET=0xFFFFE000
|
||||
CONFIG_BOOTP_PREFER_SERVERIP=y
|
||||
CONFIG_POSITION_INDEPENDENT=y
|
||||
CONFIG_DISABLE_SDMMC1_EARLY=y
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
* (C) Copyright 2009 SAMSUNG Electronics
|
||||
* Minkyu Kang <mk7.kang@samsung.com>
|
||||
* Jaehoon Chung <jh80.chung@samsung.com>
|
||||
* Portions Copyright 2011-2016 NVIDIA Corporation
|
||||
* Portions Copyright 2011-2019 NVIDIA Corporation
|
||||
*/
|
||||
|
||||
#include <bouncebuf.h>
|
||||
|
|
@ -15,6 +15,9 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch-tegra/tegra_mmc.h>
|
||||
#include <linux/err.h>
|
||||
#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
|
||||
#include <asm/arch/clock.h>
|
||||
#endif
|
||||
|
||||
struct tegra_mmc_plat {
|
||||
struct mmc_config cfg;
|
||||
|
|
@ -30,6 +33,7 @@ struct tegra_mmc_priv {
|
|||
struct gpio_desc wp_gpio; /* Write Protect GPIO */
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
int mmc_id; /* peripheral id */
|
||||
};
|
||||
|
||||
static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
|
||||
|
|
@ -372,6 +376,25 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
|
|||
|
||||
rate = clk_set_rate(&priv->clk, clock);
|
||||
div = (rate + clock - 1) / clock;
|
||||
|
||||
#if defined(CONFIG_TEGRA210)
|
||||
if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
|
||||
/* clock_adjust_periph_pll_div() chooses a 'bad' clock
|
||||
* on SDMMC1 T210, so skip it here and force a clock
|
||||
* that's been spec'd in the table in the TRM for
|
||||
* card-detect (400KHz).
|
||||
*/
|
||||
uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
|
||||
CLOCK_ID_PERIPH, 24727273, NULL);
|
||||
div = 62;
|
||||
|
||||
debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
|
||||
__func__, effective_rate, div, clock);
|
||||
} else {
|
||||
clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
|
||||
clock, &div);
|
||||
}
|
||||
#endif
|
||||
debug("div = %d\n", div);
|
||||
|
||||
writew(0, &priv->reg->clkcon);
|
||||
|
|
@ -446,16 +469,19 @@ static int tegra_mmc_set_ios(struct udevice *dev)
|
|||
|
||||
static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
|
||||
{
|
||||
#if defined(CONFIG_TEGRA30)
|
||||
#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
|
||||
u32 val;
|
||||
u16 clk_con;
|
||||
int timeout;
|
||||
int id = priv->mmc_id;
|
||||
|
||||
debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
|
||||
debug("%s: sdmmc address = %p, id = %d\n", __func__,
|
||||
priv->reg, id);
|
||||
|
||||
/* Set the pad drive strength for SDMMC1 or 3 only */
|
||||
if (priv->reg != (void *)0x78000000 &&
|
||||
priv->reg != (void *)0x78000400) {
|
||||
if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
|
||||
debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
|
||||
__func__);
|
||||
__func__);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -464,11 +490,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
|
|||
val |= MEMCOMP_PADCTRL_VREF;
|
||||
writel(val, &priv->reg->sdmemcmppadctl);
|
||||
|
||||
/* Disable SD Clock Enable before running auto-cal as per TRM */
|
||||
clk_con = readw(&priv->reg->clkcon);
|
||||
debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
|
||||
clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
||||
writew(clk_con, &priv->reg->clkcon);
|
||||
|
||||
val = readl(&priv->reg->autocalcfg);
|
||||
val &= 0xFFFF0000;
|
||||
val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
|
||||
val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
|
||||
writel(val, &priv->reg->autocalcfg);
|
||||
#endif
|
||||
val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
|
||||
writel(val, &priv->reg->autocalcfg);
|
||||
debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
|
||||
udelay(1);
|
||||
timeout = 100; /* 10 mSec max (100*100uS) */
|
||||
do {
|
||||
val = readl(&priv->reg->autocalsts);
|
||||
udelay(100);
|
||||
} while ((val & AUTO_CAL_ACTIVE) && --timeout);
|
||||
val = readl(&priv->reg->autocalsts);
|
||||
debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
|
||||
__func__, val, timeout);
|
||||
|
||||
/* Re-enable SD Clock Enable when auto-cal is done */
|
||||
clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
|
||||
writew(clk_con, &priv->reg->clkcon);
|
||||
clk_con = readw(&priv->reg->clkcon);
|
||||
debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
|
||||
|
||||
if (timeout == 0) {
|
||||
printf("%s: Warning: Autocal timed out!\n", __func__);
|
||||
/* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_TEGRA210)
|
||||
u32 tap_value, trim_value;
|
||||
|
||||
/* Set tap/trim values for SDMMC1/3 @ <48MHz here */
|
||||
val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */
|
||||
val &= IO_TRIM_BYPASS_MASK;
|
||||
if (id == PERIPH_ID_SDMMC1) {
|
||||
tap_value = 4; /* default */
|
||||
if (val)
|
||||
tap_value = 3;
|
||||
trim_value = 2;
|
||||
} else { /* SDMMC3 */
|
||||
tap_value = 3;
|
||||
trim_value = 3;
|
||||
}
|
||||
|
||||
val = readl(&priv->reg->venclkctl);
|
||||
val &= ~TRIM_VAL_MASK;
|
||||
val |= (trim_value << TRIM_VAL_SHIFT);
|
||||
val &= ~TAP_VAL_MASK;
|
||||
val |= (tap_value << TAP_VAL_SHIFT);
|
||||
writel(val, &priv->reg->venclkctl);
|
||||
debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
|
||||
#endif /* T210 */
|
||||
#endif /* T30/T210 */
|
||||
}
|
||||
|
||||
static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
|
||||
|
|
@ -514,6 +594,13 @@ static int tegra_mmc_init(struct udevice *dev)
|
|||
unsigned int mask;
|
||||
debug(" tegra_mmc_init called\n");
|
||||
|
||||
#if defined(CONFIG_TEGRA210)
|
||||
priv->mmc_id = clock_decode_periph_id(dev);
|
||||
if (priv->mmc_id == PERIPH_ID_NONE) {
|
||||
printf("%s: Missing/invalid peripheral ID\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
tegra_mmc_reset(priv, mmc);
|
||||
|
||||
#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
|
||||
|
|
|
|||
|
|
@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = {
|
|||
{ INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) },
|
||||
{ INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) },
|
||||
{ INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) },
|
||||
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
|
||||
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) },
|
||||
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
/*
|
||||
* NVIDIA Tegra210 QSPI controller driver
|
||||
*
|
||||
* (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com>
|
||||
* (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
@ -41,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
#define QSPI_CMD1_BITLEN_SHIFT 0
|
||||
|
||||
/* COMMAND2 */
|
||||
#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6)
|
||||
#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6)
|
||||
#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0)
|
||||
#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0)
|
||||
#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
|
||||
#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
|
||||
#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
|
||||
#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
|
||||
|
||||
/* TRANSFER STATUS */
|
||||
#define QSPI_XFER_STS_RDY BIT(30)
|
||||
|
|
@ -96,10 +97,8 @@ struct tegra210_qspi_priv {
|
|||
static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
|
||||
{
|
||||
struct tegra_spi_platdata *plat = bus->platdata;
|
||||
const void *blob = gd->fdt_blob;
|
||||
int node = dev_of_offset(bus);
|
||||
|
||||
plat->base = devfdt_get_addr(bus);
|
||||
plat->base = dev_read_addr(bus);
|
||||
plat->periph_id = clock_decode_periph_id(bus);
|
||||
|
||||
if (plat->periph_id == PERIPH_ID_NONE) {
|
||||
|
|
@ -109,10 +108,11 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus)
|
|||
}
|
||||
|
||||
/* Use 500KHz as a suitable default */
|
||||
plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
|
||||
500000);
|
||||
plat->deactivate_delay_us = fdtdec_get_int(blob, node,
|
||||
"spi-deactivate-delay", 0);
|
||||
plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
|
||||
500000);
|
||||
plat->deactivate_delay_us = dev_read_u32_default(bus,
|
||||
"spi-deactivate-delay",
|
||||
0);
|
||||
debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
|
||||
__func__, plat->base, plat->periph_id, plat->frequency,
|
||||
plat->deactivate_delay_us);
|
||||
|
|
@ -126,25 +126,32 @@ static int tegra210_qspi_probe(struct udevice *bus)
|
|||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
||||
|
||||
priv->regs = (struct qspi_regs *)plat->base;
|
||||
struct qspi_regs *regs = priv->regs;
|
||||
|
||||
priv->last_transaction_us = timer_get_us();
|
||||
priv->freq = plat->frequency;
|
||||
priv->periph_id = plat->periph_id;
|
||||
|
||||
debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
|
||||
priv->periph_id);
|
||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
||||
|
||||
/* Set tap delays here, clock change above resets QSPI controller */
|
||||
u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
|
||||
(0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
|
||||
writel(reg, ®s->command2);
|
||||
debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra210_qspi_claim_bus(struct udevice *bus)
|
||||
static int tegra210_qspi_claim_bus(struct udevice *dev)
|
||||
{
|
||||
struct udevice *bus = dev->parent;
|
||||
struct tegra210_qspi_priv *priv = dev_get_priv(bus);
|
||||
struct qspi_regs *regs = priv->regs;
|
||||
|
||||
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
|
||||
clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
|
||||
|
||||
debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
|
||||
|
||||
/* Set master mode and sw controlled CS */
|
||||
|
|
|
|||
|
|
@ -46,6 +46,14 @@
|
|||
"zImage fat 0 1 mmcpart 0; " \
|
||||
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
|
||||
|
||||
#define UBOOT_UPDATE \
|
||||
"uboot_hwpart=1\0" \
|
||||
"uboot_blk=0\0" \
|
||||
"set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
|
||||
"setexpr blkcnt ${blkcnt} / 0x200\0" \
|
||||
"update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
|
||||
"mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
|
||||
|
||||
#define EMMC_BOOTCMD \
|
||||
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
|
||||
"ro rootfstype=ext4 rootwait\0" \
|
||||
|
|
@ -104,6 +112,7 @@
|
|||
"fdt_module=" FDT_MODULE "\0" \
|
||||
NFS_BOOTCMD \
|
||||
SD_BOOTCMD \
|
||||
UBOOT_UPDATE \
|
||||
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
|
||||
"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
|
||||
"flash_eth.img && source ${loadaddr}\0" \
|
||||
|
|
|
|||
|
|
@ -40,6 +40,17 @@
|
|||
#undef CONFIG_SYS_MAXARGS
|
||||
#define CONFIG_SYS_MAXARGS 32
|
||||
|
||||
#define UBOOT_UPDATE \
|
||||
"uboot_hwpart=1\0" \
|
||||
"uboot_blk=0\0" \
|
||||
"set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
|
||||
"setexpr blkcnt ${blkcnt} / 0x200\0" \
|
||||
"update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
|
||||
"mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
|
||||
|
||||
#define BOARD_EXTRA_ENV_SETTINGS \
|
||||
UBOOT_UPDATE
|
||||
|
||||
#include "tegra-common-usb-gadget.h"
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -27,10 +27,14 @@
|
|||
#define CONFIG_TEGRA_NAND
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
|
||||
#define UBOOT_UPDATE \
|
||||
"update_uboot=nand erase.part u-boot && " \
|
||||
"nand write ${loadaddr} u-boot ${filesize}\0" \
|
||||
|
||||
/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
|
||||
#define BOARD_EXTRA_ENV_SETTINGS \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
UBOOT_UPDATE
|
||||
|
||||
/* Increase console I/O buffer size */
|
||||
#undef CONFIG_SYS_CBSIZE
|
||||
|
|
|
|||
|
|
@ -39,6 +39,17 @@
|
|||
#undef CONFIG_SYS_MAXARGS
|
||||
#define CONFIG_SYS_MAXARGS 32
|
||||
|
||||
#define UBOOT_UPDATE \
|
||||
"uboot_hwpart=1\0" \
|
||||
"uboot_blk=0\0" \
|
||||
"set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && " \
|
||||
"setexpr blkcnt ${blkcnt} / 0x200\0" \
|
||||
"update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && " \
|
||||
"mmc write ${loadaddr} ${uboot_blk} ${blkcnt}\0" \
|
||||
|
||||
#define BOARD_EXTRA_ENV_SETTINGS \
|
||||
UBOOT_UPDATE
|
||||
|
||||
#include "tegra-common-usb-gadget.h"
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
|
|
|
|||
46
include/configs/p3450-0000.h
Normal file
46
include/configs/p3450-0000.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2018-2019 NVIDIA Corporation.
|
||||
*/
|
||||
|
||||
#ifndef _P3450_0000_H
|
||||
#define _P3450_0000_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include "tegra210-common.h"
|
||||
|
||||
/* High-level configuration options */
|
||||
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P3450-0000"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_TEGRA_ENABLE_UARTA
|
||||
|
||||
/* Only MMC/PXE/DHCP for now, add USB back in later when supported */
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
/* Environment at end of QSPI, in the VER partition */
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 48000000
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
|
||||
|
||||
#define CONFIG_PREBOOT
|
||||
|
||||
#define BOARD_EXTRA_ENV_SETTINGS \
|
||||
"preboot=if test -e mmc 1:1 /u-boot-preboot.scr; then " \
|
||||
"load mmc 1:1 ${scriptaddr} /u-boot-preboot.scr; " \
|
||||
"source ${scriptaddr}; " \
|
||||
"fi\0"
|
||||
|
||||
/* General networking support */
|
||||
#include "tegra-common-usb-gadget.h"
|
||||
#include "tegra-common-post.h"
|
||||
|
||||
/* Crystal is 38.4MHz. clk_m runs at half that rate */
|
||||
#define COUNTER_FREQUENCY 19200000
|
||||
|
||||
#endif /* _P3450_0000_H */
|
||||
|
|
@ -46,8 +46,8 @@
|
|||
"scriptaddr=0x90000000\0" \
|
||||
"pxefile_addr_r=0x90100000\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
"fdt_addr_r=0x82000000\0" \
|
||||
"ramdisk_addr_r=0x82100000\0"
|
||||
"fdt_addr_r=0x83000000\0" \
|
||||
"ramdisk_addr_r=0x83200000\0"
|
||||
|
||||
/* For USB EHCI controller */
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
|
|
|
|||
Loading…
Reference in a new issue