sun7i: Add support for taking CPUs offline via PSCI
Based on the original version by Marc Zyngier. It adds a psci_cpu_off implementation for the A20 SoC. The mechanism works by first preparing the calling CPU to go offline (disable and flush cache, disable SMP), then requesting CPU 0 to pull the plug. The request is sent as FIQ on SGI15. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Jan Kiszka
Hans de Goede
parent
213480e12d
commit
602fa46c2c
1 changed files with 171 additions and 0 deletions
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@ -18,6 +18,7 @@
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*/
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#include <config.h>
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#include <asm/gic.h>
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#include <asm/psci.h>
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#include <asm/arch/cpu.h>
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@ -38,6 +39,8 @@
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#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
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#define TEN_MS (10 * ONE_MS)
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#define GICD_BASE 0x1c81000
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#define GICC_BASE 0x1c82000
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.macro timer_wait reg, ticks
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@ Program CNTP_TVAL
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@ -61,7 +64,27 @@
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.globl psci_arch_init
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psci_arch_init:
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movw r4, #(GICD_BASE & 0xffff)
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movt r4, #(GICD_BASE >> 16)
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ldr r5, [r4, #GICD_IGROUPRn]
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bic r5, r5, #(1 << 15) @ SGI15 as Group-0
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str r5, [r4, #GICD_IGROUPRn]
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mov r5, #0 @ Set SGI15 priority to 0
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strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
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add r4, r4, #0x1000 @ GICC address
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mov r5, #0xff
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str r5, [r4, #GICC_PMR] @ Be cool with non-secure
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ldr r5, [r4, #GICC_CTLR]
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orr r5, r5, #(1 << 3) @ Switch FIQEn on
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str r5, [r4, #GICC_CTLR]
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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orr r5, r5, #4 @ Enable FIQ in monitor mode
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb
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@ -79,6 +102,78 @@ psci_arch_init:
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bx lr
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.globl psci_fiq_enter
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psci_fiq_enter:
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push {r0-r12}
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@ Switch to secure
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mrc p15, 0, r7, c1, c1, 0
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bic r8, r7, #1
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mcr p15, 0, r8, c1, c1, 0
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isb
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@ Validate reason based on IAR and acknowledge
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movw r8, #(GICC_BASE & 0xffff)
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movt r8, #(GICC_BASE >> 16)
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ldr r9, [r8, #GICC_IAR]
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movw r10, #0x3ff
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movt r10, #0
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cmp r9, r10 @ skip spurious interrupt 1023
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beq out
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movw r10, #0x3fe @ ...and 1022
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cmp r9, r10
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beq out
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str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
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dsb
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@ Compute CPU number
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lsr r9, r9, #10
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and r9, r9, #0xf
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movw r8, #(SUN7I_CPUCFG_BASE & 0xffff)
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movt r8, #(SUN7I_CPUCFG_BASE >> 16)
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@ Wait for the core to enter WFI
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lsl r11, r9, #6 @ x64
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add r11, r11, r8
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1: ldr r10, [r11, #0x48]
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tst r10, #(1 << 2)
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bne 2f
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timer_wait r10, ONE_MS
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b 1b
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@ Reset CPU
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2: mov r10, #0
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str r10, [r11, #0x40]
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@ Lock CPU
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mov r10, #1
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lsl r9, r10, r9 @ r9 is now CPU mask
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ldr r10, [r8, #0x1e4]
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bic r10, r10, r9
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str r10, [r8, #0x1e4]
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@ Set power gating
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ldr r10, [r8, #0x1b4]
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orr r10, r10, #1
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str r10, [r8, #0x1b4]
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timer_wait r10, ONE_MS
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@ Activate power clamp
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mov r10, #1
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1: str r10, [r8, #0x1b0]
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lsl r10, r10, #1
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orr r10, r10, #1
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tst r10, #0x100
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beq 1b
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@ Restore security level
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out: mcr p15, 0, r7, c1, c1, 0
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pop {r0-r12}
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subs pc, lr, #4
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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@ -144,6 +239,53 @@ psci_cpu_on:
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_target_pc:
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.word 0
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/* Imported from Linux kernel */
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v7_flush_dcache_all:
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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flush_levels:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mrs r9, cpsr @ make cssr&csidr read atomic
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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msr cpsr_c, r9
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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mov r9, r7 @ create working copy of max index
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loop2:
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orr r11, r10, r4, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r9, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the index
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bge loop2
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subs r4, r4, #1 @ decrement the way
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bge loop1
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt flush_levels
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb st
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isb
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bx lr
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_sunxi_cpu_entry:
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@ Set SMP bit
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mrc p15, 0, r0, c1, c0, 1
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@ -158,5 +300,34 @@ _sunxi_cpu_entry:
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ldr r0, [r0]
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b _do_nonsec_entry
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.globl psci_cpu_off
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psci_cpu_off:
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mrc p15, 0, r0, c1, c0, 0 @ SCTLR
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bic r0, r0, #(1 << 2) @ Clear C bit
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mcr p15, 0, r0, c1, c0, 0 @ SCTLR
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isb
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dsb
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bl v7_flush_dcache_all
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clrex @ Why???
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mrc p15, 0, r0, c1, c0, 1 @ ACTLR
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bic r0, r0, #(1 << 6) @ Clear SMP bit
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mcr p15, 0, r0, c1, c0, 1 @ ACTLR
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isb
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dsb
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@ Ask CPU0 to pull the rug...
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movw r0, #(GICD_BASE & 0xffff)
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movt r0, #(GICD_BASE >> 16)
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movw r1, #15 @ SGI15
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movt r1, #1 @ Target is CPU0
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str r1, [r0, #GICD_SGIR]
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dsb
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1: wfi
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b 1b
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text_end:
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.popsection
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