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doc: arch: Convert README.mips to reST

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Convert plain text documentation to reStructuredText format and add
it to Sphinx TOC tree. No essential content change.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
This commit is contained in:
Bin Meng 2019-07-18 00:34:03 -07:00 committed by Tom Rini
parent d838138657
commit 5f2c16dab2
2 changed files with 12 additions and 18 deletions
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2
doc/arch/index.rst
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@ -5,3 +5,5 @@ Architecture-specific doc
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
mips

28
doc/README.mips → doc/arch/mips.rst
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@ -1,17 +1,16 @@
.. SPDX-License-Identifier: GPL-2.0+
MIPS
====
Notes for the MIPS architecture port of U-Boot Notes for the MIPS architecture port of U-Boot
Toolchains Toolchains
---------- ----------
http://www.denx.de/wiki/DULG/ELDK * `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
ELDK < DULG < DENX * `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
* `Buildroot <http://buildroot.uclibc.org/>`_
http://www.emdebian.org/crosstools.html
Embedded Debian -- Cross-development toolchains
http://buildroot.uclibc.org/
Buildroot
Known Issues Known Issues
------------ ------------
@ -24,9 +23,9 @@ Known Issues
re-initializes the cache. The more common uImage 'bootm' command does re-initializes the cache. The more common uImage 'bootm' command does
not suffer this problem. not suffer this problem.
[workaround] To avoid this cache incoherency, [workaround] To avoid this cache incoherency:
1) insert flush_cache(all) before calling dcache_disable(), or - insert flush_cache(all) before calling dcache_disable(), or
2) fix dcache_disable() to do both flushing and disabling cache. - fix dcache_disable() to do both flushing and disabling cache.
* Note that Linux users need to kill dcache_disable() in do_bootelf_exec() * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
or override do_bootelf_exec() not to disable I-/D-caches, because most or override do_bootelf_exec() not to disable I-/D-caches, because most
@ -36,19 +35,12 @@ TODOs
----- -----
* Probe CPU types, I-/D-cache and TLB size etc. automatically * Probe CPU types, I-/D-cache and TLB size etc. automatically
* Secondary cache support missing * Secondary cache support missing
* Initialize TLB entries redardless of their use * Initialize TLB entries redardless of their use
* R2000/R3000 class parts are not supported * R2000/R3000 class parts are not supported
* Limited testing across different MIPS variants * Limited testing across different MIPS variants
* Due to cache initialization issues, the DRAM on board must be * Due to cache initialization issues, the DRAM on board must be
initialized in board specific assembler language before the cache init initialized in board specific assembler language before the cache init
code is run -- that is, initialize the DRAM in lowlevel_init(). code is run -- that is, initialize the DRAM in lowlevel_init().
* centralize/share more CPU code of MIPS32, MIPS64 and XBurst * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
* support Qemu Malta * support Qemu Malta