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powerpc/t4240qds: Adjust DDR timing for RDIMM

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RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2013-06-25 11:37:46 -07:00
parent d8556db1d4
commit 5ecf41cc3d
1 changed files with 9 additions and 10 deletions
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19
board/freescale/t4qds/ddr.h
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@ -64,16 +64,15 @@ static const struct board_specific_parameters rdimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
{4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
{4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
{4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
{2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
{2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
{}
};