board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also known as Socionext SynQuacer E-Series. It contians one "SC2A11" SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots, 3 PCIe slots (1 4x port and 2 1x ports which are expanded via PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard MicroATX Form Factor. For more information, see this page; https://www.96boards.org/product/developerbox/ Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
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@ -1778,6 +1778,19 @@ config ARCH_UNIPHIER
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Support for UniPhier SoC family developed by Socionext Inc.
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(formerly, System LSI Business Division of Panasonic Corporation)
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoCs"
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select ARM64
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select DM
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select GIC_V3
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select PSCI_RESET
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select SYSRESET
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select SYSRESET_PSCI
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select OF_CONTROL
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help
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Support for SynQuacer SoC family developed by Socionext Inc.
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This SoC is used on 96boards EE DeveloperBox.
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config ARCH_STM32
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bool "Support STMicroelectronics STM32 MCU with cortex M"
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select CPU_V7M
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@ -2121,6 +2134,7 @@ source "board/isee/igep003x/Kconfig"
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source "board/kontron/sl28/Kconfig"
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source "board/myir/mys_6ulx/Kconfig"
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source "board/seeed/npi_imx6ull/Kconfig"
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source "board/socionext/developerbox/Kconfig"
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source "board/spear/spear300/Kconfig"
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source "board/spear/spear310/Kconfig"
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source "board/spear/spear320/Kconfig"
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36
board/socionext/developerbox/Kconfig
Normal file
36
board/socionext/developerbox/Kconfig
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@ -0,0 +1,36 @@
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if ARCH_SYNQUACER
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choice
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prompt "SC2A11 Cortex-A53 MPCore 24cores"
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optional
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config TARGET_DEVELOPERBOX
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bool "Socionext DeveloperBox"
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select PCI
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select DM_PCI
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select PCIE_ECAM_SYNQUACER
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select SYS_DISABLE_DCACHE_OPS
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select OF_BOARD_SETUP
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help
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Choose this option if you build the U-Boot for the DeveloperBox
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96boards Enterprise Edition.
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This board will booted from SCP firmware and it enables SMMU, thus
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the dcache is updated automatically when DMA operation is executed.
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endchoice
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config SYS_SOC
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default "sc2a11"
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if TARGET_DEVELOPERBOX
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config SYS_BOARD
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default "developerbox"
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config SYS_VENDOR
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default "socionext"
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config SYS_CONFIG_NAME
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default "synquacer"
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endif
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endif
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14
board/socionext/developerbox/MAINTAINERS
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14
board/socionext/developerbox/MAINTAINERS
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@ -0,0 +1,14 @@
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DEVELOPER BOX
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M: Masami Hiramatsu <masami.hiramatsu@linaro.org>
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M: Jassi Brar <jaswinder.singh@linaro.org>
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S: Maintained
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F: arch/arm/dts/synquacer-*
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F: board/socionext/developerbox/*
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F: configs/synquacer_developerbox_defconfig
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F: drivers/i2c/synquacer_i2c.c
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F: drivers/mmc/f_sdh30.c
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F: drivers/net/sni_netsec.c
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F: drivers/pci/pcie_ecam_synquacer.c
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F: drivers/spi/spi-synquacer.c
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F: include/configs/synquacer.h
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F: doc/board/socionext/developerbox.rst
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9
board/socionext/developerbox/Makefile
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9
board/socionext/developerbox/Makefile
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@ -0,0 +1,9 @@
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#
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# Author: Masami Hiramatsu <masami.hiramatsu@linaro.org>
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#
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# Copyright (C) 2021 Linaro Ltd.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := developerbox.o
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146
board/socionext/developerbox/developerbox.c
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146
board/socionext/developerbox/developerbox.c
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// SPDX-License-Identifier: GPL-2.0
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/*
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* u-boot/board/socionext/developerbox/developerbox.c
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*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Copyright (C) 2021 Linaro Ltd.
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*/
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#include <asm/types.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <common.h>
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#include <env_internal.h>
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#include <fdt_support.h>
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#include <log.h>
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static struct mm_region sc2a11_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* 1st DDR block */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = PHYS_SDRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* 2nd DDR place holder */
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0,
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}, {
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/* 3rd DDR place holder */
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0,
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = sc2a11_mem_map;
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#define DDR_REGION_INDEX(i) (1 + (i))
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#define MAX_DDR_REGIONS 3
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struct draminfo_entry {
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u64 base;
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u64 size;
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};
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struct draminfo {
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u32 nr_regions;
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u32 reserved;
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struct draminfo_entry entry[3];
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};
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struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
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DECLARE_GLOBAL_DATA_PTR;
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#define LOAD_OFFSET 0x100
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_LOAD_ADDR + LOAD_OFFSET;
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gd->env_addr = (ulong)&default_environment[0];
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return 0;
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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/* Remove SPI NOR and I2C0 for making DT compatible with EDK2 */
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fdt_del_node_and_alias(blob, "spi_nor");
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fdt_del_node_and_alias(blob, "i2c0");
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return 0;
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}
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/*
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* DRAM configuration
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*/
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int dram_init(void)
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{
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struct draminfo_entry *ent = synquacer_draminfo->entry;
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struct mm_region *mr;
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int i, ri;
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if (synquacer_draminfo->nr_regions < 1) {
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log_err("Failed to get correct DRAM information\n");
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return -1;
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}
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/*
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* U-Boot RAM size must be under the first DRAM region so that it doesn't
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* access secure memory which is at the end of the first DRAM region.
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*/
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gd->ram_size = ent[0].size;
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/* Update memory region maps */
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for (i = 0; i < synquacer_draminfo->nr_regions; i++) {
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if (i >= MAX_DDR_REGIONS)
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break;
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ri = DDR_REGION_INDEX(i);
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mem_map[ri].phys = ent[i].base;
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mem_map[ri].size = ent[i].size;
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if (i == 0)
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continue;
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mr = &mem_map[DDR_REGION_INDEX(0)];
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mem_map[ri].virt = mr->virt + mr->size;
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mem_map[ri].attrs = mr->attrs;
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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struct draminfo_entry *ent = synquacer_draminfo->entry;
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int i;
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for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
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if (i < synquacer_draminfo->nr_regions) {
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debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base);
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gd->bd->bi_dram[i].start = ent[i].base;
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gd->bd->bi_dram[i].size = ent[i].size;
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}
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}
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return 0;
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}
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int print_cpuinfo(void)
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{
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printf("CPU: SC2A11:Cortex-A53 MPCore 24cores\n");
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return 0;
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}
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112
configs/synquacer_developerbox_defconfig
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112
configs/synquacer_developerbox_defconfig
Normal file
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CONFIG_ARM=y
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CONFIG_ARCH_SYNQUACER=y
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CONFIG_SYS_TEXT_BASE=0x08200000
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CONFIG_ENV_SIZE=0x30000
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CONFIG_ENV_OFFSET=0x300000
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CONFIG_DEBUG_UART_BASE=0x2a400000
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CONFIG_DEBUG_UART_CLOCK=62500000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_DM_GPIO=y
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CONFIG_TARGET_DEVELOPERBOX=y
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CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox"
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CONFIG_AHCI=y
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CONFIG_BOOTSTAGE_STASH_SIZE=4096
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CONFIG_BOOTM_EFI=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTEFI=y
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CONFIG_CMD_NVEDIT_EFI=y
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CONFIG_CMD_EFIDEBUG=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_NVEDIT_INFO=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_NET=y
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CONFIG_CMD_BOOTP=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_DATE=y
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CONFIG_CMD_RTC=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_PART=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_POWEROFF=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_SATA=y
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CONFIG_CMD_NVME=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDPARTS_DEFAULT="nor1:448k(BootStrap-BL1),576k(Flash-Writer),512k(SCP-BL2),480k(FIP-TFA),32k(Stg2-Tables),1m@2m(U-Boot),1m@3m(UBoot-Env),2m@5m(Ex-OPTEE)"
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CONFIG_MTDIDS_DEFAULT="nor1=nor1"
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CONFIG_CMD_LOG=y
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CONFIG_PARTITION_TYPE_GUID=y
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CONFIG_EFI_PARTITION=y
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CONFIG_EFI_LOADER=y
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CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
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CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
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CONFIG_EFI_UNICODE_CAPITALIZATION=y
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CONFIG_EFI_HAVE_RUNTIME_RESET=y
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CONFIG_EFI_GET_TIME=y
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CONFIG_EFI_SET_TIME=y
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CONFIG_CMD_EFI_VARIABLE_FILE_STORE=Y
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CONFIG_OF_SEPARATE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_USE_ENV_SPI_BUS=y
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CONFIG_ENV_SPI_BUS=0
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CONFIG_USE_ENV_SPI_CS=y
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CONFIG_ENV_SPI_CS=0
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CONFIG_PROT_UDP=y
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CONFIG_BAUDRATE=115200
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_CONS_INDEX=0
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CONFIG_DM_SERIAL=y
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CONFIG_PL01X_SERIAL=y
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CONFIG_SATA=y
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CONFIG_NVME=y
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CONFIG_SCSI_AHCI=y
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CONFIG_AHCI_PCI=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_SYNQUACER=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_F_SDH30=y
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CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_SPEED=31250000
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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CONFIG_NET=y
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CONFIG_NETDEVICES=y
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CONFIG_SNI_NETSEC=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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CONFIG_RGMII=y
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CONFIG_MII=y
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CONFIG_DM_RTC=y
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CONFIG_RTC_PCF8563=y
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CONFIG_SCSI=y
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CONFIG_DM_SCSI=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_SYNQUACER_SPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PCI=y
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CONFIG_USB_STORAGE=y
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@ -22,6 +22,7 @@ Board-specific doc
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rockchip/index
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sifive/index
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sipeed/index
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socionext/index
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st/index
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tbs/index
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toradex/index
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87
doc/board/socionext/developerbox.rst
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87
doc/board/socionext/developerbox.rst
Normal file
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@ -0,0 +1,87 @@
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.. SPDX-License-Identifier: GPL-2.0+
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Introduction
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============
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DeveloperBox is a certified 96boards Enterprise Edition board. The board/SoC has: -
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* Socionext SC2A11 24-cores ARM Cortex-A53 on tbe Mini-ATX form factor motherboard
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* 4 DIMM slots (4GB DDR4-2400 UDIMM shipped by default)
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* 1 4xPCIe Gen2 slot and 2 1xPCIe Gen2 slots
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(1x slots are connected via PCIe bridge chip)
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* 4 USB-3.0 ports
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* 2 SATA ports
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* 1 GbE network port
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* 1 USB-UART serial port (micro USB)
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* 64MB SPI NOR Flash
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* 8GB eMMC Flash Storage
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* 96boards LS connector
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The DeveloperBox schematic can be found here: -
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https://www.96boards.org/documentation/enterprise/developerbox/hardware-docs/mzsc2am_v03_20180115_a.pdf
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And the other documents can be found here: -
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https://www.96boards.org/documentation/enterprise/developerbox/
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Currently, the U-Boot port supports: -
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* USB
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* eMMC
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* SPI-NOR
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* SATA
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* GbE
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The DeveloperBox boots the TF-A and EDK2 as a main bootloader by default.
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The DeveloperBox U-Boot port will replace the EDK2 and boot from TF-A as
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BL33, but no need to combine with it.
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Compile from source
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===================
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You can build U-Boot without any additinal source code.::
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cd u-boot
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export ARCH=arm64
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export CROSS_COMPILE=aarch64-linux-gnu-
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make SynQuacer_defconfig
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make -j `noproc`
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Then, expand the binary to 1MB for preparing flash.::
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cp u-boot.bin SPI_NOR_UBOOT.fd
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truncate -s 1M SPI_NOR_UBOOT.fd
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Installation
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============
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You can install the SNI_NOR_UBOOT.fd via NOR flash writer.
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Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port.
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Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing.
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*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail*
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https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html
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When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0::
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/*------------------------------------------*/
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/* SC2A11 "SynQuacer" series Flash writer */
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/* */
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/* Version: cd254ac */
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/* Build: 12/15/17 11:25:45 */
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/*------------------------------------------*/
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Command Input >
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Once the flasher tool is running we are ready flash the UEFI image::
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flash rawwrite 200000 100000
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>> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) <<
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*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).*
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After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board.
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|
9
doc/board/socionext/index.rst
Normal file
9
doc/board/socionext/index.rst
Normal file
|
@ -0,0 +1,9 @@
|
|||
.. SPDX-License-Identifier: GPL-2.0+
|
||||
|
||||
Socionext
|
||||
=========
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
developerbox
|
109
include/configs/synquacer.h
Normal file
109
include/configs/synquacer.h
Normal file
|
@ -0,0 +1,109 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2016-2017 Socionext Inc.
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* Timers for fasp(TIMCLK) */
|
||||
#define CONFIG_SYS_HZ 1000 /* 1 msec */
|
||||
#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
|
||||
|
||||
/*
|
||||
* SDRAM (for initialize)
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
|
||||
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
|
||||
|
||||
#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
|
||||
#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
|
||||
|
||||
#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
|
||||
|
||||
/*
|
||||
* Boot info
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
|
||||
#define CONFIG_SYS_MALLOC_LEN (0x01000000) /* 16Mbyte size of malloc() */
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default kernel load address */
|
||||
|
||||
/*
|
||||
* Hardware drivers support
|
||||
*/
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
|
||||
|
||||
/* Serial (pl011) */
|
||||
#define UART_CLK (62500000)
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_PL011_SERIAL
|
||||
#define CONFIG_PL011_CLOCK UART_CLK
|
||||
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
|
||||
|
||||
/* Support MTD */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_BASE (0x08000000)
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 }
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 1024
|
||||
#define CONFIG_SYS_MAXARGS 128
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
|
||||
/* #define CONFIG_SYS_PCI_64BIT 1 */
|
||||
|
||||
/* Distro boot settings */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
|
||||
#else
|
||||
#define BOOT_TARGET_DEVICE_USB(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
|
||||
#else
|
||||
#define BOOT_TARGET_DEVICE_MMC(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NVME
|
||||
#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
|
||||
#else
|
||||
#define BOOT_TARGET_DEVICE_NVME(func)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_SCSI
|
||||
#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
|
||||
#else
|
||||
#define BOOT_TARGET_DEVICE_SCSI(func)
|
||||
#endif
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
BOOT_TARGET_DEVICE_USB(func) \
|
||||
BOOT_TARGET_DEVICE_MMC(func) \
|
||||
BOOT_TARGET_DEVICE_SCSI(func) \
|
||||
BOOT_TARGET_DEVICE_NVME(func) \
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#else /* CONFIG_SPL_BUILD */
|
||||
#define BOOTENV
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"fdt_addr_r=0x9fe00000\0" \
|
||||
"kernel_addr_r=0x90000000\0" \
|
||||
"ramdisk_addr_r=0xa0000000\0" \
|
||||
"scriptaddr=0x88000000\0" \
|
||||
"pxefile_addr_r=0x88100000\0" \
|
||||
BOOTENV
|
||||
|
||||
#endif /* __CONFIG_H */
|
Loading…
Reference in a new issue