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ppc4xx: Add static support for 44x IBM SDRAM Controller

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This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Adam Graham 2008-10-08 10:13:14 -07:00 committed by Stefan Roese
parent f09f09d389
commit 59217bae40
1 changed files with 53 additions and 18 deletions
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71
cpu/ppc4xx/44x_spd_ddr2.c
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@ -60,6 +60,26 @@
"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
} while (0) } while (0)
#if defined(CONFIG_440)
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2
* memory region. Right now the cache should still be disabled in U-Boot
* because of the EMAC driver, that need its buffer descriptor to be located
* in non cached memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CONFIG_4xx_DCACHE
/* enable caching on SDRAM */
#define MY_TLB_WORD2_I_ENABLE 0
#else
/* disable caching on SDRAM */
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
#endif /* CONFIG_4xx_DCACHE */
#endif /* CONFIG_440 */
#if defined(CONFIG_SPD_EEPROM) #if defined(CONFIG_SPD_EEPROM)
/*-----------------------------------------------------------------------------+ /*-----------------------------------------------------------------------------+
@ -130,22 +150,6 @@
#define NUMMEMWORDS 8 #define NUMMEMWORDS 8
#define NUMLOOPS 64 /* memory test loops */ #define NUMLOOPS 64 /* memory test loops */
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
* region. Right now the cache should still be disabled in U-Boot because of the
* EMAC driver, that need it's buffer descriptor to be located in non cached
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
#ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
#endif
/* /*
* Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
* To support such configurations, we "only" map the first 2GB via the TLB's. We * To support such configurations, we "only" map the first 2GB via the TLB's. We
@ -2958,9 +2962,10 @@ static void test(void)
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Function: initdram * Function: initdram
* Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
* banks. The configuration is performed using static, compile- * The configuration is performed using static, compile-
* time parameters. * time parameters.
* Configures the PPC405EX(r) and PPC460EX/GT
*---------------------------------------------------------------------------*/ *---------------------------------------------------------------------------*/
phys_size_t initdram(int board_type) phys_size_t initdram(int board_type)
{ {
@ -2976,6 +2981,18 @@ phys_size_t initdram(int board_type)
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
unsigned long val; unsigned long val;
#if defined(CONFIG_440)
mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
#endif
/* Set Memory Bank Configuration Registers */ /* Set Memory Bank Configuration Registers */
mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF); mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
@ -3069,6 +3086,14 @@ phys_size_t initdram(int board_type)
mfsdram(SDRAM_MCOPT2, val); mfsdram(SDRAM_MCOPT2, val);
mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
#if defined(CONFIG_440)
/*
* Program TLB entries with caches enabled, for best performace
* while auto-calibrating and ECC generation
*/
program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
#endif
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*------------------------------------------------------------------ /*------------------------------------------------------------------
@ -3082,6 +3107,16 @@ phys_size_t initdram(int board_type)
ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* defined(CONFIG_DDR_ECC) */ #endif /* defined(CONFIG_DDR_ECC) */
#if defined(CONFIG_440)
/*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
* desired cache functionality
*/
remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
#endif
ppc4xx_ibm_ddr2_register_dump(); ppc4xx_ibm_ddr2_register_dump();
#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)