socfpga: Adding pin mux handoff files
Adding the generated pin mux configuration by Preloader Generator tool Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This commit is contained in:
Chin Liang See
Albert ARIBAUD
parent
5d649d2b08
commit
572886af59
2 changed files with 268 additions and 0 deletions
214
board/altera/socfpga/pinmux_config.c
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214
board/altera/socfpga/pinmux_config.c
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/* This file is generated by Preloader Generator */
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#include "pinmux_config.h"
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/* pin mux configuration data */
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unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
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0, /* EMACIO0 - Unused */
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2, /* EMACIO1 - USB */
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2, /* EMACIO2 - USB */
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2, /* EMACIO3 - USB */
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2, /* EMACIO4 - USB */
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2, /* EMACIO5 - USB */
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2, /* EMACIO6 - USB */
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2, /* EMACIO7 - USB */
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2, /* EMACIO8 - USB */
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0, /* EMACIO9 - Unused */
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2, /* EMACIO10 - USB */
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2, /* EMACIO11 - USB */
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2, /* EMACIO12 - USB */
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2, /* EMACIO13 - USB */
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0, /* EMACIO14 - N/A */
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0, /* EMACIO15 - N/A */
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0, /* EMACIO16 - N/A */
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0, /* EMACIO17 - N/A */
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0, /* EMACIO18 - N/A */
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0, /* EMACIO19 - N/A */
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3, /* FLASHIO0 - SDMMC */
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3, /* FLASHIO1 - SDMMC */
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3, /* FLASHIO2 - SDMMC */
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3, /* FLASHIO3 - SDMMC */
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0, /* FLASHIO4 - SDMMC */
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0, /* FLASHIO5 - SDMMC */
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0, /* FLASHIO6 - SDMMC */
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0, /* FLASHIO7 - SDMMC */
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0, /* FLASHIO8 - SDMMC */
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3, /* FLASHIO9 - SDMMC */
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3, /* FLASHIO10 - SDMMC */
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3, /* FLASHIO11 - SDMMC */
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3, /* GENERALIO0 - TRACE */
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3, /* GENERALIO1 - TRACE */
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3, /* GENERALIO2 - TRACE */
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3, /* GENERALIO3 - TRACE */
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3, /* GENERALIO4 - TRACE */
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3, /* GENERALIO5 - TRACE */
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3, /* GENERALIO6 - TRACE */
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3, /* GENERALIO7 - TRACE */
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3, /* GENERALIO8 - TRACE */
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3, /* GENERALIO9 - SPIM0 */
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3, /* GENERALIO10 - SPIM0 */
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3, /* GENERALIO11 - SPIM0 */
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3, /* GENERALIO12 - SPIM0 */
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2, /* GENERALIO13 - CAN0 */
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2, /* GENERALIO14 - CAN0 */
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3, /* GENERALIO15 - I2C0 */
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3, /* GENERALIO16 - I2C0 */
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2, /* GENERALIO17 - UART0 */
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2, /* GENERALIO18 - UART0 */
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0, /* GENERALIO19 - N/A */
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0, /* GENERALIO20 - N/A */
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0, /* GENERALIO21 - N/A */
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0, /* GENERALIO22 - N/A */
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0, /* GENERALIO23 - N/A */
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0, /* GENERALIO24 - N/A */
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0, /* GENERALIO25 - N/A */
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0, /* GENERALIO26 - N/A */
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0, /* GENERALIO27 - N/A */
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0, /* GENERALIO28 - N/A */
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0, /* GENERALIO29 - N/A */
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0, /* GENERALIO30 - N/A */
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0, /* GENERALIO31 - N/A */
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2, /* MIXED1IO0 - EMAC */
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2, /* MIXED1IO1 - EMAC */
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2, /* MIXED1IO2 - EMAC */
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2, /* MIXED1IO3 - EMAC */
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2, /* MIXED1IO4 - EMAC */
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2, /* MIXED1IO5 - EMAC */
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2, /* MIXED1IO6 - EMAC */
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2, /* MIXED1IO7 - EMAC */
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2, /* MIXED1IO8 - EMAC */
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2, /* MIXED1IO9 - EMAC */
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2, /* MIXED1IO10 - EMAC */
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2, /* MIXED1IO11 - EMAC */
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2, /* MIXED1IO12 - EMAC */
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2, /* MIXED1IO13 - EMAC */
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0, /* MIXED1IO14 - Unused */
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3, /* MIXED1IO15 - QSPI */
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3, /* MIXED1IO16 - QSPI */
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3, /* MIXED1IO17 - QSPI */
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3, /* MIXED1IO18 - QSPI */
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3, /* MIXED1IO19 - QSPI */
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3, /* MIXED1IO20 - QSPI */
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0, /* MIXED1IO21 - GPIO */
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0, /* MIXED2IO0 - N/A */
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0, /* MIXED2IO1 - N/A */
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0, /* MIXED2IO2 - N/A */
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0, /* MIXED2IO3 - N/A */
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0, /* MIXED2IO4 - N/A */
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0, /* MIXED2IO5 - N/A */
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0, /* MIXED2IO6 - N/A */
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0, /* MIXED2IO7 - N/A */
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0, /* GPLINMUX48 */
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0, /* GPLINMUX49 */
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0, /* GPLINMUX50 */
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0, /* GPLINMUX51 */
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0, /* GPLINMUX52 */
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0, /* GPLINMUX53 */
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0, /* GPLINMUX54 */
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0, /* GPLINMUX55 */
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0, /* GPLINMUX56 */
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0, /* GPLINMUX57 */
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0, /* GPLINMUX58 */
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0, /* GPLINMUX59 */
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0, /* GPLINMUX60 */
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0, /* GPLINMUX61 */
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0, /* GPLINMUX62 */
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0, /* GPLINMUX63 */
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0, /* GPLINMUX64 */
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0, /* GPLINMUX65 */
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0, /* GPLINMUX66 */
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0, /* GPLINMUX67 */
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0, /* GPLINMUX68 */
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0, /* GPLINMUX69 */
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0, /* GPLINMUX70 */
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1, /* GPLMUX0 */
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1, /* GPLMUX1 */
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1, /* GPLMUX2 */
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1, /* GPLMUX3 */
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1, /* GPLMUX4 */
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1, /* GPLMUX5 */
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1, /* GPLMUX6 */
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1, /* GPLMUX7 */
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1, /* GPLMUX8 */
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1, /* GPLMUX9 */
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1, /* GPLMUX10 */
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1, /* GPLMUX11 */
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1, /* GPLMUX12 */
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1, /* GPLMUX13 */
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1, /* GPLMUX14 */
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1, /* GPLMUX15 */
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1, /* GPLMUX16 */
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1, /* GPLMUX17 */
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1, /* GPLMUX18 */
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1, /* GPLMUX19 */
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1, /* GPLMUX20 */
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1, /* GPLMUX21 */
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1, /* GPLMUX22 */
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1, /* GPLMUX23 */
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1, /* GPLMUX24 */
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1, /* GPLMUX25 */
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1, /* GPLMUX26 */
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1, /* GPLMUX27 */
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1, /* GPLMUX28 */
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1, /* GPLMUX29 */
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1, /* GPLMUX30 */
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1, /* GPLMUX31 */
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1, /* GPLMUX32 */
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1, /* GPLMUX33 */
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1, /* GPLMUX34 */
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1, /* GPLMUX35 */
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1, /* GPLMUX36 */
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1, /* GPLMUX37 */
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1, /* GPLMUX38 */
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1, /* GPLMUX39 */
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1, /* GPLMUX40 */
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1, /* GPLMUX41 */
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1, /* GPLMUX42 */
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1, /* GPLMUX43 */
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1, /* GPLMUX44 */
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1, /* GPLMUX45 */
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1, /* GPLMUX46 */
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1, /* GPLMUX47 */
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1, /* GPLMUX48 */
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1, /* GPLMUX49 */
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1, /* GPLMUX50 */
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1, /* GPLMUX51 */
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1, /* GPLMUX52 */
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1, /* GPLMUX53 */
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1, /* GPLMUX54 */
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1, /* GPLMUX55 */
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1, /* GPLMUX56 */
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1, /* GPLMUX57 */
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1, /* GPLMUX58 */
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1, /* GPLMUX59 */
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1, /* GPLMUX60 */
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1, /* GPLMUX61 */
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1, /* GPLMUX62 */
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1, /* GPLMUX63 */
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1, /* GPLMUX64 */
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1, /* GPLMUX65 */
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1, /* GPLMUX66 */
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1, /* GPLMUX67 */
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1, /* GPLMUX68 */
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1, /* GPLMUX69 */
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1, /* GPLMUX70 */
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0, /* NANDUSEFPGA */
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0, /* UART0USEFPGA */
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0, /* RGMII1USEFPGA */
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0, /* SPIS0USEFPGA */
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0, /* CAN0USEFPGA */
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0, /* I2C0USEFPGA */
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0, /* SDMMCUSEFPGA */
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0, /* QSPIUSEFPGA */
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0, /* SPIS1USEFPGA */
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0, /* RGMII0USEFPGA */
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0, /* UART1USEFPGA */
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0, /* CAN1USEFPGA */
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0, /* USB1USEFPGA */
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0, /* I2C3USEFPGA */
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0, /* I2C2USEFPGA */
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0, /* I2C1USEFPGA */
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0, /* SPIM1USEFPGA */
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0, /* USB0USEFPGA */
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0 /* SPIM0USEFPGA */
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};
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54
board/altera/socfpga/pinmux_config.h
Normal file
54
board/altera/socfpga/pinmux_config.h
Normal file
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@ -0,0 +1,54 @@
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/* This file is generated by Preloader Generator */
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#ifndef _PRELOADER_PINMUX_CONFIG_H_
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#define _PRELOADER_PINMUX_CONFIG_H_
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/*
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* State of enabling for which IP connected out through the muxing.
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* Value 1 mean the IP connection is muxed out
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*/
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#define CONFIG_HPS_EMAC0 (0)
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#define CONFIG_HPS_EMAC1 (1)
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#define CONFIG_HPS_USB0 (0)
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#define CONFIG_HPS_USB1 (1)
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#define CONFIG_HPS_NAND (0)
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#define CONFIG_HPS_SDMMC (1)
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#define CONFIG_HPS_QSPI (1)
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#define CONFIG_HPS_UART0 (1)
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#define CONFIG_HPS_UART1 (0)
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#define CONFIG_HPS_TRACE (1)
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#define CONFIG_HPS_I2C0 (1)
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#define CONFIG_HPS_I2C1 (0)
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#define CONFIG_HPS_I2C2 (0)
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#define CONFIG_HPS_I2C3 (0)
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#define CONFIG_HPS_SPIM0 (1)
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#define CONFIG_HPS_SPIM1 (0)
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#define CONFIG_HPS_SPIS0 (0)
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#define CONFIG_HPS_SPIS1 (0)
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#define CONFIG_HPS_CAN0 (1)
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#define CONFIG_HPS_CAN1 (0)
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/* IP attribute value (which affected by pin muxing configuration) */
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#define CONFIG_HPS_SDMMC_BUSWIDTH (4)
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/* 1 if the pins are connected out */
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#define CONFIG_HPS_QSPI_CS0 (1)
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#define CONFIG_HPS_QSPI_CS1 (0)
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#define CONFIG_HPS_QSPI_CS2 (0)
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#define CONFIG_HPS_QSPI_CS3 (0)
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/* UART */
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/* 1 means the pin is mux out or available */
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#define CONFIG_HPS_UART0_TX (1)
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#define CONFIG_HPS_UART0_RX (1)
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#define CONFIG_HPS_UART0_CTS (0)
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#define CONFIG_HPS_UART0_RTS (0)
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#define CONFIG_HPS_UART1_TX (0)
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#define CONFIG_HPS_UART1_RX (0)
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#define CONFIG_HPS_UART1_CTS (0)
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#define CONFIG_HPS_UART1_RTS (0)
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/* Pin mux data */
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#define CONFIG_HPS_PINMUX_NUM (207)
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#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
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