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i.MX for 2021.04

Browse source 
----------------
 
 - new boards:
 	- i.MX8MN Beacon EmbeddedWorks (2GB)
 	- Gateworks Venice imx8mm
 - convert to DM:
 	- imx53-qsb, mx53loco, mx51evk, mx23-evk
 - Fixes :
 	- Network : FEC ethernet quirks
 	- DH dh-imx6
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
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Merge tag 'u-boot-imx-20210303' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2021.04
----------------

- new boards:
	- i.MX8MN Beacon EmbeddedWorks (2GB)
	- Gateworks Venice imx8mm
- convert to DM:
	- imx53-qsb, mx53loco, mx51evk, mx23-evk
- Fixes :
	- Network : FEC ethernet quirks
	- DH dh-imx6

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
This commit is contained in:
Tom Rini 2021-03-03 10:10:34 -05:00
commit 52ba373b78
80 changed files with 11232 additions and 410 deletions
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5
Makefile
View file

@ -1548,7 +1548,10 @@ flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
endif
endif
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL u-boot.bin FORCE
u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
MKIMAGEFLAGS_u-boot.ubl = -n $(UBL_CONFIG) -T ublimage -e $(CONFIG_SYS_TEXT_BASE)

11
arch/arm/dts/Makefile
View file

@ -648,10 +648,17 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-pcm052.dtb \
vf610-bk4r1.dtb
dtb-$(CONFIG_MX23) += \
imx23-evk.dtb
dtb-$(CONFIG_MX28) += \
imx28-xea.dtb
dtb-$(CONFIG_MX51) += \
imx51-babbage.dtb
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
imx53-qsb.dtb \
imx53-kp.dtb \
imx53-m53menlo.dtb
@ -783,6 +790,10 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \

2
arch/arm/dts/fsl-imx8qm-apalis.dts
View file

@ -503,7 +503,7 @@
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 11 1>;
status = "okay";

2
arch/arm/dts/fsl-imx8qxp-apalis.dts
View file

@ -229,7 +229,7 @@
pinctrl-0 = <&pinctrl_fec1>;
fsl,magic-packet;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-reset-duration = <10>;
phy-reset-post-delay = <150>;
phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;

4
arch/arm/dts/imx23-evk-u-boot.dtsi Normal file
View file

@ -0,0 +1,4 @@
// SPDX-License-Identifier: GPL-2.0+
#include "imx23-u-boot.dtsi"

145
arch/arm/dts/imx23-evk.dts Normal file
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@ -0,0 +1,145 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
/dts-v1/;
#include "imx23.dtsi"
/ {
model = "Freescale i.MX23 Evaluation Kit";
compatible = "fsl,imx23-evk", "fsl,imx23";
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x08000000>;
};
reg_vddio_sd0: regulator-vddio-sd0 {
compatible = "regulator-fixed";
regulator-name = "vddio-sd0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 0>;
};
reg_lcd_3v3: regulator-lcd-3v3 {
compatible = "regulator-fixed";
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 18 0>;
enable-active-high;
};
reg_lcd_5v: regulator-lcd-5v {
compatible = "regulator-fixed";
regulator-name = "lcd-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
panel {
compatible = "sii,43wvf1g";
backlight = <&backlight_display>;
dvdd-supply = <&reg_lcd_3v3>;
avdd-supply = <&reg_lcd_5v>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
apb@80000000 {
apbh@80000000 {
nand-controller@8000c000 {
pinctrl-names = "default";
pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
status = "okay";
};
ssp0: spi@80010000 {
compatible = "fsl,imx23-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
bus-width = <4>;
wp-gpios = <&gpio1 30 0>;
vmmc-supply = <&reg_vddio_sd0>;
status = "okay";
};
pinctrl@80018000 {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_LCD_RESET__GPIO_1_18
MX23_PAD_PWM3__GPIO_1_29
MX23_PAD_PWM4__GPIO_1_30
MX23_PAD_SSP1_DETECT__SSP1_DETECT
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
};
lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>;
status = "okay";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
apbx@80040000 {
lradc@80050000 {
status = "okay";
fsl,lradc-touchscreen-wires = <4>;
};
pwm: pwm@80064000 {
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pins_a>;
status = "okay";
};
auart0: serial@8006c000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_pins_a>;
status = "okay";
};
duart: serial@80070000 {
pinctrl-names = "default";
pinctrl-0 = <&duart_pins_a>;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
};
};
ahb@80080000 {
usb0: usb@80080000 {
status = "okay";
};
};
backlight_display: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 2 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};

333
arch/arm/dts/imx23-pinfunc.h Normal file
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@ -0,0 +1,333 @@
/*
* Header providing constants for i.MX23 pinctrl bindings.
*
* Copyright (C) 2013 Lothar Waßmann <LW@KARO-electronics.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __DT_BINDINGS_MX23_PINCTRL_H__
#define __DT_BINDINGS_MX23_PINCTRL_H__
#include "mxs-pinfunc.h"
#define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
#define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
#define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
#define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
#define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
#define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
#define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
#define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
#define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
#define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
#define MX23_PAD_GPMI_D10__GPMI_D10 0x00a0
#define MX23_PAD_GPMI_D11__GPMI_D11 0x00b0
#define MX23_PAD_GPMI_D12__GPMI_D12 0x00c0
#define MX23_PAD_GPMI_D13__GPMI_D13 0x00d0
#define MX23_PAD_GPMI_D14__GPMI_D14 0x00e0
#define MX23_PAD_GPMI_D15__GPMI_D15 0x00f0
#define MX23_PAD_GPMI_CLE__GPMI_CLE 0x0100
#define MX23_PAD_GPMI_ALE__GPMI_ALE 0x0110
#define MX23_PAD_GPMI_CE2N__GPMI_CE2N 0x0120
#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 0x0130
#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 0x0140
#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 0x0150
#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 0x0160
#define MX23_PAD_GPMI_WPN__GPMI_WPN 0x0170
#define MX23_PAD_GPMI_WRN__GPMI_WRN 0x0180
#define MX23_PAD_GPMI_RDN__GPMI_RDN 0x0190
#define MX23_PAD_AUART1_CTS__AUART1_CTS 0x01a0
#define MX23_PAD_AUART1_RTS__AUART1_RTS 0x01b0
#define MX23_PAD_AUART1_RX__AUART1_RX 0x01c0
#define MX23_PAD_AUART1_TX__AUART1_TX 0x01d0
#define MX23_PAD_I2C_SCL__I2C_SCL 0x01e0
#define MX23_PAD_I2C_SDA__I2C_SDA 0x01f0
#define MX23_PAD_LCD_D00__LCD_D00 0x1000
#define MX23_PAD_LCD_D01__LCD_D01 0x1010
#define MX23_PAD_LCD_D02__LCD_D02 0x1020
#define MX23_PAD_LCD_D03__LCD_D03 0x1030
#define MX23_PAD_LCD_D04__LCD_D04 0x1040
#define MX23_PAD_LCD_D05__LCD_D05 0x1050
#define MX23_PAD_LCD_D06__LCD_D06 0x1060
#define MX23_PAD_LCD_D07__LCD_D07 0x1070
#define MX23_PAD_LCD_D08__LCD_D08 0x1080
#define MX23_PAD_LCD_D09__LCD_D09 0x1090
#define MX23_PAD_LCD_D10__LCD_D10 0x10a0
#define MX23_PAD_LCD_D11__LCD_D11 0x10b0
#define MX23_PAD_LCD_D12__LCD_D12 0x10c0
#define MX23_PAD_LCD_D13__LCD_D13 0x10d0
#define MX23_PAD_LCD_D14__LCD_D14 0x10e0
#define MX23_PAD_LCD_D15__LCD_D15 0x10f0
#define MX23_PAD_LCD_D16__LCD_D16 0x1100
#define MX23_PAD_LCD_D17__LCD_D17 0x1110
#define MX23_PAD_LCD_RESET__LCD_RESET 0x1120
#define MX23_PAD_LCD_RS__LCD_RS 0x1130
#define MX23_PAD_LCD_WR__LCD_WR 0x1140
#define MX23_PAD_LCD_CS__LCD_CS 0x1150
#define MX23_PAD_LCD_DOTCK__LCD_DOTCK 0x1160
#define MX23_PAD_LCD_ENABLE__LCD_ENABLE 0x1170
#define MX23_PAD_LCD_HSYNC__LCD_HSYNC 0x1180
#define MX23_PAD_LCD_VSYNC__LCD_VSYNC 0x1190
#define MX23_PAD_PWM0__PWM0 0x11a0
#define MX23_PAD_PWM1__PWM1 0x11b0
#define MX23_PAD_PWM2__PWM2 0x11c0
#define MX23_PAD_PWM3__PWM3 0x11d0
#define MX23_PAD_PWM4__PWM4 0x11e0
#define MX23_PAD_SSP1_CMD__SSP1_CMD 0x2000
#define MX23_PAD_SSP1_DETECT__SSP1_DETECT 0x2010
#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 0x2020
#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 0x2030
#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 0x2040
#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 0x2050
#define MX23_PAD_SSP1_SCK__SSP1_SCK 0x2060
#define MX23_PAD_ROTARYA__ROTARYA 0x2070
#define MX23_PAD_ROTARYB__ROTARYB 0x2080
#define MX23_PAD_EMI_A00__EMI_A00 0x2090
#define MX23_PAD_EMI_A01__EMI_A01 0x20a0
#define MX23_PAD_EMI_A02__EMI_A02 0x20b0
#define MX23_PAD_EMI_A03__EMI_A03 0x20c0
#define MX23_PAD_EMI_A04__EMI_A04 0x20d0
#define MX23_PAD_EMI_A05__EMI_A05 0x20e0
#define MX23_PAD_EMI_A06__EMI_A06 0x20f0
#define MX23_PAD_EMI_A07__EMI_A07 0x2100
#define MX23_PAD_EMI_A08__EMI_A08 0x2110
#define MX23_PAD_EMI_A09__EMI_A09 0x2120
#define MX23_PAD_EMI_A10__EMI_A10 0x2130
#define MX23_PAD_EMI_A11__EMI_A11 0x2140
#define MX23_PAD_EMI_A12__EMI_A12 0x2150
#define MX23_PAD_EMI_BA0__EMI_BA0 0x2160
#define MX23_PAD_EMI_BA1__EMI_BA1 0x2170
#define MX23_PAD_EMI_CASN__EMI_CASN 0x2180
#define MX23_PAD_EMI_CE0N__EMI_CE0N 0x2190
#define MX23_PAD_EMI_CE1N__EMI_CE1N 0x21a0
#define MX23_PAD_GPMI_CE1N__GPMI_CE1N 0x21b0
#define MX23_PAD_GPMI_CE0N__GPMI_CE0N 0x21c0
#define MX23_PAD_EMI_CKE__EMI_CKE 0x21d0
#define MX23_PAD_EMI_RASN__EMI_RASN 0x21e0
#define MX23_PAD_EMI_WEN__EMI_WEN 0x21f0
#define MX23_PAD_EMI_D00__EMI_D00 0x3000
#define MX23_PAD_EMI_D01__EMI_D01 0x3010
#define MX23_PAD_EMI_D02__EMI_D02 0x3020
#define MX23_PAD_EMI_D03__EMI_D03 0x3030
#define MX23_PAD_EMI_D04__EMI_D04 0x3040
#define MX23_PAD_EMI_D05__EMI_D05 0x3050
#define MX23_PAD_EMI_D06__EMI_D06 0x3060
#define MX23_PAD_EMI_D07__EMI_D07 0x3070
#define MX23_PAD_EMI_D08__EMI_D08 0x3080
#define MX23_PAD_EMI_D09__EMI_D09 0x3090
#define MX23_PAD_EMI_D10__EMI_D10 0x30a0
#define MX23_PAD_EMI_D11__EMI_D11 0x30b0
#define MX23_PAD_EMI_D12__EMI_D12 0x30c0
#define MX23_PAD_EMI_D13__EMI_D13 0x30d0
#define MX23_PAD_EMI_D14__EMI_D14 0x30e0
#define MX23_PAD_EMI_D15__EMI_D15 0x30f0
#define MX23_PAD_EMI_DQM0__EMI_DQM0 0x3100
#define MX23_PAD_EMI_DQM1__EMI_DQM1 0x3110
#define MX23_PAD_EMI_DQS0__EMI_DQS0 0x3120
#define MX23_PAD_EMI_DQS1__EMI_DQS1 0x3130
#define MX23_PAD_EMI_CLK__EMI_CLK 0x3140
#define MX23_PAD_EMI_CLKN__EMI_CLKN 0x3150
#define MX23_PAD_GPMI_D00__LCD_D8 0x0001
#define MX23_PAD_GPMI_D01__LCD_D9 0x0011
#define MX23_PAD_GPMI_D02__LCD_D10 0x0021
#define MX23_PAD_GPMI_D03__LCD_D11 0x0031
#define MX23_PAD_GPMI_D04__LCD_D12 0x0041
#define MX23_PAD_GPMI_D05__LCD_D13 0x0051
#define MX23_PAD_GPMI_D06__LCD_D14 0x0061
#define MX23_PAD_GPMI_D07__LCD_D15 0x0071
#define MX23_PAD_GPMI_D08__LCD_D18 0x0081
#define MX23_PAD_GPMI_D09__LCD_D19 0x0091
#define MX23_PAD_GPMI_D10__LCD_D20 0x00a1
#define MX23_PAD_GPMI_D11__LCD_D21 0x00b1
#define MX23_PAD_GPMI_D12__LCD_D22 0x00c1
#define MX23_PAD_GPMI_D13__LCD_D23 0x00d1
#define MX23_PAD_GPMI_D14__AUART2_RX 0x00e1
#define MX23_PAD_GPMI_D15__AUART2_TX 0x00f1
#define MX23_PAD_GPMI_CLE__LCD_D16 0x0101
#define MX23_PAD_GPMI_ALE__LCD_D17 0x0111
#define MX23_PAD_GPMI_CE2N__ATA_A2 0x0121
#define MX23_PAD_AUART1_RTS__IR_CLK 0x01b1
#define MX23_PAD_AUART1_RX__IR_RX 0x01c1
#define MX23_PAD_AUART1_TX__IR_TX 0x01d1
#define MX23_PAD_I2C_SCL__GPMI_RDY2 0x01e1
#define MX23_PAD_I2C_SDA__GPMI_CE2N 0x01f1
#define MX23_PAD_LCD_D00__ETM_DA8 0x1001
#define MX23_PAD_LCD_D01__ETM_DA9 0x1011
#define MX23_PAD_LCD_D02__ETM_DA10 0x1021
#define MX23_PAD_LCD_D03__ETM_DA11 0x1031
#define MX23_PAD_LCD_D04__ETM_DA12 0x1041
#define MX23_PAD_LCD_D05__ETM_DA13 0x1051
#define MX23_PAD_LCD_D06__ETM_DA14 0x1061
#define MX23_PAD_LCD_D07__ETM_DA15 0x1071
#define MX23_PAD_LCD_D08__ETM_DA0 0x1081
#define MX23_PAD_LCD_D09__ETM_DA1 0x1091
#define MX23_PAD_LCD_D10__ETM_DA2 0x10a1
#define MX23_PAD_LCD_D11__ETM_DA3 0x10b1
#define MX23_PAD_LCD_D12__ETM_DA4 0x10c1
#define MX23_PAD_LCD_D13__ETM_DA5 0x10d1
#define MX23_PAD_LCD_D14__ETM_DA6 0x10e1
#define MX23_PAD_LCD_D15__ETM_DA7 0x10f1
#define MX23_PAD_LCD_RESET__ETM_TCTL 0x1121
#define MX23_PAD_LCD_RS__ETM_TCLK 0x1131
#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 0x1161
#define MX23_PAD_LCD_ENABLE__I2C_SCL 0x1171
#define MX23_PAD_LCD_HSYNC__I2C_SDA 0x1181
#define MX23_PAD_LCD_VSYNC__LCD_BUSY 0x1191
#define MX23_PAD_PWM0__ROTARYA 0x11a1
#define MX23_PAD_PWM1__ROTARYB 0x11b1
#define MX23_PAD_PWM2__GPMI_RDY3 0x11c1
#define MX23_PAD_PWM3__ETM_TCTL 0x11d1
#define MX23_PAD_PWM4__ETM_TCLK 0x11e1
#define MX23_PAD_SSP1_DETECT__GPMI_CE3N 0x2011
#define MX23_PAD_SSP1_DATA1__I2C_SCL 0x2031
#define MX23_PAD_SSP1_DATA2__I2C_SDA 0x2041
#define MX23_PAD_ROTARYA__AUART2_RTS 0x2071
#define MX23_PAD_ROTARYB__AUART2_CTS 0x2081
#define MX23_PAD_GPMI_D00__SSP2_DATA0 0x0002
#define MX23_PAD_GPMI_D01__SSP2_DATA1 0x0012
#define MX23_PAD_GPMI_D02__SSP2_DATA2 0x0022
#define MX23_PAD_GPMI_D03__SSP2_DATA3 0x0032
#define MX23_PAD_GPMI_D04__SSP2_DATA4 0x0042
#define MX23_PAD_GPMI_D05__SSP2_DATA5 0x0052
#define MX23_PAD_GPMI_D06__SSP2_DATA6 0x0062
#define MX23_PAD_GPMI_D07__SSP2_DATA7 0x0072
#define MX23_PAD_GPMI_D08__SSP1_DATA4 0x0082
#define MX23_PAD_GPMI_D09__SSP1_DATA5 0x0092
#define MX23_PAD_GPMI_D10__SSP1_DATA6 0x00a2
#define MX23_PAD_GPMI_D11__SSP1_DATA7 0x00b2
#define MX23_PAD_GPMI_D15__GPMI_CE3N 0x00f2
#define MX23_PAD_GPMI_RDY0__SSP2_DETECT 0x0132
#define MX23_PAD_GPMI_RDY1__SSP2_CMD 0x0142
#define MX23_PAD_GPMI_WRN__SSP2_SCK 0x0182
#define MX23_PAD_AUART1_CTS__SSP1_DATA4 0x01a2
#define MX23_PAD_AUART1_RTS__SSP1_DATA5 0x01b2
#define MX23_PAD_AUART1_RX__SSP1_DATA6 0x01c2
#define MX23_PAD_AUART1_TX__SSP1_DATA7 0x01d2
#define MX23_PAD_I2C_SCL__AUART1_TX 0x01e2
#define MX23_PAD_I2C_SDA__AUART1_RX 0x01f2
#define MX23_PAD_LCD_D08__SAIF2_SDATA0 0x1082
#define MX23_PAD_LCD_D09__SAIF1_SDATA0 0x1092
#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK 0x10a2
#define MX23_PAD_LCD_D11__SAIF_LRCLK 0x10b2
#define MX23_PAD_LCD_D12__SAIF2_SDATA1 0x10c2
#define MX23_PAD_LCD_D13__SAIF2_SDATA2 0x10d2
#define MX23_PAD_LCD_D14__SAIF1_SDATA2 0x10e2
#define MX23_PAD_LCD_D15__SAIF1_SDATA1 0x10f2
#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK 0x1102
#define MX23_PAD_LCD_RESET__GPMI_CE3N 0x1122
#define MX23_PAD_PWM0__DUART_RX 0x11a2
#define MX23_PAD_PWM1__DUART_TX 0x11b2
#define MX23_PAD_PWM3__AUART1_CTS 0x11d2
#define MX23_PAD_PWM4__AUART1_RTS 0x11e2
#define MX23_PAD_SSP1_CMD__JTAG_TDO 0x2002
#define MX23_PAD_SSP1_DETECT__USB_OTG_ID 0x2012
#define MX23_PAD_SSP1_DATA0__JTAG_TDI 0x2022
#define MX23_PAD_SSP1_DATA1__JTAG_TCLK 0x2032
#define MX23_PAD_SSP1_DATA2__JTAG_RTCK 0x2042
#define MX23_PAD_SSP1_DATA3__JTAG_TMS 0x2052
#define MX23_PAD_SSP1_SCK__JTAG_TRST 0x2062
#define MX23_PAD_ROTARYA__SPDIF 0x2072
#define MX23_PAD_ROTARYB__GPMI_CE3N 0x2082
#define MX23_PAD_GPMI_D00__GPIO_0_0 0x0003
#define MX23_PAD_GPMI_D01__GPIO_0_1 0x0013
#define MX23_PAD_GPMI_D02__GPIO_0_2 0x0023
#define MX23_PAD_GPMI_D03__GPIO_0_3 0x0033
#define MX23_PAD_GPMI_D04__GPIO_0_4 0x0043
#define MX23_PAD_GPMI_D05__GPIO_0_5 0x0053
#define MX23_PAD_GPMI_D06__GPIO_0_6 0x0063
#define MX23_PAD_GPMI_D07__GPIO_0_7 0x0073
#define MX23_PAD_GPMI_D08__GPIO_0_8 0x0083
#define MX23_PAD_GPMI_D09__GPIO_0_9 0x0093
#define MX23_PAD_GPMI_D10__GPIO_0_10 0x00a3
#define MX23_PAD_GPMI_D11__GPIO_0_11 0x00b3
#define MX23_PAD_GPMI_D12__GPIO_0_12 0x00c3
#define MX23_PAD_GPMI_D13__GPIO_0_13 0x00d3
#define MX23_PAD_GPMI_D14__GPIO_0_14 0x00e3
#define MX23_PAD_GPMI_D15__GPIO_0_15 0x00f3
#define MX23_PAD_GPMI_CLE__GPIO_0_16 0x0103
#define MX23_PAD_GPMI_ALE__GPIO_0_17 0x0113
#define MX23_PAD_GPMI_CE2N__GPIO_0_18 0x0123
#define MX23_PAD_GPMI_RDY0__GPIO_0_19 0x0133
#define MX23_PAD_GPMI_RDY1__GPIO_0_20 0x0143
#define MX23_PAD_GPMI_RDY2__GPIO_0_21 0x0153
#define MX23_PAD_GPMI_RDY3__GPIO_0_22 0x0163
#define MX23_PAD_GPMI_WPN__GPIO_0_23 0x0173
#define MX23_PAD_GPMI_WRN__GPIO_0_24 0x0183
#define MX23_PAD_GPMI_RDN__GPIO_0_25 0x0193
#define MX23_PAD_AUART1_CTS__GPIO_0_26 0x01a3
#define MX23_PAD_AUART1_RTS__GPIO_0_27 0x01b3
#define MX23_PAD_AUART1_RX__GPIO_0_28 0x01c3
#define MX23_PAD_AUART1_TX__GPIO_0_29 0x01d3
#define MX23_PAD_I2C_SCL__GPIO_0_30 0x01e3
#define MX23_PAD_I2C_SDA__GPIO_0_31 0x01f3
#define MX23_PAD_LCD_D00__GPIO_1_0 0x1003
#define MX23_PAD_LCD_D01__GPIO_1_1 0x1013
#define MX23_PAD_LCD_D02__GPIO_1_2 0x1023
#define MX23_PAD_LCD_D03__GPIO_1_3 0x1033
#define MX23_PAD_LCD_D04__GPIO_1_4 0x1043
#define MX23_PAD_LCD_D05__GPIO_1_5 0x1053
#define MX23_PAD_LCD_D06__GPIO_1_6 0x1063
#define MX23_PAD_LCD_D07__GPIO_1_7 0x1073
#define MX23_PAD_LCD_D08__GPIO_1_8 0x1083
#define MX23_PAD_LCD_D09__GPIO_1_9 0x1093
#define MX23_PAD_LCD_D10__GPIO_1_10 0x10a3
#define MX23_PAD_LCD_D11__GPIO_1_11 0x10b3
#define MX23_PAD_LCD_D12__GPIO_1_12 0x10c3
#define MX23_PAD_LCD_D13__GPIO_1_13 0x10d3
#define MX23_PAD_LCD_D14__GPIO_1_14 0x10e3
#define MX23_PAD_LCD_D15__GPIO_1_15 0x10f3
#define MX23_PAD_LCD_D16__GPIO_1_16 0x1103
#define MX23_PAD_LCD_D17__GPIO_1_17 0x1113
#define MX23_PAD_LCD_RESET__GPIO_1_18 0x1123
#define MX23_PAD_LCD_RS__GPIO_1_19 0x1133
#define MX23_PAD_LCD_WR__GPIO_1_20 0x1143
#define MX23_PAD_LCD_CS__GPIO_1_21 0x1153
#define MX23_PAD_LCD_DOTCK__GPIO_1_22 0x1163
#define MX23_PAD_LCD_ENABLE__GPIO_1_23 0x1173
#define MX23_PAD_LCD_HSYNC__GPIO_1_24 0x1183
#define MX23_PAD_LCD_VSYNC__GPIO_1_25 0x1193
#define MX23_PAD_PWM0__GPIO_1_26 0x11a3
#define MX23_PAD_PWM1__GPIO_1_27 0x11b3
#define MX23_PAD_PWM2__GPIO_1_28 0x11c3
#define MX23_PAD_PWM3__GPIO_1_29 0x11d3
#define MX23_PAD_PWM4__GPIO_1_30 0x11e3
#define MX23_PAD_SSP1_CMD__GPIO_2_0 0x2003
#define MX23_PAD_SSP1_DETECT__GPIO_2_1 0x2013
#define MX23_PAD_SSP1_DATA0__GPIO_2_2 0x2023
#define MX23_PAD_SSP1_DATA1__GPIO_2_3 0x2033
#define MX23_PAD_SSP1_DATA2__GPIO_2_4 0x2043
#define MX23_PAD_SSP1_DATA3__GPIO_2_5 0x2053
#define MX23_PAD_SSP1_SCK__GPIO_2_6 0x2063
#define MX23_PAD_ROTARYA__GPIO_2_7 0x2073
#define MX23_PAD_ROTARYB__GPIO_2_8 0x2083
#define MX23_PAD_EMI_A00__GPIO_2_9 0x2093
#define MX23_PAD_EMI_A01__GPIO_2_10 0x20a3
#define MX23_PAD_EMI_A02__GPIO_2_11 0x20b3
#define MX23_PAD_EMI_A03__GPIO_2_12 0x20c3
#define MX23_PAD_EMI_A04__GPIO_2_13 0x20d3
#define MX23_PAD_EMI_A05__GPIO_2_14 0x20e3
#define MX23_PAD_EMI_A06__GPIO_2_15 0x20f3
#define MX23_PAD_EMI_A07__GPIO_2_16 0x2103
#define MX23_PAD_EMI_A08__GPIO_2_17 0x2113
#define MX23_PAD_EMI_A09__GPIO_2_18 0x2123
#define MX23_PAD_EMI_A10__GPIO_2_19 0x2133
#define MX23_PAD_EMI_A11__GPIO_2_20 0x2143
#define MX23_PAD_EMI_A12__GPIO_2_21 0x2153
#define MX23_PAD_EMI_BA0__GPIO_2_22 0x2163
#define MX23_PAD_EMI_BA1__GPIO_2_23 0x2173
#define MX23_PAD_EMI_CASN__GPIO_2_24 0x2183
#define MX23_PAD_EMI_CE0N__GPIO_2_25 0x2193
#define MX23_PAD_EMI_CE1N__GPIO_2_26 0x21a3
#define MX23_PAD_GPMI_CE1N__GPIO_2_27 0x21b3
#define MX23_PAD_GPMI_CE0N__GPIO_2_28 0x21c3
#define MX23_PAD_EMI_CKE__GPIO_2_29 0x21d3
#define MX23_PAD_EMI_RASN__GPIO_2_30 0x21e3
#define MX23_PAD_EMI_WEN__GPIO_2_31 0x21f3
#endif /* __DT_BINDINGS_MX23_PINCTRL_H__ */

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arch/arm/dts/imx23-u-boot.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
&gpio0 {
gpio-ranges = <&pinctrl 0 0 32>;
};
&gpio1 {
gpio-ranges = <&pinctrl 0 32 31>;
};
&gpio2 {
gpio-ranges = <&pinctrl 0 63 32>;
};

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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2012 Freescale Semiconductor, Inc.
#include "imx23-pinfunc.h"
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&icoll>;
/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
*/
chosen {};
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
serial0 = &auart0;
serial1 = &auart1;
spi0 = &ssp0;
spi1 = &ssp1;
usbphy0 = &usbphy0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,arm926ej-s";
device_type = "cpu";
reg = <0>;
};
};
apb@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x80000>;
ranges;
apbh@80000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x40000>;
ranges;
icoll: interrupt-controller@80000000 {
compatible = "fsl,imx23-icoll", "fsl,icoll";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x80000000 0x2000>;
};
dma_apbh: dma-apbh@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 0x2000>;
interrupts = <0 14 20 0
13 13 13 13>;
interrupt-names = "empty", "ssp0", "ssp1", "empty",
"gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <8>;
clocks = <&clks 15>;
};
ecc@80008000 {
reg = <0x80008000 0x2000>;
status = "disabled";
};
nand-controller@8000c000 {
compatible = "fsl,imx23-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <56>;
interrupt-names = "bch";
clocks = <&clks 34>;
clock-names = "gpmi_io";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
status = "disabled";
};
ssp0: spi@80010000 {
reg = <0x80010000 0x2000>;
interrupts = <15>;
clocks = <&clks 33>;
dmas = <&dma_apbh 1>;
dma-names = "rx-tx";
status = "disabled";
};
etm@80014000 {
reg = <0x80014000 0x2000>;
status = "disabled";
};
pinctrl: pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-pinctrl", "simple-bus";
reg = <0x80018000 0x2000>;
gpio0: gpio@0 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
reg = <0>;
interrupts = <16>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@1 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
reg = <1>;
interrupts = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@2 {
compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
reg = <2>;
interrupts = <18>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
duart_pins_a: duart@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_PWM0__DUART_RX
MX23_PAD_PWM1__DUART_TX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart0_pins_a: auart0@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_AUART1_RX__AUART1_RX
MX23_PAD_AUART1_TX__AUART1_TX
MX23_PAD_AUART1_CTS__AUART1_CTS
MX23_PAD_AUART1_RTS__AUART1_RTS
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart0_2pins_a: auart0-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_I2C_SCL__AUART1_TX
MX23_PAD_I2C_SDA__AUART1_RX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
auart1_2pins_a: auart1-2pins@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D14__AUART2_RX
MX23_PAD_GPMI_D15__AUART2_TX
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpmi_pins_a: gpmi-nand@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__GPMI_D00
MX23_PAD_GPMI_D01__GPMI_D01
MX23_PAD_GPMI_D02__GPMI_D02
MX23_PAD_GPMI_D03__GPMI_D03
MX23_PAD_GPMI_D04__GPMI_D04
MX23_PAD_GPMI_D05__GPMI_D05
MX23_PAD_GPMI_D06__GPMI_D06
MX23_PAD_GPMI_D07__GPMI_D07
MX23_PAD_GPMI_CLE__GPMI_CLE
MX23_PAD_GPMI_ALE__GPMI_ALE
MX23_PAD_GPMI_RDY0__GPMI_RDY0
MX23_PAD_GPMI_RDY1__GPMI_RDY1
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
MX23_PAD_GPMI_RDN__GPMI_RDN
MX23_PAD_GPMI_CE1N__GPMI_CE1N
MX23_PAD_GPMI_CE0N__GPMI_CE0N
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
gpmi_pins_fixup: gpmi-pins-fixup@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_WPN__GPMI_WPN
MX23_PAD_GPMI_WRN__GPMI_WRN
MX23_PAD_GPMI_RDN__GPMI_RDN
>;
fsl,drive-strength = <MXS_DRIVE_12mA>;
};
mmc0_4bit_pins_a: mmc0-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA0__SSP1_DATA0
MX23_PAD_SSP1_DATA1__SSP1_DATA1
MX23_PAD_SSP1_DATA2__SSP1_DATA2
MX23_PAD_SSP1_DATA3__SSP1_DATA3
MX23_PAD_SSP1_CMD__SSP1_CMD
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc0_8bit_pins_a: mmc0-8bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA0__SSP1_DATA0
MX23_PAD_SSP1_DATA1__SSP1_DATA1
MX23_PAD_SSP1_DATA2__SSP1_DATA2
MX23_PAD_SSP1_DATA3__SSP1_DATA3
MX23_PAD_GPMI_D08__SSP1_DATA4
MX23_PAD_GPMI_D09__SSP1_DATA5
MX23_PAD_GPMI_D10__SSP1_DATA6
MX23_PAD_GPMI_D11__SSP1_DATA7
MX23_PAD_SSP1_CMD__SSP1_CMD
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc0_pins_fixup: mmc0-pins-fixup@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DETECT__SSP1_DETECT
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc0_sck_cfg: mmc0-sck-cfg@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
mmc1_4bit_pins_a: mmc1-4bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D01__SSP2_DATA1
MX23_PAD_GPMI_D02__SSP2_DATA2
MX23_PAD_GPMI_D03__SSP2_DATA3
MX23_PAD_GPMI_RDY1__SSP2_CMD
MX23_PAD_GPMI_WRN__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
mmc1_8bit_pins_a: mmc1-8bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D01__SSP2_DATA1
MX23_PAD_GPMI_D02__SSP2_DATA2
MX23_PAD_GPMI_D03__SSP2_DATA3
MX23_PAD_GPMI_D04__SSP2_DATA4
MX23_PAD_GPMI_D05__SSP2_DATA5
MX23_PAD_GPMI_D06__SSP2_DATA6
MX23_PAD_GPMI_D07__SSP2_DATA7
MX23_PAD_GPMI_RDY1__SSP2_CMD
MX23_PAD_GPMI_WRN__SSP2_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
pwm2_pins_a: pwm2@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_PWM2__PWM2
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_24bit_pins_a: lcdif-24bit@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_LCD_D00__LCD_D00
MX23_PAD_LCD_D01__LCD_D01
MX23_PAD_LCD_D02__LCD_D02
MX23_PAD_LCD_D03__LCD_D03
MX23_PAD_LCD_D04__LCD_D04
MX23_PAD_LCD_D05__LCD_D05
MX23_PAD_LCD_D06__LCD_D06
MX23_PAD_LCD_D07__LCD_D07
MX23_PAD_LCD_D08__LCD_D08
MX23_PAD_LCD_D09__LCD_D09
MX23_PAD_LCD_D10__LCD_D10
MX23_PAD_LCD_D11__LCD_D11
MX23_PAD_LCD_D12__LCD_D12
MX23_PAD_LCD_D13__LCD_D13
MX23_PAD_LCD_D14__LCD_D14
MX23_PAD_LCD_D15__LCD_D15
MX23_PAD_LCD_D16__LCD_D16
MX23_PAD_LCD_D17__LCD_D17
MX23_PAD_GPMI_D08__LCD_D18
MX23_PAD_GPMI_D09__LCD_D19
MX23_PAD_GPMI_D10__LCD_D20
MX23_PAD_GPMI_D11__LCD_D21
MX23_PAD_GPMI_D12__LCD_D22
MX23_PAD_GPMI_D13__LCD_D23
MX23_PAD_LCD_DOTCK__LCD_DOTCK
MX23_PAD_LCD_ENABLE__LCD_ENABLE
MX23_PAD_LCD_HSYNC__LCD_HSYNC
MX23_PAD_LCD_VSYNC__LCD_VSYNC
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
spi2_pins_a: spi2@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_GPMI_WRN__SSP2_SCK
MX23_PAD_GPMI_RDY1__SSP2_CMD
MX23_PAD_GPMI_D00__SSP2_DATA0
MX23_PAD_GPMI_D03__SSP2_DATA3
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c_pins_a: i2c@0 {
reg = <0>;
fsl,pinmux-ids = <
MX23_PAD_I2C_SCL__I2C_SCL
MX23_PAD_I2C_SDA__I2C_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c_pins_b: i2c@1 {
reg = <1>;
fsl,pinmux-ids = <
MX23_PAD_LCD_ENABLE__I2C_SCL
MX23_PAD_LCD_HSYNC__I2C_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
i2c_pins_c: i2c@2 {
reg = <2>;
fsl,pinmux-ids = <
MX23_PAD_SSP1_DATA1__I2C_SCL
MX23_PAD_SSP1_DATA2__I2C_SDA
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
};
digctl@8001c000 {
compatible = "fsl,imx23-digctl";
reg = <0x8001c000 2000>;
status = "disabled";
};
emi@80020000 {
reg = <0x80020000 0x2000>;
status = "disabled";
};
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
interrupts = <7 5 9 26
19 0 25 23
60 58 9 0
0 0 0 0>;
interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
"saif0", "empty", "auart0-rx", "auart0-tx",
"auart1-rx", "auart1-tx", "saif1", "empty",
"empty", "empty", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 16>;
};
dcp: crypto@80028000 {
compatible = "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <53 54>;
status = "okay";
};
pxp@8002a000 {
reg = <0x8002a000 0x2000>;
status = "disabled";
};
efuse@8002c000 {
compatible = "fsl,imx23-ocotp", "fsl,ocotp";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x8002c000 0x2000>;
clocks = <&clks 15>;
};
axi-ahb@8002e000 {
reg = <0x8002e000 0x2000>;
status = "disabled";
};
lcdif@80030000 {
compatible = "fsl,imx23-lcdif";
reg = <0x80030000 2000>;
interrupts = <46 45>;
clocks = <&clks 38>;
status = "disabled";
};
ssp1: spi@80034000 {
reg = <0x80034000 0x2000>;
interrupts = <2>;
clocks = <&clks 33>;
dmas = <&dma_apbh 2>;
dma-names = "rx-tx";
status = "disabled";
};
tvenc@80038000 {
reg = <0x80038000 0x2000>;
status = "disabled";
};
};
apbx@80040000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80040000 0x40000>;
ranges;
clks: clkctrl@80040000 {
compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
reg = <0x80040000 0x2000>;
#clock-cells = <1>;
};
saif0: saif@80042000 {
reg = <0x80042000 0x2000>;
dmas = <&dma_apbx 4>;
dma-names = "rx-tx";
status = "disabled";
};
power@80044000 {
reg = <0x80044000 0x2000>;
status = "disabled";
};
saif1: saif@80046000 {
reg = <0x80046000 0x2000>;
dmas = <&dma_apbx 10>;
dma-names = "rx-tx";
status = "disabled";
};
audio-out@80048000 {
reg = <0x80048000 0x2000>;
dmas = <&dma_apbx 1>;
dma-names = "tx";
status = "disabled";
};
audio-in@8004c000 {
reg = <0x8004c000 0x2000>;
dmas = <&dma_apbx 0>;
dma-names = "rx";
status = "disabled";
};
lradc: lradc@80050000 {
compatible = "fsl,imx23-lradc";
reg = <0x80050000 0x2000>;
interrupts = <36 37 38 39 40 41 42 43 44>;
status = "disabled";
clocks = <&clks 26>;
#io-channel-cells = <1>;
};
spdif@80054000 {
reg = <0x80054000 2000>;
dmas = <&dma_apbx 2>;
dma-names = "tx";
status = "disabled";
};
i2c: i2c@80058000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-i2c";
reg = <0x80058000 0x2000>;
interrupts = <27>;
clock-frequency = <100000>;
dmas = <&dma_apbx 3>;
dma-names = "rx-tx";
status = "disabled";
};
rtc@8005c000 {
compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
reg = <0x8005c000 0x2000>;
interrupts = <22>;
};
pwm: pwm@80064000 {
compatible = "fsl,imx23-pwm";
reg = <0x80064000 0x2000>;
clocks = <&clks 30>;
#pwm-cells = <2>;
fsl,pwm-number = <5>;
status = "disabled";
};
timrot@80068000 {
compatible = "fsl,imx23-timrot", "fsl,timrot";
reg = <0x80068000 0x2000>;
interrupts = <28 29 30 31>;
clocks = <&clks 28>;
};
auart0: serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24>;
clocks = <&clks 32>;
dmas = <&dma_apbx 6>, <&dma_apbx 7>;
dma-names = "rx", "tx";
status = "disabled";
};
auart1: serial@8006e000 {
compatible = "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <59>;
clocks = <&clks 32>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
status = "disabled";
};
duart: serial@80070000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x80070000 0x2000>;
interrupts = <0>;
clocks = <&clks 32>, <&clks 16>;
clock-names = "uart", "apb_pclk";
status = "disabled";
};
usbphy0: usbphy@8007c000 {
compatible = "fsl,imx23-usbphy";
reg = <0x8007c000 0x2000>;
clocks = <&clks 41>;
status = "disabled";
};
};
};
ahb@80080000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80080000 0x80000>;
ranges;
usb0: usb@80080000 {
compatible = "fsl,imx23-usb", "fsl,imx27-usb";
reg = <0x80080000 0x40000>;
interrupts = <11>;
fsl,usbphy = <&usbphy0>;
clocks = <&clks 40>;
status = "disabled";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&lradc 8>;
};
};

726
arch/arm/dts/imx51-babbage.dts Normal file
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@ -0,0 +1,726 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx51.dtsi"
/ {
model = "Freescale i.MX51 Babbage Board";
compatible = "fsl,imx51-babbage", "fsl,imx51";
chosen {
stdout-path = &uart1;
};
memory@90000000 {
device_type = "memory";
reg = <0x90000000 0x20000000>;
};
ckih1 {
clock-frequency = <22579200>;
};
clk_osc: clk-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk_osc_gate: clk-osc-gate {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clk26mhz_osc>;
clocks = <&clk_osc>;
#clock-cells = <0>;
enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
clk_audio: clk-audio {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clk26mhz_audio>;
clocks = <&clk_osc_gate>;
#clock-cells = <0>;
enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
};
clk_usb: clk-usb {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_clk26mhz_usb>;
clocks = <&clk_osc_gate>;
#clock-cells = <0>;
enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
display1: disp1 {
compatible = "fsl,imx-parallel-display";
#address-cells = <1>;
#size-cells = <0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp1>;
};
};
port@1 {
reg = <1>;
parallel_display_out: endpoint {
remote-endpoint = <&tfp410_in>;
};
};
};
display2: disp2 {
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2>;
status = "disabled";
display-timings {
native-mode = <&timing1>;
timing1: claawvga {
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
port {
display1_in: endpoint {
remote-endpoint = <&ipu_di1_disp2>;
};
};
};
dvi-connector {
compatible = "dvi-connector";
digital;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
dvi-encoder {
compatible = "ti,tfp410";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&parallel_display_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_POWER>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-diagnostic {
label = "diagnostic";
gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_hub_reset: regulator@0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotgreg>;
reg = <0>;
regulator-name = "hub_reset";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx51-babbage-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <3>;
};
usbphy1: usbphy1 {
compatible = "usb-nop-xceiv";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1reg>;
clocks = <&clk_usb>;
clock-names = "main_clk";
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
vcc-supply = <&vusb_reg>;
#phy-cells = <0>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
pmic: mc13892@0 {
compatible = "fsl,mc13892";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
spi-max-frequency = <6000000>;
spi-cs-high;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
fsl,mc13xxx-uses-adc;
fsl,mc13xxx-uses-rtc;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdig_reg: vdig {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
};
vsd_reg: vsd {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3150000>;
};
vusb_reg: vusb {
regulator-boot-on;
};
vusb2_reg: vusb2 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vvideo_reg: vvideo {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
};
vaudio_reg: vaudio {
regulator-min-microvolt = <2300000>;
regulator-max-microvolt = <3000000>;
};
vcam_reg: vcam {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
};
};
flash: at45db321d@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "U-Boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "Kernel";
reg = <0x40000 0x3c0000>;
};
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2>;
cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "mii";
phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clk_audio>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
&ipu_di0_disp1 {
remote-endpoint = <&display0_in>;
};
&ipu_di1_disp2 {
remote-endpoint = <&display1_in>;
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>;
linux,keymap = <
MATRIX_KEY(0, 0, KEY_UP)
MATRIX_KEY(0, 1, KEY_DOWN)
MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
MATRIX_KEY(0, 3, KEY_HOME)
MATRIX_KEY(1, 0, KEY_RIGHT)
MATRIX_KEY(1, 1, KEY_LEFT)
MATRIX_KEY(1, 2, KEY_ENTER)
MATRIX_KEY(1, 3, KEY_VOLUMEUP)
MATRIX_KEY(2, 0, KEY_F6)
MATRIX_KEY(2, 1, KEY_F8)
MATRIX_KEY(2, 2, KEY_F9)
MATRIX_KEY(2, 3, KEY_F10)
MATRIX_KEY(3, 0, KEY_F1)
MATRIX_KEY(3, 1, KEY_F2)
MATRIX_KEY(3, 2, KEY_F3)
MATRIX_KEY(3, 3, KEY_POWER)
>;
status = "okay";
};
&pmu {
secure-reg-access;
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_hub_reset>;
fsl,usbphy = <&usbphy1>;
phy_type = "ulpi";
status = "okay";
};
&usbphy0 {
vcc-supply = <&vusb_reg>;
};
&usbotg {
dr_mode = "otg";
disable-over-current;
phy_type = "utmi_wide";
status = "okay";
};
&iomuxc {
imx51-babbage {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
>;
};
pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
fsl,pins = <
MX51_PAD_CSPI1_RDY__GPIO4_26 0x85
>;
};
pinctrl_clk26mhz_osc: clk26mhzoscgrp {
fsl,pins = <
MX51_PAD_DI1_PIN12__GPIO3_1 0x85
>;
};
pinctrl_clk26mhz_usb: clk26mhzusbgrp {
fsl,pins = <
MX51_PAD_EIM_D17__GPIO2_1 0x85
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 /* CS1 */
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
MX51_PAD_GPIO1_0__GPIO1_0 0x100
MX51_PAD_GPIO1_1__GPIO1_1 0x100
>;
};
pinctrl_esdhc2: esdhc2grp {
fsl,pins = <
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
MX51_PAD_GPIO1_5__GPIO1_5 0x100 /* WP */
MX51_PAD_GPIO1_6__GPIO1_6 0x100 /* CD */
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
MX51_PAD_NANDF_RB2__FEC_COL 0x00000180
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x00000180
MX51_PAD_NANDF_D9__FEC_RDATA0 0x00002180
MX51_PAD_NANDF_D8__FEC_TDATA0 0x00002004
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
MX51_PAD_NANDF_CS3__FEC_MDC 0x00002004
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x00002004
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x00002004
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x00002004
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x00002004
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x00002180
MX51_PAD_NANDF_D11__FEC_RX_DV 0x000020a4
MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX51_PAD_EIM_A27__GPIO2_21 0x5
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX51_PAD_EIM_D22__GPIO2_6 0x80000000
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX51_PAD_EIM_D19__I2C1_SCL 0x400001ed
MX51_PAD_EIM_D16__I2C1_SDA 0x400001ed
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
>;
};
pinctrl_ipu_disp1: ipudisp1grp {
fsl,pins = <
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
>;
};
pinctrl_ipu_disp2: ipudisp2grp {
fsl,pins = <
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
MX51_PAD_DI_GP4__DI2_PIN15 0x5
>;
};
pinctrl_kpp: kppgrp {
fsl,pins = <
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX51_PAD_GPIO1_8__GPIO1_8 0xe5 /* IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX51_PAD_USBH1_CLK__USBH1_CLK 0x80000000
MX51_PAD_USBH1_DIR__USBH1_DIR 0x80000000
MX51_PAD_USBH1_NXT__USBH1_NXT 0x80000000
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x80000000
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x80000000
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x80000000
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x80000000
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x80000000
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x80000000
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x80000000
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x80000000
>;
};
pinctrl_usbh1reg: usbh1reggrp {
fsl,pins = <
MX51_PAD_EIM_D21__GPIO2_5 0x85
>;
};
pinctrl_usbotgreg: usbotgreggrp {
fsl,pins = <
MX51_PAD_GPIO1_7__GPIO1_7 0x85
>;
};
};
};

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arch/arm/dts/imx51-pinfunc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#ifndef __DTS_IMX51_PINFUNC_H
#define __DTS_IMX51_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
#define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
#define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
#define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
#define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
#define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
#define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
#define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
#define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
#define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
#define MX51_PAD_EIM_D17__UART2_RXD 0x060 0x3f4 0x9ec 0x3 0x0
#define MX51_PAD_EIM_D17__UART3_CTS 0x060 0x3f4 0x000 0x4 0x0
#define MX51_PAD_EIM_D17__USBH2_DATA1 0x060 0x3f4 0x000 0x2 0x0
#define MX51_PAD_EIM_D18__AUD5_TXC 0x064 0x3f8 0x8e4 0x7 0x0
#define MX51_PAD_EIM_D18__EIM_D18 0x064 0x3f8 0x000 0x0 0x0
#define MX51_PAD_EIM_D18__GPIO2_2 0x064 0x3f8 0x000 0x1 0x0
#define MX51_PAD_EIM_D18__UART2_TXD 0x064 0x3f8 0x000 0x3 0x0
#define MX51_PAD_EIM_D18__UART3_RTS 0x064 0x3f8 0x9f0 0x4 0x1
#define MX51_PAD_EIM_D18__USBH2_DATA2 0x064 0x3f8 0x000 0x2 0x0
#define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0
#define MX51_PAD_EIM_D19__AUD5_TXFS 0x068 0x3fc 0x8e8 0x7 0x0
#define MX51_PAD_EIM_D19__EIM_D19 0x068 0x3fc 0x000 0x0 0x0
#define MX51_PAD_EIM_D19__GPIO2_3 0x068 0x3fc 0x000 0x1 0x0
#define MX51_PAD_EIM_D19__I2C1_SCL 0x068 0x3fc 0x9b0 0x4 0x0
#define MX51_PAD_EIM_D19__UART2_RTS 0x068 0x3fc 0x9e8 0x3 0x1
#define MX51_PAD_EIM_D19__USBH2_DATA3 0x068 0x3fc 0x000 0x2 0x0
#define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0
#define MX51_PAD_EIM_D20__EIM_D20 0x06c 0x400 0x000 0x0 0x0
#define MX51_PAD_EIM_D20__GPIO2_4 0x06c 0x400 0x000 0x1 0x0
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB 0x06c 0x400 0x000 0x4 0x0
#define MX51_PAD_EIM_D20__USBH2_DATA4 0x06c 0x400 0x000 0x2 0x0
#define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0
#define MX51_PAD_EIM_D21__EIM_D21 0x070 0x404 0x000 0x0 0x0
#define MX51_PAD_EIM_D21__GPIO2_5 0x070 0x404 0x000 0x1 0x0
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB 0x070 0x404 0x000 0x3 0x0
#define MX51_PAD_EIM_D21__USBH2_DATA5 0x070 0x404 0x000 0x2 0x0
#define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0
#define MX51_PAD_EIM_D22__EIM_D22 0x074 0x408 0x000 0x0 0x0
#define MX51_PAD_EIM_D22__GPIO2_6 0x074 0x408 0x000 0x1 0x0
#define MX51_PAD_EIM_D22__USBH2_DATA6 0x074 0x408 0x000 0x2 0x0
#define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0
#define MX51_PAD_EIM_D23__EIM_D23 0x078 0x40c 0x000 0x0 0x0
#define MX51_PAD_EIM_D23__GPIO2_7 0x078 0x40c 0x000 0x1 0x0
#define MX51_PAD_EIM_D23__SPDIF_OUT1 0x078 0x40c 0x000 0x4 0x0
#define MX51_PAD_EIM_D23__USBH2_DATA7 0x078 0x40c 0x000 0x2 0x0
#define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0
#define MX51_PAD_EIM_D24__EIM_D24 0x07c 0x410 0x000 0x0 0x0
#define MX51_PAD_EIM_D24__GPIO2_8 0x07c 0x410 0x000 0x1 0x0
#define MX51_PAD_EIM_D24__I2C2_SDA 0x07c 0x410 0x9bc 0x4 0x0
#define MX51_PAD_EIM_D24__UART3_CTS 0x07c 0x410 0x000 0x3 0x0
#define MX51_PAD_EIM_D24__USBOTG_DATA0 0x07c 0x410 0x000 0x2 0x0
#define MX51_PAD_EIM_D25__EIM_D25 0x080 0x414 0x000 0x0 0x0
#define MX51_PAD_EIM_D25__KEY_COL6 0x080 0x414 0x9c8 0x1 0x0
#define MX51_PAD_EIM_D25__UART2_CTS 0x080 0x414 0x000 0x4 0x0
#define MX51_PAD_EIM_D25__UART3_RXD 0x080 0x414 0x9f4 0x3 0x0
#define MX51_PAD_EIM_D25__USBOTG_DATA1 0x080 0x414 0x000 0x2 0x0
#define MX51_PAD_EIM_D26__EIM_D26 0x084 0x418 0x000 0x0 0x0
#define MX51_PAD_EIM_D26__KEY_COL7 0x084 0x418 0x9cc 0x1 0x0
#define MX51_PAD_EIM_D26__UART2_RTS 0x084 0x418 0x9e8 0x4 0x3
#define MX51_PAD_EIM_D26__UART3_TXD 0x084 0x418 0x000 0x3 0x0
#define MX51_PAD_EIM_D26__USBOTG_DATA2 0x084 0x418 0x000 0x2 0x0
#define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0
#define MX51_PAD_EIM_D27__EIM_D27 0x088 0x41c 0x000 0x0 0x0
#define MX51_PAD_EIM_D27__GPIO2_9 0x088 0x41c 0x000 0x1 0x0
#define MX51_PAD_EIM_D27__I2C2_SCL 0x088 0x41c 0x9b8 0x4 0x0
#define MX51_PAD_EIM_D27__UART3_RTS 0x088 0x41c 0x9f0 0x3 0x3
#define MX51_PAD_EIM_D27__USBOTG_DATA3 0x088 0x41c 0x000 0x2 0x0
#define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0
#define MX51_PAD_EIM_D28__EIM_D28 0x08c 0x420 0x000 0x0 0x0
#define MX51_PAD_EIM_D28__KEY_ROW4 0x08c 0x420 0x9d0 0x1 0x0
#define MX51_PAD_EIM_D28__USBOTG_DATA4 0x08c 0x420 0x000 0x2 0x0
#define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 0x0
#define MX51_PAD_EIM_D29__EIM_D29 0x090 0x424 0x000 0x0 0x0
#define MX51_PAD_EIM_D29__KEY_ROW5 0x090 0x424 0x9d4 0x1 0x0
#define MX51_PAD_EIM_D29__USBOTG_DATA5 0x090 0x424 0x000 0x2 0x0
#define MX51_PAD_EIM_D30__AUD6_TXC 0x094 0x428 0x8fc 0x5 0x0
#define MX51_PAD_EIM_D30__EIM_D30 0x094 0x428 0x000 0x0 0x0
#define MX51_PAD_EIM_D30__KEY_ROW6 0x094 0x428 0x9d8 0x1 0x0
#define MX51_PAD_EIM_D30__USBOTG_DATA6 0x094 0x428 0x000 0x2 0x0
#define MX51_PAD_EIM_D31__AUD6_TXFS 0x098 0x42c 0x900 0x5 0x0
#define MX51_PAD_EIM_D31__EIM_D31 0x098 0x42c 0x000 0x0 0x0
#define MX51_PAD_EIM_D31__KEY_ROW7 0x098 0x42c 0x9dc 0x1 0x0
#define MX51_PAD_EIM_D31__USBOTG_DATA7 0x098 0x42c 0x000 0x2 0x0
#define MX51_PAD_EIM_A16__EIM_A16 0x09c 0x430 0x000 0x0 0x0
#define MX51_PAD_EIM_A16__GPIO2_10 0x09c 0x430 0x000 0x1 0x0
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 0x09c 0x430 0x000 0x7 0x0
#define MX51_PAD_EIM_A17__EIM_A17 0x0a0 0x434 0x000 0x0 0x0
#define MX51_PAD_EIM_A17__GPIO2_11 0x0a0 0x434 0x000 0x1 0x0
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 0x0a0 0x434 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__BOOT_LPB0 0x0a4 0x438 0x000 0x7 0x0
#define MX51_PAD_EIM_A18__EIM_A18 0x0a4 0x438 0x000 0x0 0x0
#define MX51_PAD_EIM_A18__GPIO2_12 0x0a4 0x438 0x000 0x1 0x0
#define MX51_PAD_EIM_A19__BOOT_LPB1 0x0a8 0x43c 0x000 0x7 0x0
#define MX51_PAD_EIM_A19__EIM_A19 0x0a8 0x43c 0x000 0x0 0x0
#define MX51_PAD_EIM_A19__GPIO2_13 0x0a8 0x43c 0x000 0x1 0x0
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 0x0ac 0x440 0x000 0x7 0x0
#define MX51_PAD_EIM_A20__EIM_A20 0x0ac 0x440 0x000 0x0 0x0
#define MX51_PAD_EIM_A20__GPIO2_14 0x0ac 0x440 0x000 0x1 0x0
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 0x0b0 0x444 0x000 0x7 0x0
#define MX51_PAD_EIM_A21__EIM_A21 0x0b0 0x444 0x000 0x0 0x0
#define MX51_PAD_EIM_A21__GPIO2_15 0x0b0 0x444 0x000 0x1 0x0
#define MX51_PAD_EIM_A22__EIM_A22 0x0b4 0x448 0x000 0x0 0x0
#define MX51_PAD_EIM_A22__GPIO2_16 0x0b4 0x448 0x000 0x1 0x0
#define MX51_PAD_EIM_A23__BOOT_HPN_EN 0x0b8 0x44c 0x000 0x7 0x0
#define MX51_PAD_EIM_A23__EIM_A23 0x0b8 0x44c 0x000 0x0 0x0
#define MX51_PAD_EIM_A23__GPIO2_17 0x0b8 0x44c 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__EIM_A24 0x0bc 0x450 0x000 0x0 0x0
#define MX51_PAD_EIM_A24__GPIO2_18 0x0bc 0x450 0x000 0x1 0x0
#define MX51_PAD_EIM_A24__USBH2_CLK 0x0bc 0x450 0x000 0x2 0x0
#define MX51_PAD_EIM_A25__DISP1_PIN4 0x0c0 0x454 0x000 0x6 0x0
#define MX51_PAD_EIM_A25__EIM_A25 0x0c0 0x454 0x000 0x0 0x0
#define MX51_PAD_EIM_A25__GPIO2_19 0x0c0 0x454 0x000 0x1 0x0
#define MX51_PAD_EIM_A25__USBH2_DIR 0x0c0 0x454 0x000 0x2 0x0
#define MX51_PAD_EIM_A26__CSI1_DATA_EN 0x0c4 0x458 0x9a0 0x5 0x0
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK 0x0c4 0x458 0x908 0x6 0x0
#define MX51_PAD_EIM_A26__EIM_A26 0x0c4 0x458 0x000 0x0 0x0
#define MX51_PAD_EIM_A26__GPIO2_20 0x0c4 0x458 0x000 0x1 0x0
#define MX51_PAD_EIM_A26__USBH2_STP 0x0c4 0x458 0x000 0x2 0x0
#define MX51_PAD_EIM_A27__CSI2_DATA_EN 0x0c8 0x45c 0x99c 0x5 0x0
#define MX51_PAD_EIM_A27__DISP1_PIN1 0x0c8 0x45c 0x9a4 0x6 0x0
#define MX51_PAD_EIM_A27__EIM_A27 0x0c8 0x45c 0x000 0x0 0x0
#define MX51_PAD_EIM_A27__GPIO2_21 0x0c8 0x45c 0x000 0x1 0x0
#define MX51_PAD_EIM_A27__USBH2_NXT 0x0c8 0x45c 0x000 0x2 0x0
#define MX51_PAD_EIM_EB0__EIM_EB0 0x0cc 0x460 0x000 0x0 0x0
#define MX51_PAD_EIM_EB1__EIM_EB1 0x0d0 0x464 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__AUD5_RXFS 0x0d4 0x468 0x8e0 0x6 0x0
#define MX51_PAD_EIM_EB2__CSI1_D2 0x0d4 0x468 0x000 0x5 0x0
#define MX51_PAD_EIM_EB2__EIM_EB2 0x0d4 0x468 0x000 0x0 0x0
#define MX51_PAD_EIM_EB2__FEC_MDIO 0x0d4 0x468 0x954 0x3 0x0
#define MX51_PAD_EIM_EB2__GPIO2_22 0x0d4 0x468 0x000 0x1 0x0
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 0x0d4 0x468 0x000 0x7 0x0
#define MX51_PAD_EIM_EB3__AUD5_RXC 0x0d8 0x46c 0x8dc 0x6 0x0
#define MX51_PAD_EIM_EB3__CSI1_D3 0x0d8 0x46c 0x000 0x5 0x0
#define MX51_PAD_EIM_EB3__EIM_EB3 0x0d8 0x46c 0x000 0x0 0x0
#define MX51_PAD_EIM_EB3__FEC_RDATA1 0x0d8 0x46c 0x95c 0x3 0x0
#define MX51_PAD_EIM_EB3__GPIO2_23 0x0d8 0x46c 0x000 0x1 0x0
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 0x0d8 0x46c 0x000 0x7 0x0
#define MX51_PAD_EIM_OE__EIM_OE 0x0dc 0x470 0x000 0x0 0x0
#define MX51_PAD_EIM_OE__GPIO2_24 0x0dc 0x470 0x000 0x1 0x0
#define MX51_PAD_EIM_CS0__EIM_CS0 0x0e0 0x474 0x000 0x0 0x0
#define MX51_PAD_EIM_CS0__GPIO2_25 0x0e0 0x474 0x000 0x1 0x0
#define MX51_PAD_EIM_CS1__EIM_CS1 0x0e4 0x478 0x000 0x0 0x0
#define MX51_PAD_EIM_CS1__GPIO2_26 0x0e4 0x478 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__AUD5_TXD 0x0e8 0x47c 0x8d8 0x6 0x1
#define MX51_PAD_EIM_CS2__CSI1_D4 0x0e8 0x47c 0x000 0x5 0x0
#define MX51_PAD_EIM_CS2__EIM_CS2 0x0e8 0x47c 0x000 0x0 0x0
#define MX51_PAD_EIM_CS2__FEC_RDATA2 0x0e8 0x47c 0x960 0x3 0x0
#define MX51_PAD_EIM_CS2__GPIO2_27 0x0e8 0x47c 0x000 0x1 0x0
#define MX51_PAD_EIM_CS2__USBOTG_STP 0x0e8 0x47c 0x000 0x2 0x0
#define MX51_PAD_EIM_CS3__AUD5_RXD 0x0ec 0x480 0x8d4 0x6 0x1
#define MX51_PAD_EIM_CS3__CSI1_D5 0x0ec 0x480 0x000 0x5 0x0
#define MX51_PAD_EIM_CS3__EIM_CS3 0x0ec 0x480 0x000 0x0 0x0
#define MX51_PAD_EIM_CS3__FEC_RDATA3 0x0ec 0x480 0x964 0x3 0x0
#define MX51_PAD_EIM_CS3__GPIO2_28 0x0ec 0x480 0x000 0x1 0x0
#define MX51_PAD_EIM_CS3__USBOTG_NXT 0x0ec 0x480 0x000 0x2 0x0
#define MX51_PAD_EIM_CS4__AUD5_TXC 0x0f0 0x484 0x8e4 0x6 0x1
#define MX51_PAD_EIM_CS4__CSI1_D6 0x0f0 0x484 0x000 0x5 0x0
#define MX51_PAD_EIM_CS4__EIM_CS4 0x0f0 0x484 0x000 0x0 0x0
#define MX51_PAD_EIM_CS4__FEC_RX_ER 0x0f0 0x484 0x970 0x3 0x0
#define MX51_PAD_EIM_CS4__GPIO2_29 0x0f0 0x484 0x000 0x1 0x0
#define MX51_PAD_EIM_CS4__USBOTG_CLK 0x0f0 0x484 0x000 0x2 0x0
#define MX51_PAD_EIM_CS5__AUD5_TXFS 0x0f4 0x488 0x8e8 0x6 0x1
#define MX51_PAD_EIM_CS5__CSI1_D7 0x0f4 0x488 0x000 0x5 0x0
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK 0x0f4 0x488 0x904 0x4 0x0
#define MX51_PAD_EIM_CS5__EIM_CS5 0x0f4 0x488 0x000 0x0 0x0
#define MX51_PAD_EIM_CS5__FEC_CRS 0x0f4 0x488 0x950 0x3 0x0
#define MX51_PAD_EIM_CS5__GPIO2_30 0x0f4 0x488 0x000 0x1 0x0
#define MX51_PAD_EIM_CS5__USBOTG_DIR 0x0f4 0x488 0x000 0x2 0x0
#define MX51_PAD_EIM_DTACK__EIM_DTACK 0x0f8 0x48c 0x000 0x0 0x0
#define MX51_PAD_EIM_DTACK__GPIO2_31 0x0f8 0x48c 0x000 0x1 0x0
#define MX51_PAD_EIM_LBA__EIM_LBA 0x0fc 0x494 0x000 0x0 0x0
#define MX51_PAD_EIM_LBA__GPIO3_1 0x0fc 0x494 0x978 0x1 0x0
#define MX51_PAD_EIM_CRE__EIM_CRE 0x100 0x4a0 0x000 0x0 0x0
#define MX51_PAD_EIM_CRE__GPIO3_2 0x100 0x4a0 0x97c 0x1 0x0
#define MX51_PAD_DRAM_CS1__DRAM_CS1 0x104 0x4d0 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__GPIO3_3 0x108 0x4e4 0x980 0x3 0x0
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x108 0x4e4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WE_B__PATA_DIOW 0x108 0x4e4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WE_B__SD3_DATA0 0x108 0x4e4 0x93c 0x2 0x0
#define MX51_PAD_NANDF_RE_B__GPIO3_4 0x10c 0x4e8 0x984 0x3 0x0
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x10c 0x4e8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RE_B__PATA_DIOR 0x10c 0x4e8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RE_B__SD3_DATA1 0x10c 0x4e8 0x940 0x2 0x0
#define MX51_PAD_NANDF_ALE__GPIO3_5 0x110 0x4ec 0x988 0x3 0x0
#define MX51_PAD_NANDF_ALE__NANDF_ALE 0x110 0x4ec 0x000 0x0 0x0
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x110 0x4ec 0x000 0x1 0x0
#define MX51_PAD_NANDF_CLE__GPIO3_6 0x114 0x4f0 0x98c 0x3 0x0
#define MX51_PAD_NANDF_CLE__NANDF_CLE 0x114 0x4f0 0x000 0x0 0x0
#define MX51_PAD_NANDF_CLE__PATA_RESET_B 0x114 0x4f0 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__GPIO3_7 0x118 0x4f4 0x990 0x3 0x0
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x118 0x4f4 0x000 0x0 0x0
#define MX51_PAD_NANDF_WP_B__PATA_DMACK 0x118 0x4f4 0x000 0x1 0x0
#define MX51_PAD_NANDF_WP_B__SD3_DATA2 0x118 0x4f4 0x944 0x2 0x0
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 0x11c 0x4f8 0x930 0x5 0x0
#define MX51_PAD_NANDF_RB0__GPIO3_8 0x11c 0x4f8 0x994 0x3 0x0
#define MX51_PAD_NANDF_RB0__NANDF_RB0 0x11c 0x4f8 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB0__PATA_DMARQ 0x11c 0x4f8 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB0__SD3_DATA3 0x11c 0x4f8 0x948 0x2 0x0
#define MX51_PAD_NANDF_RB1__CSPI_MOSI 0x120 0x4fc 0x91c 0x6 0x0
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY 0x120 0x4fc 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB1__GPIO3_9 0x120 0x4fc 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB1__NANDF_RB1 0x120 0x4fc 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB1__PATA_IORDY 0x120 0x4fc 0x000 0x1 0x0
#define MX51_PAD_NANDF_RB1__SD4_CMD 0x120 0x4fc 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB2__DISP2_WAIT 0x124 0x500 0x9a8 0x5 0x0
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x124 0x500 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB2__FEC_COL 0x124 0x500 0x94c 0x1 0x0
#define MX51_PAD_NANDF_RB2__GPIO3_10 0x124 0x500 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB2__NANDF_RB2 0x124 0x500 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP 0x124 0x500 0x000 0x7 0x0
#define MX51_PAD_NANDF_RB2__USBH3_NXT 0x124 0x500 0xa20 0x6 0x0
#define MX51_PAD_NANDF_RB3__DISP1_WAIT 0x128 0x504 0x000 0x5 0x0
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x128 0x504 0x000 0x2 0x0
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x128 0x504 0x968 0x1 0x0
#define MX51_PAD_NANDF_RB3__GPIO3_11 0x128 0x504 0x000 0x3 0x0
#define MX51_PAD_NANDF_RB3__NANDF_RB3 0x128 0x504 0x000 0x0 0x0
#define MX51_PAD_NANDF_RB3__USBH3_CLK 0x128 0x504 0x9f8 0x6 0x0
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM 0x128 0x504 0x000 0x7 0x0
#define MX51_PAD_GPIO_NAND__GPIO_NAND 0x12c 0x514 0x998 0x0 0x0
#define MX51_PAD_GPIO_NAND__PATA_INTRQ 0x12c 0x514 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS0__GPIO3_16 0x130 0x518 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS0__NANDF_CS0 0x130 0x518 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS1__GPIO3_17 0x134 0x51c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS1__NANDF_CS1 0x134 0x51c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__CSPI_SCLK 0x138 0x520 0x914 0x6 0x0
#define MX51_PAD_NANDF_CS2__FEC_TX_ER 0x138 0x520 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS2__GPIO3_18 0x138 0x520 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS2__NANDF_CS2 0x138 0x520 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS2__PATA_CS_0 0x138 0x520 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS2__SD4_CLK 0x138 0x520 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP 0x138 0x520 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS3__FEC_MDC 0x13c 0x524 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS3__GPIO3_19 0x13c 0x524 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS3__NANDF_CS3 0x13c 0x524 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS3__PATA_CS_1 0x13c 0x524 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS3__SD4_DAT0 0x13c 0x524 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM 0x13c 0x524 0x000 0x7 0x0
#define MX51_PAD_NANDF_CS4__FEC_TDATA1 0x140 0x528 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS4__GPIO3_20 0x140 0x528 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS4__NANDF_CS4 0x140 0x528 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS4__PATA_DA_0 0x140 0x528 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS4__SD4_DAT1 0x140 0x528 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS4__USBH3_STP 0x140 0x528 0xa24 0x7 0x0
#define MX51_PAD_NANDF_CS5__FEC_TDATA2 0x144 0x52c 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS5__GPIO3_21 0x144 0x52c 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS5__NANDF_CS5 0x144 0x52c 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS5__PATA_DA_1 0x144 0x52c 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS5__SD4_DAT2 0x144 0x52c 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS5__USBH3_DIR 0x144 0x52c 0xa1c 0x7 0x0
#define MX51_PAD_NANDF_CS6__CSPI_SS3 0x148 0x530 0x928 0x7 0x0
#define MX51_PAD_NANDF_CS6__FEC_TDATA3 0x148 0x530 0x000 0x2 0x0
#define MX51_PAD_NANDF_CS6__GPIO3_22 0x148 0x530 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS6__NANDF_CS6 0x148 0x530 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS6__PATA_DA_2 0x148 0x530 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS6__SD4_DAT3 0x148 0x530 0x000 0x5 0x0
#define MX51_PAD_NANDF_CS7__FEC_TX_EN 0x14c 0x534 0x000 0x1 0x0
#define MX51_PAD_NANDF_CS7__GPIO3_23 0x14c 0x534 0x000 0x3 0x0
#define MX51_PAD_NANDF_CS7__NANDF_CS7 0x14c 0x534 0x000 0x0 0x0
#define MX51_PAD_NANDF_CS7__SD3_CLK 0x14c 0x534 0x000 0x5 0x0
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 0x150 0x538 0x000 0x2 0x0
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x150 0x538 0x974 0x1 0x0
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 0x150 0x538 0x000 0x3 0x0
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT 0x150 0x538 0x938 0x0 0x0
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD 0x150 0x538 0x000 0x5 0x0
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x154 0x53c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D15__GPIO3_25 0x154 0x53c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D15__NANDF_D15 0x154 0x53c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D15__PATA_DATA15 0x154 0x53c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D15__SD3_DAT7 0x154 0x53c 0x000 0x5 0x0
#define MX51_PAD_NANDF_D14__ECSPI2_SS3 0x158 0x540 0x934 0x2 0x0
#define MX51_PAD_NANDF_D14__GPIO3_26 0x158 0x540 0x000 0x3 0x0
#define MX51_PAD_NANDF_D14__NANDF_D14 0x158 0x540 0x000 0x0 0x0
#define MX51_PAD_NANDF_D14__PATA_DATA14 0x158 0x540 0x000 0x1 0x0
#define MX51_PAD_NANDF_D14__SD3_DAT6 0x158 0x540 0x000 0x5 0x0
#define MX51_PAD_NANDF_D13__ECSPI2_SS2 0x15c 0x544 0x000 0x2 0x0
#define MX51_PAD_NANDF_D13__GPIO3_27 0x15c 0x544 0x000 0x3 0x0
#define MX51_PAD_NANDF_D13__NANDF_D13 0x15c 0x544 0x000 0x0 0x0
#define MX51_PAD_NANDF_D13__PATA_DATA13 0x15c 0x544 0x000 0x1 0x0
#define MX51_PAD_NANDF_D13__SD3_DAT5 0x15c 0x544 0x000 0x5 0x0
#define MX51_PAD_NANDF_D12__ECSPI2_SS1 0x160 0x548 0x930 0x2 0x1
#define MX51_PAD_NANDF_D12__GPIO3_28 0x160 0x548 0x000 0x3 0x0
#define MX51_PAD_NANDF_D12__NANDF_D12 0x160 0x548 0x000 0x0 0x0
#define MX51_PAD_NANDF_D12__PATA_DATA12 0x160 0x548 0x000 0x1 0x0
#define MX51_PAD_NANDF_D12__SD3_DAT4 0x160 0x548 0x000 0x5 0x0
#define MX51_PAD_NANDF_D11__FEC_RX_DV 0x164 0x54c 0x96c 0x2 0x0
#define MX51_PAD_NANDF_D11__GPIO3_29 0x164 0x54c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D11__NANDF_D11 0x164 0x54c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D11__PATA_DATA11 0x164 0x54c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D11__SD3_DATA3 0x164 0x54c 0x948 0x5 0x1
#define MX51_PAD_NANDF_D10__GPIO3_30 0x168 0x550 0x000 0x3 0x0
#define MX51_PAD_NANDF_D10__NANDF_D10 0x168 0x550 0x000 0x0 0x0
#define MX51_PAD_NANDF_D10__PATA_DATA10 0x168 0x550 0x000 0x1 0x0
#define MX51_PAD_NANDF_D10__SD3_DATA2 0x168 0x550 0x944 0x5 0x1
#define MX51_PAD_NANDF_D9__FEC_RDATA0 0x16c 0x554 0x958 0x2 0x0
#define MX51_PAD_NANDF_D9__GPIO3_31 0x16c 0x554 0x000 0x3 0x0
#define MX51_PAD_NANDF_D9__NANDF_D9 0x16c 0x554 0x000 0x0 0x0
#define MX51_PAD_NANDF_D9__PATA_DATA9 0x16c 0x554 0x000 0x1 0x0
#define MX51_PAD_NANDF_D9__SD3_DATA1 0x16c 0x554 0x940 0x5 0x1
#define MX51_PAD_NANDF_D8__FEC_TDATA0 0x170 0x558 0x000 0x2 0x0
#define MX51_PAD_NANDF_D8__GPIO4_0 0x170 0x558 0x000 0x3 0x0
#define MX51_PAD_NANDF_D8__NANDF_D8 0x170 0x558 0x000 0x0 0x0
#define MX51_PAD_NANDF_D8__PATA_DATA8 0x170 0x558 0x000 0x1 0x0
#define MX51_PAD_NANDF_D8__SD3_DATA0 0x170 0x558 0x93c 0x5 0x1
#define MX51_PAD_NANDF_D7__GPIO4_1 0x174 0x55c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D7__NANDF_D7 0x174 0x55c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D7__PATA_DATA7 0x174 0x55c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D7__USBH3_DATA0 0x174 0x55c 0x9fc 0x5 0x0
#define MX51_PAD_NANDF_D6__GPIO4_2 0x178 0x560 0x000 0x3 0x0
#define MX51_PAD_NANDF_D6__NANDF_D6 0x178 0x560 0x000 0x0 0x0
#define MX51_PAD_NANDF_D6__PATA_DATA6 0x178 0x560 0x000 0x1 0x0
#define MX51_PAD_NANDF_D6__SD4_LCTL 0x178 0x560 0x000 0x2 0x0
#define MX51_PAD_NANDF_D6__USBH3_DATA1 0x178 0x560 0xa00 0x5 0x0
#define MX51_PAD_NANDF_D5__GPIO4_3 0x17c 0x564 0x000 0x3 0x0
#define MX51_PAD_NANDF_D5__NANDF_D5 0x17c 0x564 0x000 0x0 0x0
#define MX51_PAD_NANDF_D5__PATA_DATA5 0x17c 0x564 0x000 0x1 0x0
#define MX51_PAD_NANDF_D5__SD4_WP 0x17c 0x564 0x000 0x2 0x0
#define MX51_PAD_NANDF_D5__USBH3_DATA2 0x17c 0x564 0xa04 0x5 0x0
#define MX51_PAD_NANDF_D4__GPIO4_4 0x180 0x568 0x000 0x3 0x0
#define MX51_PAD_NANDF_D4__NANDF_D4 0x180 0x568 0x000 0x0 0x0
#define MX51_PAD_NANDF_D4__PATA_DATA4 0x180 0x568 0x000 0x1 0x0
#define MX51_PAD_NANDF_D4__SD4_CD 0x180 0x568 0x000 0x2 0x0
#define MX51_PAD_NANDF_D4__USBH3_DATA3 0x180 0x568 0xa08 0x5 0x0
#define MX51_PAD_NANDF_D3__GPIO4_5 0x184 0x56c 0x000 0x3 0x0
#define MX51_PAD_NANDF_D3__NANDF_D3 0x184 0x56c 0x000 0x0 0x0
#define MX51_PAD_NANDF_D3__PATA_DATA3 0x184 0x56c 0x000 0x1 0x0
#define MX51_PAD_NANDF_D3__SD4_DAT4 0x184 0x56c 0x000 0x2 0x0
#define MX51_PAD_NANDF_D3__USBH3_DATA4 0x184 0x56c 0xa0c 0x5 0x0
#define MX51_PAD_NANDF_D2__GPIO4_6 0x188 0x570 0x000 0x3 0x0
#define MX51_PAD_NANDF_D2__NANDF_D2 0x188 0x570 0x000 0x0 0x0
#define MX51_PAD_NANDF_D2__PATA_DATA2 0x188 0x570 0x000 0x1 0x0
#define MX51_PAD_NANDF_D2__SD4_DAT5 0x188 0x570 0x000 0x2 0x0
#define MX51_PAD_NANDF_D2__USBH3_DATA5 0x188 0x570 0xa10 0x5 0x0
#define MX51_PAD_NANDF_D1__GPIO4_7 0x18c 0x574 0x000 0x3 0x0
#define MX51_PAD_NANDF_D1__NANDF_D1 0x18c 0x574 0x000 0x0 0x0
#define MX51_PAD_NANDF_D1__PATA_DATA1 0x18c 0x574 0x000 0x1 0x0
#define MX51_PAD_NANDF_D1__SD4_DAT6 0x18c 0x574 0x000 0x2 0x0
#define MX51_PAD_NANDF_D1__USBH3_DATA6 0x18c 0x574 0xa14 0x5 0x0
#define MX51_PAD_NANDF_D0__GPIO4_8 0x190 0x578 0x000 0x3 0x0
#define MX51_PAD_NANDF_D0__NANDF_D0 0x190 0x578 0x000 0x0 0x0
#define MX51_PAD_NANDF_D0__PATA_DATA0 0x190 0x578 0x000 0x1 0x0
#define MX51_PAD_NANDF_D0__SD4_DAT7 0x190 0x578 0x000 0x2 0x0
#define MX51_PAD_NANDF_D0__USBH3_DATA7 0x190 0x578 0xa18 0x5 0x0
#define MX51_PAD_CSI1_D8__CSI1_D8 0x194 0x57c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D8__GPIO3_12 0x194 0x57c 0x998 0x3 0x1
#define MX51_PAD_CSI1_D9__CSI1_D9 0x198 0x580 0x000 0x0 0x0
#define MX51_PAD_CSI1_D9__GPIO3_13 0x198 0x580 0x000 0x3 0x0
#define MX51_PAD_CSI1_D10__CSI1_D10 0x19c 0x584 0x000 0x0 0x0
#define MX51_PAD_CSI1_D11__CSI1_D11 0x1a0 0x588 0x000 0x0 0x0
#define MX51_PAD_CSI1_D12__CSI1_D12 0x1a4 0x58c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D13__CSI1_D13 0x1a8 0x590 0x000 0x0 0x0
#define MX51_PAD_CSI1_D14__CSI1_D14 0x1ac 0x594 0x000 0x0 0x0
#define MX51_PAD_CSI1_D15__CSI1_D15 0x1b0 0x598 0x000 0x0 0x0
#define MX51_PAD_CSI1_D16__CSI1_D16 0x1b4 0x59c 0x000 0x0 0x0
#define MX51_PAD_CSI1_D17__CSI1_D17 0x1b8 0x5a0 0x000 0x0 0x0
#define MX51_PAD_CSI1_D18__CSI1_D18 0x1bc 0x5a4 0x000 0x0 0x0
#define MX51_PAD_CSI1_D19__CSI1_D19 0x1c0 0x5a8 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC 0x1c4 0x5ac 0x000 0x0 0x0
#define MX51_PAD_CSI1_VSYNC__GPIO3_14 0x1c4 0x5ac 0x000 0x3 0x0
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC 0x1c8 0x5b0 0x000 0x0 0x0
#define MX51_PAD_CSI1_HSYNC__GPIO3_15 0x1c8 0x5b0 0x000 0x3 0x0
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK 0x000 0x5b4 0x000 0x0 0x0
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK 0x000 0x5b8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__CSI2_D12 0x1cc 0x5bc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D12__GPIO4_9 0x1cc 0x5bc 0x000 0x3 0x0
#define MX51_PAD_CSI2_D13__CSI2_D13 0x1d0 0x5c0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D13__GPIO4_10 0x1d0 0x5c0 0x000 0x3 0x0
#define MX51_PAD_CSI2_D14__CSI2_D14 0x1d4 0x5c4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D15__CSI2_D15 0x1d8 0x5c8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D16__CSI2_D16 0x1dc 0x5cc 0x000 0x0 0x0
#define MX51_PAD_CSI2_D17__CSI2_D17 0x1e0 0x5d0 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__CSI2_D18 0x1e4 0x5d4 0x000 0x0 0x0
#define MX51_PAD_CSI2_D18__GPIO4_11 0x1e4 0x5d4 0x000 0x3 0x0
#define MX51_PAD_CSI2_D19__CSI2_D19 0x1e8 0x5d8 0x000 0x0 0x0
#define MX51_PAD_CSI2_D19__GPIO4_12 0x1e8 0x5d8 0x000 0x3 0x0
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC 0x1ec 0x5dc 0x000 0x0 0x0
#define MX51_PAD_CSI2_VSYNC__GPIO4_13 0x1ec 0x5dc 0x000 0x3 0x0
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC 0x1f0 0x5e0 0x000 0x0 0x0
#define MX51_PAD_CSI2_HSYNC__GPIO4_14 0x1f0 0x5e0 0x000 0x3 0x0
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK 0x1f4 0x5e4 0x000 0x0 0x0
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x1f4 0x5e4 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__GPIO4_16 0x1f8 0x5e8 0x000 0x3 0x0
#define MX51_PAD_I2C1_CLK__I2C1_CLK 0x1f8 0x5e8 0x000 0x0 0x0
#define MX51_PAD_I2C1_DAT__GPIO4_17 0x1fc 0x5ec 0x000 0x3 0x0
#define MX51_PAD_I2C1_DAT__I2C1_DAT 0x1fc 0x5ec 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x200 0x5f0 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 0x200 0x5f0 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x204 0x5f4 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x204 0x5f4 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD 0x204 0x5f4 0x9f4 0x1 0x2
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x208 0x5f8 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_CK__GPIO4_20 0x208 0x5f8 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x20c 0x5fc 0x000 0x0 0x0
#define MX51_PAD_AUD3_BB_FS__GPIO4_21 0x20c 0x5fc 0x000 0x3 0x0
#define MX51_PAD_AUD3_BB_FS__UART3_TXD 0x20c 0x5fc 0x000 0x1 0x0
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x210 0x600 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MOSI__GPIO4_22 0x210 0x600 0x000 0x3 0x0
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA 0x210 0x600 0x9b4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__AUD4_RXD 0x214 0x604 0x8c4 0x1 0x1
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x214 0x604 0x000 0x0 0x0
#define MX51_PAD_CSPI1_MISO__GPIO4_23 0x214 0x604 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS0__AUD4_TXC 0x218 0x608 0x8cc 0x1 0x1
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 0x218 0x608 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS0__GPIO4_24 0x218 0x608 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SS1__AUD4_TXD 0x21c 0x60c 0x8c8 0x1 0x1
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 0x21c 0x60c 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SS1__GPIO4_25 0x21c 0x60c 0x000 0x3 0x0
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS 0x220 0x610 0x8d0 0x1 0x1
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY 0x220 0x610 0x000 0x0 0x0
#define MX51_PAD_CSPI1_RDY__GPIO4_26 0x220 0x610 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x224 0x614 0x000 0x0 0x0
#define MX51_PAD_CSPI1_SCLK__GPIO4_27 0x224 0x614 0x000 0x3 0x0
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL 0x224 0x614 0x9b0 0x1 0x1
#define MX51_PAD_UART1_RXD__GPIO4_28 0x228 0x618 0x000 0x3 0x0
#define MX51_PAD_UART1_RXD__UART1_RXD 0x228 0x618 0x9e4 0x0 0x0
#define MX51_PAD_UART1_TXD__GPIO4_29 0x22c 0x61c 0x000 0x3 0x0
#define MX51_PAD_UART1_TXD__PWM2_PWMO 0x22c 0x61c 0x000 0x1 0x0
#define MX51_PAD_UART1_TXD__UART1_TXD 0x22c 0x61c 0x000 0x0 0x0
#define MX51_PAD_UART1_RTS__GPIO4_30 0x230 0x620 0x000 0x3 0x0
#define MX51_PAD_UART1_RTS__UART1_RTS 0x230 0x620 0x9e0 0x0 0x0
#define MX51_PAD_UART1_CTS__GPIO4_31 0x234 0x624 0x000 0x3 0x0
#define MX51_PAD_UART1_CTS__UART1_CTS 0x234 0x624 0x000 0x0 0x0
#define MX51_PAD_UART2_RXD__FIRI_TXD 0x238 0x628 0x000 0x1 0x0
#define MX51_PAD_UART2_RXD__GPIO1_20 0x238 0x628 0x000 0x3 0x0
#define MX51_PAD_UART2_RXD__UART2_RXD 0x238 0x628 0x9ec 0x0 0x2
#define MX51_PAD_UART2_TXD__FIRI_RXD 0x23c 0x62c 0x000 0x1 0x0
#define MX51_PAD_UART2_TXD__GPIO1_21 0x23c 0x62c 0x000 0x3 0x0
#define MX51_PAD_UART2_TXD__UART2_TXD 0x23c 0x62c 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__CSI1_D0 0x240 0x630 0x000 0x2 0x0
#define MX51_PAD_UART3_RXD__GPIO1_22 0x240 0x630 0x000 0x3 0x0
#define MX51_PAD_UART3_RXD__UART1_DTR 0x240 0x630 0x000 0x0 0x0
#define MX51_PAD_UART3_RXD__UART3_RXD 0x240 0x630 0x9f4 0x1 0x4
#define MX51_PAD_UART3_TXD__CSI1_D1 0x244 0x634 0x000 0x2 0x0
#define MX51_PAD_UART3_TXD__GPIO1_23 0x244 0x634 0x000 0x3 0x0
#define MX51_PAD_UART3_TXD__UART1_DSR 0x244 0x634 0x000 0x0 0x0
#define MX51_PAD_UART3_TXD__UART3_TXD 0x244 0x634 0x000 0x1 0x0
#define MX51_PAD_OWIRE_LINE__GPIO1_24 0x248 0x638 0x000 0x3 0x0
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE 0x248 0x638 0x000 0x0 0x0
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT 0x248 0x638 0x000 0x6 0x0
#define MX51_PAD_KEY_ROW0__KEY_ROW0 0x24c 0x63c 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW1__KEY_ROW1 0x250 0x640 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW2__KEY_ROW2 0x254 0x644 0x000 0x0 0x0
#define MX51_PAD_KEY_ROW3__KEY_ROW3 0x258 0x648 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__KEY_COL0 0x25c 0x64c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL0__PLL1_BYP 0x25c 0x64c 0x90c 0x7 0x0
#define MX51_PAD_KEY_COL1__KEY_COL1 0x260 0x650 0x000 0x0 0x0
#define MX51_PAD_KEY_COL1__PLL2_BYP 0x260 0x650 0x910 0x7 0x0
#define MX51_PAD_KEY_COL2__KEY_COL2 0x264 0x654 0x000 0x0 0x0
#define MX51_PAD_KEY_COL2__PLL3_BYP 0x264 0x654 0x000 0x7 0x0
#define MX51_PAD_KEY_COL3__KEY_COL3 0x268 0x658 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__I2C2_SCL 0x26c 0x65c 0x9b8 0x3 0x1
#define MX51_PAD_KEY_COL4__KEY_COL4 0x26c 0x65c 0x000 0x0 0x0
#define MX51_PAD_KEY_COL4__SPDIF_OUT1 0x26c 0x65c 0x000 0x6 0x0
#define MX51_PAD_KEY_COL4__UART1_RI 0x26c 0x65c 0x000 0x1 0x0
#define MX51_PAD_KEY_COL4__UART3_RTS 0x26c 0x65c 0x9f0 0x2 0x4
#define MX51_PAD_KEY_COL5__I2C2_SDA 0x270 0x660 0x9bc 0x3 0x1
#define MX51_PAD_KEY_COL5__KEY_COL5 0x270 0x660 0x000 0x0 0x0
#define MX51_PAD_KEY_COL5__UART1_DCD 0x270 0x660 0x000 0x1 0x0
#define MX51_PAD_KEY_COL5__UART3_CTS 0x270 0x660 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__CSPI_SCLK 0x278 0x678 0x914 0x1 0x1
#define MX51_PAD_USBH1_CLK__GPIO1_25 0x278 0x678 0x000 0x2 0x0
#define MX51_PAD_USBH1_CLK__I2C2_SCL 0x278 0x678 0x9b8 0x5 0x2
#define MX51_PAD_USBH1_CLK__USBH1_CLK 0x278 0x678 0x000 0x0 0x0
#define MX51_PAD_USBH1_DIR__CSPI_MOSI 0x27c 0x67c 0x91c 0x1 0x1
#define MX51_PAD_USBH1_DIR__GPIO1_26 0x27c 0x67c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DIR__I2C2_SDA 0x27c 0x67c 0x9bc 0x5 0x2
#define MX51_PAD_USBH1_DIR__USBH1_DIR 0x27c 0x67c 0x000 0x0 0x0
#define MX51_PAD_USBH1_STP__CSPI_RDY 0x280 0x680 0x000 0x1 0x0
#define MX51_PAD_USBH1_STP__GPIO1_27 0x280 0x680 0x000 0x2 0x0
#define MX51_PAD_USBH1_STP__UART3_RXD 0x280 0x680 0x9f4 0x5 0x6
#define MX51_PAD_USBH1_STP__USBH1_STP 0x280 0x680 0x000 0x0 0x0
#define MX51_PAD_USBH1_NXT__CSPI_MISO 0x284 0x684 0x918 0x1 0x0
#define MX51_PAD_USBH1_NXT__GPIO1_28 0x284 0x684 0x000 0x2 0x0
#define MX51_PAD_USBH1_NXT__UART3_TXD 0x284 0x684 0x000 0x5 0x0
#define MX51_PAD_USBH1_NXT__USBH1_NXT 0x284 0x684 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA0__GPIO1_11 0x288 0x688 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA0__UART2_CTS 0x288 0x688 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x288 0x688 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA1__GPIO1_12 0x28c 0x68c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA1__UART2_RXD 0x28c 0x68c 0x9ec 0x1 0x4
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x28c 0x68c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA2__GPIO1_13 0x290 0x690 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA2__UART2_TXD 0x290 0x690 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x290 0x690 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA3__GPIO1_14 0x294 0x694 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA3__UART2_RTS 0x294 0x694 0x9e8 0x1 0x5
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x294 0x694 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA4__CSPI_SS0 0x298 0x698 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA4__GPIO1_15 0x298 0x698 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x298 0x698 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA5__CSPI_SS1 0x29c 0x69c 0x920 0x1 0x0
#define MX51_PAD_USBH1_DATA5__GPIO1_16 0x29c 0x69c 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x29c 0x69c 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA6__CSPI_SS3 0x2a0 0x6a0 0x928 0x1 0x1
#define MX51_PAD_USBH1_DATA6__GPIO1_17 0x2a0 0x6a0 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x2a0 0x6a0 0x000 0x0 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 0x2a4 0x6a4 0x000 0x1 0x0
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 0x2a4 0x6a4 0x934 0x5 0x1
#define MX51_PAD_USBH1_DATA7__GPIO1_18 0x2a4 0x6a4 0x000 0x2 0x0
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x2a4 0x6a4 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__DI1_PIN11 0x2a8 0x6a8 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 0x2a8 0x6a8 0x000 0x7 0x0
#define MX51_PAD_DI1_PIN11__GPIO3_0 0x2a8 0x6a8 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN12__DI1_PIN12 0x2ac 0x6ac 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN12__GPIO3_1 0x2ac 0x6ac 0x978 0x4 0x1
#define MX51_PAD_DI1_PIN13__DI1_PIN13 0x2b0 0x6b0 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN13__GPIO3_2 0x2b0 0x6b0 0x97c 0x4 0x1
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS 0x2b4 0x6b4 0x000 0x0 0x0
#define MX51_PAD_DI1_D0_CS__GPIO3_3 0x2b4 0x6b4 0x980 0x4 0x1
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS 0x2b8 0x6b8 0x000 0x0 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 0x2b8 0x6b8 0x000 0x2 0x0
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 0x2b8 0x6b8 0x000 0x3 0x0
#define MX51_PAD_DI1_D1_CS__GPIO3_4 0x2b8 0x6b8 0x984 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 0x2bc 0x6bc 0x9a4 0x2 0x1
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN 0x2bc 0x6bc 0x9c4 0x0 0x0
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 0x2bc 0x6bc 0x988 0x4 0x1
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 0x2c0 0x6c0 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO 0x2c0 0x6c0 0x9c4 0x0 0x1
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 0x2c0 0x6c0 0x98c 0x4 0x1
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 0x2c4 0x6c4 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 0x2c4 0x6c4 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK 0x2c4 0x6c4 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 0x2c4 0x6c4 0x990 0x4 0x1
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 0x2c8 0x6c8 0x000 0x2 0x0
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 0x2c8 0x6c8 0x000 0x3 0x0
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS 0x2c8 0x6c8 0x000 0x0 0x0
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 0x2c8 0x6c8 0x994 0x4 0x1
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x2cc 0x6cc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x2d0 0x6d0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x2d4 0x6d4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x2d8 0x6d8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x2dc 0x6dc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x2e0 0x6e0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC 0x2e4 0x6e4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x2e4 0x6e4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG 0x2e8 0x6e8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x2e8 0x6e8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 0x2ec 0x6ec 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x2ec 0x6ec 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 0x2f0 0x6f0 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x2f0 0x6f0 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE 0x2f4 0x6f4 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x2f4 0x6f4 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 0x2f8 0x6f8 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x2f8 0x6f8 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL 0x2fc 0x6fc 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x2fc 0x6fc 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 0x300 0x700 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x300 0x700 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 0x304 0x704 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x304 0x704 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH 0x308 0x708 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x308 0x708 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 0x30c 0x70c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x30c 0x70c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 0x310 0x710 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x310 0x710 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 0x314 0x714 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x314 0x714 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 0x314 0x714 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 0x314 0x714 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 0x318 0x718 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x318 0x718 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 0x318 0x718 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 0x318 0x718 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 0x31c 0x71c 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x31c 0x71c 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 0x31c 0x71c 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 0x31c 0x71c 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 0x320 0x720 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x320 0x720 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 0x320 0x720 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 0x320 0x720 0x000 0x4 0x0
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 0x324 0x724 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x324 0x724 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS 0x324 0x724 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 0x324 0x724 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 0x328 0x728 0x000 0x7 0x0
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x328 0x728 0x000 0x0 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS 0x328 0x728 0x000 0x6 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 0x328 0x728 0x000 0x5 0x0
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS 0x328 0x728 0x000 0x4 0x0
#define MX51_PAD_DI1_PIN3__DI1_PIN3 0x32c 0x72c 0x000 0x0 0x0
#define MX51_PAD_DI1_PIN2__DI1_PIN2 0x330 0x734 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP1_SER_CLK 0x338 0x740 0x000 0x0 0x0
#define MX51_PAD_DI_GP2__DISP2_WAIT 0x338 0x740 0x9a8 0x2 0x1
#define MX51_PAD_DI_GP3__CSI1_DATA_EN 0x33c 0x744 0x9a0 0x3 0x1
#define MX51_PAD_DI_GP3__DISP1_SER_DIO 0x33c 0x744 0x9c0 0x0 0x0
#define MX51_PAD_DI_GP3__FEC_TX_ER 0x33c 0x744 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN 0x340 0x748 0x99c 0x3 0x1
#define MX51_PAD_DI2_PIN4__DI2_PIN4 0x340 0x748 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN4__FEC_CRS 0x340 0x748 0x950 0x2 0x1
#define MX51_PAD_DI2_PIN2__DI2_PIN2 0x344 0x74c 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN2__FEC_MDC 0x344 0x74c 0x000 0x2 0x0
#define MX51_PAD_DI2_PIN3__DI2_PIN3 0x348 0x750 0x000 0x0 0x0
#define MX51_PAD_DI2_PIN3__FEC_MDIO 0x348 0x750 0x954 0x2 0x1
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x34c 0x754 0x000 0x0 0x0
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x34c 0x754 0x95c 0x2 0x1
#define MX51_PAD_DI_GP4__DI2_PIN15 0x350 0x758 0x000 0x4 0x0
#define MX51_PAD_DI_GP4__DISP1_SER_DIN 0x350 0x758 0x9c0 0x0 0x1
#define MX51_PAD_DI_GP4__DISP2_PIN1 0x350 0x758 0x000 0x3 0x0
#define MX51_PAD_DI_GP4__FEC_RDATA2 0x350 0x758 0x960 0x2 0x1
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x354 0x75c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x354 0x75c 0x964 0x2 0x1
#define MX51_PAD_DISP2_DAT0__KEY_COL6 0x354 0x75c 0x9c8 0x4 0x1
#define MX51_PAD_DISP2_DAT0__UART3_RXD 0x354 0x75c 0x9f4 0x5 0x8
#define MX51_PAD_DISP2_DAT0__USBH3_CLK 0x354 0x75c 0x9f8 0x3 0x1
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x358 0x760 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x358 0x760 0x970 0x2 0x1
#define MX51_PAD_DISP2_DAT1__KEY_COL7 0x358 0x760 0x9cc 0x4 0x1
#define MX51_PAD_DISP2_DAT1__UART3_TXD 0x358 0x760 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT1__USBH3_DIR 0x358 0x760 0xa1c 0x3 0x1
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x35c 0x764 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x360 0x768 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x364 0x76c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x368 0x770 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x36c 0x774 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x36c 0x774 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT6__GPIO1_19 0x36c 0x774 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT6__KEY_ROW4 0x36c 0x774 0x9d0 0x4 0x1
#define MX51_PAD_DISP2_DAT6__USBH3_STP 0x36c 0x774 0xa24 0x3 0x1
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x370 0x778 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x370 0x778 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT7__GPIO1_29 0x370 0x778 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT7__KEY_ROW5 0x370 0x778 0x9d4 0x4 0x1
#define MX51_PAD_DISP2_DAT7__USBH3_NXT 0x370 0x778 0xa20 0x3 0x1
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x374 0x77c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x374 0x77c 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT8__GPIO1_30 0x374 0x77c 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT8__KEY_ROW6 0x374 0x77c 0x9d8 0x4 0x1
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 0x374 0x77c 0x9fc 0x3 0x1
#define MX51_PAD_DISP2_DAT9__AUD6_RXC 0x378 0x780 0x8f4 0x4 0x1
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x378 0x780 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x378 0x780 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT9__GPIO1_31 0x378 0x780 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 0x378 0x780 0xa00 0x3 0x1
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x37c 0x784 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS 0x37c 0x784 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT10__FEC_COL 0x37c 0x784 0x94c 0x2 0x1
#define MX51_PAD_DISP2_DAT10__KEY_ROW7 0x37c 0x784 0x9dc 0x4 0x1
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 0x37c 0x784 0xa04 0x3 0x1
#define MX51_PAD_DISP2_DAT11__AUD6_TXD 0x380 0x788 0x8f0 0x4 0x1
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x380 0x788 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x380 0x788 0x968 0x2 0x1
#define MX51_PAD_DISP2_DAT11__GPIO1_10 0x380 0x788 0x000 0x7 0x0
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 0x380 0x788 0xa08 0x3 0x1
#define MX51_PAD_DISP2_DAT12__AUD6_RXD 0x384 0x78c 0x8ec 0x4 0x1
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x384 0x78c 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x384 0x78c 0x96c 0x2 0x1
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 0x384 0x78c 0xa0c 0x3 0x1
#define MX51_PAD_DISP2_DAT13__AUD6_TXC 0x388 0x790 0x8fc 0x4 0x1
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x388 0x790 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x388 0x790 0x974 0x2 0x1
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 0x388 0x790 0xa10 0x3 0x1
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS 0x38c 0x794 0x900 0x4 0x1
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x38c 0x794 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x38c 0x794 0x958 0x2 0x1
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 0x38c 0x794 0xa14 0x3 0x1
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS 0x390 0x798 0x8f8 0x4 0x1
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS 0x390 0x798 0x000 0x5 0x0
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x390 0x798 0x000 0x0 0x0
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x390 0x798 0x000 0x2 0x0
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 0x390 0x798 0xa18 0x3 0x1
#define MX51_PAD_SD1_CMD__AUD5_RXFS 0x394 0x79c 0x8e0 0x1 0x1
#define MX51_PAD_SD1_CMD__CSPI_MOSI 0x394 0x79c 0x91c 0x2 0x2
#define MX51_PAD_SD1_CMD__SD1_CMD 0x394 0x79c 0x000 0x0 0x0
#define MX51_PAD_SD1_CLK__AUD5_RXC 0x398 0x7a0 0x8dc 0x1 0x1
#define MX51_PAD_SD1_CLK__CSPI_SCLK 0x398 0x7a0 0x914 0x2 0x2
#define MX51_PAD_SD1_CLK__SD1_CLK 0x398 0x7a0 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA0__AUD5_TXD 0x39c 0x7a4 0x8d8 0x1 0x2
#define MX51_PAD_SD1_DATA0__CSPI_MISO 0x39c 0x7a4 0x918 0x2 0x1
#define MX51_PAD_SD1_DATA0__SD1_DATA0 0x39c 0x7a4 0x000 0x0 0x0
#define MX51_PAD_EIM_DA0__EIM_DA0 0x01c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA1__EIM_DA1 0x020 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA2__EIM_DA2 0x024 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA3__EIM_DA3 0x028 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA1__AUD5_RXD 0x3a0 0x7a8 0x8d4 0x1 0x2
#define MX51_PAD_SD1_DATA1__SD1_DATA1 0x3a0 0x7a8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA4__EIM_DA4 0x02c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA5__EIM_DA5 0x030 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA6__EIM_DA6 0x034 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA7__EIM_DA7 0x038 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA2__AUD5_TXC 0x3a4 0x7ac 0x8e4 0x1 0x2
#define MX51_PAD_SD1_DATA2__SD1_DATA2 0x3a4 0x7ac 0x000 0x0 0x0
#define MX51_PAD_EIM_DA10__EIM_DA10 0x044 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA11__EIM_DA11 0x048 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA8__EIM_DA8 0x03c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA9__EIM_DA9 0x040 0x000 0x000 0x0 0x0
#define MX51_PAD_SD1_DATA3__AUD5_TXFS 0x3a8 0x7b0 0x8e8 0x1 0x2
#define MX51_PAD_SD1_DATA3__CSPI_SS1 0x3a8 0x7b0 0x920 0x2 0x1
#define MX51_PAD_SD1_DATA3__SD1_DATA3 0x3a8 0x7b0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_0__CSPI_SS2 0x3ac 0x7b4 0x924 0x2 0x0
#define MX51_PAD_GPIO1_0__GPIO1_0 0x3ac 0x7b4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_0__SD1_CD 0x3ac 0x7b4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_1__CSPI_MISO 0x3b0 0x7b8 0x918 0x2 0x2
#define MX51_PAD_GPIO1_1__GPIO1_1 0x3b0 0x7b8 0x000 0x1 0x0
#define MX51_PAD_GPIO1_1__SD1_WP 0x3b0 0x7b8 0x000 0x0 0x0
#define MX51_PAD_EIM_DA12__EIM_DA12 0x04c 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA13__EIM_DA13 0x050 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA14__EIM_DA14 0x054 0x000 0x000 0x0 0x0
#define MX51_PAD_EIM_DA15__EIM_DA15 0x058 0x000 0x000 0x0 0x0
#define MX51_PAD_SD2_CMD__CSPI_MOSI 0x3b4 0x7bc 0x91c 0x2 0x3
#define MX51_PAD_SD2_CMD__I2C1_SCL 0x3b4 0x7bc 0x9b0 0x1 0x2
#define MX51_PAD_SD2_CMD__SD2_CMD 0x3b4 0x7bc 0x000 0x0 0x0
#define MX51_PAD_SD2_CLK__CSPI_SCLK 0x3b8 0x7c0 0x914 0x2 0x3
#define MX51_PAD_SD2_CLK__I2C1_SDA 0x3b8 0x7c0 0x9b4 0x1 0x2
#define MX51_PAD_SD2_CLK__SD2_CLK 0x3b8 0x7c0 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA0__CSPI_MISO 0x3bc 0x7c4 0x918 0x2 0x3
#define MX51_PAD_SD2_DATA0__SD1_DAT4 0x3bc 0x7c4 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA0__SD2_DATA0 0x3bc 0x7c4 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__SD1_DAT5 0x3c0 0x7c8 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA1__SD2_DATA1 0x3c0 0x7c8 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP 0x3c0 0x7c8 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA2__SD1_DAT6 0x3c4 0x7cc 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA2__SD2_DATA2 0x3c4 0x7cc 0x000 0x0 0x0
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM 0x3c4 0x7cc 0x000 0x2 0x0
#define MX51_PAD_SD2_DATA3__CSPI_SS2 0x3c8 0x7d0 0x924 0x2 0x1
#define MX51_PAD_SD2_DATA3__SD1_DAT7 0x3c8 0x7d0 0x000 0x1 0x0
#define MX51_PAD_SD2_DATA3__SD2_DATA3 0x3c8 0x7d0 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__CCM_OUT_2 0x3cc 0x7d4 0x000 0x5 0x0
#define MX51_PAD_GPIO1_2__GPIO1_2 0x3cc 0x7d4 0x000 0x0 0x0
#define MX51_PAD_GPIO1_2__I2C2_SCL 0x3cc 0x7d4 0x9b8 0x2 0x3
#define MX51_PAD_GPIO1_2__PLL1_BYP 0x3cc 0x7d4 0x90c 0x7 0x1
#define MX51_PAD_GPIO1_2__PWM1_PWMO 0x3cc 0x7d4 0x000 0x1 0x0
#define MX51_PAD_GPIO1_3__GPIO1_3 0x3d0 0x7d8 0x000 0x0 0x0
#define MX51_PAD_GPIO1_3__I2C2_SDA 0x3d0 0x7d8 0x9bc 0x2 0x3
#define MX51_PAD_GPIO1_3__PLL2_BYP 0x3d0 0x7d8 0x910 0x7 0x1
#define MX51_PAD_GPIO1_3__PWM2_PWMO 0x3d0 0x7d8 0x000 0x1 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ 0x3d4 0x7fc 0x000 0x0 0x0
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B 0x3d4 0x7fc 0x000 0x1 0x0
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK 0x3d8 0x804 0x908 0x4 0x1
#define MX51_PAD_GPIO1_4__EIM_RDY 0x3d8 0x804 0x938 0x3 0x1
#define MX51_PAD_GPIO1_4__GPIO1_4 0x3d8 0x804 0x000 0x0 0x0
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B 0x3d8 0x804 0x000 0x2 0x0
#define MX51_PAD_GPIO1_5__CSI2_MCLK 0x3dc 0x808 0x000 0x6 0x0
#define MX51_PAD_GPIO1_5__DISP2_PIN16 0x3dc 0x808 0x000 0x3 0x0
#define MX51_PAD_GPIO1_5__GPIO1_5 0x3dc 0x808 0x000 0x0 0x0
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B 0x3dc 0x808 0x000 0x2 0x0
#define MX51_PAD_GPIO1_6__DISP2_PIN17 0x3e0 0x80c 0x000 0x4 0x0
#define MX51_PAD_GPIO1_6__GPIO1_6 0x3e0 0x80c 0x000 0x0 0x0
#define MX51_PAD_GPIO1_6__REF_EN_B 0x3e0 0x80c 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__CCM_OUT_0 0x3e4 0x810 0x000 0x3 0x0
#define MX51_PAD_GPIO1_7__GPIO1_7 0x3e4 0x810 0x000 0x0 0x0
#define MX51_PAD_GPIO1_7__SD2_WP 0x3e4 0x810 0x000 0x6 0x0
#define MX51_PAD_GPIO1_7__SPDIF_OUT1 0x3e4 0x810 0x000 0x2 0x0
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN 0x3e8 0x814 0x99c 0x2 0x2
#define MX51_PAD_GPIO1_8__GPIO1_8 0x3e8 0x814 0x000 0x0 0x0
#define MX51_PAD_GPIO1_8__SD2_CD 0x3e8 0x814 0x000 0x6 0x0
#define MX51_PAD_GPIO1_8__USBH3_PWR 0x3e8 0x814 0x000 0x1 0x0
#define MX51_PAD_GPIO1_9__CCM_OUT_1 0x3ec 0x818 0x000 0x3 0x0
#define MX51_PAD_GPIO1_9__DISP2_D1_CS 0x3ec 0x818 0x000 0x2 0x0
#define MX51_PAD_GPIO1_9__DISP2_SER_CS 0x3ec 0x818 0x000 0x7 0x0
#define MX51_PAD_GPIO1_9__GPIO1_9 0x3ec 0x818 0x000 0x0 0x0
#define MX51_PAD_GPIO1_9__SD2_LCTL 0x3ec 0x818 0x000 0x6 0x0
#define MX51_PAD_GPIO1_9__USBH3_OC 0x3ec 0x818 0x000 0x1 0x0
#endif /* __DTS_IMX51_PINFUNC_H */

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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
/*
* The decompressor and also some bootloaders rely on a
* pre-existing /chosen node to be available to insert the
* command line and merge other ATAGS info.
*/
chosen {};
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &i2c1;
i2c1 = &i2c2;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &cspi;
};
tzic: tz-interrupt-controller@e0000000 {
compatible = "fsl,imx51-tzic", "fsl,tzic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xe0000000 0x4000>;
};
clocks {
ckil {
compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
osc {
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0>;
clock-latency = <62500>;
clocks = <&clks IMX5_CLK_CPU_PODF>;
clock-names = "cpu";
operating-points = <
166000 1000000
600000 1050000
800000 1100000
>;
voltage-tolerance = <5>;
};
};
pmu: pmu {
compatible = "arm,cortex-a8-pmu";
interrupt-parent = <&tzic>;
interrupts = <77>;
};
usbphy0: usbphy0 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
clock-names = "main_clk";
#phy-cells = <0>;
};
capture-subsystem {
compatible = "fsl,imx-capture-subsystem";
ports = <&ipu_csi0>, <&ipu_csi1>;
};
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>, <&ipu_di1>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&tzic>;
ranges;
iram: sram@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 0x20000>;
};
gpu: gpu@30000000 {
compatible = "amd,imageon-200.1", "amd,imageon";
reg = <0x30000000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <12>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
clock-names = "core_clk", "mem_iface_clk";
};
ipu: ipu@40000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks IMX5_CLK_IPU_GATE>,
<&clks IMX5_CLK_IPU_DI0_GATE>,
<&clks IMX5_CLK_IPU_DI1_GATE>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
ipu_csi0: port@0 {
reg = <0>;
};
ipu_csi1: port@1 {
reg = <1>;
};
ipu_di0: port@2 {
reg = <2>;
ipu_di0_disp1: endpoint {
};
};
ipu_di1: port@3 {
reg = <3>;
ipu_di1_disp2: endpoint {
};
};
};
bus@70000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x10000000>;
ranges;
spba@70000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x70000000 0x40000>;
ranges;
esdhc1: mmc@70004000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70004000 0x4000>;
interrupts = <1>;
clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC1_PER_GATE>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
esdhc2: mmc@70008000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70008000 0x4000>;
interrupts = <2>;
clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC2_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
uart3: serial@7000c000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x7000c000 0x4000>;
interrupts = <33>;
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi1: spi@70010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
reg = <0x70010000 0x4000>;
interrupts = <36>;
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi2: ssi@70014000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x70014000 0x4000>;
interrupts = <30>;
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
<&clks IMX5_CLK_SSI2_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
esdhc3: mmc@70020000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70020000 0x4000>;
interrupts = <3>;
clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC3_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
esdhc4: mmc@70024000 {
compatible = "fsl,imx51-esdhc";
reg = <0x70024000 0x4000>;
interrupts = <4>;
clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
<&clks IMX5_CLK_DUMMY>,
<&clks IMX5_CLK_ESDHC4_PER_GATE>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
};
aipstz1: bridge@73f00000 {
compatible = "fsl,imx51-aipstz";
reg = <0x73f00000 0x60>;
};
usbotg: usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
};
usbh1: usb@73f80200 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
usbh2: usb@73f80400 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
usbh3: usb@73f80600 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};
usbmisc: usbmisc@73f80800 {
#index-cells = <1>;
compatible = "fsl,imx51-usbmisc";
reg = <0x73f80800 0x200>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
};
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@73f88000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f88000 0x4000>;
interrupts = <52 53>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@73f8c000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f8c000 0x4000>;
interrupts = <54 55>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@73f90000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f90000 0x4000>;
interrupts = <56 57>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
kpp: kpp@73f94000 {
compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
reg = <0x73f94000 0x4000>;
interrupts = <60>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
wdog1: watchdog@73f98000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
clocks = <&clks IMX5_CLK_DUMMY>;
};
wdog2: watchdog@73f9c000 {
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f9c000 0x4000>;
interrupts = <59>;
clocks = <&clks IMX5_CLK_DUMMY>;
status = "disabled";
};
gpt: timer@73fa0000 {
compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
reg = <0x73fa0000 0x4000>;
interrupts = <39>;
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
<&clks IMX5_CLK_GPT_HF_GATE>;
clock-names = "ipg", "per";
};
iomuxc: iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc";
reg = <0x73fa8000 0x4000>;
};
pwm1: pwm@73fb4000 {
#pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb4000 0x4000>;
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
<&clks IMX5_CLK_PWM1_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <61>;
};
pwm2: pwm@73fb8000 {
#pwm-cells = <3>;
compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
reg = <0x73fb8000 0x4000>;
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
<&clks IMX5_CLK_PWM2_HF_GATE>;
clock-names = "ipg", "per";
interrupts = <94>;
};
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
interrupts = <31>;
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@73fc0000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fc0000 0x4000>;
interrupts = <32>;
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
src: reset-controller@73fd0000 {
compatible = "fsl,imx51-src";
reg = <0x73fd0000 0x4000>;
interrupts = <75>;
#reset-cells = <1>;
};
clks: ccm@73fd4000{
compatible = "fsl,imx51-ccm";
reg = <0x73fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
#clock-cells = <1>;
};
};
bus@80000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x80000000 0x10000000>;
ranges;
aipstz2: bridge@83f00000 {
compatible = "fsl,imx51-aipstz";
reg = <0x83f00000 0x60>;
};
iim: efuse@83f98000 {
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
reg = <0x83f98000 0x4000>;
interrupts = <69>;
clocks = <&clks IMX5_CLK_IIM_GATE>;
};
tigerp: tigerp@83fa0000 {
compatible = "fsl,imx51-tigerp";
reg = <0x83fa0000 0x28>;
};
owire: owire@83fa4000 {
compatible = "fsl,imx51-owire", "fsl,imx21-owire";
reg = <0x83fa4000 0x4000>;
interrupts = <88>;
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
status = "disabled";
};
ecspi2: spi@83fac000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-ecspi";
reg = <0x83fac000 0x4000>;
interrupts = <37>;
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
sdma: sdma@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_AHB>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
cspi: spi@83fc0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
reg = <0x83fc0000 0x4000>;
interrupts = <38>;
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
<&clks IMX5_CLK_CSPI_IPG_GATE>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c2: i2c@83fc4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc4000 0x4000>;
interrupts = <63>;
clocks = <&clks IMX5_CLK_I2C2_GATE>;
status = "disabled";
};
i2c1: i2c@83fc8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
reg = <0x83fc8000 0x4000>;
interrupts = <62>;
clocks = <&clks IMX5_CLK_I2C1_GATE>;
status = "disabled";
};
ssi1: ssi@83fcc000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
<&clks IMX5_CLK_SSI1_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
audmux: audmux@83fd0000 {
compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
reg = <0x83fd0000 0x4000>;
clocks = <&clks IMX5_CLK_DUMMY>;
clock-names = "audmux";
status = "disabled";
};
m4if: m4if@83fd8000 {
compatible = "fsl,imx51-m4if";
reg = <0x83fd8000 0x1000>;
};
weim: weim@83fda000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx51-weim";
reg = <0x83fda000 0x1000>;
clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
ranges = <
0 0 0xb0000000 0x08000000
1 0 0xb8000000 0x08000000
2 0 0xc0000000 0x08000000
3 0 0xc8000000 0x04000000
4 0 0xcc000000 0x02000000
5 0 0xce000000 0x02000000
>;
status = "disabled";
};
nfc: nand@83fdb000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx51-nand";
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
interrupts = <8>;
clocks = <&clks IMX5_CLK_NFC_GATE>;
status = "disabled";
};
pata: pata@83fe0000 {
compatible = "fsl,imx51-pata", "fsl,imx27-pata";
reg = <0x83fe0000 0x4000>;
interrupts = <70>;
clocks = <&clks IMX5_CLK_PATA_GATE>;
status = "disabled";
};
ssi3: ssi@83fe8000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
reg = <0x83fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
<&clks IMX5_CLK_SSI3_ROOT_GATE>;
clock-names = "ipg", "baud";
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
status = "disabled";
};
fec: ethernet@83fec000 {
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
reg = <0x83fec000 0x4000>;
interrupts = <87>;
clocks = <&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>,
<&clks IMX5_CLK_FEC_GATE>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
vpu: vpu@83ff4000 {
compatible = "fsl,imx51-vpu", "cnm,codahx4";
reg = <0x83ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
<&clks IMX5_CLK_VPU_GATE>;
clock-names = "per", "ahb";
resets = <&src 1>;
iram = <&iram>;
};
sahara: crypto@83ff8000 {
compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
reg = <0x83ff8000 0x4000>;
interrupts = <19 20>;
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
clock-names = "ipg", "ahb";
};
};
};
};

387
arch/arm/dts/imx53-qsb-common.dtsi Normal file
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@ -0,0 +1,387 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
#include "imx53.dtsi"
/ {
chosen {
stdout-path = &uart1;
};
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
};
display0: disp0 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
volume-up {
label = "Volume Up";
gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
wakeup-source;
};
volume-down {
label = "Volume Down";
gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio7_7>;
user {
label = "Heartbeat";
gpios = <&gpio7 7 0>;
linux,default-trigger = "heartbeat";
};
};
panel {
compatible = "sii,43wvf1g";
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p2v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usb_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 0>;
enable-active-high;
};
};
sound {
compatible = "fsl,imx53-qsb-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-qsb-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&cpu0 {
/* CPU rated to 1GHz, not 1.2GHz as per the default settings */
operating-points = <
/* kHz uV */
166666 850000
400000 900000
800000 1050000
1000000 1200000
>;
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&ssi2 {
status = "okay";
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3>;
cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
bus-width = <8>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-qsb {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_8__GPIO1_8 0x80000000
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
led_pin_gpio7_7: led_gpio7_7 {
fsl,pins = <
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_codec: codecgrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
MX53_PAD_EIM_DA13__GPIO3_13 0xe4
>;
};
pinctrl_esdhc3: esdhc3grp {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
/* open drain */
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_ipu_disp0: ipudisp0grp {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
pinctrl_vga_sync: vgasync-grp {
fsl,pins = <
/* VGA_HSYNC, VSYNC with max drive strength */
MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
>;
};
};
};
&tve {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync>;
ddc-i2c-bus = <&i2c2>;
fsl,tve-mode = "vga";
fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */
fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
accelerometer: mma8450@1c {
compatible = "fsl,mma8450";
reg = <0x1c>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sata {
status = "okay";
};
&vpu {
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0+
//
// Copyright 2011 Freescale Semiconductor, Inc.
// Copyright 2011 Linaro Ltd.
/dts-v1/;
#include "imx53-qsb-common.dtsi"
/ {
model = "Freescale i.MX53 Quick Start Board";
compatible = "fsl,imx53-qsb", "fsl,imx53";
};
&i2c1 {
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
interrupt-parent = <&gpio7>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* low-level active IRQ at GPIO7_11 */
regulators {
buck1_reg: buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2075000>;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
buck4_reg: buck4 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1725000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo7_reg: ldo7 {
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <2750000>;
};
ldo8_reg: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo9_reg: ldo9 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
ldo10_reg: ldo10 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
regulator-always-on;
};
};
};
};
&tve {
dac-supply = <&ldo7_reg>;
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
&fec1 {
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
u-boot,dm-spl;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
tamper {
label = "tamper";
linux,code = <BTN_4>;
interrupt-parent = <&gsc>;
interrupts = <5>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
};
&A53_0 {
cpu-supply = <&buck3_reg>;
};
&A53_1 {
cpu-supply = <&buck3_reg>;
};
&A53_2 {
cpu-supply = <&buck3_reg>;
};
&A53_3 {
cpu-supply = <&buck3_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@16 {
gw,mode = <4>;
reg = <0x16>;
label = "fan_tach";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vdd_vin";
gw,voltage-divider-ohms = <22100 1000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_adc1";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_adc2";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_dram";
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_1p2";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_1p0";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_2p5";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@98 {
gw,mode = <2>;
reg = <0x98>;
label = "vdd_0p95";
};
channel@9a {
gw,mode = <2>;
reg = <0x9a>;
label = "vdd_1p8";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
fan-controller@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "gw,gsc-fan";
reg = <0x0a>;
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
pmic@69 {
compatible = "mps,mp5416";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x69>;
regulators {
buck1 {
regulator-name = "vdd_0p95";
regulator-min-microvolt = <805000>;
regulator-max-microvolt = <1000000>;
regulator-max-microamp = <2500000>;
regulator-boot-on;
};
buck2 {
regulator-name = "vdd_soc";
regulator-min-microvolt = <805000>;
regulator-max-microvolt = <900000>;
regulator-max-microamp = <1000000>;
regulator-boot-on;
};
buck3_reg: buck3 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <805000>;
regulator-max-microvolt = <1000000>;
regulator-max-microamp = <2200000>;
regulator-boot-on;
};
buck4 {
regulator-name = "vdd_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microamp = <500000>;
regulator-boot-on;
};
ldo1 {
regulator-name = "nvcc_snvs_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microamp = <300000>;
regulator-boot-on;
};
ldo2 {
regulator-name = "vdd_snvs_0p8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
};
ldo3 {
regulator-name = "vdd_0p95";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
};
ldo4 {
regulator-name = "vdd_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-venice-gw700x-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw71xx.dtsi"
/ {
model = "Gateworks Venice GW71xx-0x i.MX8MM Development Kit";
compatible = "gw,imx8mm-gw71xx-0x", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-venice-gw700x-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw72xx.dtsi"
/ {
model = "Gateworks Venice GW72xx-0x i.MX8MM Development Kit";
compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg2_vbus: regulator-usb-otg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* off-board header */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
/* RS232 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-venice-gw700x-u-boot.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
#include "imx8mm-venice-gw700x.dtsi"
#include "imx8mm-venice-gw73xx.dtsi"
/ {
model = "Gateworks Venice GW73xx-0x i.MX8MM Development Kit";
compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2020 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg2_vbus: regulator-usb-otg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_wifi_en: regulator-wifi-en {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wl>;
compatible = "regulator-fixed";
regulator-name = "wl";
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
/* off-board header */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
/* off-board header */
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* bluetooth HCI */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
bluetooth {
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
/* RS232 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
/* SDIO WiFi */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
non-removable;
vmmc-supply = <&reg_wifi_en>;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159
>;
};
pinctrl_bten: btengrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
>;
};
pinctrl_reg_wl: regwlgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
>;
};
pinctrl_reg_usb1_en: regusb1grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x140
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
};

103
arch/arm/dts/imx8mm-venice-u-boot.dtsi Normal file
View file

@ -0,0 +1,103 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};

152
arch/arm/dts/imx8mm-venice.dts Normal file
View file

@ -0,0 +1,152 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mm.dtsi"
/ {
model = "Gateworks Venice i.MX8MM board";
compatible = "gw,imx8mm-venice", "fsl,imx8mm";
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
pagesize = <32>;
};
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

2
arch/arm/dts/imx8mp-evk-u-boot.dtsi
View file

@ -142,4 +142,6 @@
&fec {
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-reset-duration = <15>;
phy-reset-post-delay = <100>;
};

4
arch/arm/dts/imx8mq-evk-u-boot.dtsi
View file

@ -1,9 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
&reg_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
&usdhc1 {
mmc-hs400-1_8v;
};

2
arch/arm/include/asm/arch-imx8/imx-regs.h
View file

@ -26,6 +26,8 @@
#define LPI2C4_BASE_ADDR 0x5A830000
#define LPI2C5_BASE_ADDR 0x5A840000
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_IMX8QXP
#define LVDS0_PHYCTRL_BASE 0x56221000
#define LVDS1_PHYCTRL_BASE 0x56241000

1
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -63,6 +63,7 @@
#define DDR_CSD1_BASE_ADDR 0x40000000
#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
#define FEC_QUIRK_ENET_MAC
#if !defined(__ASSEMBLY__)
#include <asm/types.h>

4
arch/arm/mach-imx/Makefile
View file

@ -202,10 +202,10 @@ append = cat $(filter-out $< $(PHONY), $^) >> $@
quiet_cmd_pad_cat = CAT $@
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
u-boot-with-spl.imx: SPL u-boot.uim FORCE
u-boot-with-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(call if_changed,pad_cat)
u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx u-boot.uim FORCE
u-boot-with-nand-spl.imx: spl/u-boot-nand-spl.imx $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
$(call if_changed,pad_cat)
quiet_cmd_u-boot-nand-spl_imx = GEN $@

7
arch/arm/mach-imx/imx8m/Kconfig
View file

@ -43,6 +43,12 @@ config TARGET_IMX8MM_EVK
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
@ -95,6 +101,7 @@ source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/technexion/pico-imx8mq/Kconfig"
source "board/toradex/verdin-imx8mm/Kconfig"

19
arch/arm/mach-imx/imx8m/soc.c
View file

@ -154,6 +154,17 @@ static struct mm_region imx8m_mem_map[] = {
struct mm_region *mem_map = imx8m_mem_map;
static unsigned int imx8m_find_dram_entry_in_mem_map(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
}
void enable_caches(void)
{
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
@ -167,10 +178,11 @@ void enable_caches(void)
* please make sure that entry initial value matches
* imx8m_mem_map for DRAM1
*/
int entry = 5;
int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
while (i < CONFIG_NR_DRAM_BANKS && entry < 8) {
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
@ -198,6 +210,7 @@ __weak int board_phys_sdram_size(phys_size_t *size)
int dram_init(void)
{
unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
@ -212,7 +225,7 @@ int dram_init(void)
gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
imx8m_mem_map[5].size = sdram_size;
imx8m_mem_map[entry].size = sdram_size;
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;

37
arch/arm/mach-imx/mx6/soc.c
View file

@ -7,6 +7,7 @@
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <linux/delay.h>
#include <linux/errno.h>
@ -696,11 +697,47 @@ void imx_setup_hdmi(void)
#endif
#ifdef CONFIG_ARCH_MISC_INIT
/*
* UNIQUE_ID describes a unique ID based on silicon wafer
* and die X/Y position
*
* UNIQUE_ID offset 0x410
* 31:0 fuse 0
* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
*
* UNIQUE_ID offset 0x420
* 31:24 fuse 1
* The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
* 23:16 fuse 1
* The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique ID
* 15:11 fuse 1
* The wafer number of the wafer on which the device was fabricated/SJC
* CHALLENGE/ Unique ID
* 10:0 fuse 1
* FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
*/
static void setup_serial_number(void)
{
char serial_string[17];
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
if (env_get("serial#"))
return;
snprintf(serial_string, sizeof(serial_string), "%08x%08x",
fuse->uid_low, fuse->uid_high);
env_set("serial#", serial_string);
}
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
setup_serial_number();
return 0;
}
#endif

4
board/beacon/imx8mn/Kconfig
View file

@ -13,6 +13,10 @@ config IMX8MN_FORCE_NOM_SOC
bool "Force to use nominal mode for SOC and ARM"
default n
config IMX8MN_BEACON_2GB_LPDDR
bool "Enable 2GB LPDDR"
default n
source "board/freescale/common/Kconfig"
endif

1
board/beacon/imx8mn/MAINTAINERS
View file

@ -4,3 +4,4 @@ S: Maintained
F: board/beacon/imx8mn/
F: include/configs/imx8mn_beacon.h
F: configs/imx8mn_beacon_defconfig
F: configs/imx8mn_beacon_2g_defconfig

7
board/beacon/imx8mn/Makefile
View file

@ -8,6 +8,9 @@ obj-y += imx8mn_beacon.o
obj-y += ../../freescale/common/
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR
obj-y += lpddr4_2g_timing.o
else
obj-y += lpddr4_timing.o
endif
endif

1440
board/beacon/imx8mn/lpddr4_2g_timing.c Normal file
View file

File diff suppressed because it is too large Load diff

2
board/freescale/mx23evk/MAINTAINERS
View file

@ -1,6 +1,8 @@
MX23EVK BOARD
M: Fabio Estevam <festevam@gmail.com>
M: Otavio Salvador <otavio@ossystems.com.br>
S: Maintained
F: board/freescale/mx23evk/
F: arch/arm/dts/imx23-evk.dts
F: include/configs/mx23evk.h
F: configs/mx23evk_defconfig

23
board/freescale/mx23evk/mx23evk.c
View file

@ -54,26 +54,3 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_CMD_MMC
static int mx23evk_mmc_wp(int id)
{
if (id != 0) {
printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
return 1;
}
return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30);
}
int board_mmc_init(struct bd_info *bis)
{
/* Configure WP as input */
gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30);
/* Configure MMC0 Power Enable */
gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL);
}
#endif

1
board/freescale/mx51evk/MAINTAINERS
View file

@ -1,4 +1,5 @@
MX51EVK BOARD
M: Fabio Estevam <festevam@gmail.com>
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/freescale/mx51evk/

186
board/freescale/mx51evk/mx51evk.c
View file

@ -27,13 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC2_BASE_ADDR},
};
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@ -64,34 +57,6 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
MX51_PAD_NANDF_CS3__FEC_MDC,
NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
MX51_PAD_NANDF_D9__FEC_RDATA0,
MX51_PAD_NANDF_CS6__FEC_TDATA3,
MX51_PAD_NANDF_CS5__FEC_TDATA2,
MX51_PAD_NANDF_CS4__FEC_TDATA1,
MX51_PAD_NANDF_D8__FEC_TDATA0,
MX51_PAD_NANDF_CS7__FEC_TX_EN,
MX51_PAD_NANDF_CS2__FEC_TX_ER,
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
MX51_PAD_EIM_CS5__FEC_CRS,
MX51_PAD_EIM_CS4__FEC_RX_ER,
NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_MXC_SPI
static void setup_iomux_spi(void)
{
@ -112,64 +77,6 @@ static void setup_iomux_spi(void)
}
#endif
#ifdef CONFIG_USB_EHCI_MX5
#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
static void setup_usb_h1(void)
{
static const iomux_v3_cfg_t usb_h1_pads[] = {
MX51_PAD_USBH1_CLK__USBH1_CLK,
MX51_PAD_USBH1_DIR__USBH1_DIR,
MX51_PAD_USBH1_STP__USBH1_STP,
MX51_PAD_USBH1_NXT__USBH1_NXT,
MX51_PAD_USBH1_DATA0__USBH1_DATA0,
MX51_PAD_USBH1_DATA1__USBH1_DATA1,
MX51_PAD_USBH1_DATA2__USBH1_DATA2,
MX51_PAD_USBH1_DATA3__USBH1_DATA3,
MX51_PAD_USBH1_DATA4__USBH1_DATA4,
MX51_PAD_USBH1_DATA5__USBH1_DATA5,
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
MX51_PAD_EIM_D17__GPIO2_1,
MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
};
imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
}
int board_ehci_hcd_init(int port)
{
/* Set USBH1_STP to GPIO and toggle it */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
MX51_USBH_PAD_CTRL));
gpio_direction_output(MX51EVK_USBH1_STP, 0);
gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
mdelay(10);
gpio_set_value(MX51EVK_USBH1_STP, 1);
/* Set back USBH1_STP to be function */
imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
/* De-assert USB PHY RESETB */
gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
/* Drive USB_CLK_EN_B line low */
gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
/* Reset USB hub */
gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
mdelay(2);
gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
return 0;
}
#endif
static void power_init(void)
{
unsigned int val;
@ -258,6 +165,7 @@ static void power_init(void)
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
NO_PAD_CTRL));
gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14");
gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
udelay(500);
@ -265,101 +173,9 @@ static void power_init(void)
gpio_set_value(IMX_GPIO_NR(2, 14), 1);
}
#ifdef CONFIG_FSL_ESDHC_IMX
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 0));
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
NO_PAD_CTRL));
gpio_direction_input(IMX_GPIO_NR(1, 6));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
else
ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
};
static const iomux_v3_cfg_t sd2_pads[] = {
NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
};
u32 index;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
index++) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(sd1_pads,
ARRAY_SIZE(sd1_pads));
break;
case 1:
imx_iomux_v3_setup_multiple_pads(sd2_pads,
ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
#ifdef CONFIG_USB_EHCI_MX5
setup_usb_h1();
#endif
setup_iomux_lcd();
return 0;

1
board/freescale/mx53loco/MAINTAINERS
View file

@ -1,4 +1,5 @@
MX53LOCO BOARD
M: Fabio Estevam <festevam@gmail.com>
M: Jason Liu <jason.hui.liu@nxp.com>
S: Maintained
F: board/freescale/mx53loco/

124
board/freescale/mx53loco/mx53loco.c
View file

@ -18,10 +18,8 @@
#include <env.h>
#include <linux/errno.h>
#include <asm/mach-imx/mx5_video.h>
#include <netdev.h>
#include <i2c.h>
#include <input.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <asm/gpio.h>
#include <power/pmic.h>
@ -62,127 +60,6 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
/* request VBUS power enable pin, GPIO7_8 */
imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
return 0;
}
#endif
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
PAD_CTL_HYS | PAD_CTL_PKE),
NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
PAD_CTL_HYS | PAD_CTL_PKE),
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},
{MMC_SDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret;
imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
gpio_direction_input(IMX_GPIO_NR(3, 11));
imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
gpio_direction_input(IMX_GPIO_NR(3, 13));
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
else
ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
return ret;
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(struct bd_info *bis)
{
static const iomux_v3_cfg_t sd1_pads[] = {
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
MX53_PAD_EIM_DA13__GPIO3_13,
};
static const iomux_v3_cfg_t sd2_pads[] = {
NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
MX53_PAD_EIM_DA11__GPIO3_11,
};
u32 index;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
imx_iomux_v3_setup_multiple_pads(sd1_pads,
ARRAY_SIZE(sd1_pads));
break;
case 1:
imx_iomux_v3_setup_multiple_pads(sd2_pads,
ARRAY_SIZE(sd2_pads));
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return 0;
}
#endif
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
@ -327,7 +204,6 @@ static void clock_1GHz(void)
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
setup_iomux_lcd();
return 0;

12
board/gateworks/venice/Kconfig Normal file
View file

@ -0,0 +1,12 @@
if TARGET_IMX8MM_VENICE
config SYS_BOARD
default "venice"
config SYS_VENDOR
default "gateworks"
config SYS_CONFIG_NAME
default "imx8mm_venice"
endif

7
board/gateworks/venice/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
i.MX8MM Venice
M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
F: arch/arm/dts/imx8mm-venice*
F: board/gateworks/venice/
F: include/configs/venice.h
F: configs/imx8mm_venice_defconfig

12
board/gateworks/venice/Makefile Normal file
View file

@ -0,0 +1,12 @@
#
# Copyright 2021 Gateworks Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mm_venice.o gsc.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

34
board/gateworks/venice/README Normal file
View file

@ -0,0 +1,34 @@
U-Boot for the Gateworks i.MX8M Mini Venice Development Kit boards
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get ddr firmware
- Build U-Boot
- Flash to eMMC
- Boot
Get and Build the ARM Trusted firmware
======================================
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ git checkout imx_5.4.47_2.2.0
$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- bl31
$ cp build/imx8mm/release/bl31.bin .
Get the DDR Firmware
====================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9.bin
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
Build U-Boot
============
$ make imx8mm_venice_defconfig
$ make flash.bin CROSS_COMPILE=aarch64-linux-gnu- ATF_LOAD_ADDR=0x920000
Update eMMC
===========
=> tftpboot $loadaddr flash.bin
=> setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200
=> mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt

687
board/gateworks/venice/gsc.c Normal file
View file

@ -0,0 +1,687 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include <common.h>
#include <command.h>
#include <hang.h>
#include <hexdump.h>
#include <i2c.h>
#include <linux/delay.h>
#include <dm/uclass.h>
#include "gsc.h"
DECLARE_GLOBAL_DATA_PTR;
struct venice_board_info som_info;
struct venice_board_info base_info;
char venice_model[32];
/* return a mac address from EEPROM info */
int gsc_getmac(int index, uint8_t *address)
{
int i, j;
u32 maclow, machigh;
u64 mac;
j = 0;
if (som_info.macno) {
maclow = som_info.mac[5];
maclow |= som_info.mac[4] << 8;
maclow |= som_info.mac[3] << 16;
maclow |= som_info.mac[2] << 24;
machigh = som_info.mac[1];
machigh |= som_info.mac[0] << 8;
mac = machigh;
mac <<= 32;
mac |= maclow;
for (i = 0; i < som_info.macno; i++, j++) {
if (index == j)
goto out;
}
}
maclow = base_info.mac[5];
maclow |= base_info.mac[4] << 8;
maclow |= base_info.mac[3] << 16;
maclow |= base_info.mac[2] << 24;
machigh = base_info.mac[1];
machigh |= base_info.mac[0] << 8;
mac = machigh;
mac <<= 32;
mac |= maclow;
for (i = 0; i < base_info.macno; i++, j++) {
if (index == j)
goto out;
}
return -EINVAL;
out:
mac += i;
address[0] = (mac >> 40) & 0xff;
address[1] = (mac >> 32) & 0xff;
address[2] = (mac >> 24) & 0xff;
address[3] = (mac >> 16) & 0xff;
address[4] = (mac >> 8) & 0xff;
address[5] = (mac >> 0) & 0xff;
return 0;
}
/* System Controller registers */
enum {
GSC_SC_CTRL0 = 0,
GSC_SC_CTRL1 = 1,
GSC_SC_STATUS = 10,
GSC_SC_FWCRC = 12,
GSC_SC_FWVER = 14,
GSC_SC_WP = 15,
GSC_SC_RST_CAUSE = 16,
GSC_SC_THERM_PROTECT = 19,
};
/* System Controller Control1 bits */
enum {
GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */
GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */
GSC_SC_CTRL1_BOOT_CHK = 6, /* 1 = enable alt boot check */
GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */
};
/* System Controller Interrupt bits */
enum {
GSC_SC_IRQ_PB = 0, /* Pushbutton switch */
GSC_SC_IRQ_SECURE = 1, /* Secure Key erase operation complete */
GSC_SC_IRQ_EEPROM_WP = 2, /* EEPROM write violation */
GSC_SC_IRQ_GPIO = 4, /* GPIO change */
GSC_SC_IRQ_TAMPER = 5, /* Tamper detect */
GSC_SC_IRQ_WATCHDOG = 6, /* Watchdog trip */
GSC_SC_IRQ_PBLONG = 7, /* Pushbutton long hold */
};
/* System Controller WP bits */
enum {
GSC_SC_WP_ALL = 0, /* Write Protect All EEPROM regions */
GSC_SC_WP_BOARDINFO = 1, /* Write Protect Board Info region */
};
/* System Controller Reset Cause */
enum {
GSC_SC_RST_CAUSE_VIN = 0,
GSC_SC_RST_CAUSE_PB = 1,
GSC_SC_RST_CAUSE_WDT = 2,
GSC_SC_RST_CAUSE_CPU = 3,
GSC_SC_RST_CAUSE_TEMP_LOCAL = 4,
GSC_SC_RST_CAUSE_TEMP_REMOTE = 5,
GSC_SC_RST_CAUSE_SLEEP = 6,
GSC_SC_RST_CAUSE_BOOT_WDT = 7,
GSC_SC_RST_CAUSE_BOOT_WDT_MAN = 8,
GSC_SC_RST_CAUSE_SOFT_PWR = 9,
GSC_SC_RST_CAUSE_MAX = 10,
};
static struct udevice *gsc_get_dev(int busno, int slave)
{
struct udevice *dev;
int ret;
#if (IS_ENABLED(CONFIG_SPL_BUILD))
ret = i2c_get_chip_for_busnum(busno + 1, slave, 1, &dev);
if (ret)
return NULL;
#else
struct udevice *bus;
busno--;
ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus);
if (ret) {
printf("i2c%d: no bus %d\n", busno + 1, ret);
return NULL;
}
ret = i2c_get_chip(bus, slave, 1, &dev);
if (ret) {
printf("i2c%d@0x%02x: no chip %d\n", busno + 1, slave, ret);
return NULL;
}
#endif
return dev;
}
static int gsc_read_eeprom(int bus, int slave, int alen, struct venice_board_info *info)
{
int i;
int chksum;
unsigned char *buf = (unsigned char *)info;
struct udevice *dev;
int ret;
/* probe device */
dev = gsc_get_dev(bus, slave);
if (!dev) {
if (slave == GSC_EEPROM_ADDR)
puts("ERROR: Failed to probe EEPROM\n");
return -ENODEV;
}
/* read eeprom config section */
memset(info, 0, sizeof(*info));
ret = i2c_set_chip_offset_len(dev, alen);
if (ret) {
puts("EEPROM: Failed to set alen\n");
return ret;
}
ret = dm_i2c_read(dev, 0x00, buf, sizeof(*info));
if (ret) {
if (slave == GSC_EEPROM_ADDR)
printf("EEPROM: Failed to read EEPROM\n");
return ret;
}
/* validate checksum */
for (chksum = 0, i = 0; i < (int)sizeof(*info) - 2; i++)
chksum += buf[i];
if ((info->chksum[0] != chksum >> 8) ||
(info->chksum[1] != (chksum & 0xff))) {
printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
memset(info, 0, sizeof(*info));
return -EINVAL;
}
/* sanity check valid model */
if (info->model[0] != 'G' || info->model[1] != 'W') {
printf("EEPROM: I2C%d@0x%02x: Invalid Model in EEPROM\n", bus, slave);
print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, sizeof(*info));
memset(info, 0, sizeof(*info));
return -EINVAL;
}
return 0;
}
static const char *gsc_get_rst_cause(struct udevice *dev)
{
static char str[64];
static const char * const names[] = {
"VIN",
"PB",
"WDT",
"CPU",
"TEMP_L",
"TEMP_R",
"SLEEP",
"BOOT_WDT1",
"BOOT_WDT2",
"SOFT_PWR",
};
unsigned char reg;
/* reset cause */
str[0] = 0;
if (!dm_i2c_read(dev, GSC_SC_RST_CAUSE, &reg, 1)) {
if (reg < ARRAY_SIZE(names))
sprintf(str, "%s", names[reg]);
else
sprintf(str, "0x%02x", reg);
}
/* thermal protection */
if (!dm_i2c_read(dev, GSC_SC_THERM_PROTECT, &reg, 1)) {
reg |= 1;
dm_i2c_write(dev, GSC_SC_THERM_PROTECT, &reg, 1);
strcat(str, " Thermal Protection Enabled");
}
return str;
}
/* display hardware monitor ADC channels */
int gsc_hwmon(void)
{
const void *fdt = gd->fdt_blob;
struct udevice *dev;
int node, reg, mode, len, val, offset;
const char *label;
u8 buf[2];
int ret;
node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc");
if (node <= 0)
return node;
/* probe device */
dev = gsc_get_dev(1, GSC_HWMON_ADDR);
if (!dev) {
puts("ERROR: Failed to probe GSC HWMON\n");
return -ENODEV;
}
/* iterate over hwmon nodes */
node = fdt_first_subnode(fdt, node);
while (node > 0) {
reg = fdtdec_get_int(fdt, node, "reg", -1);
mode = fdtdec_get_int(fdt, node, "gw,mode", -1);
offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0);
label = fdt_stringlist_get(fdt, node, "label", 0, NULL);
if ((reg == -1) || (mode == -1) || !label)
printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL));
memset(buf, 0, sizeof(buf));
ret = dm_i2c_read(dev, reg, buf, sizeof(buf));
if (ret) {
printf("i2c error: %d\n", ret);
continue;
}
val = buf[0] | buf[1] << 8;
if (val >= 0) {
const u32 *div;
int r[2];
switch (mode) {
case 0: /* temperature (C*10) */
if (val > 0x8000)
val -= 0xffff;
printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10));
break;
case 1: /* prescaled voltage */
if (val != 0xffff)
printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
break;
case 2: /* scaled based on ref volt and resolution */
val *= 2500;
val /= 1 << 12;
/* apply pre-scaler voltage divider */
div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len);
if (div && (len == sizeof(uint32_t) * 2)) {
r[0] = fdt32_to_cpu(div[0]);
r[1] = fdt32_to_cpu(div[1]);
if (r[0] && r[1]) {
val *= (r[0] + r[1]);
val /= r[1];
}
}
/* adjust by offset */
val += offset;
printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000);
break;
}
}
node = fdt_next_subnode(fdt, node);
}
return 0;
}
/* determine BOM revision from model */
int get_bom_rev(const char *str)
{
int rev_bom = 0;
int i;
for (i = strlen(str) - 1; i > 0; i--) {
if (str[i] == '-')
break;
if (str[i] >= '1' && str[i] <= '9') {
rev_bom = str[i] - '0';
break;
}
}
return rev_bom;
}
/* determine PCB revision from model */
char get_pcb_rev(const char *str)
{
char rev_pcb = 'A';
int i;
for (i = strlen(str) - 1; i > 0; i--) {
if (str[i] == '-')
break;
if (str[i] >= 'A') {
rev_pcb = str[i];
break;
}
}
return rev_pcb;
}
/*
* get dt name based on model and detail level:
*
* For boards that are a combination of a SoM plus a Baseboard:
* Venice SoM part numbers are GW70xx where xx is:
* 7000-7019: same PCB with som dt of '0x'
* 7020-7039: same PCB with som dt of '2x'
* 7040-7059: same PCB with som dt of '4x'
* 7060-7079: same PCB with som dt of '6x'
* 7080-7099: same PCB with som dt of '8x'
* Venice Baseboard part numbers are GW7xxx where xxx is:
* 7100-7199: same PCB with base dt of '71xx'
* 7200-7299: same PCB with base dt of '72xx'
* 7300-7399: same PCB with base dt of '73xx'
* 7400-7499: same PCB with base dt of '74xx'
* 7500-7599: same PCB with base dt of '75xx'
* 7600-7699: same PCB with base dt of '76xx'
* 7700-7799: same PCB with base dt of '77xx'
* 7800-7899: same PCB with base dt of '78xx'
* DT name is comprised of:
* gw<base dt>-<som dt>-[base-pcb-rev][base-bom-rev][som-pcb-rev][som-bom-rev]
*
* For board models from 7900-7999 each PCB is unique with its own dt:
* DT name is comprised:
* gw<model>-[pcb-rev][bom-rev]
*
*/
#define snprintfcat(dest, sz, fmt, ...) \
snprintf((dest) + strlen(dest), (sz) - strlen(dest), fmt, ##__VA_ARGS__)
const char *gsc_get_dtb_name(int level, char *buf, int sz)
{
const char *pre = "imx8mm-venice-gw";
int model, rev_pcb, rev_bom;
model = ((som_info.model[2] - '0') * 1000)
+ ((som_info.model[3] - '0') * 100)
+ ((som_info.model[4] - '0') * 10)
+ (som_info.model[5] - '0');
rev_pcb = tolower(get_pcb_rev(som_info.model));
rev_bom = get_bom_rev(som_info.model);
/* som + baseboard*/
if (base_info.model[0]) {
/* baseboard id: 7100-7199->71; 7200-7299->72; etc */
int base = ((base_info.model[2] - '0') * 10) + (base_info.model[3] - '0');
/* som id: 7000-7019->1; 7020-7039->2; etc */
int som = ((model % 100) / 20) * 2;
int rev_base_pcb = tolower(get_pcb_rev(base_info.model));
int rev_base_bom = get_bom_rev(base_info.model);
snprintf(buf, sz, "%s%2dxx-%dx", pre, base, som);
switch (level) {
case 0: /* full model (ie gw73xx-0x-a1a1) */
if (rev_base_bom)
snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
else
snprintfcat(buf, sz, "-%c", rev_base_pcb);
if (rev_bom)
snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
else
snprintfcat(buf, sz, "%c", rev_pcb);
break;
case 1: /* don't care about SoM revision */
if (rev_base_bom)
snprintfcat(buf, sz, "-%c%d", rev_base_pcb, rev_base_bom);
else
snprintfcat(buf, sz, "-%c", rev_base_pcb);
snprintfcat(buf, sz, "xx");
break;
case 2: /* don't care about baseboard revision */
snprintfcat(buf, sz, "-xx");
if (rev_bom)
snprintfcat(buf, sz, "%c%d", rev_pcb, rev_bom);
else
snprintfcat(buf, sz, "%c", rev_pcb);
break;
case 3: /* don't care about SoM/baseboard revision */
break;
default:
return NULL;
}
} else {
snprintf(buf, sz, "%s%04d", pre, model);
switch (level) {
case 0: /* full model wth PCB and BOM revision first (ie gw7901-a1) */
if (rev_bom)
snprintfcat(buf, sz, "-%c%d", rev_pcb, rev_bom);
else
snprintfcat(buf, sz, "-%c", rev_pcb);
break;
case 1: /* don't care about BOM revision */
snprintfcat(buf, sz, "-%c", rev_pcb);
break;
case 2: /* don't care about PCB or BOM revision */
break;
default:
return NULL;
}
}
return buf;
}
static int gsc_read(void)
{
int ret;
ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info);
if (ret) {
memset(&som_info, 0, sizeof(som_info));
return ret;
}
/* read optional baseboard EEPROM */
return gsc_read_eeprom(2, 0x52, 2, &base_info);
}
static int gsc_info(int verbose)
{
struct udevice *dev;
unsigned char buf[16];
char rev_pcb;
int rev_bom;
if (!base_info.model[0]) {
strcpy(venice_model, som_info.model);
printf("Model : %s\n", som_info.model);
printf("Serial : %d\n", som_info.serial);
printf("MFGDate : %02x-%02x-%02x%02x\n",
som_info.mfgdate[0], som_info.mfgdate[1],
som_info.mfgdate[2], som_info.mfgdate[3]);
} else {
sprintf(venice_model, "GW%c%c%c%c-%c%c-",
som_info.model[2], /* family */
base_info.model[3], /* baseboard */
base_info.model[4], base_info.model[5], /* subload of baseboard */
som_info.model[4], som_info.model[5]); /* last 2digits of SOM */
/* baseboard revision */
rev_pcb = get_pcb_rev(base_info.model);
rev_bom = get_bom_rev(base_info.model);
if (rev_bom)
sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
else
sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
/* som revision */
rev_pcb = get_pcb_rev(som_info.model);
rev_bom = get_bom_rev(som_info.model);
if (rev_bom)
sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom);
else
sprintf(venice_model + strlen(venice_model), "%c", rev_pcb);
if (verbose > 1) {
printf("SOM : %s %d %02x-%02x-%02x%02x\n",
som_info.model, som_info.serial,
som_info.mfgdate[0], som_info.mfgdate[1],
som_info.mfgdate[2], som_info.mfgdate[3]);
printf("BASE : %s %d %02x-%02x-%02x%02x\n",
base_info.model, base_info.serial,
base_info.mfgdate[0], base_info.mfgdate[1],
base_info.mfgdate[2], base_info.mfgdate[3]);
}
printf("Model : %s\n", venice_model);
printf("Serial : %d\n", som_info.serial);
printf("MFGDate : %02x-%02x-%02x%02x\n",
som_info.mfgdate[0], som_info.mfgdate[1],
som_info.mfgdate[2], som_info.mfgdate[3]);
}
/* Display RTC */
puts("RTC : ");
dev = gsc_get_dev(1, GSC_RTC_ADDR);
if (!dev) {
puts("Failed to probe GSC RTC\n");
} else {
dm_i2c_read(dev, 0, buf, 6);
printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
}
return 0;
}
int gsc_init(int quiet)
{
unsigned char buf[16];
struct udevice *dev;
int ret;
/*
* On a board with a missing/depleted backup battery for GSC, the
* board may be ready to probe the GSC before its firmware is
* running. We will wait here indefinately for the GSC/EEPROM.
*/
while (1) {
/* probe device */
dev = gsc_get_dev(1, GSC_SC_ADDR);
if (dev)
break;
mdelay(1);
}
ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
if (ret) {
puts("ERROR: Failed reading GSC\n");
return ret;
}
gsc_read();
/* banner */
if (!quiet) {
printf("GSC : v%d 0x%04x", buf[GSC_SC_FWVER],
buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC + 1] << 8);
printf(" RST:%s", gsc_get_rst_cause(dev));
printf("\n");
gsc_info(1);
}
if (ret)
hang();
return ((16 << som_info.sdram_size) / 1024);
}
const char *gsc_get_model(void)
{
return venice_model;
}
#if !(IS_ENABLED(CONFIG_SPL_BUILD))
static int gsc_sleep(unsigned long secs)
{
unsigned char reg;
struct udevice *dev;
int ret;
/* probe device */
dev = gsc_get_dev(1, GSC_SC_ADDR);
if (!dev)
return -ENODEV;
printf("GSC Sleeping for %ld seconds\n", secs);
reg = (secs >> 24) & 0xff;
ret = dm_i2c_write(dev, 9, &reg, 1);
if (ret)
goto err;
reg = (secs >> 16) & 0xff;
ret = dm_i2c_write(dev, 8, &reg, 1);
if (ret)
goto err;
reg = (secs >> 8) & 0xff;
ret = dm_i2c_write(dev, 7, &reg, 1);
if (ret)
goto err;
reg = secs & 0xff;
ret = dm_i2c_write(dev, 6, &reg, 1);
if (ret)
goto err;
ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
if (ret)
goto err;
reg |= (1 << 2);
ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
if (ret)
goto err;
reg &= ~(1 << 2);
reg |= 0x3;
ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
if (ret)
goto err;
return 0;
err:
printf("i2c error\n");
return ret;
}
static int gsc_boot_wd_disable(void)
{
u8 reg;
struct udevice *dev;
int ret;
/* probe device */
dev = gsc_get_dev(1, GSC_SC_ADDR);
if (!dev)
return -ENODEV;
ret = dm_i2c_read(dev, GSC_SC_CTRL1, &reg, 1);
if (ret)
goto err;
reg |= (1 << GSC_SC_CTRL1_WDDIS);
reg &= ~(1 << GSC_SC_CTRL1_BOOT_CHK);
ret = dm_i2c_write(dev, GSC_SC_CTRL1, &reg, 1);
if (ret)
goto err;
puts("GSC : boot watchdog disabled\n");
return 0;
err:
printf("i2c error");
return ret;
}
static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
if (argc < 2)
return gsc_info(2);
if (strcasecmp(argv[1], "sleep") == 0) {
if (argc < 3)
return CMD_RET_USAGE;
if (!gsc_sleep(simple_strtoul(argv[2], NULL, 10)))
return CMD_RET_SUCCESS;
} else if (strcasecmp(argv[1], "hwmon") == 0) {
if (!gsc_hwmon())
return CMD_RET_SUCCESS;
} else if (strcasecmp(argv[1], "wd-disable") == 0) {
if (!gsc_boot_wd_disable())
return CMD_RET_SUCCESS;
}
return CMD_RET_USAGE;
}
U_BOOT_CMD(gsc, 4, 1, do_gsc, "Gateworks System Controller",
"[sleep <secs>]|[hwmon]|[wd-disable]\n");
#endif

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board/gateworks/venice/gsc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Gateworks Corporation
*/
#ifndef _GSC_H_
#define _GSC_H_
/* I2C slave addresses */
#define GSC_SC_ADDR 0x20
#define GSC_RTC_ADDR 0x68
#define GSC_HWMON_ADDR 0x29
#define GSC_EEPROM_ADDR 0x51
struct venice_board_info {
u8 mac[6]; /* 0x00: MAC base */
char equiv_dts[16]; /* 0x06: equivalent device-tree */
u8 res0[2]; /* 0x16: reserved */
u32 serial; /* 0x18: Serial Number */
u8 res1[4]; /* 0x1C: reserved */
u8 mfgdate[4]; /* 0x20: MFG date */
u8 macno; /* 0x24: number of mac addrs */
u8 res2[6]; /* 0x25 */
u8 sdram_size; /* 0x2B: (16 << n) MB */
u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
u8 sdram_width; /* 0x2D: (8 << n) bit */
u8 res3[2]; /* 0x2E */
char model[16]; /* 0x30: model string */
u8 res4[14]; /* 0x40 */
u8 chksum[2]; /* 0x4E */
};
int gsc_init(int quiet);
int gsc_hwmon(void);
const char *gsc_get_model(void);
const char *gsc_get_dtb_name(int level, char *buf, int len);
int gsc_getmac(int index, uint8_t *enetaddr);
#endif

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board/gateworks/venice/imx8mm_venice.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include <common.h>
#include <init.h>
#include <led.h>
#include <linux/delay.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include "gsc.h"
DECLARE_GLOBAL_DATA_PTR;
int board_phys_sdram_size(phys_size_t *size)
{
int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
if (ddr_size == 0x4) {
*size = 0x100000000;
} else if (ddr_size == 0x3) {
*size = 0xc0000000;
} else if (ddr_size == 0x2) {
*size = 0x80000000;
} else if (ddr_size == 0x1) {
*size = 0x40000000;
} else {
printf("Unknown DDR type!!!\n");
*size = 0x40000000;
}
return 0;
}
int board_fit_config_name_match(const char *name)
{
int i = 0;
const char *dtb;
char buf[32];
do {
dtb = gsc_get_dtb_name(i++, buf, sizeof(buf));
if (!strcmp(dtb, name))
return 0;
} while (dtb);
return -1;
}
#if (IS_ENABLED(CONFIG_FEC_MXC))
static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *gpr =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
unsigned short val;
switch (phydev->phy_id) {
case 0x2000a231: /* TI DP83867 GbE PHY */
puts("DP83867 ");
/* LED configuration */
val = 0;
val |= 0x5 << 4; /* LED1(Amber;Speed) : 1000BT link */
val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
break;
}
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif // IS_ENABLED(CONFIG_FEC_MXC)
int board_init(void)
{
gsc_init(1);
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
gsc_hwmon();
return 0;
}
int board_late_init(void)
{
const char *ethmac;
char env[32];
int ret, i;
u8 enetaddr[6];
led_default_state();
/* Set mac addrs */
i = 0;
do {
if (i)
sprintf(env, "eth%daddr", i);
else
sprintf(env, "ethaddr");
ethmac = env_get(env);
if (!ethmac) {
ret = gsc_getmac(i, enetaddr);
if (!ret)
eth_env_set_enetaddr(env, enetaddr);
}
i++;
} while (!ret);
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}

2505
board/gateworks/venice/lpddr4_timing.c Normal file
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12
board/gateworks/venice/lpddr4_timing.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Gateworks Corporation
*/
#ifndef __LPDDR4_TIMING_H__
#define __LPDDR4_TIMING_H__
extern struct dram_timing_info dram_timing_1gb;
extern struct dram_timing_info dram_timing_4gb;
#endif /* __LPDDR4_TIMING_H__ */

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board/gateworks/venice/spl.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Gateworks Corporation
*/
#include <common.h>
#include <cpu_func.h>
#include <hang.h>
#include <i2c.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/arch/ddr.h>
#include <asm-generic/gpio.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <power/mp5416.h>
#include "gsc.h"
#include "lpddr4_timing.h"
#define PCIE_RSTN IMX_GPIO_NR(4, 6)
DECLARE_GLOBAL_DATA_PTR;
static void spl_dram_init(int size)
{
struct dram_timing_info *dram_timing;
switch (size) {
case 1:
dram_timing = &dram_timing_1gb;
break;
case 4:
dram_timing = &dram_timing_4gb;
break;
default:
printf("Unknown DDR configuration: %d GiB\n", size);
dram_timing = &dram_timing_1gb;
size = 1;
}
printf("DRAM : LPDDR4 %d GiB\n", size);
ddr_init(dram_timing);
writel(size, M4_BOOTROM_BASE_ADDR);
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
/*
* Model specific PMIC adjustments necessary prior to DRAM init
*
* Note that we can not use pmic dm drivers here as we have a generic
* venice dt that does not have board-specific pmic's defined.
*
* Instead we must use dm_i2c.
*/
static int power_init_board(void)
{
const char *model = gsc_get_model();
struct udevice *bus;
struct udevice *dev;
int ret;
if ((!strncmp(model, "GW71", 4)) ||
(!strncmp(model, "GW72", 4)) ||
(!strncmp(model, "GW73", 4))) {
ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus);
if (ret) {
printf("PMIC : failed I2C1 probe: %d\n", ret);
return ret;
}
ret = dm_i2c_probe(bus, 0x69, 0, &dev);
if (ret) {
printf("PMIC : failed probe: %d\n", ret);
return ret;
}
puts("PMIC : MP5416\n");
/* set VDD_ARM SW3 to 0.92V for 1.6GHz */
dm_i2c_reg_write(dev, MP5416_VSET_SW3,
BIT(7) | MP5416_VSET_SW3_SVAL(920000));
}
return 0;
}
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
int dram_sz;
arch_cpu_init();
init_uart_clk(1);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0) {
printf("Failed to find clock node. Check device tree\n");
hang();
}
enable_tzc380();
/* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */
gpio_request(PCIE_RSTN, "perst#");
gpio_direction_output(PCIE_RSTN, 0);
/* GSC */
dram_sz = gsc_init(0);
/* PMIC */
power_init_board();
/* DDR initialization */
spl_dram_init(dram_sz);
board_init_r(NULL, 0);
}
/* determine prioritized order of boot devices to load U-Boot from */
void board_boot_order(u32 *spl_boot_list)
{
/*
* If the SPL was loaded via serial loader, we try to get
* U-Boot proper via USB SDP.
*/
if (spl_boot_device() == BOOT_DEVICE_BOARD)
spl_boot_list[0] = BOOT_DEVICE_BOARD;
/* we have only eMMC in default venice dt */
spl_boot_list[0] = BOOT_DEVICE_MMC1;
}
/* return boot device based on where the SPL was loaded from */
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
case USB_BOOT:
return BOOT_DEVICE_BOARD;
/* SDHC2 */
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC1;
/* SDHC3 */
case SD3_BOOT:
case MMC3_BOOT:
return BOOT_DEVICE_MMC2;
default:
return BOOT_DEVICE_NONE;
}
}

24
common/image.c
View file

@ -462,13 +462,16 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
else
ret = -ENOSPC;
break;
#ifdef CONFIG_GZIP
#ifndef USE_HOSTCC
#if CONFIG_IS_ENABLED(GZIP)
case IH_COMP_GZIP: {
ret = gunzip(load_buf, unc_len, image_buf, &image_len);
break;
}
#endif /* CONFIG_GZIP */
#ifdef CONFIG_BZIP2
#endif
#ifndef USE_HOSTCC
#if CONFIG_IS_ENABLED(BZIP2)
case IH_COMP_BZIP2: {
uint size = unc_len;
@ -484,7 +487,9 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
break;
}
#endif /* CONFIG_BZIP2 */
#ifdef CONFIG_LZMA
#endif
#ifndef USE_HOSTCC
#if CONFIG_IS_ENABLED(LZMA)
case IH_COMP_LZMA: {
SizeT lzma_len = unc_len;
@ -494,7 +499,9 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
break;
}
#endif /* CONFIG_LZMA */
#ifdef CONFIG_LZO
#endif
#ifndef USE_HOSTCC
#if CONFIG_IS_ENABLED(LZO)
case IH_COMP_LZO: {
size_t size = unc_len;
@ -503,7 +510,9 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
break;
}
#endif /* CONFIG_LZO */
#ifdef CONFIG_LZ4
#endif
#ifndef USE_HOSTCC
#if CONFIG_IS_ENABLED(LZ4)
case IH_COMP_LZ4: {
size_t size = unc_len;
@ -512,7 +521,9 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
break;
}
#endif /* CONFIG_LZ4 */
#ifdef CONFIG_ZSTD
#endif
#ifndef USE_HOSTCC
#if CONFIG_IS_ENABLED(ZSTD)
case IH_COMP_ZSTD: {
size_t size = unc_len;
ZSTD_DStream *dstream;
@ -562,6 +573,7 @@ int image_decomp(int comp, ulong load, ulong image_start, int type,
break;
}
#endif /* CONFIG_ZSTD */
#endif
default:
printf("Unimplemented compression type %d\n", comp);
return -ENOSYS;

7
configs/dh_imx6_defconfig
View file

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x10000000
CONFIG_SYS_MEMTEST_END=0x20000000
@ -28,8 +29,8 @@ CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-dhcom-pdk2"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@ -54,14 +55,12 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
@ -108,5 +107,5 @@ CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
# CONFIG_SPL_WDT is not set
CONFIG_BZIP2=y
CONFIG_OF_LIBFDT_OVERLAY=y

113
configs/imx8mm_venice_defconfig Normal file
View file

@ -0,0 +1,113 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0xff0000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_VENICE=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xff8000
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_FULL=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_UUID=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx8mm-venice-gw71xx-0x imx8mm-venice-gw72xx-0x imx8mm-venice-gw73xx-0x"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_SPL_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_PMIC_MP5416=y
CONFIG_SPL_DM_PMIC_MP5416=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_IMX_WATCHDOG=y
CONFIG_HEXDUMP=y

133
configs/imx8mn_beacon_2g_defconfig Normal file
View file

@ -0,0 +1,133 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x0
CONFIG_OF_LIBFDT_OVERLAY=y

14
configs/mx23evk_defconfig
View file

@ -7,16 +7,19 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x40000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_MX23EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="imx23-evk"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
@ -24,17 +27,22 @@ CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
CONFIG_DM=y
CONFIG_MXS_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MXS=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_SPLASH_SCREEN=y
CONFIG_VIDEO_BMP_GZIP=y
CONFIG_OF_LIBFDT=y

19
configs/mx51evk_defconfig
View file

@ -5,15 +5,19 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX51EVK=y
CONFIG_DM_GPIO=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
@ -22,16 +26,30 @@ CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
@ -39,4 +57,3 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_OF_LIBFDT=y

22
configs/mx53loco_defconfig
View file

@ -1,11 +1,14 @@
CONFIG_ARM=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX53LOCO=y
CONFIG_DM_GPIO=y
# CONFIG_CMD_BMODE is not set
CONFIG_DEFAULT_DEVICE_TREE="imx53-qsb"
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg"
CONFIG_USE_PREBOOT=y
@ -13,8 +16,9 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_DM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SATA=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -23,15 +27,28 @@ CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DWC_AHSATA=y
CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
@ -40,4 +57,3 @@ CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_SPLASH_SCREEN=y
CONFIG_OF_LIBFDT=y

1
configs/mx6sabreauto_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_NXP_BOARD_REVISION=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y

1
configs/mx6sabresd_defconfig
View file

@ -20,6 +20,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
CONFIG_FIT=y
CONFIG_SPL_FIT_PRINT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"

27
doc/board/freescale/imx8mp_evk.rst
View file

@ -16,27 +16,21 @@ Quick Start
Get and Build the ARM Trusted firmware
--------------------------------------
Note: $(srctree) is the U-Boot source directory
Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
branch: imx_5.4.47_2.2.0
branch: imx_5.4.70_2.3.0
.. code-block:: bash
$ make PLAT=imx8mp bl31
$ cp build/imx8mp/release/bl31.bin $(srctree)
Get the ddr firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9.bin
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_1d_dmem.bin
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_201904.bin $(srctree)/lpddr4_pmu_train_1d_imem.bin
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_201904.bin $(srctree)/lpddr4_pmu_train_2d_dmem.bin
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_201904.bin $(srctree)/lpddr4_pmu_train_2d_imem.bin
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.10.bin
$ chmod +x firmware-imx-8.10.bin
$ ./firmware-imx-8.10.bin
Build U-Boot
------------
@ -44,15 +38,20 @@ Build U-Boot
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-poky-linux-
$ make imx8mp_evk_defconfig
$ export ATF_LOAD_ADDR=0x960000
$ make flash.bin
$ make O=build imx8mp_evk_defconfig
$ cp ../imx-atf/build/imx8mp/release/bl31.bin ./build/bl31.bin
$ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/lpddr4_pmu_train_1d_dmem.bin
$ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/lpddr4_pmu_train_1d_imem.bin
$ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/lpddr4_pmu_train_2d_dmem.bin
$ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/lpddr4_pmu_train_2d_imem.bin
$ export ATF_LOAD_ADDR=0x970000
$ make O=build flash.bin
Burn the flash.bin to the MicroSD card at offset 32KB:
.. code-block:: bash
$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
$sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
Boot
----

7
drivers/mmc/fsl_esdhc_imx.c
View file

@ -43,6 +43,12 @@
#include "mmc_private.h"
#endif
#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#ifdef CONFIG_FSL_USDHC
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
#endif
#endif
DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
@ -1706,6 +1712,7 @@ static struct esdhc_soc_data usdhc_imx8qm_data = {
};
static const struct udevice_id fsl_esdhc_ids[] = {
{ .compatible = "fsl,imx51-esdhc", },
{ .compatible = "fsl,imx53-esdhc", },
{ .compatible = "fsl,imx6ul-usdhc", },
{ .compatible = "fsl,imx6sx-usdhc", },

6
drivers/thermal/imx_tmu.c
View file

@ -344,6 +344,7 @@ static int imx_tmu_bind(struct udevice *dev)
ofnode node, offset;
const char *name;
const void *prop;
int minc, maxc;
debug("%s dev name %s\n", __func__, dev->name);
@ -352,6 +353,10 @@ static int imx_tmu_bind(struct udevice *dev)
return 0;
pdata->zone_node = 1;
/* default alert/crit temps based on temp grade */
get_cpu_temp_grade(&minc, &maxc);
pdata->critical = maxc * 1000;
pdata->alert = (maxc - 10) * 1000;
node = ofnode_path("/thermal-zones");
ofnode_for_each_subnode(offset, node) {
@ -443,6 +448,7 @@ static int imx_tmu_probe(struct udevice *dev)
if (pdata->zone_node) {
imx_tmu_init(dev);
imx_tmu_calibration(dev);
imx_tmu_enable_msite(dev);
} else {
imx_tmu_enable_msite(dev);
}

3
include/configs/apalis-imx8.h
View file

@ -21,9 +21,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Networking */
#define FEC_QUIRK_ENET_MAC
#define FEC_ENET_ENABLE_TXC_DELAY
#define CONFIG_TFTP_TSIZE
#define CONFIG_IPADDR 192.168.10.2

4
include/configs/apalis-imx8x.h
View file

@ -25,9 +25,6 @@
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
#define FEC_ENET_ENABLE_TXC_DELAY
#define FEC_ENET_ENABLE_RXC_DELAY
#define MEM_LAYOUT_ENV_SETTINGS \
"kernel_addr_r=0x80280000\0" \
"fdt_addr_r=0x83100000\0" \
@ -143,7 +140,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0x4
#define CONFIG_ETHPRIME "eth0"
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
#define PHY_ANEG_TIMEOUT 20000
#endif /* __APALIS_IMX8X_H */

1
include/configs/capricorn-common.h
View file

@ -43,7 +43,6 @@
/* ENET Config */
#define CONFIG_FEC_XCV_TYPE RMII
#define FEC_QUIRK_ENET_MAC
/* ENET1 connects to base board and MUX with ESAI */
#define CONFIG_FEC_ENET_DEV 1

2
include/configs/colibri-imx8x.h
View file

@ -22,8 +22,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Networking */
#define FEC_QUIRK_ENET_MAC
#define CONFIG_TFTP_TSIZE
#define CONFIG_IPADDR 192.168.10.2

125
include/configs/imx8mm_venice.h Normal file
View file

@ -0,0 +1,125 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Gateworks Corporation
*/
#ifndef __IMX8MM_VENICE_H
#define __IMX8MM_VENICE_H
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_STACK 0x920000
#define CONFIG_SPL_BSS_START_ADDR 0x910000
#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x930000
/* For RAW image gives a error info not panic */
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#endif
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x44000000\0" \
"kernel_addr_r=0x42000000\0" \
"ramdisk_addr_r=0x46400000\0" \
"scriptaddr=0x46000000\0"
/* Link Definitions */
#define CONFIG_LOADADDR 0x40480000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Enable Distro Boot */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#undef CONFIG_ISO_PARTITION
#else
#define BOOTENV
#endif
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"script=boot.scr\0" \
"bootm_size=0x10000000\0" \
"ipaddr=192.168.1.22\0" \
"serverip=192.168.1.146\0" \
"dev=2\0" \
"preboot=gsc wd-disable\0" \
"console=ttymxc1,115200\0" \
"update_firmware=" \
"tftpboot $loadaddr $image && " \
"setexpr blkcnt $filesize + 0x1ff && " \
"setexpr blkcnt $blkcnt / 0x200 && " \
"mmc dev $dev && " \
"mmc write $loadaddr 0x42 $blkcnt\0" \
"boot_net=" \
"tftpboot $kernel_addr_r $image && " \
"booti $kernel_addr_r - $fdtcontroladdr\0" \
"update_rootfs=" \
"tftpboot $loadaddr $image && " \
"gzwrite mmc $dev $loadaddr $filesize 100000 1000000\0" \
"update_all=" \
"tftpboot $loadaddr $image && " \
"gzwrite mmc $dev $loadaddr $filesize\0" \
"erase_env=mmc dev $dev; mmc erase 0x7f08 0x40\0"
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_SYS_SDRAM_BASE 0x40000000
/* SDRAM configuration */
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
#define CONFIG_SYS_BOOTM_LEN SZ_256M
/* UART */
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* USDHC */
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* I2C */
#define CONFIG_SYS_I2C_SPEED 100000
/* FEC */
#define CONFIG_ETHPRIME "eth0"
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define FEC_QUIRK_ENET_MAC
#define IMX_FEC_BASE 0x30BE0000
#endif

4
include/configs/imx8mn_beacon.h
View file

@ -126,7 +126,11 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#else
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#endif
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR

1
include/configs/imx8qm_mek.h
View file

@ -173,6 +173,5 @@
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
#endif /* __IMX8QM_MEK_H */

1
include/configs/imx8qm_rom7720.h
View file

@ -161,7 +161,6 @@
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
#include <linux/stringify.h>
#endif /* __IMX8QM_ROM7720_H */

1
include/configs/imx8qxp_mek.h
View file

@ -177,7 +177,6 @@
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
/* Misc configuration */
#define CONFIG_SYS_CBSIZE 2048

8
include/configs/mx51evk.h
View file

@ -51,14 +51,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/*
* Eth Configs
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI

6
include/configs/mx53loco.h
View file

@ -30,12 +30,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 2
/* Eth Configs */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1F
/* USB Configs */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

9
include/configs/mx6sabre_common.h
View file

@ -73,11 +73,14 @@
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait rw\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \
"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \
"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run finduuid; " \
"run mmcargs; " \

8
tools/imx8mimage.c
View file

@ -32,6 +32,8 @@ static uint32_t rom_version = ROM_V1;
#define HDMI_FW_SIZE 0x17000 /* Use Last 0x1000 for IVT and CSF */
#define ALIGN_SIZE 0x1000
#define ALIGN_IMX(x, a) __ALIGN_MASK_IMX((x), (__typeof__(x))(a) - 1, a)
#define __ALIGN_MASK_IMX(x, mask, mask2) (((x) + (mask)) / (mask2) * (mask2))
static uint32_t get_cfg_value(char *token, char *name, int linenr)
{
@ -342,7 +344,7 @@ static int generate_ivt_for_fit(int fd, int fit_offset, uint32_t ep,
fit_size = fdt_totalsize(&image_header);
fit_size = ALIGN(fit_size, ALIGN_SIZE);
fit_size = ALIGN_IMX(fit_size, ALIGN_SIZE);
ret = lseek(fd, fit_offset + fit_size, SEEK_SET);
if (ret < 0) {
@ -446,7 +448,7 @@ void build_image(int ofd)
* Aligned to 104KB = 92KB FW image + 0x8000
* (IVT and alignment) + 0x4000 (second IVT + CSF)
*/
file_off += ALIGN(sbuf.st_size,
file_off += ALIGN_IMX(sbuf.st_size,
HDMI_FW_SIZE + 0x2000 + 0x1000);
}
@ -479,7 +481,7 @@ void build_image(int ofd)
imx_header[IMAGE_IVT_ID].boot_data.start =
imx_header[IMAGE_IVT_ID].fhdr.self - ivt_offset;
imx_header[IMAGE_IVT_ID].boot_data.size =
ALIGN(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset,
ALIGN_IMX(sbuf.st_size + sizeof(imx_header_v3_t) + ivt_offset,
sector_size);
image_off = header_image_off + sizeof(imx_header_v3_t);