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stv0991: configure device tree for cadence qspi & flash

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This patch add the device tree entry for qspi controller & spi flash
memory.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This commit is contained in:
Vikas Manocha 2015-07-02 18:29:42 -07:00 committed by Jagan Teki
parent e67abcaacb
commit 51d558392b
1 changed files with 34 additions and 0 deletions
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34
arch/arm/dts/stv0991.dts
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@ -20,4 +20,38 @@
reg = <0x80406000 0x1000>; reg = <0x80406000 0x1000>;
clock = <2700000>; clock = <2700000>;
}; };
aliases {
spi0 = "/spi@80203000"; /* QSPI */
};
qspi: spi@80203000 {
compatible = "cadence,qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80203000 0x100>,
<0x40000000 0x1000000>;
clocks = <3750000>;
ext-decoder = <0>; /* external decoder */
num-cs = <4>;
fifo-depth = <256>;
bus-num = <0>;
status = "okay";
flash0: n25q32@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
read-delay = <4>; /* delay value in read data capture register */
tshsl-ns = <50>;
tsd2d-ns = <50>;
tchsh-ns = <4>;
tslch-ns = <4>;
};
};
}; };