arm: dts: fsl-ls1088a: copy all missing bindings from Linux
This is effectively: cp linux/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi \ u-boot/arch/arm/dts/fsl-ls1088a.dtsi Tested working with Ten64 board (LS1088A) booting openSUSE Tumbleweed. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
This commit is contained in:
Mathew McBride
Peng Fan
parent
fd4f7b0158
commit
51b9254e02
1 changed files with 304 additions and 16 deletions
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@ -1,18 +1,27 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* NXP ls1088a SOC common device tree source
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* Device Tree Include file for NXP Layerscape-1088A family SoC.
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*
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* Copyright 2017-2020 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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*
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* Copyright 2017, 2020-2021, 2023 NXP
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*/
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#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,ls1088a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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crypto = &crypto;
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rtc1 = &ftm_alarm0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -121,12 +130,73 @@
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};
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};
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thermal-zones {
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core-cluster {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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core_cluster_alert: core-cluster-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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core-cluster-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&core_cluster_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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soc {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 1>;
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trips {
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soc-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
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<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
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<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
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<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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sysclk: sysclk {
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@ -136,6 +206,13 @@
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clock-output-names = "sysclk";
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};
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reboot {
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compatible = "syscon-reboot";
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regmap = <&reset>;
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offset = <0x0>;
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mask = <0x02>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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@ -150,13 +227,105 @@
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clocks = <&sysclk>;
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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dcfg: dcfg@1e00000 {
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compatible = "fsl,ls1088a-dcfg", "syscon";
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reg = <0x0 0x1e00000 0x0 0x10000>;
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little-endian;
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};
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reset: syscon@1e60000 {
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compatible = "fsl,ls1088a-reset", "syscon";
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reg = <0x0 0x1e60000 0x0 0x10000>;
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};
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isc: syscon@1f70000 {
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compatible = "fsl,ls1088a-isc", "syscon";
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reg = <0x0 0x1f70000 0x0 0x10000>;
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little-endian;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x1f70000 0x10000>;
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extirq: interrupt-controller@14 {
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compatible = "fsl,ls1088a-extirq";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x14 4>;
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interrupt-map =
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<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0xf 0x0>;
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};
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};
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sfp: efuse@1e80000 {
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compatible = "fsl,ls1028a-sfp";
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reg = <0x0 0x1e80000 0x0 0x10000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(4)>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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clock-names = "sfp";
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};
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tmu: tmu@1f80000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f80000 0x0 0x10000>;
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interrupts = <0 23 0x4>;
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
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fsl,tmu-calibration =
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/* Calibration data group 1 */
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<0x00000000 0x00000023
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0x00000001 0x0000002a
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0x00000002 0x00000030
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0x00000003 0x00000037
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0x00000004 0x0000003d
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0x00000005 0x00000044
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0x00000006 0x0000004a
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0x00000007 0x00000051
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0x00000008 0x00000057
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0x00000009 0x0000005e
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0x0000000a 0x00000064
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0x0000000b 0x0000006b
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/* Calibration data group 2 */
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0x00010000 0x00000022
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0x00010001 0x0000002a
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0x00010002 0x00000032
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0x00010003 0x0000003a
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0x00010004 0x00000042
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0x00010005 0x0000004a
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0x00010006 0x00000052
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0x00010007 0x0000005a
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0x00010008 0x00000062
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0x00010009 0x0000006a
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/* Calibration data group 3 */
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0x00020000 0x00000021
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0x00020001 0x0000002b
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0x00020002 0x00000035
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0x00020003 0x00000040
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0x00020004 0x0000004a
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0x00020005 0x00000054
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0x00020006 0x0000005e
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/* Calibration data group 4 */
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0x00030000 0x00000010
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0x00030001 0x0000001c
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0x00030002 0x00000027
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0x00030003 0x00000032
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0x00030004 0x0000003e
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0x00030005 0x00000049
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0x00030006 0x00000054
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0x00030007 0x00000060>;
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little-endian;
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#thermal-sensor-cells = <1>;
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};
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dspi: spi@2100000 {
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status = "disabled";
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(4)>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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};
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console@8340020 {
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compatible = "fsl,dpaa2-console";
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reg = <0x00000000 0x08340020 0 0x2>;
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};
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ptp-timer@8b95000 {
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compatible = "fsl,dpaa2-ptp";
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reg = <0x0 0x8b95000 0x0 0x100>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(1)>;
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little-endian;
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fsl,extts-fifo;
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};
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emdio1: mdio@8b96000 {
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compatible = "fsl,fman-memac-mdio";
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reg = <0x0 0x8b96000 0x0 0x1000>;
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@ -682,6 +874,86 @@
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};
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};
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cluster1_core0_watchdog: wdt@c000000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc000000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster1_core1_watchdog: wdt@c010000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc010000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster1_core2_watchdog: wdt@c020000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc020000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster1_core3_watchdog: wdt@c030000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc030000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster2_core0_watchdog: wdt@c100000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc100000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster2_core1_watchdog: wdt@c110000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc110000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster2_core2_watchdog: wdt@c120000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc120000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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cluster2_core3_watchdog: wdt@c130000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x0 0xc130000 0x0 0x1000>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>,
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<&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(16)>;
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clock-names = "wdog_clk", "apb_pclk";
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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};
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};
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};
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rcpm: power-controller@1e34040 {
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compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
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reg = <0x0 0x1e34040 0x0 0x18>;
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#fsl,rcpm-wakeup-cells = <6>;
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little-endian;
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};
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ftm_alarm0: timer@2800000 {
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compatible = "fsl,ls1088a-ftm-alarm";
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reg = <0x0 0x2800000 0x0 0x10000>;
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fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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};
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