[PATCH] This patch add varius fix to the ehci.
- fix ehci_readl, ehci_writel - introduce new define in ehci.h - introduce the handshake function for waiting on a register - fix usb_ehci_fsl with the new HC_LENGTH macro Signed-off-by: Michael Trimarchi <trimarchimichael@yahoo.it> Signed-off-by: Remy Böhmer <linux@bohmer.net>
This commit is contained in:
michael
Remy Bohmer
parent
db63299b1d
commit
51ab142b8b
4 changed files with 133 additions and 44 deletions
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@ -45,15 +45,24 @@ struct ehci_hccr {
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#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
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#define HC_VERSION(p) (((p) >> 16) & 0xffff)
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uint32_t cr_hcsparams;
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#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
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uint32_t cr_hccparams;
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uint8_t cr_hcsp_portrt[8];
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};
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struct ehci_hcor {
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uint32_t or_usbcmd;
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#define CMD_ASE (1 << 5)
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#define CMD_PARK (1 << 11) /* enable "park" */
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#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
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#define CMD_ASE (1 << 5) /* async schedule enable */
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#define CMD_LRESET (1 << 7) /* partial reset */
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#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
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#define CMD_PSE (1 << 4) /* periodic schedule enable */
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#define CMD_RESET (1 << 1) /* reset HC not bus */
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#define CMD_RUN (1 << 0) /* start/stop HC */
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uint32_t or_usbsts;
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#define STD_ASS (1 << 15)
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#define STS_HALT (1 << 12)
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uint32_t or_usbintr;
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uint32_t or_frindex;
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uint32_t or_ctrldssegment;
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@ -61,10 +70,17 @@ struct ehci_hcor {
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uint32_t or_asynclistaddr;
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uint32_t _reserved_[9];
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uint32_t or_configflag;
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#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
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uint32_t or_portsc[2];
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uint32_t or_systune;
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};
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#define USBMODE 0x68 /* USB Device mode */
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#define USBMODE_SDIS (1 << 3) /* Stream disable */
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#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
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#define USBMODE_CM_HC (3 << 0) /* host controller mode */
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#define USBMODE_CM_IDLE (0 << 0) /* idle state */
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/* Interface descriptor */
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struct usb_linux_interface_descriptor {
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unsigned char bLength;
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@ -91,11 +107,12 @@ struct usb_linux_config_descriptor {
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} __attribute__ ((packed));
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#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
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#define ehci_readl(x) (x)
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#define ehci_writel(a, b) (a) = (b)
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#define ehci_readl(x) (*((volatile u32 *)(x)))
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#define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b))
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#else
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#define ehci_readl(x) cpu_to_le32((x))
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#define ehci_writel(a, b) (a) = cpu_to_le32((b))
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#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x))))
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#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
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cpu_to_le32(((volatile u32)b)))
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#endif
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#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
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@ -99,8 +99,55 @@ static struct descriptor {
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},
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};
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static void ehci_free (void *p, size_t sz)
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static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int msec)
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{
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uint32_t result;
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do {
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result = ehci_readl(ptr);
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debug("handshake read reg(%x)=%x\n", (uint32_t)ptr, result);
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if (result == ~(uint32_t)0)
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return -1;
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result &= mask;
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if (result == done)
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return 0;
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wait_ms(1);
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msec--;
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} while (msec > 0);
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return -1;
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}
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static void ehci_free(void *p, size_t sz)
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{
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}
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static int ehci_reset(void)
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{
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uint32_t cmd;
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uint32_t tmp;
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uint32_t *reg_ptr;
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int ret = 0;
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cmd = ehci_readl(&hcor->or_usbcmd);
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cmd |= CMD_RESET;
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ehci_writel(&hcor->or_usbcmd, cmd);
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ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, 250);
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if (ret < 0) {
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printf("EHCI fail to reset\n");
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goto out;
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}
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#if defined CONFIG_EHCI_IS_TDI
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reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
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tmp = ehci_readl(reg_ptr);
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tmp |= USBMODE_CM_HC;
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#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
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tmp |= USBMODE_BE;
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#endif
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ehci_writel(reg_ptr, tmp);
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#endif
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out:
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return ret;
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}
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static void *ehci_alloc(size_t sz, size_t align)
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@ -170,6 +217,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
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uint32_t endpt, token, usbsts;
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uint32_t c, toggle;
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uint32_t cmd;
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uint32_t sts;
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debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
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buffer, length, req);
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@ -277,16 +325,19 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
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qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
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usbsts = ehci_readl(hcor->or_usbsts);
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ehci_writel(hcor->or_usbsts, (usbsts & 0x3f));
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usbsts = ehci_readl(&hcor->or_usbsts);
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ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
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/* Enable async. schedule. */
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cmd = ehci_readl(hcor->or_usbcmd);
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hcor->or_usbcmd |= CMD_ASE;
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ehci_writel(hcor->or_usbcmd, cmd);
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cmd = ehci_readl(&hcor->or_usbcmd);
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cmd |= CMD_ASE;
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ehci_writel(&hcor->or_usbcmd, cmd);
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while ((ehci_readl(hcor->or_usbsts) & STD_ASS) == 0)
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udelay(1);
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sts = ehci_readl(&hcor->or_usbsts);
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while ((sts & STD_ASS) == 0) {
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sts = ehci_readl(&hcor->or_usbsts);
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udelay(10);
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}
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/* Wait for TDs to be processed. */
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ts = get_timer(0);
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@ -298,11 +349,15 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
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} while (get_timer(ts) < CONFIG_SYS_HZ);
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/* Disable async schedule. */
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cmd = ehci_readl(hcor->or_usbcmd);
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cmd = ehci_readl(&hcor->or_usbcmd);
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cmd &= ~CMD_ASE;
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ehci_writel(hcor->or_usbcmd, cmd);
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while ((ehci_readl(hcor->or_usbsts) & STD_ASS) != 0)
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udelay(1);
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ehci_writel(&hcor->or_usbcmd, cmd);
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sts = ehci_readl(&hcor->or_usbsts);
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while ((sts & STD_ASS) != 0) {
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sts = ehci_readl(&hcor->or_usbsts);
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udelay(10);
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}
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qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
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@ -335,9 +390,9 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
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} else {
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dev->act_len = 0;
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debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
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dev->devnum, ehci_readl(hcor->or_usbsts),
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ehci_readl(hcor->or_portsc[0]),
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ehci_readl(hcor->or_portsc[1]));
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dev->devnum, ehci_readl(&hcor->or_usbsts),
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ehci_readl(&hcor->or_portsc[0]),
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ehci_readl(&hcor->or_portsc[1]));
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}
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return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
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@ -451,7 +506,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
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break;
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case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
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memset(tmpbuf, 0, 4);
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reg = ehci_readl(hcor->or_portsc[le16_to_cpu(req->index)
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reg = ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index)
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- 1]);
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if (reg & EHCI_PS_CS)
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tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
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@ -479,9 +534,12 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
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srclen = 4;
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break;
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case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
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reg = ehci_readl(hcor->or_portsc[le16_to_cpu(req->index) - 1]);
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reg = ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index) - 1]);
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reg &= ~EHCI_PS_CLEAR;
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switch (le16_to_cpu(req->value)) {
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case USB_PORT_FEAT_ENABLE:
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reg |= EHCI_PS_PE;
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break;
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case USB_PORT_FEAT_POWER:
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reg |= EHCI_PS_PP;
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break;
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@ -495,22 +553,22 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
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/* Start reset sequence. */
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reg &= ~EHCI_PS_PE;
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reg |= EHCI_PS_PR;
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ehci_writel(hcor->or_portsc[
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ehci_writel(&hcor->or_portsc[
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le16_to_cpu(req->index) - 1], reg);
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/* Wait for reset to complete. */
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udelay(500000);
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wait_ms(500);
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/* Terminate reset sequence. */
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reg &= ~EHCI_PS_PR;
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/* TODO: is it only fsl chip that requires this
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* manual setting of port enable?
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*/
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reg |= EHCI_PS_PE;
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ehci_writel(hcor->or_portsc[
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ehci_writel(&hcor->or_portsc[
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le16_to_cpu(req->index) - 1], reg);
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/* Wait for HC to complete reset. */
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udelay(2000);
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wait_ms(10);
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reg =
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ehci_readl(hcor->or_portsc[le16_to_cpu(req->index)
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ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index)
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- 1]);
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reg &= ~EHCI_PS_CLEAR;
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if ((reg & EHCI_PS_PE) == 0) {
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@ -525,10 +583,10 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
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debug("unknown feature %x\n", le16_to_cpu(req->value));
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goto unknown;
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}
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ehci_writel(hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
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ehci_writel(&hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
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break;
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case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
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reg = ehci_readl(hcor->or_portsc[le16_to_cpu(req->index) - 1]);
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reg = ehci_readl(&hcor->or_portsc[le16_to_cpu(req->index) - 1]);
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reg &= ~EHCI_PS_CLEAR;
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switch (le16_to_cpu(req->value)) {
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case USB_PORT_FEAT_ENABLE:
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@ -537,6 +595,9 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
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case USB_PORT_FEAT_C_CONNECTION:
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reg |= EHCI_PS_CSC;
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break;
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case USB_PORT_FEAT_OVER_CURRENT:
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reg |= EHCI_PS_OCC;
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break;
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case USB_PORT_FEAT_C_RESET:
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portreset &= ~(1 << le16_to_cpu(req->index));
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break;
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@ -544,7 +605,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
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debug("unknown feature %x\n", le16_to_cpu(req->value));
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goto unknown;
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}
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ehci_writel(hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
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ehci_writel(&hcor->or_portsc[le16_to_cpu(req->index) - 1], reg);
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break;
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default:
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debug("Unknown request\n");
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@ -585,6 +646,10 @@ int usb_lowlevel_init(void)
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if (ehci_hcd_init() != 0)
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return -1;
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/* EHCI spec section 4.1 */
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if (ehci_reset() != 0)
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return -1;
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/* Set head of reclaim list */
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memset(&qh_list, 0, sizeof(qh_list));
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qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
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@ -595,25 +660,31 @@ int usb_lowlevel_init(void)
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qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
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/* Set async. queue head pointer. */
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ehci_writel(hcor->or_asynclistaddr, (uint32_t)&qh_list);
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ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
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reg = ehci_readl(hccr->cr_hcsparams);
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descriptor.hub.bNbrPorts = reg & 0xf;
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printf("NbrPorts %x\n", descriptor.hub.bNbrPorts);
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reg = ehci_readl(&hccr->cr_hcsparams);
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descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
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printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
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if (reg & 0x10000) /* Port Indicators */
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descriptor.hub.wHubCharacteristics |= 0x80;
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if (reg & 0x10) /* Port Power Control */
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descriptor.hub.wHubCharacteristics |= 0x01;
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/* take control over the ports */
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cmd = ehci_readl(hcor->or_configflag);
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cmd |= 1;
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ehci_writel(hcor->or_configflag, cmd);
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/* Start the host controller. */
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cmd = ehci_readl(hcor->or_configflag);
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cmd |= 1;
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ehci_writel(hcor->or_usbcmd, cmd);
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cmd = ehci_readl(&hcor->or_usbcmd);
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/* Philips, Intel, and maybe others need CMD_RUN before the
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* root hub will detect new devices (why?); NEC doesn't */
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cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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cmd |= CMD_RUN;
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ehci_writel(&hcor->or_usbcmd, cmd);
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/* take control over the ports */
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cmd = ehci_readl(&hcor->or_configflag);
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cmd |= FLAG_CF;
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ehci_writel(&hcor->or_configflag, cmd);
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/* unblock posted writes */
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cmd = ehci_readl(&hcor->or_usbcmd);
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wait_ms(5);
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rootdev = 0;
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@ -43,7 +43,8 @@ int ehci_hcd_init(void)
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addr = (uint32_t)&(im->usb[0]);
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hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI);
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hcor = (struct ehci_hcor *)((uint32_t) hccr + hccr->cr_caplength);
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hcor = (struct ehci_hcor *)((uint32_t) hccr +
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HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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/* Configure clock */
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clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK,
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@ -181,7 +181,7 @@ struct usb_device {
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*/
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#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
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defined(CONFI_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
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defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
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defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
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defined(CONFIG_USB_R8A66597_HCD)
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