SPI: Add SPI driver support for Marvell Armada100
This patch provides support for SPI emulated over SSP for Marvell Armada100 SOC. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
This commit is contained in:
Ajay Bhargav
Albert ARIBAUD
parent
2e0c1c7d5c
commit
51100cfcca
3 changed files with 324 additions and 0 deletions
95
arch/arm/include/asm/arch-armada100/spi.h
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95
arch/arm/include/asm/arch-armada100/spi.h
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@ -0,0 +1,95 @@
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/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __ARMADA100_SPI_H_
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#define __ARMADA100_SPI_H_
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#include <asm/arch/armada100.h>
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#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
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#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
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/*
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* SSP Serial Port Registers
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* refer Appendix A.26
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*/
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struct ssp_reg {
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u32 sscr0; /* SSP Control Register 0 - 0x000 */
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u32 sscr1; /* SSP Control Register 1 - 0x004 */
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u32 sssr; /* SSP Status Register - 0x008 */
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u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
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u32 ssdr; /* SSP Data Register - 0x010 */
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u32 pad1[5];
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u32 ssto; /* SSP Timeout Register - 0x028 */
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u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
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u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
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u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
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u32 sstss; /* SSP Timeslot Status Register - 0x038 */
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};
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#define DEFAULT_WORD_LEN 8
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#define SSP_FLUSH_NUM 0x2000
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#define RX_THRESH_DEF 8
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#define TX_THRESH_DEF 8
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#define TIMEOUT_DEF 1000
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#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
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#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
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#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
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#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
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setting */
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#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
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#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
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#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
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#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
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#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
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#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
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#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
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Interrupt enable */
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#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
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#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
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#define SSCR0_FRF 0x30 /* FRame Format (mask) */
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#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
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Peripheral Interface */
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#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
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Serial Protocol (SSP) */
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#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
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#define SSCR0_ECS (1 << 6) /* External clock select */
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#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
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Enable */
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#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
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#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
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#define SSSR_BSY (1 << 4) /* SSP Busy */
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#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
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#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
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#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
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#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
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#endif /* __ARMADA100_SPI_H_ */
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@ -27,6 +27,7 @@ LIB := $(obj)libspi.o
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COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
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COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
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COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o
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COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o
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COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
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COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
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COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
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COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
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228
drivers/spi/armada100_spi.c
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228
drivers/spi/armada100_spi.c
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@ -0,0 +1,228 @@
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/*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Based on SSP driver
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* Written-by: Lei Wen <leiwen@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/arch/spi.h>
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#include <asm/gpio.h>
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#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
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struct armd_spi_slave {
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struct spi_slave slave;
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struct ssp_reg *spi_reg;
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u32 cr0, cr1;
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u32 int_cr1;
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u32 clear_sr;
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const void *tx;
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void *rx;
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int gpio_cs_inverted;
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};
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static int spi_armd_write(struct armd_spi_slave *pss)
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{
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int wait_timeout = SSP_FLUSH_NUM;
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while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
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;
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if (!wait_timeout) {
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debug("%s: timeout error\n", __func__);
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return -1;
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}
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if (pss->tx != NULL) {
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writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
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++pss->tx;
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} else {
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writel(0, &pss->spi_reg->ssdr);
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}
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return 0;
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}
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static int spi_armd_read(struct armd_spi_slave *pss)
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{
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int wait_timeout = SSP_FLUSH_NUM;
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while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
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;
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if (!wait_timeout) {
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debug("%s: timeout error\n", __func__);
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return -1;
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}
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if (pss->rx != NULL) {
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*(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
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++pss->rx;
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} else {
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readl(&pss->spi_reg->ssdr);
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}
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return 0;
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}
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static int spi_armd_flush(struct armd_spi_slave *pss)
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{
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unsigned long limit = SSP_FLUSH_NUM;
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do {
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while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
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readl(&pss->spi_reg->ssdr);
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} while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
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writel(SSSR_ROR, &pss->spi_reg->sssr);
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return limit;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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gpio_set_value(slave->cs, pss->gpio_cs_inverted);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct armd_spi_slave *pss;
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pss = malloc(sizeof(*pss));
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if (!pss)
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return NULL;
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pss->slave.bus = bus;
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pss->slave.cs = cs;
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pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
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pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
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pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
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(SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
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pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
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pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
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| (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
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pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
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pss->clear_sr = SSSR_ROR | SSSR_TINT;
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pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
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gpio_set_value(cs, !pss->gpio_cs_inverted);
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return &pss->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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free(pss);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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if (spi_armd_flush(pss) == 0)
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return -1;
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct armd_spi_slave *pss = to_armd_spi_slave(slave);
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uint bytes = bitlen / 8;
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unsigned long limit;
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int ret = 0;
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if (bitlen == 0)
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goto done;
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/* we can only do 8 bit transfers */
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if (bitlen % 8) {
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flags |= SPI_XFER_END;
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goto done;
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}
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if (dout)
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pss->tx = dout;
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else
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pss->tx = NULL;
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if (din)
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pss->rx = din;
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else
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pss->rx = NULL;
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if (flags & SPI_XFER_BEGIN) {
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spi_cs_activate(slave);
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writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
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writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
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writel(pss->cr0, &pss->spi_reg->sscr0);
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}
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while (bytes--) {
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limit = SSP_FLUSH_NUM;
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ret = spi_armd_write(pss);
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if (ret)
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break;
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while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
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udelay(1);
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ret = spi_armd_read(pss);
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if (ret)
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break;
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}
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done:
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if (flags & SPI_XFER_END) {
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/* Stop SSP */
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writel(pss->clear_sr, &pss->spi_reg->sssr);
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clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
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writel(0, &pss->spi_reg->ssto);
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spi_cs_deactivate(slave);
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}
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return ret;
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}
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