Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi
- cadence-quadspi fixes (Apurva Nandan, Dhruva Gole) - CHIP_ERASE optimization (Marek Vasut) - fixups for s25fs512s (Takahiro Kuwano)
This commit is contained in:
Tom Rini
commit
50f64026f7
7 changed files with 231 additions and 44 deletions
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@ -669,6 +669,7 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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case SNOR_MFR_MICRON:
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/* Some Micron need WREN command; all will accept it */
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need_wren = true;
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fallthrough;
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case SNOR_MFR_ISSI:
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case SNOR_MFR_MACRONIX:
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case SNOR_MFR_WINBOND:
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@ -903,6 +904,30 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info)
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}
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#endif
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/**
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* spi_nor_erase_chip() - Erase the entire flash memory.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int spi_nor_erase_chip(struct spi_nor *nor)
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{
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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int ret;
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spi_nor_setup_op(nor, &op, nor->write_proto);
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ret = spi_mem_exec_op(nor->spi, &op);
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if (ret)
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return ret;
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return nor->mtd.size;
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}
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/*
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* Initiate the erasure of a single sector. Returns the number of bytes erased
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* on success, a negative error code on error.
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@ -974,7 +999,12 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
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if (ret < 0)
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goto erase_err;
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ret = spi_nor_erase_sector(nor, addr);
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if (len == mtd->size &&
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!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
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ret = spi_nor_erase_chip(nor);
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} else {
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ret = spi_nor_erase_sector(nor, addr);
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}
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if (ret < 0)
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goto erase_err;
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@ -3199,6 +3229,87 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
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/* Use ID byte 4 to distinguish S25FS256T and S25Hx-T */
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#define S25FS256T_ID4 (0x08)
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/* Number of dummy cycle for Read Any Register (RDAR) op. */
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#define S25FS_S_RDAR_DUMMY 8
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static int s25fs_s_quad_enable(struct spi_nor *nor)
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{
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return spansion_quad_enable_volatile(nor, 0, S25FS_S_RDAR_DUMMY);
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}
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static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr)
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{
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/* Support 8 x 4KB sectors at bottom */
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return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K);
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}
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static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,
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const struct spi_nor_flash_parameter *params)
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{
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int ret;
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u8 cfr3v;
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/* Bank Address Register is not supported */
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if (CONFIG_IS_ENABLED(SPI_FLASH_BAR))
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return -EOPNOTSUPP;
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/*
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* Read CR3V to check if uniform sector is selected. If not, assign an
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* erase hook that supports non-uniform erase.
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*/
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ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V,
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S25FS_S_RDAR_DUMMY, &cfr3v);
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if (ret)
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return ret;
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if (!(cfr3v & CFR3V_UNHYSA))
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nor->erase = s25fs_s_erase_non_uniform;
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return spi_nor_default_setup(nor, info, params);
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}
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static void s25fs_s_default_init(struct spi_nor *nor)
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{
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nor->setup = s25fs_s_setup;
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}
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static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor,
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const struct sfdp_parameter_header *header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/* The erase size is set to 4K from BFPT, but it's wrong. Fix it. */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = nor->info->sector_size;
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/* The S25FS-S chip family reports 512-byte pages in BFPT but
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* in reality the write buffer still wraps at the safe default
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* of 256 bytes. Overwrite the page size advertised by BFPT
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* to get the writes working.
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*/
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params->page_size = 256;
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return 0;
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}
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static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor,
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struct spi_nor_flash_parameter *params)
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{
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/* READ_1_1_2 is not supported */
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params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
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/* READ_1_1_4 is not supported */
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params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
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/* PP_1_1_4 is not supported */
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params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
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/* Use volatile register to enable quad */
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params->quad_enable = s25fs_s_quad_enable;
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}
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static struct spi_nor_fixups s25fs_s_fixups = {
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.default_init = s25fs_s_default_init,
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.post_bfpt = s25fs_s_post_bfpt_fixup,
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.post_sfdp = s25fs_s_post_sfdp_fixup,
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};
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static int s25_mdp_ready(struct spi_nor *nor)
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{
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u32 addr;
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@ -3897,6 +4008,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
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if (CONFIG_IS_ENABLED(SPI_FLASH_BAR) &&
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!strcmp(nor->info->name, "s25fl256l"))
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nor->fixups = &s25fl256l_fixups;
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/* For FS-S (family ID = 0x81) */
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if (JEDEC_MFR(nor->info) == SNOR_MFR_SPANSION && nor->info->id[5] == 0x81)
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nor->fixups = &s25fs_s_fixups;
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#endif
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#ifdef CONFIG_SPI_FLASH_MT35XU
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@ -312,13 +312,12 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
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* which is unsupported on some flash devices during register
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* reads, prefer STIG mode for such small reads.
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*/
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if (!op->addr.nbytes ||
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op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
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if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
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mode = CQSPI_STIG_READ;
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else
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mode = CQSPI_READ;
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} else {
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if (!op->addr.nbytes || !op->data.buf.out)
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if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
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mode = CQSPI_STIG_WRITE;
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else
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mode = CQSPI_WRITE;
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@ -362,8 +361,15 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
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{
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bool all_true, all_false;
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all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
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op->data.dtr;
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/*
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* op->dummy.dtr is required for converting nbytes into ncycles.
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* Also, don't check the dtr field of the op phase having zero nbytes.
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*/
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all_true = op->cmd.dtr &&
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(!op->addr.nbytes || op->addr.dtr) &&
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(!op->dummy.nbytes || op->dummy.dtr) &&
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(!op->data.nbytes || op->data.dtr);
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all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
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!op->data.dtr;
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@ -120,7 +120,16 @@ static int cadence_qspi_set_protocol(struct cadence_spi_priv *priv,
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{
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int ret;
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priv->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
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/*
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* For an op to be DTR, cmd phase along with every other non-empty
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* phase should have dtr field set to 1. If an op phase has zero
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* nbytes, ignore its dtr field; otherwise, check its dtr field.
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* Also, dummy checks not performed here Since supports_op()
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* already checks that all or none of the fields are DTR.
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*/
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priv->dtr = op->cmd.dtr &&
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(!op->addr.nbytes || op->addr.dtr) &&
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(!op->data.nbytes || op->data.dtr);
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ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
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if (ret < 0)
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@ -367,6 +376,9 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg)
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if (!cadence_qspi_wait_idle(reg_base))
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return -EIO;
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/* Flush the CMDCTRL reg after the execution */
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writel(0, reg_base + CQSPI_REG_CMDCTRL);
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return 0;
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}
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@ -453,11 +465,6 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
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unsigned int dummy_clk;
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u8 opcode;
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if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
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printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
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return -EINVAL;
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}
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if (priv->dtr)
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opcode = op->cmd.opcode >> 8;
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else
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@ -540,26 +547,12 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
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unsigned int reg = 0;
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unsigned int wr_data;
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unsigned int wr_len;
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unsigned int dummy_clk;
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unsigned int txlen = op->data.nbytes;
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const void *txbuf = op->data.buf.out;
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void *reg_base = priv->regbase;
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u32 addr;
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u8 opcode;
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/* Reorder address to SPI bus order if only transferring address */
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if (!txlen) {
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addr = cpu_to_be32(op->addr.val);
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if (op->addr.nbytes == 3)
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addr >>= 8;
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txbuf = &addr;
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txlen = op->addr.nbytes;
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}
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if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
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printf("QSPI: Invalid input arguments txlen %u\n", txlen);
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return -EINVAL;
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}
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if (priv->dtr)
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opcode = op->cmd.opcode >> 8;
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else
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@ -567,6 +560,27 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
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reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
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/* setup ADDR BIT field */
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if (op->addr.nbytes) {
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writel(op->addr.val, priv->regbase + CQSPI_REG_CMDADDRESS);
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/*
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* address bytes are zero indexed
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*/
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reg |= (((op->addr.nbytes - 1) &
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CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) <<
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CQSPI_REG_CMDCTRL_ADD_BYTES_LSB);
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reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
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}
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/* Set up dummy cycles. */
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dummy_clk = cadence_qspi_calc_dummy(op, priv->dtr);
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if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
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return -EOPNOTSUPP;
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if (dummy_clk)
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reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
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<< CQSPI_REG_CMDCTRL_DUMMY_LSB;
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if (txlen) {
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/* writing data = yes */
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reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
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@ -11,6 +11,7 @@
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#include <linux/bitfield.h>
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#include <linux/log2.h>
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#include <linux/iopoll.h>
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#include <power/regulator.h>
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#define DW_SIZE 4
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#define CHUNK_SIZE 16
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@ -34,6 +35,34 @@
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#define UMA_CTS_RDYST BIT(24)
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#define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8)
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/* Direct Write Configuration Register */
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#define DWR_CFG_WBURST_MASK GENMASK(25, 24)
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#define DWR_CFG_ADDSIZ_MASK GENMASK(17, 16)
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#define DWR_CFG_ABPCK_MASK GENMASK(11, 10)
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#define DRW_CFG_DBPCK_MASK GENMASK(9, 8)
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#define DRW_CFG_WRCMD 2
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enum {
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DWR_WBURST_1_BYTE,
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DWR_WBURST_16_BYTE = 3,
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};
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enum {
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DWR_ADDSIZ_24_BIT,
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DWR_ADDSIZ_32_BIT,
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};
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enum {
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DWR_ABPCK_BIT_PER_CLK,
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DWR_ABPCK_2_BIT_PER_CLK,
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DWR_ABPCK_4_BIT_PER_CLK,
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};
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enum {
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DWR_DBPCK_BIT_PER_CLK,
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DWR_DBPCK_2_BIT_PER_CLK,
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DWR_DBPCK_4_BIT_PER_CLK,
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};
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struct npcm_fiu_regs {
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unsigned int drd_cfg;
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unsigned int dwr_cfg;
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@ -67,19 +96,10 @@ struct npcm_fiu_regs {
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struct npcm_fiu_priv {
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struct npcm_fiu_regs *regs;
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struct clk clk;
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};
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static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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int ret;
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debug("%s: set speed %u\n", bus->name, speed);
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ret = clk_set_rate(&priv->clk, speed);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -349,13 +369,38 @@ static int npcm_fiu_exec_op(struct spi_slave *slave,
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static int npcm_fiu_spi_probe(struct udevice *bus)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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int ret;
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struct udevice *vqspi_supply;
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int vqspi_uv;
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priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus);
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ret = clk_get_by_index(bus, 0, &priv->clk);
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if (ret < 0)
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return ret;
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if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
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device_get_supply_regulator(bus, "vqspi-supply", &vqspi_supply);
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vqspi_uv = dev_read_u32_default(bus, "vqspi-microvolt", 0);
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/* Set IO voltage */
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if (vqspi_supply && vqspi_uv)
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regulator_set_value(vqspi_supply, vqspi_uv);
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}
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return 0;
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}
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static int npcm_fiu_spi_bind(struct udevice *bus)
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{
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struct npcm_fiu_regs *regs;
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if (dev_read_bool(bus, "nuvoton,spix-mode")) {
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regs = dev_read_addr_ptr(bus);
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if (!regs)
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return -EINVAL;
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/* Setup direct write cfg for SPIX */
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writel(FIELD_PREP(DWR_CFG_WBURST_MASK, DWR_WBURST_16_BYTE) |
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FIELD_PREP(DWR_CFG_ADDSIZ_MASK, DWR_ADDSIZ_24_BIT) |
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FIELD_PREP(DWR_CFG_ABPCK_MASK, DWR_ABPCK_4_BIT_PER_CLK) |
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FIELD_PREP(DRW_CFG_DBPCK_MASK, DWR_DBPCK_4_BIT_PER_CLK) |
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DRW_CFG_WRCMD, ®s->dwr_cfg);
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}
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return 0;
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}
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@ -384,4 +429,5 @@ U_BOOT_DRIVER(npcm_fiu_spi) = {
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.ops = &npcm_fiu_spi_ops,
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.priv_auto = sizeof(struct npcm_fiu_priv),
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.probe = npcm_fiu_spi_probe,
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.bind = npcm_fiu_spi_bind,
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};
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|
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@ -181,8 +181,12 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave,
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if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2)
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return false;
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if (op->data.dir != SPI_MEM_NO_DATA &&
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op->dummy.buswidth == 8 && op->data.nbytes % 2)
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/*
|
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* Transactions of odd length do not make sense for 8D-8D-8D mode
|
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* because a byte is transferred in just half a cycle.
|
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*/
|
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if (op->data.dir != SPI_MEM_NO_DATA && op->data.dir != SPI_MEM_DATA_IN &&
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op->data.buswidth == 8 && op->data.nbytes % 2)
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return false;
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return spi_mem_check_buswidth(slave, op);
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|
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|
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@ -556,7 +556,7 @@ static bool f_ospi_supports_op(struct spi_slave *slave,
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if (!f_ospi_supports_op_width(op))
|
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return false;
|
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return true;
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return spi_mem_default_supports_op(slave, op);
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||||
}
|
||||
|
||||
static int f_ospi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
|
|||
struct udevice *bus = dev->parent;
|
||||
struct synquacer_spi_priv *priv = dev_get_priv(bus);
|
||||
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
|
||||
u32 val, div, bus_width;
|
||||
u32 val, div, bus_width = 1;
|
||||
int rwflag;
|
||||
|
||||
rwflag = (rx ? 1 : 0) | (tx ? 2 : 0);
|
||||
|
|
@ -211,6 +211,8 @@ static void synquacer_spi_config(struct udevice *dev, void *rx, const void *tx)
|
|||
bus_width = 4;
|
||||
else if (priv->mode & SPI_TX_OCTAL)
|
||||
bus_width = 8;
|
||||
else
|
||||
log_warning("SPI mode not configured, setting to byte mode\n");
|
||||
|
||||
div = DIV_ROUND_UP(125000000, priv->speed);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue