imx: add i.MX8MQ SoC Revision and is_mx8m helper
Add i.MX8MQ SoC Revision Add is_mx8m helper The 7ULP is a dummy number, so use 0xEx. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
parent
d7cb10a05f
commit
4fdffb9856
2 changed files with 5 additions and 2 deletions
|
@ -25,12 +25,14 @@
|
|||
#define MXC_CPU_MX6QP 0x69
|
||||
#define MXC_CPU_MX7S 0x71 /* dummy ID */
|
||||
#define MXC_CPU_MX7D 0x72
|
||||
#define MXC_CPU_MX7ULP 0x81 /* Temporally hard code */
|
||||
#define MXC_CPU_MX8MQ 0x82
|
||||
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
|
||||
#define MXC_CPU_VF610 0xF6 /* dummy ID */
|
||||
|
||||
#define MXC_SOC_MX6 0x60
|
||||
#define MXC_SOC_MX7 0x70
|
||||
#define MXC_SOC_MX7ULP 0x80 /* dummy */
|
||||
#define MXC_SOC_MX8M 0x80
|
||||
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define CHIP_REV_1_1 0x11
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
|
||||
#define is_mx6() (is_soc_type(MXC_SOC_MX6))
|
||||
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
|
||||
#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
|
||||
|
||||
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
|
||||
#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
|
||||
|
|
Loading…
Reference in a new issue