powerpc/T104xD4RDB: Add T104xD4RDB boards support
T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
T1040D4RDB is re-designed T1040RDB board with following changes :
- Support of DDR4 memory
- Support of 0x66 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
- Support of QE-TDM
Similarily T1042D4RDB is a Freescale reference board that hosts the T1040
SoC. T1042D4RDB is re-designed T1042RDB board with following changes :
- Support of DDR4 memory
- Support for 0x86 serdes protocol which can support following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
- Support of DIU
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Priyanka Jain
York Sun
parent
26473945ad
commit
4b6067ae9d
19 changed files with 284 additions and 16 deletions
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@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h
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F: configs/T1040RDB_defconfig
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F: configs/T1040RDB_NAND_defconfig
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F: configs/T1040RDB_SPIFLASH_defconfig
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F: configs/T1040D4RDB_defconfig
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F: configs/T1040D4RDB_NAND_defconfig
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F: configs/T1040D4RDB_SPIFLASH_defconfig
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F: configs/T1042RDB_defconfig
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F: configs/T1042D4RDB_defconfig
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F: configs/T1042D4RDB_NAND_defconfig
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F: configs/T1042D4RDB_SPIFLASH_defconfig
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F: configs/T1042RDB_PI_defconfig
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F: configs/T1042RDB_PI_NAND_defconfig
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F: configs/T1042RDB_PI_SPIFLASH_defconfig
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@ -15,6 +21,8 @@ T1040RDB_SDCARD BOARD
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#M: -
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S: Maintained
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F: configs/T1040RDB_SDCARD_defconfig
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F: configs/T1040D4RDB_SDCARD_defconfig
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F: configs/T1042D4RDB_SDCARD_defconfig
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F: configs/T1042RDB_PI_SDCARD_defconfig
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T1040RDB_SECURE_BOOT BOARD
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@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
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(a personality of T1040 SoC). The board is similar to T1040RDB but is
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designed specially with low power features targeted for Printing Image Market.
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The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
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The board is re-designed T1040RDB board with following changes :
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- Support of DDR4 memory and some enhancements
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The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
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The board is re-designed T1040RDB board with following changes :
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- Support of DDR4 memory
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- Support for 0x86 serdes protocol which can support following interfaces
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- 2 RGMII's on DTSEC4, DTSEC5
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- 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
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Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
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-------------------------------------------------------------------------
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Board Si Protocol Targeted Market
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@ -19,6 +30,8 @@ Board Si Protocol Targeted Market
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T1040RDB T1040 0x66 Networking
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T1040RDB T1042 0x86 Networking
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T1042RDB_PI T1042 0x06 Printing & Imaging
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T1040D4RDB T1040 0x66 Networking
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T1042D4RDB T1042 0x86 Networking
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T1040 SoC Overview
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@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features:
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T1040 SoC Personalities
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-------------------------
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T1022 Personality:
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T1022 is a reduced personality of T1040 with less core/clusters.
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@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB
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Please note QE Firmware is only valid for T1040RDB
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Switch Settings: (ON is 0, OFF is 1)
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===============
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Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
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==========================================================
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NOR boot SW setting:
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SW1: 00010011
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SW2: 10111011
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SW3: 11100001
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NAND boot SW setting:
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SW1: 10001000
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SW2: 00111011
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@ -284,3 +301,67 @@ SD boot SW setting:
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SW1: 00100000
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SW2: 00111011
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SW3: 11100001
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Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
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=============================================================
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NOR boot SW setting:
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SW1: 00010011
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SW2: 10111001
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SW3: 11100001
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NAND boot SW setting:
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SW1: 10001000
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SW2: 00111001
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SW3: 11110001
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SPI boot SW setting:
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SW1: 00100010
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SW2: 10111001
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SW3: 11100001
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SD boot SW setting:
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SW1: 00100000
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SW2: 00111001
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SW3: 11100001
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PBL-based image generation
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==========================
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Changes only the required register bit in in PBI commands.
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Provides reference code which might needs some
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modification as per requirement.
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example:
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By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
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which needs to be changed for SPI and SD.
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For SD-boot
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==============
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1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
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example:
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RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
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Change
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66000002 40000002 ec027000 01000000
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to
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66000002 40000002 6c027000 01000000
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2. SD does not support flush so remove flush from pbl, make changes in
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tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
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with 0x091380c0
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For SPI-boot
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==============
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1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
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example:
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RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
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Change
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66000002 40000002 ec027000 01000000
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to
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66000002 40000002 5c027000 01000000
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2. SPI does not support flush so remove flush from pbl, make changes in
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tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
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with 0x091380c0
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@ -69,7 +69,11 @@ static void cpld_dump_regs(void)
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printf("int_status = 0x%02x\n", CPLD_READ(int_status));
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printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
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printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
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#if defined(CONFIG_T104XD4RDB)
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printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
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#else
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printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
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#endif
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printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
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printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
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printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
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@ -21,7 +21,11 @@ struct cpld_data {
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u8 int_status; /* 0x12 - Interrupt status Register */
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u8 flash_ctl_status; /* 0x13 - Flash control and status register */
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u8 fan_ctl_status; /* 0x14 - Fan control and status register */
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#if defined(CONFIG_T104XD4RDB)
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u8 int_mask; /* 0x15 - Interrupt mask Register */
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#else
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u8 led_ctl_status; /* 0x15 - LED control and status register */
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#endif
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u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
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u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
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u8 boot_override; /* 0x18 - Boot override register */
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@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value)\
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cpld_write(offsetof(struct cpld_data, reg), value)
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#define MISC_CTL_SG_SEL 0x80
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#define MISC_CTL_AURORA_SEL 0x02
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@ -75,7 +75,11 @@ found:
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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#ifdef CONFIG_SYS_FSL_DDR4
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popts->half_strength_driver_enable = 1;
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#else
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popts->half_strength_driver_enable = 0;
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#endif
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/*
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* Write leveling override
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*/
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@ -91,8 +95,14 @@ found:
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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#ifdef CONFIG_SYS_FSL_DDR4
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
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#else
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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#endif
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}
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#if defined(CONFIG_DEEP_SLEEP)
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@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = {
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* num| hi| rank| clk| wrlvl | wrlvl
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* ranks| mhz| GB |adjst| start | ctl2
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*/
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#ifdef CONFIG_SYS_FSL_DDR4
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{2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a},
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#elif defined(CONFIG_SYS_FSL_DDR3)
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{2, 833, 4, 4, 6, 0x06060607, 0x08080807},
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{2, 833, 0, 4, 6, 0x06060607, 0x08080807},
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{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
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@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = {
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{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
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{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
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{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
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#else
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#error DDR type not defined
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#endif
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{}
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};
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#endif
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis)
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int idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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#ifdef CONFIG_T1040RDB
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#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
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case PHY_INTERFACE_MODE_SGMII:
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/* T1040RDB only supports SGMII on DTSEC3 */
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/* T1040RDB & T1040D4RDB only supports SGMII on
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* DTSEC3
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*/
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_SGMII1_PHY_ADDR);
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break;
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@ -59,6 +61,20 @@ int board_eth_init(bd_t *bis)
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_SGMII1_PHY_ADDR);
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break;
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#endif
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#ifdef CONFIG_T1042D4RDB
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case PHY_INTERFACE_MODE_SGMII:
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/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
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* & DTSEC3
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*/
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if (FM1_DTSEC1 == i)
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phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
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if (FM1_DTSEC2 == i)
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phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
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if (FM1_DTSEC3 == i)
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phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
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fm_info_set_phy_address(i, phy_addr);
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break;
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#endif
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case PHY_INTERFACE_MODE_RGMII:
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if (FM1_DTSEC4 == i)
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7
board/freescale/t104xrdb/t1040d4_rcw.cfg
Normal file
7
board/freescale/t104xrdb/t1040d4_rcw.cfg
Normal file
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@ -0,0 +1,7 @@
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#PBL preamble and RCW header
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aa55aa55 010e0100
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# serdes protocol 0x66
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0c18000e 0e000000 00000000 00000000
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66000002 40000002 ec027000 01000000
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00000000 00000000 00000000 00030810
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00000000 0342580f 00000000 00000000
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7
board/freescale/t104xrdb/t1042d4_rcw.cfg
Normal file
7
board/freescale/t104xrdb/t1042d4_rcw.cfg
Normal file
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@ -0,0 +1,7 @@
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#PBL preamble and RCW header
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aa55aa55 010e0100
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# serdes protocol 0x86
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0c18000e 0e000000 00000000 00000000
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86000002 40000002 ec027000 01000000
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00000000 00000000 00000000 00030810
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00000000 0342500f 00000000 00000000
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@ -28,7 +28,11 @@ int checkboard(void)
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struct cpu_type *cpu = gd->arch.cpu;
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u8 sw;
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#ifdef CONFIG_T104XD4RDB
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printf("Board: %sD4RDB\n", cpu->name);
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#else
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printf("Board: %sRDB\n", cpu->name);
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#endif
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printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_ver));
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@ -91,6 +95,34 @@ int board_early_init_r(void)
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int misc_init_r(void)
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{
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_s1;
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srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
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printf("SERDES Reference : 0x%X\n", srds_s1);
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/* select SGMII*/
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if (srds_s1 == 0x86)
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CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
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MISC_CTL_SG_SEL);
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/* select SGMII and Aurora*/
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if (srds_s1 == 0x8E)
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CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
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MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
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#if defined(CONFIG_T1040D4RDB)
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/* Mask all CPLD interrupt sources, except QSGMII interrupts */
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if (CPLD_READ(sw_ver) < 0x03) {
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debug("CPLD SW version 0x%02x doesn't support int_mask\n",
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CPLD_READ(sw_ver));
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} else {
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CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
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~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
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}
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#endif
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return 0;
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}
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6
configs/T1040D4RDB_NAND_defconfig
Normal file
6
configs/T1040D4RDB_NAND_defconfig
Normal file
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@ -0,0 +1,6 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
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CONFIG_PPC=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_T104XRDB=y
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CONFIG_SPI_FLASH=y
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6
configs/T1040D4RDB_SDCARD_defconfig
Normal file
6
configs/T1040D4RDB_SDCARD_defconfig
Normal file
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@ -0,0 +1,6 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
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CONFIG_PPC=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_T104XRDB=y
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CONFIG_SPI_FLASH=y
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6
configs/T1040D4RDB_SPIFLASH_defconfig
Normal file
6
configs/T1040D4RDB_SPIFLASH_defconfig
Normal file
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@ -0,0 +1,6 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
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CONFIG_PPC=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_T104XRDB=y
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CONFIG_SPI_FLASH=y
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5
configs/T1040D4RDB_defconfig
Normal file
5
configs/T1040D4RDB_defconfig
Normal file
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@ -0,0 +1,5 @@
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
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CONFIG_PPC=y
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CONFIG_MPC85xx=y
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CONFIG_TARGET_T104XRDB=y
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CONFIG_SPI_FLASH=y
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6
configs/T1042D4RDB_NAND_defconfig
Normal file
6
configs/T1042D4RDB_NAND_defconfig
Normal file
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@ -0,0 +1,6 @@
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T104XRDB=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
6
configs/T1042D4RDB_SDCARD_defconfig
Normal file
6
configs/T1042D4RDB_SDCARD_defconfig
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T104XRDB=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
6
configs/T1042D4RDB_SPIFLASH_defconfig
Normal file
6
configs/T1042D4RDB_SPIFLASH_defconfig
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
CONFIG_SPL=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T104XRDB=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
5
configs/T1042D4RDB_defconfig
Normal file
5
configs/T1042D4RDB_defconfig
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
|
||||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T104XRDB=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
|
|
@ -29,6 +29,14 @@
|
|||
#ifdef CONFIG_T1042RDB
|
||||
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
|
||||
#endif
|
||||
#ifdef CONFIG_T1040D4RDB
|
||||
#define CONFIG_SYS_FSL_PBL_RCW \
|
||||
$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
|
||||
#endif
|
||||
#ifdef CONFIG_T1042D4RDB
|
||||
#define CONFIG_SYS_FSL_PBL_RCW \
|
||||
$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
|
||||
#define CONFIG_SPL_ENV_SUPPORT
|
||||
|
|
@ -220,7 +228,9 @@
|
|||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#ifndef CONFIG_SYS_FSL_DDR4
|
||||
#define CONFIG_SYS_FSL_DDR3
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x51
|
||||
|
|
@ -278,8 +288,23 @@
|
|||
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
|
||||
#define CPLD_LBMAP_RESET 0xFF
|
||||
#define CPLD_LBMAP_SHIFT 0x03
|
||||
#ifdef CONFIG_T1042RDB_PI
|
||||
|
||||
#if defined(CONFIG_T1042RDB_PI)
|
||||
#define CPLD_DIU_SEL_DFP 0x80
|
||||
#elif defined(CONFIG_T1042D4RDB)
|
||||
#define CPLD_DIU_SEL_DFP 0xc0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_T1040D4RDB)
|
||||
#define CPLD_INT_MASK_ALL 0xFF
|
||||
#define CPLD_INT_MASK_THERM 0x80
|
||||
#define CPLD_INT_MASK_DVI_DFP 0x40
|
||||
#define CPLD_INT_MASK_QSGMII1 0x20
|
||||
#define CPLD_INT_MASK_QSGMII2 0x10
|
||||
#define CPLD_INT_MASK_SGMI1 0x08
|
||||
#define CPLD_INT_MASK_SGMI2 0x04
|
||||
#define CPLD_INT_MASK_TDMR1 0x02
|
||||
#define CPLD_INT_MASK_TDMR2 0x01
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
|
||||
|
|
@ -447,7 +472,7 @@
|
|||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#ifdef CONFIG_T1042RDB_PI
|
||||
#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
|
||||
/* Video */
|
||||
#define CONFIG_FSL_DIU_FB
|
||||
|
||||
|
|
@ -492,11 +517,11 @@
|
|||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR 0x70
|
||||
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
|
||||
#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_T1042RDB_PI
|
||||
#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
|
||||
/* LDI/DVI Encoder for display */
|
||||
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
|
||||
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
|
||||
|
|
@ -664,7 +689,7 @@
|
|||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
||||
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
|
||||
#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
|
||||
#define CONFIG_QE
|
||||
#define CONFIG_U_QE
|
||||
#endif
|
||||
|
|
@ -693,7 +718,7 @@
|
|||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
|
||||
#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_QE_FW_ADDR 0x130000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
|
|
@ -718,17 +743,32 @@
|
|||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
|
||||
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
|
||||
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
|
||||
#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
|
||||
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
|
||||
#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
|
||||
#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_T104XD4RDB
|
||||
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
|
||||
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
|
||||
#else
|
||||
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
|
||||
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
|
||||
#endif
|
||||
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
|
||||
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
|
||||
|
||||
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
|
||||
#ifdef CONFIG_T1040RDB
|
||||
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
|
||||
#define CONFIG_VSC9953
|
||||
#define CONFIG_VSC9953_CMD
|
||||
#ifdef CONFIG_T1040RDB
|
||||
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
|
||||
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
|
||||
#else
|
||||
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
|
||||
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
|
|
@ -836,6 +876,10 @@
|
|||
#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
|
||||
#elif defined(CONFIG_T1042RDB)
|
||||
#define FDTFILE "t1042rdb/t1042rdb.dtb"
|
||||
#elif defined(CONFIG_T1040D4RDB)
|
||||
#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
|
||||
#elif defined(CONFIG_T1042D4RDB)
|
||||
#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_DIU_FB
|
||||
|
|
|
|||
Loading…
Reference in a new issue