- mvebu: a38x: Define supported UART baudrates (Pali)
- kwbimage: Misc improvements (Pali)
- espressobin/turris_mox/turris_omnia: Enable some more devices
  like SATA via PCIe, SATA & NVMe (Pali)
- a37xx: Remove unused CONFIG_DEBUG_UART_SHIFT options (Pali)
- turris_omnia: Disable MCU watchdog in SPL when booting over
  UART (Marek)
- kwbimage: Fix some Coverity issue (Heinrich)
This commit is contained in:
Tom Rini 2021-09-01 07:52:08 -04:00
commit 48cf96fbdf
12 changed files with 138 additions and 101 deletions

View file

@ -14,6 +14,7 @@
#include <asm/pl310.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/spl.h>
#include <sdhci.h>
#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
@ -80,6 +81,65 @@ int mvebu_soc_family(void)
return MVEBU_SOC_UNKNOWN;
}
u32 get_boot_device(void)
{
u32 val;
u32 boot_device;
/*
* First check, if UART boot-mode is active. This can only
* be done, via the bootrom error register. Here the
* MSB marks if the UART mode is active.
*/
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
if (boot_device == BOOTROM_ERR_MODE_UART)
return BOOT_DEVICE_UART;
#ifdef CONFIG_ARMADA_38X
/*
* If the bootrom error code contains any other than zeros it's an
* error condition and the bootROM has fallen back to UART boot
*/
boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
if (boot_device)
return BOOT_DEVICE_UART;
#endif
/*
* Now check the SAR register for the strapped boot-device
*/
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
#ifdef BOOT_FROM_NAND
case BOOT_FROM_NAND:
return BOOT_DEVICE_NAND;
#endif
#ifdef BOOT_FROM_MMC
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
return BOOT_DEVICE_MMC1;
#endif
case BOOT_FROM_UART:
#ifdef BOOT_FROM_UART_ALT
case BOOT_FROM_UART_ALT:
#endif
return BOOT_DEVICE_UART;
#ifdef BOOT_FROM_SATA
case BOOT_FROM_SATA:
case BOOT_FROM_SATA_ALT:
return BOOT_DEVICE_SATA;
#endif
case BOOT_FROM_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_BOOTROM;
};
}
#if defined(CONFIG_DISPLAY_CPUINFO)
#if defined(CONFIG_ARMADA_375)

View file

@ -148,6 +148,8 @@ void __noreturn return_to_bootrom(void);
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
#endif
u32 get_boot_device(void);
void get_sar_freq(struct sar_freq_modes *sar_freq);
/*

View file

@ -189,7 +189,7 @@
#define BOOT_FROM_SPI 0x3
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#else
#elif defined(CONFIG_ARMADA_XP)
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
#define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))

View file

@ -171,74 +171,6 @@ int spl_parse_board_header(struct spl_image_info *spl_image,
return 0;
}
static u32 get_boot_device(void)
{
u32 val;
u32 boot_device;
/*
* First check, if UART boot-mode is active. This can only
* be done, via the bootrom error register. Here the
* MSB marks if the UART mode is active.
*/
val = readl(CONFIG_BOOTROM_ERR_REG);
boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS;
debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device);
if (boot_device == BOOTROM_ERR_MODE_UART)
return BOOT_DEVICE_UART;
#ifdef CONFIG_ARMADA_38X
/*
* If the bootrom error code contains any other than zeros it's an
* error condition and the bootROM has fallen back to UART boot
*/
boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS;
if (boot_device)
return BOOT_DEVICE_UART;
#endif
/*
* Now check the SAR register for the strapped boot-device
*/
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device);
switch (boot_device) {
#ifdef BOOT_FROM_NAND
case BOOT_FROM_NAND:
return BOOT_DEVICE_NAND;
#endif
#ifdef BOOT_FROM_MMC
case BOOT_FROM_MMC:
case BOOT_FROM_MMC_ALT:
return BOOT_DEVICE_MMC1;
#endif
case BOOT_FROM_UART:
#ifdef BOOT_FROM_UART_ALT
case BOOT_FROM_UART_ALT:
#endif
return BOOT_DEVICE_UART;
#ifdef BOOT_FROM_SATA
case BOOT_FROM_SATA:
case BOOT_FROM_SATA_ALT:
return BOOT_DEVICE_SATA;
#endif
case BOOT_FROM_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_BOOTROM;
};
}
#else
static u32 get_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
#endif
u32 spl_boot_device(void)
{
u32 boot_device = get_boot_device();
@ -285,6 +217,15 @@ u32 spl_boot_device(void)
}
}
#else
u32 spl_boot_device(void)
{
return BOOT_DEVICE_BOOTROM;
}
#endif
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{

View file

@ -129,7 +129,6 @@ static int omnia_mcu_read(u8 cmd, void *buf, int len)
return dm_i2c_read(chip, cmd, buf, len);
}
#ifndef CONFIG_SPL_BUILD
static int omnia_mcu_write(u8 cmd, const void *buf, int len)
{
struct udevice *chip;
@ -158,7 +157,6 @@ static bool disable_mcu_watchdog(void)
return true;
}
#endif
static bool omnia_detect_sata(void)
{
@ -325,7 +323,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
return &board_topology_map_1g;
}
#ifndef CONFIG_SPL_BUILD
static int set_regdomain(void)
{
struct omnia_eeprom oep;
@ -394,7 +391,6 @@ static void handle_reset_button(void)
}
}
}
#endif
int board_early_init_f(void)
{
@ -423,24 +419,35 @@ int board_early_init_f(void)
return 0;
}
void spl_board_init(void)
{
/*
* If booting from UART, disable MCU watchdog in SPL, since uploading
* U-Boot proper can take too much time and trigger it.
*/
if (get_boot_device() == BOOT_DEVICE_UART)
disable_mcu_watchdog();
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
#ifndef CONFIG_SPL_BUILD
disable_mcu_watchdog();
#endif
return 0;
}
int board_late_init(void)
{
#ifndef CONFIG_SPL_BUILD
/*
* If not booting from UART, MCU watchdog was not disabled in SPL,
* disable it now.
*/
if (get_boot_device() != BOOT_DEVICE_UART)
disable_mcu_watchdog();
set_regdomain();
handle_reset_button();
#endif
pci_init();
return 0;

View file

@ -63,7 +63,6 @@ CONFIG_PHY=y
CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y

View file

@ -30,6 +30,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
@ -46,6 +47,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_AHCI_PCI=y
CONFIG_AHCI_MVEBU=y
CONFIG_CLK=y
CONFIG_CLK_MVEBU=y
@ -77,7 +79,6 @@ CONFIG_MVEBU_COMPHY_SUPPORT=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y

View file

@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-turris-mox"
CONFIG_DEBUG_UART_BASE=0xd0012000
CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_OF_BOARD_FIXUP=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@ -32,6 +33,7 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
@ -47,6 +49,8 @@ CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
@ -81,7 +85,8 @@ CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y

View file

@ -33,6 +33,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_I2C=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
@ -77,6 +78,7 @@ CONFIG_PHY_MARVELL=y
CONFIG_PHY_GIGE=y
CONFIG_MVNETA=y
CONFIG_MII=y
CONFIG_NVME=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
CONFIG_DM_RTC=y

View file

@ -79,7 +79,6 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_ARMADA_37XX=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_MVEBU_A3700_UART=y
CONFIG_MVEBU_A3700_SPI=y

View file

@ -39,6 +39,15 @@
#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE)
#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
9600, 19200, 38400, 57600, 115200, \
230400, 460800, 500000, 576000, \
921600, 1000000, 1152000, 1500000, \
2000000, 2500000, 3125000, 4000000, \
5150000 }
#endif
/* auto boot */
/*

View file

@ -5,8 +5,6 @@
*
* (C) Copyright 2013 Thomas Petazzoni
* <thomas.petazzoni@free-electrons.com>
*
* Not implemented: support for the register headers in v1 images
*/
#include "imagetool.h"
@ -59,13 +57,13 @@ struct hash_v1 {
};
struct boot_mode boot_modes[] = {
{ 0x4D, "i2c" },
{ 0x5A, "spi" },
{ 0x8B, "nand" },
{ 0x78, "sata" },
{ 0x9C, "pex" },
{ 0x69, "uart" },
{ 0xAE, "sdio" },
{ IBR_HDR_I2C_ID, "i2c" },
{ IBR_HDR_SPI_ID, "spi" },
{ IBR_HDR_NAND_ID, "nand" },
{ IBR_HDR_SATA_ID, "sata" },
{ IBR_HDR_PEX_ID, "pex" },
{ IBR_HDR_UART_ID, "uart" },
{ IBR_HDR_SDIO_ID, "sdio" },
{},
};
@ -75,10 +73,10 @@ struct nand_ecc_mode {
};
struct nand_ecc_mode nand_ecc_modes[] = {
{ 0x00, "default" },
{ 0x01, "hamming" },
{ 0x02, "rs" },
{ 0x03, "disabled" },
{ IBR_HDR_ECC_DEFAULT, "default" },
{ IBR_HDR_ECC_FORCED_HAMMING, "hamming" },
{ IBR_HDR_ECC_FORCED_RS, "rs" },
{ IBR_HDR_ECC_DISABLED, "disabled" },
{},
};
@ -832,6 +830,12 @@ static int kwb_dump_fuse_cmds(struct secure_hdr_v1 *sec_hdr)
if (!strcmp(e->name, "a38x")) {
FILE *out = fopen("kwb_fuses_a38x.txt", "w+");
if (!out) {
fprintf(stderr, "Couldn't open eFuse settings: '%s': %s\n",
"kwb_fuses_a38x.txt", strerror(errno));
return -ENOENT;
}
kwb_dump_fuse_cmds_38x(out, sec_hdr);
fclose(out);
goto done;
@ -1060,6 +1064,11 @@ int export_pub_kak_hash(RSA *kak, struct secure_hdr_v1 *secure_hdr)
int res;
hashf = fopen("pub_kak_hash.txt", "w");
if (!hashf) {
fprintf(stderr, "Couldn't open hash file: '%s': %s\n",
"pub_kak_hash.txt", strerror(errno));
return 1;
}
res = kwb_export_pubkey(kak, &secure_hdr->kak, hashf, "KAK");
@ -1076,7 +1085,7 @@ int kwb_sign_csk_with_kak(struct image_tool_params *params,
int csk_idx = image_get_csk_index();
struct sig_v1 tmp_sig;
if (csk_idx >= 16) {
if (csk_idx < 0 || csk_idx > 15) {
fprintf(stderr, "Invalid CSK index %d\n", csk_idx);
return 1;
}
@ -1670,6 +1679,9 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
if (mhdr->ext & 0x1) {
struct ext_hdr_v0 *ext_hdr;
if (header_size + sizeof(*ext_hdr) > image_size)
return -FDT_ERR_BADSTRUCTURE;
ext_hdr = (struct ext_hdr_v0 *)
(ptr + sizeof(struct main_hdr_v0));
checksum = image_checksum8(ext_hdr,
@ -1678,9 +1690,7 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
if (checksum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
}
if (image_version((void *)ptr) == 1) {
} else if (image_version((void *)ptr) == 1) {
struct main_hdr_v1 *mhdr = (struct main_hdr_v1 *)ptr;
uint32_t offset;
uint32_t size;
@ -1744,12 +1754,14 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size,
return -FDT_ERR_BADSTRUCTURE;
size = le32_to_cpu(mhdr->blocksize);
if (offset + size > image_size || size % 4 != 0)
if (size < 4 || offset + size > image_size || size % 4 != 0)
return -FDT_ERR_BADSTRUCTURE;
if (image_checksum32(ptr + offset, size - 4) !=
*(uint32_t *)(ptr + offset + size - 4))
return -FDT_ERR_BADSTRUCTURE;
} else {
return -FDT_ERR_BADSTRUCTURE;
}
return 0;