* Fix flash parameters passed to Linux for PPChameleon board
* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
This commit is contained in:
wdenk
parent
f832d8a143
commit
46a414dc12
6 changed files with 65 additions and 25 deletions
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@ -2,6 +2,10 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Fix flash parameters passed to Linux for PPChameleon board
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* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
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* Patch by Paul Ruhland, 10 Jun 2004:
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fix support for Logic SDK-LH7A404 board and clean up the
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LH7A404 register macros.
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@ -96,11 +96,15 @@ int misc_init_f (void)
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return 0; /* dummy implementation */
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}
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extern flash_info_t flash_info[]; /* info for FLASH chips */
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int misc_init_r (void)
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{
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#if 0 /* test-only */
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DECLARE_GLOBAL_DATA_PTR;
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/* adjust flash start and size as well as the offset */
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gd->bd->bi_flashstart = 0 - flash_info[0].size;
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gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
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#if 0
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volatile unsigned short *fpga_mode =
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(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
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@ -192,8 +196,6 @@ int misc_init_r (void)
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*duart0_mcr = 0x08;
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*duart1_mcr = 0x08;
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#endif
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#endif
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return (0);
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}
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@ -44,10 +44,10 @@ unsigned long flash_init (void)
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#ifdef __DEBUG_START_FROM_SRAM__
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return CFG_DUMMY_FLASH_SIZE;
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#else
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unsigned long size_b0;
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unsigned long size;
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int i;
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uint pbcr;
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unsigned long base_b0;
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unsigned long base;
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int size_val = 0;
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/* Init: no FLASHes known */
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@ -57,22 +57,22 @@ unsigned long flash_init (void)
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/* Static FLASH Bank configuration here - FIXME XXX */
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size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
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size_b0, size_b0<<20);
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size, size<<20);
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}
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/* Setup offsets */
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flash_get_offsets (-size_b0, &flash_info[0]);
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flash_get_offsets (-size, &flash_info[0]);
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/* Re-do sizing to get full correct info */
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mtdcr(ebccfga, pb0cr);
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pbcr = mfdcr(ebccfgd);
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mtdcr(ebccfga, pb0cr);
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base_b0 = -size_b0;
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switch (size_b0) {
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base = -size;
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switch (size) {
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case 1 << 20:
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size_val = 0;
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break;
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@ -89,7 +89,7 @@ unsigned long flash_init (void)
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size_val = 4;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
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pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
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mtdcr(ebccfgd, pbcr);
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/* Monitor protection ON by default */
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@ -98,8 +98,8 @@ unsigned long flash_init (void)
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0xffffffff,
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&flash_info[0]);
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flash_info[0].size = size_b0;
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flash_info[0].size = size;
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return (size_b0);
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return (size);
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#endif
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}
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@ -414,6 +414,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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out32 (EMAC_IAL + hw_p->hw_addr, reg);
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switch (devnum) {
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#if defined(CONFIG_NET_MULTI)
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case 1:
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/* setup MAL tx & rx channel pointers */
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/* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
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@ -422,6 +423,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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/* set RX buffer size */
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mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
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break;
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#endif
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case 0:
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default:
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/* setup MAL tx & rx channel pointers */
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@ -121,11 +121,7 @@
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x40000000
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#ifdef DEBUG
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
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#endif
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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@ -135,11 +131,12 @@
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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@ -148,6 +145,10 @@
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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@ -260,9 +261,11 @@
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
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OR_SCY_5_CLK | OR_EHTR)
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/*
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* FLASH timing:
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*/
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#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
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OR_SCY_3_CLK | OR_EHTR | OR_BI)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
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@ -291,12 +294,42 @@
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/*
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* Memory Periodic Timer Prescaler
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*
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* The Divider for PTA (refresh timer) configuration is based on an
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* example SDRAM configuration (64 MBit, one bank). The adjustment to
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* the number of chip selects (NCS) and the actually needed refresh
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* rate is done by setting MPTPR.
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*
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* PTA is calculated from
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* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
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*
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* gclk CPU clock (not bus clock!)
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* Trefresh Refresh cycle * 4 (four word bursts used)
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*
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* 4096 Rows from SDRAM example configuration
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* 1000 factor s -> ms
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* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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* --------------------------------------------
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* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
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*
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* 50 MHz => 50.000.000 / Divider = 98
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* 66 Mhz => 66.000.000 / Divider = 129
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* 80 Mhz => 80.000.000 / Divider = 156
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*/
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/* periodic timer for refresh */
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#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
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#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
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#define CFG_MAMR_PTA 98
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
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/*
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* For 16 MBit, refresh rates could be 31.3 us
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* (= 64 ms / 2K = 125 / quad bursts).
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* For a simpler initialization, 15.6 us is used instead.
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*
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* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
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* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
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*/
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
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@ -310,7 +310,6 @@ void start_armboot (void)
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if (getenv ("ethaddr")) {
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smc_set_mac_addr(gd->bd->bi_enetaddr);
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}
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eth_init(gd->bd);
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#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
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/* Initialize from environment */
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