ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3 (commit 457391b0380335d5e9a5babdec90ac53928b23b4) Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Ralph Siemsen
Marek Vasut
parent
2d67a095dc
commit
4647a84b6c
2 changed files with 626 additions and 0 deletions
477
arch/arm/dts/r9a06g032.dtsi
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477
arch/arm/dts/r9a06g032.dtsi
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@ -0,0 +1,477 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
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*
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* Copyright (C) 2018 Renesas Electronics Europe Limited
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a06g032-sysctrl.h>
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/ {
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compatible = "renesas,r9a06g032";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0>;
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clocks = <&sysctrl R9A06G032_CLK_A7MP>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <1>;
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clocks = <&sysctrl R9A06G032_CLK_A7MP>;
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enable-method = "renesas,r9a06g032-smp";
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cpu-release-addr = <0 0x4000c204>;
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};
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};
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ext_jtag_clk: extjtagclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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ext_mclk: extmclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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};
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ext_rgmii_ref: extrgmiiref {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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ext_rtc_clk: extrtcclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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rtc0: rtc@40006000 {
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compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
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reg = <0x40006000 0x1000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "alarm", "timer", "pps";
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clocks = <&sysctrl R9A06G032_HCLK_RTC>;
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clock-names = "hclk";
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power-domains = <&sysctrl>;
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status = "disabled";
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};
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wdt0: watchdog@40008000 {
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compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
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reg = <0x40008000 0x1000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
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clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
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status = "disabled";
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};
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wdt1: watchdog@40009000 {
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compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
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reg = <0x40009000 0x1000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
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clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
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status = "disabled";
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};
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sysctrl: system-controller@4000c000 {
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compatible = "renesas,r9a06g032-sysctrl";
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reg = <0x4000c000 0x1000>;
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status = "okay";
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#clock-cells = <1>;
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#power-domain-cells = <0>;
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clocks = <&ext_mclk>, <&ext_rtc_clk>,
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<&ext_jtag_clk>, <&ext_rgmii_ref>;
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clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
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#address-cells = <1>;
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#size-cells = <1>;
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dmamux: dma-router@a0 {
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compatible = "renesas,rzn1-dmamux";
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reg = <0xa0 4>;
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#dma-cells = <6>;
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dma-requests = <32>;
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dma-masters = <&dma0 &dma1>;
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};
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};
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udc: usb@4001e000 {
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compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
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reg = <0x4001e000 0x2000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysctrl R9A06G032_HCLK_USBF>,
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<&sysctrl R9A06G032_HCLK_USBPM>;
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clock-names = "hclkf", "hclkpm";
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power-domains = <&sysctrl>;
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status = "disabled";
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};
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pci_usb: pci@40030000 {
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compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
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device_type = "pci";
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clocks = <&sysctrl R9A06G032_HCLK_USBH>,
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<&sysctrl R9A06G032_HCLK_USBPM>,
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<&sysctrl R9A06G032_CLK_PCI_USB>;
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clock-names = "hclkh", "hclkpm", "pciclk";
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power-domains = <&sysctrl>;
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reg = <0x40030000 0xc00>,
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<0x40020000 0x1100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
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/* Should map all possible DDR as inbound ranges, but
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* the IP only supports a 256MB, 512MB, or 1GB window.
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* flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
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*/
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dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
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0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
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0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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usb@1,0 {
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reg = <0x800 0 0 0 0>;
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phys = <&usbphy>;
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phy-names = "usb";
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};
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usb@2,0 {
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reg = <0x1000 0 0 0 0>;
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phys = <&usbphy>;
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phy-names = "usb";
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};
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};
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uart0: serial@40060000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
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reg = <0x40060000 0x400>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@40061000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
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reg = <0x40061000 0x400>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@40062000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
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reg = <0x40062000 0x400>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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status = "disabled";
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};
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uart3: serial@50000000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
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reg = <0x50000000 0x400>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart4: serial@50001000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
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reg = <0x50001000 0x400>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart5: serial@50002000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
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reg = <0x50002000 0x400>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart6: serial@50003000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
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reg = <0x50003000 0x400>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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uart7: serial@50004000 {
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compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
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reg = <0x50004000 0x400>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
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clock-names = "baudclk", "apb_pclk";
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dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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pinctrl: pinctrl@40067000 {
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compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
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reg = <0x40067000 0x1000>, <0x51000000 0x480>;
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clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
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clock-names = "bus";
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status = "okay";
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};
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nand_controller: nand-controller@40102000 {
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compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
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reg = <0x40102000 0x2000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
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clock-names = "hclk", "eclk";
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power-domains = <&sysctrl>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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dma0: dma-controller@40104000 {
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compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
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reg = <0x40104000 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "hclk";
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clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
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dma-channels = <8>;
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dma-requests = <16>;
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dma-masters = <1>;
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#dma-cells = <3>;
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block_size = <0xfff>;
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data-width = <8>;
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};
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dma1: dma-controller@40105000 {
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compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
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reg = <0x40105000 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "hclk";
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clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
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dma-channels = <8>;
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dma-requests = <16>;
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dma-masters = <1>;
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#dma-cells = <3>;
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block_size = <0xfff>;
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data-width = <8>;
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};
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gmac2: ethernet@44002000 {
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compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
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reg = <0x44002000 0x2000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
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clock-names = "stmmaceth";
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power-domains = <&sysctrl>;
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snps,multicast-filter-bins = <256>;
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snps,perfect-filter-entries = <128>;
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tx-fifo-depth = <2048>;
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rx-fifo-depth = <4096>;
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status = "disabled";
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};
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eth_miic: eth-miic@44030000 {
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compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44030000 0x10000>;
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clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
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<&sysctrl R9A06G032_CLK_RGMII_REF>,
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<&sysctrl R9A06G032_CLK_RMII_REF>,
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<&sysctrl R9A06G032_HCLK_SWITCH_RG>;
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clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
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power-domains = <&sysctrl>;
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status = "disabled";
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mii_conv1: mii-conv@1 {
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reg = <1>;
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status = "disabled";
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};
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mii_conv2: mii-conv@2 {
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reg = <2>;
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status = "disabled";
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};
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mii_conv3: mii-conv@3 {
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reg = <3>;
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status = "disabled";
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};
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mii_conv4: mii-conv@4 {
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reg = <4>;
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status = "disabled";
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};
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mii_conv5: mii-conv@5 {
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reg = <5>;
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status = "disabled";
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};
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};
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switch: switch@44050000 {
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compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
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reg = <0x44050000 0x10000>;
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clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
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<&sysctrl R9A06G032_CLK_SWITCH>;
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clock-names = "hclk", "clk";
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power-domains = <&sysctrl>;
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status = "disabled";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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switch_port0: port@0 {
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reg = <0>;
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pcs-handle = <&mii_conv5>;
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status = "disabled";
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};
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switch_port1: port@1 {
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reg = <1>;
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pcs-handle = <&mii_conv4>;
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status = "disabled";
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};
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switch_port2: port@2 {
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reg = <2>;
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pcs-handle = <&mii_conv3>;
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status = "disabled";
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};
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switch_port3: port@3 {
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reg = <3>;
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pcs-handle = <&mii_conv2>;
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status = "disabled";
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};
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|
||||
switch_port4: port@4 {
|
||||
reg = <4>;
|
||||
ethernet = <&gmac2>;
|
||||
label = "cpu";
|
||||
phy-mode = "internal";
|
||||
status = "disabled";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@44101000 {
|
||||
compatible = "arm,gic-400", "arm,cortex-a7-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x44101000 0x1000>, /* Distributer */
|
||||
<0x44102000 0x2000>, /* CPU interface */
|
||||
<0x44104000 0x2000>, /* Virt interface control */
|
||||
<0x44106000 0x2000>; /* Virt CPU interface */
|
||||
interrupts =
|
||||
<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
can0: can@52104000 {
|
||||
compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
|
||||
reg = <0x52104000 0x800>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
|
||||
power-domains = <&sysctrl>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@52105000 {
|
||||
compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
|
||||
reg = <0x52105000 0x800>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
|
||||
power-domains = <&sysctrl>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
always-on;
|
||||
interrupts =
|
||||
<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
usbphy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
149
include/dt-bindings/clock/r9a06g032-sysctrl.h
Normal file
149
include/dt-bindings/clock/r9a06g032-sysctrl.h
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* R9A06G032 sysctrl IDs
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Europe Limited
|
||||
*
|
||||
* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
|
||||
#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
|
||||
|
||||
#define R9A06G032_CLK_PLL_USB 1
|
||||
#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
|
||||
#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
|
||||
#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
|
||||
#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
|
||||
#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
|
||||
#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
|
||||
#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
|
||||
#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
|
||||
#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
|
||||
#define R9A06G032_CLK_25_PG4 26
|
||||
#define R9A06G032_CLK_25_PG5 27
|
||||
#define R9A06G032_CLK_25_PG6 28
|
||||
#define R9A06G032_CLK_25_PG7 29
|
||||
#define R9A06G032_CLK_25_PG8 30
|
||||
#define R9A06G032_CLK_ADC 31
|
||||
#define R9A06G032_CLK_ECAT100 32
|
||||
#define R9A06G032_CLK_HSR100 33
|
||||
#define R9A06G032_CLK_I2C0 34
|
||||
#define R9A06G032_CLK_I2C1 35
|
||||
#define R9A06G032_CLK_MII_REF 36
|
||||
#define R9A06G032_CLK_NAND 37
|
||||
#define R9A06G032_CLK_NOUSBP2_PG6 38
|
||||
#define R9A06G032_CLK_P1_PG2 39
|
||||
#define R9A06G032_CLK_P1_PG3 40
|
||||
#define R9A06G032_CLK_P1_PG4 41
|
||||
#define R9A06G032_CLK_P4_PG3 42
|
||||
#define R9A06G032_CLK_P4_PG4 43
|
||||
#define R9A06G032_CLK_P6_PG1 44
|
||||
#define R9A06G032_CLK_P6_PG2 45
|
||||
#define R9A06G032_CLK_P6_PG3 46
|
||||
#define R9A06G032_CLK_P6_PG4 47
|
||||
#define R9A06G032_CLK_PCI_USB 48
|
||||
#define R9A06G032_CLK_QSPI0 49
|
||||
#define R9A06G032_CLK_QSPI1 50
|
||||
#define R9A06G032_CLK_RGMII_REF 51
|
||||
#define R9A06G032_CLK_RMII_REF 52
|
||||
#define R9A06G032_CLK_SDIO0 53
|
||||
#define R9A06G032_CLK_SDIO1 54
|
||||
#define R9A06G032_CLK_SERCOS100 55
|
||||
#define R9A06G032_CLK_SLCD 56
|
||||
#define R9A06G032_CLK_SPI0 57
|
||||
#define R9A06G032_CLK_SPI1 58
|
||||
#define R9A06G032_CLK_SPI2 59
|
||||
#define R9A06G032_CLK_SPI3 60
|
||||
#define R9A06G032_CLK_SPI4 61
|
||||
#define R9A06G032_CLK_SPI5 62
|
||||
#define R9A06G032_CLK_SWITCH 63
|
||||
#define R9A06G032_HCLK_ECAT125 65
|
||||
#define R9A06G032_HCLK_PINCONFIG 66
|
||||
#define R9A06G032_HCLK_SERCOS 67
|
||||
#define R9A06G032_HCLK_SGPIO2 68
|
||||
#define R9A06G032_HCLK_SGPIO3 69
|
||||
#define R9A06G032_HCLK_SGPIO4 70
|
||||
#define R9A06G032_HCLK_TIMER0 71
|
||||
#define R9A06G032_HCLK_TIMER1 72
|
||||
#define R9A06G032_HCLK_USBF 73
|
||||
#define R9A06G032_HCLK_USBH 74
|
||||
#define R9A06G032_HCLK_USBPM 75
|
||||
#define R9A06G032_CLK_48_PG_F 76
|
||||
#define R9A06G032_CLK_48_PG4 77
|
||||
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */
|
||||
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
|
||||
#define R9A06G032_HCLK_CAN0 85
|
||||
#define R9A06G032_HCLK_CAN1 86
|
||||
#define R9A06G032_HCLK_DELTASIGMA 87
|
||||
#define R9A06G032_HCLK_PWMPTO 88
|
||||
#define R9A06G032_HCLK_RSV 89
|
||||
#define R9A06G032_HCLK_SGPIO0 90
|
||||
#define R9A06G032_HCLK_SGPIO1 91
|
||||
#define R9A06G032_RTOS_MDC 92
|
||||
#define R9A06G032_CLK_CM3 93
|
||||
#define R9A06G032_CLK_DDRC 94
|
||||
#define R9A06G032_CLK_ECAT25 95
|
||||
#define R9A06G032_CLK_HSR50 96
|
||||
#define R9A06G032_CLK_HW_RTOS 97
|
||||
#define R9A06G032_CLK_SERCOS50 98
|
||||
#define R9A06G032_HCLK_ADC 99
|
||||
#define R9A06G032_HCLK_CM3 100
|
||||
#define R9A06G032_HCLK_CRYPTO_EIP150 101
|
||||
#define R9A06G032_HCLK_CRYPTO_EIP93 102
|
||||
#define R9A06G032_HCLK_DDRC 103
|
||||
#define R9A06G032_HCLK_DMA0 104
|
||||
#define R9A06G032_HCLK_DMA1 105
|
||||
#define R9A06G032_HCLK_GMAC0 106
|
||||
#define R9A06G032_HCLK_GMAC1 107
|
||||
#define R9A06G032_HCLK_GPIO0 108
|
||||
#define R9A06G032_HCLK_GPIO1 109
|
||||
#define R9A06G032_HCLK_GPIO2 110
|
||||
#define R9A06G032_HCLK_HSR 111
|
||||
#define R9A06G032_HCLK_I2C0 112
|
||||
#define R9A06G032_HCLK_I2C1 113
|
||||
#define R9A06G032_HCLK_LCD 114
|
||||
#define R9A06G032_HCLK_MSEBI_M 115
|
||||
#define R9A06G032_HCLK_MSEBI_S 116
|
||||
#define R9A06G032_HCLK_NAND 117
|
||||
#define R9A06G032_HCLK_PG_I 118
|
||||
#define R9A06G032_HCLK_PG19 119
|
||||
#define R9A06G032_HCLK_PG20 120
|
||||
#define R9A06G032_HCLK_PG3 121
|
||||
#define R9A06G032_HCLK_PG4 122
|
||||
#define R9A06G032_HCLK_QSPI0 123
|
||||
#define R9A06G032_HCLK_QSPI1 124
|
||||
#define R9A06G032_HCLK_ROM 125
|
||||
#define R9A06G032_HCLK_RTC 126
|
||||
#define R9A06G032_HCLK_SDIO0 127
|
||||
#define R9A06G032_HCLK_SDIO1 128
|
||||
#define R9A06G032_HCLK_SEMAP 129
|
||||
#define R9A06G032_HCLK_SPI0 130
|
||||
#define R9A06G032_HCLK_SPI1 131
|
||||
#define R9A06G032_HCLK_SPI2 132
|
||||
#define R9A06G032_HCLK_SPI3 133
|
||||
#define R9A06G032_HCLK_SPI4 134
|
||||
#define R9A06G032_HCLK_SPI5 135
|
||||
#define R9A06G032_HCLK_SWITCH 136
|
||||
#define R9A06G032_HCLK_SWITCH_RG 137
|
||||
#define R9A06G032_HCLK_UART0 138
|
||||
#define R9A06G032_HCLK_UART1 139
|
||||
#define R9A06G032_HCLK_UART2 140
|
||||
#define R9A06G032_HCLK_UART3 141
|
||||
#define R9A06G032_HCLK_UART4 142
|
||||
#define R9A06G032_HCLK_UART5 143
|
||||
#define R9A06G032_HCLK_UART6 144
|
||||
#define R9A06G032_HCLK_UART7 145
|
||||
#define R9A06G032_CLK_UART0 146
|
||||
#define R9A06G032_CLK_UART1 147
|
||||
#define R9A06G032_CLK_UART2 148
|
||||
#define R9A06G032_CLK_UART3 149
|
||||
#define R9A06G032_CLK_UART4 150
|
||||
#define R9A06G032_CLK_UART5 151
|
||||
#define R9A06G032_CLK_UART6 152
|
||||
#define R9A06G032_CLK_UART7 153
|
||||
|
||||
#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
|
||||
Loading…
Reference in a new issue