arm: mvebu: Add support for Thecus N2350 (Armada 385) board
Thecus N2350 is a NAS based on Marvell Armada 385 SoC. Specification: - Processor: Marvel MV88F6820 Dual Core at 1GHz - 1 GiB DDR4 RAM - 4MB Macronix mx25l3205d SPI flash - 512MB Hynix H27U4G8F2DTR-BC NAND flash - I2C - 2x USB 3.0 - 1x GBE LAN port (PHY: Marvell 88E1510) - 2x SATA (hot swap slots) - 3x buttons - 10x LEDS - serial console Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tony Dinh
Stefan Roese
parent
5c73428f4a
commit
3fdd09f90f
8 changed files with 746 additions and 0 deletions
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@ -247,6 +247,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-385-atl-x530.dtb \
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armada-385-atl-x530DP.dtb \
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armada-385-db-88f6820-amc.dtb \
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armada-385-thecus-n2350.dtb \
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armada-385-turris-omnia.dtb \
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armada-388-clearfog.dtb \
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armada-388-gp.dtb \
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446
arch/arm/dts/armada-385-thecus-n2350.dts
Normal file
446
arch/arm/dts/armada-385-thecus-n2350.dts
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@ -0,0 +1,446 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Thecus N2350 board
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*
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* Copyright (C) 2018-2023 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2018 Manuel Jung <manuel.jung@hotmail.com>
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-385.dtsi"
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/ {
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model = "Thecus N2350";
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compatible = "thecus,n2350", "marvell,armada385";
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aliases {
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ethernet0 = ð0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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};
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usb3_0_phy: usb3_0_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&usb3_0_power>;
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};
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usb3_1_phy: usb3_1_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&usb3_1_power>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-0 = <&pmx_power_button &pmx_copy_button &pmx_reset_button>;
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pinctrl-names = "default";
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button@1 {
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label = "Power Button";
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linux,code = <KEY_POWER>;
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gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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};
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button@2 {
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label = "Copy Button";
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linux,code = <KEY_COPY>;
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gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
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};
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button@3 {
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label = "Reset Button";
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linux,code = <KEY_RESTART>;
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gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pmx_sata1_white_led
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&pmx_sata1_red_led
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&pmx_sata2_white_led
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&pmx_sata2_red_led
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&pmx_sys_white_led
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&pmx_sys_red_led
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&pmx_pwr_blue_led
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&pmx_pwr_red_led
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&pmx_usb_white_led
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&pmx_usb_red_led>;
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pinctrl-names = "default";
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white_sata1 {
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label = "n2350:white:sata1";
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gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "ide-disk1";
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};
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red_sata1 {
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label = "n2350:red:sata1";
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gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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};
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white-sata2 {
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label = "n2350:white:sata2";
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gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
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};
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red-sata2 {
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label = "n2350:red:sata2";
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gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
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};
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white-sys {
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label = "n2350:white:sys";
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gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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red-sys {
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label = "n2350:red:sys";
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gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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blue-pwr {
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label = "n2350:blue:pwr";
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gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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red-pwr {
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label = "n2350:red:pwr";
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gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
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};
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white-usb {
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label = "n2350:white:usb";
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gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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};
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red-usb {
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label = "n2350:red:usb";
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gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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usb3_0_power: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "USB3_0_Power";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
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};
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usb3_1_power: regulator@2 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "USB3_1_Power";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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};
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reg_sata0: regulator@3 {
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compatible = "regulator-fixed";
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regulator-name = "pwr_en_sata0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata0: v5-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata0>;
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};
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reg_12v_sata0: v12-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata0>;
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};
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reg_sata1: regulator@4 {
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regulator-name = "pwr_en_sata1";
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compatible = "regulator-fixed";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata1: v5-sata1 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata1";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata1>;
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};
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reg_12v_sata1: v12-sata1 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata1";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata1>;
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};
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};
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gpio-poweroff {
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compatible = "gpio-poweroff";
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pinctrl-0 = <&pmx_pwr_off>;
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pinctrl-names = "default";
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gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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};
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};
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&ahci0 {
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status = "okay";
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};
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&bm {
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status = "okay";
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};
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&bm_bppi {
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status = "okay";
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};
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ð0 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <1>;
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <100000>;
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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&nand_controller {
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status = "okay";
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nand@0 {
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status = "okay";
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reg = <0>;
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label = "pxa3xx_nand-0";
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nand-rb = <0>;
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marvell,nand-keep-config;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "rootfs";
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reg = <0x00000000 0x20000000>;
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};
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};
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};
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};
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&pciec {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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&pinctrl {
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pinctrl-names = "default";
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pmx_power_button: pmx-power-button {
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marvell,pins = "mpp49";
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marvell,function = "gpio";
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};
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pmx_copy_button: pmx-copy-button {
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marvell,pins = "mpp52";
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marvell,function = "gpio";
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};
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pmx_reset_button: pmx-reset-button {
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marvell,pins = "mpp50";
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marvell,function = "gpio";
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};
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pmx_sata1_white_led: pmx-sata1-white-led {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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pmx_sata1_red_led: pmx-sata1-red-led {
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marvell,pins = "mpp46";
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marvell,function = "gpio";
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};
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pmx_sata2_white_led: pmx-sata2-white-led {
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marvell,pins = "mpp19";
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marvell,function = "gpio";
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};
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pmx_sata2_red_led: pmx-sata2-red-led {
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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pmx_sys_white_led: pmx-sys-white-led {
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marvell,pins = "mpp14";
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marvell,function = "gpio";
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};
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pmx_sys_red_led: pmx-sys-red-led {
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marvell,pins = "mpp15";
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marvell,function = "gpio";
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};
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pmx_buzzer: pmx-buzzer {
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marvell,pins = "mpp51";
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marvell,function = "gpio";
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};
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pmx_pwr_off: pmx-pwr-off {
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marvell,pins = "mpp54";
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marvell,function = "gpio";
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};
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pmx_pwr_blue_led: pmx-pwr-blue-led {
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marvell,pins = "mpp43";
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marvell,function = "gpio";
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};
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pmx_pwr_red_led: pmx-pwr-red-led {
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marvell,pins = "mpp18";
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marvell,function = "gpio";
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};
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pmx_usb_white_led: pmx-usb-white-led {
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marvell,pins = "mpp16";
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marvell,function = "gpio";
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};
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pmx_usb_red_led: pmx-usb-red-led {
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marvell,pins = "mpp17";
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marvell,function = "gpio";
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};
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};
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&sdhci {
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broken-cd;
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wp-inverted;
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bus-width = <8>;
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status = "okay";
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no-1-8-v;
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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status = "okay";
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/* spi: 4M Flash Macronix MX25L3205D */
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "macronix,mx25l3205d", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <108000000>;
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spi-cpha;
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partition@0 {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x00100000 0x00010000>;
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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@ -97,6 +97,9 @@ config 88F6820
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config CUSTOMER_BOARD_SUPPORT
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bool
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config DDR4
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bool "Support Marvell DDR4 Training driver"
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choice
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prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
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optional
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@ -175,6 +178,11 @@ config TARGET_MAXBCM
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select BOARD_ECC_SUPPORT
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select MV78460
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config TARGET_N2350
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bool "Support Thecus N2350"
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select 88F6820
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select DDR4
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config TARGET_THEADORABLE
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bool "Support theadorable Armada XP"
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select BOARD_LATE_INIT if USB
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@ -257,6 +265,7 @@ config SYS_BOARD
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default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
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default "ds414" if TARGET_DS414
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default "maxbcm" if TARGET_MAXBCM
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default "n2350" if TARGET_N2350
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default "theadorable" if TARGET_THEADORABLE
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default "a38x" if TARGET_CONTROLCENTERDC
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default "x530" if TARGET_X530
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@ -276,6 +285,7 @@ config SYS_CONFIG_NAME
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default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
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default "ds414" if TARGET_DS414
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default "maxbcm" if TARGET_MAXBCM
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default "n2350" if TARGET_N2350
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default "theadorable" if TARGET_THEADORABLE
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default "turris_omnia" if TARGET_TURRIS_OMNIA
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default "turris_mox" if TARGET_TURRIS_MOX
|
||||
|
|
@ -298,6 +308,7 @@ config SYS_VENDOR
|
|||
default "solidrun" if TARGET_CLEARFOG
|
||||
default "kobol" if TARGET_HELIOS4
|
||||
default "Synology" if TARGET_DS414
|
||||
default "thecus" if TARGET_N2350
|
||||
default "CZ.NIC" if TARGET_TURRIS_OMNIA
|
||||
default "CZ.NIC" if TARGET_TURRIS_MOX
|
||||
default "gdsys" if TARGET_CONTROLCENTERDC
|
||||
|
|
|
|||
7
board/thecus/n2350/MAINTAINERS
Normal file
7
board/thecus/n2350/MAINTAINERS
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
N2350 BOARD
|
||||
M: Tony Dinh <mibodhi@gmail.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/armada-385-thecus-n2350.dts
|
||||
F: board/thecus/n2350/
|
||||
F: include/configs/n2350.h
|
||||
F: configs/n2350_defconfig
|
||||
6
board/thecus/n2350/Makefile
Normal file
6
board/thecus/n2350/Makefile
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
#
|
||||
|
||||
obj-y := n2350.o
|
||||
126
board/thecus/n2350/n2350.c
Normal file
126
board/thecus/n2350/n2350.c
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Those N2350_GPP_xx values and defines in board_serdes_map, and board_topology_map
|
||||
* are taken from the Marvell U-Boot version "u-boot-a38x-2015T1_p18_Thecus"
|
||||
*/
|
||||
|
||||
#define N2350_GPP_OUT_ENA_LOW (~(BIT(20) | BIT(21) | BIT(24)))
|
||||
#define N2350_GPP_OUT_ENA_MID (~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
|
||||
#define N2350_GPP_OUT_VAL_LOW 0x1200000
|
||||
#define N2350_GPP_OUT_VAL_MID 0x1001
|
||||
#define N2350_GPP_POL_LOW 0x0
|
||||
#define N2350_GPP_POL_MID 0x0
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{ SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR4 init code in the SPL U-Boot version to configure
|
||||
* the DDR4 controller.
|
||||
*/
|
||||
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866L, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
|
||||
MV_DDR_DIE_CAP_4GBIT, /* mem_size - N2350 board has 2x512MB DRAM banks */
|
||||
MV_DDR_FREQ_800, /* frequency */
|
||||
0, 0, /* cas_wl cas_l */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_DEFAULT} }, /* timing */
|
||||
BUS_MASK_32BIT, /* Busses mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
NOT_COMBINED, /* ddr twin-die combined */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Those MPP values are taken from the Marvell U-Boot version
|
||||
* "u-boot-a38x-2015T1_p18_Thecus"
|
||||
*/
|
||||
|
||||
/* Configure MPP */
|
||||
writel(0x50111111, MVEBU_MPP_BASE + 0x00); /* MPP0_7 */
|
||||
writel(0x00555555, MVEBU_MPP_BASE + 0x04); /* MPP8_15 */
|
||||
writel(0x55000000, MVEBU_MPP_BASE + 0x08); /* MPP16_23 */
|
||||
writel(0x05050050, MVEBU_MPP_BASE + 0x0c); /* MPP24_31 */
|
||||
writel(0x05555555, MVEBU_MPP_BASE + 0x10); /* MPP32_39 */
|
||||
writel(0x00000565, MVEBU_MPP_BASE + 0x14); /* MPP40_47 */
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x18); /* MPP48_55 */
|
||||
writel(0x00004444, MVEBU_MPP_BASE + 0x1c); /* MPP56_63 */
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(N2350_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(N2350_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(N2350_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(N2350_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(N2350_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(N2350_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
93
configs/n2350_defconfig
Normal file
93
configs/n2350_defconfig
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_CMDLINE_TAG=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x00800000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
|
||||
CONFIG_TARGET_N2350=y
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-385-thecus-n2350"
|
||||
CONFIG_SPL_TEXT_BASE=0x40000030
|
||||
CONFIG_SYS_PROMPT="N2350 > "
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK=0x4002c000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xf1012000
|
||||
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||
CONFIG_IDENT_STRING="\nThecus N2350"
|
||||
CONFIG_SYS_LOAD_ADDR=0x800000
|
||||
CONFIG_ENV_ADDR=0x100000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x22fd0
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x40023000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_DNS=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=pxa3xx_nand-0:-(rootfs);spi1.0:1M(u-boot),64K@1M(u-boot-env),-(data)"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_ARP_TIMEOUT=200
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_SYS_64BIT_LBA=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MVTWSI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_SF_DEFAULT_SPEED=50000000
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MVMDIO=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ARMADA_38X=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_ARMADA38X=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_KIRKWOOD_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
56
include/configs/n2350.h
Normal file
56
include/configs/n2350.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_N2350_H
|
||||
#define _CONFIG_N2350_H
|
||||
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
/* Keep device tree and initrd in lower memory so the kernel can access them */
|
||||
#define RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0"
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/* Include the common distro boot environment */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(SCSI, scsi, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#define KERNEL_ADDR_R __stringify(0x1000000)
|
||||
#define FDT_ADDR_R __stringify(0x2000000)
|
||||
#define RAMDISK_ADDR_R __stringify(0x2200000)
|
||||
#define SCRIPT_ADDR_R __stringify(0x1800000)
|
||||
#define PXEFILE_ADDR_R __stringify(0x1900000)
|
||||
|
||||
#define LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"kernel_addr_r=" KERNEL_ADDR_R "\0" \
|
||||
"fdt_addr_r=" FDT_ADDR_R "\0" \
|
||||
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
|
||||
"scriptaddr=" SCRIPT_ADDR_R "\0" \
|
||||
"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"console=ttyS0,115200\0" \
|
||||
BOOTENV
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
#endif /* _CONFIG_N2350_H */
|
||||
Loading…
Reference in a new issue