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Merge tag 'fsl-qoriq-2022-10-18' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq

Browse source 
Layerscape update
 - support sysreset,
 - de-select FSL_IFC when booting from SD
 - disable unused parts of ICID tables
 - reduce ns_dev size for csu
 - enable dma snooping for ls104x
 - nand driver fixups for ls1043ardb rev 7.0 boards.
This commit is contained in:
Tom Rini 2022-10-24 21:28:47 -04:00
commit 3eebbd866b
10 changed files with 74 additions and 8 deletions
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4
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View file

@ -63,7 +63,7 @@ config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
@ -100,7 +100,7 @@ config ARCH_LS1043A
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT)
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2

2
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View file

@ -1229,6 +1229,7 @@ int timer_init(void)
return 0;
}
#if !CONFIG_IS_ENABLED(SYSRESET)
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void)
@ -1248,6 +1249,7 @@ void __efi_runtime reset_cpu(void)
scfg_out32(rstcr, val);
#endif
}
#endif
#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)

2
arch/arm/cpu/armv8/fsl-layerscape/icid.c
View file

@ -46,6 +46,7 @@ void set_icids(void)
#endif
}
#ifndef CONFIG_SPL_BUILD
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
{
int i, ret;
@ -190,3 +191,4 @@ void fdt_fixup_icid(void *blob)
fdt_fixup_fman_icids(blob, smmu_ph);
#endif
}
#endif

2
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -682,7 +682,7 @@ void fsl_lsch2_early_init_f(void)
SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
SCFG_SNPCNFGCR_SATAWRSNP);
SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP);
#elif defined(CONFIG_ARCH_LS1012A)
setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |

16
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View file

@ -12,11 +12,15 @@
#include <asm/armv8/sec_firmware.h>
struct icid_id_table {
#ifndef CONFIG_SPL_BUILD
const char *compat;
u32 id;
u32 reg;
phys_addr_t compat_addr;
#endif
phys_addr_t reg_addr;
u32 reg;
#ifndef CONFIG_SPL_BUILD
u32 id;
#endif
bool le;
};
@ -31,6 +35,13 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
void set_icids(void);
void fdt_fixup_icid(void *blob);
#ifdef CONFIG_SPL_BUILD
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .reg = regA, \
.reg_addr = addr, \
.le = _le \
}
#else
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .compat = name, \
.id = idA, \
@ -39,6 +50,7 @@ void fdt_fixup_icid(void *blob);
.reg_addr = addr, \
.le = _le \
}
#endif
#ifdef CONFIG_SYS_FSL_SEC_LE
#define SEC_IS_LE true

1
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View file

@ -383,6 +383,7 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000
#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000
#define SCFG_SNPCNFGCR_EDMASNP 0x00020000
#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000
#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000
#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000

4
board/freescale/ls1043ardb/cpld.c
View file

@ -69,6 +69,10 @@ void cpld_set_defbank(void)
void cpld_set_nand(void)
{
u16 reg = CPLD_CFG_RCW_SRC_NAND;
if (CPLD_READ(cpld_ver) > 0x2)
reg = CPLD_CFG_RCW_SRC_NAND_4K;
u8 reg5 = (u8)(reg >> 1);
u8 reg6 = (u8)(reg & 1);

1
board/freescale/ls1043ardb/cpld.h
View file

@ -41,5 +41,6 @@ void cpld_rev_bit(unsigned char *value);
#define CPLD_BANK_SEL_ALTBANK 0x04
#define CPLD_CFG_RCW_SRC_NOR 0x025
#define CPLD_CFG_RCW_SRC_NAND 0x106
#define CPLD_CFG_RCW_SRC_NAND_4K 0x118
#define CPLD_CFG_RCW_SRC_SD 0x040
#endif

46
board/freescale/ls1043ardb/ls1043ardb.c
View file

@ -167,7 +167,7 @@ int checkboard(void)
if (cfg_rcw_src == 0x25)
printf("vBank %d\n", CPLD_READ(vbank));
else if (cfg_rcw_src == 0x106)
else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118))
puts("NAND\n");
else
printf("Invalid setting of SW4\n");
@ -347,10 +347,54 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
void nand_fixup(void)
{
u32 csor = 0;
if (CPLD_READ(pcba_ver) < 0x7)
return;
/* Change NAND Flash PGS/SPRZ configuration */
csor = CONFIG_SYS_NAND_CSOR;
if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K)
csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K;
if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64)
csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224;
if (IS_ENABLED(CONFIG_TFABOOT)) {
u8 cfg_rcw_src1, cfg_rcw_src2;
u16 cfg_rcw_src;
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
cpld_rev_bit(&cfg_rcw_src1);
cfg_rcw_src = cfg_rcw_src1;
cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
if (cfg_rcw_src == 0x25)
set_ifc_csor(IFC_CS1, csor);
else if (cfg_rcw_src == 0x118)
set_ifc_csor(IFC_CS0, csor);
else
printf("Invalid setting\n");
} else {
if (IS_ENABLED(CONFIG_NAND_BOOT))
set_ifc_csor(IFC_CS0, csor);
else
set_ifc_csor(IFC_CS1, csor);
}
}
#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
int board_fix_fdt(void *blob)
{
/* nand driver fix up */
nand_fixup();
/* fdt fix up */
fdt_fixup_phy_addr(blob);
return 0;
}
#endif

4
include/fsl_csu.h
View file

@ -24,8 +24,8 @@ enum csu_cslx_access {
};
struct csu_ns_dev {
unsigned long ind;
uint32_t val;
u8 ind;
u8 val;
};
void enable_layerscape_ns_access(void);