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driver/ddr: Fix DDR register timing_cfg_8

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The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-06-26 11:14:44 -07:00
parent de51916310
commit 3d75ec95f5
1 changed files with 3 additions and 0 deletions
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3
drivers/ddr/fsl/ctrl_regs.c
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@ -1857,6 +1857,9 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr,
acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps);
wrtord_bg = max(4, picos_to_mclk(7500));
if (popts->otf_burst_chop_en)
wrtord_bg += 2;
pre_all_rec = 0;
ddr->timing_cfg_8 = (0