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Second set of u-boot-at91 features for the 2022.07 cycle

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Merge tag 'u-boot-at91-2022.07-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2022.07 cycle:

This feature set includes the new driver for the AT91 reset controller,
a new board called sam9x60 curiosity, and several other fixes and
clean-ups (sama7g5ek qspi clock, impedance; remove unused code,
introduce Kconfig symbols for SPL timers)
This commit is contained in:
Tom Rini 2022-04-26 07:54:12 -04:00
commit 3970f7728d
63 changed files with 652 additions and 90 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arm/dts/Makefile
View file

@ -1021,6 +1021,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
dtb-$(CONFIG_TARGET_SAM9X60_CURIOSITY) += at91-sam9x60_curiosity.dtb
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \

79
arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi Normal file
View file

@ -0,0 +1,79 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x60_curiosity-u-boot.dtsi - Device Tree Include file for SAM9X60
* CURIOSITY.
*
* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
*
* Author: Durai Manickam KR <durai.manickamkr@microchip.com>
*/
/ {
ahb {
u-boot,dm-pre-reloc;
apb {
u-boot,dm-pre-reloc;
pinctrl {
u-boot,dm-pre-reloc;
};
};
};
chosen {
u-boot,dm-pre-reloc;
};
};
&clk32 {
u-boot,dm-pre-reloc;
};
&dbgu {
u-boot,dm-pre-reloc;
};
&main_rc {
u-boot,dm-pre-reloc;
};
&main_xtal {
u-boot,dm-pre-reloc;
};
&pinctrl_dbgu {
u-boot,dm-pre-reloc;
};
&pinctrl_sdhci0 {
u-boot,dm-pre-reloc;
};
&pioA {
u-boot,dm-pre-reloc;
};
&pioB {
u-boot,dm-pre-reloc;
};
&pit64b0 {
u-boot,dm-pre-reloc;
};
&pmc {
u-boot,dm-pre-reloc;
};
&sdhci0 {
u-boot,dm-pre-reloc;
};
&slow_rc_osc {
u-boot,dm-pre-reloc;
};
&slow_xtal {
u-boot,dm-pre-reloc;
};

74
arch/arm/dts/at91-sam9x60_curiosity.dts Normal file
View file

@ -0,0 +1,74 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x60_curiosity.dts - Device Tree file for SAM9X60 CURIOSITY board
*
* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
*
* Author: Durai Manickam KR <durai.manickamkr@microchip.com>
*/
/dts-v1/;
#include <dt-bindings/mfd/atmel-flexcom.h>
#include "sam9x60.dtsi"
/ {
model = "Microchip SAM9X60 CURIOSITY";
compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9";
ahb {
apb {
flx0: flexcom@f801c600 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c@600 {
compatible = "atmel,sama5d2-i2c";
reg = <0x600 0x200>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
status = "okay";
eeprom@53 {
compatible = "atmel,24c32";
reg = <0x53>;
pagesize = <16>;
};
};
};
pinctrl {
pinctrl_flx0: flx0_default {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
};
};
chosen {
stdout-path = &dbgu;
i2c0 = &flx0;
};
clocks {
slow_xtal: slow_xtal {
clock-frequency = <32768>;
};
main_xtal: main_xtal {
clock-frequency = <24000000>;
};
};
memory {
reg = <0x20000000 0x8000000>;
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
};

2
arch/arm/dts/at91-sama7g5ek.dts
View file

@ -667,7 +667,7 @@
<PIN_PB21__QSPI0_INT>;
bias-disable;
slew-rate = <0>;
atmel,drive-strength = <ATMEL_PIO_DRVSTR_HI>;
atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
};
pinctrl_sdmmc0_default: sdmmc0_default {

13
arch/arm/dts/sam9x60.dtsi
View file

@ -223,12 +223,25 @@
status = "okay";
};
reset_controller: rstc@fffffe00 {
compatible = "microchip,sam9x60-rstc";
reg = <0xfffffe00 0x10>;
clocks = <&clk32 0>;
};
pit: timer@fffffe40 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffe40 0x10>;
clocks = <&pmc PMC_TYPE_CORE 11>; /* ID_MCK. */
};
pit64b0: timer@f0028000 {
compatible = "microchip,sam9x60-pit64b";
reg = <0xf0028000 0xec>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
clock-names = "pclk", "gclk";
};
clk32: sckc@fffffe50 {
compatible = "microchip,sam9x60-sckc";
reg = <0xfffffe50 0x4>;

9
arch/arm/dts/sama7g5.dtsi
View file

@ -232,6 +232,13 @@
clocks = <&clk32k 0>;
};
reset_controller: rstc@e001d000 {
compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc";
reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
#reset-cells = <1>;
clocks = <&clk32k 0>;
};
clk32k: clock-controller@e001d050 {
compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d050 0x4>;
@ -316,7 +323,7 @@
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
clock-names = "pclk", "gclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
assigned-clocks = <&pmc PMC_TYPE_GCK 79>;
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
#address-cells = <1>;
#size-cells = <0>;

7
arch/arm/mach-at91/Kconfig
View file

@ -165,6 +165,12 @@ config TARGET_SAM9X60EK
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
config TARGET_SAM9X60_CURIOSITY
bool "SAM9X60 CURIOSITY board"
select SAM9X60
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
@ -339,6 +345,7 @@ source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sam9x60_curiosity/Kconfig"
source "board/atmel/sama7g5ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"

2
arch/arm/mach-at91/arm926ejs/Makefile
View file

@ -18,7 +18,9 @@ obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-y += clock.o
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)SYSRESET
obj-y += reset.o
endif
ifneq ($(CONFIG_ATMEL_PIT_TIMER),y)
ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y)
# old non-DM timer driver

3
arch/arm/mach-at91/armv7/Makefile
View file

@ -11,9 +11,6 @@ obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o clock.o
obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o
obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o
obj-y += cpu.o
ifndef CONFIG_$(SPL_TPL_)SYSRESET
obj-y += reset.o
endif
ifneq ($(CONFIG_ATMEL_TCB_TIMER),y)
ifneq ($(CONFIG_ATMEL_PIT_TIMER),y)
ifneq ($(CONFIG_MCHP_PIT64B_TIMER),y)

31
arch/arm/mach-at91/armv7/reset.c
View file

@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* (C) Copyright 2013
* Bo Shen <voice.shen@atmel.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */
void reset_cpu(void)
{
at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
writel(AT91_RSTC_KEY
| AT91_RSTC_CR_PROCRST /* Processor Reset */
| AT91_RSTC_CR_PERRST /* Peripheral Reset */
#ifdef CONFIG_AT91RESET_EXTRST
| AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
#endif
, &rstc->cr);
/* never reached */
do { } while (1);
}

15
board/atmel/sam9x60_curiosity/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_SAM9X60_CURIOSITY
config SYS_BOARD
default "sam9x60_curiosity"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at91"
config SYS_CONFIG_NAME
default "sam9x60_curiosity"
endif

7
board/atmel/sam9x60_curiosity/MAINTAINERS Normal file
View file

@ -0,0 +1,7 @@
SAM9X60 CURIOSITY BOARD
M: Durai Manickam KR <durai.manickamkr@microchip.com>
M: Eugen Hristev <eugen.hristev@microchip.com>
S: Maintained
F: board/atmel/sam9x60_curiosity/
F: include/configs/sam9x60_curiosity.h
F: configs/sam9x60_curiosity_mmc_defconfig

7
board/atmel/sam9x60_curiosity/Makefile Normal file
View file

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
#
# Author: Durai Manickam KR <durai.manickamkr@microchip.com>
obj-y += sam9x60_curiosity.o

75
board/atmel/sam9x60_curiosity/sam9x60_curiosity.c Normal file
View file

@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
*
* Author: Durai Manickam KR <durai.manickamkr@microchip.com>
*/
#include <common.h>
#include <debug_uart.h>
#include <fdtdec.h>
#include <init.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_sfr.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
int board_late_init(void)
{
at91_prepare_cpu_var();
return 0;
}
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
at91_seriald_hw_init();
}
#endif
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
debug_uart_init();
#endif
return 0;
}
#define MAC24AA_MAC_OFFSET 0xfa
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
#ifdef CONFIG_I2C_EEPROM
at91_set_ethaddr(MAC24AA_MAC_OFFSET);
#endif
return 0;
}
#endif
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
return 0;
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}

1
configs/gardena-smart-gateway-at91sam_defconfig
View file

@ -101,6 +101,7 @@ CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
# CONFIG_SYS_WHITE_ON_BLACK is not set
CONFIG_WDT=y
CONFIG_WDT_AT91=y

74
configs/sam9x60_curiosity_mmc_defconfig Normal file
View file

@ -0,0 +1,74 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x23f00000
CONFIG_SYS_MALLOC_LEN=0x81000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_TARGET_SAM9X60_CURIOSITY=y
CONFIG_ATMEL_LEGACY=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_ENV_SIZE=0x4000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sam9x60_curiosity"
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0xfffff200
CONFIG_DEBUG_UART_CLOCK=200000000
CONFIG_DEBUG_UART=y
CONFIG_SYS_LOAD_ADDR=0x22000000
CONFIG_FIT=y
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="fatload mmc 0:1 0x21000000 at91-sam9x60_curiosity.dtb; fatload mmc 0:1 0x22000000 zImage; bootz 0x22000000 - 0x21000000"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTFILESIZE=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_HASH=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GENERIC_CLK=y
CONFIG_AT91_SAM9X60_PLL=y
CONFIG_CPU=y
CONFIG_AT91_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_PHY_MICREL=y
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_AT91=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_MCHP_PIT64B_TIMER=y
CONFIG_OF_LIBFDT_OVERLAY=y

3
configs/sam9x60ek_mmc_defconfig
View file

@ -76,6 +76,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_W1=y
CONFIG_W1_GPIO=y

3
configs/sam9x60ek_nandflash_defconfig
View file

@ -78,6 +78,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y

3
configs/sam9x60ek_qspiflash_defconfig
View file

@ -90,6 +90,9 @@ CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_W1=y
CONFIG_W1_GPIO=y
CONFIG_W1_EEPROM=y

5
configs/sama5d27_giantboard_defconfig
View file

@ -77,9 +77,14 @@ CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y

5
configs/sama5d27_som1_ek_mmc1_defconfig
View file

@ -89,8 +89,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d27_som1_ek_mmc_defconfig
View file

@ -89,8 +89,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d27_som1_ek_qspiflash_defconfig
View file

@ -88,8 +88,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d27_wlsom1_ek_mmc_defconfig
View file

@ -94,8 +94,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d27_wlsom1_ek_qspiflash_defconfig
View file

@ -98,8 +98,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d2_icp_mmc_defconfig
View file

@ -80,7 +80,12 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_SPL_ATMEL_TCB_TIMER=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER_HII is not set

3
configs/sama5d2_icp_qspiflash_defconfig
View file

@ -87,6 +87,9 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y

3
configs/sama5d2_ptc_ek_mmc_defconfig
View file

@ -70,6 +70,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y

3
configs/sama5d2_ptc_ek_nandflash_defconfig
View file

@ -70,6 +70,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y

5
configs/sama5d2_xplained_emmc_defconfig
View file

@ -88,8 +88,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_SPL_ATMEL_TCB_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d2_xplained_mmc_defconfig
View file

@ -90,8 +90,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_SPL_ATMEL_TCB_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d2_xplained_qspiflash_defconfig
View file

@ -90,8 +90,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_SPL_ATMEL_TCB_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d2_xplained_spiflash_defconfig
View file

@ -94,8 +94,13 @@ CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ATMEL_QSPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_TCB_TIMER=y
CONFIG_SPL_ATMEL_TCB_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

3
configs/sama5d36ek_cmp_mmc_defconfig
View file

@ -65,6 +65,9 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set

3
configs/sama5d36ek_cmp_nandflash_defconfig
View file

@ -67,6 +67,9 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set

3
configs/sama5d36ek_cmp_spiflash_defconfig
View file

@ -67,6 +67,9 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set

5
configs/sama5d3_xplained_mmc_defconfig
View file

@ -84,8 +84,13 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d3_xplained_nandflash_defconfig
View file

@ -87,8 +87,13 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d3xek_mmc_defconfig
View file

@ -92,8 +92,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d3xek_nandflash_defconfig
View file

@ -94,8 +94,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d3xek_spiflash_defconfig
View file

@ -93,8 +93,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d4_xplained_mmc_defconfig
View file

@ -85,8 +85,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d4_xplained_nandflash_defconfig
View file

@ -89,8 +89,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d4_xplained_spiflash_defconfig
View file

@ -91,8 +91,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d4ek_mmc_defconfig
View file

@ -83,8 +83,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d4ek_nandflash_defconfig
View file

@ -87,8 +87,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

5
configs/sama5d4ek_spiflash_defconfig
View file

@ -86,8 +86,13 @@ CONFIG_ATMEL_USART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_SPL_TIMER=y
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_SPL_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y

3
configs/sama7g5ek_mmc1_defconfig
View file

@ -71,6 +71,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_MCHP_PIT64B_TIMER=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER_HII is not set

3
configs/sama7g5ek_mmc_defconfig
View file

@ -71,6 +71,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_ATMEL_USART=y
CONFIG_TIMER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y
CONFIG_MCHP_PIT64B_TIMER=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER_HII is not set

3
configs/vinco_defconfig
View file

@ -56,3 +56,6 @@ CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="L+G VInCo"
CONFIG_USB_GADGET_ATMEL_USBA=y
CONFIG_USB_ETHER=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_CMD_RESET=y
CONFIG_SYSRESET_AT91=y

3
drivers/spi/atmel-quadspi.c
View file

@ -438,6 +438,9 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave,
{
struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
if (!spi_mem_default_supports_op(slave, op))
return false;
if (aq->caps->octal) {
if (atmel_qspi_sama7g5_find_mode(op) < 0)
return false;

15
drivers/sysreset/Kconfig
View file

@ -77,6 +77,21 @@ config SYSRESET_OCTEON
This enables the system reset driver support for Marvell Octeon
SoCs.
config SYSRESET_AT91
bool "Enable support for Microchip/Atmel reset driver"
depends on ARCH_AT91
select SYSRESET_SPL_AT91 if SPL && SPL_SYSRESET
help
This enables the system reset driver support for Microchip/Atmel
SoCs.
config SYSRESET_SPL_AT91
bool "Enable support for Microchip/Atmel reset driver in SPL"
depends on ARCH_AT91
help
This enables the system reset driver support for Microchip/Atmel
SoCs in SPL.
config SYSRESET_PSCI
bool "Enable support for PSCI System Reset"
depends on ARM_PSCI_FW

1
drivers/sysreset/Makefile
View file

@ -20,5 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o

71
drivers/sysreset/sysreset_at91.c Normal file
View file

@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
*/
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <asm/arch/at91_rstc.h>
#include <clk.h>
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <sysreset.h>
static int at91_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
at91_rstc_t *rstc = (at91_rstc_t *)dev_get_priv(dev);
writel(AT91_RSTC_KEY
| AT91_RSTC_CR_PROCRST /* Processor Reset */
| AT91_RSTC_CR_PERRST /* Peripheral Reset */
#ifdef CONFIG_AT91RESET_EXTRST
| AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */
#endif
, &rstc->cr);
return -EINPROGRESS;
}
static int at91_sysreset_probe(struct udevice *dev)
{
struct clk slck;
void *priv;
int ret;
priv = dev_remap_addr(dev);
if (!priv)
return -EINVAL;
dev_set_priv(dev, priv);
ret = clk_get_by_index(dev, 0, &slck);
if (ret)
return ret;
ret = clk_prepare_enable(&slck);
if (ret)
return ret;
return 0;
}
static struct sysreset_ops at91_sysreset = {
.request = at91_sysreset_request,
};
static const struct udevice_id a91_sysreset_ids[] = {
{ .compatible = "atmel,sama5d3-rstc" },
{ .compatible = "microchip,sam9x60-rstc" },
{ }
};
U_BOOT_DRIVER(sysreset_at91) = {
.id = UCLASS_SYSRESET,
.name = "at91_reset",
.ops = &at91_sysreset,
.probe = at91_sysreset_probe,
.of_match = a91_sysreset_ids,
};

17
drivers/timer/Kconfig
View file

@ -90,6 +90,15 @@ config ATMEL_PIT_TIMER
it is designed to offer maximum accuracy and efficient management,
even for systems with long response time.
config SPL_ATMEL_PIT_TIMER
bool "Atmel periodic interval timer support in SPL"
depends on SPL_TIMER
help
Select this to enable a periodic interval timer for Atmel devices,
it is designed to offer maximum accuracy and efficient management,
even for systems with long response time.
Select this to be available in SPL.
config ATMEL_TCB_TIMER
bool "Atmel timer counter support"
depends on TIMER
@ -98,6 +107,14 @@ config ATMEL_TCB_TIMER
Select this to enable the use of the timer counter as a monotonic
counter.
config SPL_ATMEL_TCB_TIMER
bool "Atmel timer counter support in SPL"
depends on SPL_TIMER
depends on ARCH_AT91
help
Select this to enable the use of the timer counter as a monotonic
counter in SPL.
config CADENCE_TTC_TIMER
bool "Cadence TTC (Triple Timer Counter)"
depends on TIMER

5
drivers/timer/Makefile
View file

@ -7,8 +7,9 @@ obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o

11
include/configs/at91-sama5_common.h
View file

@ -15,15 +15,4 @@
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#ifdef CONFIG_SD_BOOT
#else
#ifdef CONFIG_NAND_BOOT
/* u-boot env in nand flash */
#elif CONFIG_SPI_BOOT
/* u-boot env in serial flash, by default is bus 0 and cs 0 */
#endif
#endif
#endif

6
include/configs/at91sam9m10g45ek.h
View file

@ -40,12 +40,6 @@
#endif
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
#elif CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in mmc */
#endif
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE 0x010000
#define CONFIG_SPL_STACK 0x310000

9
include/configs/at91sam9n12ek.h
View file

@ -59,15 +59,6 @@
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
#endif
#ifdef CONFIG_SPI_BOOT
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
#endif
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x6000
#define CONFIG_SPL_STACK 0x308000

31
include/configs/sam9x60_curiosity.h Normal file
View file

@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the SAM9X60 CURIOSITY board.
*
* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
*
* Author: Durai Manickam KR <durai.manickamkr@microchip.com>
*/
#ifndef __CONFIG_H__
#define __CONFIG_H__
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID 0 /* ignored in arm */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x8000000 /* 128 MB */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x218000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \
GENERATED_GBL_DATA_SIZE)
#endif
#endif

10
include/configs/sam9x60ek.h
View file

@ -40,14 +40,4 @@
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in sd card */
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
#elif defined(CONFIG_QSPI_BOOT)
/* bootstrap + u-boot + env + linux in SPI NOR flash */
#endif
#endif

4
include/configs/sama5d27_som1_ek.h
View file

@ -21,10 +21,6 @@
(0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
#endif
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000

12
include/configs/sama5d2_xplained.h
View file

@ -18,18 +18,6 @@
(0x22000000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif
/* SerialFlash */
#ifdef CONFIG_SD_BOOT
/* bootstrap + u-boot + env in sd card */
#elif CONFIG_SPI_BOOT
/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */
#endif
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_BSS_START_ADDR 0x20000000