Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
- A fix for a long standing bug that has been exposed by commit
50128aeb0f ("cyclic: get rid of cyclic_init()") preventing 8xx boards
from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
This commit is contained in:
Tom Rini
commit
386e77cda8
29 changed files with 2129 additions and 140 deletions
|
|
@ -28,6 +28,7 @@ config MPC85xx
|
|||
|
||||
config MPC8xx
|
||||
bool "MPC8xx"
|
||||
select CREATE_ARCH_SYMLINK
|
||||
select BOARD_EARLY_INIT_F
|
||||
imply CMD_REGINFO
|
||||
imply WDT_MPC8xx
|
||||
|
|
|
|||
|
|
@ -11,6 +11,9 @@ choice
|
|||
config TARGET_MCR3000
|
||||
bool "Support MCR3000 board from CSSI"
|
||||
|
||||
config TARGET_CMPC885
|
||||
bool "Support CMPC885 board from CSSI"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
|
|
@ -84,6 +87,7 @@ config SYS_DER
|
|||
help
|
||||
Debug Event Register (37-47)
|
||||
|
||||
source "board/cssi/MCR3000/Kconfig"
|
||||
source "board/cssi/mcr3000/Kconfig"
|
||||
|
||||
source "board/cssi/cmpc885/Kconfig"
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -171,6 +171,7 @@ in_flash:
|
|||
lis r3, CONFIG_SYS_IMMR@h
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
|
||||
li r3, 0 /* clear boot_flag for calling board_init_f */
|
||||
bl board_init_f /* run 1st part of board init code (from Flash) */
|
||||
|
||||
/* NOTREACHED - board_init_f() does not return */
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
|
|||
dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
|
||||
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
|
||||
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
|
||||
dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb
|
||||
|
||||
include $(srctree)/scripts/Makefile.dts
|
||||
|
||||
|
|
|
|||
94
arch/powerpc/dts/cmpc885.dts
Normal file
94
arch/powerpc/dts/cmpc885.dts
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* CMPC885 Device Tree Source
|
||||
*
|
||||
* Copyright 2020 CS Group
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "CMPC885";
|
||||
compatible = "fsl, cmpc885", "fsl,mod885";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
chosen {
|
||||
stdout-path = &SERIAL;
|
||||
};
|
||||
|
||||
WDT: watchdog@0 {
|
||||
device_type = "watchdog";
|
||||
compatible = "fsl,pq1-wdt";
|
||||
};
|
||||
|
||||
SERIAL: serial {
|
||||
compatible = "fsl,pq1-smc";
|
||||
};
|
||||
|
||||
FEC1: fec@0 {
|
||||
compatible = "fsl,pq1-fec1";
|
||||
};
|
||||
|
||||
FEC2: fec@1 {
|
||||
compatible = "fsl,pq1-fec2";
|
||||
};
|
||||
|
||||
soc: immr@ff000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device-type = "soc";
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0xff000000 0x4000>;
|
||||
reg = <0xff000000 0x00000200>;
|
||||
|
||||
CPM1_PIO_B: gpio-controller@ab8 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,cpm1-pario-bank-b";
|
||||
reg = <0xab8 0x10>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
CPM1_PIO_D: gpio-controller@970 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,cpm1-pario-bank-d";
|
||||
reg = <0x970 0x10>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
CPM1_PIO_A: gpio-controller@950 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,cpm1-pario-bank-a";
|
||||
reg = <0x950 0x10>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
CPM1_PIO_C: gpio-controller@960 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,cpm1-pario-bank-c";
|
||||
reg = <0x960 0x10>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
CPM1_PIO_E: gpio-controller@ac8 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,cpm1-pario-bank-e";
|
||||
reg = <0xac8 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
spi: spi@aa0 {
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,mpc8xx-spi";
|
||||
gpios = <&CPM1_PIO_B 21 1>; /* /EEPROM_CS ACTIVE_LOW */
|
||||
|
||||
eeprom@0 {
|
||||
cell-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
12
arch/powerpc/include/asm/arch-mpc8xx/gpio.h
Normal file
12
arch/powerpc/include/asm/arch-mpc8xx/gpio.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
#ifndef _MPC8XX_GPIO_H_
|
||||
#define _MPC8XX_GPIO_H_
|
||||
|
||||
struct mpc8xx_gpio_plat {
|
||||
ulong addr;
|
||||
unsigned long size;
|
||||
uint ngpios;
|
||||
};
|
||||
|
||||
#endif /* MPC8XX_GPIO_H_ */
|
||||
|
|
@ -2,5 +2,7 @@ BOARDS from CS GROUP France
|
|||
M: Christophe Leroy <christophe.leroy@csgroup.eu>
|
||||
S: Maintained
|
||||
F: board/cssi/
|
||||
F: include/configs/MCR3000.h
|
||||
F: include/configs/mcr3000.h
|
||||
F: configs/MCR3000_defconfig
|
||||
F: include/configs/cmpc885.h
|
||||
F: configs/CMPC885_defconfig
|
||||
|
|
|
|||
23
board/cssi/cmpc885/Kconfig
Normal file
23
board/cssi/cmpc885/Kconfig
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
if TARGET_CMPC885
|
||||
|
||||
config SYS_BOARD
|
||||
default "cmpc885"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "cssi"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "cmpc885"
|
||||
|
||||
config TEXT_BASE
|
||||
default 0x40000000
|
||||
|
||||
config CPLD_BASE
|
||||
hex
|
||||
default 0xc8000000
|
||||
|
||||
config FPGA_BASE
|
||||
hex
|
||||
default 0xd0000000
|
||||
|
||||
endif
|
||||
10
board/cssi/cmpc885/Makefile
Normal file
10
board/cssi/cmpc885/Makefile
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2010-2020 CS Group
|
||||
# Charles Frey <charles.frey@c-s.fr>
|
||||
# Christophe Leroy <christophe.leroy@c-s.fr>
|
||||
#
|
||||
|
||||
obj-y += cmpc885.o
|
||||
obj-y += sdram.o
|
||||
obj-$(CONFIG_CMD_NAND) += nand.o
|
||||
1106
board/cssi/cmpc885/cmpc885.c
Normal file
1106
board/cssi/cmpc885/cmpc885.c
Normal file
File diff suppressed because it is too large
Load diff
7
board/cssi/cmpc885/cmpc885.env
Normal file
7
board/cssi/cmpc885/cmpc885.env
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
loadaddr=0x1a00000
|
||||
filename=cmpc885.itb
|
||||
console_args=console=ttyCPM0,115200N8
|
||||
loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr} /boot/${filename};ubifsumount; ubi detach
|
||||
flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; run loadkernel; bootm $loadaddr#$config
|
||||
tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename};bootm $loadaddr#$config
|
||||
update=echo 'Updating ubi image'; if tftp $loadaddr $ubifile; then nand erase.chip; nand write $loadaddr 0x00 $filesize; fi;
|
||||
47
board/cssi/cmpc885/nand.c
Normal file
47
board/cssi/cmpc885/nand.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2010-2020 CS Group
|
||||
* Florent Trinh Thai <florent.trinh-thai@c-s.fr>
|
||||
* Christophe Leroy <christophe.leroy@c-s.fr>
|
||||
* Charles Frey <charles.frey@c-s.fr>
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <nand.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/mtd/rawnand.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define BIT_CLE BIT(3)
|
||||
#define BIT_ALE BIT(2)
|
||||
#define BIT_NCE BIT(0)
|
||||
|
||||
static u32 nand_mask(unsigned int ctrl)
|
||||
{
|
||||
return ((ctrl & NAND_CLE) ? BIT_CLE : 0) |
|
||||
((ctrl & NAND_ALE) ? BIT_ALE : 0) |
|
||||
(!(ctrl & NAND_NCE) ? BIT_NCE : 0);
|
||||
}
|
||||
|
||||
static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
|
||||
{
|
||||
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
struct nand_chip *chip = mtd_to_nand(mtdinfo);
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE)
|
||||
clrsetbits_be16(&immr->im_ioport.iop_pddat,
|
||||
BIT_CLE | BIT_ALE | BIT_NCE, nand_mask(ctrl));
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
out_8(chip->IO_ADDR_W, cmd);
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *chip)
|
||||
{
|
||||
chip->chip_delay = 60;
|
||||
chip->ecc.mode = NAND_ECC_SOFT;
|
||||
chip->cmd_ctrl = nand_hwcontrol;
|
||||
|
||||
return 0;
|
||||
}
|
||||
107
board/cssi/cmpc885/sdram.c
Normal file
107
board/cssi/cmpc885/sdram.c
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 CS Group
|
||||
* Charles Frey <charles.frey@c-s.fr>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <linux/delay.h>
|
||||
#include <init.h>
|
||||
#include <asm/io.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)CONFIG_CPLD_BASE + 3)
|
||||
|
||||
#define _NOT_USED_ 0xFFFFEC04
|
||||
|
||||
static const uint sdram_table[] = {
|
||||
/* DRAM - single read. (offset 0 in upm RAM) */
|
||||
0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x0FFFEC00,
|
||||
0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/* DRAM - burst read. (offset 8 in upm RAM) */
|
||||
0x0F0CEC04, 0x0FFFEC04, 0x00AF2C04, 0x00FFEC00,
|
||||
0x00FFEC00, 0x00FFEC00, 0x0FFCE000, 0x1FFFEC05,
|
||||
|
||||
/* DRAM - Precharge all banks. (offset 16 in upm RAM) */
|
||||
_NOT_USED_, 0x0FFCE004, 0x1FFFEC05, _NOT_USED_,
|
||||
|
||||
/* DRAM - NOP. (offset 20 in upm RAM) */
|
||||
0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/* DRAM - single write. (offset 24 in upm RAM) */
|
||||
0x0F0CEC04, 0x0FFFEC00, 0x00AF2004, 0x0FFFEC04,
|
||||
0x0FFCE004, 0x0FFFEC04, 0xFFFFEC05, _NOT_USED_,
|
||||
|
||||
/* DRAM - burst write. (offset 32 in upm RAM) */
|
||||
0x0F0CEC04, 0x0FFFEC00, 0x00AF2000, 0x00FFEC00,
|
||||
0x00FFEC00, 0x00FFEC04, 0x0FFFEC04, 0x0FFCE004,
|
||||
0x1FFFEC05, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/* refresh (offset 48 in upm RAM) */
|
||||
0x0FFDE404, 0x0FFEAC04, 0x0FFD6C84, 0x0FFFEC04,
|
||||
0x0FFFEC04, 0x0FFFEC04, 0x0FFFEC04, 0x1FFFEC85,
|
||||
|
||||
/* init (offset 56 in upm RAM) */
|
||||
0x0FEEA874, 0x0FBD6474, 0x1FFFEC45, _NOT_USED_,
|
||||
|
||||
/* exception. (offset 60 in upm RAM) */
|
||||
0x0FFCE004, 0xFFFFEC05, _NOT_USED_, _NOT_USED_
|
||||
};
|
||||
|
||||
/* SDRAM initialization */
|
||||
int dram_init(void)
|
||||
{
|
||||
immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
memctl8xx_t __iomem *memctl = &immap->im_memctl;
|
||||
u32 max_size, mamr;
|
||||
u8 val;
|
||||
|
||||
printf("UPMA init for SDRAM (CAS latency 2), ");
|
||||
printf("init address 0x%08x, size ", (int)dram_init);
|
||||
|
||||
/* Verify the SDRAM size of the board */
|
||||
val = (in_8(ADDR_CPLD_R_TYPE) & 0x30) >> 4;
|
||||
|
||||
if (val == 0x03 || val == 0x00) {
|
||||
max_size = 64 * SZ_1M; /* 64 Mo of SDRAM */
|
||||
mamr = 0x20104000;
|
||||
} else {
|
||||
max_size = 128 * SZ_1M; /* 128 Mo of SDRAM */
|
||||
mamr = 0x20206000;
|
||||
}
|
||||
|
||||
/* Configure CS1 */
|
||||
out_be32(&memctl->memc_or1,
|
||||
~(max_size - 1) | OR_CSNT_SAM | OR_ACS_DIV2);
|
||||
out_be32(&memctl->memc_br1, CFG_SYS_SDRAM_BASE | BR_MS_UPMA | BR_V);
|
||||
|
||||
/* Configure UPMA for CS1 */
|
||||
upmconfig(UPMA, (uint *)sdram_table, ARRAY_SIZE(sdram_table));
|
||||
|
||||
out_be16(&memctl->memc_mptpr, MPTPR_PTP_DIV32);
|
||||
/* disable refresh */
|
||||
out_be32(&memctl->memc_mamr, mamr);
|
||||
udelay(100);
|
||||
|
||||
/* NOP to maintain DQM high */
|
||||
out_be32(&memctl->memc_mcr, 0x80002114);
|
||||
udelay(200);
|
||||
|
||||
out_be32(&memctl->memc_mcr, 0x80002111); /* PRECHARGE cmd */
|
||||
out_be32(&memctl->memc_mcr, 0x80002830); /* AUTO REFRESH cmd */
|
||||
out_be32(&memctl->memc_mar, 0x00000088);
|
||||
out_be32(&memctl->memc_mcr, 0x80002138);
|
||||
|
||||
/* Enable refresh */
|
||||
setbits_be32(&memctl->memc_mamr, MAMR_PTAE);
|
||||
|
||||
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, max_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
95
board/cssi/cmpc885/u-boot.lds
Normal file
95
board/cssi/cmpc885/u-boot.lds
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010-2020 CS Group
|
||||
* Christophe Leroy <christophe.leroy@c-s.fr>
|
||||
*
|
||||
* (C) Copyright 2001-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Modified by Yuli Barcohen <yuli@arabellasw.com>
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
arch/powerpc/lib/built-in.o (.text*)
|
||||
drivers/net/built-in.o (.text*)
|
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .;
|
||||
env/embedded.o (.text.environment)
|
||||
|
||||
*(.text)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__u_boot_list : {
|
||||
KEEP(*(SORT(__u_boot_list*)));
|
||||
}
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
/*
|
||||
* _end - This is end of u-boot.bin image.
|
||||
* dtb will be appended here to make u-boot-dtb.bin
|
||||
*/
|
||||
_end = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
ENTRY(_start)
|
||||
|
|
@ -1,13 +1,13 @@
|
|||
if TARGET_MCR3000
|
||||
|
||||
config SYS_BOARD
|
||||
default "MCR3000"
|
||||
default "mcr3000"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "cssi"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "MCR3000"
|
||||
default "mcr3000"
|
||||
|
||||
config TEXT_BASE
|
||||
default 0x04000000
|
||||
|
|
@ -4,5 +4,5 @@
|
|||
# Christophe Leroy <christophe.leroy@c-s.fr>
|
||||
#
|
||||
|
||||
obj-y += MCR3000.o
|
||||
obj-y += mcr3000.o
|
||||
obj-$(CONFIG_CMD_NAND) += nand.o
|
||||
|
|
@ -58,8 +58,6 @@ static const uint cs1_dram_table_66[] = {
|
|||
|
||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
||||
{
|
||||
const char *sync = "receive";
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
/* BRG */
|
||||
|
|
@ -72,16 +70,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
|
|||
/* Bus Frequency for CPM */
|
||||
do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
|
||||
|
||||
/* E1 interface - Set data rate */
|
||||
do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
|
||||
|
||||
/* E1 interface - Set channel phase to 0 */
|
||||
do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
|
||||
|
||||
/* E1 interface - rising edge sync pulse transmit */
|
||||
do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
|
||||
sync, strlen(sync), 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
14
board/cssi/mcr3000/mcr3000.env
Normal file
14
board/cssi/mcr3000/mcr3000.env
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
|
||||
sdram_type=SDRAM
|
||||
flash_type=AM29LV160DB
|
||||
loadaddr=0x1200000
|
||||
filename=mcr3000.itb
|
||||
dhcp_ip=ip=:::::eth0:dhcp
|
||||
console_args=console=ttyCPM0,115200N8
|
||||
loadkernel=ubi part nand0;ubifsmount ubi0;ubifsload ${loadaddr} /boot/${filename};ubifsumount; ubi detach
|
||||
bootcmd=run flashboot
|
||||
flashboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off;${ofl_args}; run loadkernel; bootm ${loadaddr}
|
||||
tftpboot=setenv bootargs ${console_args} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:mcr3k:eth0:off ${ofl_args}; tftp ${loadaddr} ${filename}; bootm ${loadaddr}
|
||||
dhcpboot=dhcp ${loadaddr} ${filename};setenv bootargs ${console_args} ${dhcp_ip} ${ofl_args}; bootm ${loadaddr}
|
||||
update=echo 'Updating ubi image'; if tftp 0x2000 $ubifile; then nand erase.chip; nand write 0x2000 0x00 $filesize; fi
|
||||
110
configs/CMPC885_defconfig
Normal file
110
configs/CMPC885_defconfig
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x2000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="cmpc885"
|
||||
CONFIG_SYS_PROMPT="S3K> "
|
||||
CONFIG_ENV_ADDR=0x40004000
|
||||
CONFIG_MPC8xx=y
|
||||
CONFIG_TARGET_CMPC885=y
|
||||
CONFIG_MPC885=y
|
||||
CONFIG_8xx_GCLK_FREQ=132000000
|
||||
CONFIG_CMD_IMMAP=y
|
||||
CONFIG_SYS_SIUMCR=0x00620000
|
||||
CONFIG_SYS_SYPCR=0xFFFFFF8F
|
||||
CONFIG_SYS_TBSCR=0x00C3
|
||||
CONFIG_SYS_PISCR=0x0000
|
||||
CONFIG_SYS_PLPRCR_BOOL=y
|
||||
CONFIG_SYS_PLPRCR=0x374d4000
|
||||
CONFIG_SYS_SCCR=0x00420000
|
||||
CONFIG_SYS_SCCR_MASK=0x00000000
|
||||
CONFIG_SYS_DER=0x2002000F
|
||||
CONFIG_SYS_MONITOR_LEN=327680
|
||||
CONFIG_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=5
|
||||
CONFIG_AUTOBOOT_KEYED=y
|
||||
CONFIG_AUTOBOOT_PROMPT="\nEnter password - autoboot in %d sec...\n"
|
||||
CONFIG_AUTOBOOT_DELAY_STR="root"
|
||||
CONFIG_USE_BOOTCOMMAND=y
|
||||
CONFIG_BOOTCOMMAND="run flashboot"
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
# CONFIG_CMD_ELF is not set
|
||||
# CONFIG_CMD_GO is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
# CONFIG_CMD_NFS is not set
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_MII_INIT=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_USE_IPADDR=y
|
||||
CONFIG_IPADDR="192.168.0.3"
|
||||
CONFIG_USE_NETMASK=y
|
||||
CONFIG_NETMASK="255.255.255.0"
|
||||
CONFIG_USE_SERVERIP=y
|
||||
CONFIG_SERVERIP="192.168.0.1"
|
||||
# CONFIG_DM_DEVICE_REMOVE is not set
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR0_PRELIM=0x40000801
|
||||
CONFIG_SYS_OR0_PRELIM=0xFFC00924
|
||||
CONFIG_SYS_BR1_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR1_PRELIM=0x00000081
|
||||
CONFIG_SYS_OR1_PRELIM=0xFC000E00
|
||||
CONFIG_SYS_BR2_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR2_PRELIM=0xC0000401
|
||||
CONFIG_SYS_OR2_PRELIM=0xFFFF8142
|
||||
CONFIG_SYS_BR3_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR3_PRELIM=0xE0000801
|
||||
CONFIG_SYS_OR3_PRELIM=0xFF00010A
|
||||
CONFIG_SYS_BR4_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR4_PRELIM=0xD0000801
|
||||
CONFIG_SYS_OR4_PRELIM=0xFC000D08
|
||||
CONFIG_SYS_BR5_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR5_PRELIM=0xC8000801
|
||||
CONFIG_SYS_OR5_PRELIM=0xFFFF8D10
|
||||
CONFIG_SYS_BR6_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR6_PRELIM=0x80000801
|
||||
CONFIG_SYS_OR6_PRELIM=0xFFFF8908
|
||||
CONFIG_SYS_BR7_PRELIM_BOOL=y
|
||||
CONFIG_SYS_BR7_PRELIM=0xF0000001
|
||||
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
|
||||
CONFIG_MPC8XX_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SYS_MAX_FLASH_SECT=71
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_RMII=y
|
||||
CONFIG_MPC8XX_FEC=y
|
||||
CONFIG_FEC1_PHY=1
|
||||
CONFIG_FEC2_PHY=2
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_MPC8XX_SPI=y
|
||||
CONFIG_WDT=y
|
||||
# CONFIG_REGEX is not set
|
||||
CONFIG_LZMA=y
|
||||
|
|
@ -20,6 +20,7 @@ CONFIG_SYS_SCCR=0x00C20000
|
|||
CONFIG_SYS_SCCR_MASK=0x60000000
|
||||
CONFIG_SYS_DER=0x2002000F
|
||||
CONFIG_SYS_MONITOR_LEN=327680
|
||||
CONFIG_FIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_SYS_MONITOR_BASE=0x04000000
|
||||
CONFIG_BOOTDELAY=5
|
||||
|
|
@ -36,11 +37,12 @@ CONFIG_HUSH_PARSER=y
|
|||
CONFIG_SYS_PBSIZE=278
|
||||
# CONFIG_CMD_BDI is not set
|
||||
# CONFIG_CMD_CONSOLE is not set
|
||||
CONFIG_SYS_BOOTM_LEN=0x800000
|
||||
CONFIG_SYS_BOOTM_LEN=0x2000000
|
||||
# CONFIG_CMD_IMI is not set
|
||||
CONFIG_CMD_ASKENV=y
|
||||
# CONFIG_CMD_LOADB is not set
|
||||
# CONFIG_CMD_LOADS is not set
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_ECHO is not set
|
||||
# CONFIG_CMD_ITEST is not set
|
||||
|
|
@ -51,6 +53,8 @@ CONFIG_CMD_MII=y
|
|||
CONFIG_MII_INIT=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_SLEEP is not set
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
|
|
@ -58,7 +62,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|||
CONFIG_USE_IPADDR=y
|
||||
CONFIG_IPADDR="192.168.0.3"
|
||||
CONFIG_USE_NETMASK=y
|
||||
CONFIG_NETMASK="255.0.0.0"
|
||||
CONFIG_NETMASK="255.255.255.0"
|
||||
CONFIG_USE_SERVERIP=y
|
||||
CONFIG_SERVERIP="192.168.0.1"
|
||||
CONFIG_SYS_BR0_PRELIM_BOOL=y
|
||||
|
|
@ -87,6 +91,7 @@ CONFIG_SYS_BR7_PRELIM=0x1C000001
|
|||
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_FLASH_SHOW_PROGRESS=0
|
||||
|
|
@ -97,5 +102,4 @@ CONFIG_MPC8XX_FEC=y
|
|||
# CONFIG_PCI is not set
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_WDT=y
|
||||
CONFIG_SHA256=y
|
||||
CONFIG_LZMA=y
|
||||
|
|
|
|||
|
|
@ -547,6 +547,13 @@ config MPC8XXX_GPIO
|
|||
value setting, the open-drain feature, which can configure individual
|
||||
GPIOs to work as open-drain outputs, is supported.
|
||||
|
||||
config MPC8XX_GPIO
|
||||
bool "Freescale MPC8XX GPIO driver"
|
||||
depends on DM_GPIO
|
||||
help
|
||||
This driver supports parallel IO ports from MPC8XX CPUs.
|
||||
Each GPIO bank is identified by its own entry in the device tree.
|
||||
|
||||
config MPC83XX_SPISEL_BOOT
|
||||
bool "Freescale MPC83XX SPISEL_BOOT driver"
|
||||
depends on DM_GPIO && ARCH_MPC830X
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o
|
|||
obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
|
||||
obj-$(CONFIG_ALTERA_PIO) += altera_pio.o
|
||||
obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o
|
||||
obj-$(CONFIG_MPC8XX_GPIO) += mpc8xx_gpio.o
|
||||
obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o
|
||||
obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
|
||||
obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o
|
||||
|
|
|
|||
347
drivers/gpio/mpc8xx_gpio.c
Normal file
347
drivers/gpio/mpc8xx_gpio.c
Normal file
|
|
@ -0,0 +1,347 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* (C) Copyright 2020 CS Group
|
||||
* Charles Frey <charles.frey@c-s.fr>
|
||||
*
|
||||
* based on driver/gpio/mpc8xxx_gpio.c, which is
|
||||
* Copyright 2016 Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
|
||||
*
|
||||
* based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
|
||||
* Copyright 2010 eXMeritus, A Boeing Company
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm.h>
|
||||
#include <mapmem.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <malloc.h>
|
||||
|
||||
enum {
|
||||
MPC8XX_CPM1_PORTA,
|
||||
MPC8XX_CPM1_PORTB,
|
||||
MPC8XX_CPM1_PORTC,
|
||||
MPC8XX_CPM1_PORTD,
|
||||
MPC8XX_CPM1_PORTE,
|
||||
};
|
||||
|
||||
/*
|
||||
* The MPC885 CPU CPM has 5 I/O ports, and each ports has different
|
||||
* register length : 16 bits for ports A,C,D and 32 bits for ports
|
||||
* B and E.
|
||||
*
|
||||
* This structure allows us to select the accessors according to the
|
||||
* port we are configuring.
|
||||
*/
|
||||
struct mpc8xx_gpio_data {
|
||||
/* The bank's register base in memory */
|
||||
void __iomem *base;
|
||||
/* The address of the registers; used to identify the bank */
|
||||
ulong addr;
|
||||
/* The GPIO count of the bank */
|
||||
uint gpio_count;
|
||||
/* Type needed to use the correct accessors */
|
||||
int type;
|
||||
};
|
||||
|
||||
/* Structure for ports A, C, D */
|
||||
struct iop_16 {
|
||||
u16 pdir;
|
||||
u16 ppar;
|
||||
u16 podr;
|
||||
u16 pdat;
|
||||
};
|
||||
|
||||
/* Port B */
|
||||
struct iop_32_b {
|
||||
u32 pdir;
|
||||
u32 ppar;
|
||||
u32 podr;
|
||||
u32 pdat;
|
||||
};
|
||||
|
||||
/* Port E */
|
||||
struct iop_32_e {
|
||||
u32 pdir;
|
||||
u32 ppar;
|
||||
u32 psor;
|
||||
u32 podr;
|
||||
u32 pdat;
|
||||
};
|
||||
|
||||
union iop_32 {
|
||||
struct iop_32_b b;
|
||||
struct iop_32_e e;
|
||||
};
|
||||
|
||||
inline u32 gpio_mask(uint gpio, int type)
|
||||
{
|
||||
if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
|
||||
return 1U << (31 - (gpio));
|
||||
else
|
||||
return 1U << (15 - (gpio));
|
||||
}
|
||||
|
||||
static inline u16 gpio16_get_val(void __iomem *base, u16 mask, int type)
|
||||
{
|
||||
struct iop_16 *regs = base;
|
||||
|
||||
return in_be16(®s->pdat) & mask;
|
||||
}
|
||||
|
||||
static inline u16 gpio16_get_dir(void __iomem *base, u16 mask, int type)
|
||||
{
|
||||
struct iop_16 *regs = base;
|
||||
|
||||
return in_be16(®s->pdir) & mask;
|
||||
}
|
||||
|
||||
static inline void gpio16_set_in(void __iomem *base, u16 gpios, int type)
|
||||
{
|
||||
struct iop_16 *regs = base;
|
||||
|
||||
clrbits_be16(®s->pdat, gpios);
|
||||
/* GPDIR register 0 -> input */
|
||||
clrbits_be16(®s->pdir, gpios);
|
||||
}
|
||||
|
||||
static inline void gpio16_set_lo(void __iomem *base, u16 gpios, int type)
|
||||
{
|
||||
struct iop_16 *regs = base;
|
||||
|
||||
clrbits_be16(®s->pdat, gpios);
|
||||
/* GPDIR register 1 -> output */
|
||||
setbits_be16(®s->pdir, gpios);
|
||||
}
|
||||
|
||||
static inline void gpio16_set_hi(void __iomem *base, u16 gpios, int type)
|
||||
{
|
||||
struct iop_16 *regs = base;
|
||||
|
||||
setbits_be16(®s->pdat, gpios);
|
||||
/* GPDIR register 1 -> output */
|
||||
setbits_be16(®s->pdir, gpios);
|
||||
}
|
||||
|
||||
/* PORT B AND E */
|
||||
static inline u32 gpio32_get_val(void __iomem *base, u32 mask, int type)
|
||||
{
|
||||
union iop_32 __iomem *regs = base;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB)
|
||||
return in_be32(®s->b.pdat) & mask;
|
||||
else
|
||||
return in_be32(®s->e.pdat) & mask;
|
||||
}
|
||||
|
||||
static inline u32 gpio32_get_dir(void __iomem *base, u32 mask, int type)
|
||||
{
|
||||
union iop_32 __iomem *regs = base;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB)
|
||||
return in_be32(®s->b.pdir) & mask;
|
||||
else
|
||||
return in_be32(®s->e.pdir) & mask;
|
||||
}
|
||||
|
||||
static inline void gpio32_set_in(void __iomem *base, u32 gpios, int type)
|
||||
{
|
||||
union iop_32 __iomem *regs = base;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB) {
|
||||
clrbits_be32(®s->b.pdat, gpios);
|
||||
/* GPDIR register 0 -> input */
|
||||
clrbits_be32(®s->b.pdir, gpios);
|
||||
} else { /* Port E */
|
||||
clrbits_be32(®s->e.pdat, gpios);
|
||||
/* GPDIR register 0 -> input */
|
||||
clrbits_be32(®s->e.pdir, gpios);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio32_set_lo(void __iomem *base, u32 gpios, int type)
|
||||
{
|
||||
union iop_32 __iomem *regs = base;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB) {
|
||||
clrbits_be32(®s->b.pdat, gpios);
|
||||
/* GPDIR register 1 -> output */
|
||||
setbits_be32(®s->b.pdir, gpios);
|
||||
} else {
|
||||
clrbits_be32(®s->e.pdat, gpios);
|
||||
/* GPDIR register 1 -> output */
|
||||
setbits_be32(®s->e.pdir, gpios);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio32_set_hi(void __iomem *base, u32 gpios, int type)
|
||||
{
|
||||
union iop_32 __iomem *regs = base;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB) {
|
||||
setbits_be32(®s->b.pdat, gpios);
|
||||
/* GPDIR register 1 -> output */
|
||||
setbits_be32(®s->b.pdir, gpios);
|
||||
} else {
|
||||
setbits_be32(®s->e.pdat, gpios);
|
||||
/* GPDIR register 1 -> output */
|
||||
setbits_be32(®s->e.pdir, gpios);
|
||||
}
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_direction_input(struct udevice *dev, uint gpio)
|
||||
{
|
||||
struct mpc8xx_gpio_data *data = dev_get_priv(dev);
|
||||
int type = data->type;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
|
||||
gpio32_set_in(data->base, gpio_mask(gpio, type), type);
|
||||
else
|
||||
gpio16_set_in(data->base, gpio_mask(gpio, type), type);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_set_value(struct udevice *dev, uint gpio, int value)
|
||||
{
|
||||
struct mpc8xx_gpio_data *data = dev_get_priv(dev);
|
||||
int type = data->type;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE) {
|
||||
if (value)
|
||||
gpio32_set_hi(data->base, gpio_mask(gpio, type), type);
|
||||
else
|
||||
gpio32_set_lo(data->base, gpio_mask(gpio, type), type);
|
||||
} else {
|
||||
if (value)
|
||||
gpio16_set_hi(data->base, gpio_mask(gpio, type), type);
|
||||
else
|
||||
gpio16_set_lo(data->base, gpio_mask(gpio, type), type);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_direction_output(struct udevice *dev, uint gpio,
|
||||
int value)
|
||||
{
|
||||
return mpc8xx_gpio_set_value(dev, gpio, value);
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_get_value(struct udevice *dev, uint gpio)
|
||||
{
|
||||
struct mpc8xx_gpio_data *data = dev_get_priv(dev);
|
||||
int type = data->type;
|
||||
|
||||
/* Input -> read value from GPDAT register */
|
||||
if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
|
||||
return gpio32_get_val(data->base, gpio_mask(gpio, type), type);
|
||||
else
|
||||
return gpio16_get_val(data->base, gpio_mask(gpio, type), type);
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_get_function(struct udevice *dev, uint gpio)
|
||||
{
|
||||
struct mpc8xx_gpio_data *data = dev_get_priv(dev);
|
||||
int type = data->type;
|
||||
int dir;
|
||||
|
||||
if (type == MPC8XX_CPM1_PORTB || type == MPC8XX_CPM1_PORTE)
|
||||
dir = gpio32_get_dir(data->base, gpio_mask(gpio, type), type);
|
||||
else
|
||||
dir = gpio16_get_dir(data->base, gpio_mask(gpio, type), type);
|
||||
return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct mpc8xx_gpio_plat *plat = dev_get_plat(dev);
|
||||
fdt_addr_t addr;
|
||||
u32 reg[2];
|
||||
|
||||
dev_read_u32_array(dev, "reg", reg, 2);
|
||||
addr = dev_translate_address(dev, reg);
|
||||
|
||||
plat->addr = addr;
|
||||
plat->size = reg[1];
|
||||
plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_platdata_to_priv(struct udevice *dev)
|
||||
{
|
||||
struct mpc8xx_gpio_data *priv = dev_get_priv(dev);
|
||||
struct mpc8xx_gpio_plat *plat = dev_get_plat(dev);
|
||||
unsigned long size = plat->size;
|
||||
int type;
|
||||
|
||||
if (size == 0)
|
||||
size = 0x100;
|
||||
|
||||
priv->addr = plat->addr;
|
||||
priv->base = map_sysmem(plat->addr, size);
|
||||
|
||||
if (!priv->base)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->gpio_count = plat->ngpios;
|
||||
|
||||
type = dev_get_driver_data(dev);
|
||||
|
||||
if ((type == MPC8XX_CPM1_PORTA || type == MPC8XX_CPM1_PORTC ||
|
||||
type == MPC8XX_CPM1_PORTD) && plat->ngpios == 32)
|
||||
priv->gpio_count = 16;
|
||||
|
||||
priv->type = type;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_gpio_probe(struct udevice *dev)
|
||||
{
|
||||
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct mpc8xx_gpio_data *data = dev_get_priv(dev);
|
||||
char name[32], *str;
|
||||
|
||||
mpc8xx_gpio_platdata_to_priv(dev);
|
||||
|
||||
snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
|
||||
str = strdup(name);
|
||||
|
||||
if (!str)
|
||||
return -ENOMEM;
|
||||
|
||||
uc_priv->bank_name = str;
|
||||
uc_priv->gpio_count = data->gpio_count;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_gpio_ops gpio_mpc8xx_ops = {
|
||||
.direction_input = mpc8xx_gpio_direction_input,
|
||||
.direction_output = mpc8xx_gpio_direction_output,
|
||||
.get_value = mpc8xx_gpio_get_value,
|
||||
.set_value = mpc8xx_gpio_set_value,
|
||||
.get_function = mpc8xx_gpio_get_function,
|
||||
};
|
||||
|
||||
static const struct udevice_id mpc8xx_gpio_ids[] = {
|
||||
{ .compatible = "fsl,cpm1-pario-bank-a", .data = MPC8XX_CPM1_PORTA },
|
||||
{ .compatible = "fsl,cpm1-pario-bank-b", .data = MPC8XX_CPM1_PORTB },
|
||||
{ .compatible = "fsl,cpm1-pario-bank-c", .data = MPC8XX_CPM1_PORTC },
|
||||
{ .compatible = "fsl,cpm1-pario-bank-d", .data = MPC8XX_CPM1_PORTD },
|
||||
{ .compatible = "fsl,cpm1-pario-bank-e", .data = MPC8XX_CPM1_PORTE },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(gpio_mpc8xx) = {
|
||||
.name = "gpio_mpc8xx",
|
||||
.id = UCLASS_GPIO,
|
||||
.ops = &gpio_mpc8xx_ops,
|
||||
.of_to_plat = mpc8xx_gpio_ofdata_to_platdata,
|
||||
.plat_auto = sizeof(struct mpc8xx_gpio_plat),
|
||||
.of_match = mpc8xx_gpio_ids,
|
||||
.probe = mpc8xx_gpio_probe,
|
||||
.priv_auto = sizeof(struct mpc8xx_gpio_data),
|
||||
};
|
||||
|
|
@ -24,12 +24,29 @@
|
|||
|
||||
#include <asm/cpm_8xx.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#define CPM_SPI_BASE_RX CPM_SPI_BASE
|
||||
#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
|
||||
|
||||
#define MAX_BUFFER 0x104
|
||||
|
||||
struct mpc8xx_priv {
|
||||
spi_t __iomem *spi;
|
||||
struct gpio_desc gpios[16];
|
||||
int max_cs;
|
||||
};
|
||||
|
||||
static int mpc8xx_spi_set_mode(struct udevice *dev, uint mod)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_spi_set_speed(struct udevice *dev, uint speed)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_spi_probe(struct udevice *dev)
|
||||
{
|
||||
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
|
||||
|
|
@ -38,42 +55,9 @@ static int mpc8xx_spi_probe(struct udevice *dev)
|
|||
cbd_t __iomem *tbdf, *rbdf;
|
||||
|
||||
/* Disable relocation */
|
||||
out_be16(&spi->spi_rpbase, 0);
|
||||
out_be16(&spi->spi_rpbase, 0x1d80);
|
||||
|
||||
/* 1 */
|
||||
/* ------------------------------------------------
|
||||
* Initialize Port B SPI pins -> page 34-8 MPC860UM
|
||||
* (we are only in Master Mode !)
|
||||
* ------------------------------------------------ */
|
||||
|
||||
/* --------------------------------------------
|
||||
* GPIO or per. Function
|
||||
* PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
|
||||
* PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
|
||||
* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
|
||||
* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
|
||||
* -------------------------------------------- */
|
||||
clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
|
||||
|
||||
/* ----------------------------------------------
|
||||
* In/Out or per. Function 0/1
|
||||
* PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
|
||||
* PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
|
||||
* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
|
||||
* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
|
||||
* ---------------------------------------------- */
|
||||
setbits_be32(&cp->cp_pbdir, 0x0000000F);
|
||||
|
||||
/* ----------------------------------------------
|
||||
* open drain or active output
|
||||
* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
|
||||
* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
|
||||
* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
|
||||
* PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
|
||||
* ---------------------------------------------- */
|
||||
|
||||
clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
|
||||
|
||||
/* Initialize the parameter ram.
|
||||
* We need to make sure many things are initialized to zero
|
||||
*/
|
||||
|
|
@ -143,6 +127,22 @@ static int mpc8xx_spi_probe(struct udevice *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void mpc8xx_spi_cs_activate(struct udevice *dev)
|
||||
{
|
||||
struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
|
||||
struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
|
||||
|
||||
dm_gpio_set_value(&priv->gpios[platdata->cs], 1);
|
||||
}
|
||||
|
||||
static void mpc8xx_spi_cs_deactivate(struct udevice *dev)
|
||||
{
|
||||
struct mpc8xx_priv *priv = dev_get_priv(dev->parent);
|
||||
struct dm_spi_slave_plat *platdata = dev_get_parent_plat(dev);
|
||||
|
||||
dm_gpio_set_value(&priv->gpios[platdata->cs], 0);
|
||||
}
|
||||
|
||||
static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
||||
const void *dout, void *din, unsigned long flags)
|
||||
{
|
||||
|
|
@ -159,7 +159,8 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|||
rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
|
||||
|
||||
/* Set CS for device */
|
||||
clrbits_be32(&cp->cp_pbdat, 0x0001);
|
||||
if (flags & SPI_XFER_BEGIN)
|
||||
mpc8xx_spi_cs_activate(dev);
|
||||
|
||||
/* Setting tx bd status and data length */
|
||||
out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
|
||||
|
|
@ -186,21 +187,40 @@ static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
|
|||
for (tm = 0; tm < 1000; ++tm) {
|
||||
if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
|
||||
break;
|
||||
|
||||
if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
if (tm >= 1000)
|
||||
printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
|
||||
|
||||
/* Clear CS for device */
|
||||
setbits_be32(&cp->cp_pbdat, 0x0001);
|
||||
if (flags & SPI_XFER_END)
|
||||
mpc8xx_spi_cs_deactivate(dev);
|
||||
|
||||
return count;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc8xx_spi_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct mpc8xx_priv *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
|
||||
ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
priv->max_cs = ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
static const struct dm_spi_ops mpc8xx_spi_ops = {
|
||||
.xfer = mpc8xx_spi_xfer,
|
||||
.set_speed = mpc8xx_spi_set_speed,
|
||||
.set_mode = mpc8xx_spi_set_mode,
|
||||
};
|
||||
|
||||
static const struct udevice_id mpc8xx_spi_ids[] = {
|
||||
|
|
@ -212,6 +232,8 @@ U_BOOT_DRIVER(mpc8xx_spi) = {
|
|||
.name = "mpc8xx_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = mpc8xx_spi_ids,
|
||||
.of_to_plat = mpc8xx_spi_ofdata_to_platdata,
|
||||
.ops = &mpc8xx_spi_ops,
|
||||
.probe = mpc8xx_spi_probe,
|
||||
.priv_auto = sizeof(struct mpc8xx_priv),
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,83 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 CS Systemes d'Information
|
||||
* Christophe Leroy <christophe.leroy@c-s.fr>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
"sdram_type=SDRAM\0" \
|
||||
"flash_type=AM29LV160DB\0" \
|
||||
"loadaddr=0x400000\0" \
|
||||
"filename=uImage.lzma\0" \
|
||||
"nfsroot=/opt/ofs\0" \
|
||||
"dhcp_ip=ip=:::::eth0:dhcp\0" \
|
||||
"console_args=console=ttyCPM0,115200N8\0" \
|
||||
"flashboot=setenv bootargs " \
|
||||
"${console_args} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
|
||||
"mcr3k:eth0:off;" \
|
||||
"${ofl_args}; " \
|
||||
"bootm 0x04060000 - 0x04050000\0" \
|
||||
"tftpboot=setenv bootargs " \
|
||||
"${console_args} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
|
||||
"mcr3k:eth0:off " \
|
||||
"${ofl_args}; " \
|
||||
"tftp ${loadaddr} ${filename};" \
|
||||
"tftp 0xf00000 mcr3000.dtb;" \
|
||||
"bootm ${loadaddr} - 0xf00000\0" \
|
||||
"netboot=dhcp ${loadaddr} ${filename};" \
|
||||
"tftp 0xf00000 mcr3000.dtb;" \
|
||||
"setenv bootargs " \
|
||||
"root=/dev/nfs rw " \
|
||||
"${console_args} " \
|
||||
"${dhcp_ip};" \
|
||||
"bootm ${loadaddr} - 0xf00000\0" \
|
||||
"nfsboot=setenv bootargs " \
|
||||
"root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \
|
||||
"${console_args} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
|
||||
"mcr3k:eth0:off;" \
|
||||
"bootm 0x04060000 - 0x04050000\0" \
|
||||
"dhcpboot=dhcp ${loadaddr} ${filename};" \
|
||||
"tftp 0xf00000 mcr3000.dtb;" \
|
||||
"setenv bootargs " \
|
||||
"${console_args} " \
|
||||
"${dhcp_ip} " \
|
||||
"${ofl_args}; " \
|
||||
"bootm ${loadaddr} - 0xf00000\0"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
||||
/* Definitions for initial stack pointer and data area (in DPRAM) */
|
||||
#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
|
||||
#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
|
||||
|
||||
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
|
||||
#define CFG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
/* FLASH organization */
|
||||
#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/* Environment Configuration */
|
||||
|
||||
/* environment is in FLASH */
|
||||
|
||||
/* Ethernet configuration part */
|
||||
|
||||
/* NAND configuration part */
|
||||
#define CFG_SYS_NAND_BASE 0x0C000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
29
include/configs/cmpc885.h
Normal file
29
include/configs/cmpc885.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2022 CS Group
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* Definitions for initial stack pointer and data area (in DPRAM) */
|
||||
#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
|
||||
#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
|
||||
|
||||
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
|
||||
#define CFG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
/* FLASH Configuration */
|
||||
#define CFG_SYS_FLASH_BASE 0x40000000
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 24 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_SYS_BOOTMAPSZ (32 << 20)
|
||||
|
||||
/* NAND configuration part */
|
||||
#define CFG_SYS_NAND_BASE 0xC0000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
40
include/configs/mcr3000.h
Normal file
40
include/configs/mcr3000.h
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 CS Systemes d'Information
|
||||
* Christophe Leroy <christophe.leroy@c-s.fr>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
||||
/* Definitions for initial stack pointer and data area (in DPRAM) */
|
||||
#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
|
||||
#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
|
||||
|
||||
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
|
||||
#define CFG_SYS_SDRAM_BASE 0x00000000
|
||||
|
||||
/* FLASH organization */
|
||||
#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 32 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_SYS_BOOTMAPSZ (32 << 20)
|
||||
|
||||
/* Environment Configuration */
|
||||
|
||||
/* environment is in FLASH */
|
||||
|
||||
/* Ethernet configuration part */
|
||||
|
||||
/* NAND configuration part */
|
||||
#define CFG_SYS_NAND_BASE 0x0C000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue