arm: timer: factor out FSL arch timer erratum workaround
At the moment we have the workaround for the Freescale arch timer erratum A-008585 merged into the generic timer_read_counter() routine. Split those two up, so that we can add other errata workaround more easily. Also add an explaining comment on the way. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Andreas Färber <afaerber@suse.de> Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
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1 changed files with 25 additions and 6 deletions
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@ -20,27 +20,46 @@ unsigned long get_tbclk(void)
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return cntfrq;
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
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/*
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* Generic timer implementation of timer_read_counter()
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* FSL erratum A-008585 says that the ARM generic timer counter "has the
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* potential to contain an erroneous value for a small number of core
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* clock cycles every time the timer value changes".
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* This sometimes leads to a consecutive counter read returning a lower
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* value than the previous one, thus reporting the time to go backwards.
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* The workaround is to read the counter twice and only return when the value
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* was the same in both reads.
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* Assumes that the CPU runs in much higher frequency than the timer.
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*/
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unsigned long timer_read_counter(void)
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{
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unsigned long cntpct;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
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/* This erratum number needs to be confirmed to match ARM document */
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unsigned long temp;
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#endif
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isb();
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
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asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
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while (temp != cntpct) {
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
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}
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#endif
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return cntpct;
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}
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#else
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/*
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* timer_read_counter() using the Arm Generic Timer (aka arch timer).
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*/
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unsigned long timer_read_counter(void)
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{
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unsigned long cntpct;
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isb();
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asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
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return cntpct;
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}
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#endif
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uint64_t get_ticks(void)
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{
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