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ARM: t20/t30: swap host1x and disp1 clock parents

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According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This commit is contained in:
Svyatoslav Ryhel 2023-02-14 19:35:24 +02:00 committed by Tom
parent fca18a2643
commit 2fafac30ef
2 changed files with 4 additions and 4 deletions
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4
arch/arm/mach-tegra/tegra20/clock.c
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@ -760,8 +760,8 @@ struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },

4
arch/arm/mach-tegra/tegra30/clock.c
View file

@ -799,8 +799,8 @@ struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_HOST1X, CLOCK_ID_CGENERAL },
{ PERIPH_ID_DISP1, CLOCK_ID_PERIPH },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },