Merge branch 'next' of git://git.denx.de/u-boot-video
This commit is contained in:
Tom Rini
commit
2dc5b553b9
9 changed files with 657 additions and 6 deletions
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@ -14,6 +14,27 @@ config DM_VIDEO
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option compiles in the video uclass and routes all LCD/video access
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through this.
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config BACKLIGHT_PWM
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bool "Generic PWM based Backlight Driver"
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depends on DM_VIDEO && DM_PWM
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default y
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help
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If you have a LCD backlight adjustable by PWM, say Y to enable
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this driver.
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This driver can be use with "simple-panel" and
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it understands the standard device tree
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(leds/backlight/pwm-backlight.txt)
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config BACKLIGHT_GPIO
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bool "Generic GPIO based Backlight Driver"
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depends on DM_VIDEO
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help
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If you have a LCD backlight adjustable by GPIO, say Y to enable
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this driver.
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This driver can be used with "simple-panel" and
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it understands the standard device tree
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(leds/backlight/gpio-backlight.txt)
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config VIDEO_BPP8
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bool "Support 8-bit-per-pixel displays"
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depends on DM_VIDEO
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@ -98,6 +119,14 @@ config SYS_WHITE_ON_BLACK
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better in low-light situations or to reduce eye strain in some
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cases.
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config NO_FB_CLEAR
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bool "Skip framebuffer clear"
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help
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If firmware (whatever loads u-boot) has already put a splash image
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on screen, you might want to preserve it until whatever u-boot
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loads takes over the screen. This, for example, can be used to
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keep splash image on screen until grub graphical boot menu starts.
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source "drivers/video/fonts/Kconfig"
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config VIDCONSOLE_AS_LCD
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@ -436,6 +465,8 @@ config VIDEO_SANDBOX_SDL
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console device and can display stdout output. Within U-Boot is is
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a normal bitmap display and can display images as well as text.
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source "drivers/video/stm32/Kconfig"
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config VIDEO_TEGRA20
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bool "Enable LCD support on Tegra20"
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depends on OF_CONTROL
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@ -601,4 +632,14 @@ config VIDEO_DW_HDMI
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rather requires a SoC-specific glue driver to call it), it
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can not be enabled from the configuration menu.
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config VIDEO_SIMPLE
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bool "Simple display driver for preconfigured display"
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help
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Enables a simple generic display driver which utilizes the
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simple-framebuffer devicetree bindings.
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This driver assumes that the display hardware has been initialized
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before u-boot starts, and u-boot will simply render to the pre-
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allocated frame buffer surface.
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endmenu
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@ -11,9 +11,8 @@ obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
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obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
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obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
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obj-$(CONFIG_DM_VIDEO) += video_bmp.o
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ifdef CONFIG_DM_VIDEO
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obj-$(CONFIG_DM_PWM) += pwm_backlight.o
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endif
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obj-$(CONFIG_BACKLIGHT_PWM) += pwm_backlight.o
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obj-$(CONFIG_BACKLIGHT_GPIO) += backlight_gpio.o
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obj-$(CONFIG_CONSOLE_NORMAL) += console_normal.o
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obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
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obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
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@ -53,10 +52,11 @@ obj-$(CONFIG_FORMIKE) += formike.o
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obj-$(CONFIG_LG4573) += lg4573.o
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obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
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obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
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obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
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obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
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obj-${CONFIG_EXYNOS_FB} += exynos/
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obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
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obj-${CONFIG_VIDEO_STM32} += stm32/
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obj-y += bridge/
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obj-y += sunxi/
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74
drivers/video/backlight_gpio.c
Normal file
74
drivers/video/backlight_gpio.c
Normal file
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@ -0,0 +1,74 @@
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author: Patrick Delaunay <patrick.delaunay@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <backlight.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct gpio_backlight_priv {
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struct gpio_desc gpio;
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bool def_value;
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};
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static int gpio_backlight_enable(struct udevice *dev)
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{
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struct gpio_backlight_priv *priv = dev_get_priv(dev);
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dm_gpio_set_value(&priv->gpio, 1);
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return 0;
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}
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static int gpio_backlight_ofdata_to_platdata(struct udevice *dev)
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{
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struct gpio_backlight_priv *priv = dev_get_priv(dev);
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int ret;
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ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio,
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GPIOD_IS_OUT);
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if (ret) {
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debug("%s: Warning: cannot get GPIO: ret=%d\n",
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__func__, ret);
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return ret;
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}
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priv->def_value = dev_read_bool(dev, "default-on");
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return 0;
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}
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static int gpio_backlight_probe(struct udevice *dev)
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{
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struct gpio_backlight_priv *priv = dev_get_priv(dev);
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if (priv->def_value)
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gpio_backlight_enable(dev);
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return 0;
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}
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static const struct backlight_ops gpio_backlight_ops = {
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.enable = gpio_backlight_enable,
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};
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static const struct udevice_id gpio_backlight_ids[] = {
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{ .compatible = "gpio-backlight" },
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{ }
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};
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U_BOOT_DRIVER(gpio_backlight) = {
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.name = "gpio_backlight",
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.id = UCLASS_PANEL_BACKLIGHT,
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.of_match = gpio_backlight_ids,
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.ops = &gpio_backlight_ops,
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.ofdata_to_platdata = gpio_backlight_ofdata_to_platdata,
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.probe = gpio_backlight_probe,
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.priv_auto_alloc_size = sizeof(struct gpio_backlight_priv),
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};
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@ -2081,7 +2081,8 @@ static int cfg_video_init(void)
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}
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eorx = fgx ^ bgx;
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video_clear();
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if (!CONFIG_IS_ENABLED(NO_FB_CLEAR))
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video_clear();
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#ifdef CONFIG_VIDEO_LOGO
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/* Plot the logo and get start point of console */
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73
drivers/video/simplefb.c
Normal file
73
drivers/video/simplefb.c
Normal file
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@ -0,0 +1,73 @@
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/*
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* (C) Copyright 2017 Rob Clark
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <fdt_support.h>
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#include <video.h>
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static int simple_video_probe(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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const void *blob = gd->fdt_blob;
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const int node = dev_of_offset(dev);
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const char *format;
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fdt_addr_t base;
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fdt_size_t size;
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base = fdtdec_get_addr_size_auto_parent(blob, dev_of_offset(dev->parent),
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node, "reg", 0, &size, false);
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if (base == FDT_ADDR_T_NONE) {
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debug("%s: Failed to decode memory region\n", __func__);
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return -EINVAL;
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}
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debug("%s: base=%llx, size=%llu\n", __func__, base, size);
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/*
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* TODO is there some way to reserve the framebuffer
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* region so it isn't clobbered?
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*/
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plat->base = base;
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plat->size = size;
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video_set_flush_dcache(dev, true);
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debug("%s: Query resolution...\n", __func__);
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uc_priv->xsize = fdtdec_get_uint(blob, node, "width", 0);
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uc_priv->ysize = fdtdec_get_uint(blob, node, "height", 0);
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uc_priv->rot = 0;
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format = fdt_getprop(blob, node, "format", NULL);
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debug("%s: %dx%d@%s\n", __func__, uc_priv->xsize, uc_priv->ysize, format);
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if (strcmp(format, "r5g6b5") == 0) {
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uc_priv->bpix = VIDEO_BPP16;
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} else if (strcmp(format, "a8b8g8r8") == 0) {
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uc_priv->bpix = VIDEO_BPP32;
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} else {
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printf("%s: invalid format: %s\n", __func__, format);
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return -EINVAL;
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}
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return 0;
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}
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static const struct udevice_id simple_video_ids[] = {
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{ .compatible = "simple-framebuffer" },
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{ }
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};
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U_BOOT_DRIVER(simple_video) = {
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.name = "simple_video",
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.id = UCLASS_VIDEO,
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.of_match = simple_video_ids,
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.probe = simple_video_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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44
drivers/video/stm32/Kconfig
Normal file
44
drivers/video/stm32/Kconfig
Normal file
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@ -0,0 +1,44 @@
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#
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# Copyright (C) STMicroelectronics SA 2017
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#
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# Authors: Philippe Cornu <philippe.cornu@st.com>
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# Yannick Fertre <yannick.fertre@st.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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menuconfig VIDEO_STM32
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bool "Enable STM32 video support"
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depends on DM_VIDEO
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help
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STM32 supports many video output options including RGB and
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DSI. This option enables these supports which can be used on
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devices which have RGB TFT or DSI display connected.
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config VIDEO_STM32_MAX_XRES
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int "Maximum horizontal resolution (for memory allocation purposes)"
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depends on VIDEO_STM32
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default 640
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help
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The maximum horizontal resolution to support for the framebuffer.
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This configuration is used for reserving/allocating memory for the
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framebuffer during device-model binding/probing.
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config VIDEO_STM32_MAX_YRES
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int "Maximum vertical resolution (for memory allocation purposes)"
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depends on VIDEO_STM32
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default 480
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help
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The maximum vertical resolution to support for the framebuffer.
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This configuration is used for reserving/allocating memory for the
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framebuffer during device-model binding/probing.
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config VIDEO_STM32_MAX_BPP
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int "Maximum bits per pixel (for memory allocation purposes)"
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depends on VIDEO_STM32
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default 16
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help
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The maximum bits per pixel to support for the framebuffer.
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This configuration is used for reserving/allocating memory for the
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framebuffer during device-model binding/probing.
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10
drivers/video/stm32/Makefile
Normal file
10
drivers/video/stm32/Makefile
Normal file
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@ -0,0 +1,10 @@
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#
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# Copyright (C) STMicroelectronics SA 2017
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#
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# Authors: Philippe Cornu <philippe.cornu@st.com>
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# Yannick Fertre <yannick.fertre@st.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
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406
drivers/video/stm32/stm32_ltdc.c
Normal file
406
drivers/video/stm32/stm32_ltdc.c
Normal file
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@ -0,0 +1,406 @@
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/*
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* Copyright (C) STMicroelectronics SA 2017
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*
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* Authors: Philippe Cornu <philippe.cornu@st.com>
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* Yannick Fertre <yannick.fertre@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <panel.h>
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#include <video.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <dm/device-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct stm32_ltdc_priv {
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void __iomem *regs;
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struct display_timing timing;
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enum video_log2_bpp l2bpp;
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u32 bg_col_argb;
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u32 crop_x, crop_y, crop_w, crop_h;
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u32 alpha;
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};
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/* LTDC main registers */
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#define LTDC_IDR 0x00 /* IDentification */
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#define LTDC_LCR 0x04 /* Layer Count */
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#define LTDC_SSCR 0x08 /* Synchronization Size Configuration */
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#define LTDC_BPCR 0x0C /* Back Porch Configuration */
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#define LTDC_AWCR 0x10 /* Active Width Configuration */
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#define LTDC_TWCR 0x14 /* Total Width Configuration */
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#define LTDC_GCR 0x18 /* Global Control */
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#define LTDC_GC1R 0x1C /* Global Configuration 1 */
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#define LTDC_GC2R 0x20 /* Global Configuration 2 */
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#define LTDC_SRCR 0x24 /* Shadow Reload Configuration */
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#define LTDC_GACR 0x28 /* GAmma Correction */
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#define LTDC_BCCR 0x2C /* Background Color Configuration */
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#define LTDC_IER 0x34 /* Interrupt Enable */
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#define LTDC_ISR 0x38 /* Interrupt Status */
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#define LTDC_ICR 0x3C /* Interrupt Clear */
|
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#define LTDC_LIPCR 0x40 /* Line Interrupt Position Conf. */
|
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#define LTDC_CPSR 0x44 /* Current Position Status */
|
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#define LTDC_CDSR 0x48 /* Current Display Status */
|
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|
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/* LTDC layer 1 registers */
|
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#define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
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#define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
|
||||
#define LTDC_L1CR 0x84 /* L1 Control */
|
||||
#define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
|
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#define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
|
||||
#define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
|
||||
#define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
|
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#define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
|
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#define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
|
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#define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
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#define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
|
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#define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
|
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#define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
|
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#define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
|
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#define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
|
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#define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
|
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#define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
|
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#define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
|
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#define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
|
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|
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/* Bit definitions */
|
||||
#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
|
||||
#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
|
||||
|
||||
#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
|
||||
#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
|
||||
|
||||
#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
|
||||
#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
|
||||
|
||||
#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
|
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#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
|
||||
|
||||
#define GCR_LTDCEN BIT(0) /* LTDC ENable */
|
||||
#define GCR_DEN BIT(16) /* Dither ENable */
|
||||
#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
|
||||
#define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
|
||||
#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
|
||||
#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
|
||||
|
||||
#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
|
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#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
|
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#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
|
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#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
|
||||
#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
|
||||
#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
|
||||
#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
|
||||
#define GC1R_BCP BIT(22) /* Background Colour Programmable */
|
||||
#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
|
||||
#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
|
||||
#define GC1R_TP BIT(25) /* Timing Programmable */
|
||||
#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
|
||||
#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
|
||||
#define GC1R_DWP BIT(28) /* Dither Width Programmable */
|
||||
#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
|
||||
#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
|
||||
|
||||
#define GC2R_EDCA BIT(0) /* External Display Control Ability */
|
||||
#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
|
||||
#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
|
||||
#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
|
||||
#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
|
||||
#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
|
||||
|
||||
#define SRCR_IMR BIT(0) /* IMmediate Reload */
|
||||
#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
|
||||
|
||||
#define LXCR_LEN BIT(0) /* Layer ENable */
|
||||
#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
|
||||
#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
|
||||
|
||||
#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
|
||||
#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
|
||||
|
||||
#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
|
||||
#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
|
||||
|
||||
#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
|
||||
|
||||
#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
|
||||
|
||||
#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
|
||||
#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
|
||||
|
||||
#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
|
||||
#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
|
||||
|
||||
#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
|
||||
|
||||
#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
|
||||
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
|
||||
|
||||
enum stm32_ltdc_pix_fmt {
|
||||
PF_ARGB8888 = 0,
|
||||
PF_RGB888,
|
||||
PF_RGB565,
|
||||
PF_ARGB1555,
|
||||
PF_ARGB4444,
|
||||
PF_L8,
|
||||
PF_AL44,
|
||||
PF_AL88
|
||||
};
|
||||
|
||||
/* TODO add more color format support */
|
||||
static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
|
||||
{
|
||||
enum stm32_ltdc_pix_fmt pf;
|
||||
|
||||
switch (l2bpp) {
|
||||
case VIDEO_BPP16:
|
||||
pf = PF_RGB565;
|
||||
break;
|
||||
|
||||
case VIDEO_BPP1:
|
||||
case VIDEO_BPP2:
|
||||
case VIDEO_BPP4:
|
||||
case VIDEO_BPP8:
|
||||
case VIDEO_BPP32:
|
||||
default:
|
||||
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
|
||||
__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
|
||||
pf = PF_RGB565;
|
||||
break;
|
||||
}
|
||||
|
||||
debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
|
||||
|
||||
return (u32)pf;
|
||||
}
|
||||
|
||||
static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
|
||||
{
|
||||
/* Reload configuration immediately & enable LTDC */
|
||||
setbits_le32(priv->regs + LTDC_SRCR, SRCR_IMR);
|
||||
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
|
||||
}
|
||||
|
||||
static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
|
||||
{
|
||||
void __iomem *regs = priv->regs;
|
||||
struct display_timing *timing = &priv->timing;
|
||||
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
|
||||
u32 total_w, total_h;
|
||||
u32 val;
|
||||
|
||||
/* Convert video timings to ltdc timings */
|
||||
hsync = timing->hsync_len.typ - 1;
|
||||
vsync = timing->vsync_len.typ - 1;
|
||||
acc_hbp = hsync + timing->hback_porch.typ;
|
||||
acc_vbp = vsync + timing->vback_porch.typ;
|
||||
acc_act_w = acc_hbp + timing->hactive.typ;
|
||||
acc_act_h = acc_vbp + timing->vactive.typ;
|
||||
total_w = acc_act_w + timing->hfront_porch.typ;
|
||||
total_h = acc_act_h + timing->vfront_porch.typ;
|
||||
|
||||
/* Synchronization sizes */
|
||||
val = (hsync << 16) | vsync;
|
||||
clrsetbits_le32(regs + LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
|
||||
|
||||
/* Accumulated back porch */
|
||||
val = (acc_hbp << 16) | acc_vbp;
|
||||
clrsetbits_le32(regs + LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
|
||||
|
||||
/* Accumulated active width */
|
||||
val = (acc_act_w << 16) | acc_act_h;
|
||||
clrsetbits_le32(regs + LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
|
||||
|
||||
/* Total width & height */
|
||||
val = (total_w << 16) | total_h;
|
||||
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
|
||||
|
||||
/* Signal polarities */
|
||||
val = 0;
|
||||
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
|
||||
if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
|
||||
val |= GCR_HSPOL;
|
||||
if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
|
||||
val |= GCR_VSPOL;
|
||||
if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
|
||||
val |= GCR_DEPOL;
|
||||
if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
|
||||
val |= GCR_PCPOL;
|
||||
clrsetbits_le32(regs + LTDC_GCR,
|
||||
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
|
||||
|
||||
/* Overall background color */
|
||||
writel(priv->bg_col_argb, priv->regs + LTDC_BCCR);
|
||||
}
|
||||
|
||||
static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
|
||||
{
|
||||
void __iomem *regs = priv->regs;
|
||||
u32 x0, x1, y0, y1;
|
||||
u32 pitch_in_bytes;
|
||||
u32 line_length;
|
||||
u32 bus_width;
|
||||
u32 val, tmp, bpp;
|
||||
|
||||
x0 = priv->crop_x;
|
||||
x1 = priv->crop_x + priv->crop_w - 1;
|
||||
y0 = priv->crop_y;
|
||||
y1 = priv->crop_y + priv->crop_h - 1;
|
||||
|
||||
/* Horizontal start and stop position */
|
||||
tmp = (readl(regs + LTDC_BPCR) & BPCR_AHBP) >> 16;
|
||||
val = ((x1 + 1 + tmp) << 16) + (x0 + 1 + tmp);
|
||||
clrsetbits_le32(regs + LTDC_L1WHPCR, LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS,
|
||||
val);
|
||||
|
||||
/* Vertical start & stop position */
|
||||
tmp = readl(regs + LTDC_BPCR) & BPCR_AVBP;
|
||||
val = ((y1 + 1 + tmp) << 16) + (y0 + 1 + tmp);
|
||||
clrsetbits_le32(regs + LTDC_L1WVPCR, LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS,
|
||||
val);
|
||||
|
||||
/* Layer background color */
|
||||
writel(priv->bg_col_argb, regs + LTDC_L1DCCR);
|
||||
|
||||
/* Color frame buffer pitch in bytes & line length */
|
||||
bpp = VNBITS(priv->l2bpp);
|
||||
pitch_in_bytes = priv->crop_w * (bpp >> 3);
|
||||
bus_width = 8 << ((readl(regs + LTDC_GC2R) & GC2R_BW) >> 4);
|
||||
line_length = ((bpp >> 3) * priv->crop_w) + (bus_width >> 3) - 1;
|
||||
val = (pitch_in_bytes << 16) | line_length;
|
||||
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
|
||||
|
||||
/* Pixel format */
|
||||
val = stm32_ltdc_get_pixel_format(priv->l2bpp);
|
||||
clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
|
||||
|
||||
/* Constant alpha value */
|
||||
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
|
||||
|
||||
/* Blending factors */
|
||||
clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
|
||||
BF1_PAXCA | BF2_1PAXCA);
|
||||
|
||||
/* Frame buffer line number */
|
||||
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
|
||||
|
||||
/* Frame buffer address */
|
||||
writel(fb_addr, regs + LTDC_L1CFBAR);
|
||||
|
||||
/* Enable layer 1 */
|
||||
setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
|
||||
}
|
||||
|
||||
static int stm32_ltdc_probe(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
||||
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
||||
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
|
||||
struct udevice *panel;
|
||||
struct clk pclk, pxclk;
|
||||
int ret;
|
||||
|
||||
priv->regs = (void *)dev_read_addr(dev);
|
||||
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
|
||||
debug("%s: ltdc dt register address error\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = uclass_first_device(UCLASS_PANEL, &panel);
|
||||
if (ret) {
|
||||
debug("%s: panel device error %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = panel_enable_backlight(panel);
|
||||
if (ret) {
|
||||
debug("%s: panel %s enable backlight error %d\n",
|
||||
__func__, panel->name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
|
||||
0, &priv->timing);
|
||||
if (ret) {
|
||||
debug("%s: decode display timing error %d\n", __func__, ret);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_get_by_name(dev, "pclk", &pclk);
|
||||
if (ret) {
|
||||
debug("%s: peripheral clock get error %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_enable(&pclk);
|
||||
if (ret) {
|
||||
debug("%s: peripheral clock enable error %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Verify pixel clock value if any & inform user accordingly */
|
||||
ret = clk_get_by_name(dev, "pxclk", &pxclk);
|
||||
if (!ret) {
|
||||
if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
|
||||
printf("Warning: please adjust ltdc pixel clock\n");
|
||||
}
|
||||
|
||||
/* TODO Below parameters are hard-coded for the moment... */
|
||||
priv->l2bpp = VIDEO_BPP16;
|
||||
priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
|
||||
priv->crop_x = 0;
|
||||
priv->crop_y = 0;
|
||||
priv->crop_w = priv->timing.hactive.typ;
|
||||
priv->crop_h = priv->timing.vactive.typ;
|
||||
priv->alpha = 0xFF;
|
||||
|
||||
debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
|
||||
priv->timing.hactive.typ, priv->timing.vactive.typ,
|
||||
VNBITS(priv->l2bpp), uc_plat->base);
|
||||
debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
|
||||
priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
|
||||
priv->bg_col_argb, priv->alpha);
|
||||
|
||||
/* Configure & start LTDC */
|
||||
stm32_ltdc_set_mode(priv);
|
||||
stm32_ltdc_set_layer1(priv, uc_plat->base);
|
||||
stm32_ltdc_enable(priv);
|
||||
|
||||
uc_priv->xsize = priv->timing.hactive.typ;
|
||||
uc_priv->ysize = priv->timing.vactive.typ;
|
||||
uc_priv->bpix = priv->l2bpp;
|
||||
|
||||
video_set_flush_dcache(dev, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_ltdc_bind(struct udevice *dev)
|
||||
{
|
||||
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
||||
|
||||
uc_plat->size = CONFIG_VIDEO_STM32_MAX_XRES *
|
||||
CONFIG_VIDEO_STM32_MAX_YRES *
|
||||
(CONFIG_VIDEO_STM32_MAX_BPP >> 3);
|
||||
debug("%s: frame buffer max size %d bytes\n", __func__, uc_plat->size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id stm32_ltdc_ids[] = {
|
||||
{ .compatible = "st,stm32-ltdc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stm32_ltdc) = {
|
||||
.name = "stm32_ltdc",
|
||||
.id = UCLASS_VIDEO,
|
||||
.of_match = stm32_ltdc_ids,
|
||||
.probe = stm32_ltdc_probe,
|
||||
.bind = stm32_ltdc_bind,
|
||||
.priv_auto_alloc_size = sizeof(struct stm32_ltdc_priv),
|
||||
};
|
||||
|
|
@ -199,7 +199,9 @@ static int video_post_probe(struct udevice *dev)
|
|||
#else
|
||||
priv->colour_bg = 0xffffff;
|
||||
#endif
|
||||
video_clear(dev);
|
||||
|
||||
if (!CONFIG_IS_ENABLED(NO_FB_CLEAR))
|
||||
video_clear(dev);
|
||||
|
||||
/*
|
||||
* Create a text console device. For now we always do this, although
|
||||
|
|
|
|||
Loading…
Reference in a new issue