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ARM926EJS: Fix cache.c to comply with checkpatch.pl

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Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
This commit is contained in:
Marek Vasut 2012-04-06 03:25:07 +00:00 committed by Albert ARIBAUD
parent c6201553ba
commit 2694bb9bcc
1 changed files with 8 additions and 9 deletions
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17
arch/arm/cpu/arm926ejs/cache.c
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@ -30,7 +30,7 @@
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
}
void flush_dcache_all(void)
@ -40,7 +40,7 @@ void flush_dcache_all(void)
"mrc p15, 0, r15, c7, c14, 3\n"
"bne 0b\n"
"mcr p15, 0, %0, c7, c10, 4\n"
::"r"(0):"memory"
: : "r"(0) : "memory"
);
}
@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
}
void flush_cache(unsigned long start, unsigned long size)
@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size)
/*
* Stub implementations for l2 cache operations
*/
void __l2_cache_disable(void)
{
}
void __l2_cache_disable(void) {}
void l2_cache_disable(void)
__attribute__((weak, alias("__l2_cache_disable")));
__attribute__((weak, alias("__l2_cache_disable")));